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szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/wr_status_flags_sshft.vhd | 19 | 23,122 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_block
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`protect end_protected
| bsd-2-clause | 2b3756197802cdd73b5721a3290e457a | 0.942176 | 1.851093 | false | false | false | false |
wltr/common-vhdl | memory/two_port_ram/src/rtl/two_port_ram.vhd | 1 | 2,994 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Two port block RAM.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity two_port_ram is
generic (
-- Memory depth
depth_g : positive := 32;
-- Data bit width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Write port
wr_addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
wr_en_i : in std_ulogic;
wr_data_i : in std_ulogic_vector(width_g - 1 downto 0);
wr_done_o : out std_ulogic;
-- Read port
rd_addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
rd_en_i : in std_ulogic;
rd_data_o : out std_ulogic_vector(width_g - 1 downto 0);
rd_data_en_o : out std_ulogic);
end entity two_port_ram;
architecture rtl of two_port_ram is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
type mem_t is array (0 to depth_g - 1) of std_ulogic_vector(wr_data_i'range);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal mem : mem_t;
signal rd_data : std_ulogic_vector(rd_data_o'range);
signal rd_data_en : std_ulogic;
signal wr_done : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
rd_data_o <= rd_data;
rd_data_en_o <= rd_data_en;
wr_done_o <= wr_done;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
rd_data <= (others => '0');
rd_data_en <= '0';
wr_done <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
rd_data_en <= '0';
wr_done <= '0';
if rst_syn_i = '1' then
reset;
else
if wr_en_i = '1' then
mem(to_integer(unsigned(wr_addr_i))) <= wr_data_i;
wr_done <= '1';
end if;
if rd_en_i = '1' then
rd_data <= mem(to_integer(unsigned(rd_addr_i)));
rd_data_en <= '1';
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 3b0d47ea234d43949050b2e3a81128bb | 0.415498 | 3.965563 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_f22a7e3f4b613ff0.vhd | 1 | 6,983 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_f22a7e3f4b613ff0.vhd when simulating
-- the core, fr_cmplr_v6_3_f22a7e3f4b613ff0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_f22a7e3f4b613ff0 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_f22a7e3f4b613ff0;
ARCHITECTURE fr_cmplr_v6_3_f22a7e3f4b613ff0_a OF fr_cmplr_v6_3_f22a7e3f4b613ff0 IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_f22a7e3f4b613ff0
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_f22a7e3f4b613ff0 USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "44",
c_accum_path_widths => "44",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_f22a7e3f4b613ff0.mif",
c_coef_file_lines => 240,
c_coef_mem_packing => 0,
c_coef_memtype => 1,
c_coef_path_sign => "0",
c_coef_path_src => "0",
c_coef_path_widths => "16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "1",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_f22a7e3f4b613ff0",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 0,
c_data_memtype => 1,
c_data_path_sign => "0",
c_data_path_src => "0",
c_data_path_widths => "25",
c_data_width => 25,
c_datapath_memtype => 2,
c_decim_rate => 10,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 5600000,
c_interp_rate => 1,
c_ipbuff_memtype => 0,
c_latency => 31,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 32,
c_m_data_tuser_width => 2,
c_mem_arrangement => 0,
c_num_channels => 4,
c_num_filts => 1,
c_num_madds => 1,
c_num_reload_slots => 1,
c_num_taps => 240,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "26",
c_output_rate => 56000000,
c_output_width => 26,
c_oversampling_rate => 24,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 32,
c_s_data_tuser_width => 2,
c_symmetry => 0,
c_xdevicefamily => "virtex6",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_f22a7e3f4b613ff0
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_f22a7e3f4b613ff0_a;
| lgpl-3.0 | b5b4dc7ff57b5d7e47c0a4cf03500cd7 | 0.553201 | 3.465509 | false | false | false | false |
wltr/common-vhdl | communication/uart/src/rtl/uart_rx.vhd | 1 | 5,908 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Receive asynchronous serial data.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.lfsr_pkg.all;
entity uart_rx is
generic (
-- Data bit width
data_width_g : positive := 8;
-- Parity bit: 0 = None, 1 = Odd, 2 = Even
parity_g : natural range 0 to 2 := 0;
-- Number of stop bits
stop_bits_g : positive range 1 to 2 := 1;
-- Number of clock cycles per bit
num_ticks_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Reception line
rx_i : in std_ulogic;
-- Interface
data_o : out std_ulogic_vector(data_width_g - 1 downto 0);
data_en_o : out std_ulogic;
error_o : out std_ulogic);
end entity uart_rx;
architecture rtl of uart_rx is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- Transmission bit length
constant rx_len_c : natural := 1 + data_width_g + stop_bits_g + natural(ceil(real(parity_g / 2)));
-- LFSR counter bit length
constant len_c : natural := lfsr_length(rx_len_c);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : std_ulogic_vector(len_c - 1 downto 0);
signal data : std_ulogic_vector(rx_len_c - 1 downto 0);
signal data_en : std_ulogic;
signal parity_error : std_ulogic;
signal stop_error : std_ulogic;
signal busy : std_ulogic;
signal done : std_ulogic;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal parity_init : std_ulogic;
signal parity_bit : std_ulogic;
signal parity : std_ulogic_vector(data_o'range);
signal data_bits : std_ulogic_vector(data_o'range);
signal rx_fedge : std_ulogic;
signal bit_strobe : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data_bits;
data_en_o <= data_en;
error_o <= parity_error or stop_error;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Extract data bits from received packet
data_bits <= data(data_width_g downto 1);
-- Set parity bit's initial value
parity_init <= '1' when parity_g = 1 else '0';
-- Compute parity bit
parity(0) <= data_bits(0) xor parity_init;
parity_gen : for i in 1 to parity'high generate
parity(i) <= data_bits(i) xor parity(i - 1);
end generate parity_gen;
parity_bit <= parity(parity'high) xor data(data_width_g + 1);
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Detect falling edge on rx_i
rx_edge_inst : entity work.edge_detector
generic map (
init_value_g => '1',
edge_type_g => 1,
hold_flag_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
ack_i => '0',
sig_i => rx_i,
edge_o => rx_fedge);
bit_clock_recovery_inst : entity work.bit_clock_recovery
generic map (
num_cycles_g => num_ticks_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
sig_i => rx_i,
bit_clk_o => bit_strobe);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= seed_c;
data <= (others => '0');
data_en <= '0';
parity_error <= '0';
stop_error <= '0';
busy <= '0';
done <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
data_en <= '0';
parity_error <= '0';
stop_error <= '0';
done <= '0';
if rst_syn_i = '1' then
reset;
else
if busy = '0' and rx_fedge = '1' then
busy <= '1';
elsif busy = '1' and bit_strobe = '1' then
data <= rx_i & data(data'high downto data'low + 1);
if count = lfsr_shift(seed_c, rx_len_c - 1) then
count <= seed_c;
busy <= '0';
done <= '1';
else
count <= lfsr_shift(count);
end if;
end if;
stop_error <= done and not data(data'high);
if parity_g = 0 then
parity_error <= '0';
data_en <= done and data(data'high);
else
parity_error <= done and parity_bit;
data_en <= done and data(data'high) and not parity_bit;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | de0bfda4d3dd02db0a0c39da305af6a3 | 0.429418 | 4.097087 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/addsb_11_0_26986301a9f671cd.vhd | 1 | 4,568 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_26986301a9f671cd.vhd when simulating
-- the core, addsb_11_0_26986301a9f671cd. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_26986301a9f671cd IS
PORT (
a : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
END addsb_11_0_26986301a9f671cd;
ARCHITECTURE addsb_11_0_26986301a9f671cd_a OF addsb_11_0_26986301a9f671cd IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_26986301a9f671cd
PORT (
a : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(24 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(24 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_26986301a9f671cd USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 25,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "0000000000000000000000000",
c_b_width => 25,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 25,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_26986301a9f671cd
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_26986301a9f671cd_a;
| lgpl-3.0 | 73cfb4867c99958461291965c497320f | 0.53634 | 4.141432 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/cntr_11_0_3166d4cc5b09c744.vhd | 1 | 4,453 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cntr_11_0_3166d4cc5b09c744.vhd when simulating
-- the core, cntr_11_0_3166d4cc5b09c744. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cntr_11_0_3166d4cc5b09c744 IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END cntr_11_0_3166d4cc5b09c744;
ARCHITECTURE cntr_11_0_3166d4cc5b09c744_a OF cntr_11_0_3166d4cc5b09c744 IS
-- synthesis translate_off
COMPONENT wrapped_cntr_11_0_3166d4cc5b09c744
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sinit : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cntr_11_0_3166d4cc5b09c744 USE ENTITY XilinxCoreLib.c_counter_binary_v11_0(behavioral)
GENERIC MAP (
c_ainit_val => "0",
c_ce_overrides_sync => 0,
c_count_by => "1",
c_count_mode => 0,
c_count_to => "1",
c_fb_latency => 0,
c_has_ce => 1,
c_has_load => 0,
c_has_sclr => 0,
c_has_sinit => 1,
c_has_sset => 0,
c_has_thresh0 => 0,
c_implementation => 0,
c_latency => 1,
c_load_low => 0,
c_restrict_count => 0,
c_sclr_overrides_sset => 1,
c_sinit_val => "0",
c_thresh0_value => "1",
c_verbosity => 0,
c_width => 2,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cntr_11_0_3166d4cc5b09c744
PORT MAP (
clk => clk,
ce => ce,
sinit => sinit,
q => q
);
-- synthesis translate_on
END cntr_11_0_3166d4cc5b09c744_a;
| lgpl-3.0 | 29afbc1468a05c1d12dfcf141955952e | 0.534247 | 4.150047 | false | false | false | false |
wltr/common-vhdl | generic/mem_data_triplicator/src/rtl/mem_data_triplicator_wr_only.vhd | 1 | 2,799 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Triplicate data on write.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity mem_data_triplicator_wr_only is
generic (
-- Memory depth
depth_g : positive := 1048576;
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g / 3)))) - 1 downto 0);
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Memory interface
mem_addr_o : out std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
mem_wr_en_o : out std_ulogic;
mem_data_o : out std_ulogic_vector(width_g - 1 downto 0);
mem_busy_i : in std_ulogic;
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_wr_only;
architecture rtl of mem_data_triplicator_wr_only is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal wr_busy : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= wr_busy or mem_busy_i;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Calculate addresses
mem_data_triplicator_addr_inst : entity work.mem_data_triplicator_addr
generic map (
depth_g => depth_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => addr_i,
rd_en_i => '0',
wr_en_i => wr_en_i,
mem_addr_o => mem_addr_o,
mem_done_i => mem_done_i);
-- Triplicate data on write
mem_data_triplicator_wr_inst : entity work.mem_data_triplicator_wr
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => wr_en_i,
data_i => data_i,
busy_o => wr_busy,
done_o => done_o,
mem_wr_en_o => mem_wr_en_o,
mem_data_o => mem_data_o,
mem_done_i => mem_done_i);
end architecture rtl;
| lgpl-2.1 | cc78b96f68727e3937b7d36044f60674 | 0.444444 | 3.644531 | false | false | false | false |
wltr/common-vhdl | generic/external_inputs/src/rtl/external_inputs.vhd | 1 | 2,498 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Synchronize and filter external inputs.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity external_inputs is
generic (
-- Initial value of input signals
init_value_g : std_ulogic := '0';
-- Number of inputs
num_inputs_g : positive := 1;
-- Add glitch filter
filter_g : boolean := true);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Input signals
sig_i : in std_ulogic_vector(num_inputs_g - 1 downto 0);
-- Synchronized and filtered output signals
sig_o : out std_ulogic_vector(num_inputs_g - 1 downto 0));
end entity external_inputs;
architecture rtl of external_inputs is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal sig : std_ulogic_vector(sig_i'range);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
inst_gen : for i in sig_i'range generate
-- Synchronize the inputs into the local clock domain
delay_inst : entity work.delay
generic map (
init_value_g => init_value_g,
num_delay_g => 2)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
sig_i => sig_i(i),
dlyd_o => sig(i));
-- Direct output without glitch filter
no_filter_gen : if filter_g = false generate
sig_o(i) <= sig(i);
end generate no_filter_gen;
-- Filter glitches
filter_gen : if filter_g = true generate
glitch_filter_inst : entity work.glitch_filter
generic map (
init_value_g => init_value_g,
num_delay_g => 1)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
sig_i => sig(i),
sig_o => sig_o(i));
end generate filter_gen;
end generate inst_gen;
end architecture rtl;
| lgpl-2.1 | 2ea25ab51f669678b18a8df1cffeab65 | 0.455965 | 4.128926 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/cc_cmplr_v3_0_e58a4eb9f6488d2d.vhd | 1 | 6,148 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_e58a4eb9f6488d2d.vhd when simulating
-- the core, cc_cmplr_v3_0_e58a4eb9f6488d2d. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_e58a4eb9f6488d2d IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_e58a4eb9f6488d2d;
ARCHITECTURE cc_cmplr_v3_0_e58a4eb9f6488d2d_a OF cc_cmplr_v3_0_e58a4eb9f6488d2d IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_e58a4eb9f6488d2d
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_e58a4eb9f6488d2d USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 61,
c_c2 => 61,
c_c3 => 61,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2240,
c_component_name => "cc_cmplr_v3_0_e58a4eb9f6488d2d",
c_diff_delay => 2,
c_family => "artix7",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 61,
c_i2 => 61,
c_i3 => 61,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 2500,
c_min_rate => 2500,
c_num_channels => 4,
c_num_stages => 3,
c_output_width => 61,
c_rate => 2500,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_e58a4eb9f6488d2d
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_e58a4eb9f6488d2d_a;
| lgpl-3.0 | 73d63a608ab608288f9d9e11bab2b9f9 | 0.55758 | 3.591121 | false | false | false | false |
wltr/common-vhdl | generic/mem_data_triplicator/src/rtl/mem_data_triplicator_rd_only.vhd | 1 | 3,051 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Perform majority voting on read.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity mem_data_triplicator_rd_only is
generic (
-- Memory depth
depth_g : positive := 1048576;
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g / 3)))) - 1 downto 0);
rd_en_i : in std_ulogic;
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
voted_o : out std_ulogic;
-- Memory interface
mem_addr_o : out std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
mem_rd_en_o : out std_ulogic;
mem_data_i : in std_ulogic_vector(width_g - 1 downto 0);
mem_data_en_i : in std_ulogic;
mem_busy_i : in std_ulogic;
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_rd_only;
architecture rtl of mem_data_triplicator_rd_only is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal rd_busy : std_ulogic;
signal rd_data_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= rd_busy or mem_busy_i;
done_o <= rd_data_en;
data_en_o <= rd_data_en;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Calculate addresses
mem_data_triplicator_addr_inst : entity work.mem_data_triplicator_addr
generic map (
depth_g => depth_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => addr_i,
rd_en_i => rd_en_i,
wr_en_i => '0',
mem_addr_o => mem_addr_o,
mem_done_i => mem_done_i);
-- Perform majority voting on read
mem_data_triplicator_rd_inst : entity work.mem_data_triplicator_rd
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rd_en_i => rd_en_i,
data_o => data_o,
data_en_o => rd_data_en,
busy_o => rd_busy,
voted_o => voted_o,
mem_rd_en_o => mem_rd_en_o,
mem_data_i => mem_data_i,
mem_data_en_i => mem_data_en_i);
end architecture rtl;
| lgpl-2.1 | d7ced03e17986655cde565e6d10a6a80 | 0.454277 | 3.543554 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/testbench/text_mode_pkg_tb.vhd | 1 | 1,521 | use work.text_mode_pkg.all;
use work.tbu_text_out_pkg.all;
use work.colors_pkg.all;
use work.resource_handles_helper_pkg.all;
entity text_mode_pkg_tb is
end;
architecture testbench of text_mode_pkg_tb is
constant HELLO_WORLD_STRING: text_mode_string_type := (
x => 0,
y => 0,
text => "Hello world!!! ",
visible => true
);
constant SCORE_STRING: text_mode_string_type := (
x => 0,
y => 10,
text => "SCORE: 0 ",
visible => true
);
constant STRINGS: text_mode_strings_type := (
HELLO_WORLD_STRING,
SCORE_STRING
);
begin
process begin
for y in 0 to 11 loop
for x in 0 to 79 loop
--put( to_string(character_at_x_y(x,y)) );
print( to_string(character_at_x_y(x, y, strings)), newline => false );
end loop;
print("");
end loop;
for y in 0 to 11 loop
for x in 0 to 79 loop
--put( to_string(character_at_x_y(x,y)) );
if text_pixel_at_x_y(x, y, strings) then
print( "#", newline => false );
else
print( " ", newline => false );
end if;
end loop;
print("");
end loop;
put(to_string( game_strings_count ));
std.env.finish;
end process;
end; | unlicense | 91d1f3f9db04c4a2f29d96f05d22fc04 | 0.454306 | 3.831234 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter.vhd | 1 | 4,956 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Calculate the coefficients and pass them on the each channel.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.ads1281_filter_pkg.all;
entity ads1281_filter is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Synchronization strobe
strb_ms_i : in std_ulogic;
-- Sample strobe
strb_sample_o : out std_ulogic;
-- ADC bit streams
adc_m0_i : in std_ulogic_vector(ads1281_filter_num_channels_c - 1 downto 0);
adc_m1_i : in std_ulogic_vector(ads1281_filter_num_channels_c - 1 downto 0);
-- Filter results
result_o : out ads1281_filter_result_t;
result_en_o : out std_ulogic_vector(ads1281_filter_num_channels_c - 1 downto 0));
end entity ads1281_filter;
architecture rtl of ads1281_filter is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal m1_changed : std_ulogic;
signal sample_strb : std_ulogic;
signal coeff1 : unsigned(23 downto 0);
signal coeff1_en : std_ulogic;
signal coeff1_done : std_ulogic;
signal coeff1_start : std_ulogic;
signal coeff2 : unsigned(23 downto 0);
signal coeff2_en : std_ulogic;
signal coeff2_done : std_ulogic;
signal coeff2_start : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
strb_sample_o <= sample_strb;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Check for changes on any M1 bit stream
ads1281_filter_sampling_inst : entity work.ads1281_filter_sampling
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
adc_m1_i => adc_m1_i,
changed_o => m1_changed);
-- Create sampling strobe from incoming M1 (has typically more edges) bit stream
bit_clock_recovery_inst : entity work.bit_clock_recovery
generic map (
num_cycles_g => 40,
offset_g => -3,
edge_type_g => 0)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => '1',
sig_i => m1_changed,
bit_clk_o => sample_strb);
-- Alternate between the two interleaved filters
ads1281_filter_select_inst : entity work.ads1281_filter_select
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
strb_ms_i => strb_ms_i,
coeff1_start_o => coeff1_start,
coeff2_start_o => coeff2_start);
-- Calculating the filter coefficients for the 1st interleaved filter
ads1281_filter_coefficients_inst_0 : entity work.ads1281_filter_coefficients
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
start_i => coeff1_start,
next_i => sample_strb,
coeff_o => coeff1,
coeff_en_o => coeff1_en,
done_o => coeff1_done);
-- Calculating the filter coefficients for the 2nd interleaved filter
ads1281_filter_coefficients_inst_1 : entity work.ads1281_filter_coefficients
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
start_i => coeff2_start,
next_i => sample_strb,
coeff_o => coeff2,
coeff_en_o => coeff2_en,
done_o => coeff2_done);
-- Generate filter channels
ads1281_filter_channel_gen : for i in 0 to ads1281_filter_num_channels_c - 1 generate
ads1281_filter_channel_inst : entity work.ads1281_filter_channel
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
sample_i => sample_strb,
adc_m0_i => adc_m0_i(i),
adc_m1_i => adc_m1_i(i),
coeff1_i => coeff1,
coeff1_en_i => coeff1_en,
coeff1_done_i => coeff1_done,
coeff2_i => coeff2,
coeff2_en_i => coeff2_en,
coeff2_done_i => coeff2_done,
result_o => result_o(i),
result_en_o => result_en_o(i));
end generate ads1281_filter_channel_gen;
end architecture rtl;
| lgpl-2.1 | b98d5958241bb104ba8bdb3e1353bbac | 0.497175 | 3.630769 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_average_calculator.vhd | 1 | 5,978 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Calculate average of 10 ADS1281 filter outputs.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_average_calculator is
port (
clk_i : in std_ulogic;
rst_n_i : in std_ulogic;
stb_50hz_i : in std_ulogic;
data_i : in signed(23 downto 0);
en_i : in std_ulogic;
avg_o : out signed(23 downto 0);
en_o : out std_ulogic);
end entity ads1281_average_calculator;
architecture rtl of ads1281_average_calculator is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR's initial value
constant seed_c : std_ulogic_vector(3 downto 0) := "0001";
-- LFSR's value after 9 shifts
constant data_c : std_ulogic_vector(3 downto 0) := "1011";
-- LFSR's value after 2 shifts
constant padding_c : std_ulogic_vector(3 downto 0) := "0100";
type state_t is (ADD, ADD_MIN, ADD_MAX, DONE);
type reg_t is record
state : state_t;
lfsr : std_ulogic_vector(3 downto 0);
sum : signed(27 downto 0);
min : signed(23 downto 0);
max : signed(23 downto 0);
end record reg_t;
constant init_c : reg_t := (
state => ADD,
lfsr => seed_c,
sum => (others => '0'),
min => (others => '0'),
max => (others => '0'));
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
signal lfsr_in : std_ulogic;
signal add_in : signed(23 downto 0);
signal sum : signed(27 downto 0);
signal avg : signed(23 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
avg_o <= avg when reg.state = DONE else (others => '0');
en_o <= '1' when reg.state = DONE else '0';
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- LFSR feedback polynomial: x^4 + x^3 + 1 (period: 15)
lfsr_in <= reg.lfsr(reg.lfsr'high) xor reg.lfsr(reg.lfsr'high - 1);
-- Shifting sum to the right by 4 bits, this equals a division by 16
avg <= reg.sum(reg.sum'high downto reg.sum'length - avg'length);
-- Adder
sum <= reg.sum + add_in;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
process (clk_i, rst_n_i) is
begin -- process
if rst_n_i = '0' then
reg <= init_c;
elsif rising_edge(clk_i) then
reg <= next_reg;
end if;
end process;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
process(reg, lfsr_in, sum, stb_50hz_i, data_i, en_i) is
begin -- process
-- Defaults
next_reg <= reg;
add_in <= (others => '0');
if stb_50hz_i = '1' then
-- Reset
next_reg <= init_c;
else
case reg.state is
when ADD =>
if en_i = '1' then
-- Add new data to the sum
add_in <= data_i;
next_reg.sum <= sum;
if reg.lfsr = seed_c then
-- First data is stored as minimum and maximum
next_reg.min <= data_i;
next_reg.max <= data_i;
else
if data_i < reg.min then
-- If new data is smaller than current minimum, it is stored as new minimum
next_reg.min <= data_i;
end if;
if data_i > reg.max then
-- If new data is greater than current maximum, it is stored as new maximum
next_reg.max <= data_i;
end if;
end if;
if reg.lfsr = data_c then
-- Continue with adding the minimum value to the sum
next_reg.state <= ADD_MIN;
next_reg.lfsr <= seed_c;
else
next_reg.lfsr <= reg.lfsr(reg.lfsr'high - 1 downto reg.lfsr'low) & lfsr_in;
end if;
end if;
when ADD_MIN =>
-- Add minimum to the sum
add_in <= reg.min;
next_reg.sum <= sum;
if reg.lfsr = padding_c then
-- Continue with adding the maximum value to the sum
next_reg.state <= ADD_MAX;
next_reg.lfsr <= seed_c;
else
next_reg.lfsr <= reg.lfsr(reg.lfsr'high - 1 downto reg.lfsr'low) & lfsr_in;
end if;
when ADD_MAX =>
-- Add maximum to the sum
add_in <= reg.max;
next_reg.sum <= sum;
if reg.lfsr = padding_c then
-- Reset
next_reg.state <= DONE;
else
next_reg.lfsr <= reg.lfsr(reg.lfsr'high - 1 downto reg.lfsr'low) & lfsr_in;
end if;
when DONE =>
-- Reset when done
next_reg <= init_c;
end case;
end if;
end process;
end architecture rtl;
| lgpl-2.1 | 9a722dfcaad902b4b21cdf516d6315fc | 0.40649 | 4.508296 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_decoder.vhd | 1 | 3,450 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Decode the ADS1281 bit streams M0 and M1 according to the equation from
-- the data sheet.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_filter_decoder is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Buffered ADC bit streams
adc_m0_i : in std_ulogic_vector(2 downto 0);
adc_m1_i : in std_ulogic_vector(2 downto 0);
-- Decoded data
data_o : out signed(6 downto 0));
end entity ads1281_filter_decoder;
architecture rtl of ads1281_filter_decoder is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
constant addr_len_c : natural := adc_m0_i'length + adc_m1_i'length;
type lut_t is array (0 to 2**addr_len_c - 1) of integer range -49 to 49;
-- Look-up table with pre-calculated values using the following equation:
-- Y[n] = 3*M0[n-2] - 6*M0[n-3] + 4*M0[n-4] + 9*(M1[n] - 2*M1[n-1] + M1[n-2])
constant lut : lut_t := (
1, -17, 37, 19, -17, -35, 19, 1, -5, -23, 31, 13, -23, -41, 13, -5, 13, -5,
49, 31, -5, -23, 31, 13, 7, -11, 43, 25, -11, -29, 25, 7, -7, -25, 29, 11,
-25, -43, 11, -7, -13, -31, 23, 5, -31, -49, 5, -13, 5, -13, 41, 23, -13,
-31, 23, 5, -1, -19, 35, 17, -19, -37, 17, -1);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal data : signed(6 downto 0);
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal addr : unsigned(addr_len_c - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Combine samples and previous sample values to an address
addr <= adc_m0_i(2) & adc_m0_i(1) & adc_m0_i(0) & adc_m1_i(2) & adc_m1_i(1) & adc_m1_i(0);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data <= to_signed(0, data'length);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Map combined address to pre-calculated output value
data <= to_signed(lut(to_integer(addr)), data'length);
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 66ad10ea5e9de946c7f2145d8ca7d9cb | 0.385507 | 4.116945 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/npc_ai_projectile.vhd | 1 | 2,801 | library ieee;
use ieee.std_logic_1164.all;
use work.graphics_types_pkg.all;
use work.game_state_pkg.all;
-- "Artifical intelligence" (for lack of a better name) for moving NPCs
-- (non-player characters, such as enemies) around the screen. The "projectile"
-- strategy consists in moving the NPC with a constant speed until it reaches
-- the limits
entity npc_ai_projectile is
port (
reset, clock: in std_logic;
-- time base pulse, NPC state gets updated when high (tipically once every 100 ms)
time_base: in std_logic;
-- true if NPC is active in the game and must be updated
enabled: in boolean;
-- starting point for the NPC
initial_position: in point_type;
-- start velocity for the NPC
initial_speed: in point_type;
-- limits for NPC movement
allowed_region: in rectangle_type;
-- NPC restarts from this point if it was disabled
assigned_position: in point_type;
-- calculated NPC position
npc_position: out point_type
);
end;
architecture rtl of npc_ai_projectile is
-- current NPC position
signal position: point_type;
-- current NPC speed
signal speed: point_type;
signal previous_enable: boolean;
begin
process (clock, reset, initial_position, initial_speed, time_base) is
variable new_position: point_type;
begin
if reset then
position <= initial_position;
speed <= initial_speed;
elsif rising_edge(clock) then
if time_base = '1' then
if enabled then
if previous_enable then
new_position := position + speed;
else
new_position := assigned_position;
end if;
-- make sure x position is within limits
if new_position.x <= allowed_region.left then
new_position.x := allowed_region.left;
elsif new_position.x >= allowed_region.right then
new_position.x := allowed_region.right;
end if;
-- make sure y position is within limits
if new_position.y <= allowed_region.top then
new_position.y := allowed_region.top;
elsif new_position.y >= allowed_region.bottom then
new_position.y := allowed_region.bottom;
end if;
position <= new_position;
end if;
previous_enable <= enabled;
end if;
end if;
end process;
npc_position <= position;
end; | unlicense | c56f46abd3cc219d98baf791f0c45176 | 0.550875 | 4.637417 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_position_calc/xwb_position_calc_core.vhd | 1 | 20,837 | ------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core Module for position calculation with de-cross, amplitude compensation
-- and delay tuning.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-07-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- Position Calc
use work.position_calc_core_pkg.all;
entity xwb_position_calc_core is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_rffe_version : string := "V2";
g_with_switching : natural := 0
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
-----------------------------
-- BPF Data
-----------------------------
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
bpf_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
pos_x_tbt_o : out std_logic_vector(25 downto 0);
pos_y_tbt_o : out std_logic_vector(25 downto 0);
pos_q_tbt_o : out std_logic_vector(25 downto 0);
pos_sum_tbt_o : out std_logic_vector(25 downto 0);
pos_tbt_valid_o : out std_logic;
pos_x_fofb_o : out std_logic_vector(25 downto 0);
pos_y_fofb_o : out std_logic_vector(25 downto 0);
pos_q_fofb_o : out std_logic_vector(25 downto 0);
pos_sum_fofb_o : out std_logic_vector(25 downto 0);
pos_fofb_valid_o : out std_logic;
pos_x_monit_o : out std_logic_vector(25 downto 0);
pos_y_monit_o : out std_logic_vector(25 downto 0);
pos_q_monit_o : out std_logic_vector(25 downto 0);
pos_sum_monit_o : out std_logic_vector(25 downto 0);
pos_monit_valid_o : out std_logic;
pos_x_monit_1_o : out std_logic_vector(25 downto 0);
pos_y_monit_1_o : out std_logic_vector(25 downto 0);
pos_q_monit_1_o : out std_logic_vector(25 downto 0);
pos_sum_monit_1_o : out std_logic_vector(25 downto 0);
pos_monit_1_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0);
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_11120000_o : out std_logic;
clk_ce_111200000_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic;
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(15 downto 0)
);
end xwb_position_calc_core;
architecture rtl of xwb_position_calc_core is
begin
cmp_wb_position_calc_core : wb_position_calc_core
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity,
g_rffe_version => g_rffe_version,
g_with_switching => g_with_switching
)
port map
(
rst_n_i => rst_n_i,
clk_i => clk_i,
fs_rst_n_i => fs_rst_n_i,
fs_rst2x_n_i => fs_rst2x_n_i,
fs_clk_i => fs_clk_i, -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i => fs_clk2x_i, -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i => adc_ch0_i,
adc_ch1_i => adc_ch1_i,
adc_ch2_i => adc_ch2_i,
adc_ch3_i => adc_ch3_i,
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o => adc_ch0_dbg_data_o,
adc_ch1_dbg_data_o => adc_ch1_dbg_data_o,
adc_ch2_dbg_data_o => adc_ch2_dbg_data_o,
adc_ch3_dbg_data_o => adc_ch3_dbg_data_o,
bpf_ch0_o => bpf_ch0_o,
bpf_ch1_o => bpf_ch1_o,
bpf_ch2_o => bpf_ch2_o,
bpf_ch3_o => bpf_ch3_o,
bpf_valid_o => bpf_valid_o,
mix_ch0_i_o => mix_ch0_i_o,
mix_ch0_q_o => mix_ch0_q_o,
mix_ch1_i_o => mix_ch1_i_o,
mix_ch1_q_o => mix_ch1_q_o,
mix_ch2_i_o => mix_ch2_i_o,
mix_ch2_q_o => mix_ch2_q_o,
mix_ch3_i_o => mix_ch3_i_o,
mix_ch3_q_o => mix_ch3_q_o,
mix_valid_o => mix_valid_o,
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o,
tbt_decim_valid_o => tbt_decim_valid_o,
tbt_amp_ch0_o => tbt_amp_ch0_o,
tbt_amp_ch1_o => tbt_amp_ch1_o,
tbt_amp_ch2_o => tbt_amp_ch2_o,
tbt_amp_ch3_o => tbt_amp_ch3_o,
tbt_amp_valid_o => tbt_amp_valid_o,
tbt_pha_ch0_o => tbt_pha_ch0_o,
tbt_pha_ch1_o => tbt_pha_ch1_o,
tbt_pha_ch2_o => tbt_pha_ch2_o,
tbt_pha_ch3_o => tbt_pha_ch3_o,
tbt_pha_valid_o => tbt_pha_valid_o,
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o,
fofb_decim_valid_o => fofb_decim_valid_o,
fofb_amp_ch0_o => fofb_amp_ch0_o,
fofb_amp_ch1_o => fofb_amp_ch1_o,
fofb_amp_ch2_o => fofb_amp_ch2_o,
fofb_amp_ch3_o => fofb_amp_ch3_o,
fofb_amp_valid_o => fofb_amp_valid_o,
fofb_pha_ch0_o => fofb_pha_ch0_o,
fofb_pha_ch1_o => fofb_pha_ch1_o,
fofb_pha_ch2_o => fofb_pha_ch2_o,
fofb_pha_ch3_o => fofb_pha_ch3_o,
fofb_pha_valid_o => fofb_pha_valid_o,
monit_amp_ch0_o => monit_amp_ch0_o,
monit_amp_ch1_o => monit_amp_ch1_o,
monit_amp_ch2_o => monit_amp_ch2_o,
monit_amp_ch3_o => monit_amp_ch3_o,
monit_amp_valid_o => monit_amp_valid_o,
pos_x_tbt_o => pos_x_tbt_o,
pos_y_tbt_o => pos_y_tbt_o,
pos_q_tbt_o => pos_q_tbt_o,
pos_sum_tbt_o => pos_sum_tbt_o,
pos_tbt_valid_o => pos_tbt_valid_o,
pos_x_fofb_o => pos_x_fofb_o,
pos_y_fofb_o => pos_y_fofb_o,
pos_q_fofb_o => pos_q_fofb_o,
pos_sum_fofb_o => pos_sum_fofb_o,
pos_fofb_valid_o => pos_fofb_valid_o,
pos_x_monit_o => pos_x_monit_o,
pos_y_monit_o => pos_y_monit_o,
pos_q_monit_o => pos_q_monit_o,
pos_sum_monit_o => pos_sum_monit_o,
pos_monit_valid_o => pos_monit_valid_o,
pos_x_monit_1_o => pos_x_monit_1_o,
pos_y_monit_1_o => pos_y_monit_1_o,
pos_q_monit_1_o => pos_q_monit_1_o,
pos_sum_monit_1_o => pos_sum_monit_1_o,
pos_monit_1_valid_o => pos_monit_1_valid_o,
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o => clk_swap_o,
flag1_o => flag1_o,
flag2_o => flag2_o,
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o,
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o => clk_ce_1_o,
clk_ce_1112_o => clk_ce_1112_o,
clk_ce_11120000_o => clk_ce_11120000_o,
clk_ce_111200000_o => clk_ce_111200000_o,
clk_ce_1390000_o => clk_ce_1390000_o,
clk_ce_2_o => clk_ce_2_o,
clk_ce_2224_o => clk_ce_2224_o,
clk_ce_22240000_o => clk_ce_22240000_o,
clk_ce_222400000_o => clk_ce_222400000_o,
clk_ce_2780000_o => clk_ce_2780000_o,
clk_ce_35_o => clk_ce_35_o,
clk_ce_5000_o => clk_ce_5000_o,
clk_ce_556_o => clk_ce_556_o,
clk_ce_5560000_o => clk_ce_5560000_o,
clk_ce_70_o => clk_ce_70_o,
dbg_cur_address_o => dbg_cur_address_o,
dbg_adc_ch0_cond_o => dbg_adc_ch0_cond_o,
dbg_adc_ch1_cond_o => dbg_adc_ch1_cond_o,
dbg_adc_ch2_cond_o => dbg_adc_ch2_cond_o,
dbg_adc_ch3_cond_o => dbg_adc_ch3_cond_o
);
end rtl;
| lgpl-3.0 | 9177555c37220ec630d6cf09ce9866fe | 0.37227 | 3.856561 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/fr_cmplr_v6_3_483a28da4a562c1e.vhd | 1 | 6,992 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_483a28da4a562c1e.vhd when simulating
-- the core, fr_cmplr_v6_3_483a28da4a562c1e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_483a28da4a562c1e IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_483a28da4a562c1e;
ARCHITECTURE fr_cmplr_v6_3_483a28da4a562c1e_a OF fr_cmplr_v6_3_483a28da4a562c1e IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_483a28da4a562c1e
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_483a28da4a562c1e USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "45,45",
c_accum_path_widths => "45,45",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_483a28da4a562c1e.mif",
c_coef_file_lines => 140,
c_coef_mem_packing => 0,
c_coef_memtype => 2,
c_coef_path_sign => "0,0",
c_coef_path_src => "0,0",
c_coef_path_widths => "16,16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "4",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_483a28da4a562c1e",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 1,
c_data_memtype => 1,
c_data_path_sign => "0,0",
c_data_path_src => "0,1",
c_data_path_widths => "24,24",
c_data_width => 24,
c_datapath_memtype => 1,
c_decim_rate => 35,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 1,
c_interp_rate => 1,
c_ipbuff_memtype => 0,
c_latency => 12,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 64,
c_m_data_tuser_width => 1,
c_mem_arrangement => 1,
c_num_channels => 2,
c_num_filts => 1,
c_num_madds => 4,
c_num_reload_slots => 1,
c_num_taps => 248,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "25,25",
c_output_rate => 35,
c_output_width => 25,
c_oversampling_rate => 1,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 48,
c_s_data_tuser_width => 1,
c_symmetry => 1,
c_xdevicefamily => "artix7",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_483a28da4a562c1e
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_483a28da4a562c1e_a;
| lgpl-3.0 | ad7554393a75c8f45ac4b06fe1e4501b | 0.552489 | 3.483807 | false | false | false | false |
wltr/common-vhdl | generic/mem_data_triplicator/src/rtl/mem_data_triplicator/mem_data_triplicator_wr.vhd | 1 | 4,075 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Triplicate data on write.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mem_data_triplicator_wr is
generic (
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Memory interface
mem_wr_en_o : out std_ulogic;
mem_data_o : out std_ulogic_vector(width_g - 1 downto 0);
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_wr;
architecture rtl of mem_data_triplicator_wr is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- FSM states
type state_t is (IDLE, A_WRITTEN, B_WRITTEN, C_WRITTEN);
-- FSM registers
type reg_t is record
state : state_t;
mem_wr_en : std_ulogic;
mem_data : std_ulogic_vector(width_g - 1 downto 0);
busy : std_ulogic;
done : std_ulogic;
end record reg_t;
-- FSM initial state
constant init_c : reg_t := (
state => IDLE,
mem_wr_en => '0',
mem_data => (others => '0'),
busy => '0',
done => '0');
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= reg.busy;
done_o <= reg.done;
mem_wr_en_o <= reg.mem_wr_en;
mem_data_o <= reg.mem_data;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- FSM registering
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
-- FSM combinatorics
comb : process(reg, wr_en_i, data_i, mem_done_i) is
begin -- process comb
-- Defaults
next_reg <= reg;
next_reg.mem_wr_en <= init_c.mem_wr_en;
next_reg.done <= init_c.done;
case reg.state is
when IDLE =>
if wr_en_i = '1' then
next_reg.mem_data <= data_i;
next_reg.mem_wr_en <= '1';
next_reg.busy <= '1';
next_reg.state <= A_WRITTEN;
end if;
when A_WRITTEN =>
if mem_done_i = '1' then
next_reg.mem_wr_en <= '1';
next_reg.state <= B_WRITTEN;
end if;
when B_WRITTEN =>
if mem_done_i = '1' then
next_reg.mem_wr_en <= '1';
next_reg.state <= C_WRITTEN;
end if;
when C_WRITTEN =>
if mem_done_i = '1' then
next_reg <= init_c;
next_reg.done <= '1';
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | 9a7bca580a0a3e1ac98bbc4de2dd697b | 0.395092 | 4.166667 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/video_engine.vhd | 1 | 4,259 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.basic_types_pkg.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.game_state_pkg.all;
use work.colors_pkg.all;
use work.vga_pkg.all;
use work.text_mode_pkg.all;
-- The video engine produces the signals to drive a VGA display from the game
-- data provided. Its main functions are:
-- 1) To draw the game background on the screen
-- 2) To draw the game sprites (performed in the sprites engine subblock)
-- 3) To check for collisions between the game sprites (performed in the
-- sprites engine subblock)
entity video_engine is
generic (
SPRITES_INITIAL_VALUES: sprites_array_type;
SPRITES_COLLISION_QUERY: sprite_collision_query_type
);
port (
-- system clock used for all user logic
clock_50MHz: in std_logic;
-- synchronous reset for all user logic
reset: in std_logic;
-- VGA pixel clock (~27.175 MHz)
vga_clock_in: in std_logic;
-- bundle with all signals required to drive the VGA display
vga_signals: out vga_output_signals_type;
sprites_coordinates: in point_array_type(SPRITES_INITIAL_VALUES'range);
sprites_enabled: in bool_vector(SPRITES_INITIAL_VALUES'range);
sprite_collisions_results: out bool_vector;
background_bitmap: paletted_bitmap_type;
text_mode_strings: text_mode_strings_type
);
end;
architecture rtl of video_engine is
-- interface signals for sprites_engine
signal sprite_pixel: palette_color_type;
-- true when output pixel from sprite engine should be drawn on the screen
signal sprite_pixel_is_valid: boolean;
signal vga_hsync, vga_vsync: std_logic;
signal video_on: std_logic;
signal raster_position: point_type;
begin
vga_timing: entity work.vga_timing_generator
port map(
vga_clock_in => vga_clock_in,
horiz_sync_out => vga_hsync,
vert_sync_out => vga_vsync,
video_on => video_on,
pixel_row => raster_position.y,
pixel_column => raster_position.x
);
sprites_engine: entity work.sprites_engine
generic map (
SPRITES_INITIAL_VALUES => SPRITES_INITIAL_VALUES,
SPRITES_COLLISION_QUERY => SPRITES_COLLISION_QUERY
)
port map(
clock => vga_clock_in,
reset => reset,
raster_position => raster_position / ZOOM_FACTOR,
sprites_coordinates => sprites_coordinates,
sprites_enabled => sprites_enabled,
sprite_pixel => sprite_pixel,
sprite_pixel_is_valid => sprite_pixel_is_valid,
sprite_collisions_results => sprite_collisions_results
);
vga_signals.hsync <= vga_hsync;
vga_signals.vsync <= vga_vsync;
vga_signals.sync <= '1';
vga_signals.blank <= '1'; -- looks like this one is active low...
-- The same input clock is added to the output signals because it may
-- required by the video DAC chip
vga_signals.vga_clock_out <= vga_clock_in;
process (all) is
variable palette_pixel: palette_color_type;
variable output_pixel: output_pixel_type;
variable background_point: point_type;
begin
if not video_on then
palette_pixel := PC_BLACK;
elsif text_pixel_at_x_y(raster_position.x, raster_position.y, text_mode_strings) then
palette_pixel := TEXT_COLOR;
elsif sprite_pixel_is_valid then
palette_pixel := sprite_pixel;
else
background_point.x := (raster_position.x / ZOOM_FACTOR) mod background_bitmap'length(1);
background_point.y := (raster_position.y / ZOOM_FACTOR) mod background_bitmap'length(2);
palette_pixel := background_bitmap(background_point.y, background_point.x);
end if;
output_pixel := output_pixel_from_palette_color(palette_pixel);
vga_signals.red <= output_pixel.r;
vga_signals.green <= output_pixel.g;
vga_signals.blue <= output_pixel.b;
end process;
end; | unlicense | c17550d8d7d26aec19fd5398fae24590 | 0.62409 | 3.843863 | false | false | false | false |
wltr/common-vhdl | memory/fifo/src/rtl/fifo_tmr.vhd | 1 | 3,107 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- First-in, first-out buffer with TMR.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity fifo_tmr is
generic (
-- FIFO depth
depth_g : positive := 32;
-- Data bit width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Write port
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
done_o : out std_ulogic;
full_o : out std_ulogic;
wr_busy_o : out std_ulogic;
-- Read port
rd_en_i : in std_ulogic;
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
empty_o : out std_ulogic;
rd_busy_o : out std_ulogic);
end entity fifo_tmr;
architecture rtl of fifo_tmr is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal fifo_wr_en : std_ulogic;
signal fifo_data_in : std_ulogic_vector(width_g - 1 downto 0);
signal fifo_done : std_ulogic;
signal fifo_rd_en : std_ulogic;
signal fifo_data_out : std_ulogic_vector(width_g - 1 downto 0);
signal fifo_data_out_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
rd_tmr_inst : entity work.mem_data_triplicator_rd
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rd_en_i => rd_en_i,
data_o => data_o,
data_en_o => data_en_o,
busy_o => rd_busy_o,
voted_o => open,
mem_rd_en_o => fifo_rd_en,
mem_data_i => fifo_data_out,
mem_data_en_i => fifo_data_out_en);
wr_tmr_inst : entity work.mem_data_triplicator_wr
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => wr_en_i,
data_i => data_i,
busy_o => wr_busy_o,
done_o => done_o,
mem_wr_en_o => fifo_wr_en,
mem_data_o => fifo_data_in,
mem_done_i => fifo_done);
fifo_inst : entity work.fifo
generic map (
depth_g => (depth_g * 3),
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => fifo_wr_en,
data_i => fifo_data_in,
done_o => fifo_done,
full_o => full_o,
rd_en_i => fifo_rd_en,
data_o => fifo_data_out,
data_en_o => fifo_data_out_en,
empty_o => empty_o);
end architecture rtl;
| lgpl-2.1 | 86664fa5b5aad6be5f19fa9e13db66ca | 0.456711 | 3.270526 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/adventure_demo/resource_data_pkg.vhd | 1 | 11,009 | use work.sprites_pkg.all;
use work.graphics_types_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.npc_pkg.all;
package resource_data_pkg is
-- Here we define all the sprites used in the game
constant GAME_SPRITES: sprite_init_array_type := (
(SPRITE_PLAYER, bitmap_handle => BITMAP_SORCERER),
(SPRITE_AXE, bitmap_handle => BITMAP_AXE ),
(SPRITE_ARCHER, bitmap_handle => BITMAP_ARCHER ),
(SPRITE_CHEST, bitmap_handle => BITMAP_CHEST ),
(SPRITE_GHOST, bitmap_handle => BITMAP_GHOST ),
(SPRITE_SCORPION, bitmap_handle => BITMAP_SCORPION),
(SPRITE_ORYX_11, bitmap_handle => BITMAP_ORYX_11 ),
(SPRITE_ORYX_12, bitmap_handle => BITMAP_ORYX_12 ),
(SPRITE_ORYX_21, bitmap_handle => BITMAP_ORYX_21 ),
(SPRITE_ORYX_22, bitmap_handle => BITMAP_ORYX_22 ),
(SPRITE_BAT, bitmap_handle => BITMAP_BAT ),
(SPRITE_REAPER, bitmap_handle => BITMAP_REAPER )
);
constant GAME_COLLISIONS: sprite_collision_init_array_type := (
( COLLISION_PLAYER_GHOST, SPRITE_PLAYER, SPRITE_GHOST ),
( COLLISION_PLAYER_SCORPION, SPRITE_PLAYER, SPRITE_SCORPION ),
( COLLISION_PLAYER_ORYX, SPRITE_PLAYER, SPRITE_ORYX_11 ),
( COLLISION_PLAYER_CHEST, SPRITE_PLAYER, SPRITE_CHEST ),
( COLLISION_PLAYER_REAPER, SPRITE_PLAYER, SPRITE_REAPER )
);
-- Define the Non-Player Characters (NPCs) used in the game. NPCs have
-- their positions updated automatically; the user logic is responsible for
-- reading their positions and assigning them to the corresponding sprites
constant GAME_NPCS: npc_init_array_type := (
-- Ghost, moves around the chest in a diamond-shaped path
( NPC_GHOST,
make_npc_bouncer(
initial_position => (144, 64),
allowed_region => (128, 64, 160, 96),
initial_speed => (1, 1)
)),
-- Scorpion, moves horizontally accross the screen
( NPC_SCORPION,
make_npc_bouncer(
initial_position => (0, 128),
initial_speed => (1, 0)
)),
-- Bat, moves horizontally
( NPC_BAT,
make_npc_bouncer(
initial_position => (160, 160),
allowed_region => (0, 160, 300, 164),
initial_speed => (1, 1)
)),
-- Oryx, tries to kill the player with its sword
( NPC_ORYX,
make_npc_follower(
initial_position => (300, 220),
slowdown_factor => 2
)),
-- Archer, tries to hide behind the player
( NPC_ARCHER,
make_npc_follower(
initial_position => (0, 0),
slowdown_factor => 1
)),
-- Reaper, stays near the player
( NPC_REAPER,
make_npc_follower(
initial_position => (300, 64),
slowdown_factor => 4
))
);
-- Here we define the actual bitmaps for each sprite in the game. This is
-- the second step to add a new sprite in the game.
constant GAME_BITMAPS: bitmap_init_array_type := (
(
handle => BITMAP_SORCERER,
bitmap => (
(23, 23, 24, 24, 23, 0, 20, 20),
( 0, 23, 24, 24, 23, 23, 0, 20),
(23, 23, 57, 34, 57, 34, 0, 61),
( 0, 23, 23, 57, 57, 57, 0, 20),
(23, 23, 24, 24, 24, 23, 23, 57),
(57, 20, 20, 20, 19, 20, 0, 20),
( 0, 23, 23, 23, 23, 23, 0, 20),
(23, 19, 23, 23, 23, 19, 0, 19)
)
),
(
handle => BITMAP_AXE,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 18, 0, 0, 37, 0),
( 0, 0, 0, 0, 18, 18, 0, 0),
( 0, 0, 0, 0, 18, 18, 18, 19),
( 0, 0, 0, 37, 0, 18, 19, 19),
( 0, 0, 37, 0, 0, 19, 19, 0),
( 0, 37, 0, 0, 0, 0, 0, 0),
(37, 0, 0, 0, 0, 0, 0, 0)
)
),
(
handle => BITMAP_ARCHER,
bitmap => (
(29, 29, 30, 30, 29, 0, 25, 0),
( 0, 29, 30, 30, 30, 29, 0, 25),
( 0, 29, 57, 34, 57, 34, 0, 25),
( 0, 3, 57, 57, 57, 57, 0, 25),
(44, 29, 30, 30, 30, 29, 29, 57),
(57, 37, 38, 38, 19, 37, 0, 41),
( 0, 29, 29, 29, 29, 29, 0, 25),
( 0, 37, 0, 0, 0, 37, 38, 0)
)
),
(
handle => BITMAP_CHEST,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 38, 38, 38, 38, 38, 38, 0),
(38, 2, 2, 2, 2, 38, 2, 38),
(38, 38, 38, 38, 38, 38, 38, 38),
(38, 1, 46, 1, 22, 38, 22, 38),
(38, 21, 21, 1, 22, 37, 22, 38),
(37, 37, 37, 37, 37, 37, 37, 37),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
),
(
handle => BITMAP_GHOST,
bitmap => (
( 0, 0, 0, 53, 53, 53, 20, 0),
( 0, 0, 53, 53, 24, 53, 24, 0),
( 0, 0, 53, 53, 53, 53, 53, 0),
( 0, 53, 53, 53, 53, 34, 53, 53),
( 0, 0, 53, 53, 53, 34, 20, 0),
(53, 0, 53, 53, 53, 53, 20, 0),
( 0, 53, 53, 53, 53, 53, 20, 0),
( 0, 0, 53, 53, 53, 20, 0, 0)
)
),
(
handle => BITMAP_SCORPION,
bitmap => (
( 0, 18, 18, 18, 0, 0, 0, 0),
(18, 0, 0, 17, 17, 0, 0, 0),
(18, 0, 0, 0, 17, 0, 0, 0),
(18, 0, 0, 0, 0, 0, 0, 0),
(18, 18, 0, 0, 0, 0, 0, 0),
(17, 18, 18, 18, 18, 24, 18, 24),
( 0, 17, 18, 18, 18, 18, 18, 18),
(17, 0, 17, 0, 17, 0, 17, 0)
)
),
(
handle => BITMAP_ORYX_11,
bitmap => (
( 0, 20, 0, 0, 20, 0, 0, 0),
(20, 20, 0, 20, 0, 0, 34, 34),
(20, 20, 0, 20, 0, 34, 17, 17),
(20, 20, 0, 0, 20, 34, 17, 17),
(20, 20, 0, 0, 0, 33, 24, 34),
(20, 20, 0, 0, 34, 33, 33, 34),
(34, 34, 0, 34, 33, 34, 33, 34),
(17, 34, 17, 34, 17, 33, 34, 33)
)
),
(
handle => BITMAP_ORYX_12,
bitmap => (
( 0, 0, 0, 20, 0, 0, 0, 0),
(34, 34, 0, 0, 20, 0, 0, 0),
(33, 33, 34, 0, 20, 0, 0, 0),
(34, 33, 34, 20, 0, 0, 0, 0),
(34, 24, 33, 0, 0, 0, 0, 0),
(34, 33, 33, 34, 0, 0, 0, 0),
(34, 33, 34, 34, 34, 34, 34, 34),
(33, 34, 17, 34, 18, 18, 18, 34)
)
),
(
handle => BITMAP_ORYX_21,
bitmap => (
(17, 34, 17, 34, 33, 17, 17, 34),
(34, 34, 0, 0, 34, 34, 34, 33),
(34, 0, 0, 0, 0, 34, 33, 33),
( 0, 0, 0, 0, 34, 17, 34, 34),
( 0, 0, 0, 34, 17, 34, 34, 17),
( 0, 0, 0, 34, 34, 34, 0, 33),
( 0, 0, 0, 34, 34, 34, 0, 0),
( 0, 0, 34, 34, 34, 34, 0, 0)
)
),
(
handle => BITMAP_ORYX_22,
bitmap => (
(34, 17, 17, 34, 18, 18, 20, 34),
(33, 34, 34, 34, 18, 20, 20, 34),
(33, 33, 34, 34, 18, 18, 20, 34),
(34, 34, 17, 34, 18, 18, 20, 34),
(17, 34, 34, 17, 34, 18, 18, 34),
(33, 0, 34, 34, 34, 34, 34, 34),
( 0, 0, 34, 34, 34, 0, 0, 0),
( 0, 0, 34, 34, 34, 34, 0, 0)
)
),
(
handle => BITMAP_BAT,
bitmap => (
( 0, 0, 0, 17, 0, 17, 0, 0),
( 0, 17, 0, 17, 17, 17, 0, 17),
(17, 17, 0, 46, 17, 46, 0, 17),
(17, 17, 17, 17, 17, 17, 17, 17),
(17, 17, 17, 17, 17, 17, 17, 17),
(17, 17, 0, 17, 17, 0, 17, 17),
(17, 0, 0, 17, 0, 0, 0, 17),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
),
( handle => BITMAP_REAPER,
bitmap => (
(34, 34, 34, 19, 19, 19, 19, 19),
( 0, 34, 19, 33, 33, 33, 0, 38),
( 0, 34, 34, 23, 53, 23, 0, 38),
( 0, 34, 34, 53, 53, 53, 0, 38),
(34, 34, 34, 34, 34, 34, 34, 53),
(53, 34, 34, 34, 34, 34, 0, 38),
( 0, 34, 34, 34, 34, 34, 0, 38),
(34, 34, 34, 34, 34, 34, 34, 38)
)),
( handle => BITMAP_FOREST_TILE,
bitmap => (
(11, 11, 11, 11, 12, 1, 11, 11),
(12, 1, 11, 11, 11, 12, 11, 11),
(11, 12, 11, 11, 11, 11, 11, 11),
(11, 11, 11, 12, 11, 11, 11, 11),
(11, 11, 11, 11, 12, 11, 11, 11),
(11, 11, 11, 11, 11, 11, 1, 11),
(11, 12, 11, 11, 11, 11, 12, 11),
(11, 11, 12, 11, 11, 11, 11, 11)
)),
(
handle => BITMAP_GAME_OVER_TILE,
bitmap => (
(22, 46, 22, 46, 22, 46, 22, 22),
(22, 22, 46, 26, 26, 26, 46, 22),
(22, 46, 26, 53, 53, 53, 25, 22),
(22, 26, 53, 53, 53, 53, 53, 42),
(22, 42, 53, 53, 34, 53, 34, 23),
(22, 22, 23, 36, 53, 34, 53, 23),
(22, 22, 22, 23, 36, 36, 36, 23),
(22, 22, 22, 22, 24, 23, 23, 22)
)
),
(
handle => BITMAP_GAME_WON_TILE,
bitmap => (
( 7, 7, 38, 38, 38, 38, 38, 7),
( 7, 7, 38, 46, 46, 1, 38, 17),
( 7, 7, 46, 26, 46, 46, 38, 17),
( 7, 46, 26, 46, 26, 46, 38, 7),
(38, 38, 38, 38, 38, 38, 38, 7),
(38, 1, 46, 2, 38, 2, 38, 7),
(38, 2, 1, 2, 38, 2, 38, 7),
(38, 38, 38, 38, 38, 38, 7, 7)
)
)
);
end;
| unlicense | ee2c23a5dcb009ec61d5b199d9cbb381 | 0.348624 | 3.042001 | false | false | false | false |
wltr/common-vhdl | generic/stop_watch/src/rtl/stop_watch.vhd | 1 | 2,152 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Count time in between strobes.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity stop_watch is
generic (
-- Counter bit width
bit_width_g : positive := 8);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Sample and reset counter value
sample_i : in std_ulogic;
-- Count
value_o : out std_ulogic_vector(bit_width_g - 1 downto 0));
end entity stop_watch;
architecture rtl of stop_watch is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : unsigned(bit_width_g - 1 downto 0) := (others => '0');
signal value : unsigned(bit_width_g - 1 downto 0) := (others => '0');
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
value_o <= std_ulogic_vector(value);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Count
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= to_unsigned(0, count'length);
value <= to_unsigned(0, value'length);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
elsif sample_i = '1' then
count <= to_unsigned(0, count'length);
value <= count;
elsif en_i = '1' then
count <= count + 1;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | c0bd4a6865b6338cb3477c2ee57dde0e | 0.421004 | 4.598291 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/space_shooter_demo/resource_data_pkg.vhd | 1 | 6,284 | use work.sprites_pkg.all;
use work.graphics_types_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.npc_pkg.all;
package resource_data_pkg is
-- Here we define all the sprites used in the game
constant GAME_SPRITES: sprite_init_array_type := (
(SPRITE_PLAYER_SHIP_1, bitmap_handle => BITMAP_PLAYER_SHIP_1),
(SPRITE_PLAYER_SHIP_2, bitmap_handle => BITMAP_PLAYER_SHIP_2),
(SPRITE_PLAYER_SHOT, bitmap_handle => BITMAP_PLAYER_SHOT),
(SPRITE_ENEMY_SHIP_1, bitmap_handle => BITMAP_ENEMY_SHIP_1),
(SPRITE_ENEMY_SHIP_2, bitmap_handle => BITMAP_ENEMY_SHIP_2),
(SPRITE_ALIEN_SHIP_1, bitmap_handle => BITMAP_ALIEN_SHIP),
(SPRITE_ALIEN_SHIP_2, bitmap_handle => BITMAP_ALIEN_SHIP),
(SPRITE_ALIEN_SHIP_3, bitmap_handle => BITMAP_ALIEN_SHIP)
);
constant GAME_COLLISIONS: sprite_collision_init_array_type := (
( COLLISION_PLAYER_SHOT_ALIEN_1, SPRITE_PLAYER_SHOT, SPRITE_ALIEN_SHIP_1 ),
( COLLISION_PLAYER_SHOT_ALIEN_2, SPRITE_PLAYER_SHOT, SPRITE_ALIEN_SHIP_2 ),
( COLLISION_PLAYER_SHOT_ALIEN_3, SPRITE_PLAYER_SHOT, SPRITE_ALIEN_SHIP_3 ),
( COLLISION_PLAYER_SHOT_ENEMY_1, SPRITE_PLAYER_SHOT, SPRITE_ENEMY_SHIP_1 ),
( COLLISION_PLAYER_2_ALIEN_1, SPRITE_PLAYER_SHIP_2, SPRITE_ALIEN_SHIP_1 ),
( COLLISION_PLAYER_2_ALIEN_2, SPRITE_PLAYER_SHIP_2, SPRITE_ALIEN_SHIP_2 ),
( COLLISION_PLAYER_2_ALIEN_2, SPRITE_PLAYER_SHIP_2, SPRITE_ALIEN_SHIP_3 ),
( COLLISION_PLAYER_2_ENEMY_1, SPRITE_PLAYER_SHIP_2, SPRITE_ENEMY_SHIP_2 )
);
-- Define the Non-Player Characters (NPCs) used in the game. NPCs have
-- their positions updated automatically; the user logic is responsible for
-- reading their positions and assigning them to the corresponding sprites
constant GAME_NPCS: npc_init_array_type := (
-- Player shot
( NPC_PLAYER_SHOT,
make_npc_projectile(
initial_position => (48, 152),
initial_speed => (4, 0),
allowed_region => (0, 0, 328, 240)
)),
-- Enemy ship 1
( NPC_ENEMY_SHIP,
make_npc_bouncer(
initial_position => (200, 60),
allowed_region => (200, 60, 300, 180),
initial_speed => (2, 2)
)),
-- Alien ship #1
( NPC_ALIEN_SHIP_1,
make_npc_bouncer(
initial_position => (400, 100),
initial_speed => (1, 2)
)),
-- Alien ship #2
( NPC_ALIEN_SHIP_2,
make_npc_bouncer(
initial_position => (410, 120),
initial_speed => (1, 2)
)),
-- Alien ship #3
( NPC_ALIEN_SHIP_3,
make_npc_bouncer(
initial_position => (420, 140),
initial_speed => (1, 2)
))
);
-- Here we define the actual bitmaps for each sprite in the game. This is
-- the second step to add a new sprite in the game.
constant GAME_BITMAPS: bitmap_init_array_type := (
( handle => BITMAP_PLAYER_SHIP_1,
bitmap => (
( 0, 20, 53, 53, 53, 53, 53, 17),
( 0, 55, 24, 20, 20, 20, 20, 53),
( 0, 0, 0, 0, 3, 3, 19, 49),
( 0, 18, 18, 18, 19, 19, 2, 54),
(18, 20, 20, 20, 53, 53, 53, 20),
( 0, 18, 18, 18, 17, 19, 19, 19),
(18, 20, 20, 20, 18, 0, 3, 3),
( 0, 18, 18, 18, 0, 0, 0, 0)
)
),
( handle => BITMAP_PLAYER_SHIP_2,
bitmap => (
(33, 0, 0, 0, 0, 0, 0, 0),
(53, 19, 0, 0, 0, 0, 0, 0),
( 5, 7, 7, 5, 5, 0, 0, 0),
( 7, 54, 10, 53, 10, 7, 0, 0),
(35, 54, 10, 10, 10, 52, 7, 0),
(18, 53, 48, 54, 54, 10, 10, 6),
( 3, 3, 18, 53, 53, 54, 54, 5),
( 0, 0, 0, 19, 20, 20, 20, 17)
)
),
( handle => BITMAP_PLAYER_SHOT,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 50, 43, 50, 0, 0, 0),
( 0, 51, 36, 36, 43, 50, 0, 0),
( 0, 51, 36, 36, 43, 50, 0, 0),
( 0, 0, 50, 43, 50, 0, 0, 0),
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
),
( handle => BITMAP_ENEMY_SHIP_1,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
( 0, 0, 0, 33, 17, 17, 17, 17),
( 0, 33, 17, 36, 53, 36, 8, 8),
(33, 17, 8, 8, 8, 8, 8, 17),
(17, 17, 17, 17, 17, 17, 17, 20),
(17, 24, 24, 24, 24, 24, 24, 24),
(33, 17, 17, 17, 17, 17, 24, 24),
( 0, 0, 0, 0, 0, 33, 17, 17)
)
),
( handle => BITMAP_ENEMY_SHIP_2,
bitmap => (
( 0, 0, 0, 0, 0, 0, 0, 0),
(17, 17, 0, 0, 0, 0, 0, 0),
( 8, 17, 17, 0, 17, 17, 0, 0),
(17, 20, 20, 33, 20, 17, 24, 0),
(20, 19, 19, 19, 19, 17, 40, 26),
(24, 24, 24, 17, 19, 17, 24, 0),
(24, 24, 17, 33, 17, 17, 0, 0),
(17, 17, 17, 0, 0, 0, 0, 0)
)
),
( handle => BITMAP_ALIEN_SHIP,
bitmap => (
( 0, 0, 22, 23, 23, 23, 22, 0),
(22, 23, 23, 0, 17, 19, 23, 22),
( 0, 0, 16, 3, 19, 10, 19, 23),
( 0, 54, 10, 20, 10, 36, 10, 0),
( 0, 0, 16, 3, 19, 10, 19, 23),
(22, 23, 23, 0, 17, 19, 23, 22),
( 0, 0, 22, 23, 23, 23, 22, 0),
( 0, 0, 0, 0, 0, 0, 0, 0)
)
)
);
end;
| unlicense | 5148ddf202fba1d5ac7e16d5991ef068 | 0.411203 | 2.978199 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_2717b25e8a23e5e2.vhd | 1 | 6,147 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_2717b25e8a23e5e2.vhd when simulating
-- the core, cc_cmplr_v3_0_2717b25e8a23e5e2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_2717b25e8a23e5e2 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_2717b25e8a23e5e2;
ARCHITECTURE cc_cmplr_v3_0_2717b25e8a23e5e2_a OF cc_cmplr_v3_0_2717b25e8a23e5e2 IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_2717b25e8a23e5e2
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_2717b25e8a23e5e2 USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 58,
c_c2 => 58,
c_c3 => 58,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2,
c_component_name => "cc_cmplr_v3_0_2717b25e8a23e5e2",
c_diff_delay => 2,
c_family => "virtex6",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 58,
c_i2 => 58,
c_i3 => 58,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 1120,
c_min_rate => 1120,
c_num_channels => 2,
c_num_stages => 3,
c_output_width => 58,
c_rate => 1120,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_2717b25e8a23e5e2
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_2717b25e8a23e5e2_a;
| lgpl-3.0 | f70f8b4ccf41a43ebad6e05939493533 | 0.557508 | 3.586348 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_mac.vhd | 1 | 2,226 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Multiply the filter coefficients with the input data and accumulate
-- the results.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_filter_mac is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Decoded data
data_i : in signed(6 downto 0);
-- Coefficient
coeff_i : in unsigned(23 downto 0);
coeff_en_i : in std_ulogic;
coeff_done_i : in std_ulogic;
-- MAC result
data_o : out signed(23 downto 0);
data_en_o : out std_ulogic);
end entity ads1281_filter_mac;
architecture rtl of ads1281_filter_mac is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal res : signed(30 downto 0);
signal res_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Multiply filter coefficient with input data
ads1281_filter_multiplier_inst : entity work.ads1281_filter_multiplier
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => data_i,
coeff_i => coeff_i,
coeff_en_i => coeff_en_i,
res_o => res,
res_en_o => res_en);
-- Accumulate result
ads1281_filter_accumulator_inst : entity work.ads1281_filter_accumulator
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
data_i => res,
data_en_i => res_en,
coeff_done_i => coeff_done_i,
data_o => data_o,
data_en_o => data_en_o);
end architecture rtl;
| lgpl-2.1 | d835cd9da73f94868f97bf0c9c355d54 | 0.442049 | 4.039927 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/addsb_11_0_239e4f614ba09ab1.vhd | 1 | 4,569 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_239e4f614ba09ab1.vhd when simulating
-- the core, addsb_11_0_239e4f614ba09ab1. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_239e4f614ba09ab1 IS
PORT (
a : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END addsb_11_0_239e4f614ba09ab1;
ARCHITECTURE addsb_11_0_239e4f614ba09ab1_a OF addsb_11_0_239e4f614ba09ab1 IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_239e4f614ba09ab1
PORT (
a : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_239e4f614ba09ab1 USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 26,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "00000000000000000000000000",
c_b_width => 26,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 26,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_239e4f614ba09ab1
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_239e4f614ba09ab1_a;
| lgpl-3.0 | 81d701d4405e25802433319f1fc70ee1 | 0.536441 | 4.068566 | false | false | false | false |
wltr/common-vhdl | generic/array_transmitter/src/rtl/array_tx.vhd | 1 | 3,557 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Send multiple packets.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity array_tx is
generic (
-- Number of data packets
data_count_g : positive range 2 to positive'high := 8;
-- Data bit width
data_width_g : positive := 32);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Internal interface
data_i : in std_ulogic_vector((data_count_g * data_width_g) - 1 downto 0);
data_en_i : in std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Transmitter interface
tx_data_o : out std_ulogic_vector(data_width_g - 1 downto 0);
tx_data_en_o : out std_ulogic;
tx_done_i : in std_ulogic);
end entity array_tx;
architecture rtl of array_tx is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(data_count_g);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter maximum value
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, data_count_g - 1);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : std_ulogic_vector(len_c - 1 downto 0) := seed_c;
signal tx_en : std_ulogic := '0';
signal busy : std_ulogic := '0';
signal done : std_ulogic := '0';
signal data : std_ulogic_vector(data_i'range) := (others => '0');
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= busy;
done_o <= done;
tx_data_o <= data(data'high downto data'high - data_width_g + 1);
tx_data_en_o <= tx_en;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= seed_c;
tx_en <= '0';
busy <= '0';
done <= '0';
data <= (others => '0');
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
tx_en <= '0';
done <= '0';
if busy = '1' and tx_done_i = '1' then
if count = max_c then
count <= seed_c;
busy <= '0';
done <= '1';
else
count <= lfsr_shift(count);
tx_en <= '1';
data <= data(data'high - data_width_g downto data'low) & (data_width_g - 1 downto 0 => '0');
end if;
end if;
if data_en_i = '1' then
busy <= '1';
tx_en <= '1';
data <= data_i;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 87e5f4c58e2bca978387fbba073edd6f | 0.427326 | 4.005631 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_05afd5373121e2a3.vhd | 1 | 6,979 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_05afd5373121e2a3.vhd when simulating
-- the core, fr_cmplr_v6_3_05afd5373121e2a3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_05afd5373121e2a3 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_05afd5373121e2a3;
ARCHITECTURE fr_cmplr_v6_3_05afd5373121e2a3_a OF fr_cmplr_v6_3_05afd5373121e2a3 IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_05afd5373121e2a3
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_05afd5373121e2a3 USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "41",
c_accum_path_widths => "41",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_05afd5373121e2a3.mif",
c_coef_file_lines => 42,
c_coef_mem_packing => 0,
c_coef_memtype => 2,
c_coef_path_sign => "0",
c_coef_path_src => "0",
c_coef_path_widths => "16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "1",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_05afd5373121e2a3",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 1,
c_data_memtype => 1,
c_data_path_sign => "0",
c_data_path_src => "0",
c_data_path_widths => "24",
c_data_width => 24,
c_datapath_memtype => 2,
c_decim_rate => 2,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 2800000,
c_interp_rate => 1,
c_ipbuff_memtype => 0,
c_latency => 30,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 32,
c_m_data_tuser_width => 2,
c_mem_arrangement => 1,
c_num_channels => 4,
c_num_filts => 1,
c_num_madds => 1,
c_num_reload_slots => 1,
c_num_taps => 81,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "25",
c_output_rate => 5600000,
c_output_width => 25,
c_oversampling_rate => 21,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 24,
c_s_data_tuser_width => 2,
c_symmetry => 1,
c_xdevicefamily => "virtex6",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_05afd5373121e2a3
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_05afd5373121e2a3_a;
| lgpl-3.0 | 79a948466e3da1a7e7a6b9274fd0f966 | 0.552945 | 3.548043 | false | false | false | false |
wltr/common-vhdl | generic/edge_detector/src/rtl/edge_detector.vhd | 1 | 3,767 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Detect edges on input signal.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity edge_detector is
generic (
-- Initial value of observed signal
init_value_g : std_ulogic := '0';
-- Edge type: 0 = Rising, 1 = Falling, 2 = Both
edge_type_g : natural range 0 to 2 := 0;
-- Hold flag until it is acknowledged
hold_flag_g : boolean := false);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Acknowledge detected edges
ack_i : in std_ulogic;
-- Monitored signal
sig_i : in std_ulogic;
-- Detection flag
edge_o : out std_ulogic);
end entity edge_detector;
architecture rtl of edge_detector is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal sig : std_ulogic := init_value_g;
signal edge : std_ulogic := '0';
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal detected : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
edge_o <= edge;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Detect rising edge
rising_gen : if edge_type_g = 0 generate
detected <= (sig_i and not sig) and en_i;
end generate rising_gen;
-- Detect falling edge
falling_gen : if edge_type_g = 1 generate
detected <= (not sig_i and sig) and en_i;
end generate falling_gen;
-- Detect both edges
both_gen : if edge_type_g = 2 generate
detected <= (sig_i xor sig) and en_i;
end generate both_gen;
-- Directly report a detected edge
direct_gen : if hold_flag_g = false generate
edge <= detected;
end generate direct_gen;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
sig <= init_value_g;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Save last state of observed signal
sig <= sig_i;
end if;
end if;
end process regs;
-- Hold flag which reports a detected edge
hold_gen : if hold_flag_g = true generate
hold : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
edge <= '0';
end procedure reset;
begin -- process hold
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if ack_i = '1' then
-- The acknowledge input resets the flag
edge <= '0';
elsif detected = '1' then
-- Set flag when an edge is detected
edge <= '1';
end if;
end if;
end if;
end process hold;
end generate hold_gen;
end architecture rtl;
| lgpl-2.1 | 0a6691a69875176716a34aba52fb7a10 | 0.439873 | 4.691158 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/addsb_11_0_3537d66a2361cd1e.vhd | 1 | 4,568 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file addsb_11_0_3537d66a2361cd1e.vhd when simulating
-- the core, addsb_11_0_3537d66a2361cd1e. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY addsb_11_0_3537d66a2361cd1e IS
PORT (
a : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END addsb_11_0_3537d66a2361cd1e;
ARCHITECTURE addsb_11_0_3537d66a2361cd1e_a OF addsb_11_0_3537d66a2361cd1e IS
-- synthesis translate_off
COMPONENT wrapped_addsb_11_0_3537d66a2361cd1e
PORT (
a : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_addsb_11_0_3537d66a2361cd1e USE ENTITY XilinxCoreLib.c_addsub_v11_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 26,
c_add_mode => 0,
c_ainit_val => "0",
c_b_constant => 0,
c_b_type => 0,
c_b_value => "00000000000000000000000000",
c_b_width => 26,
c_borrow_low => 1,
c_bypass_low => 0,
c_ce_overrides_bypass => 1,
c_ce_overrides_sclr => 0,
c_has_bypass => 0,
c_has_c_in => 0,
c_has_c_out => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_sinit => 0,
c_has_sset => 0,
c_implementation => 0,
c_latency => 0,
c_out_width => 26,
c_sclr_overrides_sset => 0,
c_sinit_val => "0",
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_addsb_11_0_3537d66a2361cd1e
PORT MAP (
a => a,
b => b,
s => s
);
-- synthesis translate_on
END addsb_11_0_3537d66a2361cd1e_a;
| lgpl-3.0 | 45dd373580a07adc7740009cfb916ad5 | 0.53634 | 4.104223 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_position_calc/wb_position_calc_core.vhd | 1 | 88,243 | ------------------------------------------------------------------------------
-- Title : Wishbone Position Calculation Core
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-07-02
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Core Module for position calculation with de-cross, amplitude compensation
-- and delay tuning.
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-07-02 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- Position Calc
use work.position_calc_core_pkg.all;
-- WB registers
use work.pos_calc_wbgen2_pkg.all;
entity wb_position_calc_core is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_rffe_version : string := "V2";
g_with_switching : natural := 0
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
-----------------------------
-- BPF Data
-----------------------------
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
bpf_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
pos_x_tbt_o : out std_logic_vector(25 downto 0);
pos_y_tbt_o : out std_logic_vector(25 downto 0);
pos_q_tbt_o : out std_logic_vector(25 downto 0);
pos_sum_tbt_o : out std_logic_vector(25 downto 0);
pos_tbt_valid_o : out std_logic;
pos_x_fofb_o : out std_logic_vector(25 downto 0);
pos_y_fofb_o : out std_logic_vector(25 downto 0);
pos_q_fofb_o : out std_logic_vector(25 downto 0);
pos_sum_fofb_o : out std_logic_vector(25 downto 0);
pos_fofb_valid_o : out std_logic;
pos_x_monit_o : out std_logic_vector(25 downto 0);
pos_y_monit_o : out std_logic_vector(25 downto 0);
pos_q_monit_o : out std_logic_vector(25 downto 0);
pos_sum_monit_o : out std_logic_vector(25 downto 0);
pos_monit_valid_o : out std_logic;
pos_x_monit_1_o : out std_logic_vector(25 downto 0);
pos_y_monit_1_o : out std_logic_vector(25 downto 0);
pos_q_monit_1_o : out std_logic_vector(25 downto 0);
pos_sum_monit_1_o : out std_logic_vector(25 downto 0);
pos_monit_1_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0);
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_11120000_o : out std_logic;
clk_ce_111200000_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic;
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(15 downto 0)
);
end wb_position_calc_core;
architecture rtl of wb_position_calc_core is
---------------------------------------------------------
-- Constants --
---------------------------------------------------------
constant c_periph_addr_size : natural := 5+2;
constant c_cdc_data_ref_width : natural := 4*c_dsp_ref_num_bits; -- c_num_adc_channels ?
constant c_cdc_data_ref_iq_width : natural := 8*c_dsp_ref_num_bits; -- c_num_adc_channels*2 ?
constant c_cdc_data_pos_width : natural := 4*c_dsp_pos_num_bits; -- c_num_adc_channels ?
constant c_cdc_ref_size : natural := 16;
-- Crossbar component constants
-- Number of slaves
constant c_slaves : natural := 2;
-- Number of masters
constant c_masters : natural := 1; -- Top master.
constant c_num_pipeline_regs : integer := 8;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
( 0 => f_sdb_embed_device(c_xwb_pos_calc_core_regs_sdb,
x"00000000"), -- Register interface
1 => f_sdb_embed_device(c_xwb_bpm_swap_sdb, x"00000100") -- WB swap
);
-- Self Describing Bus ROM Address. It will be an addressed slave as well.
constant c_sdb_address : t_wishbone_address := x"00000600";
---------------------------------------------------------
-- General Signals --
---------------------------------------------------------
signal sys_clr : std_logic;
signal sys_clr2x : std_logic;
-- Try to reduce fanout of clear signal
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of sys_clr: signal is "REDUCE";
attribute MAX_FANOUT of sys_clr2x: signal is "REDUCE";
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
-- Register interface signals
signal regs_out : t_pos_calc_out_registers;
signal regs_in : t_pos_calc_in_registers;
-----------------------------
-- Wishbone crossbar signals
-----------------------------
-- Crossbar master/slave arrays
signal cbar_slave_in : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_out : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_in : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_out : t_wishbone_master_out_array(c_slaves-1 downto 0);
---------------------------------------------------------
-- ADC, MIX and BPF data --
---------------------------------------------------------
signal adc_ch0_sp : std_logic_vector(15 downto 0);
signal adc_ch1_sp : std_logic_vector(15 downto 0);
signal adc_ch2_sp : std_logic_vector(15 downto 0);
signal adc_ch3_sp : std_logic_vector(15 downto 0);
signal adc_ch0_cond : std_logic_vector(15 downto 0);
signal adc_ch1_cond : std_logic_vector(15 downto 0);
signal adc_ch2_cond : std_logic_vector(15 downto 0);
signal adc_ch3_cond : std_logic_vector(15 downto 0);
-- Input conditioner signals
signal adc_ch0_pos_calc : std_logic_vector(15 downto 0);
signal adc_ch1_pos_calc : std_logic_vector(15 downto 0);
signal adc_ch2_pos_calc : std_logic_vector(15 downto 0);
signal adc_ch3_pos_calc : std_logic_vector(15 downto 0);
-- BPM Swap signals
signal sw_mode1 : std_logic_vector(1 downto 0);
signal sw_mode2 : std_logic_vector(1 downto 0);
signal clk_swap_en : std_logic;
signal wdw_rst : std_logic;
signal wdw_rst_n : std_logic;
signal wdw_input_cond_rst_n : std_logic;
signal wdw_sw_clk_in : std_logic;
signal wdw_sw_clk : std_logic;
signal wdw_use_en : std_logic;
signal wdw_dly : std_logic_vector(15 downto 0);
signal bpf_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal bpf_valid : std_logic := '1';
signal mix_ch0_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch0_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch1_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch1_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch2_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch2_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch3_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_ch3_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal mix_valid : std_logic := '1';
---------------------------------------------------------
-- TBT data --
---------------------------------------------------------
signal tbt_decim_ch0_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch0_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch1_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch1_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch2_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch2_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch3_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_ch3_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_decim_valid : std_logic := '1';
signal tbt_decim_q_ch01_incorrect_int : std_logic;
signal tbt_decim_q_ch23_incorrect_int : std_logic;
signal tbt_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_amp_valid : std_logic := '1';
signal tbt_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal tbt_pha_valid : std_logic := '1';
---------------------------------------------------------
-- FOFB data --
---------------------------------------------------------
signal fofb_decim_ch0_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch0_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch1_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch1_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch2_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch2_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch3_i : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_ch3_q : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_decim_valid : std_logic := '1';
signal fofb_decim_q_ch01_missing_int : std_logic;
signal fofb_decim_q_ch23_missing_int : std_logic;
signal fofb_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_amp_valid : std_logic := '1';
signal fofb_pha_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal fofb_pha_valid : std_logic := '1';
---------------------------------------------------------
-- Monitoring data --
---------------------------------------------------------
signal monit_amp_ch0 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch1 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch2 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch3 : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_valid : std_logic := '1';
signal monit_amp_ch0_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch1_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch2_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_ch3_fs_sync : std_logic_vector(c_dsp_ref_num_bits-1 downto 0);
signal monit_amp_valid_fs_sync : std_logic := '1';
signal monit_cic_unexpected_int : std_logic;
signal monit_cfir_incorrect_int : std_logic;
signal monit_pfir_incorrect_int : std_logic;
signal monit_pos_1_incorrect_int : std_logic;
---------------------------------------------------------
-- Position data --
---------------------------------------------------------
signal x_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_tbt_valid : std_logic := '1';
signal y_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_tbt_valid : std_logic := '1';
signal q_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_tbt_valid : std_logic := '1';
signal sum_tbt : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_tbt_valid : std_logic := '1';
signal x_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_fofb_valid : std_logic := '1';
signal y_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_fofb_valid : std_logic := '1';
signal q_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_fofb_valid : std_logic := '1';
signal sum_fofb : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_fofb_valid : std_logic := '1';
signal x_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_monit_valid : std_logic := '1';
signal y_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_valid : std_logic := '1';
signal q_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_valid : std_logic := '1';
signal sum_monit : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_valid : std_logic := '1';
signal x_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal pos_monit_valid_fs_sync : std_logic := '1';
signal x_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal x_monit_1_valid : std_logic := '1';
signal y_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_1_valid : std_logic := '1';
signal q_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_1_valid : std_logic := '1';
signal sum_monit_1 : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_1_valid : std_logic := '1';
signal x_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal y_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal q_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal sum_monit_1_fs_sync : std_logic_vector(c_dsp_pos_num_bits-1 downto 0);
signal pos_monit_1_valid_fs_sync : std_logic := '1';
---------------------------------------------------------
-- FIFO CDC signals
---------------------------------------------------------
signal fifo_bpf_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_bpf_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_bpf_valid_in : std_logic;
signal fifo_bpf_valid_out : std_logic;
signal fifo_mix_in : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_mix_out : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_mix_valid_in : std_logic;
signal fifo_mix_valid_out : std_logic;
signal fifo_tbt_decim_in : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_tbt_decim_out : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_tbt_decim_valid_in : std_logic;
signal fifo_tbt_decim_valid_out : std_logic;
signal fifo_tbt_amp_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_amp_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_amp_valid_in : std_logic;
signal fifo_tbt_amp_valid_out : std_logic;
signal fifo_tbt_pha_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_pha_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_tbt_pha_valid_in : std_logic;
signal fifo_tbt_pha_valid_out : std_logic;
signal fifo_tbt_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_tbt_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_tbt_pos_valid_in : std_logic;
signal fifo_tbt_pos_valid_out : std_logic;
signal fifo_fofb_decim_in : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_fofb_decim_out : std_logic_vector(c_cdc_data_ref_iq_width-1 downto 0);
signal fifo_fofb_decim_valid_in : std_logic;
signal fifo_fofb_decim_valid_out : std_logic;
signal fifo_fofb_amp_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_amp_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_amp_valid_in : std_logic;
signal fifo_fofb_amp_valid_out : std_logic;
signal fifo_fofb_pha_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_pha_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_fofb_pha_valid_in : std_logic;
signal fifo_fofb_pha_valid_out : std_logic;
signal fifo_fofb_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_fofb_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_fofb_pos_valid_in : std_logic;
signal fifo_fofb_pos_valid_out : std_logic;
signal fifo_monit_amp_in : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_monit_amp_out : std_logic_vector(c_cdc_data_ref_width-1 downto 0);
signal fifo_monit_amp_valid_in : std_logic;
signal fifo_monit_amp_valid_out : std_logic;
signal fifo_monit_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_pos_valid_in : std_logic;
signal fifo_monit_pos_valid_out : std_logic;
signal fifo_monit_1_pos_in : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_1_pos_out : std_logic_vector(c_cdc_data_pos_width-1 downto 0);
signal fifo_monit_1_pos_valid_in : std_logic;
signal fifo_monit_1_pos_valid_out : std_logic;
---------------------------------------------------------
-- Clock Enable signals --
---------------------------------------------------------
signal clk_ce_1 : std_logic;
signal clk_ce_1112 : std_logic;
signal clk_ce_1390000 : std_logic;
signal clk_ce_2 : std_logic;
signal clk_ce_2224 : std_logic;
signal clk_ce_22240000 : std_logic;
signal clk_ce_222400000 : std_logic;
signal clk_ce_2780000 : std_logic;
signal clk_ce_35 : std_logic;
signal clk_ce_5000 : std_logic;
signal clk_ce_556 : std_logic;
signal clk_ce_5560000 : std_logic;
signal clk_ce_70 : std_logic;
signal clk_ce_11120000_int : std_logic;
signal clk_ce_111200000_int : std_logic;
-- Components instatiation
component wb_pos_calc_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
fs_clk2x_i : in std_logic;
regs_i : in t_pos_calc_in_registers;
regs_o : out t_pos_calc_out_registers
);
end component;
begin
-- fs_rst_n_i => fs_rst_n_i,
--sys_clr <= not fs_rst_n_i;
--sys_clr2x <= not fs_rst2x_n_i;
sys_clr <= '0';
sys_clr2x <= '0';
-----------------------------
-- WB Position Calc Core Address decoder
-----------------------------
-- We need 2 outputs, as in the same wishbone addressing range, 2
-- other wishbone peripherals must be driven:
--
-- 0 -> WB Position Calc Core Register Wishbone Interface
-- 1 -> WB Uncross module.
-- The Internal Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => true, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_in,
slave_o => cbar_slave_out,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_in,
master_o => cbar_master_out
);
-- External master connection
cbar_slave_in(0).adr <= wb_adr_i;
cbar_slave_in(0).dat <= wb_dat_i;
cbar_slave_in(0).sel <= wb_sel_i;
cbar_slave_in(0).we <= wb_we_i;
cbar_slave_in(0).cyc <= wb_cyc_i;
cbar_slave_in(0).stb <= wb_stb_i;
wb_dat_o <= cbar_slave_out(0).dat;
wb_ack_o <= cbar_slave_out(0).ack;
wb_stall_o <= cbar_slave_out(0).stall;
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => cbar_master_out(0).dat,
sl_sel_i => cbar_master_out(0).sel,
sl_cyc_i => cbar_master_out(0).cyc,
sl_stb_i => cbar_master_out(0).stb,
sl_we_i => cbar_master_out(0).we,
sl_dat_o => cbar_master_in(0).dat,
sl_ack_o => cbar_master_in(0).ack,
sl_rty_o => cbar_master_in(0).rty,
sl_err_o => cbar_master_in(0).err,
sl_int_o => cbar_master_in(0).int,
sl_stall_o => cbar_master_in(0).stall
);
resized_addr(c_periph_addr_size-1 downto 0)
<= cbar_master_out(0).adr(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size)
<= (others => '0');
-----------------------------
-- Position Calc Core Register Wishbone Interface. Word addressed!
-----------------------------
--Position Calc Core register interface is the slave number 0, word addressed
cmp_wb_pos_calc_regs : wb_pos_calc_regs
port map(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wb_slv_adp_out.adr(4 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => fs_clk_i,
fs_clk2x_i => fs_clk2x_i,
regs_i => regs_in,
regs_o => regs_out
);
-- Unused wishbone signals
wb_slv_adp_in.int <= '0';
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
-- Registers fixed assignments
regs_in.ds_tbt_thres_reserved_i <= (others => '0');
regs_in.ds_fofb_thres_reserved_i <= (others => '0');
regs_in.ds_monit_thres_reserved_i <= (others => '0');
regs_in.kx_reserved_i <= (others => '0');
regs_in.ky_reserved_i <= (others => '0');
regs_in.ksum_reserved_i <= (others => '0');
regs_in.dds_cfg_reserved_ch0_i <= (others => '0');
regs_in.dds_cfg_reserved_ch1_i <= (others => '0');
regs_in.dds_cfg_reserved_ch2_i <= (others => '0');
regs_in.dds_cfg_reserved_ch3_i <= (others => '0');
regs_in.dds_pinc_ch0_reserved_i <= (others => '0');
regs_in.dds_pinc_ch1_reserved_i <= (others => '0');
regs_in.dds_pinc_ch2_reserved_i <= (others => '0');
regs_in.dds_pinc_ch3_reserved_i <= (others => '0');
regs_in.dds_poff_ch0_reserved_i <= (others => '0');
regs_in.dds_poff_ch1_reserved_i <= (others => '0');
regs_in.dds_poff_ch2_reserved_i <= (others => '0');
regs_in.dds_poff_ch3_reserved_i <= (others => '0');
-- Sync with fs_clk
regs_in.dsp_monit_amp_ch0_i <=
std_logic_vector(resize(signed(monit_amp_ch0_fs_sync), regs_in.dsp_monit_amp_ch0_i'length));
regs_in.dsp_monit_amp_ch1_i <=
std_logic_vector(resize(signed(monit_amp_ch1_fs_sync), regs_in.dsp_monit_amp_ch1_i'length));
regs_in.dsp_monit_amp_ch2_i <=
std_logic_vector(resize(signed(monit_amp_ch2_fs_sync), regs_in.dsp_monit_amp_ch2_i'length));
regs_in.dsp_monit_amp_ch3_i <=
std_logic_vector(resize(signed(monit_amp_ch3_fs_sync), regs_in.dsp_monit_amp_ch3_i'length));
-- Sync with fs_clk
regs_in.dsp_monit_pos_x_i <=
std_logic_vector(resize(signed(x_monit_fs_sync), regs_in.dsp_monit_pos_x_i'length));
regs_in.dsp_monit_pos_y_i <=
std_logic_vector(resize(signed(y_monit_fs_sync), regs_in.dsp_monit_pos_y_i'length));
regs_in.dsp_monit_pos_q_i <=
std_logic_vector(resize(signed(q_monit_fs_sync), regs_in.dsp_monit_pos_q_i'length));
regs_in.dsp_monit_pos_sum_i <=
std_logic_vector(resize(signed(sum_monit_fs_sync), regs_in.dsp_monit_pos_sum_i'length));
-----------------------------
-- BPM Swap Module.
-----------------------------
-- BPM Swap Module interface is the slave number 1
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
fs_clk_i => fs_clk_i,
fs_rst_n_i => fs_rst_n_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => cbar_master_out(1).adr,
wb_dat_i => cbar_master_out(1).dat,
wb_dat_o => cbar_master_in(1).dat,
wb_sel_i => cbar_master_out(1).sel,
wb_we_i => cbar_master_out(1).we,
wb_cyc_i => cbar_master_out(1).cyc,
wb_stb_i => cbar_master_out(1).stb,
wb_ack_o => cbar_master_in(1).ack,
wb_stall_o => cbar_master_in(1).stall,
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i => adc_ch0_i,
chb_i => adc_ch1_i,
chc_i => adc_ch2_i,
chd_i => adc_ch3_i,
-- Output to data processing level
cha_o => adc_ch0_sp,
chb_o => adc_ch1_sp,
chc_o => adc_ch2_sp,
chd_o => adc_ch3_sp,
mode1_o => sw_mode1,
mode2_o => sw_mode2,
wdw_rst_o => wdw_rst,
wdw_sw_clk_i => wdw_sw_clk_in,
wdw_use_o => wdw_use_en,
wdw_dly_o => wdw_dly,
-- Output to RFFE board
clk_swap_o => clk_swap_o,
clk_swap_en_o => clk_swap_en,
flag1_o => flag1_o,
flag2_o => flag2_o,
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o
);
wdw_sw_clk_in <= wdw_sw_clk;
wdw_rst_n <= not wdw_rst;
adc_ch0_dbg_data_o <= adc_ch0_sp;
adc_ch1_dbg_data_o <= adc_ch1_sp;
adc_ch2_dbg_data_o <= adc_ch2_sp;
adc_ch3_dbg_data_o <= adc_ch3_sp;
cmp_input_conditioner : input_conditioner
generic map
(
g_sw_interval => 1000/2, -- We need to generate 2x the FOFB decimation rate
g_input_width => 16, -- FIXME: use ADC constant
g_output_width => 16, -- FIXME: use ADC constant
g_window_width => 24, -- This must match the MATLAB script
g_input_delay => 2+3, -- wb_bpm_swap fixed latency + multiplier pipeline latency
g_window_coef_file => f_window_file(g_rffe_version)
)
port map
(
reset_n_i => wdw_input_cond_rst_n,
clk_i => fs_clk_i,
adc_a_i => adc_ch0_sp,
adc_b_i => adc_ch1_sp,
adc_c_i => adc_ch2_sp,
adc_d_i => adc_ch3_sp,
switch_o => wdw_sw_clk,
switch_en_i => clk_swap_en,
switch_delay_i => wdw_dly,
a_o => adc_ch0_cond,
b_o => adc_ch1_cond,
c_o => adc_ch2_cond,
d_o => adc_ch3_cond,
dbg_cur_address_o => dbg_cur_address_o
);
wdw_input_cond_rst_n <= fs_rst_n_i or wdw_rst_n;
dbg_adc_ch0_cond_o <= adc_ch0_cond;
dbg_adc_ch1_cond_o <= adc_ch1_cond;
dbg_adc_ch2_cond_o <= adc_ch2_cond;
dbg_adc_ch3_cond_o <= adc_ch3_cond;
-- Bypass windowing conditioning if switching is disabled
--
-- sw_mode1 controls channels 0 and 2 : "00" is matched,
-- "01" is direct, "10" is inverted, "11" is switching
--
-- sw_mode2 controls channels 1 and 3 : "00" is matched,
-- "01" is direct, "10" is inverted, "11" is switching
--adc_ch0_pos_calc <= adc_ch0_cond when sw_mode1 = "11" else adc_ch0_sp;
--adc_ch1_pos_calc <= adc_ch1_cond when sw_mode2 = "11" else adc_ch1_sp;
--adc_ch2_pos_calc <= adc_ch2_cond when sw_mode1 = "11" else adc_ch2_sp;
--adc_ch3_pos_calc <= adc_ch3_cond when sw_mode2 = "11" else adc_ch3_sp;
adc_ch0_pos_calc <= adc_ch0_cond when wdw_use_en = '1' else adc_ch0_sp;
adc_ch1_pos_calc <= adc_ch1_cond when wdw_use_en = '1' else adc_ch1_sp;
adc_ch2_pos_calc <= adc_ch2_cond when wdw_use_en = '1' else adc_ch2_sp;
adc_ch3_pos_calc <= adc_ch3_cond when wdw_use_en = '1' else adc_ch3_sp;
cmp_position_calc: position_calc
generic map
(
g_pipeline_regs => c_num_pipeline_regs
)
port map
(
adc_ch0_i => adc_ch0_pos_calc,
adc_ch1_i => adc_ch1_pos_calc,
adc_ch2_i => adc_ch2_pos_calc,
adc_ch3_i => adc_ch3_pos_calc,
clk => fs_clk2x_i,
clr => sys_clr2x,
del_sig_div_fofb_thres_i => regs_out.ds_tbt_thres_val_o,
del_sig_div_monit_thres_i => regs_out.ds_fofb_thres_val_o,
del_sig_div_tbt_thres_i => regs_out.ds_monit_thres_val_o,
ksum_i => regs_out.ksum_val_o,
kx_i => regs_out.kx_val_o,
ky_i => regs_out.ky_val_o,
dds_config_valid_ch0_i => regs_out.dds_cfg_valid_ch0_o,
dds_config_valid_ch1_i => regs_out.dds_cfg_valid_ch1_o,
dds_config_valid_ch2_i => regs_out.dds_cfg_valid_ch2_o,
dds_config_valid_ch3_i => regs_out.dds_cfg_valid_ch3_o,
dds_pinc_ch0_i => regs_out.dds_pinc_ch0_val_o,
dds_pinc_ch1_i => regs_out.dds_pinc_ch1_val_o,
dds_pinc_ch2_i => regs_out.dds_pinc_ch2_val_o,
dds_pinc_ch3_i => regs_out.dds_pinc_ch3_val_o,
dds_poff_ch0_i => regs_out.dds_poff_ch0_val_o,
dds_poff_ch1_i => regs_out.dds_poff_ch1_val_o,
dds_poff_ch2_i => regs_out.dds_poff_ch2_val_o,
dds_poff_ch3_i => regs_out.dds_poff_ch3_val_o,
--adc_ch0_dbg_data_o => adc_ch0_dbg_data_o,
--adc_ch1_dbg_data_o => adc_ch1_dbg_data_o,
--adc_ch2_dbg_data_o => adc_ch2_dbg_data_o,
--adc_ch3_dbg_data_o => adc_ch3_dbg_data_o,
adc_ch0_dbg_data_o => open,
adc_ch1_dbg_data_o => open,
adc_ch2_dbg_data_o => open,
adc_ch3_dbg_data_o => open,
bpf_ch0_o => bpf_ch0,
bpf_ch1_o => bpf_ch1,
bpf_ch2_o => bpf_ch2,
bpf_ch3_o => bpf_ch3,
mix_ch0_i_o => mix_ch0_i,
mix_ch0_q_o => mix_ch0_q,
mix_ch1_i_o => mix_ch1_i,
mix_ch1_q_o => mix_ch1_q,
mix_ch2_i_o => mix_ch2_i,
mix_ch2_q_o => mix_ch2_q,
mix_ch3_i_o => mix_ch3_i,
mix_ch3_q_o => mix_ch3_q,
tbt_decim_ch0_i_o => tbt_decim_ch0_i,
tbt_decim_ch0_q_o => tbt_decim_ch0_q,
tbt_decim_ch1_i_o => tbt_decim_ch1_i,
tbt_decim_ch1_q_o => tbt_decim_ch1_q,
tbt_decim_ch2_i_o => tbt_decim_ch2_i,
tbt_decim_ch2_q_o => tbt_decim_ch2_q,
tbt_decim_ch3_i_o => tbt_decim_ch3_i,
tbt_decim_ch3_q_o => tbt_decim_ch3_q,
tbt_decim_q_ch01_incorrect_o => tbt_decim_q_ch01_incorrect_int,
tbt_decim_q_ch23_incorrect_o => tbt_decim_q_ch23_incorrect_int,
tbt_amp_ch0_o => tbt_amp_ch0,
tbt_amp_ch1_o => tbt_amp_ch1,
tbt_amp_ch2_o => tbt_amp_ch2,
tbt_amp_ch3_o => tbt_amp_ch3,
tbt_pha_ch0_o => tbt_pha_ch0,
tbt_pha_ch1_o => tbt_pha_ch1,
tbt_pha_ch2_o => tbt_pha_ch2,
tbt_pha_ch3_o => tbt_pha_ch3,
fofb_decim_ch0_i_o => fofb_decim_ch0_i,
fofb_decim_ch0_q_o => fofb_decim_ch0_q,
fofb_decim_ch1_i_o => fofb_decim_ch1_i,
fofb_decim_ch1_q_o => fofb_decim_ch1_q,
fofb_decim_ch2_i_o => fofb_decim_ch2_i,
fofb_decim_ch2_q_o => fofb_decim_ch2_q,
fofb_decim_ch3_i_o => fofb_decim_ch3_i,
fofb_decim_ch3_q_o => fofb_decim_ch3_q,
fofb_decim_q_01_missing_o => fofb_decim_q_ch01_missing_int,
fofb_decim_q_23_missing_o => fofb_decim_q_ch23_missing_int,
fofb_amp_ch0_o => fofb_amp_ch0,
fofb_amp_ch1_o => fofb_amp_ch1,
fofb_amp_ch2_o => fofb_amp_ch2,
fofb_amp_ch3_o => fofb_amp_ch3,
fofb_pha_ch0_o => fofb_pha_ch0,
fofb_pha_ch1_o => fofb_pha_ch1,
fofb_pha_ch2_o => fofb_pha_ch2,
fofb_pha_ch3_o => fofb_pha_ch3,
monit_amp_ch0_o => monit_amp_ch0,
monit_amp_ch1_o => monit_amp_ch1,
monit_amp_ch2_o => monit_amp_ch2,
monit_amp_ch3_o => monit_amp_ch3,
monit_cic_unexpected_o => monit_cic_unexpected_int,
monit_cfir_incorrect_o => monit_cfir_incorrect_int,
monit_pfir_incorrect_o => monit_pfir_incorrect_int,
x_tbt_o => x_tbt,
x_tbt_valid_o => x_tbt_valid,
y_tbt_o => y_tbt,
y_tbt_valid_o => y_tbt_valid, -- will be removed soon
q_tbt_o => q_tbt,
q_tbt_valid_o => q_tbt_valid, -- will be removed soon
sum_tbt_o => sum_tbt,
sum_tbt_valid_o => sum_tbt_valid, -- will be removed soon
x_fofb_o => x_fofb,
x_fofb_valid_o => x_fofb_valid,
y_fofb_o => y_fofb,
y_fofb_valid_o => y_fofb_valid, -- will be removed soon
q_fofb_o => q_fofb,
q_fofb_valid_o => q_fofb_valid, -- will be removed soon
sum_fofb_o => sum_fofb,
sum_fofb_valid_o => sum_fofb_valid,-- will be removed soon
x_monit_o => x_monit,
x_monit_valid_o => x_monit_valid,
y_monit_o => y_monit,
y_monit_valid_o => y_monit_valid, -- will be removed soon
q_monit_o => q_monit,
q_monit_valid_o => q_monit_valid, -- will be removed soon
sum_monit_o => sum_monit,
sum_monit_valid_o => sum_monit_valid, -- will be removed soon
x_monit_1_o => x_monit_1,
x_monit_1_valid_o => x_monit_1_valid,
y_monit_1_o => y_monit_1,
y_monit_1_valid_o => y_monit_1_valid, -- will be removed soon
q_monit_1_o => q_monit_1,
q_monit_1_valid_o => q_monit_1_valid, -- will be removed soon
sum_monit_1_o => sum_monit_1,
sum_monit_1_valid_o => sum_monit_1_valid,-- will be removed soon
monit_pos_1_incorrect_o => monit_pos_1_incorrect_int,
-- Clock drivers for various rates
clk_ce_1_o => clk_ce_1,
clk_ce_1112_o => clk_ce_1112,
clk_ce_1390000_o => clk_ce_1390000,
clk_ce_2_o => clk_ce_2,
clk_ce_2224_o => clk_ce_2224,
clk_ce_22240000_o => clk_ce_22240000,
clk_ce_222400000_o => clk_ce_222400000,
clk_ce_2780000_o => clk_ce_2780000,
clk_ce_35_o => clk_ce_35,
clk_ce_5000_o => clk_ce_5000,
clk_ce_556_o => clk_ce_556,
clk_ce_5560000_o => clk_ce_5560000,
clk_ce_70_o => clk_ce_70
);
--------------------------------------------------------------------------
-- Missing CE --
--------------------------------------------------------------------------
-- Generate missing clk_ce_11120000
cmp_xlclockdriver_clk_ce_11120000 : xlclockdriver
generic map (
log_2_period => 24,
period => 11200000, -- FIXME: Change CE net name to the correct ones! This is just to avoid changing the interface
pipeline_regs => c_num_pipeline_regs,
use_bufg => 0
)
port map (
sysce => '1',
sysclk => fs_clk2x_i,
sysclr => sys_clr2x,
ce => clk_ce_11120000_int,
clk => open
);
clk_ce_11120000_o <= clk_ce_11120000_int;
-- Generate missing clk_ce_111200000
cmp_xlclockdriver_clk_ce_111200000 : xlclockdriver
generic map (
log_2_period => 27,
period => 112000000, -- FIXME: Change CE net name to the correct ones! This is just to avoid changing the interface
pipeline_regs => c_num_pipeline_regs,
use_bufg => 0
)
port map (
sysce => '1',
sysclk => fs_clk2x_i,
sysclr => sys_clr2x,
ce => clk_ce_111200000_int,
clk => open
);
clk_ce_111200000_o <= clk_ce_111200000_int;
-- Output CE
clk_ce_1_o <= clk_ce_1;
clk_ce_1112_o <= clk_ce_1112;
clk_ce_1390000_o <= clk_ce_1390000;
clk_ce_2_o <= clk_ce_2;
clk_ce_2224_o <= clk_ce_2224;
clk_ce_22240000_o <= clk_ce_22240000;
clk_ce_222400000_o <= clk_ce_222400000;
clk_ce_2780000_o <= clk_ce_2780000;
clk_ce_35_o <= clk_ce_35;
clk_ce_5000_o <= clk_ce_5000;
clk_ce_556_o <= clk_ce_556;
clk_ce_5560000_o <= clk_ce_5560000;
clk_ce_70_o <= clk_ce_70;
--------------------------------------------------------------------------
-- Position Calc Counters
--------------------------------------------------------------------------
cmp_position_calc_counters : position_calc_counters
port map
(
fs_clk2x_i => fs_clk2x_i,-- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
fs_rst2x_n_i => fs_rst2x_n_i,
-- Clock enables for various rates
tbt_ce_i => clk_ce_70,
fofb_ce_i => clk_ce_2224,
monit_cic_ce_i => clk_ce_5560000,
monit_cfir_ce_i => clk_ce_11120000_int, -- check this rate!
monit_pfir_ce_i => clk_ce_22240000,
monit_01_ce_i => clk_ce_222400000,
tbt_decim_q_ch01_incorrect_i => tbt_decim_q_ch01_incorrect_int,
tbt_decim_q_ch23_incorrect_i => tbt_decim_q_ch23_incorrect_int,
tbt_decim_err_clr_i => regs_out.dsp_err_clr_tbt_o,
fofb_decim_q_ch01_missing_i => fofb_decim_q_ch01_missing_int,
fofb_decim_q_ch23_missing_i => fofb_decim_q_ch23_missing_int,
fofb_decim_err_clr_i => regs_out.dsp_err_clr_fofb_o,
monit_cic_unexpected_i => monit_cic_unexpected_int,
monit_cfir_incorrect_i => monit_cfir_incorrect_int,
monit_part1_err_clr_i => regs_out.dsp_err_clr_monit_part1_o,
monit_pfir_incorrect_i => monit_pfir_incorrect_int,
monit_pos_1_incorrect_i => monit_pos_1_incorrect_int,
monit_part2_err_clr_i => regs_out.dsp_err_clr_monit_part2_o,
tbt_incorrect_ctnr_ch01_o => regs_in.dsp_ctnr_tbt_ch01_i,
tbt_incorrect_ctnr_ch23_o => regs_in.dsp_ctnr_tbt_ch23_i,
fofb_incorrect_ctnr_ch01_o => regs_in.dsp_ctnr_fofb_ch01_i,
fofb_incorrect_ctnr_ch23_o => regs_in.dsp_ctnr_fofb_ch23_i,
monit_cic_incorrect_ctnr_o => regs_in.dsp_ctnr1_monit_cic_i,
monit_cfir_incorrect_ctnr_o => regs_in.dsp_ctnr1_monit_cfir_i,
monit_pfir_incorrect_ctnr_o => regs_in.dsp_ctnr2_monit_pfir_i,
monit_01_incorrect_ctnr_o => regs_in.dsp_ctnr2_monit_fir_01_i
);
--------------------------------------------------------------------------
-- CDC position data (Amplitudes and Position) to fs_clk domain --
--------------------------------------------------------------------------
--------------------------------------------------------------------------
-- MIX and BPF data --
--------------------------------------------------------------------------
-- BPF data
cmp_position_calc_cdc_fifo_bpf : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_bpf_in,
valid_i => fifo_bpf_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_bpf_out,
valid_o => fifo_bpf_valid_out
);
p_reg_cdc_fifo_bpf_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_bpf_in <= (others => '0');
fifo_bpf_valid_in <= '0';
elsif clk_ce_2 = '1' then
fifo_bpf_in <= bpf_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
bpf_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
bpf_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
bpf_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_bpf_valid_in <= bpf_valid;
else
fifo_bpf_valid_in <= '0';
end if;
end if;
end process;
bpf_ch3_o <= fifo_bpf_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
bpf_ch2_o <= fifo_bpf_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
bpf_ch1_o <= fifo_bpf_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
bpf_ch0_o <= fifo_bpf_out(c_dsp_ref_num_bits-1 downto 0);
bpf_valid_o <= fifo_bpf_valid_out;
-- MIX data
cmp_position_calc_cdc_fifo_mix : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_iq_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_mix_in,
valid_i => fifo_mix_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_mix_out,
valid_o => fifo_mix_valid_out
);
p_reg_cdc_fifo_mix_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_mix_in <= (others => '0');
fifo_mix_valid_in <= '0';
elsif clk_ce_2 = '1' then
fifo_mix_in <= mix_ch3_q & -- 8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits
mix_ch3_i & -- 7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits
mix_ch2_q & -- 6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits
mix_ch2_i & -- 5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits
mix_ch1_q & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
mix_ch1_i & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
mix_ch0_q & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
mix_ch0_i; -- c_dsp_ref_num_bits-1 downto 0
fifo_mix_valid_in <= mix_valid;
else
fifo_mix_valid_in <= '0';
end if;
end if;
end process;
mix_ch3_q_o <= fifo_mix_out(8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits);
mix_ch3_i_o <= fifo_mix_out(7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits);
mix_ch2_q_o <= fifo_mix_out(6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits);
mix_ch2_i_o <= fifo_mix_out(5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits);
mix_ch1_q_o <= fifo_mix_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
mix_ch1_i_o <= fifo_mix_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
mix_ch0_q_o <= fifo_mix_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
mix_ch0_i_o <= fifo_mix_out(c_dsp_ref_num_bits-1 downto 0);
mix_valid_o <= fifo_mix_valid_out;
--------------------------------------------------------------------------
-- TBT data --
--------------------------------------------------------------------------
-- TBT Decim data
cmp_position_calc_cdc_fifo_tbt_decim : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_iq_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_decim_in,
valid_i => fifo_tbt_decim_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_decim_out,
valid_o => fifo_tbt_decim_valid_out
);
p_reg_cdc_fifo_tbt_decim_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_decim_in <= (others => '0');
fifo_tbt_decim_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_decim_in <= tbt_decim_ch3_q & -- 8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits
tbt_decim_ch3_i & -- 7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits
tbt_decim_ch2_q & -- 6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits
tbt_decim_ch2_i & -- 5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits
tbt_decim_ch1_q & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
tbt_decim_ch1_i & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
tbt_decim_ch0_q & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
tbt_decim_ch0_i; -- c_dsp_ref_num_bits-1 downto 0
fifo_tbt_decim_valid_in <= tbt_decim_valid;
else
fifo_tbt_decim_valid_in <= '0';
end if;
end if;
end process;
tbt_decim_ch3_q_o <= fifo_tbt_decim_out(8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits);
tbt_decim_ch3_i_o <= fifo_tbt_decim_out(7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits);
tbt_decim_ch2_q_o <= fifo_tbt_decim_out(6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits);
tbt_decim_ch2_i_o <= fifo_tbt_decim_out(5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits);
tbt_decim_ch1_q_o <= fifo_tbt_decim_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
tbt_decim_ch1_i_o <= fifo_tbt_decim_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
tbt_decim_ch0_q_o <= fifo_tbt_decim_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
tbt_decim_ch0_i_o <= fifo_tbt_decim_out(c_dsp_ref_num_bits-1 downto 0);
tbt_decim_valid_o <= fifo_tbt_decim_valid_out;
--TBT amplitudes data
cmp_position_calc_cdc_fifo_tbt_amp : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_amp_in,
valid_i => fifo_tbt_amp_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_amp_out,
valid_o => fifo_tbt_amp_valid_out
);
p_reg_cdc_fifo_tbt_amp_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_amp_in <= (others => '0');
fifo_tbt_amp_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_amp_in <= tbt_amp_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
tbt_amp_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
tbt_amp_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
tbt_amp_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_tbt_amp_valid_in <= tbt_amp_valid;
else
fifo_tbt_amp_valid_in <= '0';
end if;
end if;
end process;
tbt_amp_ch3_o <= fifo_tbt_amp_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
tbt_amp_ch2_o <= fifo_tbt_amp_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
tbt_amp_ch1_o <= fifo_tbt_amp_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
tbt_amp_ch0_o <= fifo_tbt_amp_out(c_dsp_ref_num_bits-1 downto 0);
tbt_amp_valid_o <= fifo_tbt_amp_valid_out;
--TBT phase data
cmp_position_calc_cdc_fifo_tbt_phase : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_pha_in,
valid_i => fifo_tbt_pha_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_pha_out,
valid_o => fifo_tbt_pha_valid_out
);
p_reg_cdc_fifo_tbt_pha_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_pha_in <= (others => '0');
fifo_tbt_pha_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_pha_in <= tbt_pha_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
tbt_pha_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
tbt_pha_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
tbt_pha_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_tbt_pha_valid_in <= tbt_pha_valid;
else
fifo_tbt_pha_valid_in <= '0';
end if;
end if;
end process;
tbt_pha_ch3_o <= fifo_tbt_pha_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
tbt_pha_ch2_o <= fifo_tbt_pha_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
tbt_pha_ch1_o <= fifo_tbt_pha_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
tbt_pha_ch0_o <= fifo_tbt_pha_out(c_dsp_ref_num_bits-1 downto 0);
tbt_pha_valid_o <= fifo_tbt_pha_valid_out;
-- TBT position data
cmp_position_calc_cdc_fifo_tbt_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_tbt_pos_in,
valid_i => fifo_tbt_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_tbt_pos_out,
valid_o => fifo_tbt_pos_valid_out
);
p_reg_cdc_fifo_tbt_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_tbt_pos_in <= (others => '0');
fifo_tbt_pos_valid_in <= '0';
elsif clk_ce_70 = '1' then
fifo_tbt_pos_in <= sum_tbt & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_tbt & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_tbt & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_tbt; -- c_dsp_pos_num_bits-1 downto 0
fifo_tbt_pos_valid_in <= x_tbt_valid;
else
fifo_tbt_pos_valid_in <= '0';
end if;
end if;
end process;
pos_sum_tbt_o <= fifo_tbt_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
pos_q_tbt_o <= fifo_tbt_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
pos_y_tbt_o <= fifo_tbt_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
pos_x_tbt_o <= fifo_tbt_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_tbt_valid_o <= fifo_tbt_pos_valid_out;
--------------------------------------------------------------------------
-- FOFB data --
--------------------------------------------------------------------------
-- FOFB Decim data
cmp_position_calc_cdc_fifo_fofb_decim : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_iq_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_decim_in,
valid_i => fifo_fofb_decim_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_decim_out,
valid_o => fifo_fofb_decim_valid_out
);
p_reg_cdc_fifo_fofb_decim_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_decim_in <= (others => '0');
fifo_fofb_decim_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_decim_in <= fofb_decim_ch3_q & -- 8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits
fofb_decim_ch3_i & -- 7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits
fofb_decim_ch2_q & -- 6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits
fofb_decim_ch2_i & -- 5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits
fofb_decim_ch1_q & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
fofb_decim_ch1_i & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
fofb_decim_ch0_q & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
fofb_decim_ch0_i; -- c_dsp_ref_num_bits-1 downto 0
fifo_fofb_decim_valid_in <= fofb_decim_valid;
else
fifo_fofb_decim_valid_in <= '0';
end if;
end if;
end process;
fofb_decim_ch3_q_o <= fifo_fofb_decim_out(8*c_dsp_ref_num_bits-1 downto 7*c_dsp_ref_num_bits);
fofb_decim_ch3_i_o <= fifo_fofb_decim_out(7*c_dsp_ref_num_bits-1 downto 6*c_dsp_ref_num_bits);
fofb_decim_ch2_q_o <= fifo_fofb_decim_out(6*c_dsp_ref_num_bits-1 downto 5*c_dsp_ref_num_bits);
fofb_decim_ch2_i_o <= fifo_fofb_decim_out(5*c_dsp_ref_num_bits-1 downto 4*c_dsp_ref_num_bits);
fofb_decim_ch1_q_o <= fifo_fofb_decim_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
fofb_decim_ch1_i_o <= fifo_fofb_decim_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
fofb_decim_ch0_q_o <= fifo_fofb_decim_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
fofb_decim_ch0_i_o <= fifo_fofb_decim_out(c_dsp_ref_num_bits-1 downto 0);
fofb_decim_valid_o <= fifo_fofb_decim_valid_out;
--FOFB amplitudes data
cmp_position_calc_cdc_fifo_fofb_amp : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_amp_in,
valid_i => fifo_fofb_amp_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_amp_out,
valid_o => fifo_fofb_amp_valid_out
);
p_reg_cdc_fifo_fofb_amp_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_amp_in <= (others => '0');
fifo_fofb_amp_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_amp_in <= fofb_amp_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
fofb_amp_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
fofb_amp_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
fofb_amp_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_fofb_amp_valid_in <= fofb_amp_valid;
else
fifo_fofb_amp_valid_in <= '0';
end if;
end if;
end process;
fofb_amp_ch3_o <= fifo_fofb_amp_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
fofb_amp_ch2_o <= fifo_fofb_amp_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
fofb_amp_ch1_o <= fifo_fofb_amp_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
fofb_amp_ch0_o <= fifo_fofb_amp_out(c_dsp_ref_num_bits-1 downto 0);
fofb_amp_valid_o <= fifo_fofb_amp_valid_out;
-- FOFB phase data
cmp_position_calc_cdc_fifo_fofb_phase : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_pha_in,
valid_i => fifo_fofb_pha_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_pha_out,
valid_o => fifo_fofb_pha_valid_out
);
p_reg_cdc_fifo_fofb_pha_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_pha_in <= (others => '0');
fifo_fofb_pha_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_pha_in <= fofb_pha_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
fofb_pha_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
fofb_pha_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
fofb_pha_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_fofb_pha_valid_in <= fofb_pha_valid;
else
fifo_fofb_pha_valid_in <= '0';
end if;
end if;
end process;
fofb_pha_ch3_o <= fifo_fofb_pha_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
fofb_pha_ch2_o <= fifo_fofb_pha_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
fofb_pha_ch1_o <= fifo_fofb_pha_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
fofb_pha_ch0_o <= fifo_fofb_pha_out(c_dsp_ref_num_bits-1 downto 0);
fofb_pha_valid_o <= fifo_fofb_pha_valid_out;
-- FOFB position data
cmp_position_calc_cdc_fifo_fofb_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_fofb_pos_in,
valid_i => fifo_fofb_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_fofb_pos_out,
valid_o => fifo_fofb_pos_valid_out
);
p_reg_cdc_fifo_fofb_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_fofb_pos_in <= (others => '0');
fifo_fofb_pos_valid_in <= '0';
elsif clk_ce_2224 = '1' then
fifo_fofb_pos_in <= sum_fofb & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_fofb & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_fofb & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_fofb; -- c_dsp_pos_num_bits-1 downto 0
fifo_fofb_pos_valid_in <= x_fofb_valid;
else
fifo_fofb_pos_valid_in <= '0';
end if;
end if;
end process;
pos_sum_fofb_o <= fifo_fofb_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
pos_q_fofb_o <= fifo_fofb_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
pos_y_fofb_o <= fifo_fofb_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
pos_x_fofb_o <= fifo_fofb_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_fofb_valid_o <= fifo_fofb_pos_valid_out;
--------------------------------------------------------------------------
-- Monitoring data --
--------------------------------------------------------------------------
-- Monitoring amplitudes data
cmp_position_calc_cdc_fifo_monit_amp : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_ref_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_monit_amp_in,
valid_i => fifo_monit_amp_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_monit_amp_out,
valid_o => fifo_monit_amp_valid_out
);
p_reg_cdc_fifo_monit_amp_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_monit_amp_in <= (others => '0');
fifo_monit_amp_valid_in <= '0';
elsif clk_ce_22240000 = '1' then
fifo_monit_amp_in <= monit_amp_ch3 & -- 4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits
monit_amp_ch2 & -- 3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits
monit_amp_ch1 & -- 2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits
monit_amp_ch0; -- c_dsp_ref_num_bits-1 downto 0
fifo_monit_amp_valid_in <= monit_amp_valid;
else
fifo_monit_amp_valid_in <= '0';
end if;
end if;
end process;
monit_amp_ch3_fs_sync <= fifo_monit_amp_out(4*c_dsp_ref_num_bits-1 downto 3*c_dsp_ref_num_bits);
monit_amp_ch2_fs_sync <= fifo_monit_amp_out(3*c_dsp_ref_num_bits-1 downto 2*c_dsp_ref_num_bits);
monit_amp_ch1_fs_sync <= fifo_monit_amp_out(2*c_dsp_ref_num_bits-1 downto c_dsp_ref_num_bits);
monit_amp_ch0_fs_sync <= fifo_monit_amp_out(c_dsp_ref_num_bits-1 downto 0);
monit_amp_valid_fs_sync <= fifo_monit_amp_valid_out;
monit_amp_ch3_o <= monit_amp_ch3_fs_sync;
monit_amp_ch2_o <= monit_amp_ch2_fs_sync;
monit_amp_ch1_o <= monit_amp_ch1_fs_sync;
monit_amp_ch0_o <= monit_amp_ch0_fs_sync;
monit_amp_valid_o <= monit_amp_valid_fs_sync;
-- Monitoring position data
cmp_position_calc_cdc_fifo_monit_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_monit_pos_in,
valid_i => fifo_monit_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_monit_pos_out,
valid_o => fifo_monit_pos_valid_out
);
p_reg_cdc_fifo_monit_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_monit_pos_in <= (others => '0');
fifo_monit_pos_valid_in <= '0';
elsif clk_ce_22240000 = '1' then
fifo_monit_pos_in <= sum_monit & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_monit & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_monit & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_monit; -- c_dsp_pos_num_bits-1 downto 0
fifo_monit_pos_valid_in <= x_monit_valid;
else
fifo_monit_pos_valid_in <= '0';
end if;
end if;
end process;
sum_monit_fs_sync <= fifo_monit_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
q_monit_fs_sync <= fifo_monit_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
y_monit_fs_sync <= fifo_monit_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
x_monit_fs_sync <= fifo_monit_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_monit_valid_fs_sync <= fifo_monit_pos_valid_out;
pos_sum_monit_o <= sum_monit_fs_sync;
pos_q_monit_o <= q_monit_fs_sync;
pos_y_monit_o <= y_monit_fs_sync;
pos_x_monit_o <= x_monit_fs_sync;
pos_monit_valid_o <= pos_monit_valid_fs_sync;
--------------------------------------------------------------------------
-- Monitoring 1 Hz data --
--------------------------------------------------------------------------
-- Monitoring 1 Hz position data
cmp_position_calc_cdc_fifo_monit_1_pos : position_calc_cdc_fifo
generic map
(
g_data_width => c_cdc_data_pos_width,
g_size => c_cdc_ref_size
)
port map
(
clk_wr_i => fs_clk2x_i,
data_i => fifo_monit_1_pos_in,
valid_i => fifo_monit_1_pos_valid_in,
clk_rd_i => fs_clk_i,
data_o => fifo_monit_1_pos_out,
valid_o => fifo_monit_1_pos_valid_out
);
p_reg_cdc_fifo_monit_1_pos_inputs : process(fs_clk2x_i)
begin
if rising_edge(fs_clk2x_i) then
if fs_rst2x_n_i = '0' then
fifo_monit_1_pos_in <= (others => '0');
fifo_monit_1_pos_valid_in <= '0';
elsif clk_ce_222400000 = '1' then
fifo_monit_1_pos_in <= sum_monit_1 & -- 4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits
q_monit_1 & -- 3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits
y_monit_1 & -- 2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits
x_monit_1; -- c_dsp_pos_num_bits-1 downto 0
fifo_monit_1_pos_valid_in <= x_monit_1_valid;
else
fifo_monit_1_pos_valid_in <= '0';
end if;
end if;
end process;
sum_monit_1_fs_sync <= fifo_monit_1_pos_out(4*c_dsp_pos_num_bits-1 downto 3*c_dsp_pos_num_bits);
q_monit_1_fs_sync <= fifo_monit_1_pos_out(3*c_dsp_pos_num_bits-1 downto 2*c_dsp_pos_num_bits);
y_monit_1_fs_sync <= fifo_monit_1_pos_out(2*c_dsp_pos_num_bits-1 downto c_dsp_pos_num_bits);
x_monit_1_fs_sync <= fifo_monit_1_pos_out(c_dsp_pos_num_bits-1 downto 0);
pos_monit_1_valid_fs_sync <= fifo_monit_1_pos_valid_out;
pos_sum_monit_1_o <= sum_monit_1_fs_sync;
pos_q_monit_1_o <= q_monit_1_fs_sync;
pos_y_monit_1_o <= y_monit_1_fs_sync;
pos_x_monit_1_o <= x_monit_1_fs_sync;
pos_monit_1_valid_o <= pos_monit_1_valid_fs_sync;
end rtl;
| lgpl-3.0 | ffc0792220e04a80a127a128c0ab35e3 | 0.449599 | 3.437057 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/text_mode_pkg.vhd | 1 | 2,515 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.colors_pkg.all;
use work.graphics_types_pkg.all;
use work.font_pkg.all;
package text_mode_pkg is
-- Constrain text coordinates to optmize resources usage
subtype text_coordinate_type is natural range 0 to 127;
constant TEXT_ROWS_COUNT: text_coordinate_type := 25;
constant TEXT_COLUMNS_COUNT: text_coordinate_type := 80;
-- Define color for all on screen text
constant TEXT_COLOR: palette_color_type := PC_WHITE;
-- Representation of a text mode string shown on the screen
type text_mode_string_type is record
x: text_coordinate_type;
y: text_coordinate_type;
text: string(1 to 16);
visible: boolean;
end record;
type text_mode_strings_type is array (natural range <>) of text_mode_string_type;
function character_at_x_y(x, y: text_coordinate_type; strings: text_mode_strings_type) return character;
function text_pixel_at_x_y(x, y: pixel_coordinate_type; strings: text_mode_strings_type) return boolean;
end;
package body text_mode_pkg is
function character_at_x_y(x, y: text_coordinate_type; strings: text_mode_strings_type) return character is
begin
for i in strings'range loop
if y = strings(i).y and x >= strings(i).x and x < strings(i).x + strings(i).text'length then
return strings(i).text(x - strings(i).x + 1);
end if;
end loop;
return ' ';
end;
-- Return true when
function text_pixel_at_x_y(x, y: pixel_coordinate_type; strings: text_mode_strings_type) return boolean is
variable char: character;
variable ascii_code: natural range 0 to 127;
variable glyph: glyph_type;
variable x_unsigned: unsigned(10 downto 0);
variable y_unsigned: unsigned(10 downto 0);
variable glyph_x: unsigned(2 downto 0);
variable glyph_y: unsigned(3 downto 0);
begin
char := character_at_x_y(x / FONT_WIDTH, y / FONT_HEIGHT, strings);
ascii_code := character'pos(char);
glyph := FONT_ROM(ascii_code);
x_unsigned := to_unsigned(x, x_unsigned'length);
y_unsigned := to_unsigned(y, y_unsigned'length);
glyph_x := x_unsigned(glyph_x'range);
glyph_y := y_unsigned(glyph_y'range);
return glyph(to_integer(glyph_y))(to_integer(glyph_x)) = '1';
end;
end; | unlicense | 22b9820bed1b226e3f74537e7d614069 | 0.62664 | 3.55226 | false | false | false | false |
lerwys/GitTest | models/blackboxes/fixed_dds.vhd | 2 | 4,899 | -------------------------------------------------------------------------------
-- Title : Fixed sin-cos DDS
-- Project :
-------------------------------------------------------------------------------
-- File : fixed_dds.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Fixed frequency phase and quadrature DDS for use in tuned DDCs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity fixed_dds is
generic (
g_number_of_points : natural := 148;
g_output_width : natural := 24;
g_dither : boolean := false;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram"
);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0)
);
end entity fixed_dds;
-------------------------------------------------------------------------------
architecture str of fixed_dds is
constant c_bus_size : natural := f_log2_size(g_number_of_points);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0);
component generic_simple_dpram is
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(c_bus_size-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_bus_size-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component generic_simple_dpram;
component lut_sweep is
generic (
g_bus_size : natural;
g_first_address : natural;
g_last_address : natural;
g_sweep_mode : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(c_bus_size-1 downto 0));
end component lut_sweep;
begin -- architecture str
cmp_sin_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_sin_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => sin_o
);
cmp_cos_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_cos_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => cos_o
);
cmp_sweep : lut_sweep
generic map (
g_bus_size => c_bus_size,
g_first_address => 0,
g_last_address => g_number_of_points-1,
g_sweep_mode => "sawtooth")
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
ce_i => ce_i,
address_o => cur_address);
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | d9c6a0bc348e027bc674eecf7b601de5 | 0.43764 | 3.594277 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/position_calc.vhd | 1 | 21,712 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dsp_cores_pkg.all;
entity position_calc is
generic (
g_pipeline_regs : integer := 8
);
port(
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
clk : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
clr : in std_logic; -- clear signal
del_sig_div_fofb_thres_i : in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i : in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i : in std_logic_vector(25 downto 0);
ksum_i : in std_logic_vector(24 downto 0);
kx_i : in std_logic_vector(24 downto 0);
ky_i : in std_logic_vector(24 downto 0);
dds_config_valid_ch0_i : in std_logic;
dds_config_valid_ch1_i : in std_logic;
dds_config_valid_ch2_i : in std_logic;
dds_config_valid_ch3_i : in std_logic;
dds_pinc_ch0_i : in std_logic_vector(29 downto 0);
dds_pinc_ch1_i : in std_logic_vector(29 downto 0);
dds_pinc_ch2_i : in std_logic_vector(29 downto 0);
dds_pinc_ch3_i : in std_logic_vector(29 downto 0);
dds_poff_ch0_i : in std_logic_vector(29 downto 0);
dds_poff_ch1_i : in std_logic_vector(29 downto 0);
dds_poff_ch2_i : in std_logic_vector(29 downto 0);
dds_poff_ch3_i : in std_logic_vector(29 downto 0);
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_q_ch01_incorrect_o : out std_logic;
tbt_decim_q_ch23_incorrect_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_q_01_missing_o : out std_logic;
fofb_decim_q_23_missing_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_cic_unexpected_o : out std_logic;
monit_cfir_incorrect_o : out std_logic;
monit_pfir_incorrect_o : out std_logic;
x_tbt_o : out std_logic_vector(25 downto 0);
x_tbt_valid_o : out std_logic;
y_tbt_o : out std_logic_vector(25 downto 0);
y_tbt_valid_o : out std_logic;
q_tbt_o : out std_logic_vector(25 downto 0);
q_tbt_valid_o : out std_logic;
sum_tbt_o : out std_logic_vector(25 downto 0);
sum_tbt_valid_o : out std_logic;
x_fofb_o : out std_logic_vector(25 downto 0);
x_fofb_valid_o : out std_logic;
y_fofb_o : out std_logic_vector(25 downto 0);
y_fofb_valid_o : out std_logic;
q_fofb_o : out std_logic_vector(25 downto 0);
q_fofb_valid_o : out std_logic;
sum_fofb_o : out std_logic_vector(25 downto 0);
sum_fofb_valid_o : out std_logic;
x_monit_o : out std_logic_vector(25 downto 0);
x_monit_valid_o : out std_logic;
y_monit_o : out std_logic_vector(25 downto 0);
y_monit_valid_o : out std_logic;
q_monit_o : out std_logic_vector(25 downto 0);
q_monit_valid_o : out std_logic;
sum_monit_o : out std_logic_vector(25 downto 0);
sum_monit_valid_o : out std_logic;
x_monit_1_o : out std_logic_vector(25 downto 0);
x_monit_1_valid_o : out std_logic;
y_monit_1_o : out std_logic_vector(25 downto 0);
y_monit_1_valid_o : out std_logic;
q_monit_1_o : out std_logic_vector(25 downto 0);
q_monit_1_valid_o : out std_logic;
sum_monit_1_o : out std_logic_vector(25 downto 0);
sum_monit_1_valid_o : out std_logic;
monit_pos_1_incorrect_o : out std_logic;
-- Clock drivers for various rates
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic
);
end position_calc;
architecture rtl of position_calc is
signal ce : std_logic;
signal ce_clr : std_logic;
signal clk_ce_1 : std_logic;
signal clk_ce_1112 : std_logic;
signal clk_ce_1390000 : std_logic;
signal clk_ce_2 : std_logic;
signal clk_ce_2224 : std_logic;
signal clk_ce_22240000 : std_logic;
signal clk_ce_2780000 : std_logic;
signal clk_ce_35 : std_logic;
signal clk_ce_5000 : std_logic;
signal clk_ce_556 : std_logic;
signal clk_ce_5560000 : std_logic;
signal clk_ce_70 : std_logic;
begin
ce <= '1';
--ce_clr <= '0';
ce_clr <= clr;
-- FIXME: fix CE names. They don't match the correct ones!
cmp_default_clock_driver : default_clock_driver
generic map(
pipeline_regs => g_pipeline_regs
)
port map(
sysce => ce,
sysce_clr => ce_clr,
sysclk => clk,
ce_1 => clk_ce_1_o,
ce_10000 => open,
ce_1120 => clk_ce_1112_o,
ce_1400000 => clk_ce_1390000_o,
ce_2 => clk_ce_2_o,
ce_2240 => clk_ce_2224_o,
ce_22400000 => clk_ce_22240000_o,
ce_224000000 => clk_ce_222400000_o,
ce_2500 => open,
ce_2800000 => clk_ce_2780000_o,
ce_35 => clk_ce_35_o,
ce_4480 => open,
ce_44800000 => open,
ce_5000 => clk_ce_5000_o,
ce_560 => clk_ce_556_o,
ce_5600000 => clk_ce_5560000_o,
ce_56000000 => open,
ce_70 => clk_ce_70_o,
ce_logic_1 => open,
ce_logic_1400000 => open,
ce_logic_2240 => open,
ce_logic_22400000 => open,
ce_logic_2800000 => open,
ce_logic_560 => open,
ce_logic_5600000 => open,
ce_logic_70 => open,
clk_1 => open,
clk_10000 => open,
clk_1120 => open,
clk_1400000 => open,
clk_2 => open,
clk_2240 => open,
clk_22400000 => open,
clk_224000000 => open,
clk_2500 => open,
clk_2800000 => open,
clk_35 => open,
clk_4480 => open,
clk_44800000 => open,
clk_5000 => open,
clk_560 => open,
clk_5600000 => open,
clk_56000000 => open,
clk_70 => open
);
cmp_ddc_bpm_476_066_cw : ddc_bpm_476_066_cw
generic map (
pipeline_regs => g_pipeline_regs
)
port map (
adc_ch0_i => adc_ch0_i,
adc_ch1_i => adc_ch1_i,
adc_ch2_i => adc_ch2_i,
adc_ch3_i => adc_ch3_i,
ce => ce,
ce_clr => ce_clr,
clk => clk,
del_sig_div_fofb_thres_i => del_sig_div_fofb_thres_i,
del_sig_div_monit_thres_i => del_sig_div_monit_thres_i,
del_sig_div_tbt_thres_i => del_sig_div_tbt_thres_i,
ksum_i => ksum_i,
kx_i => kx_i,
ky_i => ky_i,
dds_config_valid_ch0_i => dds_config_valid_ch0_i,
dds_config_valid_ch1_i => dds_config_valid_ch1_i,
dds_config_valid_ch2_i => dds_config_valid_ch2_i,
dds_config_valid_ch3_i => dds_config_valid_ch3_i,
dds_pinc_ch0_i => dds_pinc_ch0_i,
dds_pinc_ch1_i => dds_pinc_ch1_i,
dds_pinc_ch2_i => dds_pinc_ch2_i,
dds_pinc_ch3_i => dds_pinc_ch3_i,
dds_poff_ch0_i => dds_poff_ch0_i,
dds_poff_ch1_i => dds_poff_ch1_i,
dds_poff_ch2_i => dds_poff_ch2_i,
dds_poff_ch3_i => dds_poff_ch3_i,
adc_ch0_dbg_data_o => adc_ch0_dbg_data_o,
adc_ch1_dbg_data_o => adc_ch1_dbg_data_o,
adc_ch2_dbg_data_o => adc_ch2_dbg_data_o,
adc_ch3_dbg_data_o => adc_ch3_dbg_data_o,
bpf_ch0_o => bpf_ch0_o,
bpf_ch1_o => bpf_ch1_o,
bpf_ch2_o => bpf_ch2_o,
bpf_ch3_o => bpf_ch3_o,
mix_ch0_i_o => mix_ch0_i_o,
mix_ch0_q_o => mix_ch0_q_o,
mix_ch1_i_o => mix_ch1_i_o,
mix_ch1_q_o => mix_ch1_q_o,
mix_ch2_i_o => mix_ch2_i_o,
mix_ch2_q_o => mix_ch2_q_o,
mix_ch3_i_o => mix_ch3_i_o,
mix_ch3_q_o => mix_ch3_q_o,
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o,
tbt_decim_ch01_incorrect_o => tbt_decim_q_ch01_incorrect_o,
tbt_decim_ch23_incorrect_o => tbt_decim_q_ch23_incorrect_o,
tbt_amp_ch0_o => tbt_amp_ch0_o,
tbt_amp_ch1_o => tbt_amp_ch1_o,
tbt_amp_ch2_o => tbt_amp_ch2_o,
tbt_amp_ch3_o => tbt_amp_ch3_o,
tbt_pha_ch0_o => tbt_pha_ch0_o,
tbt_pha_ch1_o => tbt_pha_ch1_o,
tbt_pha_ch2_o => tbt_pha_ch2_o,
tbt_pha_ch3_o => tbt_pha_ch3_o,
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o,
cic_fofb_q_01_missing_o => fofb_decim_q_01_missing_o,
cic_fofb_q_23_missing_o => fofb_decim_q_23_missing_o,
fofb_amp_ch0_o => fofb_amp_ch0_o,
fofb_amp_ch1_o => fofb_amp_ch1_o,
fofb_amp_ch2_o => fofb_amp_ch2_o,
fofb_amp_ch3_o => fofb_amp_ch3_o,
fofb_pha_ch0_o => fofb_pha_ch0_o,
fofb_pha_ch1_o => fofb_pha_ch1_o,
fofb_pha_ch2_o => fofb_pha_ch2_o,
fofb_pha_ch3_o => fofb_pha_ch3_o,
monit_amp_ch0_o => monit_amp_ch0_o,
monit_amp_ch1_o => monit_amp_ch1_o,
monit_amp_ch2_o => monit_amp_ch2_o,
monit_amp_ch3_o => monit_amp_ch3_o,
monit_cic_unexpected_o => monit_cic_unexpected_o,
monit_cfir_incorrect_o => monit_cfir_incorrect_o,
monit_pfir_incorrect_o => monit_pfir_incorrect_o,
x_tbt_o => x_tbt_o,
x_tbt_valid_o => x_tbt_valid_o,
y_tbt_o => y_tbt_o,
y_tbt_valid_o => y_tbt_valid_o,
q_tbt_o => q_tbt_o,
q_tbt_valid_o => q_tbt_valid_o,
sum_tbt_o => sum_tbt_o,
sum_tbt_valid_o => sum_tbt_valid_o,
x_fofb_o => x_fofb_o,
x_fofb_valid_o => x_fofb_valid_o,
y_fofb_o => y_fofb_o,
y_fofb_valid_o => y_fofb_valid_o,
q_fofb_o => q_fofb_o,
q_fofb_valid_o => q_fofb_valid_o,
sum_fofb_o => sum_fofb_o,
sum_fofb_valid_o => sum_fofb_valid_o,
x_monit_o => x_monit_o,
x_monit_valid_o => x_monit_valid_o,
y_monit_o => y_monit_o,
y_monit_valid_o => y_monit_valid_o,
q_monit_o => q_monit_o,
q_monit_valid_o => q_monit_valid_o,
sum_monit_o => sum_monit_o,
sum_monit_valid_o => sum_monit_valid_o,
x_monit_1_o => x_monit_1_o,
x_monit_1_valid_o => x_monit_1_valid_o,
y_monit_1_o => y_monit_1_o,
y_monit_1_valid_o => y_monit_1_valid_o,
q_monit_1_o => q_monit_1_o,
q_monit_1_valid_o => q_monit_1_valid_o,
sum_monit_1_o => sum_monit_1_o,
sum_monit_1_valid_o => sum_monit_1_valid_o,
monit_pos_1_incorrect_o => monit_pos_1_incorrect_o
);
end rtl;
| lgpl-3.0 | efe679c91900df7906c7abd07cac5ee4 | 0.377902 | 3.786536 | false | false | false | false |
wltr/common-vhdl | interfaces/max5541_interface/src/rtl/max5541_interface.vhd | 1 | 4,541 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Send data to MAX5541 DAC.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity max5541_interface is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
data_i : in std_ulogic_vector(15 downto 0);
data_en_i : in std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- MAX5541 signals
cs_o : out std_ulogic;
sclk_o : out std_ulogic;
din_o : out std_ulogic);
end entity max5541_interface;
architecture rtl of max5541_interface is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(data_i'length);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter maximum value
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, data_i'length - 1);
-- FSM states
type state_t is (IDLE, CLK_HIGH, CLK_LOW);
-- FSM registers
type reg_t is record
state : state_t;
lfsr : std_ulogic_vector(len_c - 1 downto 0);
count : std_ulogic;
data : std_ulogic_vector(15 downto 0);
clk : std_ulogic;
done : std_ulogic;
end record reg_t;
-- FSM initial state
constant init_c : reg_t := (
state => IDLE,
lfsr => seed_c,
count => '0',
data => (others => '0'),
clk => '0',
done => '0');
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
signal busy : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= busy;
done_o <= reg.done;
cs_o <= not busy;
sclk_o <= reg.clk;
din_o <= reg.data(reg.data'high);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- FSM registering
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
-- FSM combinatorics
comb : process(reg, data_i, data_en_i) is
begin -- process comb
-- Defaults
next_reg <= reg;
busy <= '1';
next_reg.done <= init_c.done;
case reg.state is
when IDLE =>
busy <= '0';
if data_en_i = '1' then
next_reg.data <= data_i;
next_reg.state <= CLK_HIGH;
end if;
when CLK_HIGH =>
if reg.count = '1' then
next_reg.clk <= '1';
next_reg.count <= '0';
next_reg.state <= CLK_LOW;
else
next_reg.count <= '1';
end if;
when CLK_LOW =>
if reg.count = '1' then
if reg.lfsr = max_c then
next_reg <= init_c;
next_reg.done <= '1';
else
next_reg.clk <= '0';
next_reg.count <= '0';
next_reg.state <= CLK_HIGH;
next_reg.data <= reg.data(reg.data'high - 1 downto reg.data'low) & '0';
next_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
else
next_reg.count <= '1';
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | 837d963ea6b7f835f44e0503cb86ce76 | 0.412464 | 4.23206 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_result_accumulator.vhd | 1 | 4,111 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Accumulate filter results.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
entity ads1281_result_accumulator is
generic (
-- Number of results to be accumulated
num_results_g : positive := 10);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Filter results
result_i : in std_ulogic_vector(23 downto 0);
result_en_i : in std_ulogic;
-- Accumulated results
result_o : out std_ulogic_vector(27 downto 0);
result_en_o : out std_ulogic);
end entity ads1281_result_accumulator;
architecture rtl of ads1281_result_accumulator is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(num_results_g);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter maximal value
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, num_results_g - 1);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : std_ulogic_vector(len_c - 1 downto 0);
signal sum : signed(27 downto 0);
signal sum_en : std_ulogic;
signal num : std_ulogic;
signal carry : std_ulogic;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal sum_0 : signed(14 downto 0);
signal sum_1 : signed(14 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
result_o <= std_ulogic_vector(sum);
result_en_o <= sum_en;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
sum_0 <= signed('0' & std_ulogic_vector(sum(13 downto 0))) + signed('0' & result_i(13 downto 0));
sum_1 <= signed(std_ulogic_vector(sum(27 downto 14)) & carry) + signed(result_i(23 downto 14) & '1');
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= seed_c;
sum <= to_signed(0, sum'length);
sum_en <= '0';
num <= '0';
carry <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
sum_en <= '0';
if rst_syn_i = '1' then
reset;
else
if result_en_i = '1' then
sum(13 downto 0) <= sum_0(13 downto 0);
carry <= sum_0(14);
num <= '1';
elsif sum_en = '0' and num = '1' then
sum(27 downto 14) <= sum_1(14 downto 1);
carry <= '0';
num <= '0';
if count = max_c then
sum_en <= '1';
else
count <= lfsr_shift(count);
end if;
elsif sum_en = '1' then
reset;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 1eb2d8769a8839d1ea0831476b266356 | 0.397713 | 4.639955 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/adventure_demo/de2_adventure_demo_top.vhd | 1 | 2,781 | library ieee;
use ieee.std_logic_1164.all;
-- VAGE (VHDL Advanced Game Engine) demo using the 'Adventure' game demo and
-- the Altera DE2 board as a hardware platform. The purpose of this file is
-- simply to instantiate the game top entity. It should not contain any game-
-- related code. This is also a perfect place for vendor-specific and board-
-- specific code, such as PLLs.
entity de2_adventure_demo_top is
-- Port names as defined in the standard DE2 settings file.
port (
-- 50 MHz clock provided by the DE2 board
clock_50: in std_logic;
-- Input toggle switches
sw: in std_logic_vector(17 downto 0);
-- Input push-button switches, active low
key: in std_logic_vector(3 downto 0);
-- Green leds
ledg: out std_logic_vector(7 downto 0);
-- Pixel clock for the ADV7123 video DAC
vga_clk: out std_logic;
-- VGA blank signal, high outside of active area
vga_blank: out std_logic;
-- VGA horizontal sync, pulsed low between lines
vga_hs: out std_logic;
-- VGA vertical sync, pulsed low between frames
vga_vs: out std_logic;
-- Composite sync for the ADV7123; if not used, should be tied low
vga_sync: out std_logic;
-- VGA red channel output
vga_r: out std_logic_vector(9 downto 0);
-- VGA green channel output
vga_g: out std_logic_vector(9 downto 0);
-- VGA blue channel output
vga_b: out std_logic_vector(9 downto 0)
);
end;
architecture rtl of de2_adventure_demo_top is
-- Component declaration for the PLL used to generate the 25 MHz pixel
-- clock from the board 50 MHz system clock
component video_pll
port(
inclk0: in std_logic := '0';
c0: out std_logic
);
end component;
signal vga_pll_clock_out: std_logic;
begin
game: entity work.adventure_demo_top
port map(
clock_50_Mhz => clock_50,
reset => sw(17),
debug_bits => ledg,
vga_clock_in => vga_pll_clock_out,
vga_clock_out => vga_clk,
vga_blank => vga_blank,
vga_n_hsync => vga_hs,
vga_n_vsync => vga_vs,
vga_n_sync => vga_sync,
vga_red => vga_r,
vga_green => vga_g,
vga_blue => vga_b,
input_switches => sw(1 downto 0),
input_buttons => not key
);
-- Instantiate a PLL to generate the pixel clock frequency (~25 MHZ),
-- using the DE2 50Mhz clock as input
video_PLL_inst : video_PLL port map (
inclk0 => clock_50,
c0 => vga_pll_clock_out
);
end; | unlicense | 53168a80d766b91b7957a42be60988c1 | 0.574973 | 3.905899 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/nonleaf_results.vhd | 1 | 484,765 | library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF/zero_filling1"
entity zero_filling1_entity_d0ac9899b1 is
port (
in1: in std_logic_vector(15 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end zero_filling1_entity_d0ac9899b1;
architecture structural of zero_filling1_entity_d0ac9899b1 is
signal concat_y_net: std_logic_vector(23 downto 0);
signal constant_op_net: std_logic_vector(7 downto 0);
signal register1_q_net_x0: std_logic_vector(15 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(15 downto 0);
begin
register1_q_net_x0 <= in1;
out1 <= reinterpret2_output_port_net_x0;
concat: entity work.concat_cd3162dc0d
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
constant_x0: entity work.constant_91ef1678ca
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
reinterpret: entity work.reinterpret_7025463ea8
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register1_q_net_x0,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_f21e7f2ddf
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => constant_op_net,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => concat_y_net,
output_port => reinterpret2_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF"
entity bpf_entity_d31c4af409 is
port (
din_ch0: in std_logic_vector(15 downto 0);
din_ch1: in std_logic_vector(15 downto 0);
din_ch2: in std_logic_vector(15 downto 0);
din_ch3: in std_logic_vector(15 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end bpf_entity_d31c4af409;
architecture structural of bpf_entity_d31c4af409 is
signal register1_q_net_x1: std_logic_vector(15 downto 0);
signal register2_q_net_x1: std_logic_vector(15 downto 0);
signal register3_q_net_x1: std_logic_vector(15 downto 0);
signal register_q_net_x1: std_logic_vector(15 downto 0);
signal reinterpret2_output_port_net_x4: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x5: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x6: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x7: std_logic_vector(23 downto 0);
begin
register_q_net_x1 <= din_ch0;
register1_q_net_x1 <= din_ch1;
register2_q_net_x1 <= din_ch2;
register3_q_net_x1 <= din_ch3;
dout_ch0 <= reinterpret2_output_port_net_x7;
dout_ch1 <= reinterpret2_output_port_net_x4;
dout_ch2 <= reinterpret2_output_port_net_x5;
dout_ch3 <= reinterpret2_output_port_net_x6;
zero_filling1_d0ac9899b1: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register1_q_net_x1,
out1 => reinterpret2_output_port_net_x4
);
zero_filling2_d7e27e9bae: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register2_q_net_x1,
out1 => reinterpret2_output_port_net_x5
);
zero_filling3_1ae3b6c91e: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register3_q_net_x1,
out1 => reinterpret2_output_port_net_x6
);
zero_filling4_6d7b2d0c57: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register_q_net_x1,
out1 => reinterpret2_output_port_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub/TDM_dds_ch01_cosine"
entity tdm_dds_ch01_cosine_entity_4b8bfc9243 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
rst: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_dds_ch01_cosine_entity_4b8bfc9243;
architecture structural of tdm_dds_ch01_cosine_entity_4b8bfc9243 is
signal black_box_cos_o_net_x0: std_logic_vector(23 downto 0);
signal ce_1_sg_x0: std_logic;
signal ce_2_sg_x0: std_logic;
signal ce_logic_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal clk_2_sg_x0: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant11_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register4_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x0 <= ce_1;
ce_2_sg_x0 <= ce_2;
ce_logic_1_sg_x0 <= ce_logic_1;
clk_1_sg_x0 <= clk_1;
clk_2_sg_x0 <= clk_2;
black_box_cos_o_net_x0 <= din_ch0;
constant11_op_net_x0 <= rst;
dout <= register_q_net_x0;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x0,
clk => clk_1_sg_x0,
d => register2_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => register2_q_net,
d1 => register3_q_net,
sel(0) => register4_q_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op(0) => mux_sel1_op_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch0_q_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch1_q_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register4_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub"
entity dds_sub_entity_a4b6b880f6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_01_cosine: out std_logic_vector(23 downto 0);
dds_01_sine: out std_logic_vector(23 downto 0);
dds_23_cosine: out std_logic_vector(23 downto 0);
dds_23_sine: out std_logic_vector(23 downto 0)
);
end dds_sub_entity_a4b6b880f6;
architecture structural of dds_sub_entity_a4b6b880f6 is
signal black_box_cos_o_net_x1: std_logic_vector(23 downto 0);
signal black_box_sin_o_net_x1: std_logic_vector(23 downto 0);
signal ce_1_sg_x4: std_logic;
signal ce_2_sg_x4: std_logic;
signal ce_logic_1_sg_x4: std_logic;
signal clk_1_sg_x4: std_logic;
signal clk_2_sg_x4: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant16_op_net_x0: std_logic;
signal constant17_op_net_x0: std_logic;
signal constant3_op_net: std_logic;
signal constant7_op_net_x0: std_logic;
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
begin
ce_1_sg_x4 <= ce_1;
ce_2_sg_x4 <= ce_2;
ce_logic_1_sg_x4 <= ce_logic_1;
clk_1_sg_x4 <= clk_1;
clk_2_sg_x4 <= clk_2;
dds_01_cosine <= register_q_net_x4;
dds_01_sine <= register_q_net_x5;
dds_23_cosine <= register_q_net_x6;
dds_23_sine <= register_q_net_x7;
black_box: entity work.fixed_dds
generic map (
g_cos_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos.ram",
g_dither => false,
g_number_of_points => 148,
g_output_width => 24,
g_sin_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin.ram"
)
port map (
ce_i => ce_2_sg_x4,
clk_i => clk_2_sg_x4,
rst_n_i => constant3_op_net,
cos_o => black_box_cos_o_net_x1,
sin_o => black_box_sin_o_net_x1
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant16: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant16_op_net_x0
);
constant17: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant17_op_net_x0
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant7: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant7_op_net_x0
);
tdm_dds_ch01_cosine_4b8bfc9243: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant11_op_net_x0,
dout => register_q_net_x4
);
tdm_dds_ch01_sine_1129eb9762: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant7_op_net_x0,
dout => register_q_net_x5
);
tdm_dds_ch23_cosine_398d5cee32: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant16_op_net_x0,
dout => register_q_net_x6
);
tdm_dds_ch23_sine_782ff6a42a: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant17_op_net_x0,
dout => register_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch/TDDM_fofb_amp0"
entity tddm_fofb_amp0_entity_fd74c6ad6e is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp0_entity_fd74c6ad6e;
architecture structural of tddm_fofb_amp0_entity_fd74c6ad6e is
signal assert2_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x0: std_logic;
signal ce_1120_sg_x0: std_logic;
signal ce_2240_sg_x0: std_logic;
signal clk_1120_sg_x0: std_logic;
signal clk_2240_sg_x0: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x0 <= ce_1120;
ce_2240_sg_x0 <= ce_2240;
assert3_dout_net_x0 <= ch_in;
clk_1120_sg_x0 <= clk_1120;
clk_2240_sg_x0 <= clk_2240;
assert2_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant1_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch"
entity tddm_fofb_amp_4ch_entity_2cc521a83f is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp_4ch_entity_2cc521a83f;
architecture structural of tddm_fofb_amp_4ch_entity_2cc521a83f is
signal assert2_dout_net_x2: std_logic_vector(23 downto 0);
signal assert2_dout_net_x3: std_logic_vector(23 downto 0);
signal assert3_dout_net_x2: std_logic;
signal assert3_dout_net_x3: std_logic;
signal ce_1120_sg_x2: std_logic;
signal ce_2240_sg_x2: std_logic;
signal clk_1120_sg_x2: std_logic;
signal clk_2240_sg_x2: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
assert2_dout_net_x2 <= amp_in0;
assert2_dout_net_x3 <= amp_in1;
ce_1120_sg_x2 <= ce_1120;
ce_2240_sg_x2 <= ce_2240;
assert3_dout_net_x2 <= ch_in0;
assert3_dout_net_x3 <= ch_in1;
clk_1120_sg_x2 <= clk_1120;
clk_2240_sg_x2 <= clk_2240;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_fofb_amp0_fd74c6ad6e: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x2,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x2,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_amp1_61cbc8ec65: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x3,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_b60a69fd9b is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_b60a69fd9b;
architecture structural of tddm_tbt_cordic1_entity_b60a69fd9b is
signal assert1_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x4: std_logic;
signal ce_1120_sg_x4: std_logic;
signal ce_2240_sg_x4: std_logic;
signal clk_1120_sg_x4: std_logic;
signal clk_2240_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x4 <= ce_1120;
ce_2240_sg_x4 <= ce_2240;
assert3_dout_net_x4 <= ch_in;
clk_1120_sg_x4 <= clk_1120;
clk_2240_sg_x4 <= clk_2240;
assert1_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant1_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0"
entity tddm_tbt_cordic0_entity_38de3613fe is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_cordic_ch_in: in std_logic;
fofb_cordic_din: in std_logic_vector(23 downto 0);
fofb_cordic_pin: in std_logic_vector(23 downto 0);
fofb_cordic_data0_out: out std_logic_vector(23 downto 0);
fofb_cordic_data1_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase0_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic0_entity_38de3613fe;
architecture structural of tddm_tbt_cordic0_entity_38de3613fe is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x4: std_logic_vector(23 downto 0);
signal assert3_dout_net_x5: std_logic;
signal ce_1120_sg_x5: std_logic;
signal ce_2240_sg_x5: std_logic;
signal clk_1120_sg_x5: std_logic;
signal clk_2240_sg_x5: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x5 <= ce_1120;
ce_2240_sg_x5 <= ce_2240;
clk_1120_sg_x5 <= clk_1120;
clk_2240_sg_x5 <= clk_2240;
assert3_dout_net_x5 <= fofb_cordic_ch_in;
assert2_dout_net_x4 <= fofb_cordic_din;
assert1_dout_net_x1 <= fofb_cordic_pin;
fofb_cordic_data0_out <= down_sample2_q_net_x2;
fofb_cordic_data1_out <= down_sample1_q_net_x2;
fofb_cordic_phase0_out <= down_sample2_q_net_x3;
fofb_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_fofb_cordic0_int_516d0c2a22: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert2_dout_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_cordic1_b60a69fd9b: entity work.tddm_tbt_cordic1_entity_b60a69fd9b
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert1_dout_net_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC"
entity fofb_cordic_entity_fad57e49ce is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_tbt_cordic0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_fad57e49ce;
architecture structural of fofb_cordic_entity_fad57e49ce is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x5: std_logic_vector(23 downto 0);
signal assert3_dout_net_x6: std_logic;
signal ce_1120_sg_x6: std_logic;
signal ce_1_sg_x5: std_logic;
signal ce_2240_sg_x6: std_logic;
signal clk_1120_sg_x6: std_logic;
signal clk_1_sg_x5: std_logic;
signal clk_2240_sg_x6: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x5 <= ce_1;
ce_1120_sg_x6 <= ce_1120;
ce_2240_sg_x6 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x5 <= clk_1;
clk_1120_sg_x6 <= clk_1120;
clk_2240_sg_x6 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x5;
ch_out <= assert3_dout_net_x6;
tddm_tbt_cordic0 <= down_sample1_q_net_x4;
tddm_tbt_cordic0_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic0_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic0_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x5
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x6
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic0_38de3613fe: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x6,
ce_2240 => ce_2240_sg_x6,
clk_1120 => clk_1120_sg_x6,
clk_2240 => clk_2240_sg_x6,
fofb_cordic_ch_in => assert3_dout_net_x6,
fofb_cordic_din => assert2_dout_net_x5,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/Reg"
entity reg_entity_cf7aa296b2 is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end reg_entity_cf7aa296b2;
architecture structural of reg_entity_cf7aa296b2 is
signal ce_1120_sg_x7: std_logic;
signal clk_1120_sg_x7: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
begin
ce_1120_sg_x7 <= ce_1120;
clk_1120_sg_x7 <= clk_1120;
register_q_net_x2 <= din;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 23,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
d => convert_dout_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x2,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/TDDM_fofb_cic0"
entity tddm_fofb_cic0_entity_6b909292ff is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_ch_in: in std_logic;
fofb_i_in: in std_logic_vector(23 downto 0);
fofb_q_in: in std_logic_vector(23 downto 0);
cic_fofb_ch0_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch0_q_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_fofb_cic0_entity_6b909292ff;
architecture structural of tddm_fofb_cic0_entity_6b909292ff is
signal ce_1120_sg_x11: std_logic;
signal ce_2240_sg_x9: std_logic;
signal clk_1120_sg_x11: std_logic;
signal clk_2240_sg_x9: std_logic;
signal delay_q_net_x3: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x11 <= ce_1120;
ce_2240_sg_x9 <= ce_2240;
clk_1120_sg_x11 <= clk_1120;
clk_2240_sg_x9 <= clk_2240;
delay_q_net_x3 <= fofb_ch_in;
register_q_net_x4 <= fofb_i_in;
register_q_net_x3 <= fofb_q_in;
cic_fofb_ch0_i_out <= down_sample2_q_net_x2;
cic_fofb_ch0_q_out <= down_sample2_q_net_x3;
cic_fofb_ch1_i_out <= down_sample1_q_net_x2;
cic_fofb_ch1_q_out <= down_sample1_q_net_x3;
tddm_fofb_cic0_i_06b84397ec: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_cic0_q_a6a1d7c301: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg"
entity reg_entity_71dd029fba is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0)
);
end reg_entity_71dd029fba;
architecture structural of reg_entity_71dd029fba is
signal ce_1120_sg_x12: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x12: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x12 <= ce_1120;
clk_1120_sg_x12 <= clk_1120;
cic_fofb_q_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_q_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x3;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
d => convert_dout_net,
en(0) => cic_fofb_q_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x3
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_q_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg1"
entity reg1_entity_b079f30e3c is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end reg1_entity_b079f30e3c;
architecture structural of reg1_entity_b079f30e3c is
signal ce_1120_sg_x13: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x13: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register1_q_net_x2: std_logic;
signal register_q_net_x4: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x13 <= ce_1120;
clk_1120_sg_x13 <= clk_1120;
cic_fofb_i_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_i_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x4;
valid_out <= register1_q_net_x2;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d => convert_dout_net,
en(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x4
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_i_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb"
entity cic_fofb_entity_2ed6a6e00c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb_q_x0: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end cic_fofb_entity_2ed6a6e00c;
architecture structural of cic_fofb_entity_2ed6a6e00c is
signal ce_1120_sg_x14: std_logic;
signal ce_1_sg_x6: std_logic;
signal ce_logic_1_sg_x5: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tuser_chan_out_net: std_logic;
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x0: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x14: std_logic;
signal clk_1_sg_x6: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay_q_net_x4: std_logic;
signal register1_q_net_x3: std_logic;
signal register3_q_net_x0: std_logic;
signal register4_q_net_x0: std_logic_vector(23 downto 0);
signal register5_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(24 downto 0);
signal register_q_net_x6: std_logic_vector(24 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x6 <= ce_1;
ce_1120_sg_x14 <= ce_1120;
ce_logic_1_sg_x5 <= ce_logic_1;
register3_q_net_x0 <= ch_in;
clk_1_sg_x6 <= clk_1;
clk_1120_sg_x14 <= clk_1120;
register4_q_net_x0 <= i_in;
register5_q_net_x0 <= q_in;
ch_out <= delay_q_net_x4;
cic_fofb_q_x0 <= cic_fofb_q_event_tlast_missing_net_x0;
i_out <= register_q_net_x6;
q_out <= register_q_net_x5;
valid_out <= register1_q_net_x3;
cic_fofb_i: entity work.xlcic_compiler_2d3b496704eca3daaae85383d488a908
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register4_q_net_x0,
s_axis_data_tlast => relational2_op_net,
m_axis_data_tdata_data => cic_fofb_i_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => cic_fofb_i_m_axis_data_tvalid_net_x0
);
cic_fofb_q: entity work.xlcic_compiler_2d3b496704eca3daaae85383d488a908
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register5_q_net_x0,
s_axis_data_tlast => relational2_op_net,
event_tlast_missing => cic_fofb_q_event_tlast_missing_net_x0,
m_axis_data_tdata_data => cic_fofb_q_m_axis_data_tdata_data_net_x0,
m_axis_data_tvalid => cic_fofb_q_m_axis_data_tvalid_net_x0
);
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1120_sg_x14,
clk => clk_1120_sg_x14,
d(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q(0) => delay_q_net_x4
);
reg1_b079f30e3c: entity work.reg1_entity_b079f30e3c
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_i_m_axis_data_tdata_data_net_x0,
en => cic_fofb_i_m_axis_data_tvalid_net_x0,
dout => register_q_net_x6,
valid_out => register1_q_net_x3
);
reg_71dd029fba: entity work.reg_entity_71dd029fba
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_q_m_axis_data_tdata_data_net_x0,
en => cic_fofb_q_m_axis_data_tvalid_net_x0,
dout => register_q_net_x5
);
relational2: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x0,
b => constant1_op_net,
ce => ce_1_sg_x6,
clk => clk_1_sg_x6,
clr => '0',
op(0) => relational2_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp"
entity fofb_amp_entity_078cdb1842 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_078cdb1842;
architecture structural of fofb_amp_entity_078cdb1842 is
signal ce_1120_sg_x15: std_logic;
signal ce_1_sg_x7: std_logic;
signal ce_2240_sg_x10: std_logic;
signal ce_logic_1_sg_x6: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x15: std_logic;
signal clk_1_sg_x7: std_logic;
signal clk_2240_sg_x10: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x7 <= ce_1;
ce_1120_sg_x15 <= ce_1120;
ce_2240_sg_x10 <= ce_2240;
ce_logic_1_sg_x6 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x7 <= clk_1;
clk_1120_sg_x15 <= clk_1120;
clk_2240_sg_x10 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic0 <= down_sample1_q_net_x4;
tddm_fofb_cic0_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic0_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic0_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_2ed6a6e00c: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x7,
ce_1120 => ce_1120_sg_x15,
ce_logic_1 => ce_logic_1_sg_x6,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x7,
clk_1120 => clk_1120_sg_x15,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_6375e37e24: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_cf7aa296b2: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic0_6b909292ff: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x15,
ce_2240 => ce_2240_sg_x10,
clk_1120 => clk_1120_sg_x15,
clk_2240 => clk_2240_sg_x10,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0"
entity fofb_amp0_entity_95b23bfc2c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp0_entity_95b23bfc2c;
architecture structural of fofb_amp0_entity_95b23bfc2c is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x16: std_logic;
signal ce_1_sg_x8: std_logic;
signal ce_2240_sg_x11: std_logic;
signal ce_logic_1_sg_x7: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x16: std_logic;
signal clk_1_sg_x8: std_logic;
signal clk_2240_sg_x11: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x8 <= ce_1;
ce_1120_sg_x16 <= ce_1120;
ce_2240_sg_x11 <= ce_2240;
ce_logic_1_sg_x7 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x8 <= clk_1;
clk_1120_sg_x16 <= clk_1120;
clk_2240_sg_x11 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_078cdb1842: entity work.fofb_amp_entity_078cdb1842
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ce_logic_1 => ce_logic_1_sg_x7,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic0 => down_sample1_q_net_x10,
tddm_fofb_cic0_x0 => down_sample2_q_net_x10,
tddm_fofb_cic0_x1 => down_sample1_q_net_x11,
tddm_fofb_cic0_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_fad57e49ce: entity work.fofb_cordic_entity_fad57e49ce
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
tddm_tbt_cordic0 => down_sample1_q_net_x8,
tddm_tbt_cordic0_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic0_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic0_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_CORDIC"
entity fofb_cordic_entity_e4c0810ec7 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_fofb_cordic1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_e4c0810ec7;
architecture structural of fofb_cordic_entity_e4c0810ec7 is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x20: std_logic;
signal ce_1_sg_x9: std_logic;
signal ce_2240_sg_x15: std_logic;
signal clk_1120_sg_x20: std_logic;
signal clk_1_sg_x9: std_logic;
signal clk_2240_sg_x15: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x9 <= ce_1;
ce_1120_sg_x20 <= ce_1120;
ce_2240_sg_x15 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x9 <= clk_1;
clk_1120_sg_x20 <= clk_1120;
clk_2240_sg_x15 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
tddm_fofb_cordic1 <= down_sample1_q_net_x4;
tddm_fofb_cordic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cordic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cordic1_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x6
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x7
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_fofb_cordic1_77b64089dc: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x20,
ce_2240 => ce_2240_sg_x15,
clk_1120 => clk_1120_sg_x20,
clk_2240 => clk_2240_sg_x15,
fofb_cordic_ch_in => assert3_dout_net_x7,
fofb_cordic_din => assert2_dout_net_x6,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_amp"
entity fofb_amp_entity_f70fcc8ed9 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_f70fcc8ed9;
architecture structural of fofb_amp_entity_f70fcc8ed9 is
signal ce_1120_sg_x29: std_logic;
signal ce_1_sg_x11: std_logic;
signal ce_2240_sg_x19: std_logic;
signal ce_logic_1_sg_x9: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x29: std_logic;
signal clk_1_sg_x11: std_logic;
signal clk_2240_sg_x19: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x11 <= ce_1;
ce_1120_sg_x29 <= ce_1120;
ce_2240_sg_x19 <= ce_2240;
ce_logic_1_sg_x9 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x11 <= clk_1;
clk_1120_sg_x29 <= clk_1120;
clk_2240_sg_x19 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic1 <= down_sample1_q_net_x4;
tddm_fofb_cic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic1_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_579902476d: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x11,
ce_1120 => ce_1120_sg_x29,
ce_logic_1 => ce_logic_1_sg_x9,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x11,
clk_1120 => clk_1120_sg_x29,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_a06a1c33b5: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_b669a3b118: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic1_4a640315a5: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x29,
ce_2240 => ce_2240_sg_x19,
clk_1120 => clk_1120_sg_x29,
clk_2240 => clk_2240_sg_x19,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1"
entity fofb_amp1_entity_a049562dde is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp1_entity_a049562dde;
architecture structural of fofb_amp1_entity_a049562dde is
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x30: std_logic;
signal ce_1_sg_x12: std_logic;
signal ce_2240_sg_x20: std_logic;
signal ce_logic_1_sg_x10: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x30: std_logic;
signal clk_1_sg_x12: std_logic;
signal clk_2240_sg_x20: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x12 <= ce_1;
ce_1120_sg_x30 <= ce_1120;
ce_2240_sg_x20 <= ce_2240;
ce_logic_1_sg_x10 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x12 <= clk_1;
clk_1120_sg_x30 <= clk_1120;
clk_2240_sg_x20 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x7;
ch_out <= assert3_dout_net_x8;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_f70fcc8ed9: entity work.fofb_amp_entity_f70fcc8ed9
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ce_logic_1 => ce_logic_1_sg_x10,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic1 => down_sample1_q_net_x10,
tddm_fofb_cic1_x0 => down_sample2_q_net_x10,
tddm_fofb_cic1_x1 => down_sample1_q_net_x11,
tddm_fofb_cic1_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_e4c0810ec7: entity work.fofb_cordic_entity_e4c0810ec7
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
tddm_fofb_cordic1 => down_sample1_q_net_x8,
tddm_fofb_cordic1_x0 => down_sample2_q_net_x8,
tddm_fofb_cordic1_x1 => down_sample1_q_net_x9,
tddm_fofb_cordic1_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp"
entity fofb_amp_entity_8b25d4b0b6 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
fofb_amp0: out std_logic_vector(23 downto 0);
fofb_amp0_x0: out std_logic_vector(23 downto 0);
fofb_amp0_x1: out std_logic_vector(23 downto 0);
fofb_amp0_x2: out std_logic_vector(23 downto 0);
fofb_amp0_x3: out std_logic_vector(23 downto 0);
fofb_amp0_x4: out std_logic_vector(23 downto 0);
fofb_amp0_x5: out std_logic_vector(23 downto 0);
fofb_amp0_x6: out std_logic_vector(23 downto 0);
fofb_amp0_x7: out std_logic;
fofb_amp1: out std_logic_vector(23 downto 0);
fofb_amp1_x0: out std_logic_vector(23 downto 0);
fofb_amp1_x1: out std_logic_vector(23 downto 0);
fofb_amp1_x2: out std_logic_vector(23 downto 0);
fofb_amp1_x3: out std_logic_vector(23 downto 0);
fofb_amp1_x4: out std_logic_vector(23 downto 0);
fofb_amp1_x5: out std_logic_vector(23 downto 0);
fofb_amp1_x6: out std_logic_vector(23 downto 0);
fofb_amp1_x7: out std_logic
);
end fofb_amp_entity_8b25d4b0b6;
architecture structural of fofb_amp_entity_8b25d4b0b6 is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x31: std_logic;
signal ce_1_sg_x13: std_logic;
signal ce_2240_sg_x21: std_logic;
signal ce_logic_1_sg_x11: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x4: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x5: std_logic;
signal clk_1120_sg_x31: std_logic;
signal clk_1_sg_x13: std_logic;
signal clk_2240_sg_x21: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal register3_q_net_x4: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x4: std_logic_vector(23 downto 0);
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x4: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x13 <= ce_1;
ce_1120_sg_x31 <= ce_1120;
ce_2240_sg_x21 <= ce_2240;
ce_logic_1_sg_x11 <= ce_logic_1;
register3_q_net_x4 <= ch_in0;
register3_q_net_x5 <= ch_in1;
clk_1_sg_x13 <= clk_1;
clk_1120_sg_x31 <= clk_1120;
clk_2240_sg_x21 <= clk_2240;
register4_q_net_x4 <= i_in0;
register4_q_net_x5 <= i_in1;
register5_q_net_x4 <= q_in0;
register5_q_net_x5 <= q_in1;
amp_out0 <= down_sample2_q_net_x16;
amp_out1 <= down_sample1_q_net_x16;
amp_out2 <= down_sample2_q_net_x17;
amp_out3 <= down_sample1_q_net_x17;
fofb_amp0 <= down_sample1_q_net_x18;
fofb_amp0_x0 <= down_sample2_q_net_x18;
fofb_amp0_x1 <= down_sample1_q_net_x19;
fofb_amp0_x2 <= down_sample2_q_net_x19;
fofb_amp0_x3 <= down_sample1_q_net_x20;
fofb_amp0_x4 <= down_sample2_q_net_x20;
fofb_amp0_x5 <= down_sample1_q_net_x21;
fofb_amp0_x6 <= down_sample2_q_net_x21;
fofb_amp0_x7 <= cic_fofb_q_event_tlast_missing_net_x4;
fofb_amp1 <= down_sample1_q_net_x22;
fofb_amp1_x0 <= down_sample2_q_net_x22;
fofb_amp1_x1 <= down_sample1_q_net_x23;
fofb_amp1_x2 <= down_sample2_q_net_x23;
fofb_amp1_x3 <= down_sample1_q_net_x24;
fofb_amp1_x4 <= down_sample2_q_net_x24;
fofb_amp1_x5 <= down_sample1_q_net_x25;
fofb_amp1_x6 <= down_sample2_q_net_x25;
fofb_amp1_x7 <= cic_fofb_q_event_tlast_missing_net_x5;
fofb_amp0_95b23bfc2c: entity work.fofb_amp0_entity_95b23bfc2c
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x4,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x4,
q_in => register5_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
fofb_amp => down_sample1_q_net_x20,
fofb_amp_x0 => down_sample2_q_net_x20,
fofb_amp_x1 => down_sample1_q_net_x21,
fofb_amp_x2 => down_sample2_q_net_x21,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x4,
fofb_cordic => down_sample1_q_net_x18,
fofb_cordic_x0 => down_sample2_q_net_x18,
fofb_cordic_x1 => down_sample1_q_net_x19,
fofb_cordic_x2 => down_sample2_q_net_x19
);
fofb_amp1_a049562dde: entity work.fofb_amp1_entity_a049562dde
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x5,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x5,
q_in => register5_q_net_x5,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
fofb_amp => down_sample1_q_net_x24,
fofb_amp_x0 => down_sample2_q_net_x24,
fofb_amp_x1 => down_sample1_q_net_x25,
fofb_amp_x2 => down_sample2_q_net_x25,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x5,
fofb_cordic => down_sample1_q_net_x22,
fofb_cordic_x0 => down_sample2_q_net_x22,
fofb_cordic_x1 => down_sample1_q_net_x23,
fofb_cordic_x2 => down_sample2_q_net_x23
);
tddm_fofb_amp_4ch_2cc521a83f: entity work.tddm_fofb_amp_4ch_entity_2cc521a83f
port map (
amp_in0 => assert2_dout_net_x6,
amp_in1 => assert2_dout_net_x7,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ch_in0 => assert3_dout_net_x7,
ch_in1 => assert3_dout_net_x8,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
amp_out0 => down_sample2_q_net_x16,
amp_out1 => down_sample1_q_net_x16,
amp_out2 => down_sample2_q_net_x17,
amp_out3 => down_sample1_q_net_x17
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3/Cast_truncate1"
entity cast_truncate1_entity_56731b7870 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_56731b7870;
architecture structural of cast_truncate1_entity_56731b7870 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3"
entity k_fofb_mult3_entity_697accc8e2 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_fofb_mult3_entity_697accc8e2;
architecture structural of k_fofb_mult3_entity_697accc8e2 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2240_sg_x22: std_logic;
signal ce_2_sg_x5: std_logic;
signal clk_2240_sg_x22: std_logic;
signal clk_2_sg_x5: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x5 <= ce_2;
ce_2240_sg_x22 <= ce_2240;
clk_2_sg_x5 <= clk_2;
clk_2240_sg_x22 <= clk_2240;
assert5_dout_net_x0 <= in1;
kx_i_net_x0 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_56731b7870: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x22,
clk => clk_2240_sg_x22,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x0,
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
clr => '0',
core_ce => ce_2_sg_x5,
core_clk => clk_2_sg_x5,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_1_mult"
entity k_monit_1_mult_entity_016885a3ac is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_1_mult_entity_016885a3ac;
architecture structural of k_monit_1_mult_entity_016885a3ac is
signal ce_224000000_sg_x0: std_logic;
signal ce_2_sg_x8: std_logic;
signal clk_224000000_sg_x0: std_logic;
signal clk_2_sg_x8: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool_dout_net_x0: std_logic;
begin
ce_2_sg_x8 <= ce_2;
ce_224000000_sg_x0 <= ce_224000000;
clk_2_sg_x8 <= clk_2;
clk_224000000_sg_x0 <= clk_224000000;
reinterpret3_output_port_net_x0 <= in1;
kx_i_net_x2 <= in2;
ufix_to_bool_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_fe5c8d5ea5: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x0,
clk => clk_224000000_sg_x0,
d(0) => ufix_to_bool_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret3_output_port_net_x0,
b => kx_i_net_x2,
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
clr => '0',
core_ce => ce_2_sg_x8,
core_clk => clk_2_sg_x8,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_mult3"
entity k_monit_mult3_entity_8a778fb5f4 is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_mult3_entity_8a778fb5f4;
architecture structural of k_monit_mult3_entity_8a778fb5f4 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_22400000_sg_x0: std_logic;
signal ce_2_sg_x11: std_logic;
signal clk_22400000_sg_x0: std_logic;
signal clk_2_sg_x11: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x4: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x11 <= ce_2;
ce_22400000_sg_x0 <= ce_22400000;
clk_2_sg_x11 <= clk_2;
clk_22400000_sg_x0 <= clk_22400000;
assert11_dout_net_x0 <= in1;
kx_i_net_x4 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_47fd83104e: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x0,
clk => clk_22400000_sg_x0,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => kx_i_net_x4,
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
clr => '0',
core_ce => ce_2_sg_x11,
core_clk => clk_2_sg_x11,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_tbt_mult"
entity k_tbt_mult_entity_b8fafff255 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_tbt_mult_entity_b8fafff255;
architecture structural of k_tbt_mult_entity_b8fafff255 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2_sg_x14: std_logic;
signal ce_70_sg_x0: std_logic;
signal clk_2_sg_x14: std_logic;
signal clk_70_sg_x0: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x6: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x14 <= ce_2;
ce_70_sg_x0 <= ce_70;
clk_2_sg_x14 <= clk_2;
clk_70_sg_x0 <= clk_70;
assert5_dout_net_x0 <= in1;
kx_i_net_x6 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4592ea30ee: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x0,
clk => clk_70_sg_x0,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x6,
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
clr => '0',
core_ce => ce_2_sg_x14,
core_clk => clk_2_sg_x14,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4/Cast_truncate1"
entity cast_truncate1_entity_18a9b21a64 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_18a9b21a64;
architecture structural of cast_truncate1_entity_18a9b21a64 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4"
entity ksum_fofb_mult4_entity_ac3ed97096 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_fofb_mult4_entity_ac3ed97096;
architecture structural of ksum_fofb_mult4_entity_ac3ed97096 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2240_sg_x25: std_logic;
signal ce_2_sg_x17: std_logic;
signal clk_2240_sg_x25: std_logic;
signal clk_2_sg_x17: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x17 <= ce_2;
ce_2240_sg_x25 <= ce_2240;
clk_2_sg_x17 <= clk_2;
clk_2240_sg_x25 <= clk_2240;
assert11_dout_net_x0 <= in1;
ksum_i_net_x0 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_18a9b21a64: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x25,
clk => clk_2240_sg_x25,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x0,
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
clr => '0',
core_ce => ce_2_sg_x17,
core_clk => clk_2_sg_x17,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_1_mult1"
entity ksum_monit_1_mult1_entity_c66dc07078 is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_1_mult1_entity_c66dc07078;
architecture structural of ksum_monit_1_mult1_entity_c66dc07078 is
signal ce_224000000_sg_x3: std_logic;
signal ce_2_sg_x18: std_logic;
signal clk_224000000_sg_x3: std_logic;
signal clk_2_sg_x18: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x1: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret4_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool3_dout_net_x0: std_logic;
begin
ce_2_sg_x18 <= ce_2;
ce_224000000_sg_x3 <= ce_224000000;
clk_2_sg_x18 <= clk_2;
clk_224000000_sg_x3 <= clk_224000000;
reinterpret4_output_port_net_x0 <= in1;
ksum_i_net_x1 <= in2;
ufix_to_bool3_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_92cc22397d: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x3,
clk => clk_224000000_sg_x3,
d(0) => ufix_to_bool3_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret4_output_port_net_x0,
b => ksum_i_net_x1,
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
clr => '0',
core_ce => ce_2_sg_x18,
core_clk => clk_2_sg_x18,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_mult2"
entity ksum_monit_mult2_entity_31877b6d2b is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_mult2_entity_31877b6d2b;
architecture structural of ksum_monit_mult2_entity_31877b6d2b is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_22400000_sg_x3: std_logic;
signal ce_2_sg_x19: std_logic;
signal clk_22400000_sg_x3: std_logic;
signal clk_2_sg_x19: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x19 <= ce_2;
ce_22400000_sg_x3 <= ce_22400000;
clk_2_sg_x19 <= clk_2;
clk_22400000_sg_x3 <= clk_22400000;
assert5_dout_net_x0 <= in1;
ksum_i_net_x2 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4c5b033963: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x3,
clk => clk_22400000_sg_x3,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => ksum_i_net_x2,
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
clr => '0',
core_ce => ce_2_sg_x19,
core_clk => clk_2_sg_x19,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_tbt_mult3"
entity ksum_tbt_mult3_entity_e0be30d675 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_tbt_mult3_entity_e0be30d675;
architecture structural of ksum_tbt_mult3_entity_e0be30d675 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2_sg_x20: std_logic;
signal ce_70_sg_x3: std_logic;
signal clk_2_sg_x20: std_logic;
signal clk_70_sg_x3: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x3: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x20 <= ce_2;
ce_70_sg_x3 <= ce_70;
clk_2_sg_x20 <= clk_2;
clk_70_sg_x3 <= clk_70;
assert11_dout_net_x0 <= in1;
ksum_i_net_x3 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_91bc0d396f: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x3,
clk => clk_70_sg_x3,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_7786f9df1b07f80e",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x3,
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
clr => '0',
core_ce => ce_2_sg_x20,
core_clk => clk_2_sg_x20,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En"
entity datareg_en_entity_5c82ef2965 is
port (
ce_2: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0);
valid: out std_logic
);
end datareg_en_entity_5c82ef2965;
architecture structural of datareg_en_entity_5c82ef2965 is
signal ce_2_sg_x21: std_logic;
signal clk_2_sg_x21: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant12_op_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2_sg_x21 <= ce_2;
clk_2_sg_x21 <= clk_2;
constant12_op_net_x0 <= din;
constant11_op_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d(0) => constant11_op_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d => constant12_op_net_x0,
en(0) => constant11_op_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En1"
entity datareg_en1_entity_8d533fde9e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end datareg_en1_entity_8d533fde9e;
architecture structural of datareg_en1_entity_8d533fde9e is
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal constant11_op_net_x1: std_logic;
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= din;
constant11_op_net_x1 <= en;
dout <= register_q_net_x2;
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => register_q_net_x1,
en(0) => constant11_op_net_x1,
rst => "0",
q => register_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0"
entity cmixer_0_entity_f630e8d7ec is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine: in std_logic_vector(23 downto 0);
dds_msine: in std_logic_vector(23 downto 0);
dds_valid: in std_logic;
din_i: in std_logic_vector(23 downto 0);
din_q: in std_logic_vector(23 downto 0);
en: in std_logic;
ch_out: out std_logic;
i_out: out std_logic_vector(23 downto 0);
q_out: out std_logic_vector(23 downto 0)
);
end cmixer_0_entity_f630e8d7ec;
architecture structural of cmixer_0_entity_f630e8d7ec is
signal a_i: std_logic_vector(23 downto 0);
signal a_r: std_logic_vector(23 downto 0);
signal b_i: std_logic_vector(23 downto 0);
signal b_r: std_logic_vector(23 downto 0);
signal ce_1_sg_x15: std_logic;
signal ce_2_sg_x22: std_logic;
signal clk_1_sg_x15: std_logic;
signal clk_2_sg_x22: std_logic;
signal complexmult_m_axis_dout_tdata_imag_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tuser_net: std_logic;
signal complexmult_m_axis_dout_tvalid_net: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x0: std_logic;
signal convert1_dout_net: std_logic_vector(23 downto 0);
signal convert2_dout_net: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
signal register_q_net_x8: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x15 <= ce_1;
ce_2_sg_x22 <= ce_2;
register1_q_net_x1 <= ch_in;
clk_1_sg_x15 <= clk_1;
clk_2_sg_x22 <= clk_2;
register_q_net_x6 <= dds_cosine;
register_q_net_x7 <= dds_msine;
constant15_op_net_x0 <= dds_valid;
register_q_net_x8 <= din_i;
constant12_op_net_x1 <= din_q;
constant11_op_net_x2 <= en;
ch_out <= register3_q_net_x5;
i_out <= register4_q_net_x5;
q_out <= register5_q_net_x5;
complexmult: entity work.xlcomplex_multiplier_456da30af0f77a480cf80f52b29b4396
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
s_axis_a_tdata_imag => a_i,
s_axis_a_tdata_real => a_r,
s_axis_a_tvalid => constant15_op_net_x0,
s_axis_b_tdata_imag => b_i,
s_axis_b_tdata_real => b_r,
s_axis_b_tuser(0) => register_q_net,
s_axis_b_tvalid => register1_q_net_x0,
m_axis_dout_tdata_imag => complexmult_m_axis_dout_tdata_imag_net,
m_axis_dout_tdata_real => complexmult_m_axis_dout_tdata_real_net,
m_axis_dout_tuser(0) => complexmult_m_axis_dout_tuser_net,
m_axis_dout_tvalid => complexmult_m_axis_dout_tvalid_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret1_output_port_net,
en => "1",
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert2_dout_net
);
datareg_en1_8d533fde9e: entity work.datareg_en1_entity_8d533fde9e
port map (
ce_1 => ce_1_sg_x15,
clk_1 => clk_1_sg_x15,
din => register_q_net_x8,
en => constant11_op_net_x2,
dout => register_q_net_x2
);
datareg_en_5c82ef2965: entity work.datareg_en_entity_5c82ef2965
port map (
ce_2 => ce_2_sg_x22,
clk_2 => clk_2_sg_x22,
din => constant12_op_net_x1,
en => constant11_op_net_x2,
dout => register_q_net_x0,
valid => register1_q_net_x0
);
delay: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x0,
q => b_i
);
delay1: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x2,
q => b_r
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x6,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_r
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x7,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_i
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => complexmult_m_axis_dout_tuser_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register3_q_net_x5
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert1_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net_x5
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert2_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net_x5
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => register1_q_net_x1,
en(0) => constant11_op_net_x2,
rst => "0",
q(0) => register_q_net
);
reinterpret: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_imag_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_real_net,
output_port => reinterpret1_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer/TDDM_Mixer0_i"
entity tddm_mixer0_i_entity_f95b8f24ad is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_mixer0_i_entity_f95b8f24ad;
architecture structural of tddm_mixer0_i_entity_f95b8f24ad is
signal ce_1_sg_x18: std_logic;
signal ce_2_sg_x25: std_logic;
signal clk_1_sg_x18: std_logic;
signal clk_2_sg_x25: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register3_q_net_x6: std_logic;
signal register4_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x18 <= ce_1;
ce_2_sg_x25 <= ce_2;
register3_q_net_x6 <= ch_in;
clk_1_sg_x18 <= clk_1;
clk_2_sg_x25 <= clk_2;
register4_q_net_x6 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register3_q_net_x6,
b(0) => constant_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x6,
b => constant1_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer"
entity tddm_mixer_entity_8537ade7b6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
mix0_ch_in: in std_logic;
mix0_i_in: in std_logic_vector(23 downto 0);
mix0_q_in: in std_logic_vector(23 downto 0);
mix1_ch_in: in std_logic;
mix1_i_in: in std_logic_vector(23 downto 0);
mix1_q_in: in std_logic_vector(23 downto 0);
mix_ch0_i_out: out std_logic_vector(23 downto 0);
mix_ch0_q_out: out std_logic_vector(23 downto 0);
mix_ch1_i_out: out std_logic_vector(23 downto 0);
mix_ch1_q_out: out std_logic_vector(23 downto 0);
mix_ch2_i_out: out std_logic_vector(23 downto 0);
mix_ch2_q_out: out std_logic_vector(23 downto 0);
mix_ch3_i_out: out std_logic_vector(23 downto 0);
mix_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_mixer_entity_8537ade7b6;
architecture structural of tddm_mixer_entity_8537ade7b6 is
signal ce_1_sg_x22: std_logic;
signal ce_2_sg_x29: std_logic;
signal clk_1_sg_x22: std_logic;
signal clk_2_sg_x29: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x7: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x7: std_logic_vector(23 downto 0);
signal register3_q_net_x10: std_logic;
signal register3_q_net_x9: std_logic;
signal register4_q_net_x8: std_logic_vector(23 downto 0);
signal register4_q_net_x9: std_logic_vector(23 downto 0);
signal register5_q_net_x8: std_logic_vector(23 downto 0);
signal register5_q_net_x9: std_logic_vector(23 downto 0);
begin
ce_1_sg_x22 <= ce_1;
ce_2_sg_x29 <= ce_2;
clk_1_sg_x22 <= clk_1;
clk_2_sg_x29 <= clk_2;
register3_q_net_x9 <= mix0_ch_in;
register4_q_net_x8 <= mix0_i_in;
register5_q_net_x8 <= mix0_q_in;
register3_q_net_x10 <= mix1_ch_in;
register4_q_net_x9 <= mix1_i_in;
register5_q_net_x9 <= mix1_q_in;
mix_ch0_i_out <= down_sample2_q_net_x4;
mix_ch0_q_out <= down_sample2_q_net_x5;
mix_ch1_i_out <= down_sample1_q_net_x4;
mix_ch1_q_out <= down_sample1_q_net_x5;
mix_ch2_i_out <= down_sample2_q_net_x6;
mix_ch2_q_out <= down_sample2_q_net_x7;
mix_ch3_i_out <= down_sample1_q_net_x6;
mix_ch3_q_out <= down_sample1_q_net_x7;
tddm_mixer0_i_f95b8f24ad: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x8,
dout_ch0 => down_sample2_q_net_x4,
dout_ch1 => down_sample1_q_net_x4
);
tddm_mixer0_q_2c5e18f496: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x8,
dout_ch0 => down_sample2_q_net_x5,
dout_ch1 => down_sample1_q_net_x5
);
tddm_mixer1_i_1afc4ccdba: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x9,
dout_ch0 => down_sample2_q_net_x6,
dout_ch1 => down_sample1_q_net_x6
);
tddm_mixer1_q_ee4acbed30: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x9,
dout_ch0 => down_sample2_q_net_x7,
dout_ch1 => down_sample1_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer"
entity mixer_entity_a1cd828545 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine_0: in std_logic_vector(23 downto 0);
dds_cosine_1: in std_logic_vector(23 downto 0);
dds_msine_0: in std_logic_vector(23 downto 0);
dds_msine_1: in std_logic_vector(23 downto 0);
dds_valid_0: in std_logic;
dds_valid_1: in std_logic;
din0: in std_logic_vector(23 downto 0);
din1: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
i_out0: out std_logic_vector(23 downto 0);
i_out1: out std_logic_vector(23 downto 0);
q_out0: out std_logic_vector(23 downto 0);
q_out1: out std_logic_vector(23 downto 0);
tddm_mixer: out std_logic_vector(23 downto 0);
tddm_mixer_x0: out std_logic_vector(23 downto 0);
tddm_mixer_x1: out std_logic_vector(23 downto 0);
tddm_mixer_x2: out std_logic_vector(23 downto 0);
tddm_mixer_x3: out std_logic_vector(23 downto 0);
tddm_mixer_x4: out std_logic_vector(23 downto 0);
tddm_mixer_x5: out std_logic_vector(23 downto 0);
tddm_mixer_x6: out std_logic_vector(23 downto 0)
);
end mixer_entity_a1cd828545;
architecture structural of mixer_entity_a1cd828545 is
signal ce_1_sg_x23: std_logic;
signal ce_2_sg_x30: std_logic;
signal clk_1_sg_x23: std_logic;
signal clk_2_sg_x30: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x1: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant2_op_net_x1: std_logic_vector(23 downto 0);
signal constant3_op_net_x1: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register3_q_net_x11: std_logic;
signal register3_q_net_x12: std_logic;
signal register4_q_net_x10: std_logic_vector(23 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x10: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x16: std_logic_vector(23 downto 0);
signal register_q_net_x17: std_logic_vector(23 downto 0);
begin
ce_1_sg_x23 <= ce_1;
ce_2_sg_x30 <= ce_2;
register1_q_net_x3 <= ch_in0;
register1_q_net_x4 <= ch_in1;
clk_1_sg_x23 <= clk_1;
clk_2_sg_x30 <= clk_2;
register_q_net_x12 <= dds_cosine_0;
register_q_net_x14 <= dds_cosine_1;
register_q_net_x13 <= dds_msine_0;
register_q_net_x15 <= dds_msine_1;
constant15_op_net_x1 <= dds_valid_0;
constant3_op_net_x1 <= dds_valid_1;
register_q_net_x16 <= din0;
register_q_net_x17 <= din1;
ch_out0 <= register3_q_net_x11;
ch_out1 <= register3_q_net_x12;
i_out0 <= register4_q_net_x10;
i_out1 <= register4_q_net_x11;
q_out0 <= register5_q_net_x10;
q_out1 <= register5_q_net_x11;
tddm_mixer <= down_sample1_q_net_x8;
tddm_mixer_x0 <= down_sample2_q_net_x8;
tddm_mixer_x1 <= down_sample1_q_net_x9;
tddm_mixer_x2 <= down_sample2_q_net_x9;
tddm_mixer_x3 <= down_sample1_q_net_x10;
tddm_mixer_x4 <= down_sample2_q_net_x10;
tddm_mixer_x5 <= down_sample1_q_net_x11;
tddm_mixer_x6 <= down_sample2_q_net_x11;
cmixer_0_f630e8d7ec: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x3,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x12,
dds_msine => register_q_net_x13,
dds_valid => constant15_op_net_x1,
din_i => register_q_net_x16,
din_q => constant12_op_net_x1,
en => constant11_op_net_x2,
ch_out => register3_q_net_x11,
i_out => register4_q_net_x10,
q_out => register5_q_net_x10
);
cmixer_1_61bfc18f90: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x4,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x14,
dds_msine => register_q_net_x15,
dds_valid => constant3_op_net_x1,
din_i => register_q_net_x17,
din_q => constant2_op_net_x1,
en => constant1_op_net_x2,
ch_out => register3_q_net_x12,
i_out => register4_q_net_x11,
q_out => register5_q_net_x11
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x2
);
constant11: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x2
);
constant12: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant12_op_net_x1
);
constant2: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net_x1
);
tddm_mixer_8537ade7b6: entity work.tddm_mixer_entity_8537ade7b6
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
mix0_ch_in => register3_q_net_x11,
mix0_i_in => register4_q_net_x10,
mix0_q_in => register5_q_net_x10,
mix1_ch_in => register3_q_net_x12,
mix1_i_in => register4_q_net_x11,
mix1_q_in => register5_q_net_x11,
mix_ch0_i_out => down_sample2_q_net_x8,
mix_ch0_q_out => down_sample2_q_net_x9,
mix_ch1_i_out => down_sample1_q_net_x8,
mix_ch1_q_out => down_sample1_q_net_x9,
mix_ch2_i_out => down_sample2_q_net_x10,
mix_ch2_q_out => down_sample2_q_net_x11,
mix_ch3_i_out => down_sample1_q_net_x10,
mix_ch3_q_out => down_sample1_q_net_x11
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2/format1"
entity format1_entity_4e0a69646b is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_4e0a69646b;
architecture structural of format1_entity_4e0a69646b is
signal ce_5600000_sg_x0: std_logic;
signal clk_5600000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_5600000_sg_x0 <= ce_5600000;
clk_5600000_sg_x0 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_5600000_sg_x0,
clk => clk_5600000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2"
entity cast2_entity_4b7421c7c9 is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast2_entity_4b7421c7c9;
architecture structural of cast2_entity_4b7421c7c9 is
signal ce_5600000_sg_x1: std_logic;
signal clk_5600000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_5600000_sg_x1 <= ce_5600000;
clk_5600000_sg_x1 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x1 <= data_in;
monit_pfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_4e0a69646b: entity work.format1_entity_4e0a69646b
port map (
ce_5600000 => ce_5600000_sg_x1,
clk_5600000 => clk_5600000_sg_x1,
din => monit_pfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x1,
clk => clk_5600000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4/format1"
entity format1_entity_3cf61b0d44 is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_3cf61b0d44;
architecture structural of format1_entity_3cf61b0d44 is
signal ce_2800000_sg_x0: std_logic;
signal clk_2800000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_2800000_sg_x0 <= ce_2800000;
clk_2800000_sg_x0 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_2800000_sg_x0,
clk => clk_2800000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4"
entity cast4_entity_4ed908d7fc is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast4_entity_4ed908d7fc;
architecture structural of cast4_entity_4ed908d7fc is
signal ce_2800000_sg_x1: std_logic;
signal clk_2800000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2800000_sg_x1 <= ce_2800000;
clk_2800000_sg_x1 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x1 <= data_in;
monit_cfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_3cf61b0d44: entity work.format1_entity_3cf61b0d44
port map (
ce_2800000 => ce_2800000_sg_x1,
clk_2800000 => clk_2800000_sg_x1,
din => monit_cfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2800000_sg_x1,
clk => clk_2800000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_cfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Reg1"
entity reg1_entity_8661a44192 is
port (
ce_1400000: in std_logic;
clk_1400000: in std_logic;
din: in std_logic_vector(60 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end reg1_entity_8661a44192;
architecture structural of reg1_entity_8661a44192 is
signal ce_1400000_sg_x0: std_logic;
signal clk_1400000_sg_x0: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(60 downto 0);
begin
ce_1400000_sg_x0 <= ce_1400000;
clk_1400000_sg_x0 <= clk_1400000;
monit_cic_m_axis_data_tdata_data_net_x0 <= din;
monit_cic_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 59,
din_width => 61,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
d => convert_dout_net,
en(0) => monit_cic_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_c88e29aa6b
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cic_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c/TDDM_monit_amp_c_int"
entity tddm_monit_amp_c_int_entity_554a834349 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_22400000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_int_entity_554a834349;
architecture structural of tddm_monit_amp_c_int_entity_554a834349 is
signal ce_22400000_sg_x4: std_logic;
signal ce_5600000_sg_x2: std_logic;
signal clk_22400000_sg_x4: std_logic;
signal clk_5600000_sg_x2: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal delay2_q_net_x0: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_22400000_sg_x4 <= ce_22400000;
ce_5600000_sg_x2 <= ce_5600000;
delay2_q_net_x0 <= ch_in;
clk_22400000_sg_x4 <= clk_22400000;
clk_5600000_sg_x2 <= clk_5600000;
register_q_net_x1 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register2_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register3_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant1_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant3_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant4_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c"
entity tddm_monit_amp_c_entity_5b2613eff7 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_ch_in: in std_logic_vector(1 downto 0);
monit_din: in std_logic_vector(23 downto 0);
monit_ch0_out: out std_logic_vector(23 downto 0);
monit_ch1_out: out std_logic_vector(23 downto 0);
monit_ch2_out: out std_logic_vector(23 downto 0);
monit_ch3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_entity_5b2613eff7;
architecture structural of tddm_monit_amp_c_entity_5b2613eff7 is
signal ce_22400000_sg_x5: std_logic;
signal ce_5600000_sg_x3: std_logic;
signal clk_22400000_sg_x5: std_logic;
signal clk_5600000_sg_x3: std_logic;
signal delay2_q_net_x1: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x5 <= ce_22400000;
ce_5600000_sg_x3 <= ce_5600000;
clk_22400000_sg_x5 <= clk_22400000;
clk_5600000_sg_x3 <= clk_5600000;
delay2_q_net_x1 <= monit_ch_in;
register_q_net_x2 <= monit_din;
monit_ch0_out <= down_sample2_q_net_x1;
monit_ch1_out <= down_sample1_q_net_x1;
monit_ch2_out <= down_sample3_q_net_x1;
monit_ch3_out <= down_sample4_q_net_x1;
tddm_monit_amp_c_int_554a834349: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x5,
ce_5600000 => ce_5600000_sg_x3,
ch_in => delay2_q_net_x1,
clk_22400000 => clk_22400000_sg_x5,
clk_5600000 => clk_5600000_sg_x3,
din => register_q_net_x2,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c"
entity monit_amp_c_entity_c83793ea71 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out_x1: out std_logic_vector(1 downto 0);
monit_cfir_x0: out std_logic;
monit_cic_x0: out std_logic;
monit_pfir_x0: out std_logic;
tddm_monit_amp_c: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x0: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x1: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x2: out std_logic_vector(23 downto 0)
);
end monit_amp_c_entity_c83793ea71;
architecture structural of monit_amp_c_entity_c83793ea71 is
signal ce_1400000_sg_x1: std_logic;
signal ce_1_sg_x24: std_logic;
signal ce_22400000_sg_x6: std_logic;
signal ce_2800000_sg_x2: std_logic;
signal ce_5600000_sg_x4: std_logic;
signal ce_560_sg_x0: std_logic;
signal ce_logic_1400000_sg_x0: std_logic;
signal ce_logic_2800000_sg_x0: std_logic;
signal ce_logic_560_sg_x0: std_logic;
signal ch_out_x0: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x1: std_logic;
signal clk_1_sg_x24: std_logic;
signal clk_22400000_sg_x6: std_logic;
signal clk_2800000_sg_x2: std_logic;
signal clk_5600000_sg_x4: std_logic;
signal clk_560_sg_x0: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay1_q_net: std_logic_vector(23 downto 0);
signal delay2_q_net_x2: std_logic_vector(1 downto 0);
signal delay3_q_net: std_logic_vector(23 downto 0);
signal delay_q_net: std_logic_vector(1 downto 0);
signal dout_x0: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x2: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal monit_cic_event_tlast_unexpected_net_x0: std_logic;
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tuser_chan_out_net: std_logic_vector(1 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register3_q_net: std_logic_vector(1 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x24 <= ce_1;
ce_1400000_sg_x1 <= ce_1400000;
ce_22400000_sg_x6 <= ce_22400000;
ce_2800000_sg_x2 <= ce_2800000;
ce_560_sg_x0 <= ce_560;
ce_5600000_sg_x4 <= ce_5600000;
ce_logic_1400000_sg_x0 <= ce_logic_1400000;
ce_logic_2800000_sg_x0 <= ce_logic_2800000;
ce_logic_560_sg_x0 <= ce_logic_560;
ch_out_x0 <= ch_in;
clk_1_sg_x24 <= clk_1;
clk_1400000_sg_x1 <= clk_1400000;
clk_22400000_sg_x6 <= clk_22400000;
clk_2800000_sg_x2 <= clk_2800000;
clk_560_sg_x0 <= clk_560;
clk_5600000_sg_x4 <= clk_5600000;
dout_x0 <= din;
amp_out <= register_q_net_x3;
ch_out_x1 <= delay2_q_net_x2;
monit_cfir_x0 <= monit_cfir_event_s_data_chanid_incorrect_net_x0;
monit_cic_x0 <= monit_cic_event_tlast_unexpected_net_x0;
monit_pfir_x0 <= monit_pfir_event_s_data_chanid_incorrect_net_x0;
tddm_monit_amp_c <= down_sample1_q_net_x2;
tddm_monit_amp_c_x0 <= down_sample2_q_net_x2;
tddm_monit_amp_c_x1 <= down_sample3_q_net_x2;
tddm_monit_amp_c_x2 <= down_sample4_q_net_x2;
cast2_4b7421c7c9: entity work.cast2_entity_4b7421c7c9
port map (
ce_5600000 => ce_5600000_sg_x4,
clk_5600000 => clk_5600000_sg_x4,
data_in => monit_pfir_m_axis_data_tdata_net_x1,
en => monit_pfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x3
);
cast4_4ed908d7fc: entity work.cast4_entity_4ed908d7fc
port map (
ce_2800000 => ce_2800000_sg_x2,
clk_2800000 => clk_2800000_sg_x2,
data_in => monit_cfir_m_axis_data_tdata_net_x1,
en => monit_cfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0
);
constant1: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => monit_cic_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
d => dout_x0,
en => '1',
rst => '1',
q => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_5600000_sg_x4,
clk => clk_5600000_sg_x4,
d => monit_pfir_m_axis_data_tuser_chanid_net,
en => '1',
rst => '1',
q => delay2_q_net_x2
);
delay3: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => register_q_net_x1,
en => '1',
rst => '1',
q => delay3_q_net
);
monit_cfir: entity work.xlfir_compiler_2acadf5a08d72e0ee15ce4e1ac741dc6
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_2800000 => ce_2800000_sg_x2,
ce_logic_1400000 => ce_logic_1400000_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_2800000 => clk_2800000_sg_x2,
clk_logic_1400000 => clk_1400000_sg_x1,
s_axis_data_tdata => delay3_q_net,
s_axis_data_tuser_chanid => delay_q_net,
src_ce => ce_1400000_sg_x1,
src_clk => clk_1400000_sg_x1,
event_s_data_chanid_incorrect => monit_cfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_cfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_cfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_cfir_m_axis_data_tvalid_net_x0
);
monit_cic: entity work.xlcic_compiler_6efc67831a277bdb0701519c5a976f20
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_560 => ce_560_sg_x0,
ce_logic_560 => ce_logic_560_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_560 => clk_560_sg_x0,
clk_logic_560 => clk_560_sg_x0,
s_axis_data_tdata_data => delay1_q_net,
s_axis_data_tlast => relational2_op_net,
event_tlast_unexpected => monit_cic_event_tlast_unexpected_net_x0,
m_axis_data_tdata_data => monit_cic_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out => monit_cic_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => monit_cic_m_axis_data_tvalid_net_x0
);
monit_pfir: entity work.xlfir_compiler_1da691037bdf8c1b85b3b4502d6e9610
port map (
ce => ce_1_sg_x24,
ce_2800000 => ce_2800000_sg_x2,
ce_5600000 => ce_5600000_sg_x4,
ce_logic_2800000 => ce_logic_2800000_sg_x0,
clk => clk_1_sg_x24,
clk_2800000 => clk_2800000_sg_x2,
clk_5600000 => clk_5600000_sg_x4,
clk_logic_2800000 => clk_2800000_sg_x2,
s_axis_data_tdata => register_q_net_x0,
s_axis_data_tuser_chanid => register3_q_net,
src_ce => ce_2800000_sg_x2,
src_clk => clk_2800000_sg_x2,
event_s_data_chanid_incorrect => monit_pfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pfir_m_axis_data_tvalid_net_x0
);
reg1_8661a44192: entity work.reg1_entity_8661a44192
port map (
ce_1400000 => ce_1400000_sg_x1,
clk_1400000 => clk_1400000_sg_x1,
din => monit_cic_m_axis_data_tdata_data_net_x0,
en => monit_cic_m_axis_data_tvalid_net_x0,
dout => register_q_net_x1
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_2800000_sg_x2,
clk => clk_2800000_sg_x2,
d => monit_cfir_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register3_q_net
);
relational2: entity work.relational_83ca2c6a3c
port map (
a => ch_out_x0,
b => constant1_op_net,
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
clr => '0',
op(0) => relational2_op_net
);
tddm_monit_amp_c_5b2613eff7: entity work.tddm_monit_amp_c_entity_5b2613eff7
port map (
ce_22400000 => ce_22400000_sg_x6,
ce_5600000 => ce_5600000_sg_x4,
clk_22400000 => clk_22400000_sg_x6,
clk_5600000 => clk_5600000_sg_x4,
monit_ch_in => delay2_q_net_x2,
monit_din => register_q_net_x3,
monit_ch0_out => down_sample2_q_net_x2,
monit_ch1_out => down_sample1_q_net_x2,
monit_ch2_out => down_sample3_q_net_x2,
monit_ch3_out => down_sample4_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/TDDM_monit_amp_out"
entity tddm_monit_amp_out_entity_521eb373cc is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_amp_ch_in: in std_logic_vector(1 downto 0);
monit_amp_din: in std_logic_vector(23 downto 0);
monit_amp_data0_out: out std_logic_vector(23 downto 0);
monit_amp_data1_out: out std_logic_vector(23 downto 0);
monit_amp_data2_out: out std_logic_vector(23 downto 0);
monit_amp_data3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_out_entity_521eb373cc;
architecture structural of tddm_monit_amp_out_entity_521eb373cc is
signal ce_22400000_sg_x8: std_logic;
signal ce_5600000_sg_x6: std_logic;
signal clk_22400000_sg_x8: std_logic;
signal clk_5600000_sg_x6: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x8 <= ce_22400000;
ce_5600000_sg_x6 <= ce_5600000;
clk_22400000_sg_x8 <= clk_22400000;
clk_5600000_sg_x6 <= clk_5600000;
delay2_q_net_x4 <= monit_amp_ch_in;
register_q_net_x5 <= monit_amp_din;
monit_amp_data0_out <= down_sample2_q_net_x1;
monit_amp_data1_out <= down_sample1_q_net_x1;
monit_amp_data2_out <= down_sample3_q_net_x1;
monit_amp_data3_out <= down_sample4_q_net_x1;
tddm_monit_amp_out_int_b60196c7a6: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x8,
ce_5600000 => ce_5600000_sg_x6,
ch_in => delay2_q_net_x4,
clk_22400000 => clk_22400000_sg_x8,
clk_5600000 => clk_5600000_sg_x6,
din => register_q_net_x5,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp"
entity monit_amp_entity_44da74e268 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
monit_amp_c: out std_logic_vector(23 downto 0);
monit_amp_c_x0: out std_logic_vector(23 downto 0);
monit_amp_c_x1: out std_logic_vector(23 downto 0);
monit_amp_c_x2: out std_logic_vector(23 downto 0);
monit_amp_c_x3: out std_logic;
monit_amp_c_x4: out std_logic;
monit_amp_c_x5: out std_logic
);
end monit_amp_entity_44da74e268;
architecture structural of monit_amp_entity_44da74e268 is
signal ce_1400000_sg_x2: std_logic;
signal ce_1_sg_x25: std_logic;
signal ce_22400000_sg_x9: std_logic;
signal ce_2800000_sg_x3: std_logic;
signal ce_5600000_sg_x7: std_logic;
signal ce_560_sg_x1: std_logic;
signal ce_logic_1400000_sg_x1: std_logic;
signal ce_logic_2800000_sg_x1: std_logic;
signal ce_logic_560_sg_x1: std_logic;
signal ch_out_x1: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x2: std_logic;
signal clk_1_sg_x25: std_logic;
signal clk_22400000_sg_x9: std_logic;
signal clk_2800000_sg_x3: std_logic;
signal clk_5600000_sg_x7: std_logic;
signal clk_560_sg_x1: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal dout_x1: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x4: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal monit_cic_event_tlast_unexpected_net_x1: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x25 <= ce_1;
ce_1400000_sg_x2 <= ce_1400000;
ce_22400000_sg_x9 <= ce_22400000;
ce_2800000_sg_x3 <= ce_2800000;
ce_560_sg_x1 <= ce_560;
ce_5600000_sg_x7 <= ce_5600000;
ce_logic_1400000_sg_x1 <= ce_logic_1400000;
ce_logic_2800000_sg_x1 <= ce_logic_2800000;
ce_logic_560_sg_x1 <= ce_logic_560;
ch_out_x1 <= ch_in;
clk_1_sg_x25 <= clk_1;
clk_1400000_sg_x2 <= clk_1400000;
clk_22400000_sg_x9 <= clk_22400000;
clk_2800000_sg_x3 <= clk_2800000;
clk_560_sg_x1 <= clk_560;
clk_5600000_sg_x7 <= clk_5600000;
dout_x1 <= din;
amp_out0 <= down_sample2_q_net_x4;
amp_out1 <= down_sample1_q_net_x4;
amp_out2 <= down_sample3_q_net_x4;
amp_out3 <= down_sample4_q_net_x4;
monit_amp_c <= down_sample1_q_net_x3;
monit_amp_c_x0 <= down_sample2_q_net_x3;
monit_amp_c_x1 <= down_sample3_q_net_x3;
monit_amp_c_x2 <= down_sample4_q_net_x3;
monit_amp_c_x3 <= monit_cfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_x4 <= monit_cic_event_tlast_unexpected_net_x1;
monit_amp_c_x5 <= monit_pfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_c83793ea71: entity work.monit_amp_c_entity_c83793ea71
port map (
ce_1 => ce_1_sg_x25,
ce_1400000 => ce_1400000_sg_x2,
ce_22400000 => ce_22400000_sg_x9,
ce_2800000 => ce_2800000_sg_x3,
ce_560 => ce_560_sg_x1,
ce_5600000 => ce_5600000_sg_x7,
ce_logic_1400000 => ce_logic_1400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x1,
ce_logic_560 => ce_logic_560_sg_x1,
ch_in => ch_out_x1,
clk_1 => clk_1_sg_x25,
clk_1400000 => clk_1400000_sg_x2,
clk_22400000 => clk_22400000_sg_x9,
clk_2800000 => clk_2800000_sg_x3,
clk_560 => clk_560_sg_x1,
clk_5600000 => clk_5600000_sg_x7,
din => dout_x1,
amp_out => register_q_net_x5,
ch_out_x1 => delay2_q_net_x4,
monit_cfir_x0 => monit_cfir_event_s_data_chanid_incorrect_net_x1,
monit_cic_x0 => monit_cic_event_tlast_unexpected_net_x1,
monit_pfir_x0 => monit_pfir_event_s_data_chanid_incorrect_net_x1,
tddm_monit_amp_c => down_sample1_q_net_x3,
tddm_monit_amp_c_x0 => down_sample2_q_net_x3,
tddm_monit_amp_c_x1 => down_sample3_q_net_x3,
tddm_monit_amp_c_x2 => down_sample4_q_net_x3
);
tddm_monit_amp_out_521eb373cc: entity work.tddm_monit_amp_out_entity_521eb373cc
port map (
ce_22400000 => ce_22400000_sg_x9,
ce_5600000 => ce_5600000_sg_x7,
clk_22400000 => clk_22400000_sg_x9,
clk_5600000 => clk_5600000_sg_x7,
monit_amp_ch_in => delay2_q_net_x4,
monit_amp_din => register_q_net_x5,
monit_amp_data0_out => down_sample2_q_net_x4,
monit_amp_data1_out => down_sample1_q_net_x4,
monit_amp_data2_out => down_sample3_q_net_x4,
monit_amp_data3_out => down_sample4_q_net_x4
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_5b94be40c5 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_5b94be40c5;
architecture structural of tddm_tbt_cordic_entity_5b94be40c5 is
signal ce_35_sg_x0: std_logic;
signal ce_70_sg_x4: std_logic;
signal clk_35_sg_x0: std_logic;
signal clk_70_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_amp_out_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x0: std_logic;
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x0 <= ce_35;
ce_70_sg_x4 <= ce_70;
p_ch_out_x0 <= ch_in;
clk_35_sg_x0 <= clk_35;
clk_70_sg_x4 <= clk_70;
p_amp_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant1_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_d3f44a687c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_d3f44a687c;
architecture structural of tddm_tbt_cordic1_entity_d3f44a687c is
signal ce_35_sg_x1: std_logic;
signal ce_70_sg_x5: std_logic;
signal clk_35_sg_x1: std_logic;
signal clk_70_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x1: std_logic;
signal p_phase_out_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x1 <= ce_35;
ce_70_sg_x5 <= ce_70;
p_ch_out_x1 <= ch_in;
clk_35_sg_x1 <= clk_35;
clk_70_sg_x5 <= clk_70;
p_phase_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant1_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_18d3979a26 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_data0_out: out std_logic_vector(23 downto 0);
tbt_cordic_data1_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_18d3979a26;
architecture structural of tddm_tbt_cordic_entity_18d3979a26 is
signal ce_35_sg_x2: std_logic;
signal ce_70_sg_x6: std_logic;
signal clk_35_sg_x2: std_logic;
signal clk_70_sg_x6: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x2 <= ce_35;
ce_70_sg_x6 <= ce_70;
clk_35_sg_x2 <= clk_35;
clk_70_sg_x6 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_data0_out <= down_sample2_q_net_x2;
tbt_cordic_data1_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d3f44a687c: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_5b94be40c5: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC"
entity tbt_cordic_entity_232cb2e43e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_232cb2e43e;
architecture structural of tbt_cordic_entity_232cb2e43e is
signal ce_1_sg_x26: std_logic;
signal ce_35_sg_x3: std_logic;
signal ce_70_sg_x7: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x26: std_logic;
signal clk_35_sg_x3: std_logic;
signal clk_70_sg_x7: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x26 <= ce_1;
ce_35_sg_x3 <= ce_35;
ce_70_sg_x7 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x26 <= clk_1;
clk_35_sg_x3 <= clk_35;
clk_70_sg_x7 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_18d3979a26: entity work.tddm_tbt_cordic_entity_18d3979a26
port map (
ce_35 => ce_35_sg_x3,
ce_70 => ce_70_sg_x7,
clk_35 => clk_35_sg_x3,
clk_70 => clk_70_sg_x7,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_data0_out => down_sample2_q_net_x4,
tbt_cordic_data1_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT/TDDM_tbt_poly_i"
entity tddm_tbt_poly_i_entity_469601736c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_poly_i_entity_469601736c;
architecture structural of tddm_tbt_poly_i_entity_469601736c is
signal ce_35_sg_x4: std_logic;
signal ce_70_sg_x8: std_logic;
signal clk_35_sg_x4: std_logic;
signal clk_70_sg_x8: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net_x1: std_logic;
signal register_q_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x4 <= ce_35;
ce_70_sg_x8 <= ce_70;
register2_q_net_x1 <= ch_in;
clk_35_sg_x4 <= clk_35;
clk_70_sg_x8 <= clk_70;
reinterpret_output_port_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register2_q_net_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register2_q_net_x1,
b => constant1_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_9ac9f65b0b is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch0_i_out: out std_logic_vector(23 downto 0);
poly35_ch0_q_out: out std_logic_vector(23 downto 0);
poly35_ch1_i_out: out std_logic_vector(23 downto 0);
poly35_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_9ac9f65b0b;
architecture structural of tddm_tbt_entity_9ac9f65b0b is
signal ce_35_sg_x6: std_logic;
signal ce_70_sg_x10: std_logic;
signal clk_35_sg_x6: std_logic;
signal clk_70_sg_x10: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x6 <= ce_35;
ce_70_sg_x10 <= ce_70;
clk_35_sg_x6 <= clk_35;
clk_70_sg_x10 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch0_i_out <= down_sample2_q_net_x2;
poly35_ch0_q_out <= down_sample2_q_net_x3;
poly35_ch1_i_out <= down_sample1_q_net_x2;
poly35_ch1_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_469601736c: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_8011b4e29e: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/Trunc"
entity trunc_entity_e5eda8a5ac is
port (
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end trunc_entity_e5eda8a5ac;
architecture structural of trunc_entity_e5eda8a5ac is
signal register1_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal slice_y_net: std_logic_vector(23 downto 0);
begin
register1_q_net_x2 <= din;
dout <= reinterpret_output_port_net_x3;
reinterpret: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x3
);
slice: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 24,
x_width => 25,
y_width => 24
)
port map (
x => register1_q_net_x2,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim"
entity tbt_poly_decim_entity_4477ec06c2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_4477ec06c2;
architecture structural of tbt_poly_decim_entity_4477ec06c2 is
signal ce_1_sg_x27: std_logic;
signal ce_35_sg_x7: std_logic;
signal ce_70_sg_x11: std_logic;
signal ce_logic_1_sg_x12: std_logic;
signal clk_1_sg_x27: std_logic;
signal clk_35_sg_x7: std_logic;
signal clk_70_sg_x11: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x12: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x27 <= ce_1;
ce_35_sg_x7 <= ce_35;
ce_70_sg_x11 <= ce_70;
ce_logic_1_sg_x12 <= ce_logic_1;
register3_q_net_x12 <= ch_in;
clk_1_sg_x27 <= clk_1;
clk_35_sg_x7 <= clk_35;
clk_70_sg_x11 <= clk_70;
register4_q_net_x11 <= i_in;
register5_q_net_x11 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_6508759a07908936c4d12ef4ec464ceb
port map (
ce => ce_1_sg_x27,
ce_35 => ce_35_sg_x7,
ce_logic_1 => ce_logic_1_sg_x12,
clk => clk_1_sg_x27,
clk_35 => clk_35_sg_x7,
clk_logic_1 => clk_1_sg_x27,
s_axis_data_tdata_path0 => register4_q_net_x11,
s_axis_data_tdata_path1 => register5_q_net_x11,
s_axis_data_tuser_chanid(0) => register3_q_net_x12,
src_ce => ce_1_sg_x27,
src_clk => clk_1_sg_x27,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_9ac9f65b0b: entity work.tddm_tbt_entity_9ac9f65b0b
port map (
ce_35 => ce_35_sg_x7,
ce_70 => ce_70_sg_x11,
clk_35 => clk_35_sg_x7,
clk_70 => clk_70_sg_x11,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch0_i_out => down_sample2_q_net_x4,
poly35_ch0_q_out => down_sample2_q_net_x5,
poly35_ch1_i_out => down_sample1_q_net_x4,
poly35_ch1_q_out => down_sample1_q_net_x5
);
trunc1_841a61ebcc: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_e5eda8a5ac: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0"
entity tbt_amp0_entity_88b1c45f0e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp0_entity_88b1c45f0e;
architecture structural of tbt_amp0_entity_88b1c45f0e is
signal ce_1_sg_x28: std_logic;
signal ce_35_sg_x8: std_logic;
signal ce_70_sg_x12: std_logic;
signal ce_logic_1_sg_x13: std_logic;
signal clk_1_sg_x28: std_logic;
signal clk_35_sg_x8: std_logic;
signal clk_70_sg_x12: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x28 <= ce_1;
ce_35_sg_x8 <= ce_35;
ce_70_sg_x12 <= ce_70;
ce_logic_1_sg_x13 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x28 <= clk_1;
clk_35_sg_x8 <= clk_35;
clk_70_sg_x12 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_232cb2e43e: entity work.tbt_cordic_entity_232cb2e43e
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_4477ec06c2: entity work.tbt_poly_decim_entity_4477ec06c2
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ce_logic_1 => ce_logic_1_sg_x13,
ch_in => register3_q_net_x13,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register4_q_net_x12,
q_in => register5_q_net_x12,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_9e99bd206d is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_ch2_out: out std_logic_vector(23 downto 0);
tbt_cordic_ch3_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_9e99bd206d;
architecture structural of tddm_tbt_cordic_entity_9e99bd206d is
signal ce_35_sg_x11: std_logic;
signal ce_70_sg_x15: std_logic;
signal clk_35_sg_x11: std_logic;
signal clk_70_sg_x15: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x11 <= ce_35;
ce_70_sg_x15 <= ce_70;
clk_35_sg_x11 <= clk_35;
clk_70_sg_x15 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_ch2_out <= down_sample2_q_net_x2;
tbt_cordic_ch3_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d22fbdac88: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_f04a48283a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC"
entity tbt_cordic_entity_9dc3371de2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_9dc3371de2;
architecture structural of tbt_cordic_entity_9dc3371de2 is
signal ce_1_sg_x29: std_logic;
signal ce_35_sg_x12: std_logic;
signal ce_70_sg_x16: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x29: std_logic;
signal clk_35_sg_x12: std_logic;
signal clk_70_sg_x16: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x29 <= ce_1;
ce_35_sg_x12 <= ce_35;
ce_70_sg_x16 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x29 <= clk_1;
clk_35_sg_x12 <= clk_35;
clk_70_sg_x16 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_baddbff1b3cb5131976384a2dda9ffff
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_9e99bd206d: entity work.tddm_tbt_cordic_entity_9e99bd206d
port map (
ce_35 => ce_35_sg_x12,
ce_70 => ce_70_sg_x16,
clk_35 => clk_35_sg_x12,
clk_70 => clk_70_sg_x16,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_ch2_out => down_sample2_q_net_x4,
tbt_cordic_ch3_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_1f4b61e651 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch2_i_out: out std_logic_vector(23 downto 0);
poly35_ch2_q_out: out std_logic_vector(23 downto 0);
poly35_ch3_i_out: out std_logic_vector(23 downto 0);
poly35_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_1f4b61e651;
architecture structural of tddm_tbt_entity_1f4b61e651 is
signal ce_35_sg_x15: std_logic;
signal ce_70_sg_x19: std_logic;
signal clk_35_sg_x15: std_logic;
signal clk_70_sg_x19: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x15 <= ce_35;
ce_70_sg_x19 <= ce_70;
clk_35_sg_x15 <= clk_35;
clk_70_sg_x19 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch2_i_out <= down_sample2_q_net_x2;
poly35_ch2_q_out <= down_sample2_q_net_x3;
poly35_ch3_i_out <= down_sample1_q_net_x2;
poly35_ch3_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_b74b709553: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_4f85d7362a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim"
entity tbt_poly_decim_entity_bb6f6b5b6a is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_bb6f6b5b6a;
architecture structural of tbt_poly_decim_entity_bb6f6b5b6a is
signal ce_1_sg_x30: std_logic;
signal ce_35_sg_x16: std_logic;
signal ce_70_sg_x20: std_logic;
signal ce_logic_1_sg_x14: std_logic;
signal clk_1_sg_x30: std_logic;
signal clk_35_sg_x16: std_logic;
signal clk_70_sg_x20: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x30 <= ce_1;
ce_35_sg_x16 <= ce_35;
ce_70_sg_x20 <= ce_70;
ce_logic_1_sg_x14 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x30 <= clk_1;
clk_35_sg_x16 <= clk_35;
clk_70_sg_x20 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_6508759a07908936c4d12ef4ec464ceb
port map (
ce => ce_1_sg_x30,
ce_35 => ce_35_sg_x16,
ce_logic_1 => ce_logic_1_sg_x14,
clk => clk_1_sg_x30,
clk_35 => clk_35_sg_x16,
clk_logic_1 => clk_1_sg_x30,
s_axis_data_tdata_path0 => register4_q_net_x12,
s_axis_data_tdata_path1 => register5_q_net_x12,
s_axis_data_tuser_chanid(0) => register3_q_net_x13,
src_ce => ce_1_sg_x30,
src_clk => clk_1_sg_x30,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_1f4b61e651: entity work.tddm_tbt_entity_1f4b61e651
port map (
ce_35 => ce_35_sg_x16,
ce_70 => ce_70_sg_x20,
clk_35 => clk_35_sg_x16,
clk_70 => clk_70_sg_x20,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch2_i_out => down_sample2_q_net_x4,
poly35_ch2_q_out => down_sample2_q_net_x5,
poly35_ch3_i_out => down_sample1_q_net_x4,
poly35_ch3_q_out => down_sample1_q_net_x5
);
trunc1_c3e3bdeec5: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_6a2a4db298: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1"
entity tbt_amp1_entity_6e98f85f9f is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp1_entity_6e98f85f9f;
architecture structural of tbt_amp1_entity_6e98f85f9f is
signal ce_1_sg_x31: std_logic;
signal ce_35_sg_x17: std_logic;
signal ce_70_sg_x21: std_logic;
signal ce_logic_1_sg_x15: std_logic;
signal clk_1_sg_x31: std_logic;
signal clk_35_sg_x17: std_logic;
signal clk_70_sg_x21: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x14: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x13: std_logic_vector(23 downto 0);
signal register5_q_net_x13: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x31 <= ce_1;
ce_35_sg_x17 <= ce_35;
ce_70_sg_x21 <= ce_70;
ce_logic_1_sg_x15 <= ce_logic_1;
register3_q_net_x14 <= ch_in;
clk_1_sg_x31 <= clk_1;
clk_35_sg_x17 <= clk_35;
clk_70_sg_x21 <= clk_70;
register4_q_net_x13 <= i_in;
register5_q_net_x13 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_9dc3371de2: entity work.tbt_cordic_entity_9dc3371de2
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_bb6f6b5b6a: entity work.tbt_poly_decim_entity_bb6f6b5b6a
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ce_logic_1 => ce_logic_1_sg_x15,
ch_in => register3_q_net_x14,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register4_q_net_x13,
q_in => register5_q_net_x13,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TDDM_tbt_amp_4ch"
entity tddm_tbt_amp_4ch_entity_9f3ac0073e is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_35: in std_logic;
ce_70: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_tbt_amp_4ch_entity_9f3ac0073e;
architecture structural of tddm_tbt_amp_4ch_entity_9f3ac0073e is
signal ce_35_sg_x20: std_logic;
signal ce_70_sg_x24: std_logic;
signal clk_35_sg_x20: std_logic;
signal clk_70_sg_x24: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
begin
p_amp_out_x6 <= amp_in0;
p_amp_out_x7 <= amp_in1;
ce_35_sg_x20 <= ce_35;
ce_70_sg_x24 <= ce_70;
p_ch_out_x7 <= ch_in0;
p_ch_out_x8 <= ch_in1;
clk_35_sg_x20 <= clk_35;
clk_70_sg_x24 <= clk_70;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_tbt_amp0_8f2b25894a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x7,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x6,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_amp1_0c4a2e4770: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x8,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x7,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp"
entity tbt_amp_entity_cbd277bb0c is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
tbt_amp0: out std_logic_vector(23 downto 0);
tbt_amp0_x0: out std_logic_vector(23 downto 0);
tbt_amp0_x1: out std_logic_vector(23 downto 0);
tbt_amp0_x2: out std_logic_vector(23 downto 0);
tbt_amp0_x3: out std_logic;
tbt_amp0_x4: out std_logic_vector(23 downto 0);
tbt_amp0_x5: out std_logic_vector(23 downto 0);
tbt_amp0_x6: out std_logic_vector(23 downto 0);
tbt_amp0_x7: out std_logic_vector(23 downto 0);
tbt_amp1: out std_logic_vector(23 downto 0);
tbt_amp1_x0: out std_logic_vector(23 downto 0);
tbt_amp1_x1: out std_logic_vector(23 downto 0);
tbt_amp1_x2: out std_logic_vector(23 downto 0);
tbt_amp1_x3: out std_logic;
tbt_amp1_x4: out std_logic_vector(23 downto 0);
tbt_amp1_x5: out std_logic_vector(23 downto 0);
tbt_amp1_x6: out std_logic_vector(23 downto 0);
tbt_amp1_x7: out std_logic_vector(23 downto 0)
);
end tbt_amp_entity_cbd277bb0c;
architecture structural of tbt_amp_entity_cbd277bb0c is
signal ce_1_sg_x32: std_logic;
signal ce_35_sg_x21: std_logic;
signal ce_70_sg_x25: std_logic;
signal ce_logic_1_sg_x16: std_logic;
signal clk_1_sg_x32: std_logic;
signal clk_35_sg_x21: std_logic;
signal clk_70_sg_x25: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x3: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x4: std_logic;
begin
ce_1_sg_x32 <= ce_1;
ce_35_sg_x21 <= ce_35;
ce_70_sg_x25 <= ce_70;
ce_logic_1_sg_x16 <= ce_logic_1;
register3_q_net_x15 <= ch_in0;
register3_q_net_x16 <= ch_in1;
clk_1_sg_x32 <= clk_1;
clk_35_sg_x21 <= clk_35;
clk_70_sg_x25 <= clk_70;
register4_q_net_x14 <= i_in0;
register4_q_net_x15 <= i_in1;
register5_q_net_x14 <= q_in0;
register5_q_net_x15 <= q_in1;
amp_out0 <= down_sample2_q_net_x24;
amp_out1 <= down_sample1_q_net_x24;
amp_out2 <= down_sample2_q_net_x25;
amp_out3 <= down_sample1_q_net_x25;
tbt_amp0 <= down_sample1_q_net_x16;
tbt_amp0_x0 <= down_sample2_q_net_x16;
tbt_amp0_x1 <= down_sample1_q_net_x17;
tbt_amp0_x2 <= down_sample2_q_net_x17;
tbt_amp0_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x3;
tbt_amp0_x4 <= down_sample1_q_net_x18;
tbt_amp0_x5 <= down_sample2_q_net_x18;
tbt_amp0_x6 <= down_sample1_q_net_x19;
tbt_amp0_x7 <= down_sample2_q_net_x19;
tbt_amp1 <= down_sample1_q_net_x20;
tbt_amp1_x0 <= down_sample2_q_net_x20;
tbt_amp1_x1 <= down_sample1_q_net_x21;
tbt_amp1_x2 <= down_sample2_q_net_x21;
tbt_amp1_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x4;
tbt_amp1_x4 <= down_sample1_q_net_x22;
tbt_amp1_x5 <= down_sample2_q_net_x22;
tbt_amp1_x6 <= down_sample1_q_net_x23;
tbt_amp1_x7 <= down_sample2_q_net_x23;
tbt_amp0_88b1c45f0e: entity work.tbt_amp0_entity_88b1c45f0e
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x15,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x14,
q_in => register5_q_net_x14,
amp_out => p_amp_out_x6,
ch_out => p_ch_out_x7,
tbt_cordic => down_sample1_q_net_x16,
tbt_cordic_x0 => down_sample2_q_net_x16,
tbt_cordic_x1 => down_sample1_q_net_x17,
tbt_cordic_x2 => down_sample2_q_net_x17,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x3,
tbt_poly_decim_x0 => down_sample1_q_net_x18,
tbt_poly_decim_x1 => down_sample2_q_net_x18,
tbt_poly_decim_x2 => down_sample1_q_net_x19,
tbt_poly_decim_x3 => down_sample2_q_net_x19
);
tbt_amp1_6e98f85f9f: entity work.tbt_amp1_entity_6e98f85f9f
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x16,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x15,
q_in => register5_q_net_x15,
amp_out => p_amp_out_x7,
ch_out => p_ch_out_x8,
tbt_cordic => down_sample1_q_net_x20,
tbt_cordic_x0 => down_sample2_q_net_x20,
tbt_cordic_x1 => down_sample1_q_net_x21,
tbt_cordic_x2 => down_sample2_q_net_x21,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x4,
tbt_poly_decim_x0 => down_sample1_q_net_x22,
tbt_poly_decim_x1 => down_sample2_q_net_x22,
tbt_poly_decim_x2 => down_sample1_q_net_x23,
tbt_poly_decim_x3 => down_sample2_q_net_x23
);
tddm_tbt_amp_4ch_9f3ac0073e: entity work.tddm_tbt_amp_4ch_entity_9f3ac0073e
port map (
amp_in0 => p_amp_out_x6,
amp_in1 => p_amp_out_x7,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ch_in0 => p_ch_out_x7,
ch_in1 => p_ch_out_x8,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
amp_out0 => down_sample2_q_net_x24,
amp_out1 => down_sample1_q_net_x24,
amp_out2 => down_sample2_q_net_x25,
amp_out3 => down_sample1_q_net_x25
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix/TDM_mix_ch0_1"
entity tdm_mix_ch0_1_entity_b9bb73dd5f is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_mix_ch0_1_entity_b9bb73dd5f;
architecture structural of tdm_mix_ch0_1_entity_b9bb73dd5f is
signal ce_1_sg_x33: std_logic;
signal ce_2_sg_x31: std_logic;
signal ce_logic_1_sg_x17: std_logic;
signal clk_1_sg_x33: std_logic;
signal clk_2_sg_x31: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register_q_net_x17: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x8: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x9: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x33 <= ce_1;
ce_2_sg_x31 <= ce_2;
ce_logic_1_sg_x17 <= ce_logic_1;
clk_1_sg_x33 <= clk_1;
clk_2_sg_x31 <= clk_2;
reinterpret2_output_port_net_x9 <= din_ch0;
reinterpret2_output_port_net_x8 <= din_ch1;
constant10_op_net_x0 <= rst;
ch_out <= register1_q_net_x4;
dout <= register_q_net_x17;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x17,
clk => clk_1_sg_x33,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
sel(0) => mux_sel1_op_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op(0) => mux_sel1_op_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register1_q_net_x4
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x17
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x9,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x8,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix"
entity tdm_mix_entity_54ce67e6e8 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
dout0: out std_logic_vector(23 downto 0);
dout1: out std_logic_vector(23 downto 0)
);
end tdm_mix_entity_54ce67e6e8;
architecture structural of tdm_mix_entity_54ce67e6e8 is
signal ce_1_sg_x35: std_logic;
signal ce_2_sg_x33: std_logic;
signal ce_logic_1_sg_x19: std_logic;
signal clk_1_sg_x35: std_logic;
signal clk_2_sg_x33: std_logic;
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register_q_net_x19: std_logic_vector(23 downto 0);
signal register_q_net_x20: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x11: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x12: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x13: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x14: std_logic_vector(23 downto 0);
begin
ce_1_sg_x35 <= ce_1;
ce_2_sg_x33 <= ce_2;
ce_logic_1_sg_x19 <= ce_logic_1;
clk_1_sg_x35 <= clk_1;
clk_2_sg_x33 <= clk_2;
reinterpret2_output_port_net_x14 <= din_ch0;
reinterpret2_output_port_net_x11 <= din_ch1;
reinterpret2_output_port_net_x12 <= din_ch2;
reinterpret2_output_port_net_x13 <= din_ch3;
ch_out0 <= register1_q_net_x6;
ch_out1 <= register1_q_net_x7;
dout0 <= register_q_net_x19;
dout1 <= register_q_net_x20;
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
tdm_mix_ch0_1_b9bb73dd5f: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x14,
din_ch1 => reinterpret2_output_port_net_x11,
rst => constant10_op_net_x0,
ch_out => register1_q_net_x6,
dout => register_q_net_x19
);
tdm_mix_ch0_2_e9327141fc: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x12,
din_ch1 => reinterpret2_output_port_net_x13,
rst => constant11_op_net_x0,
ch_out => register1_q_net_x7,
dout => register_q_net_x20
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit"
entity tdm_monit_entity_6e38292ecb is
port (
ce_1: in std_logic;
ce_2240: in std_logic;
ce_560: in std_logic;
ce_logic_560: in std_logic;
clk_1: in std_logic;
clk_2240: in std_logic;
clk_560: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end tdm_monit_entity_6e38292ecb;
architecture structural of tdm_monit_entity_6e38292ecb is
signal ce_1_sg_x36: std_logic;
signal ce_2240_sg_x26: std_logic;
signal ce_560_sg_x2: std_logic;
signal ce_logic_560_sg_x2: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal clk_1_sg_x36: std_logic;
signal clk_2240_sg_x26: std_logic;
signal clk_560_sg_x2: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal mux_sel_op_net: std_logic_vector(1 downto 0);
signal mux_y_net: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x36 <= ce_1;
ce_2240_sg_x26 <= ce_2240;
ce_560_sg_x2 <= ce_560;
ce_logic_560_sg_x2 <= ce_logic_560;
clk_1_sg_x36 <= clk_1;
clk_2240_sg_x26 <= clk_2240;
clk_560_sg_x2 <= clk_560;
down_sample2_q_net_x18 <= din_ch0;
down_sample1_q_net_x18 <= din_ch1;
down_sample2_q_net_x19 <= din_ch2;
down_sample1_q_net_x19 <= din_ch3;
constant10_op_net_x0 <= rst;
ch_out <= ch_out_x2;
dout <= dout_x2;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_560_sg_x2,
clk => clk_560_sg_x2,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => ch_out_x2
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => mux_y_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => dout_x2
);
mux: entity work.mux_f062741975
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net,
y => mux_y_net
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_eb46eda57512a5a4",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x36,
clk => clk_1_sg_x36,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op => mux_sel_op_net
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample"
entity downsample_entity_f33f90217c is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(1 downto 0);
dout: out std_logic_vector(1 downto 0)
);
end downsample_entity_f33f90217c;
architecture structural of downsample_entity_f33f90217c is
signal ce_1_sg_x37: std_logic;
signal ce_2500_sg_x0: std_logic;
signal ce_5600000_sg_x8: std_logic;
signal clk_1_sg_x37: std_logic;
signal clk_2500_sg_x0: std_logic;
signal clk_5600000_sg_x8: std_logic;
signal down_sample5_q_net: std_logic_vector(1 downto 0);
signal down_sample_q_net_x0: std_logic_vector(1 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
begin
ce_1_sg_x37 <= ce_1;
ce_2500_sg_x0 <= ce_2500;
ce_5600000_sg_x8 <= ce_5600000;
clk_1_sg_x37 <= clk_1;
clk_2500_sg_x0 <= clk_2500;
clk_5600000_sg_x8 <= clk_5600000;
mux_sel_op_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x8,
dest_clk => clk_5600000_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x0,
src_clk => clk_2500_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net_x0,
dest_ce => ce_2500_sg_x0,
dest_clk => clk_2500_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x37,
src_clk => clk_1_sg_x37,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample1"
entity downsample1_entity_312d531c6b is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample1_entity_312d531c6b;
architecture structural of downsample1_entity_312d531c6b is
signal ce_1_sg_x38: std_logic;
signal ce_2500_sg_x1: std_logic;
signal ce_5600000_sg_x9: std_logic;
signal clk_1_sg_x38: std_logic;
signal clk_2500_sg_x1: std_logic;
signal clk_5600000_sg_x9: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
begin
ce_1_sg_x38 <= ce_1;
ce_2500_sg_x1 <= ce_2500;
ce_5600000_sg_x9 <= ce_5600000;
clk_1_sg_x38 <= clk_1;
clk_2500_sg_x1 <= clk_2500;
clk_5600000_sg_x9 <= clk_5600000;
mux_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x9,
dest_clk => clk_5600000_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x1,
src_clk => clk_2500_sg_x1,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => mux_y_net_x0,
dest_ce => ce_2500_sg_x1,
dest_clk => clk_2500_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x38,
src_clk => clk_1_sg_x38,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1"
entity tdm_monit_1_entity_746ecf54b0 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
ce_logic_5600000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din_ch0: in std_logic_vector(25 downto 0);
din_ch1: in std_logic_vector(25 downto 0);
din_ch2: in std_logic_vector(25 downto 0);
din_ch3: in std_logic_vector(25 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end tdm_monit_1_entity_746ecf54b0;
architecture structural of tdm_monit_1_entity_746ecf54b0 is
signal ce_1_sg_x39: std_logic;
signal ce_22400000_sg_x10: std_logic;
signal ce_2500_sg_x2: std_logic;
signal ce_5600000_sg_x10: std_logic;
signal ce_logic_5600000_sg_x0: std_logic;
signal clk_1_sg_x39: std_logic;
signal clk_22400000_sg_x10: std_logic;
signal clk_2500_sg_x2: std_logic;
signal clk_5600000_sg_x10: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant11_op_net_x0: std_logic;
signal down_sample_q_net_x2: std_logic_vector(1 downto 0);
signal down_sample_q_net_x3: std_logic_vector(25 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x39 <= ce_1;
ce_22400000_sg_x10 <= ce_22400000;
ce_2500_sg_x2 <= ce_2500;
ce_5600000_sg_x10 <= ce_5600000;
ce_logic_5600000_sg_x0 <= ce_logic_5600000;
clk_1_sg_x39 <= clk_1;
clk_22400000_sg_x10 <= clk_22400000;
clk_2500_sg_x2 <= clk_2500;
clk_5600000_sg_x10 <= clk_5600000;
concat_y_net_x0 <= din_ch0;
concat1_y_net_x0 <= din_ch1;
concat2_y_net_x0 <= din_ch2;
concat3_y_net_x0 <= din_ch3;
constant11_op_net_x0 <= rst;
ch_out <= down_sample_q_net_x2;
dout <= down_sample_q_net_x3;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 26,
q_width => 1
)
port map (
ce => ce_logic_5600000_sg_x0,
clk => clk_5600000_sg_x10,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
downsample1_312d531c6b: entity work.downsample1_entity_312d531c6b
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_y_net_x0,
dout => down_sample_q_net_x3
);
downsample_f33f90217c: entity work.downsample_entity_f33f90217c
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_sel_op_net_x0,
dout => down_sample_q_net_x2
);
mux: entity work.mux_187c900130
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net_x0,
y => mux_y_net_x0
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_eb46eda57512a5a4",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x39,
clk => clk_1_sg_x39,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op => mux_sel_op_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat1_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat2_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat3_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/convert_filt"
entity convert_filt_entity_fda412c1bf is
port (
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end convert_filt_entity_fda412c1bf;
architecture structural of convert_filt_entity_fda412c1bf is
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x0: std_logic_vector(24 downto 0);
begin
down_sample_q_net_x4 <= din;
dout <= reinterpret5_output_port_net_x0;
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample_q_net_x4,
dout => extractor1_dout_net
);
reinterpret5: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret5_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En"
entity datareg_en_entity_79473f9ed1 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en_entity_79473f9ed1;
architecture structural of datareg_en_entity_79473f9ed1 is
signal ce_1_sg_x40: std_logic;
signal clk_1_sg_x40: std_logic;
signal divider_dout_valid_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x40 <= ce_1;
clk_1_sg_x40 <= clk_1;
reinterpret1_output_port_net_x0 <= din;
divider_dout_valid_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d(0) => divider_dout_valid_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d => reinterpret1_output_port_net_x0,
en(0) => divider_dout_valid_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En3"
entity datareg_en3_entity_6643090018 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en3_entity_6643090018;
architecture structural of datareg_en3_entity_6643090018 is
signal ce_1_sg_x43: std_logic;
signal clk_1_sg_x43: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal delay1_q_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x43 <= ce_1;
clk_1_sg_x43 <= clk_1;
convert_dout_net_x0 <= din;
delay1_q_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d(0) => delay1_q_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d => convert_dout_net_x0,
en(0) => delay1_q_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/pulse_stretcher"
entity pulse_stretcher_entity_9893378b63 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
clr: in std_logic;
pulse_in: in std_logic;
extd_out: out std_logic
);
end pulse_stretcher_entity_9893378b63;
architecture structural of pulse_stretcher_entity_9893378b63 is
signal ce_1_sg_x44: std_logic;
signal ce_70_x0: std_logic;
signal clk_1_sg_x44: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register_q_net: std_logic;
begin
ce_1_sg_x44 <= ce_1;
clk_1_sg_x44 <= clk_1;
ce_70_x0 <= clr;
register1_q_net_x1 <= pulse_in;
extd_out <= logical3_y_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
clr => '0',
ip(0) => ce_70_x0,
op(0) => inverter_op_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net,
d1(0) => inverter_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => logical1_y_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => register_q_net,
y(0) => logical3_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
d(0) => logical2_y_net,
en => "1",
rst => "0",
q(0) => register_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb"
entity delta_sigma_fofb_entity_ee61e649ea is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_logic_2240: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_fofb_entity_ee61e649ea;
architecture structural of delta_sigma_fofb_entity_ee61e649ea is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x52: std_logic;
signal ce_2240_sg_x27: std_logic;
signal ce_2_sg_x34: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_2240_sg_x0: std_logic;
signal clk_1_sg_x52: std_logic;
signal clk_2240_sg_x27: std_logic;
signal clk_2_sg_x34: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_fofb_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x20 <= a;
down_sample1_q_net_x20 <= b;
down_sample2_q_net_x21 <= c;
ce_1_sg_x52 <= ce_1;
ce_2_sg_x34 <= ce_2;
ce_2240_sg_x27 <= ce_2240;
ce_logic_2240_sg_x0 <= ce_logic_2240;
clk_1_sg_x52 <= clk_1;
clk_2_sg_x34 <= clk_2;
clk_2240_sg_x27 <= clk_2240;
down_sample1_q_net_x21 <= d;
del_sig_div_fofb_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x21,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_2240_sg_x0,
clk => clk_2240_sg_x27,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_3225c09afc: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_5b5f4b61b7: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_6643090018: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_79473f9ed1: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x34,
src_clk => clk_2_sg_x34,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_f6401a1a3d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_38948aaba0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_816d954034: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_5d505b900f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_bee4540339: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_f82d879b1c: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_2406c4a105: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_9893378b63: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x34,
clk => clk_2_sg_x34,
d => del_sig_div_fofb_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample1"
entity downsample1_entity_4c88924603 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample1_entity_4c88924603;
architecture structural of downsample1_entity_4c88924603 is
signal ce_1_sg_x57: std_logic;
signal ce_22400000_sg_x11: std_logic;
signal ce_5000_sg_x0: std_logic;
signal clk_1_sg_x57: std_logic;
signal clk_22400000_sg_x11: std_logic;
signal clk_5000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x57 <= ce_1;
ce_22400000_sg_x11 <= ce_22400000;
ce_5000_sg_x0 <= ce_5000;
clk_1_sg_x57 <= clk_1;
clk_22400000_sg_x11 <= clk_22400000;
clk_5000_sg_x0 <= clk_5000;
register13_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x11,
dest_clk => clk_22400000_sg_x11,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x0,
src_clk => clk_5000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net_x0,
dest_ce => ce_5000_sg_x0,
dest_clk => clk_5000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x57,
src_clk => clk_1_sg_x57,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample2"
entity downsample2_entity_891f07b1a7 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic;
dout: out std_logic
);
end downsample2_entity_891f07b1a7;
architecture structural of downsample2_entity_891f07b1a7 is
signal ce_1_sg_x58: std_logic;
signal ce_22400000_sg_x12: std_logic;
signal ce_5000_sg_x1: std_logic;
signal clk_1_sg_x58: std_logic;
signal clk_22400000_sg_x12: std_logic;
signal clk_5000_sg_x1: std_logic;
signal down_sample5_q_net: std_logic;
signal down_sample_q_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
begin
ce_1_sg_x58 <= ce_1;
ce_22400000_sg_x12 <= ce_22400000;
ce_5000_sg_x1 <= ce_5000;
clk_1_sg_x58 <= clk_1;
clk_22400000_sg_x12 <= clk_22400000;
clk_5000_sg_x1 <= clk_5000;
logical3_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => down_sample5_q_net,
dest_ce => ce_22400000_sg_x12,
dest_clk => clk_22400000_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x1,
src_clk => clk_5000_sg_x1,
src_clr => '0',
q(0) => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_5000_sg_x1,
dest_clk => clk_5000_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x58,
src_clk => clk_1_sg_x58,
src_clr => '0',
q(0) => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample3"
entity downsample3_entity_dba589aaee is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample3_entity_dba589aaee;
architecture structural of downsample3_entity_dba589aaee is
signal ce_1_sg_x59: std_logic;
signal ce_22400000_sg_x13: std_logic;
signal ce_5000_sg_x2: std_logic;
signal clk_1_sg_x59: std_logic;
signal clk_22400000_sg_x13: std_logic;
signal clk_5000_sg_x2: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x59 <= ce_1;
ce_22400000_sg_x13 <= ce_22400000;
ce_5000_sg_x2 <= ce_5000;
clk_1_sg_x59 <= clk_1;
clk_22400000_sg_x13 <= clk_22400000;
clk_5000_sg_x2 <= clk_5000;
register12_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x13,
dest_clk => clk_22400000_sg_x13,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x2,
src_clk => clk_5000_sg_x2,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net_x0,
dest_ce => ce_5000_sg_x2,
dest_clk => clk_5000_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x59,
src_clk => clk_1_sg_x59,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample7"
entity downsample7_entity_b85055cb62 is
port (
ce_10000: in std_logic;
ce_2: in std_logic;
ce_44800000: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_44800000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample7_entity_b85055cb62;
architecture structural of downsample7_entity_b85055cb62 is
signal ce_10000_sg_x0: std_logic;
signal ce_2_sg_x35: std_logic;
signal ce_44800000_sg_x0: std_logic;
signal clk_10000_sg_x0: std_logic;
signal clk_2_sg_x35: std_logic;
signal clk_44800000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
begin
ce_10000_sg_x0 <= ce_10000;
ce_2_sg_x35 <= ce_2;
ce_44800000_sg_x0 <= ce_44800000;
clk_10000_sg_x0 <= clk_10000;
clk_2_sg_x35 <= clk_2;
clk_44800000_sg_x0 <= clk_44800000;
register14_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_44800000_sg_x0,
dest_clk => clk_44800000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_10000_sg_x0,
src_clk => clk_10000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net_x0,
dest_ce => ce_10000_sg_x0,
dest_clk => clk_10000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x35,
src_clk => clk_2_sg_x35,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad"
entity upsample_copy_pad_entity_86c97eac4f is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad_entity_86c97eac4f;
architecture structural of upsample_copy_pad_entity_86c97eac4f is
signal ce_1_sg_x73: std_logic;
signal ce_22400000_sg_x19: std_logic;
signal ce_4480_sg_x0: std_logic;
signal clk_1_sg_x73: std_logic;
signal clk_22400000_sg_x19: std_logic;
signal clk_4480_sg_x0: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x73 <= ce_1;
ce_22400000_sg_x19 <= ce_22400000;
ce_4480_sg_x0 <= ce_4480;
clk_1_sg_x73 <= clk_1;
clk_22400000_sg_x19 <= clk_22400000;
clk_4480_sg_x0 <= clk_4480;
register10_q_net_x0 <= din;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x73,
dest_clk => clk_1_sg_x73,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x0,
src_clk => clk_4480_sg_x0,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net_x0,
dest_ce => ce_4480_sg_x0,
dest_clk => clk_4480_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x19,
src_clk => clk_22400000_sg_x19,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad1"
entity upsample_copy_pad1_entity_edde199d79 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din_x0: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad1_entity_edde199d79;
architecture structural of upsample_copy_pad1_entity_edde199d79 is
signal ce_1_sg_x74: std_logic;
signal ce_22400000_sg_x20: std_logic;
signal ce_4480_sg_x1: std_logic;
signal clk_1_sg_x74: std_logic;
signal clk_22400000_sg_x20: std_logic;
signal clk_4480_sg_x1: std_logic;
signal din_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x74 <= ce_1;
ce_22400000_sg_x20 <= ce_22400000;
ce_4480_sg_x1 <= ce_4480;
clk_1_sg_x74 <= clk_1;
clk_22400000_sg_x20 <= clk_22400000;
clk_4480_sg_x1 <= clk_4480;
din_x1 <= din_x0;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x74,
dest_clk => clk_1_sg_x74,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x1,
src_clk => clk_4480_sg_x1,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din_x1,
dest_ce => ce_4480_sg_x1,
dest_clk => clk_4480_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x20,
src_clk => clk_22400000_sg_x20,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_zero_pad"
entity upsample_zero_pad_entity_e334b63be9 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic;
dout: out std_logic
);
end upsample_zero_pad_entity_e334b63be9;
architecture structural of upsample_zero_pad_entity_e334b63be9 is
signal assert13_dout_net_x0: std_logic;
signal ce_1_sg_x77: std_logic;
signal ce_22400000_sg_x23: std_logic;
signal ce_4480_sg_x4: std_logic;
signal clk_1_sg_x77: std_logic;
signal clk_22400000_sg_x23: std_logic;
signal clk_4480_sg_x4: std_logic;
signal up_sample1_q_net_x1: std_logic;
signal up_sample5_q_net: std_logic;
begin
ce_1_sg_x77 <= ce_1;
ce_22400000_sg_x23 <= ce_22400000;
ce_4480_sg_x4 <= ce_4480;
clk_1_sg_x77 <= clk_1;
clk_22400000_sg_x23 <= clk_22400000;
clk_4480_sg_x4 <= clk_4480;
assert13_dout_net_x0 <= din;
dout <= up_sample1_q_net_x1;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => up_sample5_q_net,
dest_ce => ce_1_sg_x77,
dest_clk => clk_1_sg_x77,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x4,
src_clk => clk_4480_sg_x4,
src_clr => '0',
q(0) => up_sample1_q_net_x1
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert13_dout_net_x0,
dest_ce => ce_4480_sg_x4,
dest_clk => clk_4480_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x23,
src_clk => clk_22400000_sg_x23,
src_clr => '0',
q(0) => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit"
entity delta_sigma_monit_entity_a8f8b81626 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_2: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_logic_22400000: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_monit_entity_a8f8b81626;
architecture structural of delta_sigma_monit_entity_a8f8b81626 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert13_dout_net_x3: std_logic;
signal assert2_dout_net_x0: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert9_dout_net_x1: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_10000_sg_x1: std_logic;
signal ce_1_sg_x81: std_logic;
signal ce_22400000_sg_x27: std_logic;
signal ce_2_sg_x36: std_logic;
signal ce_44800000_sg_x1: std_logic;
signal ce_4480_sg_x8: std_logic;
signal ce_5000_sg_x8: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_22400000_sg_x0: std_logic;
signal clk_10000_sg_x1: std_logic;
signal clk_1_sg_x81: std_logic;
signal clk_22400000_sg_x27: std_logic;
signal clk_2_sg_x36: std_logic;
signal clk_44800000_sg_x1: std_logic;
signal clk_4480_sg_x8: std_logic;
signal clk_5000_sg_x8: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_monit_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din_x1: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch_x0: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal down_sample_q_net_x1: std_logic;
signal down_sample_q_net_x2: std_logic_vector(24 downto 0);
signal down_sample_q_net_x3: std_logic;
signal down_sample_q_net_x4: std_logic_vector(24 downto 0);
signal down_sample_q_net_x5: std_logic;
signal down_sample_q_net_x6: std_logic_vector(25 downto 0);
signal down_sample_q_net_x7: std_logic_vector(24 downto 0);
signal down_sample_q_net_x8: std_logic;
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal register11_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x2: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x3: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x4: std_logic;
signal up_sample1_q_net_x5: std_logic;
signal up_sample1_q_net_x6: std_logic;
signal up_sample1_q_net_x7: std_logic;
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x5 <= a;
down_sample1_q_net_x5 <= b;
down_sample3_q_net_x5 <= c;
ce_1_sg_x81 <= ce_1;
ce_10000_sg_x1 <= ce_10000;
ce_2_sg_x36 <= ce_2;
ce_22400000_sg_x27 <= ce_22400000;
ce_4480_sg_x8 <= ce_4480;
ce_44800000_sg_x1 <= ce_44800000;
ce_5000_sg_x8 <= ce_5000;
ce_logic_22400000_sg_x0 <= ce_logic_22400000;
clk_1_sg_x81 <= clk_1;
clk_10000_sg_x1 <= clk_10000;
clk_2_sg_x36 <= clk_2;
clk_22400000_sg_x27 <= clk_22400000;
clk_4480_sg_x8 <= clk_4480;
clk_44800000_sg_x1 <= clk_44800000;
clk_5000_sg_x8 <= clk_5000;
down_sample4_q_net_x5 <= d;
del_sig_div_monit_thres_i_net_x0 <= ds_thres;
q <= assert4_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert10_dout_net_x1;
sum_x0 <= assert5_dout_net_x1;
x <= assert11_dout_net_x1;
x_valid <= assert12_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x1,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x2,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x3,
dout(0) => assert12_dout_net_x1
);
assert13: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert13_dout_net_x3
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert2_dout_net_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x7,
dout => assert4_dout_net_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x0,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x4,
dout => dout_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x5,
dout(0) => valid_ds_down_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x8,
dout(0) => assert9_dout_net_x1
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample3_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_22400000_sg_x0,
clk => clk_22400000_sg_x27,
d(0) => assert13_dout_net_x3,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_0658df0e73: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_b216d22f41: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_352b935ccb: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_8be792d5b9: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d(0) => logical3_y_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
downsample1_4c88924603: entity work.downsample1_entity_4c88924603
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register13_q_net_x0,
dout => down_sample_q_net_x0
);
downsample2_891f07b1a7: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x4,
dout => down_sample_q_net_x1
);
downsample3_dba589aaee: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register12_q_net_x0,
dout => down_sample_q_net_x2
);
downsample4_c9912c17cb: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x3,
dout => down_sample_q_net_x3
);
downsample5_5d411d5dea: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => dout_stretch_x0,
dout => down_sample_q_net_x4
);
downsample6_d7e68015e5: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x1,
dout => down_sample_q_net_x5
);
downsample7_b85055cb62: entity work.downsample7_entity_b85055cb62
port map (
ce_10000 => ce_10000_sg_x1,
ce_2 => ce_2_sg_x36,
ce_44800000 => ce_44800000_sg_x1,
clk_10000 => clk_10000_sg_x1,
clk_2 => clk_2_sg_x36,
clk_44800000 => clk_44800000_sg_x1,
din => register14_q_net_x0,
dout => down_sample_q_net_x6
);
downsample8_69d7284f0d: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register11_q_net_x0,
dout => down_sample_q_net_x7
);
downsample9_f5ac9b8db2: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x2,
dout => down_sample_q_net_x8
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_427f70e3c7: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x2
);
pulse_stretcher2_9a61283281: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x3
);
pulse_stretcher3_864c3e16a6: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x4
);
pulse_stretcher4_8dfd1c8928: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert6_dout_net_x0,
pulse_in => up_sample1_q_net_x6,
extd_out => logical3_y_net_x0
);
pulse_stretcher5_ac376595d0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x0,
pulse_in => up_sample1_q_net_x5,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_694b81e6b2: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert2_dout_net_x0,
pulse_in => up_sample1_q_net_x4,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_bb8174efbd: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x1,
pulse_in => up_sample1_q_net_x7,
extd_out => logical3_y_net_x7
);
pulse_stretcher_6bf297451d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x1
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net_x0
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x36,
clk => clk_2_sg_x36,
d => del_sig_div_monit_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net_x0
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data_x0
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch_x0
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x3,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x2,
output_port => divisor_data
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x1,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x0,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data_x0,
b => down_sample_q_net_x6,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
upsample_copy_pad1_edde199d79: entity work.upsample_copy_pad1_entity_edde199d79
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din_x0 => din_x1,
dout => up_sample1_q_net_x1
);
upsample_copy_pad2_46599e345b: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => divisor_data_x0,
dout => up_sample1_q_net_x2
);
upsample_copy_pad3_3571daa38f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register7_q_net_x0,
dout => up_sample1_q_net_x3
);
upsample_copy_pad_86c97eac4f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register10_q_net_x0,
dout => up_sample1_q_net_x0
);
upsample_zero_pad1_2044d1ec3f: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x5
);
upsample_zero_pad2_7f2f8f8620: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x6
);
upsample_zero_pad3_f0b4acbf28: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x7
);
upsample_zero_pad_e334b63be9: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x4
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_tbt"
entity delta_sigma_tbt_entity_bbfa8a8a69 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_70: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_tbt_entity_bbfa8a8a69;
architecture structural of delta_sigma_tbt_entity_bbfa8a8a69 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x94: std_logic;
signal ce_2_sg_x37: std_logic;
signal ce_70_sg_x26: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_70_sg_x0: std_logic;
signal clk_1_sg_x94: std_logic;
signal clk_2_sg_x37: std_logic;
signal clk_70_sg_x26: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_tbt_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x26 <= a;
down_sample1_q_net_x26 <= b;
down_sample2_q_net_x27 <= c;
ce_1_sg_x94 <= ce_1;
ce_2_sg_x37 <= ce_2;
ce_70_sg_x26 <= ce_70;
ce_logic_70_sg_x0 <= ce_logic_70;
clk_1_sg_x94 <= clk_1;
clk_2_sg_x37 <= clk_2;
clk_70_sg_x26 <= clk_70;
down_sample1_q_net_x27 <= d;
del_sig_div_tbt_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x26,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_293aa5f110d040c2",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x27,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_70_sg_x0,
clk => clk_70_sg_x26,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_e5d0399944: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_02a2053e69: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_78179f99cc: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_ed948c360a: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_44053abf11139d96",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x37,
src_clk => clk_2_sg_x37,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_eef5ee33be: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_6f5c3f41cf: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_e720dfd76f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_0a5eb3f903: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_b95a604b09: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_e7fb2961d9: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_6e7eb70147: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_f661707a58: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x37,
clk => clk_2_sg_x37,
d => del_sig_div_tbt_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_3537d66a2361cd1e",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_47dc3a44bd8d9df86e42dac34ee6a9fc
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1/format1"
entity format1_entity_a98b06306e is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end format1_entity_a98b06306e;
architecture structural of format1_entity_a98b06306e is
signal ce_56000000_sg_x0: std_logic;
signal clk_56000000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net: std_logic_vector(25 downto 0);
begin
ce_56000000_sg_x0 <= ce_56000000;
clk_56000000_sg_x0 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 24,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 24,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_56000000_sg_x0,
clk => clk_56000000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pos_1_c_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1"
entity cast1_entity_3d447d0833 is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
data_in: in std_logic_vector(25 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(24 downto 0);
vld_out: out std_logic
);
end cast1_entity_3d447d0833;
architecture structural of cast1_entity_3d447d0833 is
signal ce_56000000_sg_x1: std_logic;
signal clk_56000000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_56000000_sg_x1 <= ce_56000000;
clk_56000000_sg_x1 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x1 <= data_in;
monit_pos_1_c_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
vld_out <= register1_q_net_x0;
format1_a98b06306e: entity work.format1_entity_a98b06306e
port map (
ce_56000000 => ce_56000000_sg_x1,
clk_56000000 => clk_56000000_sg_x1,
din => monit_pos_1_c_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out/TDDM_monit_pos_1_out_int"
entity tddm_monit_pos_1_out_int_entity_3405798202 is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_224000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout_ch0: out std_logic_vector(25 downto 0);
dout_ch1: out std_logic_vector(25 downto 0);
dout_ch2: out std_logic_vector(25 downto 0);
dout_ch3: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_int_entity_3405798202;
architecture structural of tddm_monit_pos_1_out_int_entity_3405798202 is
signal ce_224000000_sg_x4: std_logic;
signal ce_56000000_sg_x2: std_logic;
signal clk_224000000_sg_x4: std_logic;
signal clk_56000000_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(25 downto 0);
signal register2_q_net: std_logic_vector(25 downto 0);
signal register3_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x1: std_logic_vector(1 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_224000000_sg_x4 <= ce_224000000;
ce_56000000_sg_x2 <= ce_56000000;
register_q_net_x1 <= ch_in;
clk_224000000_sg_x4 <= clk_224000000;
clk_56000000_sg_x2 <= clk_56000000;
concat_y_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register1_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register_q_net_x0,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register2_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register3_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net_x0
);
relational: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant1_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant3_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant4_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out"
entity tddm_monit_pos_1_out_entity_1d58a51dbf is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
clk_224000000: in std_logic;
clk_56000000: in std_logic;
monit_pos_1_ch_in: in std_logic_vector(1 downto 0);
monit_pos_1_din: in std_logic_vector(25 downto 0);
monit_pos_1_q_out: out std_logic_vector(25 downto 0);
monit_pos_1_sum_out: out std_logic_vector(25 downto 0);
monit_pos_1_x_out: out std_logic_vector(25 downto 0);
monit_pos_1_y_out: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_entity_1d58a51dbf;
architecture structural of tddm_monit_pos_1_out_entity_1d58a51dbf is
signal ce_224000000_sg_x5: std_logic;
signal ce_56000000_sg_x3: std_logic;
signal clk_224000000_sg_x5: std_logic;
signal clk_56000000_sg_x3: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
begin
ce_224000000_sg_x5 <= ce_224000000;
ce_56000000_sg_x3 <= ce_56000000;
clk_224000000_sg_x5 <= clk_224000000;
clk_56000000_sg_x3 <= clk_56000000;
register_q_net_x2 <= monit_pos_1_ch_in;
concat_y_net_x1 <= monit_pos_1_din;
monit_pos_1_q_out <= down_sample3_q_net_x1;
monit_pos_1_sum_out <= down_sample4_q_net_x1;
monit_pos_1_x_out <= down_sample2_q_net_x1;
monit_pos_1_y_out <= down_sample1_q_net_x1;
tddm_monit_pos_1_out_int_3405798202: entity work.tddm_monit_pos_1_out_int_entity_3405798202
port map (
ce_224000000 => ce_224000000_sg_x5,
ce_56000000 => ce_56000000_sg_x3,
ch_in => register_q_net_x2,
clk_224000000 => clk_224000000_sg_x5,
clk_56000000 => clk_56000000_sg_x3,
din => concat_y_net_x1,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1"
entity monit_pos_1_entity_522c8cf08d is
port (
ce_1: in std_logic;
ce_224000000: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_logic_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_224000000: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(24 downto 0);
monit_1_pos_q: out std_logic_vector(24 downto 0);
monit_1_pos_x: out std_logic_vector(24 downto 0);
monit_1_pos_y: out std_logic_vector(24 downto 0);
monit_1_sum: out std_logic_vector(24 downto 0);
monit_1_vld_q: out std_logic;
monit_1_vld_sum: out std_logic;
monit_1_vld_x: out std_logic;
monit_1_vld_y: out std_logic;
monit_pos_1_c_x0: out std_logic
);
end monit_pos_1_entity_522c8cf08d;
architecture structural of monit_pos_1_entity_522c8cf08d is
signal ce_1_sg_x95: std_logic;
signal ce_224000000_sg_x6: std_logic;
signal ce_56000000_sg_x4: std_logic;
signal ce_5600000_sg_x11: std_logic;
signal ce_logic_5600000_sg_x1: std_logic;
signal clk_1_sg_x95: std_logic;
signal clk_224000000_sg_x6: std_logic;
signal clk_56000000_sg_x4: std_logic;
signal clk_5600000_sg_x11: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal extractor1_vld_out_net: std_logic;
signal extractor2_dout_net: std_logic_vector(24 downto 0);
signal extractor2_vld_out_net: std_logic;
signal extractor3_dout_net: std_logic_vector(24 downto 0);
signal extractor3_vld_out_net: std_logic;
signal extractor4_dout_net: std_logic_vector(24 downto 0);
signal extractor4_vld_out_net: std_logic;
signal monit_pos_1_c_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
begin
ce_1_sg_x95 <= ce_1;
ce_224000000_sg_x6 <= ce_224000000;
ce_5600000_sg_x11 <= ce_5600000;
ce_56000000_sg_x4 <= ce_56000000;
ce_logic_5600000_sg_x1 <= ce_logic_5600000;
down_sample_q_net_x3 <= ch_in;
clk_1_sg_x95 <= clk_1;
clk_224000000_sg_x6 <= clk_224000000;
clk_5600000_sg_x11 <= clk_5600000;
clk_56000000_sg_x4 <= clk_56000000;
reinterpret5_output_port_net_x1 <= din;
monit_1_pos_q <= reinterpret2_output_port_net_x1;
monit_1_pos_x <= reinterpret3_output_port_net_x1;
monit_1_pos_y <= reinterpret1_output_port_net_x1;
monit_1_sum <= reinterpret4_output_port_net_x1;
monit_1_vld_q <= ufix_to_bool2_dout_net_x1;
monit_1_vld_sum <= ufix_to_bool3_dout_net_x1;
monit_1_vld_x <= ufix_to_bool_dout_net_x1;
monit_1_vld_y <= ufix_to_bool1_dout_net_x1;
monit_pos_1_c_x0 <= monit_pos_1_c_event_s_data_chanid_incorrect_net_x0;
cast1_3d447d0833: entity work.cast1_entity_3d447d0833
port map (
ce_56000000 => ce_56000000_sg_x4,
clk_56000000 => clk_56000000_sg_x4,
data_in => monit_pos_1_c_m_axis_data_tdata_net_x1,
en => monit_pos_1_c_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0,
vld_out => register1_q_net_x0
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register1_q_net_x0,
in1 => reinterpret5_output_port_net,
y => concat_y_net_x1
);
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample3_q_net_x1,
dout => extractor1_dout_net,
vld_out(0) => extractor1_vld_out_net
);
extractor2: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample1_q_net_x1,
dout => extractor2_dout_net,
vld_out(0) => extractor2_vld_out_net
);
extractor3: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample4_q_net_x1,
dout => extractor3_dout_net,
vld_out(0) => extractor3_vld_out_net
);
extractor4: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample2_q_net_x1,
dout => extractor4_dout_net,
vld_out(0) => extractor4_vld_out_net
);
monit_pos_1_c: entity work.xlfir_compiler_eebfed0cb0075aa32aca169bb967f58b
port map (
ce => ce_1_sg_x95,
ce_5600000 => ce_5600000_sg_x11,
ce_56000000 => ce_56000000_sg_x4,
ce_logic_5600000 => ce_logic_5600000_sg_x1,
clk => clk_1_sg_x95,
clk_5600000 => clk_5600000_sg_x11,
clk_56000000 => clk_56000000_sg_x4,
clk_logic_5600000 => clk_5600000_sg_x11,
s_axis_data_tdata => reinterpret5_output_port_net_x1,
s_axis_data_tuser_chanid => down_sample_q_net_x3,
src_ce => ce_5600000_sg_x11,
src_clk => clk_5600000_sg_x11,
event_s_data_chanid_incorrect => monit_pos_1_c_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pos_1_c_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pos_1_c_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pos_1_c_m_axis_data_tvalid_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_56000000_sg_x4,
clk => clk_56000000_sg_x4,
d => monit_pos_1_c_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register_q_net_x2
);
reinterpret1: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor2_dout_net,
output_port => reinterpret1_output_port_net_x1
);
reinterpret2: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret2_output_port_net_x1
);
reinterpret3: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor4_dout_net,
output_port => reinterpret3_output_port_net_x1
);
reinterpret4: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor3_dout_net,
output_port => reinterpret4_output_port_net_x1
);
reinterpret5: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x0,
output_port => reinterpret5_output_port_net
);
tddm_monit_pos_1_out_1d58a51dbf: entity work.tddm_monit_pos_1_out_entity_1d58a51dbf
port map (
ce_224000000 => ce_224000000_sg_x6,
ce_56000000 => ce_56000000_sg_x4,
clk_224000000 => clk_224000000_sg_x6,
clk_56000000 => clk_56000000_sg_x4,
monit_pos_1_ch_in => register_q_net_x2,
monit_pos_1_din => concat_y_net_x1,
monit_pos_1_q_out => down_sample3_q_net_x1,
monit_pos_1_sum_out => down_sample4_q_net_x1,
monit_pos_1_x_out => down_sample2_q_net_x1,
monit_pos_1_y_out => down_sample1_q_net_x1
);
ufix_to_bool: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor4_vld_out_net,
en => "1",
dout(0) => ufix_to_bool_dout_net_x1
);
ufix_to_bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor2_vld_out_net,
en => "1",
dout(0) => ufix_to_bool1_dout_net_x1
);
ufix_to_bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor1_vld_out_net,
en => "1",
dout(0) => ufix_to_bool2_dout_net_x1
);
ufix_to_bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor3_vld_out_net,
en => "1",
dout(0) => ufix_to_bool3_dout_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066"
entity ddc_bpm_476_066 is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_1120: in std_logic;
ce_1400000: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_22400000: in std_logic;
ce_224000000: in std_logic;
ce_2500: in std_logic;
ce_2800000: in std_logic;
ce_35: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2240: in std_logic;
ce_logic_22400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ce_logic_5600000: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_1120: in std_logic;
clk_1400000: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
clk_22400000: in std_logic;
clk_224000000: in std_logic;
clk_2500: in std_logic;
clk_2800000: in std_logic;
clk_35: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
clk_70: in std_logic;
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066;
architecture structural of ddc_bpm_476_066 is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "ddc_bpm_476_066,sysgen_core,{clock_period=4.44116092,clocking=Clock_Enables,compilation=HDL_Netlist,sample_periods=1.00000000000 2.00000000000 35.00000000000 70.00000000000 560.00000000000 1120.00000000000 2240.00000000000 2500.00000000000 4480.00000000000 5000.00000000000 10000.00000000000 1400000.00000000000 2800000.00000000000 5600000.00000000000 22400000.00000000000 44800000.00000000000 56000000.00000000000 224000000.00000000000,testbench=0,total_blocks=3351,xilinx_adder_subtracter_block=30,xilinx_arithmetic_relational_operator_block=66,xilinx_assert_block=55,xilinx_bit_slice_extractor_block=20,xilinx_bitbasher_block=5,xilinx_bitwise_expression_evaluator_block=3,xilinx_black_box_block=1,xilinx_bus_concatenator_block=9,xilinx_bus_multiplexer_block=8,xilinx_cic_compiler_3_0_block=5,xilinx_clock_enable_probe_block=11,xilinx_complex_multiplier_5_0__block=2,xilinx_constant_block_block=83,xilinx_cordic_5_0_block=4,xilinx_counter_block=8,xilinx_delay_block=59,xilinx_divider_generator_4_0_block=9,xilinx_down_sampler_block=118,xilinx_fir_compiler_6_3_block=5,xilinx_gateway_in_block=22,xilinx_gateway_out_block=233,xilinx_inverter_block=24,xilinx_logical_block_block=72,xilinx_multiplier_block=16,xilinx_register_block=264,xilinx_sample_time_block_block=88,xilinx_system_generator_block=1,xilinx_type_converter_block=23,xilinx_type_reinterpreter_block=94,xilinx_up_sampler_block=68,xilinx_wavescope_block=2,}";
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert10_dout_net_x2: std_logic;
signal assert10_dout_net_x3: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert11_dout_net_x2: std_logic_vector(24 downto 0);
signal assert11_dout_net_x3: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert12_dout_net_x2: std_logic;
signal assert12_dout_net_x3: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x2: std_logic_vector(24 downto 0);
signal assert5_dout_net_x3: std_logic_vector(24 downto 0);
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert8_dout_net_x2: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert9_dout_net_x2: std_logic;
signal assert9_dout_net_x3: std_logic;
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
signal ce_1120_sg_x32: std_logic;
signal ce_1400000_sg_x3: std_logic;
signal ce_1_sg_x96: std_logic;
signal ce_224000000_sg_x7: std_logic;
signal ce_22400000_sg_x28: std_logic;
signal ce_2240_sg_x28: std_logic;
signal ce_2500_sg_x3: std_logic;
signal ce_2800000_sg_x4: std_logic;
signal ce_2_sg_x38: std_logic;
signal ce_35_sg_x22: std_logic;
signal ce_44800000_sg_x2: std_logic;
signal ce_4480_sg_x9: std_logic;
signal ce_5000_sg_x9: std_logic;
signal ce_56000000_sg_x5: std_logic;
signal ce_5600000_sg_x12: std_logic;
signal ce_560_sg_x3: std_logic;
signal ce_70_sg_x27: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant15_op_net_x1: std_logic;
signal constant3_op_net_x1: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_down_x2: std_logic_vector(24 downto 0);
signal dout_down_x3: std_logic_vector(24 downto 0);
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x31: std_logic_vector(23 downto 0);
signal register_q_net_x32: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
signal valid_ds_down_x1: std_logic;
signal valid_ds_down_x2: std_logic;
signal valid_ds_down_x3: std_logic;
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_1_sg_x96 <= ce_1;
ce_10000_sg_x2 <= ce_10000;
ce_1120_sg_x32 <= ce_1120;
ce_1400000_sg_x3 <= ce_1400000;
ce_2_sg_x38 <= ce_2;
ce_2240_sg_x28 <= ce_2240;
ce_22400000_sg_x28 <= ce_22400000;
ce_224000000_sg_x7 <= ce_224000000;
ce_2500_sg_x3 <= ce_2500;
ce_2800000_sg_x4 <= ce_2800000;
ce_35_sg_x22 <= ce_35;
ce_4480_sg_x9 <= ce_4480;
ce_44800000_sg_x2 <= ce_44800000;
ce_5000_sg_x9 <= ce_5000;
ce_560_sg_x3 <= ce_560;
ce_5600000_sg_x12 <= ce_5600000;
ce_56000000_sg_x5 <= ce_56000000;
ce_70_sg_x27 <= ce_70;
ce_logic_1_sg_x20 <= ce_logic_1;
ce_logic_1400000_sg_x2 <= ce_logic_1400000;
ce_logic_2240_sg_x1 <= ce_logic_2240;
ce_logic_22400000_sg_x1 <= ce_logic_22400000;
ce_logic_2800000_sg_x2 <= ce_logic_2800000;
ce_logic_560_sg_x3 <= ce_logic_560;
ce_logic_5600000_sg_x2 <= ce_logic_5600000;
ce_logic_70_sg_x1 <= ce_logic_70;
clk_1_sg_x96 <= clk_1;
clk_10000_sg_x2 <= clk_10000;
clk_1120_sg_x32 <= clk_1120;
clk_1400000_sg_x3 <= clk_1400000;
clk_2_sg_x38 <= clk_2;
clk_2240_sg_x28 <= clk_2240;
clk_22400000_sg_x28 <= clk_22400000;
clk_224000000_sg_x7 <= clk_224000000;
clk_2500_sg_x3 <= clk_2500;
clk_2800000_sg_x4 <= clk_2800000;
clk_35_sg_x22 <= clk_35;
clk_4480_sg_x9 <= clk_4480;
clk_44800000_sg_x2 <= clk_44800000;
clk_5000_sg_x9 <= clk_5000;
clk_560_sg_x3 <= clk_560;
clk_5600000_sg_x12 <= clk_5600000;
clk_56000000_sg_x5 <= clk_56000000;
clk_70_sg_x27 <= clk_70;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
bpf_d31c4af409: entity work.bpf_entity_d31c4af409
port map (
din_ch0 => adc_ch0_dbg_data_o_net,
din_ch1 => adc_ch1_dbg_data_o_net,
din_ch2 => adc_ch2_dbg_data_o_net,
din_ch3 => adc_ch3_dbg_data_o_net,
dout_ch0 => bpf_ch0_o_net,
dout_ch1 => bpf_ch1_o_net,
dout_ch2 => bpf_ch2_o_net,
dout_ch3 => bpf_ch3_o_net
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert12_dout_net_x2,
in1 => reinterpret1_output_port_net,
y => concat_y_net_x0
);
concat1: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => valid_ds_down_x2,
in1 => reinterpret2_output_port_net,
y => concat1_y_net_x0
);
concat2: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert9_dout_net_x2,
in1 => reinterpret3_output_port_net,
y => concat2_y_net_x0
);
concat3: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert10_dout_net_x2,
in1 => reinterpret4_output_port_net,
y => concat3_y_net_x0
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant15: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant15_op_net_x1
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net_x1
);
convert_filt_fda412c1bf: entity work.convert_filt_entity_fda412c1bf
port map (
din => down_sample_q_net_x4,
dout => reinterpret5_output_port_net_x1
);
dds_sub_a4b6b880f6: entity work.dds_sub_entity_a4b6b880f6
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_01_cosine => register_q_net_x12,
dds_01_sine => register_q_net_x13,
dds_23_cosine => register_q_net_x14,
dds_23_sine => register_q_net_x15
);
delta_sigma_fofb_ee61e649ea: entity work.delta_sigma_fofb_entity_ee61e649ea
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
c => down_sample2_q_net_x21,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_logic_2240 => ce_logic_2240_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
d => down_sample1_q_net_x21,
ds_thres => del_sig_div_fofb_thres_i_net,
q => assert8_dout_net_x1,
q_valid => assert9_dout_net_x1,
sum_valid => assert12_dout_net_x1,
sum_x0 => assert11_dout_net_x1,
x => assert5_dout_net_x1,
x_valid => assert10_dout_net_x1,
y => dout_down_x1,
y_valid => valid_ds_down_x1
);
delta_sigma_monit_a8f8b81626: entity work.delta_sigma_monit_entity_a8f8b81626
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
c => down_sample3_q_net_x5,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
d => down_sample4_q_net_x5,
ds_thres => del_sig_div_monit_thres_i_net,
q => assert4_dout_net_x1,
q_valid => assert9_dout_net_x2,
sum_valid => assert10_dout_net_x2,
sum_x0 => assert5_dout_net_x2,
x => assert11_dout_net_x2,
x_valid => assert12_dout_net_x2,
y => dout_down_x2,
y_valid => valid_ds_down_x2
);
delta_sigma_tbt_bbfa8a8a69: entity work.delta_sigma_tbt_entity_bbfa8a8a69
port map (
a => down_sample2_q_net_x34,
b => down_sample1_q_net_x34,
c => down_sample2_q_net_x35,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
d => down_sample1_q_net_x35,
ds_thres => del_sig_div_tbt_thres_i_net,
q => assert8_dout_net_x2,
q_valid => assert9_dout_net_x3,
sum_valid => assert12_dout_net_x3,
sum_x0 => assert11_dout_net_x3,
x => assert5_dout_net_x3,
x_valid => assert10_dout_net_x3,
y => dout_down_x3,
y_valid => valid_ds_down_x3
);
fofb_amp_8b25d4b0b6: entity work.fofb_amp_entity_8b25d4b0b6
port map (
ce_1 => ce_1_sg_x96,
ce_1120 => ce_1120_sg_x32,
ce_2240 => ce_2240_sg_x28,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_1120 => clk_1120_sg_x32,
clk_2240 => clk_2240_sg_x28,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x20,
amp_out1 => down_sample1_q_net_x20,
amp_out2 => down_sample2_q_net_x21,
amp_out3 => down_sample1_q_net_x21,
fofb_amp0 => fofb_amp_ch1_o_net,
fofb_amp0_x0 => fofb_amp_ch0_o_net,
fofb_amp0_x1 => fofb_pha_ch1_o_net,
fofb_amp0_x2 => fofb_pha_ch0_o_net,
fofb_amp0_x3 => fofb_decim_ch1_i_o_net,
fofb_amp0_x4 => fofb_decim_ch0_i_o_net,
fofb_amp0_x5 => fofb_decim_ch1_q_o_net,
fofb_amp0_x6 => fofb_decim_ch0_q_o_net,
fofb_amp0_x7 => cic_fofb_q_01_missing_o_net,
fofb_amp1 => fofb_amp_ch3_o_net,
fofb_amp1_x0 => fofb_amp_ch2_o_net,
fofb_amp1_x1 => fofb_pha_ch3_o_net,
fofb_amp1_x2 => fofb_pha_ch2_o_net,
fofb_amp1_x3 => fofb_decim_ch3_i_o_net,
fofb_amp1_x4 => fofb_decim_ch2_i_o_net,
fofb_amp1_x5 => fofb_decim_ch3_q_o_net,
fofb_amp1_x6 => fofb_decim_ch2_q_o_net,
fofb_amp1_x7 => cic_fofb_q_23_missing_o_net
);
k_fofb_mult3_697accc8e2: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert5_dout_net_x1,
in2 => kx_i_net,
vld_in => assert10_dout_net_x1,
out1 => x_fofb_o_net,
vld_out => x_fofb_valid_o_net
);
k_fofb_mult4_102b49a84e: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => dout_down_x1,
in2 => ky_i_net,
vld_in => valid_ds_down_x1,
out1 => y_fofb_o_net,
vld_out => y_fofb_valid_o_net
);
k_fofb_mult5_ed47def699: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert8_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x1,
out1 => q_fofb_o_net,
vld_out => q_fofb_valid_o_net
);
k_monit_1_mult2_30ad492eba: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret1_output_port_net_x1,
in2 => ky_i_net,
vld_in => ufix_to_bool1_dout_net_x1,
out1 => y_monit_1_o_net,
vld_out => y_monit_1_valid_o_net
);
k_monit_1_mult6_71da64dfef: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret2_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool2_dout_net_x1,
out1 => q_monit_1_o_net,
vld_out => q_monit_1_valid_o_net
);
k_monit_1_mult_016885a3ac: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret3_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool_dout_net_x1,
out1 => x_monit_1_o_net,
vld_out => x_monit_1_valid_o_net
);
k_monit_mult3_8a778fb5f4: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert11_dout_net_x2,
in2 => kx_i_net,
vld_in => assert12_dout_net_x2,
out1 => x_monit_o_net,
vld_out => x_monit_valid_o_net
);
k_monit_mult4_1b07b5102a: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => dout_down_x2,
in2 => ky_i_net,
vld_in => valid_ds_down_x2,
out1 => y_monit_o_net,
vld_out => y_monit_valid_o_net
);
k_monit_mult5_a064f6aaae: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert4_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x2,
out1 => q_monit_o_net,
vld_out => q_monit_valid_o_net
);
k_tbt_mult1_cebfa469e3: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => dout_down_x3,
in2 => ky_i_net,
vld_in => valid_ds_down_x3,
out1 => y_tbt_o_net,
vld_out => y_tbt_valid_o_net
);
k_tbt_mult2_2b721a52a5: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert8_dout_net_x2,
in2 => kx_i_net,
vld_in => assert9_dout_net_x3,
out1 => q_tbt_o_net,
vld_out => q_tbt_valid_o_net
);
k_tbt_mult_b8fafff255: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert5_dout_net_x3,
in2 => kx_i_net,
vld_in => assert10_dout_net_x3,
out1 => x_tbt_o_net,
vld_out => x_tbt_valid_o_net
);
ksum_fofb_mult4_ac3ed97096: entity work.ksum_fofb_mult4_entity_ac3ed97096
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert11_dout_net_x1,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x1,
out1 => sum_fofb_o_net,
vld_out => sum_fofb_valid_o_net
);
ksum_monit_1_mult1_c66dc07078: entity work.ksum_monit_1_mult1_entity_c66dc07078
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret4_output_port_net_x1,
in2 => ksum_i_net,
vld_in => ufix_to_bool3_dout_net_x1,
out1 => sum_monit_1_o_net,
vld_out => sum_monit_1_valid_o_net
);
ksum_monit_mult2_31877b6d2b: entity work.ksum_monit_mult2_entity_31877b6d2b
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert5_dout_net_x2,
in2 => ksum_i_net,
vld_in => assert10_dout_net_x2,
out1 => sum_monit_o_net,
vld_out => sum_monit_valid_o_net
);
ksum_tbt_mult3_e0be30d675: entity work.ksum_tbt_mult3_entity_e0be30d675
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert11_dout_net_x3,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x3,
out1 => sum_tbt_o_net,
vld_out => sum_tbt_valid_o_net
);
mixer_a1cd828545: entity work.mixer_entity_a1cd828545
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ch_in0 => register1_q_net_x6,
ch_in1 => register1_q_net_x7,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_cosine_0 => register_q_net_x12,
dds_cosine_1 => register_q_net_x14,
dds_msine_0 => register_q_net_x13,
dds_msine_1 => register_q_net_x15,
dds_valid_0 => constant15_op_net_x1,
dds_valid_1 => constant3_op_net_x1,
din0 => register_q_net_x31,
din1 => register_q_net_x32,
ch_out0 => register3_q_net_x15,
ch_out1 => register3_q_net_x16,
i_out0 => register4_q_net_x14,
i_out1 => register4_q_net_x15,
q_out0 => register5_q_net_x14,
q_out1 => register5_q_net_x15,
tddm_mixer => mix_ch1_i_o_net,
tddm_mixer_x0 => mix_ch0_i_o_net,
tddm_mixer_x1 => mix_ch1_q_o_net,
tddm_mixer_x2 => mix_ch0_q_o_net,
tddm_mixer_x3 => mix_ch3_i_o_net,
tddm_mixer_x4 => mix_ch2_i_o_net,
tddm_mixer_x5 => mix_ch3_q_o_net,
tddm_mixer_x6 => mix_ch2_q_o_net
);
monit_amp_44da74e268: entity work.monit_amp_entity_44da74e268
port map (
ce_1 => ce_1_sg_x96,
ce_1400000 => ce_1400000_sg_x3,
ce_22400000 => ce_22400000_sg_x28,
ce_2800000 => ce_2800000_sg_x4,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ch_in => ch_out_x2,
clk_1 => clk_1_sg_x96,
clk_1400000 => clk_1400000_sg_x3,
clk_22400000 => clk_22400000_sg_x28,
clk_2800000 => clk_2800000_sg_x4,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din => dout_x2,
amp_out0 => down_sample2_q_net_x5,
amp_out1 => down_sample1_q_net_x5,
amp_out2 => down_sample3_q_net_x5,
amp_out3 => down_sample4_q_net_x5,
monit_amp_c => monit_amp_ch1_o_net,
monit_amp_c_x0 => monit_amp_ch0_o_net,
monit_amp_c_x1 => monit_amp_ch2_o_net,
monit_amp_c_x2 => monit_amp_ch3_o_net,
monit_amp_c_x3 => monit_cfir_incorrect_o_net,
monit_amp_c_x4 => monit_cic_unexpected_o_net,
monit_amp_c_x5 => monit_pfir_incorrect_o_net
);
monit_pos_1_522c8cf08d: entity work.monit_pos_1_entity_522c8cf08d
port map (
ce_1 => ce_1_sg_x96,
ce_224000000 => ce_224000000_sg_x7,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ch_in => down_sample_q_net_x3,
clk_1 => clk_1_sg_x96,
clk_224000000 => clk_224000000_sg_x7,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
din => reinterpret5_output_port_net_x1,
monit_1_pos_q => reinterpret2_output_port_net_x1,
monit_1_pos_x => reinterpret3_output_port_net_x1,
monit_1_pos_y => reinterpret1_output_port_net_x1,
monit_1_sum => reinterpret4_output_port_net_x1,
monit_1_vld_q => ufix_to_bool2_dout_net_x1,
monit_1_vld_sum => ufix_to_bool3_dout_net_x1,
monit_1_vld_x => ufix_to_bool_dout_net_x1,
monit_1_vld_y => ufix_to_bool1_dout_net_x1,
monit_pos_1_c_x0 => monit_pos_1_incorrect_o_net
);
register1: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch1_i_net,
en => "1",
rst => "0",
q => adc_ch1_dbg_data_o_net
);
register2: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch2_i_net,
en => "1",
rst => "0",
q => adc_ch2_dbg_data_o_net
);
register3: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch3_i_net,
en => "1",
rst => "0",
q => adc_ch3_dbg_data_o_net
);
register_x0: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch0_i_net,
en => "1",
rst => "0",
q => adc_ch0_dbg_data_o_net
);
reinterpret1: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert11_dout_net_x2,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => dout_down_x2,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert4_dout_net_x1,
output_port => reinterpret3_output_port_net
);
reinterpret4: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert5_dout_net_x2,
output_port => reinterpret4_output_port_net
);
tbt_amp_cbd277bb0c: entity work.tbt_amp_entity_cbd277bb0c
port map (
ce_1 => ce_1_sg_x96,
ce_35 => ce_35_sg_x22,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_35 => clk_35_sg_x22,
clk_70 => clk_70_sg_x27,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x34,
amp_out1 => down_sample1_q_net_x34,
amp_out2 => down_sample2_q_net_x35,
amp_out3 => down_sample1_q_net_x35,
tbt_amp0 => tbt_amp_ch1_o_net,
tbt_amp0_x0 => tbt_amp_ch0_o_net,
tbt_amp0_x1 => tbt_pha_ch1_o_net,
tbt_amp0_x2 => tbt_pha_ch0_o_net,
tbt_amp0_x3 => tbt_decim_ch01_incorrect_o_net,
tbt_amp0_x4 => tbt_decim_ch1_i_o_net,
tbt_amp0_x5 => tbt_decim_ch0_i_o_net,
tbt_amp0_x6 => tbt_decim_ch1_q_o_net,
tbt_amp0_x7 => tbt_decim_ch0_q_o_net,
tbt_amp1 => tbt_amp_ch3_o_net,
tbt_amp1_x0 => tbt_amp_ch2_o_net,
tbt_amp1_x1 => tbt_pha_ch3_o_net,
tbt_amp1_x2 => tbt_pha_ch2_o_net,
tbt_amp1_x3 => tbt_decim_ch23_incorrect_o_net,
tbt_amp1_x4 => tbt_decim_ch3_i_o_net,
tbt_amp1_x5 => tbt_decim_ch2_i_o_net,
tbt_amp1_x6 => tbt_decim_ch3_q_o_net,
tbt_amp1_x7 => tbt_decim_ch2_q_o_net
);
tdm_mix_54ce67e6e8: entity work.tdm_mix_entity_54ce67e6e8
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
din_ch0 => bpf_ch0_o_net,
din_ch1 => bpf_ch1_o_net,
din_ch2 => bpf_ch2_o_net,
din_ch3 => bpf_ch3_o_net,
ch_out0 => register1_q_net_x6,
ch_out1 => register1_q_net_x7,
dout0 => register_q_net_x31,
dout1 => register_q_net_x32
);
tdm_monit_1_746ecf54b0: entity work.tdm_monit_1_entity_746ecf54b0
port map (
ce_1 => ce_1_sg_x96,
ce_22400000 => ce_22400000_sg_x28,
ce_2500 => ce_2500_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
clk_1 => clk_1_sg_x96,
clk_22400000 => clk_22400000_sg_x28,
clk_2500 => clk_2500_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din_ch0 => concat_y_net_x0,
din_ch1 => concat1_y_net_x0,
din_ch2 => concat2_y_net_x0,
din_ch3 => concat3_y_net_x0,
rst => constant11_op_net_x0,
ch_out => down_sample_q_net_x3,
dout => down_sample_q_net_x4
);
tdm_monit_6e38292ecb: entity work.tdm_monit_entity_6e38292ecb
port map (
ce_1 => ce_1_sg_x96,
ce_2240 => ce_2240_sg_x28,
ce_560 => ce_560_sg_x3,
ce_logic_560 => ce_logic_560_sg_x3,
clk_1 => clk_1_sg_x96,
clk_2240 => clk_2240_sg_x28,
clk_560 => clk_560_sg_x3,
din_ch0 => down_sample2_q_net_x20,
din_ch1 => down_sample1_q_net_x20,
din_ch2 => down_sample2_q_net_x21,
din_ch3 => down_sample1_q_net_x21,
rst => constant10_op_net_x0,
ch_out => ch_out_x2,
dout => dout_x2
);
end structural;
| lgpl-3.0 | dfe64fa759819701ee623591798bedf2 | 0.592972 | 2.65763 | false | false | false | false |
morelab/weblabdeusto | server/launch/sample/main_machine/main_instance/experiment_fpga/files/base.vhd | 4 | 1,972 | -- @@@CLOCK:WEBLAB@@@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity base is
Port (
inicio : in std_logic;
clk : in std_logic;
led0 : inout std_logic;
led1 : inout std_logic;
led2 : inout std_logic;
led3 : inout std_logic;
led4 : inout std_logic;
led5 : inout std_logic;
led6 : inout std_logic;
led7 : inout std_logic;
ena0 : inout std_logic;
ena1 : inout std_logic;
ena2 : inout std_logic;
ena3 : inout std_logic;
seg0 : inout std_logic;
seg1 : inout std_logic;
seg2 : inout std_logic;
seg3 : inout std_logic;
seg4 : inout std_logic;
seg5 : inout std_logic;
seg6 : inout std_logic;
dot : inout std_logic;
but0 : in std_logic;
but1 : in std_logic;
but2 : in std_logic;
but3 : in std_logic;
swi0 : in std_logic;
swi1 : in std_logic;
swi2 : in std_logic;
swi3 : in std_logic;
swi4 : in std_logic;
swi5 : in std_logic;
swi6 : in std_logic;
swi7 : in std_logic;
swi8 : in std_logic;
swi9 : in std_logic;
vleds : out std_logic_vector (7 downto 0)
);
end base;
architecture behavioral of base is
begin
led0 <= swi6;
led1 <= swi5;
led2 <= swi4;
led3 <= swi3;
vleds(0) <= led7;
vleds(1) <= led6;
vleds(2) <= led5;
vleds(3) <= led4;
vleds(4) <= led3;
vleds(5) <= led2;
vleds(6) <= led1;
vleds(7) <= led0;
end behavioral
;
| bsd-2-clause | bdd6361ff281dcc2bd3902ce0934c7f7 | 0.441176 | 3.43554 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/system_timing.vhd | 1 | 1,510 | library ieee;
use ieee.std_logic_1164.all;
entity system_timing is
generic (
TIMESTAMP_COUNTER_MAX: integer := 1000
);
port (
clock_50MHz : in std_logic;
reset : in std_logic;
time_base_50_ms_out: out std_logic;
elapsed_time_out: out integer range 0 to TIMESTAMP_COUNTER_MAX
);
end;
architecture rtl of system_timing is
constant COUNTER_50_MS_MAX: integer := 50_000_000 / 20; -- 100 ms / 20 ns
signal counter_50_ms: integer range 0 to COUNTER_50_MS_MAX;
signal time_base_50_ms: std_logic;
signal elapsed_time: integer range 0 to TIMESTAMP_COUNTER_MAX;
begin
elapsed_time_out <= elapsed_time;
time_base_50_ms_out <= time_base_50_ms;
process (clock_50MHz, reset) begin
if reset then
time_base_50_ms <= '0';
counter_50_ms <= 0;
elsif rising_edge(clock_50MHz) then
if counter_50_ms < COUNTER_50_MS_MAX then
counter_50_ms <= counter_50_ms + 1;
time_base_50_ms <= '0';
else
counter_50_ms <= 0;
time_base_50_ms <= '1';
end if;
end if;
end process;
process (clock_50MHz, reset) begin
if reset then
elapsed_time <= 0;
elsif rising_edge(clock_50MHz) then
if time_base_50_ms then
elapsed_time <= elapsed_time + 1;
end if;
end if;
end process;
end;
| unlicense | 8cddaf02be668844db9926a09c8463ae | 0.542384 | 3.638554 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_un_cross/wb_bpm_swap.vhd | 1 | 14,010 | ------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP flat interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core. In flat style.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-12 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity wb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
mode1_o : out std_logic_vector(1 downto 0);
mode2_o : out std_logic_vector(1 downto 0);
wdw_rst_o : out std_logic; -- Reset Windowing module
wdw_sw_clk_i : in std_logic; -- Switching clock from Windowing module
wdw_use_o : out std_logic; -- Use Windowing module
wdw_dly_o : out std_logic_vector(15 downto 0); -- Delay to apply the window
-- Output to RFFE board
clk_swap_o : out std_logic;
clk_swap_en_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end wb_bpm_swap;
architecture rtl of wb_bpm_swap is
-----------------------------
-- General Contants
-----------------------------
constant c_periph_addr_size : natural := 3+2;
signal fs_rst_n : std_logic;
signal wdw_use_ext_clk : std_logic;
signal clk_swap_en : std_logic;
-----------------------------
-- Wishbone Register Interface signals
-----------------------------
-- wb_bpm_swap reg structure
signal regs_in : t_bpm_swap_in_registers;
signal regs_out : t_bpm_swap_out_registers;
-----------------------------
-- Wishbone slave adapter signals/structures
-----------------------------
signal wb_slv_adp_out : t_wishbone_master_out;
signal wb_slv_adp_in : t_wishbone_master_in;
signal resized_addr : std_logic_vector(c_wishbone_address_width-1 downto 0);
component wb_bpm_swap_regs
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
fs_clk_i : in std_logic;
regs_i : in t_bpm_swap_in_registers;
regs_o : out t_bpm_swap_out_registers
);
end component;
component un_cross_top
generic(
g_delay_vec_width : natural range 0 to 16 := 16;
g_swap_div_freq_vec_width : natural range 0 to 16 := 16
);
port(
-- Commom signals
clk_i : in std_logic;
rst_n_i : in std_logic;
-- inv_chs_top core signal
const_aa_i : in std_logic_vector(15 downto 0);
const_bb_i : in std_logic_vector(15 downto 0);
const_cc_i : in std_logic_vector(15 downto 0);
const_dd_i : in std_logic_vector(15 downto 0);
const_ac_i : in std_logic_vector(15 downto 0);
const_bd_i : in std_logic_vector(15 downto 0);
const_ca_i : in std_logic_vector(15 downto 0);
const_db_i : in std_logic_vector(15 downto 0);
delay1_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
delay2_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
flag1_o : out std_logic;
flag2_o : out std_logic;
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
-- Swap clock for RFFE
clk_swap_o : out std_logic;
clk_swap_en_i : in std_logic;
-- swap_cnt_top signal
mode1_i : in std_logic_vector(1 downto 0);
mode2_i : in std_logic_vector(1 downto 0);
swap_div_f_i : in std_logic_vector(g_swap_div_freq_vec_width-1 downto 0);
ext_clk_i : in std_logic;
ext_clk_en_i : in std_logic;
-- Output to RFFE board
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end component;
begin
-----------------------------
-- Slave adapter for Wishbone Register Interface
-----------------------------
cmp_slave_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => PIPELINED,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_slv_adp_in,
master_o => wb_slv_adp_out,
sl_adr_i => resized_addr,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_rty_o => open,
sl_err_o => open,
sl_int_o => open,
sl_stall_o => wb_stall_o
);
-- See wb_bpm_swap_port.vhd for register bank addresses.
resized_addr(c_periph_addr_size-1 downto 0) <= wb_adr_i(c_periph_addr_size-1 downto 0); --cbar_master_out(0).adr(c_periph_addr_size-1 downto 0);
resized_addr(c_wishbone_address_width-1 downto c_periph_addr_size) <= (others => '0');
-- Register Bank / Wishbone Interface
cmp_wb_bpm_swap_regs : wb_bpm_swap_regs
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_slv_adp_out.adr(2 downto 0),
wb_dat_i => wb_slv_adp_out.dat,
wb_dat_o => wb_slv_adp_in.dat,
wb_cyc_i => wb_slv_adp_out.cyc,
wb_sel_i => wb_slv_adp_out.sel,
wb_stb_i => wb_slv_adp_out.stb,
wb_we_i => wb_slv_adp_out.we,
wb_ack_o => wb_slv_adp_in.ack,
wb_stall_o => wb_slv_adp_in.stall,
fs_clk_i => fs_clk_i,
regs_i => regs_in,
regs_o => regs_out
);
-- Unused wishbone signals
wb_slv_adp_in.int <= '0';
wb_slv_adp_in.err <= '0';
wb_slv_adp_in.rty <= '0';
regs_in.wdw_ctl_reserved_i <= (others => '0');
wdw_use_ext_clk <= regs_out.wdw_ctl_swclk_ext_o;
cmd_un_cross : un_cross_top
generic map (
g_delay_vec_width => 16,
g_swap_div_freq_vec_width => 16
)
port map (
clk_i => fs_clk_i,
rst_n_i => fs_rst_n_i,
const_aa_i => regs_out.a_a_o,
const_bb_i => regs_out.c_c_o,
const_cc_i => regs_out.b_b_o,
const_dd_i => regs_out.d_d_o,
const_ac_i => regs_out.a_c_o,
const_bd_i => regs_out.b_d_o,
const_ca_i => regs_out.c_a_o,
const_db_i => regs_out.d_b_o,
delay1_i => regs_out.dly_1_o,
delay2_i => regs_out.dly_2_o,
flag1_o => flag1_o,
flag2_o => flag2_o,
-- Input
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
-- Output
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
-- Swap clock for RFFE
clk_swap_o => clk_swap_o,
clk_swap_en_i => clk_swap_en,
mode1_i => regs_out.ctrl_mode1_o,
mode2_i => regs_out.ctrl_mode2_o,
swap_div_f_i => regs_out.ctrl_swap_div_f_o,
ext_clk_i => wdw_sw_clk_i,
ext_clk_en_i => wdw_use_ext_clk,
-- Output to RFFE
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o
);
clk_swap_en <= regs_out.ctrl_clk_swap_en_o;
clk_swap_en_o <= clk_swap_en;
mode1_o <= regs_out.ctrl_mode1_o;
mode2_o <= regs_out.ctrl_mode2_o;
wdw_use_o <= regs_out.wdw_ctl_use_o;
--wdw_dly_o <= regs_out.wdw_ctl_dly_o; -- FIXME: this reg is not used!
wdw_dly_o <= regs_out.dly_1_o;
wdw_rst_o <= regs_out.wdw_ctl_rst_wdw_o;
end rtl;
| lgpl-3.0 | ba77890876ef4034152c55820b49d600 | 0.389793 | 3.90686 | false | false | false | false |
wltr/common-vhdl | packages/lfsr/src/tb/fibonacci_lfsr_tb_top.vhd | 1 | 2,284 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2015 Johannes Walter <[email protected]>
--
-- Description:
-- Testbench for Fibonacci Linear Feedback Shift Register (LFSR) package.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity lfsr_tb_top is
end entity lfsr_tb_top;
architecture rtl of lfsr_tb_top is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
constant len_c : natural := lfsr_length(9);
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, 9);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal lfsr : std_ulogic_vector(len_c - 1 downto 0);
signal sig : std_ulogic;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal rst_n : std_ulogic := '0';
begin -- architecture rtl
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
clk <= not clk after 10 ns;
rst_n <= '1' after 42 ns;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process(clk, rst_n) is
procedure reset is
begin
lfsr <= seed_c;
sig <= '0';
end procedure reset;
begin -- process regs
if rst_n = '0' then
reset;
elsif rising_edge(clk) then
sig <= '0';
lfsr <= lfsr_shift(lfsr);
if lfsr = max_c then
sig <= '1';
lfsr <= seed_c;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | fd77d4d895403ed0bd65adcd6cf25839 | 0.355954 | 5.412322 | false | false | false | false |
wltr/common-vhdl | generic/glitch_filter/src/rtl/glitch_filter.vhd | 1 | 3,218 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Filter glitches with an N-stage shift register.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity glitch_filter is
generic (
-- Initial value of input signal
init_value_g : std_ulogic := '0';
-- Number of delay stages
num_delay_g : positive := 1);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Input signal
sig_i : in std_ulogic;
-- Filtered output signal
sig_o : out std_ulogic);
end entity glitch_filter;
architecture rtl of glitch_filter is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal dlyd_sig : std_ulogic_vector(num_delay_g - 1 downto 0) := (others => init_value_g);
signal sig : std_ulogic := init_value_g;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_sig : std_ulogic_vector(num_delay_g - 1 downto 0);
signal state : std_ulogic_vector(num_delay_g - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
sig_o <= sig;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Delay only for one clock cycle
single_delay_gen : if num_delay_g = 1 generate
next_sig(0) <= sig_i;
end generate single_delay_gen;
-- Delay for multiple clock cycles
multiple_delays_gen : if num_delay_g > 1 generate
next_sig <= dlyd_sig(dlyd_sig'high - 1 downto dlyd_sig'low) & sig_i;
end generate multiple_delays_gen;
-- Compute state
state(0) <= dlyd_sig(0) xnor sig_i;
state_gen : for i in 1 to num_delay_g - 1 generate
state(i) <= dlyd_sig(i) xnor state(i - 1);
end generate state_gen;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Filter signal
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
dlyd_sig <= (others => init_value_g);
sig <= init_value_g;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if en_i = '1' then
dlyd_sig <= next_sig;
end if;
if state(state'high) = '1' then
sig <= dlyd_sig(dlyd_sig'high);
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | de93eb53a134068f34f47b9c386b8e0f | 0.42573 | 4.513324 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_multiplier.vhd | 1 | 4,455 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Perform (right-)shift and add multiplication.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
entity ads1281_filter_multiplier is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Decoded data
data_i : in signed(6 downto 0);
-- Coefficient
coeff_i : in unsigned(23 downto 0);
coeff_en_i : in std_ulogic;
-- Multiplier result
res_o : out signed(30 downto 0);
res_en_o : out std_ulogic);
end entity ads1281_filter_multiplier;
architecture rtl of ads1281_filter_multiplier is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(coeff_i'length);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter value after 23 shifts
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, coeff_i'length - 1);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal lfsr : std_ulogic_vector(len_c - 1 downto 0);
signal res : unsigned(30 downto 0);
signal data : signed(data_i'range);
signal busy : std_ulogic;
signal en : std_ulogic;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal a : std_ulogic_vector(6 downto 0);
signal b : std_ulogic_vector(6 downto 0);
signal sum : unsigned(7 downto 0);
signal shift : unsigned(30 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
res_o <= signed(res);
res_en_o <= en;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- 1st adder input is data input when register's low bit is 1, otherwise 0
a <= std_ulogic_vector(data) when res(res'low) = '1' else (others => '0');
-- 2nd adder input is always the register's top section
b <= std_ulogic_vector(res(res'high downto res'high - data'length + 1));
-- Adder with sign extension
sum <= unsigned(a(a'high) & a) + unsigned(b(b'high) & b);
-- Shift register and replace top section with adder output
shift <= sum & res(res'high - sum'length + 1 downto res'low + 1);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
lfsr <= seed_c;
res <= (others => '0');
data <= (others => '0');
busy <= '0';
en <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
en <= '0';
if rst_syn_i = '1' then
reset;
else
if coeff_en_i = '1' then
-- Store data
data <= data_i;
-- Store multiplier in shift register
res <= (res'high downto coeff_i'length => '0') & coeff_i;
-- Start calculation
busy <= '1';
lfsr <= seed_c;
end if;
if lfsr = max_c then
en <= '1';
busy <= '0';
end if;
if busy = '1' then
-- Shift LFSR and result
lfsr <= lfsr_shift(lfsr);
res <= shift;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 93781d79aa239e45145b74dc30deeac9 | 0.421773 | 4.640625 | false | false | false | false |
wltr/common-vhdl | memory/single_port_ram/src/rtl/single_port_ram.vhd | 1 | 2,839 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Single port block RAM.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity single_port_ram is
generic (
-- Memory depth
depth_g : positive := 32;
-- Data bit width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
rd_en_i : in std_ulogic;
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
done_o : out std_ulogic);
end entity single_port_ram;
architecture rtl of single_port_ram is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
type mem_t is array (0 to depth_g - 1) of std_ulogic_vector(data_i'range);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal mem : mem_t;
signal data : std_ulogic_vector(data_o'range);
signal data_en : std_ulogic;
signal done : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= data;
data_en_o <= data_en;
done_o <= done;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
data <= (others => '0');
data_en <= '0';
done <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
data_en <= '0';
done <= '0';
if rst_syn_i = '1' then
reset;
else
if wr_en_i = '1' then
mem(to_integer(unsigned(addr_i))) <= data_i;
done <= '1';
elsif rd_en_i = '1' then
data <= mem(to_integer(unsigned(addr_i)));
data_en <= '1';
done <= '1';
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 1b063f831f08a44a070e8988f37fbacc | 0.40155 | 4.230999 | false | false | false | false |
wltr/common-vhdl | packages/lfsr/src/tb/galois_lfsr_tb_top.vhd | 1 | 2,264 | -------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2015 Johannes Walter <[email protected]>
--
-- Description:
-- Testbench for Galois Linear Feedback Shift Register (LFSR) package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity lfsr_tb_top is
end entity lfsr_tb_top;
architecture rtl of lfsr_tb_top is
---------------------------------------------------------------------------
-- Types and Constants
---------------------------------------------------------------------------
constant period_c : natural := 10;
constant len_c : natural := lfsr_length(period_c);
constant seed_c : lfsr_t(len_c - 1 downto 0) := lfsr_seed(len_c);
constant max_c : lfsr_t(len_c - 1 downto 0) := lfsr_shift(seed_c, period_c - 1);
---------------------------------------------------------------------------
-- Internal Registers
---------------------------------------------------------------------------
signal lfsr : lfsr_t(len_c - 1 downto 0);
signal sig : std_ulogic;
---------------------------------------------------------------------------
-- Internal Wires
---------------------------------------------------------------------------
signal clk : std_ulogic := '1';
signal rst_n : std_ulogic := '0';
begin -- architecture rtl
---------------------------------------------------------------------------
-- Signal Assignments
---------------------------------------------------------------------------
clk <= not clk after 10 ns;
rst_n <= '1' after 42 ns;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process(clk, rst_n) is
procedure reset is
begin
lfsr <= seed_c;
sig <= '0';
end procedure reset;
begin -- process regs
if rst_n = '0' then
reset;
elsif rising_edge(clk) then
sig <= '0';
lfsr <= lfsr + 1;
if lfsr = max_c then
sig <= '1';
lfsr <= seed_c;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 58e478b69147a5c4a0fc2c7d662b1df6 | 0.357332 | 5.277389 | false | false | false | false |
freecores/raggedstone | source/generate_pciregs/new_pciregs.vhd | 1 | 29,292 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pciregs.vhd |
--| |
--| Project: pci32tlite_oc |
--| |
--| Description: Registros PCI |
--| BAR0 is used externally by decoder. |
--| |
--| +-----------------------------------------------------------------------+ |
--| | PCI CONFIGURATION SPACE REGISTERS | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-------------------------------------------------------------------+ |
--| | REGISTER | adr(7..2) | offset | Byte Enable | Size | |
--| +-------------------------------------------------------------------+ |
--| | VENDORID | 000000 (r) | 00 | 0/1 | 2 | |
--| +-------------------------------------------------------------------+ |
--| | DERVICEID | 000000 (r) | 02 | 2/3 | 2 | |
--| +-------------------------------------------------------------------+ |
--| | CMD | 000001 (r/w) | 04 | 0/1 | 2 | |
--| +-------------------------------------------------------------------+ |
--| | ST | 000001 (r/w*)| 06 | 2/3 | 2 | |
--| +-------------------------------------------------------------------+ |
--| | REVISIONID | 000010 (r) | 08 | 0 | 1 | |
--| +-------------------------------------------------------------------+ |
--| | CLASSCODE | 000010 (r) | 09 | 1/2/3 | 3 | |
--| +-------------------------------------------------------------------+ |
--| | HEADERTYPE | 000011 (r) | 0E | 2 | 1 | |
--| +-------------------------------------------------------------------+ |
--| | BAR0 | 000100 (r/w) | 10 | 0/1/2/3 | 4 | |
--| +-------------------------------------------------------------------+ |
--| | SUBSYSTEMID | 001011 (r) | 2C | 0/1 | 2 | |
--| +-------------------------------------------------------------------+ |
--| | SUBSYSTEMVID | 001011 (r) | 2E | 0/1 | 2 | |
--| +-------------------------------------------------------------------+ |
--| | INTLINE | 001111 (r/w) | 3C | 0 | 1 | |
--| +-------------------------------------------------------------------+ |
--| | INTPIN | 001111 (r) | 3D | 1 | 1 | |
--| +-------------------------------------------------------------------+ |
--| (w*) Reseteable |
--| |
--| +-----------------------------------------------+ |
--| | VENDORID (r) Vendor ID register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Identifies manufacturer of device. | |
--| | VENDORIDr : vendorID (generic) | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | DEVICEID (r) Device ID register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Identifies the device. | |
--| | DEVICEIDr : deviceID (generic) | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | CMD (r/w) CoMmanD register | |
--| +-----------------------------------------------+----------------------------+ |
--| | 0 | 0 | 0 | 0 | 0 | 0 | 0 | SERRENb| (15-8) |
--| +----------------------------------------------------------------------------+ |
--| | 0 | PERRENb| 0 | 0 | 0 | 0 |MEMSPACEENb| 0 | (7-0) |
--| +----------------------------------------------------------------------------+ |
--| | SERRENb : System ERRor ENable (1 = Enabled) | |
--| | PERRENb : Parity ERRor ENable (1 = Enabled) | |
--| | MEMSPACEENb : MEMmory SPACE ENable (1 = Enabled) | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | ST (r/w*) STatus register | |
--| +-----------------------------------------------+-------------------------+ |
--| | PERRDTb | SERRSIb| -- | -- |TABORTSIb| DEVSELTIMb(1..0)| -- | (15-8) |
--| +-------------------------------------------------------------------------+ |
--| | -- | -- | -- | -- | -- | -- | -- | -- | (7-0) |
--| +-------------------------------------------------------------------------+ |
--| | PERRDTb : Parity ERRor DeTected | |
--| | SERRSIb : System ERRor SIgnaled | |
--| | TABORTSIb : Target ABORT SIgnaled | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | REVISIONID (r) Revision ID register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Identifies a device revision. | |
--| +-----------------------------------------------------------------------+ |
--| +-----------------------------------------------+ |
--| | CLASSCODE (r) CLASS CODE register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Identifies the generic funtion of the device. | |
--| +-----------------------------------------------------------------------+ |
--| +-----------------------------------------------+ |
--| | HEADERTYPE (r) Header Type register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Identifies the layout of the second part of the predefined header. | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | BAR0 (r/w) Base AddRess 0 register | |
--| +-----------------------------------------------+-----------------------+ |
--| | BAR032MBb(6..0) | -- | (31-24) |
--| +-----------------------------------------------------------------------+ |
--| | BAR032MBb : Base Address 32MBytes decode space (7 bits) | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | SUBSYSTEMVID (r) SUBSYSTEM Vendor ID register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Identifies vendor of add-in board or subsystem. | |
--| | SUBSYSTEMVIDr : subsystemvID (generic) | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | SUBSYSTEMID (r) SUBSYSTEM ID register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Vendor specific. | |
--| | SUBSYTEMIDr : subsytemID (generic) | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | INTLINE (r/w) INTerrupt LINE register | |
--| +-----------------------------------------------+-----------------------+ |
--| | INTLINEr(7..0) | (7..0) |
--| +-----------------------------------------------------------------------+ |
--| | Interrupt Line routing information | |
--| +-----------------------------------------------------------------------+ |
--| |
--| +-----------------------------------------------+ |
--| | INTPIN (r) INTerrupt PIN register | |
--| +-----------------------------------------------+-----------------------+ |
--| | Tells which interrupt pin the device uses: 01=INTA | |
--| +-----------------------------------------------------------------------+ |
--| |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Revision history : |
--| Date Version Author Description |
--| 2005-05-13 R00A00 PAU First alfa revision (eng) |
--| |
--| To do: |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pciregs is
generic (
vendorID : std_logic_vector(15 downto 0);
deviceID : std_logic_vector(15 downto 0);
revisionID : std_logic_vector(7 downto 0);
subsystemID : std_logic_vector(15 downto 0);
subsystemvID : std_logic_vector(15 downto 0);
jcarr1ID : std_logic_vector(31 downto 0);
jcarr2ID : std_logic_vector(31 downto 0);
jcarr3ID : std_logic_vector(31 downto 0);
jcarr4ID : std_logic_vector(31 downto 0);
jcarr5ID : std_logic_vector(31 downto 0);
jcarr6ID : std_logic_vector(31 downto 0);
jcarr7ID : std_logic_vector(31 downto 0);
jcarr8ID : std_logic_vector(31 downto 0);
jcarr9ID : std_logic_vector(31 downto 0);
jcarr10ID : std_logic_vector(31 downto 0);
jcarr11ID : std_logic_vector(31 downto 0);
jcarr12ID : std_logic_vector(31 downto 0);
jcarr13ID : std_logic_vector(31 downto 0);
jcarr14ID : std_logic_vector(31 downto 0);
jcarr15ID : std_logic_vector(31 downto 0);
jcarr16ID : std_logic_vector(31 downto 0);
jcarr17ID : std_logic_vector(31 downto 0);
jcarr18ID : std_logic_vector(31 downto 0);
jcarr19ID : std_logic_vector(31 downto 0);
jcarr20ID : std_logic_vector(31 downto 0);
jcarr21ID : std_logic_vector(31 downto 0);
jcarr22ID : std_logic_vector(31 downto 0);
jcarr23ID : std_logic_vector(31 downto 0);
jcarr24ID : std_logic_vector(31 downto 0);
jcarr25ID : std_logic_vector(31 downto 0);
jcarr26ID : std_logic_vector(31 downto 0);
jcarr27ID : std_logic_vector(31 downto 0);
jcarr28ID : std_logic_vector(31 downto 0);
jcarr29ID : std_logic_vector(31 downto 0);
jcarr30ID : std_logic_vector(31 downto 0);
jcarr31ID : std_logic_vector(31 downto 0);
jcarr32ID : std_logic_vector(31 downto 0);
jcarr33ID : std_logic_vector(31 downto 0);
jcarr34ID : std_logic_vector(31 downto 0);
jcarr35ID : std_logic_vector(31 downto 0);
jcarr36ID : std_logic_vector(31 downto 0);
jcarr37ID : std_logic_vector(31 downto 0);
jcarr38ID : std_logic_vector(31 downto 0);
jcarr39ID : std_logic_vector(31 downto 0);
jcarr40ID : std_logic_vector(31 downto 0);
jcarr41ID : std_logic_vector(31 downto 0);
jcarr42ID : std_logic_vector(31 downto 0)
);
port (
-- General
clk_i : in std_logic;
nrst_i : in std_logic;
--
adr_i : in std_logic_vector(5 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
dat_i : in std_logic_vector(31 downto 0);
dat_o : out std_logic_vector(31 downto 0);
--
wrcfg_i : in std_logic;
rdcfg_i : in std_logic;
perr_i : in std_logic;
serr_i : in std_logic;
tabort_i : in std_logic;
--
bar0_o : out std_logic_vector(31 downto 25);
perrEN_o : out std_logic;
serrEN_o : out std_logic;
memEN_o : out std_logic
);
end pciregs;
architecture rtl of pciregs is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
constant CLASSCODEr : std_logic_vector(23 downto 0) := X"028000"; -- Bridge-OtherBridgeDevice
constant REVISIONIDr : std_logic_vector(7 downto 0) := revisionID; -- PR00=80,PR1=81...
constant HEADERTYPEr : std_logic_vector(7 downto 0) := X"00";
constant DEVSELTIMb : std_logic_vector(1 downto 0) := b"01"; -- DEVSEL TIMing (bits) medium speed
constant VENDORIDr : std_logic_vector(15 downto 0) := vendorID;
constant DEVICEIDr : std_logic_vector(15 downto 0) := deviceID;
constant SUBSYSTEMIDr : std_logic_vector(15 downto 0) := subsystemID;
constant SUBSYSTEMVIDr : std_logic_vector(15 downto 0) := subsystemvID;
constant JCARR1IDr : std_logic_vector(31 downto 0) := jcarr1ID;
constant JCARR2IDr : std_logic_vector(31 downto 0) := jcarr2ID;
constant JCARR3IDr : std_logic_vector(31 downto 0) := jcarr3ID;
constant JCARR4IDr : std_logic_vector(31 downto 0) := jcarr4ID;
constant JCARR5IDr : std_logic_vector(31 downto 0) := jcarr5ID;
constant JCARR6IDr : std_logic_vector(31 downto 0) := jcarr6ID;
constant JCARR7IDr : std_logic_vector(31 downto 0) := jcarr7ID;
constant JCARR8IDr : std_logic_vector(31 downto 0) := jcarr8ID;
constant JCARR9IDr : std_logic_vector(31 downto 0) := jcarr9ID;
constant JCARR10IDr : std_logic_vector(31 downto 0) := jcarr10ID;
constant JCARR11IDr : std_logic_vector(31 downto 0) := jcarr11ID;
constant JCARR12IDr : std_logic_vector(31 downto 0) := jcarr12ID;
constant JCARR13IDr : std_logic_vector(31 downto 0) := jcarr13ID;
constant JCARR14IDr : std_logic_vector(31 downto 0) := jcarr14ID;
constant JCARR15IDr : std_logic_vector(31 downto 0) := jcarr15ID;
constant JCARR16IDr : std_logic_vector(31 downto 0) := jcarr16ID;
constant JCARR17IDr : std_logic_vector(31 downto 0) := jcarr17ID;
constant JCARR18IDr : std_logic_vector(31 downto 0) := jcarr18ID;
constant JCARR19IDr : std_logic_vector(31 downto 0) := jcarr19ID;
constant JCARR20IDr : std_logic_vector(31 downto 0) := jcarr20ID;
constant JCARR21IDr : std_logic_vector(31 downto 0) := jcarr21ID;
constant JCARR22IDr : std_logic_vector(31 downto 0) := jcarr22ID;
constant JCARR23IDr : std_logic_vector(31 downto 0) := jcarr23ID;
constant JCARR24IDr : std_logic_vector(31 downto 0) := jcarr24ID;
constant JCARR25IDr : std_logic_vector(31 downto 0) := jcarr25ID;
constant JCARR26IDr : std_logic_vector(31 downto 0) := jcarr26ID;
constant JCARR27IDr : std_logic_vector(31 downto 0) := jcarr27ID;
constant JCARR28IDr : std_logic_vector(31 downto 0) := jcarr28ID;
constant JCARR29IDr : std_logic_vector(31 downto 0) := jcarr29ID;
constant JCARR30IDr : std_logic_vector(31 downto 0) := jcarr30ID;
constant JCARR31IDr : std_logic_vector(31 downto 0) := jcarr31ID;
constant JCARR32IDr : std_logic_vector(31 downto 0) := jcarr32ID;
constant JCARR33IDr : std_logic_vector(31 downto 0) := jcarr33ID;
constant JCARR34IDr : std_logic_vector(31 downto 0) := jcarr34ID;
constant JCARR35IDr : std_logic_vector(31 downto 0) := jcarr35ID;
constant JCARR36IDr : std_logic_vector(31 downto 0) := jcarr36ID;
constant JCARR37IDr : std_logic_vector(31 downto 0) := jcarr37ID;
constant JCARR38IDr : std_logic_vector(31 downto 0) := jcarr38ID;
constant JCARR39IDr : std_logic_vector(31 downto 0) := jcarr39ID;
constant JCARR40IDr : std_logic_vector(31 downto 0) := jcarr40ID;
constant JCARR41IDr : std_logic_vector(31 downto 0) := jcarr41ID;
constant JCARR42IDr : std_logic_vector(31 downto 0) := jcarr42ID;
constant INTPINr : std_logic_vector(7 downto 0) := X"01"; -- INTA#
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal dataout : std_logic_vector(31 downto 0);
signal tabortPFS : std_logic;
signal serrPFS : std_logic;
signal perrPFS : std_logic;
signal adrSTCMD : std_logic;
signal adrBAR0 : std_logic;
signal adrINT : std_logic;
signal we0CMD : std_logic;
signal we1CMD : std_logic;
signal we3ST : std_logic;
signal we3BAR0 : std_logic;
signal we0INT : std_logic;
signal we1INT : std_logic;
signal st11SEN : std_logic;
signal st11REN : std_logic;
signal st14SEN : std_logic;
signal st14REN : std_logic;
signal st15SEN : std_logic;
signal st15REN : std_logic;
--+---------------------------------------------------------+
--| CONFIGURATION SPACE REGISTERS |
--+---------------------------------------------------------+
-- INTERRUPT LINE register
signal INTLINEr : std_logic_vector(7 downto 0);
-- COMMAND register bits
signal MEMSPACEENb : std_logic; -- Memory SPACE ENable (bit)
signal PERRENb : std_logic; -- Parity ERRor ENable (bit)
signal SERRENb : std_logic; -- SERR ENable (bit)
-- STATUS register bits
--signal DEVSELTIMb : std_logic_vector(1 downto 0); -- DEVSEL TIMing (bits)
signal TABORTSIb : std_logic; -- TarGet ABORT SIgnaling (bit)
signal SERRSIb : std_logic; -- System ERRor SIgnaling (bit)
signal PERRDTb : std_logic; -- Parity ERRor DeTected (bit)
-- BAR0 register bits
signal BAR032MBb : std_logic_vector(6 downto 0); -- BAR0 32MBytes Space (bits)
component pfs
port (
clk : in std_logic;
a : in std_logic;
y : out std_logic
);
end component;
begin
--+-------------------------------------------------------------------------+
--| Component instances |
--+-------------------------------------------------------------------------+
u1: pfs port map ( clk => clk_i, a => tabort_i, y => tabortPFS );
u2: pfs port map ( clk => clk_i, a => serr_i, y => serrPFS );
u3: pfs port map ( clk => clk_i, a => perr_i, y => perrPFS );
--+-------------------------------------------------------------------------+
--| Registers Address Decoder |
--+-------------------------------------------------------------------------+
adrSTCMD <= '1' when ( adr_i(5 downto 0) = b"000001" ) else '0';
adrBAR0 <= '1' when ( adr_i(5 downto 0) = b"000100" ) else '0';
adrINT <= '1' when ( adr_i(5 downto 0) = b"001111" ) else '0';
--+-------------------------------------------------------------------------+
--| WRITE ENABLE REGISTERS |
--+-------------------------------------------------------------------------+
--+-----------------------------------------+
--| Write Enable Registers |
--+-----------------------------------------+
we0CMD <= adrSTCMD and wrcfg_i and (not cbe_i(0));
we1CMD <= adrSTCMD and wrcfg_i and (not cbe_i(1));
--we2ST <= adrSTCMD and wrcfg_i and (not cbe_i(2));
we3ST <= adrSTCMD and wrcfg_i and (not cbe_i(3));
--we2BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(2));
we3BAR0 <= adrBAR0 and wrcfg_i and (not cbe_i(3));
we0INT <= adrINT and wrcfg_i and (not cbe_i(0));
--we1INT <= adrINT and wrcfg_i and (not cbe_i(1));
--+-----------------------------------------+
--| Set Enable & Reset Enable bits |
--+-----------------------------------------+
st11SEN <= tabortPFS;
st11REN <= we3ST and dat_i(27);
st14SEN <= serrPFS;
st14REN <= we3ST and dat_i(30);
st15SEN <= perrPFS;
st15REN <= we3ST and dat_i(31);
--+-------------------------------------------------------------------------+
--| WRITE REGISTERS |
--+-------------------------------------------------------------------------+
--+---------------------------------------------------------+
--| COMMAND REGISTER Write |
--+---------------------------------------------------------+
REGCMDWR: process( clk_i, nrst_i, we0CMD, we1CMD, dat_i )
begin
if( nrst_i = '0' ) then
MEMSPACEENb <= '0';
PERRENb <= '0';
SERRENb <= '0';
elsif( rising_edge( clk_i ) ) then
-- Byte 0
if( we0CMD = '1' ) then
MEMSPACEENb <= dat_i(1);
PERRENb <= dat_i(6);
end if;
-- Byte 1
if( we1CMD = '1' ) then
SERRENb <= dat_i(8);
end if;
end if;
end process REGCMDWR;
--+---------------------------------------------------------+
--| STATUS REGISTER WRITE (Reset only) |
--+---------------------------------------------------------+
REGSTWR: process( clk_i, nrst_i, st11SEN, st11REN, st14SEN, st14REN, st15SEN, st15REN )
begin
if( nrst_i = '0' ) then
TABORTSIb <= '0';
SERRSIb <= '0';
PERRDTb <= '0';
elsif( rising_edge( clk_i ) ) then
-- TarGet ABORT SIgnaling bit
if( st11SEN = '1' ) then
TABORTSIb <= '1';
elsif ( st11REN = '1' ) then
TABORTSIb <= '0';
end if;
-- System ERRor SIgnaling bit
if( st14SEN = '1' ) then
SERRSIb <= '1';
elsif ( st14REN = '1' ) then
SERRSIb <= '0';
end if;
-- Parity ERRor DEtected bit
if( st15SEN = '1' ) then
PERRDTb <= '1';
elsif ( st15REN = '1' ) then
PERRDTb <= '0';
end if;
end if;
end process REGSTWR;
--+---------------------------------------------------------+
--| INTERRUPT REGISTER Write |
--+---------------------------------------------------------+
REGINTWR: process( clk_i, nrst_i, we0INT, dat_i )
begin
if( nrst_i = '0' ) then
INTLINEr <= ( others => '0' );
elsif( rising_edge( clk_i ) ) then
-- Byte 0
if( we0INT = '1' ) then
INTLINEr <= dat_i(7 downto 0);
end if;
end if;
end process REGINTWR;
--+---------------------------------------------------------+
--| BAR0 32MBytes address space (bits 31-25) |
--+---------------------------------------------------------+
REGBAR0WR: process( clk_i, nrst_i, we3BAR0, dat_i )
begin
if( nrst_i = '0' ) then
BAR032MBb <= ( others => '1' );
elsif( rising_edge( clk_i ) ) then
-- Byte 3
if( we3BAR0 = '1' ) then
BAR032MBb <= dat_i(31 downto 25);
end if;
end if;
end process REGBAR0WR;
--+-------------------------------------------------------------------------+
--| Registers MUX (READ) |
--+-------------------------------------------------------------------------+
--+-------------------------------------------------------------------------------------------------+
RRMUX: process( adr_i, PERRDTb, SERRSIb, TABORTSIb, SERRENb, PERRENb, MEMSPACEENb, BAR032MBb,
INTLINEr, rdcfg_i )
begin
if ( rdcfg_i = '1' ) then
case adr_i is
when b"000000" =>
dataout <= DEVICEIDr & VENDORIDr;
when b"000001" =>
dataout <= PERRDTb & SERRSIb & b"00" & TABORTSIb & DEVSELTIMb & b"000000000" &
b"0000000" & SERRENb & b"0" & PERRENb & b"0000" & MEMSPACEENb & b"0";
when b"000010" =>
dataout <= CLASSCODEr & REVISIONIDr;
when b"000100" =>
dataout <= BAR032MBb & b"0" & b"00000000" & b"00000000" & b"00000000";
when b"001011" =>
dataout <= SUBSYSTEMIDr & SUBSYSTEMVIDr;
when b"001111" =>
dataout <= b"0000000000000000" & INTPINr & INTLINEr;
when b"010001" =>
dataout <= JCARR1IDr;
when b"010010" =>
dataout <= JCARR2IDr;
when b"010011" =>
dataout <= JCARR3IDr;
when b"010100" =>
dataout <= JCARR4IDr;
when b"010101" =>
dataout <= JCARR5IDr;
when b"010110" =>
dataout <= JCARR6IDr;
when b"010111" =>
dataout <= JCARR7IDr;
when b"011000" =>
dataout <= JCARR8IDr;
when b"011001" =>
dataout <= JCARR9IDr;
when b"011010" =>
dataout <= JCARR10IDr;
when b"011011" =>
dataout <= JCARR11IDr;
when b"011100" =>
dataout <= JCARR12IDr;
when b"011101" =>
dataout <= JCARR13IDr;
when b"011110" =>
dataout <= JCARR14IDr;
when b"011111" =>
dataout <= JCARR15IDr;
when b"100000" =>
dataout <= JCARR16IDr;
when b"100001" =>
dataout <= JCARR17IDr;
when b"100010" =>
dataout <= JCARR18IDr;
when b"100011" =>
dataout <= JCARR19IDr;
when b"100100" =>
dataout <= JCARR20IDr;
when b"100101" =>
dataout <= JCARR21IDr;
when b"100110" =>
dataout <= JCARR22IDr;
when b"100111" =>
dataout <= JCARR23IDr;
when b"101000" =>
dataout <= JCARR24IDr;
when b"101001" =>
dataout <= JCARR25IDr;
when b"101010" =>
dataout <= JCARR26IDr;
when b"101011" =>
dataout <= JCARR27IDr;
when b"101100" =>
dataout <= JCARR28IDr;
when b"101101" =>
dataout <= JCARR29IDr;
when b"101110" =>
dataout <= JCARR30IDr;
when b"101111" =>
dataout <= JCARR31IDr;
when b"110000" =>
dataout <= JCARR32IDr;
when b"110001" =>
dataout <= JCARR33IDr;
when b"110010" =>
dataout <= JCARR34IDr;
when b"110011" =>
dataout <= JCARR35IDr;
when b"110100" =>
dataout <= JCARR36IDr;
when b"110101" =>
dataout <= JCARR37IDr;
when b"110110" =>
dataout <= JCARR38IDr;
when b"110111" =>
dataout <= JCARR39IDr;
when b"111000" =>
dataout <= JCARR40IDr;
when b"111001" =>
dataout <= JCARR41IDr;
when b"111010" =>
dataout <= JCARR42IDr;
when others =>
dataout <= ( others => '0' );
end case;
else
dataout <= ( others => '0' );
end if;
end process RRMUX;
dat_o <= dataout;
--+-------------------------------------------------------------------------+
--| BAR0 & COMMAND REGS bits outputs |
--+-------------------------------------------------------------------------+
bar0_o <= BAR032MBb;
perrEN_o <= PERRENb;
serrEN_o <= SERRENb;
memEN_o <= MEMSPACEENb;
end rtl;
| gpl-2.0 | 31bfd1f9cf3c198a45f1e7139d6d8f7b | 0.386863 | 3.56307 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/cmpy_v5_0_02d02e0a23eb9773.vhd | 1 | 5,804 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cmpy_v5_0_02d02e0a23eb9773.vhd when simulating
-- the core, cmpy_v5_0_02d02e0a23eb9773. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cmpy_v5_0_02d02e0a23eb9773 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END cmpy_v5_0_02d02e0a23eb9773;
ARCHITECTURE cmpy_v5_0_02d02e0a23eb9773_a OF cmpy_v5_0_02d02e0a23eb9773 IS
-- synthesis translate_off
COMPONENT wrapped_cmpy_v5_0_02d02e0a23eb9773
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tdata : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
m_axis_dout_tvalid : OUT STD_LOGIC;
m_axis_dout_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_dout_tdata : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cmpy_v5_0_02d02e0a23eb9773 USE ENTITY XilinxCoreLib.cmpy_v5_0(behavioral)
GENERIC MAP (
c_a_width => 24,
c_b_width => 24,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_s_axis_a_tlast => 0,
c_has_s_axis_a_tuser => 0,
c_has_s_axis_b_tlast => 0,
c_has_s_axis_b_tuser => 1,
c_has_s_axis_ctrl_tlast => 0,
c_has_s_axis_ctrl_tuser => 0,
c_latency => 6,
c_m_axis_dout_tdata_width => 48,
c_m_axis_dout_tuser_width => 1,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_width => 24,
c_s_axis_a_tdata_width => 48,
c_s_axis_a_tuser_width => 1,
c_s_axis_b_tdata_width => 48,
c_s_axis_b_tuser_width => 1,
c_s_axis_ctrl_tdata_width => 8,
c_s_axis_ctrl_tuser_width => 1,
c_throttle_scheme => 3,
c_tlast_resolution => 0,
c_verbosity => 0,
c_xdevice => "xc7a200t",
c_xdevicefamily => "artix7",
has_negate => 0,
round => 0,
single_output => 0,
use_dsp_cascades => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cmpy_v5_0_02d02e0a23eb9773
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tuser => s_axis_b_tuser,
s_axis_b_tdata => s_axis_b_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tuser => m_axis_dout_tuser,
m_axis_dout_tdata => m_axis_dout_tdata
);
-- synthesis translate_on
END cmpy_v5_0_02d02e0a23eb9773_a;
| lgpl-3.0 | a9e50098d1c94a50478b94bff6439b67 | 0.555134 | 3.625234 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_un_cross/cross_uncross_core/rf_ch_swap.vhd | 1 | 4,290 | ------------------------------------------------------------------------------
-- Title : RF channels Swapping
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This core controls the swapping mechanism for ONE pair of
-- channels. It is possible swapping channels inputs @ clk_in_ext
-- frequency or stay fixed at direct/inverted/off position.
--
-- MODE: 00 turned off, 01 direct, 10 inverted and 11 Swapping.
--
-- CTRL: b1b0d1d0
-- This core was developed to Sirus Synchrotron Light Source.
-- The BPM RFFE uses HSWA2-30DR+ switches and are controlled by
-- arrangement of bits in CTRL.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-10-18 1.0 jose.berkenbrock Created
-- 2012-10-20 1.1 daniel.tavares Revised
-- 2013-02-22 2.0 jose.berkenbrock New status output
-- 2013-07-01 2.1 lucas.russo Changed to synchronous resets
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rf_ch_swap is
generic
(
g_direct : std_logic_vector(7 downto 0) := "10100101";
g_inverted : std_logic_vector(7 downto 0) := "01011010"
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_swap_i : in std_logic;
mode_i : in std_logic_vector(1 downto 0);
status_o : out std_logic;
ctrl_o : out std_logic_vector(7 downto 0));
end rf_ch_swap;
architecture rtl of rf_ch_swap is
signal status : std_logic;
signal ctrl : std_logic_vector(7 downto 0);
begin
--------------------------------
-- Input Register
--------------------------------
-- p_reg_mode : process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if rst_n_i = '0' then
-- s_mode <= (others => '0');
-- else
-- s_mode <= mode_i;
-- end if;
-- end if;
-- end process p_reg_mode;
--------------------------------
-- Swapping Process
--------------------------------
p_swap : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl <= "00000000";
else
case mode_i is
when "11" => -- crossed Swapping
if en_swap_i = '0' then
ctrl <= g_direct;
else
ctrl <= g_inverted;
end if;
when "10" => -- inverted
ctrl <= g_inverted;
when "01" => -- direct
ctrl <= g_direct;
when others =>
ctrl <= (others=>'0'); -- Swapping off
end case;
end if;
end if;
end process p_swap;
--------------------------------
-- Status Flag Process
--------------------------------
p_status_flag : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
status <= '0';
else
if ctrl = g_direct then
status <= '0';
elsif ctrl = g_inverted then
status <= '1';
end if;
end if;
end if;
end process p_status_flag;
--------------------------------
-- Output Register
--------------------------------
p_output : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
ctrl_o <= (others => '0'); -- rst_n_i = 0 => Swapping off
status_o <= '0';
else
ctrl_o <= ctrl;
status_o <= status;
end if;
end if;
end process p_output;
--------------------------------
end rtl;
| lgpl-3.0 | 55f66a0643055919eeea21e878e82709 | 0.417249 | 4.268657 | false | false | false | false |
lerwys/GitTest | hdl/modules/sw_windowing/generic_multiplier.vhd | 1 | 2,933 | -------------------------------------------------------------------------------
-- Title : Generic Multiplier
-- Project :
-------------------------------------------------------------------------------
-- File : generic_multiplier.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-02-25
-- Last update: 2014-02-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A multiplier where each input and output widths are determined
-- by generics. The inputs may be both unsigned, one signed or both signed, and
-- the ouput always have only one sign bit + MSBs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-02-25 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity generic_multiplier is
generic (
g_a_width : natural := 16;
g_b_width : natural := 16;
g_signed : boolean := true;
g_p_width : natural := 16);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
clk_i : in std_logic;
reset_n_i : in std_logic);
end entity generic_multiplier;
-------------------------------------------------------------------------------
architecture behavioural of generic_multiplier is
begin -- architecture str
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
multiplication : process(clk_i)
constant c_product_width : natural := g_a_width + g_b_width;
variable product : std_logic_vector(c_product_width-1 downto 0);
begin
if rising_edge(clk_i) then
if reset_n_i = '0' then
p_o <= (others => '0');
else
-- If both are signed, there are two signals. Drop the redundancy.
if g_signed = true then
product := std_logic_vector(signed(a_i) * signed(b_i));
p_o <= product(c_product_width-2 downto c_product_width - g_p_width - 1);
else
product := std_logic_vector(unsigned(a_i) * unsigned(b_i));
p_o <= product(c_product_width-1 downto c_product_width - g_p_width);
end if;
end if; -- reset
end if; -- clk
end process multiplication;
end architecture behavioural;
-------------------------------------------------------------------------------
| lgpl-3.0 | b0fe53c11446c6b714265160952b8dec | 0.431299 | 4.589984 | false | false | false | false |
wltr/common-vhdl | generic/bit_clock_recovery/src/rtl/bit_clock_recovery.vhd | 1 | 2,638 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Generate a sampling bit clock base on a data signal as reference.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity bit_clock_recovery is
generic (
-- Number of system clock cycles per bit clock cycle
num_cycles_g : positive := 40;
-- Sampling point offset from the middle of each cycle
offset_g : integer := 0;
-- Edge type: 0 = Rising, 1 = Falling, 2 = Both
edge_type_g : natural range 0 to 2 := 2);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Reference signal
sig_i : in std_ulogic;
-- Recovered bit clock
bit_clk_o : out std_ulogic);
end entity bit_clock_recovery;
architecture rtl of bit_clock_recovery is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
constant bit_width_c : natural := integer(ceil(log2(real(num_cycles_g))));
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal edge : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Detect rising and falling edges on reference signal
edge_detector_inst : entity work.edge_detector
generic map (
init_value_g => '0',
edge_type_g => edge_type_g,
hold_flag_g => false)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => en_i,
ack_i => '0',
sig_i => sig_i,
edge_o => edge);
-- Generate strobe synchronized with detected edges
lfsr_strobe_generator_inst : entity work.lfsr_strobe_generator
generic map (
period_g => num_cycles_g,
preset_value_g => num_cycles_g / 2 - offset_g - 1)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => en_i,
pre_i => edge,
strobe_o => bit_clk_o);
end architecture rtl;
| lgpl-2.1 | 23b499e66ab84dea2c8139d6afd60294 | 0.442381 | 4.227564 | false | false | false | false |
wltr/common-vhdl | generic/mem_data_triplicator/src/rtl/mem_data_triplicator/mem_data_triplicator_addr.vhd | 1 | 2,612 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Calculate addresses for triplicated memory operations.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity mem_data_triplicator_addr is
generic (
-- Memory depth
depth_g : positive := 1048576);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g / 3)))) - 1 downto 0);
rd_en_i : in std_ulogic;
wr_en_i : in std_ulogic;
-- Memory interface
mem_addr_o : out std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
mem_done_i : in std_ulogic);
end entity mem_data_triplicator_addr;
architecture rtl of mem_data_triplicator_addr is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
constant addr_offset_c : natural := natural(floor(real(depth_g / 3)));
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal mem_addr : unsigned(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
mem_addr_o <= std_ulogic_vector(mem_addr);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Calculate addresses
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
mem_addr <= to_unsigned(0, mem_addr'length);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
if wr_en_i = '1' or rd_en_i = '1' then
mem_addr <= resize(unsigned(addr_i), mem_addr'length);
elsif mem_done_i = '1' then
mem_addr <= mem_addr + addr_offset_c;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | c587c1602921f834b2ff4f2b72660227 | 0.431087 | 4.449744 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_sampling.vhd | 1 | 2,094 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Check for changes on one of the input channels.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.ads1281_filter_pkg.all;
entity ads1281_filter_sampling is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- ADC M1 bit streams
adc_m1_i : in std_ulogic_vector(ads1281_filter_num_channels_c - 1 downto 0);
-- Change detected
changed_o : out std_ulogic);
end entity ads1281_filter_sampling;
architecture rtl of ads1281_filter_sampling is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal adc_m1 : std_ulogic_vector(adc_m1_i'range);
signal changed : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
changed_o <= changed;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
adc_m1 <= (others => '0');
changed <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Defaults
changed <= '0';
if adc_m1_i /= adc_m1 then
changed <= '1';
end if;
adc_m1 <= adc_m1_i;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 3ccbd19f26bb11a125ce24306bb0704e | 0.397803 | 4.695067 | false | false | false | false |
wltr/common-vhdl | generic/delay/src/rtl/delay.vhd | 1 | 2,692 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Delay signal through an N-stage shift register.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity delay is
generic (
-- Initial value of input signal
init_value_g : std_ulogic := '0';
-- Number of delay stages
num_delay_g : positive := 2);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Input signal
sig_i : in std_ulogic;
-- Delayed signal
dlyd_o : out std_ulogic);
end entity delay;
architecture rtl of delay is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal sig : std_ulogic_vector(num_delay_g - 1 downto 0) := (others => init_value_g);
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_sig : std_ulogic_vector(num_delay_g - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
dlyd_o <= sig(sig'high);
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Delay only for one clock cycle
single_delay_gen : if num_delay_g = 1 generate
next_sig(0) <= sig_i;
end generate single_delay_gen;
-- Delay for multiple clock cycles
multiple_delays_gen : if num_delay_g > 1 generate
next_sig <= sig(sig'high - 1 downto sig'low) & sig_i;
end generate multiple_delays_gen;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
sig <= (others => init_value_g);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
elsif en_i = '1' then
sig <= next_sig;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | b245bf1842d986c10b19a640268199de | 0.395617 | 4.985185 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/fr_cmplr_v6_3_15ffe94f3ff4129f.vhd | 1 | 6,978 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_15ffe94f3ff4129f.vhd when simulating
-- the core, fr_cmplr_v6_3_15ffe94f3ff4129f. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_15ffe94f3ff4129f IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_15ffe94f3ff4129f;
ARCHITECTURE fr_cmplr_v6_3_15ffe94f3ff4129f_a OF fr_cmplr_v6_3_15ffe94f3ff4129f IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_15ffe94f3ff4129f
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_15ffe94f3ff4129f USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "41",
c_accum_path_widths => "41",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_15ffe94f3ff4129f.mif",
c_coef_file_lines => 42,
c_coef_mem_packing => 0,
c_coef_memtype => 2,
c_coef_path_sign => "0",
c_coef_path_src => "0",
c_coef_path_widths => "16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "1",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_15ffe94f3ff4129f",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 1,
c_data_memtype => 1,
c_data_path_sign => "0",
c_data_path_src => "0",
c_data_path_widths => "24",
c_data_width => 24,
c_datapath_memtype => 2,
c_decim_rate => 2,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 2800000,
c_interp_rate => 1,
c_ipbuff_memtype => 0,
c_latency => 30,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 32,
c_m_data_tuser_width => 2,
c_mem_arrangement => 1,
c_num_channels => 4,
c_num_filts => 1,
c_num_madds => 1,
c_num_reload_slots => 1,
c_num_taps => 81,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "25",
c_output_rate => 5600000,
c_output_width => 25,
c_oversampling_rate => 21,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 24,
c_s_data_tuser_width => 2,
c_symmetry => 1,
c_xdevicefamily => "artix7",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_15ffe94f3ff4129f
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_15ffe94f3ff4129f_a;
| lgpl-3.0 | 380d5e02fa290eb318e3fce4d92df805 | 0.55288 | 3.547534 | false | false | false | false |
lerwys/GitTest | hdl/modules/sw_windowing/input_conditioner.vhd | 1 | 6,574 | -------------------------------------------------------------------------------
-- Title : Input Conditioner
-- Project :
-------------------------------------------------------------------------------
-- File : input_conditioner.vhd
-- Author : Gustavo BM Bruno
-- Company :
-- Created : 2014-01-30
-- Last update: 2014-02-26
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Define the timing for the switch at the RFFE board and apply a
-- proper window at the switch to avoid the switching noise.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-01-30 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
entity input_conditioner is
generic (
--g_clk_freq : real := 120.0e6; -- System clock frequency
--g_sw_freq : real := 100.0e3; -- Desired switching frequency
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
reset_n_i : in std_logic; -- Reset data
clk_i : in std_logic; -- Main clock
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic; -- Switch position output
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end entity input_conditioner;
architecture structural of input_conditioner is
--constant c_mem_size : natural := natural(g_clk_freq/(g_sw_freq*2.0)) + 1;
constant c_mem_size : natural := g_sw_interval/2 + 1;
constant c_bus_size : natural := f_log2_size(c_mem_size);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0) := (others => '0'); -- Current index for lookup table
signal window_factor : std_logic_vector(g_window_width-1 downto 0); -- Current value of the window
-- factor, signed int
component counter is
generic (
g_mem_size : natural;
g_bus_size : natural;
g_switch_delay : natural);
port (
clk_i : in std_logic;
index_o : out std_logic_vector(c_bus_size-1 downto 0);
ce_i : in std_logic;
switch_o : out std_logic;
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
reset_n_i : in std_logic);
end component counter;
component generic_multiplier is
generic (
g_a_width : natural;
g_b_width : natural;
g_signed : boolean;
g_p_width : natural);
port (
a_i : in std_logic_vector(g_a_width-1 downto 0);
b_i : in std_logic_vector(g_b_width-1 downto 0);
p_o : out std_logic_vector(g_p_width-1 downto 0);
clk_i : in std_logic;
reset_n_i : in std_logic);
end component generic_multiplier;
begin
cmp_lut : generic_simple_dpram
generic map (
g_data_width => g_window_width,
g_size => c_mem_size,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
--g_init_file => "./window.nif",
g_init_file => g_window_coef_file,
g_dual_clock => false
)
port map (
rst_n_i => reset_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => window_factor
);
cmp_index : counter
generic map (
g_mem_size => c_mem_size,
g_bus_size => c_bus_size,
g_switch_delay => g_input_delay
)
port map (
clk_i => clk_i,
index_o => cur_address,
ce_i => '1',
reset_n_i => reset_n_i,
switch_delay_i => switch_delay_i,
switch_o => switch_o,
switch_en_i => switch_en_i
);
dbg_cur_address_o(dbg_cur_address_o'left downto cur_address'left+1)
<= (others =>'0');
dbg_cur_address_o(cur_address'left downto 0) <= cur_address;
cmp_multiplier_a : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_a_i,
b_i => window_factor,
p_o => a_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_b : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_b_i,
b_i => window_factor,
p_o => b_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_c : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_c_i,
b_i => window_factor,
p_o => c_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
cmp_multiplier_d : generic_multiplier
generic map (
g_a_width => g_input_width,
g_b_width => g_window_width,
g_signed => true,
g_p_width => g_output_width)
port map (
a_i => adc_d_i,
b_i => window_factor,
p_o => d_o,
clk_i => clk_i,
reset_n_i => reset_n_i);
end structural;
| lgpl-3.0 | ffaed2acdd70f9e4127e1de38f6b8a39 | 0.501825 | 3.318526 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/npcs_engine.vhd | 1 | 2,406 | library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.npc_pkg.all;
use work.graphics_types_pkg.all;
entity npcs_engine is
generic (
NPC_DEFINITIONS: npc_array_type
);
port (
clock: in std_logic;
reset: in std_logic;
time_base: in std_logic;
npc_enables: in bool_vector;
npc_target_positions: in point_array_type;
npc_positions: out point_array_type
);
end;
architecture rtl of npcs_engine is
alias npcs: npc_array_type is NPC_DEFINITIONS;
begin
create_npcs: for i in npcs'range generate
npc_is_follower: if npcs(i).ai_type = AI_FOLLOWER generate
follower_npc: entity work.npc_ai_follower port map (
reset => reset, clock => clock, time_base => time_base,
allowed_region => npcs(i).allowed_region,
initial_position => npcs(i).initial_position,
absolute_speed => npcs(i).absolute_speed,
slowdown_factor => npcs(i).slowdown_factor,
enabled => npc_enables(i),
assigned_position => npc_target_positions(i),
npc_position => npc_positions(i)
);
end generate;
npc_is_bouncer: if npcs(i).ai_type = AI_BOUNCER generate
bouncer_npc: entity work.npc_ai_bouncer port map(
reset => reset, clock => clock, time_base => time_base,
initial_position => npcs(i).initial_position,
initial_speed => npcs(i).initial_speed,
allowed_region => npcs(i).allowed_region,
enabled => npc_enables(i),
npc_position => npc_positions(i)
);
end generate;
npc_is_projectile: if npcs(i).ai_type = AI_PROJECTILE generate
projectile_npc: entity work.npc_ai_projectile port map(
reset => reset, clock => clock, time_base => time_base,
initial_position => npcs(i).initial_position,
initial_speed => npcs(i).initial_speed,
allowed_region => npcs(i).allowed_region,
enabled => npc_enables(i),
assigned_position => npc_target_positions(i),
npc_position => npc_positions(i)
);
end generate;
end generate;
end;
| unlicense | 8fde610968e7bb4fc921dff7cd2dad59 | 0.549875 | 3.874396 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_roots.vhd | 1 | 2,975 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Assign root values to according index numbers.
-- Root values were calculated using the fir4.awk script.
-- z0 = 1000, z1 = 736, z2 = 128, z3 = 129
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
entity ads1281_filter_roots is
generic (
-- LFSR seed value from coefficient generator
seed_g : std_ulogic_vector(10 downto 0));
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- LFSR index value
lfsr_i : in std_ulogic_vector(10 downto 0);
-- Root value
root_o : out signed(1 downto 0));
end entity ads1281_filter_roots;
architecture rtl of ads1281_filter_roots is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal root : signed(1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
root_o <= root;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
root <= to_signed(0, root'length);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
-- Map LFSR input to the according root value
case lfsr_i is
when lfsr_shift(seed_g, 128) |
lfsr_shift(seed_g, 129) |
lfsr_shift(seed_g, 736) |
lfsr_shift(seed_g, 993) |
lfsr_shift(seed_g, 1000)|
lfsr_shift(seed_g, 1257)|
lfsr_shift(seed_g, 1864)|
lfsr_shift(seed_g, 1865) =>
root <= to_signed(-1, root'length);
when lfsr_shift(seed_g, 0) |
lfsr_shift(seed_g, 257) |
lfsr_shift(seed_g, 864) |
lfsr_shift(seed_g, 865) |
lfsr_shift(seed_g, 1128)|
lfsr_shift(seed_g, 1129)|
lfsr_shift(seed_g, 1736)|
lfsr_shift(seed_g, 1993) =>
root <= to_signed(1, root'length);
when others =>
root <= to_signed(0, root'length);
end case ;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 9830c30ea407a04523650e2f3c86b69a | 0.426555 | 4.336735 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/sprites_engine.vhd | 1 | 2,891 | library ieee;
use ieee.std_logic_1164.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.colors_pkg.all;
use work.basic_types_pkg.all;
-- It is worth noting that the sprites engine should not (and does not) access
-- any game-specific constants or code. Therefore, it can be readily reused
-- accross games without any modification. The only game-dependent values are
-- given as generics when the module is instantiated.
entity sprites_engine is
generic (
SPRITES_INITIAL_VALUES: sprites_array_type;
SPRITES_COLLISION_QUERY: sprite_collision_query_type
);
port (
clock: in std_logic;
reset: in std_logic;
raster_position: point_type;
sprites_coordinates: in point_array_type(SPRITES_INITIAL_VALUES'range);
sprites_enabled: in bool_vector(SPRITES_INITIAL_VALUES'range);
sprite_pixel: out palette_color_type;
sprite_pixel_is_valid: out boolean;
sprite_collisions_results: out bool_vector
);
end;
architecture rtl of sprites_engine is
signal sprites: sprites_array_type(SPRITES_INITIAL_VALUES'range);
begin
sprite_collisions_results <= get_sprites_collisions(sprites, SPRITES_COLLISION_QUERY);
update_sprites: process (clock, reset) begin
for i in sprites'range loop
if reset then
sprites(i) <= SPRITES_INITIAL_VALUES(i);
elsif rising_edge(clock) then
sprites(i) <= update_sprite(
sprites(i),
raster_position,
sprites_coordinates(i),
sprites_enabled(i)
);
end if;
end loop;
end process;
generate_output_pixel: process (clock, reset) is
variable pixel_is_valid: boolean := false;
variable pixel_color: palette_color_type;
begin
if reset then
sprite_pixel <= PC_TRANSPARENT;
sprite_pixel_is_valid <= false;
elsif rising_edge(clock) then
sprite_pixel <= PC_TRANSPARENT;
pixel_is_valid := false;
for i in sprites'range loop
-- if sprite_contains_coordinate(sprites(i), raster_position) then
-- only enabled sprites are drawn
if sprites(i).enabled and sprite_contains_coordinate(sprites(i), raster_position) then
pixel_color := get_sprite_pixel(sprites(i), raster_position);
if pixel_color /= PC_TRANSPARENT then
sprite_pixel <= get_sprite_pixel(sprites(i), raster_position);
pixel_is_valid := true;
end if;
end if;
end loop;
sprite_pixel_is_valid <= pixel_is_valid;
end if;
end process;
end;
| unlicense | 32dba07ea82b59a52fe3ea06924070bf | 0.589415 | 4.13 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_fifo.vhd | 1 | 2,106 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Store values needed by the decoder in a shift register.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ads1281_filter_fifo is
generic (
-- Initial value of input signal
init_value_g : std_ulogic := '0';
-- Output offset from top of FIFO
offset_g : natural := 0);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Input signal
sig_i : in std_ulogic;
-- Delayed signal
fifo_o : out std_ulogic_vector(2 downto 0));
end entity ads1281_filter_fifo;
architecture rtl of ads1281_filter_fifo is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal fifo : std_ulogic_vector(fifo_o'high + offset_g downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
fifo_o <= fifo(fifo'high downto offset_g);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
fifo <= (others => init_value_g);
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
elsif en_i = '1' then
fifo <= fifo(fifo'high - 1 downto fifo'low) & sig_i;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 4a2e72a161f505965d69e9213305492e | 0.407407 | 4.797267 | false | false | false | false |
freecores/raggedstone | source/pciwbsequ.vhd | 1 | 12,312 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: pciwbsequ.vhd |
--| |
--| Project: pci32tlite_oc |
--| |
--| Description: FSM controlling PCI to Whisbone sequence. |
--| |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Revision history : |
--| Date Version Author Description |
--| 2005-05-13 R00A00 PAU First alfa revision (eng) |
--| 2006-01-09 MS added debug signals debug_init, debug_access | |
--| |
--| To do: |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------+
--| |
--| Copyright (C) 2005 Peio Azkarate, [email protected] |
--| |
--| This source file may be used and distributed without |
--| restriction provided that this copyright statement is not |
--| removed from the file and that any derivative work contains |
--| the original copyright notice and the associated disclaimer. |
--| |
--| This source file is free software; you can redistribute it |
--| and/or modify it under the terms of the GNU Lesser General |
--| Public License as published by the Free Software Foundation; |
--| either version 2.1 of the License, or (at your option) any |
--| later version. |
--| |
--| This source is distributed in the hope that it will be |
--| useful, but WITHOUT ANY WARRANTY; without even the implied |
--| warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
--| PURPOSE. See the GNU Lesser General Public License for more |
--| details. |
--| |
--| You should have received a copy of the GNU Lesser General |
--| Public License along with this source; if not, download it |
--| from http://www.opencores.org/lgpl.shtml |
--| |
--+-----------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pciwbsequ is
port (
-- General
clk_i : in std_logic;
nrst_i : in std_logic;
-- pci
--adr_i
cmd_i : in std_logic_vector(3 downto 0);
cbe_i : in std_logic_vector(3 downto 0);
frame_i : in std_logic;
irdy_i : in std_logic;
devsel_o : out std_logic;
trdy_o : out std_logic;
-- control
adrcfg_i : in std_logic;
adrmem_i : in std_logic;
pciadrLD_o : out std_logic;
pcidOE_o : out std_logic;
parOE_o : out std_logic;
wbdatLD_o : out std_logic;
wbrgdMX_o : out std_logic;
wbd16MX_o : out std_logic;
wrcfg_o : out std_logic;
rdcfg_o : out std_logic;
-- whisbone
wb_sel_o : out std_logic_vector(1 downto 0);
wb_we_o : out std_logic;
wb_stb_o : inout std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_err_i : in std_logic;
-- debug signals
debug_init : out std_logic;
debug_access : out std_logic
);
end pciwbsequ;
architecture rtl of pciwbsequ is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
type PciFSM is ( PCIIDLE, B_BUSY, S_DATA1, S_DATA2, TURN_AR );
signal pst_pci : PciFSM;
signal nxt_pci : PciFSM;
signal sdata1 : std_logic;
signal sdata2 : std_logic;
signal idleNX : std_logic;
signal sdata1NX : std_logic;
signal sdata2NX : std_logic;
signal turnarNX : std_logic;
signal idle : std_logic;
signal devselNX_n : std_logic;
signal trdyNX_n : std_logic;
signal devsel : std_logic;
signal trdy : std_logic;
signal adrpci : std_logic;
signal acking : std_logic;
signal rdcfg : std_logic;
signal targOE : std_logic;
signal pcidOE : std_logic;
begin
--+-------------------------------------------------------------------------+
--| PCI-Whisbone Sequencer |
--+-------------------------------------------------------------------------+
--+-------------------------------------------------------------+
--| FSM PCI-Whisbone |
--+-------------------------------------------------------------+
PCIFSM_CLOCKED: process( nrst_i, clk_i, nxt_pci )
begin
if( nrst_i = '0' ) then
pst_pci <= PCIIDLE;
elsif( rising_edge(clk_i) ) then
pst_pci <= nxt_pci;
end if;
end process PCIFSM_CLOCKED;
PCIFSM_COMB: process( pst_pci, frame_i, irdy_i, adrcfg_i, adrpci, acking )
begin
devselNX_n <= '1';
trdyNX_n <= '1';
case pst_pci is
when PCIIDLE =>
if ( frame_i = '0' ) then
nxt_pci <= B_BUSY;
else
nxt_pci <= PCIIDLE;
end if;
when B_BUSY =>
if ( adrpci = '0' ) then
nxt_pci <= TURN_AR;
else
nxt_pci <= S_DATA1;
devselNX_n <= '0';
end if;
when S_DATA1 =>
if ( acking = '1' ) then
nxt_pci <= S_DATA2;
devselNX_n <= '0';
trdyNX_n <= '0';
else
nxt_pci <= S_DATA1;
devselNX_n <= '0';
end if;
when S_DATA2 =>
if ( frame_i = '1' and irdy_i = '0' ) then
nxt_pci <= TURN_AR;
else
nxt_pci <= S_DATA2;
devselNX_n <= '0';
trdyNX_n <= '0';
end if;
when TURN_AR =>
if ( frame_i = '1' ) then
nxt_pci <= PCIIDLE;
else
nxt_pci <= TURN_AR;
end if;
end case;
end process PCIFSM_COMB;
--+-------------------------------------------------------------+
--| FSM control signals |
--+-------------------------------------------------------------+
adrpci <= adrmem_i or adrcfg_i;
acking <= '1' when ( wb_ack_i = '1' or wb_err_i = '1' ) or ( adrcfg_i = '1' and irdy_i = '0')
else '0';
--+-------------------------------------------------------------+
--| FSM derived Control signals |
--+-------------------------------------------------------------+
idle <= '1' when ( pst_pci = PCIIDLE ) else '0';
sdata1 <= '1' when ( pst_pci = S_DATA1 ) else '0';
sdata2 <= '1' when ( pst_pci = S_DATA2 ) else '0';
idleNX <= '1' when ( nxt_pci = PCIIDLE ) else '0';
sdata1NX <= '1' when ( nxt_pci = S_DATA1 ) else '0';
sdata2NX <= '1' when ( nxt_pci = S_DATA2 ) else '0';
turnarNX <= '1' when ( nxt_pci = TURN_AR ) else '0';
--+-------------------------------------------------------------+
--| PCI Data Output Enable |
--+-------------------------------------------------------------+
PCIDOE_P: process( nrst_i, clk_i, cmd_i(0), sdata1NX, turnarNX )
begin
if ( nrst_i = '0' ) then
pcidOE <= '0';
elsif ( rising_edge(clk_i) ) then
if ( sdata1NX = '1' and cmd_i(0) = '0' ) then
pcidOE <= '1';
elsif ( turnarNX = '1' ) then
pcidOE <= '0';
end if;
end if;
end process PCIDOE_P;
pcidOE_o <= pcidOE;
--+-------------------------------------------------------------+
--| PAR Output Enable |
--| PCI Read data phase |
--| PAR is valid 1 cicle after data is valid |
--+-------------------------------------------------------------+
PAROE_P: process( nrst_i, clk_i, cmd_i(0), sdata2NX, turnarNX )
begin
if ( nrst_i = '0' ) then
parOE_o <= '0';
elsif ( rising_edge(clk_i) ) then
if ( ( sdata2NX = '1' or turnarNX = '1' ) and cmd_i(0) = '0' ) then
parOE_o <= '1';
else
parOE_o <= '0';
end if;
end if;
end process PAROE_P;
--+-------------------------------------------------------------+
--| Target s/t/s signals OE control |
--+-------------------------------------------------------------+
-- targOE <= '1' when ( idle = '0' and adrpci = '1' ) else '0';
TARGOE_P: process( nrst_i, clk_i, sdata1NX, idleNX )
begin
if ( nrst_i = '0' ) then
targOE <= '0';
elsif ( rising_edge(clk_i) ) then
if ( sdata1NX = '1' ) then
targOE <= '1';
elsif ( idleNX = '1' ) then
targOE <= '0';
end if;
end if;
end process TARGOE_P;
--+-------------------------------------------------------------------------+
--| WHISBONE outs |
--+-------------------------------------------------------------------------+
wb_cyc_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' ) else '0';
wb_stb_o <= '1' when ( adrmem_i = '1' and sdata1 = '1' and irdy_i = '0' ) else '0';
-- PCI(Little endian) to WB(Big endian)
wb_sel_o(1) <= (not cbe_i(0)) or (not cbe_i(2));
wb_sel_o(0) <= (not cbe_i(1)) or (not cbe_i(3));
--
wb_we_o <= cmd_i(0);
--+-------------------------------------------------------------------------+
--| Syncronized PCI outs |
--+-------------------------------------------------------------------------+
PCISIG: process( nrst_i, clk_i, devselNX_n, trdyNX_n)
begin
if( nrst_i = '0' ) then
devsel <= '1';
trdy <= '1';
elsif( rising_edge(clk_i) ) then
devsel <= devselNX_n;
trdy <= trdyNX_n;
end if;
end process PCISIG;
devsel_o <= devsel when ( targOE = '1' ) else 'Z';
trdy_o <= trdy when ( targOE = '1' ) else 'Z';
--+-------------------------------------------------------------------------+
--| Other outs |
--+-------------------------------------------------------------------------+
-- rd/wr Configuration Space Registers
wrcfg_o <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '1' and sdata2 = '1' ) else '0';
rdcfg <= '1' when ( adrcfg_i = '1' and cmd_i(0) = '0' and ( sdata1 = '1' or sdata2 = '1' ) ) else '0';
rdcfg_o <= rdcfg;
-- LoaD enable signals
pciadrLD_o <= not frame_i;
wbdatLD_o <= wb_ack_i;
-- Mux control signals
wbrgdMX_o <= not rdcfg;
wbd16MX_o <= '1' when ( cbe_i(3) = '0' or cbe_i(2) = '0' ) else '0';
--+-------------------------------------------------------------------------+
--| debug outs |
--+-------------------------------------------------------------------------+
process (nrst_i, clk_i)
begin
if ( nrst_i = '0' ) then
debug_init <= '0';
elsif clk_i'event and clk_i = '1' then
if devsel = '0' then
debug_init <= '1';
end if;
end if;
end process;
process (nrst_i, clk_i)
begin
if ( nrst_i = '0' ) then
debug_access <= '0';
elsif clk_i'event and clk_i = '1' then
if wb_stb_o = '1' then
debug_access <= '1';
end if;
end if;
end process;
end rtl;
| gpl-2.0 | 2ca4150887d41578a525464cc08842cb | 0.367284 | 3.523755 | false | false | false | false |
wltr/common-vhdl | generic/lfsr_strobe_generator/src/rtl/lfsr_strobe_generator.vhd | 1 | 3,052 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Generate a strobe when a counter reaches a certain value.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity lfsr_strobe_generator is
generic (
-- Number of clock cycles in between strobes
period_g : positive := 8;
-- Counter preset value
preset_value_g : natural := 4);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Preset
pre_i : in std_ulogic;
-- Strobe signal
strobe_o : out std_ulogic);
end entity lfsr_strobe_generator;
architecture rtl of lfsr_strobe_generator is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- LFSR counter bit length
constant len_c : natural := lfsr_length(period_g);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter strobe value
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, period_g - 1);
-- LFSR counter preset value
constant preset_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, preset_value_g);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : std_ulogic_vector(len_c - 1 downto 0) := seed_c;
signal strobe : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
strobe_o <= strobe;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Generate strobe
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= seed_c;
strobe <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
strobe <= '0';
if rst_syn_i = '1' then
reset;
elsif pre_i = '1' then
-- Preset counter to specified value
count <= preset_c;
elsif en_i = '1' then
if count = max_c then
-- Reset counter
count <= seed_c;
-- Generate strobe signal
strobe <= '1';
else
-- Increment counter
count <= lfsr_shift(count);
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | b4609d9d9ab6de2becfa39e7931490bd | 0.443971 | 4.688172 | false | false | false | false |
wltr/common-vhdl | generic/mem_data_triplicator/src/rtl/mem_data_triplicator.vhd | 1 | 4,111 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Triplicate data on write and perform majority voting on read.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity mem_data_triplicator is
generic (
-- Memory depth
depth_g : positive := 1048576;
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g / 3)))) - 1 downto 0);
rd_en_i : in std_ulogic;
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
voted_o : out std_ulogic;
-- Memory interface
mem_addr_o : out std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
mem_rd_en_o : out std_ulogic;
mem_wr_en_o : out std_ulogic;
mem_data_o : out std_ulogic_vector(width_g - 1 downto 0);
mem_data_i : in std_ulogic_vector(width_g - 1 downto 0);
mem_data_en_i : in std_ulogic;
mem_busy_i : in std_ulogic;
mem_done_i : in std_ulogic);
end entity mem_data_triplicator;
architecture rtl of mem_data_triplicator is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal wr_en : std_ulogic;
signal rd_en : std_ulogic;
signal wr_busy : std_ulogic;
signal rd_busy : std_ulogic;
signal wr_done : std_ulogic;
signal rd_data_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= wr_busy or rd_busy or mem_busy_i;
done_o <= wr_done or rd_data_en;
data_en_o <= rd_data_en;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
wr_en <= wr_en_i and (not rd_en_i);
rd_en <= rd_en_i and (not wr_en_i);
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Calculate addresses
mem_data_triplicator_addr_inst : entity work.mem_data_triplicator_addr
generic map (
depth_g => depth_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => addr_i,
rd_en_i => rd_en,
wr_en_i => wr_en,
mem_addr_o => mem_addr_o,
mem_done_i => mem_done_i);
-- Triplicate data on write
mem_data_triplicator_wr_inst : entity work.mem_data_triplicator_wr
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_en_i => wr_en,
data_i => data_i,
busy_o => wr_busy,
done_o => wr_done,
mem_wr_en_o => mem_wr_en_o,
mem_data_o => mem_data_o,
mem_done_i => mem_done_i);
-- Perform majority voting on read
mem_data_triplicator_rd_inst : entity work.mem_data_triplicator_rd
generic map (
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
rd_en_i => rd_en,
data_o => data_o,
data_en_o => rd_data_en,
busy_o => rd_busy,
voted_o => voted_o,
mem_rd_en_o => mem_rd_en_o,
mem_data_i => mem_data_i,
mem_data_en_i => mem_data_en_i);
end architecture rtl;
| lgpl-2.1 | 4e6bd96aeb623494130add89ebf1ae6d | 0.459499 | 3.440167 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/fr_cmplr_v6_3_b1697e0c92d2e32a.vhd | 1 | 6,982 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_b1697e0c92d2e32a.vhd when simulating
-- the core, fr_cmplr_v6_3_b1697e0c92d2e32a. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_b1697e0c92d2e32a IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_b1697e0c92d2e32a;
ARCHITECTURE fr_cmplr_v6_3_b1697e0c92d2e32a_a OF fr_cmplr_v6_3_b1697e0c92d2e32a IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_b1697e0c92d2e32a
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_b1697e0c92d2e32a USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "44",
c_accum_path_widths => "44",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_b1697e0c92d2e32a.mif",
c_coef_file_lines => 240,
c_coef_mem_packing => 0,
c_coef_memtype => 1,
c_coef_path_sign => "0",
c_coef_path_src => "0",
c_coef_path_widths => "16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "1",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_b1697e0c92d2e32a",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 0,
c_data_memtype => 1,
c_data_path_sign => "0",
c_data_path_src => "0",
c_data_path_widths => "25",
c_data_width => 25,
c_datapath_memtype => 2,
c_decim_rate => 10,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 5600000,
c_interp_rate => 1,
c_ipbuff_memtype => 0,
c_latency => 31,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 32,
c_m_data_tuser_width => 2,
c_mem_arrangement => 0,
c_num_channels => 4,
c_num_filts => 1,
c_num_madds => 1,
c_num_reload_slots => 1,
c_num_taps => 240,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "26",
c_output_rate => 56000000,
c_output_width => 26,
c_oversampling_rate => 24,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 32,
c_s_data_tuser_width => 2,
c_symmetry => 0,
c_xdevicefamily => "artix7",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_b1697e0c92d2e32a
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_b1697e0c92d2e32a_a;
| lgpl-3.0 | 25f20f01e0570af8b6da8b8fe2133d0e | 0.553137 | 3.485771 | false | false | false | false |
lerwys/GitTest | hdl/platform/virtex6/multiplier_16x10_DSP.vhd | 1 | 4,275 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file multiplier_16x10_DSP.vhd when simulating
-- the core, multiplier_16x10_DSP. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier_16x10_DSP IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END multiplier_16x10_DSP;
ARCHITECTURE multiplier_16x10_DSP_a OF multiplier_16x10_DSP IS
-- synthesis translate_off
COMPONENT wrapped_multiplier_16x10_DSP
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(25 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_multiplier_16x10_DSP USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 16,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 10,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 3,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 25,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier_16x10_DSP
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END multiplier_16x10_DSP_a;
| lgpl-3.0 | a261b00b21d8138ff297dec9127bf2b2 | 0.544327 | 4.514256 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/ddc_bpm_476_066_cw.vhd | 2 | 53,901 |
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockdriver is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end xlclockdriver;
architecture behavior of xlclockdriver is
component bufg
port (
i: in std_logic;
o: out std_logic
);
end component;
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT : string;
attribute MAX_FANOUT of ce_vec:signal is "REDUCE";
signal ce_vec_logic : std_logic_vector(num_pipeline_regs downto 0);
attribute MAX_FANOUT of ce_vec_logic:signal is "REDUCE";
signal internal_ce: std_logic_vector(0 downto 0);
signal internal_ce_logic: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
clk <= sysclk;
clr <= sysclr;
cntr_gen: process(sysclk)
begin
if sysclk'event and sysclk = '1' then
if (sysce = '1') then
if ((cnt_clr_dly(0) = '1') or (sysclr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end if;
end process;
clr_gen: process(clk_num, sysclr)
begin
if power_of_2_counter then
cnt_clr(0) <= sysclr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or sysclr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => sysce,
clr => sysclr,
clk => sysclk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
pipelined_ce_logic: if period > 1 generate
ce_gen_logic: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec_logic(num_pipeline_regs) <= '1';
else
ce_vec_logic(num_pipeline_regs) <= '0';
end if;
end process;
ce_logic_pipeline: for index in num_pipeline_regs downto 1 generate
ce_logic_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec_logic(index downto index),
ce => sysce,
clr => sysclr,
clk => sysclk,
o => ce_vec_logic(index-1 downto index-1)
);
end generate;
internal_ce_logic <= ce_vec_logic(0 downto 0);
end generate;
use_bufg_true: if period > 1 and use_bufg = 1 generate
ce_bufg_inst: bufg
port map (
i => internal_ce(0),
o => ce
);
ce_bufg_inst_logic: bufg
port map (
i => internal_ce_logic(0),
o => ce_logic
);
end generate;
use_bufg_false: if period > 1 and (use_bufg = 0) generate
ce <= internal_ce(0);
ce_logic <= internal_ce_logic(0);
end generate;
generate_system_clk: if period = 1 generate
ce <= sysce;
ce_logic <= sysce;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity default_clock_driver is
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
ce_10000: out std_logic;
ce_1120: out std_logic;
ce_1400000: out std_logic;
ce_2: out std_logic;
ce_2240: out std_logic;
ce_22400000: out std_logic;
ce_224000000: out std_logic;
ce_2500: out std_logic;
ce_2800000: out std_logic;
ce_35: out std_logic;
ce_4480: out std_logic;
ce_44800000: out std_logic;
ce_5000: out std_logic;
ce_560: out std_logic;
ce_5600000: out std_logic;
ce_56000000: out std_logic;
ce_70: out std_logic;
ce_logic_1: out std_logic;
ce_logic_1400000: out std_logic;
ce_logic_2240: out std_logic;
ce_logic_22400000: out std_logic;
ce_logic_2800000: out std_logic;
ce_logic_560: out std_logic;
ce_logic_5600000: out std_logic;
ce_logic_70: out std_logic;
clk_1: out std_logic;
clk_10000: out std_logic;
clk_1120: out std_logic;
clk_1400000: out std_logic;
clk_2: out std_logic;
clk_2240: out std_logic;
clk_22400000: out std_logic;
clk_224000000: out std_logic;
clk_2500: out std_logic;
clk_2800000: out std_logic;
clk_35: out std_logic;
clk_4480: out std_logic;
clk_44800000: out std_logic;
clk_5000: out std_logic;
clk_560: out std_logic;
clk_5600000: out std_logic;
clk_56000000: out std_logic;
clk_70: out std_logic
);
end default_clock_driver;
architecture structural of default_clock_driver is
attribute syn_noprune: boolean;
attribute syn_noprune of structural : architecture is true;
attribute optimize_primitives: boolean;
attribute optimize_primitives of structural : architecture is false;
attribute dont_touch: boolean;
attribute dont_touch of structural : architecture is true;
signal sysce_clr_x0: std_logic;
signal sysce_x0: std_logic;
signal sysclk_x0: std_logic;
signal xlclockdriver_10000_ce: std_logic;
signal xlclockdriver_10000_clk: std_logic;
signal xlclockdriver_1120_ce: std_logic;
signal xlclockdriver_1120_clk: std_logic;
signal xlclockdriver_1400000_ce: std_logic;
signal xlclockdriver_1400000_ce_logic: std_logic;
signal xlclockdriver_1400000_clk: std_logic;
signal xlclockdriver_1_ce: std_logic;
signal xlclockdriver_1_ce_logic: std_logic;
signal xlclockdriver_1_clk: std_logic;
signal xlclockdriver_224000000_ce: std_logic;
signal xlclockdriver_224000000_clk: std_logic;
signal xlclockdriver_22400000_ce: std_logic;
signal xlclockdriver_22400000_ce_logic: std_logic;
signal xlclockdriver_22400000_clk: std_logic;
signal xlclockdriver_2240_ce: std_logic;
signal xlclockdriver_2240_ce_logic: std_logic;
signal xlclockdriver_2240_clk: std_logic;
signal xlclockdriver_2500_ce: std_logic;
signal xlclockdriver_2500_clk: std_logic;
signal xlclockdriver_2800000_ce: std_logic;
signal xlclockdriver_2800000_ce_logic: std_logic;
signal xlclockdriver_2800000_clk: std_logic;
signal xlclockdriver_2_ce: std_logic;
signal xlclockdriver_2_clk: std_logic;
signal xlclockdriver_35_ce: std_logic;
signal xlclockdriver_35_clk: std_logic;
signal xlclockdriver_44800000_ce: std_logic;
signal xlclockdriver_44800000_clk: std_logic;
signal xlclockdriver_4480_ce: std_logic;
signal xlclockdriver_4480_clk: std_logic;
signal xlclockdriver_5000_ce: std_logic;
signal xlclockdriver_5000_clk: std_logic;
signal xlclockdriver_56000000_ce: std_logic;
signal xlclockdriver_56000000_clk: std_logic;
signal xlclockdriver_5600000_ce: std_logic;
signal xlclockdriver_5600000_ce_logic: std_logic;
signal xlclockdriver_5600000_clk: std_logic;
signal xlclockdriver_560_ce: std_logic;
signal xlclockdriver_560_ce_logic: std_logic;
signal xlclockdriver_560_clk: std_logic;
signal xlclockdriver_70_ce: std_logic;
signal xlclockdriver_70_ce_logic: std_logic;
signal xlclockdriver_70_clk: std_logic;
begin
sysce_x0 <= sysce;
sysce_clr_x0 <= sysce_clr;
sysclk_x0 <= sysclk;
ce_1 <= xlclockdriver_1_ce;
ce_10000 <= xlclockdriver_10000_ce;
ce_1120 <= xlclockdriver_1120_ce;
ce_1400000 <= xlclockdriver_1400000_ce;
ce_2 <= xlclockdriver_2_ce;
ce_2240 <= xlclockdriver_2240_ce;
ce_22400000 <= xlclockdriver_22400000_ce;
ce_224000000 <= xlclockdriver_224000000_ce;
ce_2500 <= xlclockdriver_2500_ce;
ce_2800000 <= xlclockdriver_2800000_ce;
ce_35 <= xlclockdriver_35_ce;
ce_4480 <= xlclockdriver_4480_ce;
ce_44800000 <= xlclockdriver_44800000_ce;
ce_5000 <= xlclockdriver_5000_ce;
ce_560 <= xlclockdriver_560_ce;
ce_5600000 <= xlclockdriver_5600000_ce;
ce_56000000 <= xlclockdriver_56000000_ce;
ce_70 <= xlclockdriver_70_ce;
ce_logic_1 <= xlclockdriver_1_ce_logic;
ce_logic_1400000 <= xlclockdriver_1400000_ce_logic;
ce_logic_2240 <= xlclockdriver_2240_ce_logic;
ce_logic_22400000 <= xlclockdriver_22400000_ce_logic;
ce_logic_2800000 <= xlclockdriver_2800000_ce_logic;
ce_logic_560 <= xlclockdriver_560_ce_logic;
ce_logic_5600000 <= xlclockdriver_5600000_ce_logic;
ce_logic_70 <= xlclockdriver_70_ce_logic;
clk_1 <= xlclockdriver_1_clk;
clk_10000 <= xlclockdriver_10000_clk;
clk_1120 <= xlclockdriver_1120_clk;
clk_1400000 <= xlclockdriver_1400000_clk;
clk_2 <= xlclockdriver_2_clk;
clk_2240 <= xlclockdriver_2240_clk;
clk_22400000 <= xlclockdriver_22400000_clk;
clk_224000000 <= xlclockdriver_224000000_clk;
clk_2500 <= xlclockdriver_2500_clk;
clk_2800000 <= xlclockdriver_2800000_clk;
clk_35 <= xlclockdriver_35_clk;
clk_4480 <= xlclockdriver_4480_clk;
clk_44800000 <= xlclockdriver_44800000_clk;
clk_5000 <= xlclockdriver_5000_clk;
clk_560 <= xlclockdriver_560_clk;
clk_5600000 <= xlclockdriver_5600000_clk;
clk_56000000 <= xlclockdriver_56000000_clk;
clk_70 <= xlclockdriver_70_clk;
xlclockdriver_1: entity work.xlclockdriver
generic map (
log_2_period => 1,
period => 1,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1_ce,
ce_logic => xlclockdriver_1_ce_logic,
clk => xlclockdriver_1_clk
);
xlclockdriver_10000: entity work.xlclockdriver
generic map (
log_2_period => 14,
period => 10000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_10000_ce,
clk => xlclockdriver_10000_clk
);
xlclockdriver_1120: entity work.xlclockdriver
generic map (
log_2_period => 11,
period => 1120,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1120_ce,
clk => xlclockdriver_1120_clk
);
xlclockdriver_1400000: entity work.xlclockdriver
generic map (
log_2_period => 21,
period => 1400000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_1400000_ce,
ce_logic => xlclockdriver_1400000_ce_logic,
clk => xlclockdriver_1400000_clk
);
xlclockdriver_2: entity work.xlclockdriver
generic map (
log_2_period => 2,
period => 2,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2_ce,
clk => xlclockdriver_2_clk
);
xlclockdriver_2240: entity work.xlclockdriver
generic map (
log_2_period => 12,
period => 2240,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2240_ce,
ce_logic => xlclockdriver_2240_ce_logic,
clk => xlclockdriver_2240_clk
);
xlclockdriver_22400000: entity work.xlclockdriver
generic map (
log_2_period => 25,
period => 22400000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_22400000_ce,
ce_logic => xlclockdriver_22400000_ce_logic,
clk => xlclockdriver_22400000_clk
);
xlclockdriver_224000000: entity work.xlclockdriver
generic map (
log_2_period => 28,
period => 224000000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_224000000_ce,
clk => xlclockdriver_224000000_clk
);
xlclockdriver_2500: entity work.xlclockdriver
generic map (
log_2_period => 12,
period => 2500,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2500_ce,
clk => xlclockdriver_2500_clk
);
xlclockdriver_2800000: entity work.xlclockdriver
generic map (
log_2_period => 22,
period => 2800000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_2800000_ce,
ce_logic => xlclockdriver_2800000_ce_logic,
clk => xlclockdriver_2800000_clk
);
xlclockdriver_35: entity work.xlclockdriver
generic map (
log_2_period => 6,
period => 35,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_35_ce,
clk => xlclockdriver_35_clk
);
xlclockdriver_4480: entity work.xlclockdriver
generic map (
log_2_period => 13,
period => 4480,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_4480_ce,
clk => xlclockdriver_4480_clk
);
xlclockdriver_44800000: entity work.xlclockdriver
generic map (
log_2_period => 26,
period => 44800000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_44800000_ce,
clk => xlclockdriver_44800000_clk
);
xlclockdriver_5000: entity work.xlclockdriver
generic map (
log_2_period => 13,
period => 5000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_5000_ce,
clk => xlclockdriver_5000_clk
);
xlclockdriver_560: entity work.xlclockdriver
generic map (
log_2_period => 10,
period => 560,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_560_ce,
ce_logic => xlclockdriver_560_ce_logic,
clk => xlclockdriver_560_clk
);
xlclockdriver_5600000: entity work.xlclockdriver
generic map (
log_2_period => 23,
period => 5600000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_5600000_ce,
ce_logic => xlclockdriver_5600000_ce_logic,
clk => xlclockdriver_5600000_clk
);
xlclockdriver_56000000: entity work.xlclockdriver
generic map (
log_2_period => 26,
period => 56000000,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_56000000_ce,
clk => xlclockdriver_56000000_clk
);
xlclockdriver_70: entity work.xlclockdriver
generic map (
log_2_period => 7,
period => 70,
use_bufg => 0
)
port map (
sysce => sysce_x0,
sysclk => sysclk_x0,
sysclr => sysce_clr_x0,
ce => xlclockdriver_70_ce,
ce_logic => xlclockdriver_70_ce_logic,
clk => xlclockdriver_70_clk
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity ddc_bpm_476_066_cw is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce: in std_logic := '1';
ce_clr: in std_logic := '1';
clk: in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066_cw;
architecture structural of ddc_bpm_476_066_cw is
component xlpersistentdff
port (
clk: in std_logic;
d: in std_logic;
q: out std_logic
);
end component;
attribute syn_black_box: boolean;
attribute syn_black_box of xlpersistentdff: component is true;
attribute box_type: string;
attribute box_type of xlpersistentdff: component is "black_box";
attribute syn_noprune: boolean;
attribute optimize_primitives: boolean;
attribute dont_touch: boolean;
attribute syn_noprune of xlpersistentdff: component is true;
attribute optimize_primitives of xlpersistentdff: component is false;
attribute dont_touch of xlpersistentdff: component is true;
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
attribute MAX_FANOUT: string;
attribute MAX_FANOUT of ce_10000_sg_x2: signal is "REDUCE";
signal ce_1120_sg_x32: std_logic;
attribute MAX_FANOUT of ce_1120_sg_x32: signal is "REDUCE";
signal ce_1400000_sg_x3: std_logic;
attribute MAX_FANOUT of ce_1400000_sg_x3: signal is "REDUCE";
signal ce_1_sg_x96: std_logic;
attribute MAX_FANOUT of ce_1_sg_x96: signal is "REDUCE";
signal ce_224000000_sg_x7: std_logic;
attribute MAX_FANOUT of ce_224000000_sg_x7: signal is "REDUCE";
signal ce_22400000_sg_x28: std_logic;
attribute MAX_FANOUT of ce_22400000_sg_x28: signal is "REDUCE";
signal ce_2240_sg_x28: std_logic;
attribute MAX_FANOUT of ce_2240_sg_x28: signal is "REDUCE";
signal ce_2500_sg_x3: std_logic;
attribute MAX_FANOUT of ce_2500_sg_x3: signal is "REDUCE";
signal ce_2800000_sg_x4: std_logic;
attribute MAX_FANOUT of ce_2800000_sg_x4: signal is "REDUCE";
signal ce_2_sg_x38: std_logic;
attribute MAX_FANOUT of ce_2_sg_x38: signal is "REDUCE";
signal ce_35_sg_x22: std_logic;
attribute MAX_FANOUT of ce_35_sg_x22: signal is "REDUCE";
signal ce_44800000_sg_x2: std_logic;
attribute MAX_FANOUT of ce_44800000_sg_x2: signal is "REDUCE";
signal ce_4480_sg_x9: std_logic;
attribute MAX_FANOUT of ce_4480_sg_x9: signal is "REDUCE";
signal ce_5000_sg_x9: std_logic;
attribute MAX_FANOUT of ce_5000_sg_x9: signal is "REDUCE";
signal ce_56000000_sg_x5: std_logic;
attribute MAX_FANOUT of ce_56000000_sg_x5: signal is "REDUCE";
signal ce_5600000_sg_x12: std_logic;
attribute MAX_FANOUT of ce_5600000_sg_x12: signal is "REDUCE";
signal ce_560_sg_x3: std_logic;
attribute MAX_FANOUT of ce_560_sg_x3: signal is "REDUCE";
signal ce_70_sg_x27: std_logic;
attribute MAX_FANOUT of ce_70_sg_x27: signal is "REDUCE";
signal ce_clr_x0: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clkNet: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal persistentdff_inst_q: std_logic;
attribute syn_keep: boolean;
attribute syn_keep of persistentdff_inst_q: signal is true;
attribute keep: boolean;
attribute keep of persistentdff_inst_q: signal is true;
attribute preserve_signal: boolean;
attribute preserve_signal of persistentdff_inst_q: signal is true;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_clr_x0 <= ce_clr;
clkNet <= clk;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
ddc_bpm_476_066_x0: entity work.ddc_bpm_476_066
port map (
adc_ch0_i => adc_ch0_i_net,
adc_ch1_i => adc_ch1_i_net,
adc_ch2_i => adc_ch2_i_net,
adc_ch3_i => adc_ch3_i_net,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_1120 => ce_1120_sg_x32,
ce_1400000 => ce_1400000_sg_x3,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_22400000 => ce_22400000_sg_x28,
ce_224000000 => ce_224000000_sg_x7,
ce_2500 => ce_2500_sg_x3,
ce_2800000 => ce_2800000_sg_x4,
ce_35 => ce_35_sg_x22,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2240 => ce_logic_2240_sg_x1,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_1120 => clk_1120_sg_x32,
clk_1400000 => clk_1400000_sg_x3,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
clk_22400000 => clk_22400000_sg_x28,
clk_224000000 => clk_224000000_sg_x7,
clk_2500 => clk_2500_sg_x3,
clk_2800000 => clk_2800000_sg_x4,
clk_35 => clk_35_sg_x22,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
clk_70 => clk_70_sg_x27,
dds_config_valid_ch0_i => dds_config_valid_ch0_i_net,
dds_config_valid_ch1_i => dds_config_valid_ch1_i_net,
dds_config_valid_ch2_i => dds_config_valid_ch2_i_net,
dds_config_valid_ch3_i => dds_config_valid_ch3_i_net,
dds_pinc_ch0_i => dds_pinc_ch0_i_net,
dds_pinc_ch1_i => dds_pinc_ch1_i_net,
dds_pinc_ch2_i => dds_pinc_ch2_i_net,
dds_pinc_ch3_i => dds_pinc_ch3_i_net,
dds_poff_ch0_i => dds_poff_ch0_i_net,
dds_poff_ch1_i => dds_poff_ch1_i_net,
dds_poff_ch2_i => dds_poff_ch2_i_net,
dds_poff_ch3_i => dds_poff_ch3_i_net,
del_sig_div_fofb_thres_i => del_sig_div_fofb_thres_i_net,
del_sig_div_monit_thres_i => del_sig_div_monit_thres_i_net,
del_sig_div_tbt_thres_i => del_sig_div_tbt_thres_i_net,
ksum_i => ksum_i_net,
kx_i => kx_i_net,
ky_i => ky_i_net,
adc_ch0_dbg_data_o => adc_ch0_dbg_data_o_net,
adc_ch1_dbg_data_o => adc_ch1_dbg_data_o_net,
adc_ch2_dbg_data_o => adc_ch2_dbg_data_o_net,
adc_ch3_dbg_data_o => adc_ch3_dbg_data_o_net,
bpf_ch0_o => bpf_ch0_o_net,
bpf_ch1_o => bpf_ch1_o_net,
bpf_ch2_o => bpf_ch2_o_net,
bpf_ch3_o => bpf_ch3_o_net,
cic_fofb_q_01_missing_o => cic_fofb_q_01_missing_o_net,
cic_fofb_q_23_missing_o => cic_fofb_q_23_missing_o_net,
fofb_amp_ch0_o => fofb_amp_ch0_o_net,
fofb_amp_ch1_o => fofb_amp_ch1_o_net,
fofb_amp_ch2_o => fofb_amp_ch2_o_net,
fofb_amp_ch3_o => fofb_amp_ch3_o_net,
fofb_decim_ch0_i_o => fofb_decim_ch0_i_o_net,
fofb_decim_ch0_q_o => fofb_decim_ch0_q_o_net,
fofb_decim_ch1_i_o => fofb_decim_ch1_i_o_net,
fofb_decim_ch1_q_o => fofb_decim_ch1_q_o_net,
fofb_decim_ch2_i_o => fofb_decim_ch2_i_o_net,
fofb_decim_ch2_q_o => fofb_decim_ch2_q_o_net,
fofb_decim_ch3_i_o => fofb_decim_ch3_i_o_net,
fofb_decim_ch3_q_o => fofb_decim_ch3_q_o_net,
fofb_pha_ch0_o => fofb_pha_ch0_o_net,
fofb_pha_ch1_o => fofb_pha_ch1_o_net,
fofb_pha_ch2_o => fofb_pha_ch2_o_net,
fofb_pha_ch3_o => fofb_pha_ch3_o_net,
mix_ch0_i_o => mix_ch0_i_o_net,
mix_ch0_q_o => mix_ch0_q_o_net,
mix_ch1_i_o => mix_ch1_i_o_net,
mix_ch1_q_o => mix_ch1_q_o_net,
mix_ch2_i_o => mix_ch2_i_o_net,
mix_ch2_q_o => mix_ch2_q_o_net,
mix_ch3_i_o => mix_ch3_i_o_net,
mix_ch3_q_o => mix_ch3_q_o_net,
monit_amp_ch0_o => monit_amp_ch0_o_net,
monit_amp_ch1_o => monit_amp_ch1_o_net,
monit_amp_ch2_o => monit_amp_ch2_o_net,
monit_amp_ch3_o => monit_amp_ch3_o_net,
monit_cfir_incorrect_o => monit_cfir_incorrect_o_net,
monit_cic_unexpected_o => monit_cic_unexpected_o_net,
monit_pfir_incorrect_o => monit_pfir_incorrect_o_net,
monit_pos_1_incorrect_o => monit_pos_1_incorrect_o_net,
q_fofb_o => q_fofb_o_net,
q_fofb_valid_o => q_fofb_valid_o_net,
q_monit_1_o => q_monit_1_o_net,
q_monit_1_valid_o => q_monit_1_valid_o_net,
q_monit_o => q_monit_o_net,
q_monit_valid_o => q_monit_valid_o_net,
q_tbt_o => q_tbt_o_net,
q_tbt_valid_o => q_tbt_valid_o_net,
sum_fofb_o => sum_fofb_o_net,
sum_fofb_valid_o => sum_fofb_valid_o_net,
sum_monit_1_o => sum_monit_1_o_net,
sum_monit_1_valid_o => sum_monit_1_valid_o_net,
sum_monit_o => sum_monit_o_net,
sum_monit_valid_o => sum_monit_valid_o_net,
sum_tbt_o => sum_tbt_o_net,
sum_tbt_valid_o => sum_tbt_valid_o_net,
tbt_amp_ch0_o => tbt_amp_ch0_o_net,
tbt_amp_ch1_o => tbt_amp_ch1_o_net,
tbt_amp_ch2_o => tbt_amp_ch2_o_net,
tbt_amp_ch3_o => tbt_amp_ch3_o_net,
tbt_decim_ch01_incorrect_o => tbt_decim_ch01_incorrect_o_net,
tbt_decim_ch0_i_o => tbt_decim_ch0_i_o_net,
tbt_decim_ch0_q_o => tbt_decim_ch0_q_o_net,
tbt_decim_ch1_i_o => tbt_decim_ch1_i_o_net,
tbt_decim_ch1_q_o => tbt_decim_ch1_q_o_net,
tbt_decim_ch23_incorrect_o => tbt_decim_ch23_incorrect_o_net,
tbt_decim_ch2_i_o => tbt_decim_ch2_i_o_net,
tbt_decim_ch2_q_o => tbt_decim_ch2_q_o_net,
tbt_decim_ch3_i_o => tbt_decim_ch3_i_o_net,
tbt_decim_ch3_q_o => tbt_decim_ch3_q_o_net,
tbt_pha_ch0_o => tbt_pha_ch0_o_net,
tbt_pha_ch1_o => tbt_pha_ch1_o_net,
tbt_pha_ch2_o => tbt_pha_ch2_o_net,
tbt_pha_ch3_o => tbt_pha_ch3_o_net,
x_fofb_o => x_fofb_o_net,
x_fofb_valid_o => x_fofb_valid_o_net,
x_monit_1_o => x_monit_1_o_net,
x_monit_1_valid_o => x_monit_1_valid_o_net,
x_monit_o => x_monit_o_net,
x_monit_valid_o => x_monit_valid_o_net,
x_tbt_o => x_tbt_o_net,
x_tbt_valid_o => x_tbt_valid_o_net,
y_fofb_o => y_fofb_o_net,
y_fofb_valid_o => y_fofb_valid_o_net,
y_monit_1_o => y_monit_1_o_net,
y_monit_1_valid_o => y_monit_1_valid_o_net,
y_monit_o => y_monit_o_net,
y_monit_valid_o => y_monit_valid_o_net,
y_tbt_o => y_tbt_o_net,
y_tbt_valid_o => y_tbt_valid_o_net
);
default_clock_driver_x0: entity work.default_clock_driver
port map (
sysce => '1',
sysce_clr => ce_clr_x0,
sysclk => clkNet,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_1120 => ce_1120_sg_x32,
ce_1400000 => ce_1400000_sg_x3,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_22400000 => ce_22400000_sg_x28,
ce_224000000 => ce_224000000_sg_x7,
ce_2500 => ce_2500_sg_x3,
ce_2800000 => ce_2800000_sg_x4,
ce_35 => ce_35_sg_x22,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2240 => ce_logic_2240_sg_x1,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_1120 => clk_1120_sg_x32,
clk_1400000 => clk_1400000_sg_x3,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
clk_22400000 => clk_22400000_sg_x28,
clk_224000000 => clk_224000000_sg_x7,
clk_2500 => clk_2500_sg_x3,
clk_2800000 => clk_2800000_sg_x4,
clk_35 => clk_35_sg_x22,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
clk_70 => clk_70_sg_x27
);
persistentdff_inst: xlpersistentdff
port map (
clk => clkNet,
d => persistentdff_inst_q,
q => persistentdff_inst_q
);
end structural;
| lgpl-3.0 | e0e32e848dbec0935e492132b578ad11 | 0.637502 | 2.80486 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/nonleaf_results.vhd | 1 | 484,765 | library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF/zero_filling1"
entity zero_filling1_entity_d0ac9899b1 is
port (
in1: in std_logic_vector(15 downto 0);
out1: out std_logic_vector(23 downto 0)
);
end zero_filling1_entity_d0ac9899b1;
architecture structural of zero_filling1_entity_d0ac9899b1 is
signal concat_y_net: std_logic_vector(23 downto 0);
signal constant_op_net: std_logic_vector(7 downto 0);
signal register1_q_net_x0: std_logic_vector(15 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(7 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(15 downto 0);
begin
register1_q_net_x0 <= in1;
out1 <= reinterpret2_output_port_net_x0;
concat: entity work.concat_cd3162dc0d
port map (
ce => '0',
clk => '0',
clr => '0',
in0 => reinterpret_output_port_net,
in1 => reinterpret1_output_port_net,
y => concat_y_net
);
constant_x0: entity work.constant_91ef1678ca
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
reinterpret: entity work.reinterpret_7025463ea8
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register1_q_net_x0,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_f21e7f2ddf
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => constant_op_net,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => concat_y_net,
output_port => reinterpret2_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/BPF"
entity bpf_entity_d31c4af409 is
port (
din_ch0: in std_logic_vector(15 downto 0);
din_ch1: in std_logic_vector(15 downto 0);
din_ch2: in std_logic_vector(15 downto 0);
din_ch3: in std_logic_vector(15 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end bpf_entity_d31c4af409;
architecture structural of bpf_entity_d31c4af409 is
signal register1_q_net_x1: std_logic_vector(15 downto 0);
signal register2_q_net_x1: std_logic_vector(15 downto 0);
signal register3_q_net_x1: std_logic_vector(15 downto 0);
signal register_q_net_x1: std_logic_vector(15 downto 0);
signal reinterpret2_output_port_net_x4: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x5: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x6: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x7: std_logic_vector(23 downto 0);
begin
register_q_net_x1 <= din_ch0;
register1_q_net_x1 <= din_ch1;
register2_q_net_x1 <= din_ch2;
register3_q_net_x1 <= din_ch3;
dout_ch0 <= reinterpret2_output_port_net_x7;
dout_ch1 <= reinterpret2_output_port_net_x4;
dout_ch2 <= reinterpret2_output_port_net_x5;
dout_ch3 <= reinterpret2_output_port_net_x6;
zero_filling1_d0ac9899b1: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register1_q_net_x1,
out1 => reinterpret2_output_port_net_x4
);
zero_filling2_d7e27e9bae: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register2_q_net_x1,
out1 => reinterpret2_output_port_net_x5
);
zero_filling3_1ae3b6c91e: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register3_q_net_x1,
out1 => reinterpret2_output_port_net_x6
);
zero_filling4_6d7b2d0c57: entity work.zero_filling1_entity_d0ac9899b1
port map (
in1 => register_q_net_x1,
out1 => reinterpret2_output_port_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub/TDM_dds_ch01_cosine"
entity tdm_dds_ch01_cosine_entity_4b8bfc9243 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
rst: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_dds_ch01_cosine_entity_4b8bfc9243;
architecture structural of tdm_dds_ch01_cosine_entity_4b8bfc9243 is
signal black_box_cos_o_net_x0: std_logic_vector(23 downto 0);
signal ce_1_sg_x0: std_logic;
signal ce_2_sg_x0: std_logic;
signal ce_logic_1_sg_x0: std_logic;
signal clk_1_sg_x0: std_logic;
signal clk_2_sg_x0: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant11_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register4_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x0 <= ce_1;
ce_2_sg_x0 <= ce_2;
ce_logic_1_sg_x0 <= ce_logic_1;
clk_1_sg_x0 <= clk_1;
clk_2_sg_x0 <= clk_2;
black_box_cos_o_net_x0 <= din_ch0;
constant11_op_net_x0 <= rst;
dout <= register_q_net_x0;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x0,
clk => clk_1_sg_x0,
d => register2_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => register2_q_net,
d1 => register3_q_net,
sel(0) => register4_q_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op(0) => mux_sel1_op_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch0_q_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => up_sample_ch1_q_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register4_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x0,
clk => clk_1_sg_x0,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => black_box_cos_o_net_x0,
dest_ce => ce_1_sg_x0,
dest_clk => clk_1_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x0,
src_clk => clk_2_sg_x0,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/DDS_sub"
entity dds_sub_entity_a4b6b880f6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_01_cosine: out std_logic_vector(23 downto 0);
dds_01_sine: out std_logic_vector(23 downto 0);
dds_23_cosine: out std_logic_vector(23 downto 0);
dds_23_sine: out std_logic_vector(23 downto 0)
);
end dds_sub_entity_a4b6b880f6;
architecture structural of dds_sub_entity_a4b6b880f6 is
signal black_box_cos_o_net_x1: std_logic_vector(23 downto 0);
signal black_box_sin_o_net_x1: std_logic_vector(23 downto 0);
signal ce_1_sg_x4: std_logic;
signal ce_2_sg_x4: std_logic;
signal ce_logic_1_sg_x4: std_logic;
signal clk_1_sg_x4: std_logic;
signal clk_2_sg_x4: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant16_op_net_x0: std_logic;
signal constant17_op_net_x0: std_logic;
signal constant3_op_net: std_logic;
signal constant7_op_net_x0: std_logic;
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
begin
ce_1_sg_x4 <= ce_1;
ce_2_sg_x4 <= ce_2;
ce_logic_1_sg_x4 <= ce_logic_1;
clk_1_sg_x4 <= clk_1;
clk_2_sg_x4 <= clk_2;
dds_01_cosine <= register_q_net_x4;
dds_01_sine <= register_q_net_x5;
dds_23_cosine <= register_q_net_x6;
dds_23_sine <= register_q_net_x7;
black_box: entity work.fixed_dds
generic map (
g_cos_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos.ram",
g_dither => false,
g_number_of_points => 148,
g_output_width => 24,
g_sin_file => "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin.ram"
)
port map (
ce_i => ce_2_sg_x4,
clk_i => clk_2_sg_x4,
rst_n_i => constant3_op_net,
cos_o => black_box_cos_o_net_x1,
sin_o => black_box_sin_o_net_x1
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant16: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant16_op_net_x0
);
constant17: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant17_op_net_x0
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net
);
constant7: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant7_op_net_x0
);
tdm_dds_ch01_cosine_4b8bfc9243: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant11_op_net_x0,
dout => register_q_net_x4
);
tdm_dds_ch01_sine_1129eb9762: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant7_op_net_x0,
dout => register_q_net_x5
);
tdm_dds_ch23_cosine_398d5cee32: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_cos_o_net_x1,
rst => constant16_op_net_x0,
dout => register_q_net_x6
);
tdm_dds_ch23_sine_782ff6a42a: entity work.tdm_dds_ch01_cosine_entity_4b8bfc9243
port map (
ce_1 => ce_1_sg_x4,
ce_2 => ce_2_sg_x4,
ce_logic_1 => ce_logic_1_sg_x4,
clk_1 => clk_1_sg_x4,
clk_2 => clk_2_sg_x4,
din_ch0 => black_box_sin_o_net_x1,
rst => constant17_op_net_x0,
dout => register_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch/TDDM_fofb_amp0"
entity tddm_fofb_amp0_entity_fd74c6ad6e is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp0_entity_fd74c6ad6e;
architecture structural of tddm_fofb_amp0_entity_fd74c6ad6e is
signal assert2_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x0: std_logic;
signal ce_1120_sg_x0: std_logic;
signal ce_2240_sg_x0: std_logic;
signal clk_1120_sg_x0: std_logic;
signal clk_2240_sg_x0: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x0 <= ce_1120;
ce_2240_sg_x0 <= ce_2240;
assert3_dout_net_x0 <= ch_in;
clk_1120_sg_x0 <= clk_1120;
clk_2240_sg_x0 <= clk_2240;
assert2_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x0,
dest_clk => clk_2240_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x0,
src_clk => clk_1120_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
d => assert2_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x0,
b(0) => constant1_op_net,
ce => ce_1120_sg_x0,
clk => clk_1120_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/TDDM_fofb_amp_4ch"
entity tddm_fofb_amp_4ch_entity_2cc521a83f is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_fofb_amp_4ch_entity_2cc521a83f;
architecture structural of tddm_fofb_amp_4ch_entity_2cc521a83f is
signal assert2_dout_net_x2: std_logic_vector(23 downto 0);
signal assert2_dout_net_x3: std_logic_vector(23 downto 0);
signal assert3_dout_net_x2: std_logic;
signal assert3_dout_net_x3: std_logic;
signal ce_1120_sg_x2: std_logic;
signal ce_2240_sg_x2: std_logic;
signal clk_1120_sg_x2: std_logic;
signal clk_2240_sg_x2: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
assert2_dout_net_x2 <= amp_in0;
assert2_dout_net_x3 <= amp_in1;
ce_1120_sg_x2 <= ce_1120;
ce_2240_sg_x2 <= ce_2240;
assert3_dout_net_x2 <= ch_in0;
assert3_dout_net_x3 <= ch_in1;
clk_1120_sg_x2 <= clk_1120;
clk_2240_sg_x2 <= clk_2240;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_fofb_amp0_fd74c6ad6e: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x2,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x2,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_amp1_61cbc8ec65: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x2,
ce_2240 => ce_2240_sg_x2,
ch_in => assert3_dout_net_x3,
clk_1120 => clk_1120_sg_x2,
clk_2240 => clk_2240_sg_x2,
din => assert2_dout_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_b60a69fd9b is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_b60a69fd9b;
architecture structural of tddm_tbt_cordic1_entity_b60a69fd9b is
signal assert1_dout_net_x0: std_logic_vector(23 downto 0);
signal assert3_dout_net_x4: std_logic;
signal ce_1120_sg_x4: std_logic;
signal ce_2240_sg_x4: std_logic;
signal clk_1120_sg_x4: std_logic;
signal clk_2240_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1120_sg_x4 <= ce_1120;
ce_2240_sg_x4 <= ce_2240;
assert3_dout_net_x4 <= ch_in;
clk_1120_sg_x4 <= clk_1120;
clk_2240_sg_x4 <= clk_2240;
assert1_dout_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2240_sg_x4,
dest_clk => clk_2240_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x4,
src_clk => clk_1120_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
d => assert1_dout_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => assert3_dout_net_x4,
b(0) => constant1_op_net,
ce => ce_1120_sg_x4,
clk => clk_1120_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC/TDDM_tbt_cordic0"
entity tddm_tbt_cordic0_entity_38de3613fe is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_cordic_ch_in: in std_logic;
fofb_cordic_din: in std_logic_vector(23 downto 0);
fofb_cordic_pin: in std_logic_vector(23 downto 0);
fofb_cordic_data0_out: out std_logic_vector(23 downto 0);
fofb_cordic_data1_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase0_out: out std_logic_vector(23 downto 0);
fofb_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic0_entity_38de3613fe;
architecture structural of tddm_tbt_cordic0_entity_38de3613fe is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x4: std_logic_vector(23 downto 0);
signal assert3_dout_net_x5: std_logic;
signal ce_1120_sg_x5: std_logic;
signal ce_2240_sg_x5: std_logic;
signal clk_1120_sg_x5: std_logic;
signal clk_2240_sg_x5: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x5 <= ce_1120;
ce_2240_sg_x5 <= ce_2240;
clk_1120_sg_x5 <= clk_1120;
clk_2240_sg_x5 <= clk_2240;
assert3_dout_net_x5 <= fofb_cordic_ch_in;
assert2_dout_net_x4 <= fofb_cordic_din;
assert1_dout_net_x1 <= fofb_cordic_pin;
fofb_cordic_data0_out <= down_sample2_q_net_x2;
fofb_cordic_data1_out <= down_sample1_q_net_x2;
fofb_cordic_phase0_out <= down_sample2_q_net_x3;
fofb_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_fofb_cordic0_int_516d0c2a22: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert2_dout_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_cordic1_b60a69fd9b: entity work.tddm_tbt_cordic1_entity_b60a69fd9b
port map (
ce_1120 => ce_1120_sg_x5,
ce_2240 => ce_2240_sg_x5,
ch_in => assert3_dout_net_x5,
clk_1120 => clk_1120_sg_x5,
clk_2240 => clk_2240_sg_x5,
din => assert1_dout_net_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_CORDIC"
entity fofb_cordic_entity_fad57e49ce is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_tbt_cordic0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic0_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_fad57e49ce;
architecture structural of fofb_cordic_entity_fad57e49ce is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x5: std_logic_vector(23 downto 0);
signal assert3_dout_net_x6: std_logic;
signal ce_1120_sg_x6: std_logic;
signal ce_1_sg_x5: std_logic;
signal ce_2240_sg_x6: std_logic;
signal clk_1120_sg_x6: std_logic;
signal clk_1_sg_x5: std_logic;
signal clk_2240_sg_x6: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x5 <= ce_1;
ce_1120_sg_x6 <= ce_1120;
ce_2240_sg_x6 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x5 <= clk_1;
clk_1120_sg_x6 <= clk_1120;
clk_2240_sg_x6 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x5;
ch_out <= assert3_dout_net_x6;
tddm_tbt_cordic0 <= down_sample1_q_net_x4;
tddm_tbt_cordic0_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic0_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic0_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x5
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x6
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x6,
dest_clk => clk_1120_sg_x6,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x5,
src_clk => clk_1_sg_x5,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x5,
clk => clk_1_sg_x5,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic0_38de3613fe: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x6,
ce_2240 => ce_2240_sg_x6,
clk_1120 => clk_1120_sg_x6,
clk_2240 => clk_2240_sg_x6,
fofb_cordic_ch_in => assert3_dout_net_x6,
fofb_cordic_din => assert2_dout_net_x5,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x5,
dest_clk => clk_1_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x6,
src_clk => clk_1120_sg_x6,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/Reg"
entity reg_entity_cf7aa296b2 is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end reg_entity_cf7aa296b2;
architecture structural of reg_entity_cf7aa296b2 is
signal ce_1120_sg_x7: std_logic;
signal clk_1120_sg_x7: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
begin
ce_1120_sg_x7 <= ce_1120;
clk_1120_sg_x7 <= clk_1120;
register_q_net_x2 <= din;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 23,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1120_sg_x7,
clk => clk_1120_sg_x7,
d => convert_dout_net,
en => "1",
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x2,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/TDDM_fofb_cic0"
entity tddm_fofb_cic0_entity_6b909292ff is
port (
ce_1120: in std_logic;
ce_2240: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
fofb_ch_in: in std_logic;
fofb_i_in: in std_logic_vector(23 downto 0);
fofb_q_in: in std_logic_vector(23 downto 0);
cic_fofb_ch0_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch0_q_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_i_out: out std_logic_vector(23 downto 0);
cic_fofb_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_fofb_cic0_entity_6b909292ff;
architecture structural of tddm_fofb_cic0_entity_6b909292ff is
signal ce_1120_sg_x11: std_logic;
signal ce_2240_sg_x9: std_logic;
signal clk_1120_sg_x11: std_logic;
signal clk_2240_sg_x9: std_logic;
signal delay_q_net_x3: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
begin
ce_1120_sg_x11 <= ce_1120;
ce_2240_sg_x9 <= ce_2240;
clk_1120_sg_x11 <= clk_1120;
clk_2240_sg_x9 <= clk_2240;
delay_q_net_x3 <= fofb_ch_in;
register_q_net_x4 <= fofb_i_in;
register_q_net_x3 <= fofb_q_in;
cic_fofb_ch0_i_out <= down_sample2_q_net_x2;
cic_fofb_ch0_q_out <= down_sample2_q_net_x3;
cic_fofb_ch1_i_out <= down_sample1_q_net_x2;
cic_fofb_ch1_q_out <= down_sample1_q_net_x3;
tddm_fofb_cic0_i_06b84397ec: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x4,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_fofb_cic0_q_a6a1d7c301: entity work.tddm_fofb_amp0_entity_fd74c6ad6e
port map (
ce_1120 => ce_1120_sg_x11,
ce_2240 => ce_2240_sg_x9,
ch_in => delay_q_net_x3,
clk_1120 => clk_1120_sg_x11,
clk_2240 => clk_2240_sg_x9,
din => register_q_net_x3,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg"
entity reg_entity_71dd029fba is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0)
);
end reg_entity_71dd029fba;
architecture structural of reg_entity_71dd029fba is
signal ce_1120_sg_x12: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x12: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x12 <= ce_1120;
clk_1120_sg_x12 <= clk_1120;
cic_fofb_q_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_q_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x3;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x12,
clk => clk_1120_sg_x12,
d => convert_dout_net,
en(0) => cic_fofb_q_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x3
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_q_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb/Reg1"
entity reg1_entity_b079f30e3c is
port (
ce_1120: in std_logic;
clk_1120: in std_logic;
din: in std_logic_vector(57 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end reg1_entity_b079f30e3c;
architecture structural of reg1_entity_b079f30e3c is
signal ce_1120_sg_x13: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x13: std_logic;
signal convert_dout_net: std_logic_vector(24 downto 0);
signal register1_q_net_x2: std_logic;
signal register_q_net_x4: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(57 downto 0);
begin
ce_1120_sg_x13 <= ce_1120;
clk_1120_sg_x13 <= clk_1120;
cic_fofb_i_m_axis_data_tdata_data_net_x0 <= din;
cic_fofb_i_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x4;
valid_out <= register1_q_net_x2;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 56,
din_width => 58,
dout_arith => 2,
dout_bin_pt => 23,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x2
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1120_sg_x13,
clk => clk_1120_sg_x13,
d => convert_dout_net,
en(0) => cic_fofb_i_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x4
);
reinterpret2: entity work.reinterpret_fa01b5fd95
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => cic_fofb_i_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp/cic_fofb"
entity cic_fofb_entity_2ed6a6e00c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb_q_x0: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
valid_out: out std_logic
);
end cic_fofb_entity_2ed6a6e00c;
architecture structural of cic_fofb_entity_2ed6a6e00c is
signal ce_1120_sg_x14: std_logic;
signal ce_1_sg_x6: std_logic;
signal ce_logic_1_sg_x5: std_logic;
signal cic_fofb_i_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_i_m_axis_data_tuser_chan_out_net: std_logic;
signal cic_fofb_i_m_axis_data_tvalid_net_x0: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x0: std_logic;
signal cic_fofb_q_m_axis_data_tdata_data_net_x0: std_logic_vector(57 downto 0);
signal cic_fofb_q_m_axis_data_tvalid_net_x0: std_logic;
signal clk_1120_sg_x14: std_logic;
signal clk_1_sg_x6: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay_q_net_x4: std_logic;
signal register1_q_net_x3: std_logic;
signal register3_q_net_x0: std_logic;
signal register4_q_net_x0: std_logic_vector(23 downto 0);
signal register5_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(24 downto 0);
signal register_q_net_x6: std_logic_vector(24 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x6 <= ce_1;
ce_1120_sg_x14 <= ce_1120;
ce_logic_1_sg_x5 <= ce_logic_1;
register3_q_net_x0 <= ch_in;
clk_1_sg_x6 <= clk_1;
clk_1120_sg_x14 <= clk_1120;
register4_q_net_x0 <= i_in;
register5_q_net_x0 <= q_in;
ch_out <= delay_q_net_x4;
cic_fofb_q_x0 <= cic_fofb_q_event_tlast_missing_net_x0;
i_out <= register_q_net_x6;
q_out <= register_q_net_x5;
valid_out <= register1_q_net_x3;
cic_fofb_i: entity work.xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register4_q_net_x0,
s_axis_data_tlast => relational2_op_net,
m_axis_data_tdata_data => cic_fofb_i_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => cic_fofb_i_m_axis_data_tvalid_net_x0
);
cic_fofb_q: entity work.xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266
port map (
ce => ce_1_sg_x6,
ce_1120 => ce_1120_sg_x14,
ce_logic_1 => ce_logic_1_sg_x5,
clk => clk_1_sg_x6,
clk_1120 => clk_1120_sg_x14,
clk_logic_1 => clk_1_sg_x6,
s_axis_data_tdata_data => register5_q_net_x0,
s_axis_data_tlast => relational2_op_net,
event_tlast_missing => cic_fofb_q_event_tlast_missing_net_x0,
m_axis_data_tdata_data => cic_fofb_q_m_axis_data_tdata_data_net_x0,
m_axis_data_tvalid => cic_fofb_q_m_axis_data_tvalid_net_x0
);
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1120_sg_x14,
clk => clk_1120_sg_x14,
d(0) => cic_fofb_i_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q(0) => delay_q_net_x4
);
reg1_b079f30e3c: entity work.reg1_entity_b079f30e3c
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_i_m_axis_data_tdata_data_net_x0,
en => cic_fofb_i_m_axis_data_tvalid_net_x0,
dout => register_q_net_x6,
valid_out => register1_q_net_x3
);
reg_71dd029fba: entity work.reg_entity_71dd029fba
port map (
ce_1120 => ce_1120_sg_x14,
clk_1120 => clk_1120_sg_x14,
din => cic_fofb_q_m_axis_data_tdata_data_net_x0,
en => cic_fofb_q_m_axis_data_tvalid_net_x0,
dout => register_q_net_x5
);
relational2: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x0,
b => constant1_op_net,
ce => ce_1_sg_x6,
clk => clk_1_sg_x6,
clr => '0',
op(0) => relational2_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0/FOFB_amp"
entity fofb_amp_entity_078cdb1842 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic0_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_078cdb1842;
architecture structural of fofb_amp_entity_078cdb1842 is
signal ce_1120_sg_x15: std_logic;
signal ce_1_sg_x7: std_logic;
signal ce_2240_sg_x10: std_logic;
signal ce_logic_1_sg_x6: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x15: std_logic;
signal clk_1_sg_x7: std_logic;
signal clk_2240_sg_x10: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x7 <= ce_1;
ce_1120_sg_x15 <= ce_1120;
ce_2240_sg_x10 <= ce_2240;
ce_logic_1_sg_x6 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x7 <= clk_1;
clk_1120_sg_x15 <= clk_1120;
clk_2240_sg_x10 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic0 <= down_sample1_q_net_x4;
tddm_fofb_cic0_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic0_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic0_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_2ed6a6e00c: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x7,
ce_1120 => ce_1120_sg_x15,
ce_logic_1 => ce_logic_1_sg_x6,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x7,
clk_1120 => clk_1120_sg_x15,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_6375e37e24: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_cf7aa296b2: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x15,
clk_1120 => clk_1120_sg_x15,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic0_6b909292ff: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x15,
ce_2240 => ce_2240_sg_x10,
clk_1120 => clk_1120_sg_x15,
clk_2240 => clk_2240_sg_x10,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp0"
entity fofb_amp0_entity_95b23bfc2c is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp0_entity_95b23bfc2c;
architecture structural of fofb_amp0_entity_95b23bfc2c is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x16: std_logic;
signal ce_1_sg_x8: std_logic;
signal ce_2240_sg_x11: std_logic;
signal ce_logic_1_sg_x7: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x16: std_logic;
signal clk_1_sg_x8: std_logic;
signal clk_2240_sg_x11: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x8 <= ce_1;
ce_1120_sg_x16 <= ce_1120;
ce_2240_sg_x11 <= ce_2240;
ce_logic_1_sg_x7 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x8 <= clk_1;
clk_1120_sg_x16 <= clk_1120;
clk_2240_sg_x11 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_078cdb1842: entity work.fofb_amp_entity_078cdb1842
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ce_logic_1 => ce_logic_1_sg_x7,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic0 => down_sample1_q_net_x10,
tddm_fofb_cic0_x0 => down_sample2_q_net_x10,
tddm_fofb_cic0_x1 => down_sample1_q_net_x11,
tddm_fofb_cic0_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_fad57e49ce: entity work.fofb_cordic_entity_fad57e49ce
port map (
ce_1 => ce_1_sg_x8,
ce_1120 => ce_1120_sg_x16,
ce_2240 => ce_2240_sg_x11,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x8,
clk_1120 => clk_1120_sg_x16,
clk_2240 => clk_2240_sg_x11,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
tddm_tbt_cordic0 => down_sample1_q_net_x8,
tddm_tbt_cordic0_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic0_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic0_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_CORDIC"
entity fofb_cordic_entity_e4c0810ec7 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tddm_fofb_cordic1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cordic1_x2: out std_logic_vector(23 downto 0)
);
end fofb_cordic_entity_e4c0810ec7;
architecture structural of fofb_cordic_entity_e4c0810ec7 is
signal assert1_dout_net_x1: std_logic_vector(23 downto 0);
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal ce_1120_sg_x20: std_logic;
signal ce_1_sg_x9: std_logic;
signal ce_2240_sg_x15: std_logic;
signal clk_1120_sg_x20: std_logic;
signal clk_1_sg_x9: std_logic;
signal clk_2240_sg_x15: std_logic;
signal delay_q_net_x0: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal rect2pol_m_axis_dout_tdata_phase_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal rect2pol_m_axis_dout_tuser_cartesian_tuser_net: std_logic;
signal rect2pol_m_axis_dout_tvalid_net: std_logic;
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic;
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal up_sample1_q_net: std_logic_vector(24 downto 0);
signal up_sample2_q_net: std_logic_vector(24 downto 0);
signal up_sample3_q_net: std_logic;
signal up_sample_q_net: std_logic;
begin
ce_1_sg_x9 <= ce_1;
ce_1120_sg_x20 <= ce_1120;
ce_2240_sg_x15 <= ce_2240;
delay_q_net_x0 <= ch_in;
clk_1_sg_x9 <= clk_1;
clk_1120_sg_x20 <= clk_1120;
clk_2240_sg_x15 <= clk_2240;
register_q_net_x2 <= i_in;
register_q_net_x1 <= q_in;
register1_q_net_x1 <= valid_in;
amp_out <= assert2_dout_net_x6;
ch_out <= assert3_dout_net_x7;
tddm_fofb_cordic1 <= down_sample1_q_net_x4;
tddm_fofb_cordic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cordic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cordic1_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => assert1_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => assert2_dout_net_x6
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert3_dout_net_x7
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_1120_sg_x20,
dest_clk => clk_1120_sg_x20,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x9,
src_clk => clk_1_sg_x9,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
s_axis_cartesian_tdata_imag => up_sample1_q_net,
s_axis_cartesian_tdata_real => up_sample2_q_net,
s_axis_cartesian_tuser_user(0) => up_sample3_q_net,
s_axis_cartesian_tvalid => up_sample_q_net,
m_axis_dout_tdata_phase => rect2pol_m_axis_dout_tdata_phase_net,
m_axis_dout_tdata_real => rect2pol_m_axis_dout_tdata_real_net,
m_axis_dout_tuser_cartesian_tuser(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
m_axis_dout_tvalid => rect2pol_m_axis_dout_tvalid_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d(0) => rect2pol_m_axis_dout_tuser_cartesian_tuser_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret2_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x9,
clk => clk_1_sg_x9,
d => reinterpret3_output_port_net,
en(0) => rect2pol_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_phase_net,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => rect2pol_m_axis_dout_tdata_real_net,
output_port => reinterpret3_output_port_net
);
tddm_fofb_cordic1_77b64089dc: entity work.tddm_tbt_cordic0_entity_38de3613fe
port map (
ce_1120 => ce_1120_sg_x20,
ce_2240 => ce_2240_sg_x15,
clk_1120 => clk_1120_sg_x20,
clk_2240 => clk_2240_sg_x15,
fofb_cordic_ch_in => assert3_dout_net_x7,
fofb_cordic_din => assert2_dout_net_x6,
fofb_cordic_pin => assert1_dout_net_x1,
fofb_cordic_data0_out => down_sample2_q_net_x4,
fofb_cordic_data1_out => down_sample1_q_net_x4,
fofb_cordic_phase0_out => down_sample2_q_net_x5,
fofb_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x1,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample1_q_net
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register_q_net_x2,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => delay_q_net_x0,
dest_ce => ce_1_sg_x9,
dest_clk => clk_1_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_1120_sg_x20,
src_clk => clk_1120_sg_x20,
src_clr => '0',
q(0) => up_sample3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1/FOFB_amp"
entity fofb_amp_entity_f70fcc8ed9 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
cic_fofb: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tddm_fofb_cic1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x0: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x1: out std_logic_vector(23 downto 0);
tddm_fofb_cic1_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end fofb_amp_entity_f70fcc8ed9;
architecture structural of fofb_amp_entity_f70fcc8ed9 is
signal ce_1120_sg_x29: std_logic;
signal ce_1_sg_x11: std_logic;
signal ce_2240_sg_x19: std_logic;
signal ce_logic_1_sg_x9: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x1: std_logic;
signal clk_1120_sg_x29: std_logic;
signal clk_1_sg_x11: std_logic;
signal clk_2240_sg_x19: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x1: std_logic;
signal register4_q_net_x1: std_logic_vector(23 downto 0);
signal register5_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal register_q_net_x4: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x11 <= ce_1;
ce_1120_sg_x29 <= ce_1120;
ce_2240_sg_x19 <= ce_2240;
ce_logic_1_sg_x9 <= ce_logic_1;
register3_q_net_x1 <= ch_in;
clk_1_sg_x11 <= clk_1;
clk_1120_sg_x29 <= clk_1120;
clk_2240_sg_x19 <= clk_2240;
register4_q_net_x1 <= i_in;
register5_q_net_x1 <= q_in;
ch_out <= delay_q_net_x5;
cic_fofb <= cic_fofb_q_event_tlast_missing_net_x1;
i_out <= register_q_net_x8;
q_out <= register_q_net_x7;
tddm_fofb_cic1 <= down_sample1_q_net_x4;
tddm_fofb_cic1_x0 <= down_sample2_q_net_x4;
tddm_fofb_cic1_x1 <= down_sample1_q_net_x5;
tddm_fofb_cic1_x2 <= down_sample2_q_net_x5;
valid_out <= register1_q_net_x4;
cic_fofb_579902476d: entity work.cic_fofb_entity_2ed6a6e00c
port map (
ce_1 => ce_1_sg_x11,
ce_1120 => ce_1120_sg_x29,
ce_logic_1 => ce_logic_1_sg_x9,
ch_in => register3_q_net_x1,
clk_1 => clk_1_sg_x11,
clk_1120 => clk_1120_sg_x29,
i_in => register4_q_net_x1,
q_in => register5_q_net_x1,
ch_out => delay_q_net_x5,
cic_fofb_q_x0 => cic_fofb_q_event_tlast_missing_net_x1,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
valid_out => register1_q_net_x4
);
reg1_a06a1c33b5: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x8,
dout => register_q_net_x4
);
reg_b669a3b118: entity work.reg_entity_cf7aa296b2
port map (
ce_1120 => ce_1120_sg_x29,
clk_1120 => clk_1120_sg_x29,
din => register_q_net_x7,
dout => register_q_net_x3
);
tddm_fofb_cic1_4a640315a5: entity work.tddm_fofb_cic0_entity_6b909292ff
port map (
ce_1120 => ce_1120_sg_x29,
ce_2240 => ce_2240_sg_x19,
clk_1120 => clk_1120_sg_x29,
clk_2240 => clk_2240_sg_x19,
fofb_ch_in => delay_q_net_x5,
fofb_i_in => register_q_net_x4,
fofb_q_in => register_q_net_x3,
cic_fofb_ch0_i_out => down_sample2_q_net_x4,
cic_fofb_ch0_q_out => down_sample2_q_net_x5,
cic_fofb_ch1_i_out => down_sample1_q_net_x4,
cic_fofb_ch1_q_out => down_sample1_q_net_x5
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp/fofb_amp1"
entity fofb_amp1_entity_a049562dde is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
fofb_amp: out std_logic_vector(23 downto 0);
fofb_amp_x0: out std_logic_vector(23 downto 0);
fofb_amp_x1: out std_logic_vector(23 downto 0);
fofb_amp_x2: out std_logic_vector(23 downto 0);
fofb_amp_x3: out std_logic;
fofb_cordic: out std_logic_vector(23 downto 0);
fofb_cordic_x0: out std_logic_vector(23 downto 0);
fofb_cordic_x1: out std_logic_vector(23 downto 0);
fofb_cordic_x2: out std_logic_vector(23 downto 0)
);
end fofb_amp1_entity_a049562dde;
architecture structural of fofb_amp1_entity_a049562dde is
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x30: std_logic;
signal ce_1_sg_x12: std_logic;
signal ce_2240_sg_x20: std_logic;
signal ce_logic_1_sg_x10: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x2: std_logic;
signal clk_1120_sg_x30: std_logic;
signal clk_1_sg_x12: std_logic;
signal clk_2240_sg_x20: std_logic;
signal delay_q_net_x5: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register3_q_net_x2: std_logic;
signal register4_q_net_x2: std_logic_vector(23 downto 0);
signal register5_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(24 downto 0);
signal register_q_net_x8: std_logic_vector(24 downto 0);
begin
ce_1_sg_x12 <= ce_1;
ce_1120_sg_x30 <= ce_1120;
ce_2240_sg_x20 <= ce_2240;
ce_logic_1_sg_x10 <= ce_logic_1;
register3_q_net_x2 <= ch_in;
clk_1_sg_x12 <= clk_1;
clk_1120_sg_x30 <= clk_1120;
clk_2240_sg_x20 <= clk_2240;
register4_q_net_x2 <= i_in;
register5_q_net_x2 <= q_in;
amp_out <= assert2_dout_net_x7;
ch_out <= assert3_dout_net_x8;
fofb_amp <= down_sample1_q_net_x10;
fofb_amp_x0 <= down_sample2_q_net_x10;
fofb_amp_x1 <= down_sample1_q_net_x11;
fofb_amp_x2 <= down_sample2_q_net_x11;
fofb_amp_x3 <= cic_fofb_q_event_tlast_missing_net_x2;
fofb_cordic <= down_sample1_q_net_x8;
fofb_cordic_x0 <= down_sample2_q_net_x8;
fofb_cordic_x1 <= down_sample1_q_net_x9;
fofb_cordic_x2 <= down_sample2_q_net_x9;
fofb_amp_f70fcc8ed9: entity work.fofb_amp_entity_f70fcc8ed9
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ce_logic_1 => ce_logic_1_sg_x10,
ch_in => register3_q_net_x2,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register4_q_net_x2,
q_in => register5_q_net_x2,
ch_out => delay_q_net_x5,
cic_fofb => cic_fofb_q_event_tlast_missing_net_x2,
i_out => register_q_net_x8,
q_out => register_q_net_x7,
tddm_fofb_cic1 => down_sample1_q_net_x10,
tddm_fofb_cic1_x0 => down_sample2_q_net_x10,
tddm_fofb_cic1_x1 => down_sample1_q_net_x11,
tddm_fofb_cic1_x2 => down_sample2_q_net_x11,
valid_out => register1_q_net_x4
);
fofb_cordic_e4c0810ec7: entity work.fofb_cordic_entity_e4c0810ec7
port map (
ce_1 => ce_1_sg_x12,
ce_1120 => ce_1120_sg_x30,
ce_2240 => ce_2240_sg_x20,
ch_in => delay_q_net_x5,
clk_1 => clk_1_sg_x12,
clk_1120 => clk_1120_sg_x30,
clk_2240 => clk_2240_sg_x20,
i_in => register_q_net_x8,
q_in => register_q_net_x7,
valid_in => register1_q_net_x4,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
tddm_fofb_cordic1 => down_sample1_q_net_x8,
tddm_fofb_cordic1_x0 => down_sample2_q_net_x8,
tddm_fofb_cordic1_x1 => down_sample1_q_net_x9,
tddm_fofb_cordic1_x2 => down_sample2_q_net_x9
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/FOFB_amp"
entity fofb_amp_entity_8b25d4b0b6 is
port (
ce_1: in std_logic;
ce_1120: in std_logic;
ce_2240: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_1120: in std_logic;
clk_2240: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
fofb_amp0: out std_logic_vector(23 downto 0);
fofb_amp0_x0: out std_logic_vector(23 downto 0);
fofb_amp0_x1: out std_logic_vector(23 downto 0);
fofb_amp0_x2: out std_logic_vector(23 downto 0);
fofb_amp0_x3: out std_logic_vector(23 downto 0);
fofb_amp0_x4: out std_logic_vector(23 downto 0);
fofb_amp0_x5: out std_logic_vector(23 downto 0);
fofb_amp0_x6: out std_logic_vector(23 downto 0);
fofb_amp0_x7: out std_logic;
fofb_amp1: out std_logic_vector(23 downto 0);
fofb_amp1_x0: out std_logic_vector(23 downto 0);
fofb_amp1_x1: out std_logic_vector(23 downto 0);
fofb_amp1_x2: out std_logic_vector(23 downto 0);
fofb_amp1_x3: out std_logic_vector(23 downto 0);
fofb_amp1_x4: out std_logic_vector(23 downto 0);
fofb_amp1_x5: out std_logic_vector(23 downto 0);
fofb_amp1_x6: out std_logic_vector(23 downto 0);
fofb_amp1_x7: out std_logic
);
end fofb_amp_entity_8b25d4b0b6;
architecture structural of fofb_amp_entity_8b25d4b0b6 is
signal assert2_dout_net_x6: std_logic_vector(23 downto 0);
signal assert2_dout_net_x7: std_logic_vector(23 downto 0);
signal assert3_dout_net_x7: std_logic;
signal assert3_dout_net_x8: std_logic;
signal ce_1120_sg_x31: std_logic;
signal ce_1_sg_x13: std_logic;
signal ce_2240_sg_x21: std_logic;
signal ce_logic_1_sg_x11: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x4: std_logic;
signal cic_fofb_q_event_tlast_missing_net_x5: std_logic;
signal clk_1120_sg_x31: std_logic;
signal clk_1_sg_x13: std_logic;
signal clk_2240_sg_x21: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal register3_q_net_x4: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x4: std_logic_vector(23 downto 0);
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x4: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x13 <= ce_1;
ce_1120_sg_x31 <= ce_1120;
ce_2240_sg_x21 <= ce_2240;
ce_logic_1_sg_x11 <= ce_logic_1;
register3_q_net_x4 <= ch_in0;
register3_q_net_x5 <= ch_in1;
clk_1_sg_x13 <= clk_1;
clk_1120_sg_x31 <= clk_1120;
clk_2240_sg_x21 <= clk_2240;
register4_q_net_x4 <= i_in0;
register4_q_net_x5 <= i_in1;
register5_q_net_x4 <= q_in0;
register5_q_net_x5 <= q_in1;
amp_out0 <= down_sample2_q_net_x16;
amp_out1 <= down_sample1_q_net_x16;
amp_out2 <= down_sample2_q_net_x17;
amp_out3 <= down_sample1_q_net_x17;
fofb_amp0 <= down_sample1_q_net_x18;
fofb_amp0_x0 <= down_sample2_q_net_x18;
fofb_amp0_x1 <= down_sample1_q_net_x19;
fofb_amp0_x2 <= down_sample2_q_net_x19;
fofb_amp0_x3 <= down_sample1_q_net_x20;
fofb_amp0_x4 <= down_sample2_q_net_x20;
fofb_amp0_x5 <= down_sample1_q_net_x21;
fofb_amp0_x6 <= down_sample2_q_net_x21;
fofb_amp0_x7 <= cic_fofb_q_event_tlast_missing_net_x4;
fofb_amp1 <= down_sample1_q_net_x22;
fofb_amp1_x0 <= down_sample2_q_net_x22;
fofb_amp1_x1 <= down_sample1_q_net_x23;
fofb_amp1_x2 <= down_sample2_q_net_x23;
fofb_amp1_x3 <= down_sample1_q_net_x24;
fofb_amp1_x4 <= down_sample2_q_net_x24;
fofb_amp1_x5 <= down_sample1_q_net_x25;
fofb_amp1_x6 <= down_sample2_q_net_x25;
fofb_amp1_x7 <= cic_fofb_q_event_tlast_missing_net_x5;
fofb_amp0_95b23bfc2c: entity work.fofb_amp0_entity_95b23bfc2c
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x4,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x4,
q_in => register5_q_net_x4,
amp_out => assert2_dout_net_x6,
ch_out => assert3_dout_net_x7,
fofb_amp => down_sample1_q_net_x20,
fofb_amp_x0 => down_sample2_q_net_x20,
fofb_amp_x1 => down_sample1_q_net_x21,
fofb_amp_x2 => down_sample2_q_net_x21,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x4,
fofb_cordic => down_sample1_q_net_x18,
fofb_cordic_x0 => down_sample2_q_net_x18,
fofb_cordic_x1 => down_sample1_q_net_x19,
fofb_cordic_x2 => down_sample2_q_net_x19
);
fofb_amp1_a049562dde: entity work.fofb_amp1_entity_a049562dde
port map (
ce_1 => ce_1_sg_x13,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ce_logic_1 => ce_logic_1_sg_x11,
ch_in => register3_q_net_x5,
clk_1 => clk_1_sg_x13,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
i_in => register4_q_net_x5,
q_in => register5_q_net_x5,
amp_out => assert2_dout_net_x7,
ch_out => assert3_dout_net_x8,
fofb_amp => down_sample1_q_net_x24,
fofb_amp_x0 => down_sample2_q_net_x24,
fofb_amp_x1 => down_sample1_q_net_x25,
fofb_amp_x2 => down_sample2_q_net_x25,
fofb_amp_x3 => cic_fofb_q_event_tlast_missing_net_x5,
fofb_cordic => down_sample1_q_net_x22,
fofb_cordic_x0 => down_sample2_q_net_x22,
fofb_cordic_x1 => down_sample1_q_net_x23,
fofb_cordic_x2 => down_sample2_q_net_x23
);
tddm_fofb_amp_4ch_2cc521a83f: entity work.tddm_fofb_amp_4ch_entity_2cc521a83f
port map (
amp_in0 => assert2_dout_net_x6,
amp_in1 => assert2_dout_net_x7,
ce_1120 => ce_1120_sg_x31,
ce_2240 => ce_2240_sg_x21,
ch_in0 => assert3_dout_net_x7,
ch_in1 => assert3_dout_net_x8,
clk_1120 => clk_1120_sg_x31,
clk_2240 => clk_2240_sg_x21,
amp_out0 => down_sample2_q_net_x16,
amp_out1 => down_sample1_q_net_x16,
amp_out2 => down_sample2_q_net_x17,
amp_out3 => down_sample1_q_net_x17
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3/Cast_truncate1"
entity cast_truncate1_entity_56731b7870 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_56731b7870;
architecture structural of cast_truncate1_entity_56731b7870 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_fofb_mult3"
entity k_fofb_mult3_entity_697accc8e2 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_fofb_mult3_entity_697accc8e2;
architecture structural of k_fofb_mult3_entity_697accc8e2 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2240_sg_x22: std_logic;
signal ce_2_sg_x5: std_logic;
signal clk_2240_sg_x22: std_logic;
signal clk_2_sg_x5: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x5 <= ce_2;
ce_2240_sg_x22 <= ce_2240;
clk_2_sg_x5 <= clk_2;
clk_2240_sg_x22 <= clk_2240;
assert5_dout_net_x0 <= in1;
kx_i_net_x0 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_56731b7870: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x22,
clk => clk_2240_sg_x22,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x0,
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
clr => '0',
core_ce => ce_2_sg_x5,
core_clk => clk_2_sg_x5,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x5,
clk => clk_2_sg_x5,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_1_mult"
entity k_monit_1_mult_entity_016885a3ac is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_1_mult_entity_016885a3ac;
architecture structural of k_monit_1_mult_entity_016885a3ac is
signal ce_224000000_sg_x0: std_logic;
signal ce_2_sg_x8: std_logic;
signal clk_224000000_sg_x0: std_logic;
signal clk_2_sg_x8: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool_dout_net_x0: std_logic;
begin
ce_2_sg_x8 <= ce_2;
ce_224000000_sg_x0 <= ce_224000000;
clk_2_sg_x8 <= clk_2;
clk_224000000_sg_x0 <= clk_224000000;
reinterpret3_output_port_net_x0 <= in1;
kx_i_net_x2 <= in2;
ufix_to_bool_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_fe5c8d5ea5: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x0,
clk => clk_224000000_sg_x0,
d(0) => ufix_to_bool_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret3_output_port_net_x0,
b => kx_i_net_x2,
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
clr => '0',
core_ce => ce_2_sg_x8,
core_clk => clk_2_sg_x8,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x8,
clk => clk_2_sg_x8,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_monit_mult3"
entity k_monit_mult3_entity_8a778fb5f4 is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_monit_mult3_entity_8a778fb5f4;
architecture structural of k_monit_mult3_entity_8a778fb5f4 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_22400000_sg_x0: std_logic;
signal ce_2_sg_x11: std_logic;
signal clk_22400000_sg_x0: std_logic;
signal clk_2_sg_x11: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x4: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x11 <= ce_2;
ce_22400000_sg_x0 <= ce_22400000;
clk_2_sg_x11 <= clk_2;
clk_22400000_sg_x0 <= clk_22400000;
assert11_dout_net_x0 <= in1;
kx_i_net_x4 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_47fd83104e: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x0,
clk => clk_22400000_sg_x0,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => kx_i_net_x4,
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
clr => '0',
core_ce => ce_2_sg_x11,
core_clk => clk_2_sg_x11,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x11,
clk => clk_2_sg_x11,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/K_tbt_mult"
entity k_tbt_mult_entity_b8fafff255 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end k_tbt_mult_entity_b8fafff255;
architecture structural of k_tbt_mult_entity_b8fafff255 is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_2_sg_x14: std_logic;
signal ce_70_sg_x0: std_logic;
signal clk_2_sg_x14: std_logic;
signal clk_70_sg_x0: std_logic;
signal delay1_q_net_x0: std_logic;
signal kx_i_net_x6: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x14 <= ce_2;
ce_70_sg_x0 <= ce_70;
clk_2_sg_x14 <= clk_2;
clk_70_sg_x0 <= clk_70;
assert5_dout_net_x0 <= in1;
kx_i_net_x6 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4592ea30ee: entity work.cast_truncate1_entity_56731b7870
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x0,
clk => clk_70_sg_x0,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 24,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 0,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 24,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => kx_i_net_x6,
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
clr => '0',
core_ce => ce_2_sg_x14,
core_clk => clk_2_sg_x14,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x14,
clk => clk_2_sg_x14,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4/Cast_truncate1"
entity cast_truncate1_entity_18a9b21a64 is
port (
in1: in std_logic_vector(49 downto 0);
out1: out std_logic_vector(25 downto 0)
);
end cast_truncate1_entity_18a9b21a64;
architecture structural of cast_truncate1_entity_18a9b21a64 is
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal slice_y_net: std_logic_vector(25 downto 0);
begin
kx_tbt_p_net_x0 <= in1;
out1 <= reinterpret_output_port_net_x0;
reinterpret: entity work.reinterpret_9934b94a22
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x0
);
slice: entity work.xlslice
generic map (
new_lsb => 24,
new_msb => 49,
x_width => 50,
y_width => 26
)
port map (
x => kx_tbt_p_net_x0,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_fofb_mult4"
entity ksum_fofb_mult4_entity_ac3ed97096 is
port (
ce_2: in std_logic;
ce_2240: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_fofb_mult4_entity_ac3ed97096;
architecture structural of ksum_fofb_mult4_entity_ac3ed97096 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2240_sg_x25: std_logic;
signal ce_2_sg_x17: std_logic;
signal clk_2240_sg_x25: std_logic;
signal clk_2_sg_x17: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x0: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x17 <= ce_2;
ce_2240_sg_x25 <= ce_2240;
clk_2_sg_x17 <= clk_2;
clk_2240_sg_x25 <= clk_2240;
assert11_dout_net_x0 <= in1;
ksum_i_net_x0 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_18a9b21a64: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_2240_sg_x25,
clk => clk_2240_sg_x25,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x0,
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
clr => '0',
core_ce => ce_2_sg_x17,
core_clk => clk_2_sg_x17,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x17,
clk => clk_2_sg_x17,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_1_mult1"
entity ksum_monit_1_mult1_entity_c66dc07078 is
port (
ce_2: in std_logic;
ce_224000000: in std_logic;
clk_2: in std_logic;
clk_224000000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_1_mult1_entity_c66dc07078;
architecture structural of ksum_monit_1_mult1_entity_c66dc07078 is
signal ce_224000000_sg_x3: std_logic;
signal ce_2_sg_x18: std_logic;
signal clk_224000000_sg_x3: std_logic;
signal clk_2_sg_x18: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x1: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret4_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
signal ufix_to_bool3_dout_net_x0: std_logic;
begin
ce_2_sg_x18 <= ce_2;
ce_224000000_sg_x3 <= ce_224000000;
clk_2_sg_x18 <= clk_2;
clk_224000000_sg_x3 <= clk_224000000;
reinterpret4_output_port_net_x0 <= in1;
ksum_i_net_x1 <= in2;
ufix_to_bool3_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_92cc22397d: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_224000000_sg_x3,
clk => clk_224000000_sg_x3,
d(0) => ufix_to_bool3_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => reinterpret4_output_port_net_x0,
b => ksum_i_net_x1,
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
clr => '0',
core_ce => ce_2_sg_x18,
core_clk => clk_2_sg_x18,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x18,
clk => clk_2_sg_x18,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_monit_mult2"
entity ksum_monit_mult2_entity_31877b6d2b is
port (
ce_2: in std_logic;
ce_22400000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_monit_mult2_entity_31877b6d2b;
architecture structural of ksum_monit_mult2_entity_31877b6d2b is
signal assert10_dout_net_x0: std_logic;
signal assert5_dout_net_x0: std_logic_vector(24 downto 0);
signal ce_22400000_sg_x3: std_logic;
signal ce_2_sg_x19: std_logic;
signal clk_22400000_sg_x3: std_logic;
signal clk_2_sg_x19: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x2: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x19 <= ce_2;
ce_22400000_sg_x3 <= ce_22400000;
clk_2_sg_x19 <= clk_2;
clk_22400000_sg_x3 <= clk_22400000;
assert5_dout_net_x0 <= in1;
ksum_i_net_x2 <= in2;
assert10_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_4c5b033963: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_22400000_sg_x3,
clk => clk_22400000_sg_x3,
d(0) => assert10_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert5_dout_net_x0,
b => ksum_i_net_x2,
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
clr => '0',
core_ce => ce_2_sg_x19,
core_clk => clk_2_sg_x19,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x19,
clk => clk_2_sg_x19,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Ksum_tbt_mult3"
entity ksum_tbt_mult3_entity_e0be30d675 is
port (
ce_2: in std_logic;
ce_70: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
in1: in std_logic_vector(24 downto 0);
in2: in std_logic_vector(24 downto 0);
vld_in: in std_logic;
out1: out std_logic_vector(25 downto 0);
vld_out: out std_logic
);
end ksum_tbt_mult3_entity_e0be30d675;
architecture structural of ksum_tbt_mult3_entity_e0be30d675 is
signal assert11_dout_net_x0: std_logic_vector(24 downto 0);
signal assert12_dout_net_x0: std_logic;
signal ce_2_sg_x20: std_logic;
signal ce_70_sg_x3: std_logic;
signal clk_2_sg_x20: std_logic;
signal clk_70_sg_x3: std_logic;
signal delay1_q_net_x0: std_logic;
signal ksum_i_net_x3: std_logic_vector(24 downto 0);
signal kx_tbt_p_net_x0: std_logic_vector(49 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(25 downto 0);
begin
ce_2_sg_x20 <= ce_2;
ce_70_sg_x3 <= ce_70;
clk_2_sg_x20 <= clk_2;
clk_70_sg_x3 <= clk_70;
assert11_dout_net_x0 <= in1;
ksum_i_net_x3 <= in2;
assert12_dout_net_x0 <= vld_in;
out1 <= register_q_net_x0;
vld_out <= delay1_q_net_x0;
cast_truncate1_91bc0d396f: entity work.cast_truncate1_entity_18a9b21a64
port map (
in1 => kx_tbt_p_net_x0,
out1 => reinterpret_output_port_net_x0
);
delay1: entity work.xldelay
generic map (
latency => 9,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_70_sg_x3,
clk => clk_70_sg_x3,
d(0) => assert12_dout_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
kx_tbt: entity work.xlmult
generic map (
a_arith => xlSigned,
a_bin_pt => 21,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 23,
b_width => 25,
c_a_type => 0,
c_a_width => 25,
c_b_type => 0,
c_b_width => 25,
c_baat => 25,
c_output_width => 50,
c_type => 0,
core_name0 => "mult_11_2_eb6becd4c4c6b065",
extra_registers => 0,
multsign => 2,
overflow => 1,
p_arith => xlSigned,
p_bin_pt => 44,
p_width => 50,
quantization => 1
)
port map (
a => assert11_dout_net_x0,
b => ksum_i_net_x3,
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
clr => '0',
core_ce => ce_2_sg_x20,
core_clk => clk_2_sg_x20,
core_clr => '1',
en => "1",
rst => "0",
p => kx_tbt_p_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x20,
clk => clk_2_sg_x20,
d => reinterpret_output_port_net_x0,
en => "1",
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En"
entity datareg_en_entity_5c82ef2965 is
port (
ce_2: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0);
valid: out std_logic
);
end datareg_en_entity_5c82ef2965;
architecture structural of datareg_en_entity_5c82ef2965 is
signal ce_2_sg_x21: std_logic;
signal clk_2_sg_x21: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant12_op_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2_sg_x21 <= ce_2;
clk_2_sg_x21 <= clk_2;
constant12_op_net_x0 <= din;
constant11_op_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d(0) => constant11_op_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2_sg_x21,
clk => clk_2_sg_x21,
d => constant12_op_net_x0,
en(0) => constant11_op_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0/DataReg_En1"
entity datareg_en1_entity_8d533fde9e is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(23 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end datareg_en1_entity_8d533fde9e;
architecture structural of datareg_en1_entity_8d533fde9e is
signal ce_1_sg_x14: std_logic;
signal clk_1_sg_x14: std_logic;
signal constant11_op_net_x1: std_logic;
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_1_sg_x14 <= ce_1;
clk_1_sg_x14 <= clk_1;
register_q_net_x1 <= din;
constant11_op_net_x1 <= en;
dout <= register_q_net_x2;
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x14,
clk => clk_1_sg_x14,
d => register_q_net_x1,
en(0) => constant11_op_net_x1,
rst => "0",
q => register_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/CMixer_0"
entity cmixer_0_entity_f630e8d7ec is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine: in std_logic_vector(23 downto 0);
dds_msine: in std_logic_vector(23 downto 0);
dds_valid: in std_logic;
din_i: in std_logic_vector(23 downto 0);
din_q: in std_logic_vector(23 downto 0);
en: in std_logic;
ch_out: out std_logic;
i_out: out std_logic_vector(23 downto 0);
q_out: out std_logic_vector(23 downto 0)
);
end cmixer_0_entity_f630e8d7ec;
architecture structural of cmixer_0_entity_f630e8d7ec is
signal a_i: std_logic_vector(23 downto 0);
signal a_r: std_logic_vector(23 downto 0);
signal b_i: std_logic_vector(23 downto 0);
signal b_r: std_logic_vector(23 downto 0);
signal ce_1_sg_x15: std_logic;
signal ce_2_sg_x22: std_logic;
signal clk_1_sg_x15: std_logic;
signal clk_2_sg_x22: std_logic;
signal complexmult_m_axis_dout_tdata_imag_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tdata_real_net: std_logic_vector(23 downto 0);
signal complexmult_m_axis_dout_tuser_net: std_logic;
signal complexmult_m_axis_dout_tvalid_net: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x0: std_logic;
signal convert1_dout_net: std_logic_vector(23 downto 0);
signal convert2_dout_net: std_logic_vector(23 downto 0);
signal register1_q_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register3_q_net_x5: std_logic;
signal register4_q_net_x5: std_logic_vector(23 downto 0);
signal register5_q_net_x5: std_logic_vector(23 downto 0);
signal register_q_net: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
signal register_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net_x7: std_logic_vector(23 downto 0);
signal register_q_net_x8: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x15 <= ce_1;
ce_2_sg_x22 <= ce_2;
register1_q_net_x1 <= ch_in;
clk_1_sg_x15 <= clk_1;
clk_2_sg_x22 <= clk_2;
register_q_net_x6 <= dds_cosine;
register_q_net_x7 <= dds_msine;
constant15_op_net_x0 <= dds_valid;
register_q_net_x8 <= din_i;
constant12_op_net_x1 <= din_q;
constant11_op_net_x2 <= en;
ch_out <= register3_q_net_x5;
i_out <= register4_q_net_x5;
q_out <= register5_q_net_x5;
complexmult: entity work.xlcomplex_multiplier_9420c9297365b1438cc1e8469b8205e1
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
s_axis_a_tdata_imag => a_i,
s_axis_a_tdata_real => a_r,
s_axis_a_tvalid => constant15_op_net_x0,
s_axis_b_tdata_imag => b_i,
s_axis_b_tdata_real => b_r,
s_axis_b_tuser(0) => register_q_net,
s_axis_b_tvalid => register1_q_net_x0,
m_axis_dout_tdata_imag => complexmult_m_axis_dout_tdata_imag_net,
m_axis_dout_tdata_real => complexmult_m_axis_dout_tdata_real_net,
m_axis_dout_tuser(0) => complexmult_m_axis_dout_tuser_net,
m_axis_dout_tvalid => complexmult_m_axis_dout_tvalid_net
);
convert1: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret1_output_port_net,
en => "1",
dout => convert1_dout_net
);
convert2: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 19,
din_width => 24,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlTruncate
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert2_dout_net
);
datareg_en1_8d533fde9e: entity work.datareg_en1_entity_8d533fde9e
port map (
ce_1 => ce_1_sg_x15,
clk_1 => clk_1_sg_x15,
din => register_q_net_x8,
en => constant11_op_net_x2,
dout => register_q_net_x2
);
datareg_en_5c82ef2965: entity work.datareg_en_entity_5c82ef2965
port map (
ce_2 => ce_2_sg_x22,
clk_2 => clk_2_sg_x22,
din => constant12_op_net_x1,
en => constant11_op_net_x2,
dout => register_q_net_x0,
valid => register1_q_net_x0
);
delay: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x0,
q => b_i
);
delay1: entity work.delay_961b43f67a
port map (
ce => '0',
clk => '0',
clr => '0',
d => register_q_net_x2,
q => b_r
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x6,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_r
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => register_q_net_x7,
en(0) => constant15_op_net_x0,
rst => "0",
q => a_i
);
register3: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => complexmult_m_axis_dout_tuser_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q(0) => register3_q_net_x5
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert1_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register4_q_net_x5
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d => convert2_dout_net,
en(0) => complexmult_m_axis_dout_tvalid_net,
rst => "0",
q => register5_q_net_x5
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x15,
clk => clk_1_sg_x15,
d(0) => register1_q_net_x1,
en(0) => constant11_op_net_x2,
rst => "0",
q(0) => register_q_net
);
reinterpret: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_imag_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => complexmult_m_axis_dout_tdata_real_net,
output_port => reinterpret1_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer/TDDM_Mixer0_i"
entity tddm_mixer0_i_entity_f95b8f24ad is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_mixer0_i_entity_f95b8f24ad;
architecture structural of tddm_mixer0_i_entity_f95b8f24ad is
signal ce_1_sg_x18: std_logic;
signal ce_2_sg_x25: std_logic;
signal clk_1_sg_x18: std_logic;
signal clk_2_sg_x25: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register3_q_net_x6: std_logic;
signal register4_q_net_x6: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_1_sg_x18 <= ce_1;
ce_2_sg_x25 <= ce_2;
register3_q_net_x6 <= ch_in;
clk_1_sg_x18 <= clk_1;
clk_2_sg_x25 <= clk_2;
register4_q_net_x6 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_2_sg_x25,
dest_clk => clk_2_sg_x25,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x18,
src_clk => clk_1_sg_x18,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
d => register4_q_net_x6,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register3_q_net_x6,
b(0) => constant_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register3_q_net_x6,
b => constant1_op_net,
ce => ce_1_sg_x18,
clk => clk_1_sg_x18,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer/TDDM_Mixer"
entity tddm_mixer_entity_8537ade7b6 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
mix0_ch_in: in std_logic;
mix0_i_in: in std_logic_vector(23 downto 0);
mix0_q_in: in std_logic_vector(23 downto 0);
mix1_ch_in: in std_logic;
mix1_i_in: in std_logic_vector(23 downto 0);
mix1_q_in: in std_logic_vector(23 downto 0);
mix_ch0_i_out: out std_logic_vector(23 downto 0);
mix_ch0_q_out: out std_logic_vector(23 downto 0);
mix_ch1_i_out: out std_logic_vector(23 downto 0);
mix_ch1_q_out: out std_logic_vector(23 downto 0);
mix_ch2_i_out: out std_logic_vector(23 downto 0);
mix_ch2_q_out: out std_logic_vector(23 downto 0);
mix_ch3_i_out: out std_logic_vector(23 downto 0);
mix_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_mixer_entity_8537ade7b6;
architecture structural of tddm_mixer_entity_8537ade7b6 is
signal ce_1_sg_x22: std_logic;
signal ce_2_sg_x29: std_logic;
signal clk_1_sg_x22: std_logic;
signal clk_2_sg_x29: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x7: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x6: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x7: std_logic_vector(23 downto 0);
signal register3_q_net_x10: std_logic;
signal register3_q_net_x9: std_logic;
signal register4_q_net_x8: std_logic_vector(23 downto 0);
signal register4_q_net_x9: std_logic_vector(23 downto 0);
signal register5_q_net_x8: std_logic_vector(23 downto 0);
signal register5_q_net_x9: std_logic_vector(23 downto 0);
begin
ce_1_sg_x22 <= ce_1;
ce_2_sg_x29 <= ce_2;
clk_1_sg_x22 <= clk_1;
clk_2_sg_x29 <= clk_2;
register3_q_net_x9 <= mix0_ch_in;
register4_q_net_x8 <= mix0_i_in;
register5_q_net_x8 <= mix0_q_in;
register3_q_net_x10 <= mix1_ch_in;
register4_q_net_x9 <= mix1_i_in;
register5_q_net_x9 <= mix1_q_in;
mix_ch0_i_out <= down_sample2_q_net_x4;
mix_ch0_q_out <= down_sample2_q_net_x5;
mix_ch1_i_out <= down_sample1_q_net_x4;
mix_ch1_q_out <= down_sample1_q_net_x5;
mix_ch2_i_out <= down_sample2_q_net_x6;
mix_ch2_q_out <= down_sample2_q_net_x7;
mix_ch3_i_out <= down_sample1_q_net_x6;
mix_ch3_q_out <= down_sample1_q_net_x7;
tddm_mixer0_i_f95b8f24ad: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x8,
dout_ch0 => down_sample2_q_net_x4,
dout_ch1 => down_sample1_q_net_x4
);
tddm_mixer0_q_2c5e18f496: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x9,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x8,
dout_ch0 => down_sample2_q_net_x5,
dout_ch1 => down_sample1_q_net_x5
);
tddm_mixer1_i_1afc4ccdba: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register4_q_net_x9,
dout_ch0 => down_sample2_q_net_x6,
dout_ch1 => down_sample1_q_net_x6
);
tddm_mixer1_q_ee4acbed30: entity work.tddm_mixer0_i_entity_f95b8f24ad
port map (
ce_1 => ce_1_sg_x22,
ce_2 => ce_2_sg_x29,
ch_in => register3_q_net_x10,
clk_1 => clk_1_sg_x22,
clk_2 => clk_2_sg_x29,
din => register5_q_net_x9,
dout_ch0 => down_sample2_q_net_x7,
dout_ch1 => down_sample1_q_net_x7
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Mixer"
entity mixer_entity_a1cd828545 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
dds_cosine_0: in std_logic_vector(23 downto 0);
dds_cosine_1: in std_logic_vector(23 downto 0);
dds_msine_0: in std_logic_vector(23 downto 0);
dds_msine_1: in std_logic_vector(23 downto 0);
dds_valid_0: in std_logic;
dds_valid_1: in std_logic;
din0: in std_logic_vector(23 downto 0);
din1: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
i_out0: out std_logic_vector(23 downto 0);
i_out1: out std_logic_vector(23 downto 0);
q_out0: out std_logic_vector(23 downto 0);
q_out1: out std_logic_vector(23 downto 0);
tddm_mixer: out std_logic_vector(23 downto 0);
tddm_mixer_x0: out std_logic_vector(23 downto 0);
tddm_mixer_x1: out std_logic_vector(23 downto 0);
tddm_mixer_x2: out std_logic_vector(23 downto 0);
tddm_mixer_x3: out std_logic_vector(23 downto 0);
tddm_mixer_x4: out std_logic_vector(23 downto 0);
tddm_mixer_x5: out std_logic_vector(23 downto 0);
tddm_mixer_x6: out std_logic_vector(23 downto 0)
);
end mixer_entity_a1cd828545;
architecture structural of mixer_entity_a1cd828545 is
signal ce_1_sg_x23: std_logic;
signal ce_2_sg_x30: std_logic;
signal clk_1_sg_x23: std_logic;
signal clk_2_sg_x30: std_logic;
signal constant11_op_net_x2: std_logic;
signal constant12_op_net_x1: std_logic_vector(23 downto 0);
signal constant15_op_net_x1: std_logic;
signal constant1_op_net_x2: std_logic;
signal constant2_op_net_x1: std_logic_vector(23 downto 0);
signal constant3_op_net_x1: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register3_q_net_x11: std_logic;
signal register3_q_net_x12: std_logic;
signal register4_q_net_x10: std_logic_vector(23 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x10: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x16: std_logic_vector(23 downto 0);
signal register_q_net_x17: std_logic_vector(23 downto 0);
begin
ce_1_sg_x23 <= ce_1;
ce_2_sg_x30 <= ce_2;
register1_q_net_x3 <= ch_in0;
register1_q_net_x4 <= ch_in1;
clk_1_sg_x23 <= clk_1;
clk_2_sg_x30 <= clk_2;
register_q_net_x12 <= dds_cosine_0;
register_q_net_x14 <= dds_cosine_1;
register_q_net_x13 <= dds_msine_0;
register_q_net_x15 <= dds_msine_1;
constant15_op_net_x1 <= dds_valid_0;
constant3_op_net_x1 <= dds_valid_1;
register_q_net_x16 <= din0;
register_q_net_x17 <= din1;
ch_out0 <= register3_q_net_x11;
ch_out1 <= register3_q_net_x12;
i_out0 <= register4_q_net_x10;
i_out1 <= register4_q_net_x11;
q_out0 <= register5_q_net_x10;
q_out1 <= register5_q_net_x11;
tddm_mixer <= down_sample1_q_net_x8;
tddm_mixer_x0 <= down_sample2_q_net_x8;
tddm_mixer_x1 <= down_sample1_q_net_x9;
tddm_mixer_x2 <= down_sample2_q_net_x9;
tddm_mixer_x3 <= down_sample1_q_net_x10;
tddm_mixer_x4 <= down_sample2_q_net_x10;
tddm_mixer_x5 <= down_sample1_q_net_x11;
tddm_mixer_x6 <= down_sample2_q_net_x11;
cmixer_0_f630e8d7ec: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x3,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x12,
dds_msine => register_q_net_x13,
dds_valid => constant15_op_net_x1,
din_i => register_q_net_x16,
din_q => constant12_op_net_x1,
en => constant11_op_net_x2,
ch_out => register3_q_net_x11,
i_out => register4_q_net_x10,
q_out => register5_q_net_x10
);
cmixer_1_61bfc18f90: entity work.cmixer_0_entity_f630e8d7ec
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
ch_in => register1_q_net_x4,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
dds_cosine => register_q_net_x14,
dds_msine => register_q_net_x15,
dds_valid => constant3_op_net_x1,
din_i => register_q_net_x17,
din_q => constant2_op_net_x1,
en => constant1_op_net_x2,
ch_out => register3_q_net_x12,
i_out => register4_q_net_x11,
q_out => register5_q_net_x11
);
constant1: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net_x2
);
constant11: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x2
);
constant12: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant12_op_net_x1
);
constant2: entity work.constant_f394f3309c
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant2_op_net_x1
);
tddm_mixer_8537ade7b6: entity work.tddm_mixer_entity_8537ade7b6
port map (
ce_1 => ce_1_sg_x23,
ce_2 => ce_2_sg_x30,
clk_1 => clk_1_sg_x23,
clk_2 => clk_2_sg_x30,
mix0_ch_in => register3_q_net_x11,
mix0_i_in => register4_q_net_x10,
mix0_q_in => register5_q_net_x10,
mix1_ch_in => register3_q_net_x12,
mix1_i_in => register4_q_net_x11,
mix1_q_in => register5_q_net_x11,
mix_ch0_i_out => down_sample2_q_net_x8,
mix_ch0_q_out => down_sample2_q_net_x9,
mix_ch1_i_out => down_sample1_q_net_x8,
mix_ch1_q_out => down_sample1_q_net_x9,
mix_ch2_i_out => down_sample2_q_net_x10,
mix_ch2_q_out => down_sample2_q_net_x11,
mix_ch3_i_out => down_sample1_q_net_x10,
mix_ch3_q_out => down_sample1_q_net_x11
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2/format1"
entity format1_entity_4e0a69646b is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_4e0a69646b;
architecture structural of format1_entity_4e0a69646b is
signal ce_5600000_sg_x0: std_logic;
signal clk_5600000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_5600000_sg_x0 <= ce_5600000;
clk_5600000_sg_x0 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_5600000_sg_x0,
clk => clk_5600000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast2"
entity cast2_entity_4b7421c7c9 is
port (
ce_5600000: in std_logic;
clk_5600000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast2_entity_4b7421c7c9;
architecture structural of cast2_entity_4b7421c7c9 is
signal ce_5600000_sg_x1: std_logic;
signal clk_5600000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_5600000_sg_x1 <= ce_5600000;
clk_5600000_sg_x1 <= clk_5600000;
monit_pfir_m_axis_data_tdata_net_x1 <= data_in;
monit_pfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_4e0a69646b: entity work.format1_entity_4e0a69646b
port map (
ce_5600000 => ce_5600000_sg_x1,
clk_5600000 => clk_5600000_sg_x1,
din => monit_pfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x1,
clk => clk_5600000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4/format1"
entity format1_entity_3cf61b0d44 is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end format1_entity_3cf61b0d44;
architecture structural of format1_entity_3cf61b0d44 is
signal ce_2800000_sg_x0: std_logic;
signal clk_2800000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x0: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
begin
ce_2800000_sg_x0 <= ce_2800000;
clk_2800000_sg_x0 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 21,
din_width => 25,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_2800000_sg_x0,
clk => clk_2800000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cfir_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Cast4"
entity cast4_entity_4ed908d7fc is
port (
ce_2800000: in std_logic;
clk_2800000: in std_logic;
data_in: in std_logic_vector(24 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(23 downto 0)
);
end cast4_entity_4ed908d7fc;
architecture structural of cast4_entity_4ed908d7fc is
signal ce_2800000_sg_x1: std_logic;
signal clk_2800000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(23 downto 0);
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
begin
ce_2800000_sg_x1 <= ce_2800000;
clk_2800000_sg_x1 <= clk_2800000;
monit_cfir_m_axis_data_tdata_net_x1 <= data_in;
monit_cfir_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
format1_3cf61b0d44: entity work.format1_entity_3cf61b0d44
port map (
ce_2800000 => ce_2800000_sg_x1,
clk_2800000 => clk_2800000_sg_x1,
din => monit_cfir_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_2800000_sg_x1,
clk => clk_2800000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_cfir_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/Reg1"
entity reg1_entity_8661a44192 is
port (
ce_1400000: in std_logic;
clk_1400000: in std_logic;
din: in std_logic_vector(60 downto 0);
en: in std_logic;
dout: out std_logic_vector(23 downto 0)
);
end reg1_entity_8661a44192;
architecture structural of reg1_entity_8661a44192 is
signal ce_1400000_sg_x0: std_logic;
signal clk_1400000_sg_x0: std_logic;
signal convert_dout_net: std_logic_vector(23 downto 0);
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(60 downto 0);
begin
ce_1400000_sg_x0 <= ce_1400000;
clk_1400000_sg_x0 <= clk_1400000;
monit_cic_m_axis_data_tdata_data_net_x0 <= din;
monit_cic_m_axis_data_tvalid_net_x0 <= en;
dout <= register_q_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 59,
din_width => 61,
dout_arith => 2,
dout_bin_pt => 22,
dout_width => 24,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
clr => '0',
din => reinterpret2_output_port_net,
en => "1",
dout => convert_dout_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1400000_sg_x0,
clk => clk_1400000_sg_x0,
d => convert_dout_net,
en(0) => monit_cic_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
reinterpret2: entity work.reinterpret_c88e29aa6b
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_cic_m_axis_data_tdata_data_net_x0,
output_port => reinterpret2_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c/TDDM_monit_amp_c_int"
entity tddm_monit_amp_c_int_entity_554a834349 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_22400000: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0);
dout_ch2: out std_logic_vector(23 downto 0);
dout_ch3: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_int_entity_554a834349;
architecture structural of tddm_monit_amp_c_int_entity_554a834349 is
signal ce_22400000_sg_x4: std_logic;
signal ce_5600000_sg_x2: std_logic;
signal clk_22400000_sg_x4: std_logic;
signal clk_5600000_sg_x2: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal delay2_q_net_x0: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net: std_logic_vector(23 downto 0);
signal register3_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_22400000_sg_x4 <= ce_22400000;
ce_5600000_sg_x2 <= ce_5600000;
delay2_q_net_x0 <= ch_in;
clk_22400000_sg_x4 <= clk_22400000;
clk_5600000_sg_x2 <= clk_5600000;
register_q_net_x1 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register2_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register3_q_net,
dest_ce => ce_22400000_sg_x4,
dest_clk => clk_22400000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_5600000_sg_x2,
src_clk => clk_5600000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
d => register_q_net_x1,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant1_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant3_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => delay2_q_net_x0,
b => constant4_op_net,
ce => ce_5600000_sg_x2,
clk => clk_5600000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c/TDDM_monit_amp_c"
entity tddm_monit_amp_c_entity_5b2613eff7 is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_ch_in: in std_logic_vector(1 downto 0);
monit_din: in std_logic_vector(23 downto 0);
monit_ch0_out: out std_logic_vector(23 downto 0);
monit_ch1_out: out std_logic_vector(23 downto 0);
monit_ch2_out: out std_logic_vector(23 downto 0);
monit_ch3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_c_entity_5b2613eff7;
architecture structural of tddm_monit_amp_c_entity_5b2613eff7 is
signal ce_22400000_sg_x5: std_logic;
signal ce_5600000_sg_x3: std_logic;
signal clk_22400000_sg_x5: std_logic;
signal clk_5600000_sg_x3: std_logic;
signal delay2_q_net_x1: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x2: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x5 <= ce_22400000;
ce_5600000_sg_x3 <= ce_5600000;
clk_22400000_sg_x5 <= clk_22400000;
clk_5600000_sg_x3 <= clk_5600000;
delay2_q_net_x1 <= monit_ch_in;
register_q_net_x2 <= monit_din;
monit_ch0_out <= down_sample2_q_net_x1;
monit_ch1_out <= down_sample1_q_net_x1;
monit_ch2_out <= down_sample3_q_net_x1;
monit_ch3_out <= down_sample4_q_net_x1;
tddm_monit_amp_c_int_554a834349: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x5,
ce_5600000 => ce_5600000_sg_x3,
ch_in => delay2_q_net_x1,
clk_22400000 => clk_22400000_sg_x5,
clk_5600000 => clk_5600000_sg_x3,
din => register_q_net_x2,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/Monit_amp_c"
entity monit_amp_c_entity_c83793ea71 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out_x1: out std_logic_vector(1 downto 0);
monit_cfir_x0: out std_logic;
monit_cic_x0: out std_logic;
monit_pfir_x0: out std_logic;
tddm_monit_amp_c: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x0: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x1: out std_logic_vector(23 downto 0);
tddm_monit_amp_c_x2: out std_logic_vector(23 downto 0)
);
end monit_amp_c_entity_c83793ea71;
architecture structural of monit_amp_c_entity_c83793ea71 is
signal ce_1400000_sg_x1: std_logic;
signal ce_1_sg_x24: std_logic;
signal ce_22400000_sg_x6: std_logic;
signal ce_2800000_sg_x2: std_logic;
signal ce_5600000_sg_x4: std_logic;
signal ce_560_sg_x0: std_logic;
signal ce_logic_1400000_sg_x0: std_logic;
signal ce_logic_2800000_sg_x0: std_logic;
signal ce_logic_560_sg_x0: std_logic;
signal ch_out_x0: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x1: std_logic;
signal clk_1_sg_x24: std_logic;
signal clk_22400000_sg_x6: std_logic;
signal clk_2800000_sg_x2: std_logic;
signal clk_5600000_sg_x4: std_logic;
signal clk_560_sg_x0: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal delay1_q_net: std_logic_vector(23 downto 0);
signal delay2_q_net_x2: std_logic_vector(1 downto 0);
signal delay3_q_net: std_logic_vector(23 downto 0);
signal delay_q_net: std_logic_vector(1 downto 0);
signal dout_x0: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x2: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_cfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_cfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_cfir_m_axis_data_tvalid_net_x0: std_logic;
signal monit_cic_event_tlast_unexpected_net_x0: std_logic;
signal monit_cic_m_axis_data_tdata_data_net_x0: std_logic_vector(60 downto 0);
signal monit_cic_m_axis_data_tuser_chan_out_net: std_logic_vector(1 downto 0);
signal monit_cic_m_axis_data_tvalid_net_x0: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pfir_m_axis_data_tdata_net_x1: std_logic_vector(24 downto 0);
signal monit_pfir_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pfir_m_axis_data_tvalid_net_x0: std_logic;
signal register3_q_net: std_logic_vector(1 downto 0);
signal register_q_net_x0: std_logic_vector(23 downto 0);
signal register_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x3: std_logic_vector(23 downto 0);
signal relational2_op_net: std_logic;
begin
ce_1_sg_x24 <= ce_1;
ce_1400000_sg_x1 <= ce_1400000;
ce_22400000_sg_x6 <= ce_22400000;
ce_2800000_sg_x2 <= ce_2800000;
ce_560_sg_x0 <= ce_560;
ce_5600000_sg_x4 <= ce_5600000;
ce_logic_1400000_sg_x0 <= ce_logic_1400000;
ce_logic_2800000_sg_x0 <= ce_logic_2800000;
ce_logic_560_sg_x0 <= ce_logic_560;
ch_out_x0 <= ch_in;
clk_1_sg_x24 <= clk_1;
clk_1400000_sg_x1 <= clk_1400000;
clk_22400000_sg_x6 <= clk_22400000;
clk_2800000_sg_x2 <= clk_2800000;
clk_560_sg_x0 <= clk_560;
clk_5600000_sg_x4 <= clk_5600000;
dout_x0 <= din;
amp_out <= register_q_net_x3;
ch_out_x1 <= delay2_q_net_x2;
monit_cfir_x0 <= monit_cfir_event_s_data_chanid_incorrect_net_x0;
monit_cic_x0 <= monit_cic_event_tlast_unexpected_net_x0;
monit_pfir_x0 <= monit_pfir_event_s_data_chanid_incorrect_net_x0;
tddm_monit_amp_c <= down_sample1_q_net_x2;
tddm_monit_amp_c_x0 <= down_sample2_q_net_x2;
tddm_monit_amp_c_x1 <= down_sample3_q_net_x2;
tddm_monit_amp_c_x2 <= down_sample4_q_net_x2;
cast2_4b7421c7c9: entity work.cast2_entity_4b7421c7c9
port map (
ce_5600000 => ce_5600000_sg_x4,
clk_5600000 => clk_5600000_sg_x4,
data_in => monit_pfir_m_axis_data_tdata_net_x1,
en => monit_pfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x3
);
cast4_4ed908d7fc: entity work.cast4_entity_4ed908d7fc
port map (
ce_2800000 => ce_2800000_sg_x2,
clk_2800000 => clk_2800000_sg_x2,
data_in => monit_cfir_m_axis_data_tdata_net_x1,
en => monit_cfir_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0
);
constant1: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
delay: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => monit_cic_m_axis_data_tuser_chan_out_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 3,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
d => dout_x0,
en => '1',
rst => '1',
q => delay1_q_net
);
delay2: entity work.xldelay
generic map (
latency => 1,
reg_retiming => 0,
reset => 0,
width => 2
)
port map (
ce => ce_5600000_sg_x4,
clk => clk_5600000_sg_x4,
d => monit_pfir_m_axis_data_tuser_chanid_net,
en => '1',
rst => '1',
q => delay2_q_net_x2
);
delay3: entity work.xldelay
generic map (
latency => 2,
reg_retiming => 0,
reset => 0,
width => 24
)
port map (
ce => ce_1400000_sg_x1,
clk => clk_1400000_sg_x1,
d => register_q_net_x1,
en => '1',
rst => '1',
q => delay3_q_net
);
monit_cfir: entity work.xlfir_compiler_9c8746ef58b9fecaf8fa2bea81370554
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_2800000 => ce_2800000_sg_x2,
ce_logic_1400000 => ce_logic_1400000_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_2800000 => clk_2800000_sg_x2,
clk_logic_1400000 => clk_1400000_sg_x1,
s_axis_data_tdata => delay3_q_net,
s_axis_data_tuser_chanid => delay_q_net,
src_ce => ce_1400000_sg_x1,
src_clk => clk_1400000_sg_x1,
event_s_data_chanid_incorrect => monit_cfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_cfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_cfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_cfir_m_axis_data_tvalid_net_x0
);
monit_cic: entity work.xlcic_compiler_1c97a249b004729f66738a648c4f9593
port map (
ce => ce_1_sg_x24,
ce_1400000 => ce_1400000_sg_x1,
ce_560 => ce_560_sg_x0,
ce_logic_560 => ce_logic_560_sg_x0,
clk => clk_1_sg_x24,
clk_1400000 => clk_1400000_sg_x1,
clk_560 => clk_560_sg_x0,
clk_logic_560 => clk_560_sg_x0,
s_axis_data_tdata_data => delay1_q_net,
s_axis_data_tlast => relational2_op_net,
event_tlast_unexpected => monit_cic_event_tlast_unexpected_net_x0,
m_axis_data_tdata_data => monit_cic_m_axis_data_tdata_data_net_x0,
m_axis_data_tuser_chan_out => monit_cic_m_axis_data_tuser_chan_out_net,
m_axis_data_tvalid => monit_cic_m_axis_data_tvalid_net_x0
);
monit_pfir: entity work.xlfir_compiler_ef89cacae87a636bad21e5ee1476453a
port map (
ce => ce_1_sg_x24,
ce_2800000 => ce_2800000_sg_x2,
ce_5600000 => ce_5600000_sg_x4,
ce_logic_2800000 => ce_logic_2800000_sg_x0,
clk => clk_1_sg_x24,
clk_2800000 => clk_2800000_sg_x2,
clk_5600000 => clk_5600000_sg_x4,
clk_logic_2800000 => clk_2800000_sg_x2,
s_axis_data_tdata => register_q_net_x0,
s_axis_data_tuser_chanid => register3_q_net,
src_ce => ce_2800000_sg_x2,
src_clk => clk_2800000_sg_x2,
event_s_data_chanid_incorrect => monit_pfir_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pfir_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pfir_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pfir_m_axis_data_tvalid_net_x0
);
reg1_8661a44192: entity work.reg1_entity_8661a44192
port map (
ce_1400000 => ce_1400000_sg_x1,
clk_1400000 => clk_1400000_sg_x1,
din => monit_cic_m_axis_data_tdata_data_net_x0,
en => monit_cic_m_axis_data_tvalid_net_x0,
dout => register_q_net_x1
);
register3: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_2800000_sg_x2,
clk => clk_2800000_sg_x2,
d => monit_cfir_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register3_q_net
);
relational2: entity work.relational_83ca2c6a3c
port map (
a => ch_out_x0,
b => constant1_op_net,
ce => ce_560_sg_x0,
clk => clk_560_sg_x0,
clr => '0',
op(0) => relational2_op_net
);
tddm_monit_amp_c_5b2613eff7: entity work.tddm_monit_amp_c_entity_5b2613eff7
port map (
ce_22400000 => ce_22400000_sg_x6,
ce_5600000 => ce_5600000_sg_x4,
clk_22400000 => clk_22400000_sg_x6,
clk_5600000 => clk_5600000_sg_x4,
monit_ch_in => delay2_q_net_x2,
monit_din => register_q_net_x3,
monit_ch0_out => down_sample2_q_net_x2,
monit_ch1_out => down_sample1_q_net_x2,
monit_ch2_out => down_sample3_q_net_x2,
monit_ch3_out => down_sample4_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp/TDDM_monit_amp_out"
entity tddm_monit_amp_out_entity_521eb373cc is
port (
ce_22400000: in std_logic;
ce_5600000: in std_logic;
clk_22400000: in std_logic;
clk_5600000: in std_logic;
monit_amp_ch_in: in std_logic_vector(1 downto 0);
monit_amp_din: in std_logic_vector(23 downto 0);
monit_amp_data0_out: out std_logic_vector(23 downto 0);
monit_amp_data1_out: out std_logic_vector(23 downto 0);
monit_amp_data2_out: out std_logic_vector(23 downto 0);
monit_amp_data3_out: out std_logic_vector(23 downto 0)
);
end tddm_monit_amp_out_entity_521eb373cc;
architecture structural of tddm_monit_amp_out_entity_521eb373cc is
signal ce_22400000_sg_x8: std_logic;
signal ce_5600000_sg_x6: std_logic;
signal clk_22400000_sg_x8: std_logic;
signal clk_5600000_sg_x6: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(23 downto 0);
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_22400000_sg_x8 <= ce_22400000;
ce_5600000_sg_x6 <= ce_5600000;
clk_22400000_sg_x8 <= clk_22400000;
clk_5600000_sg_x6 <= clk_5600000;
delay2_q_net_x4 <= monit_amp_ch_in;
register_q_net_x5 <= monit_amp_din;
monit_amp_data0_out <= down_sample2_q_net_x1;
monit_amp_data1_out <= down_sample1_q_net_x1;
monit_amp_data2_out <= down_sample3_q_net_x1;
monit_amp_data3_out <= down_sample4_q_net_x1;
tddm_monit_amp_out_int_b60196c7a6: entity work.tddm_monit_amp_c_int_entity_554a834349
port map (
ce_22400000 => ce_22400000_sg_x8,
ce_5600000 => ce_5600000_sg_x6,
ch_in => delay2_q_net_x4,
clk_22400000 => clk_22400000_sg_x8,
clk_5600000 => clk_5600000_sg_x6,
din => register_q_net_x5,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/Monit_amp"
entity monit_amp_entity_44da74e268 is
port (
ce_1: in std_logic;
ce_1400000: in std_logic;
ce_22400000: in std_logic;
ce_2800000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_1400000: in std_logic;
clk_22400000: in std_logic;
clk_2800000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
monit_amp_c: out std_logic_vector(23 downto 0);
monit_amp_c_x0: out std_logic_vector(23 downto 0);
monit_amp_c_x1: out std_logic_vector(23 downto 0);
monit_amp_c_x2: out std_logic_vector(23 downto 0);
monit_amp_c_x3: out std_logic;
monit_amp_c_x4: out std_logic;
monit_amp_c_x5: out std_logic
);
end monit_amp_entity_44da74e268;
architecture structural of monit_amp_entity_44da74e268 is
signal ce_1400000_sg_x2: std_logic;
signal ce_1_sg_x25: std_logic;
signal ce_22400000_sg_x9: std_logic;
signal ce_2800000_sg_x3: std_logic;
signal ce_5600000_sg_x7: std_logic;
signal ce_560_sg_x1: std_logic;
signal ce_logic_1400000_sg_x1: std_logic;
signal ce_logic_2800000_sg_x1: std_logic;
signal ce_logic_560_sg_x1: std_logic;
signal ch_out_x1: std_logic_vector(1 downto 0);
signal clk_1400000_sg_x2: std_logic;
signal clk_1_sg_x25: std_logic;
signal clk_22400000_sg_x9: std_logic;
signal clk_2800000_sg_x3: std_logic;
signal clk_5600000_sg_x7: std_logic;
signal clk_560_sg_x1: std_logic;
signal delay2_q_net_x4: std_logic_vector(1 downto 0);
signal dout_x1: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x4: std_logic_vector(23 downto 0);
signal monit_cfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal monit_cic_event_tlast_unexpected_net_x1: std_logic;
signal monit_pfir_event_s_data_chanid_incorrect_net_x1: std_logic;
signal register_q_net_x5: std_logic_vector(23 downto 0);
begin
ce_1_sg_x25 <= ce_1;
ce_1400000_sg_x2 <= ce_1400000;
ce_22400000_sg_x9 <= ce_22400000;
ce_2800000_sg_x3 <= ce_2800000;
ce_560_sg_x1 <= ce_560;
ce_5600000_sg_x7 <= ce_5600000;
ce_logic_1400000_sg_x1 <= ce_logic_1400000;
ce_logic_2800000_sg_x1 <= ce_logic_2800000;
ce_logic_560_sg_x1 <= ce_logic_560;
ch_out_x1 <= ch_in;
clk_1_sg_x25 <= clk_1;
clk_1400000_sg_x2 <= clk_1400000;
clk_22400000_sg_x9 <= clk_22400000;
clk_2800000_sg_x3 <= clk_2800000;
clk_560_sg_x1 <= clk_560;
clk_5600000_sg_x7 <= clk_5600000;
dout_x1 <= din;
amp_out0 <= down_sample2_q_net_x4;
amp_out1 <= down_sample1_q_net_x4;
amp_out2 <= down_sample3_q_net_x4;
amp_out3 <= down_sample4_q_net_x4;
monit_amp_c <= down_sample1_q_net_x3;
monit_amp_c_x0 <= down_sample2_q_net_x3;
monit_amp_c_x1 <= down_sample3_q_net_x3;
monit_amp_c_x2 <= down_sample4_q_net_x3;
monit_amp_c_x3 <= monit_cfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_x4 <= monit_cic_event_tlast_unexpected_net_x1;
monit_amp_c_x5 <= monit_pfir_event_s_data_chanid_incorrect_net_x1;
monit_amp_c_c83793ea71: entity work.monit_amp_c_entity_c83793ea71
port map (
ce_1 => ce_1_sg_x25,
ce_1400000 => ce_1400000_sg_x2,
ce_22400000 => ce_22400000_sg_x9,
ce_2800000 => ce_2800000_sg_x3,
ce_560 => ce_560_sg_x1,
ce_5600000 => ce_5600000_sg_x7,
ce_logic_1400000 => ce_logic_1400000_sg_x1,
ce_logic_2800000 => ce_logic_2800000_sg_x1,
ce_logic_560 => ce_logic_560_sg_x1,
ch_in => ch_out_x1,
clk_1 => clk_1_sg_x25,
clk_1400000 => clk_1400000_sg_x2,
clk_22400000 => clk_22400000_sg_x9,
clk_2800000 => clk_2800000_sg_x3,
clk_560 => clk_560_sg_x1,
clk_5600000 => clk_5600000_sg_x7,
din => dout_x1,
amp_out => register_q_net_x5,
ch_out_x1 => delay2_q_net_x4,
monit_cfir_x0 => monit_cfir_event_s_data_chanid_incorrect_net_x1,
monit_cic_x0 => monit_cic_event_tlast_unexpected_net_x1,
monit_pfir_x0 => monit_pfir_event_s_data_chanid_incorrect_net_x1,
tddm_monit_amp_c => down_sample1_q_net_x3,
tddm_monit_amp_c_x0 => down_sample2_q_net_x3,
tddm_monit_amp_c_x1 => down_sample3_q_net_x3,
tddm_monit_amp_c_x2 => down_sample4_q_net_x3
);
tddm_monit_amp_out_521eb373cc: entity work.tddm_monit_amp_out_entity_521eb373cc
port map (
ce_22400000 => ce_22400000_sg_x9,
ce_5600000 => ce_5600000_sg_x7,
clk_22400000 => clk_22400000_sg_x9,
clk_5600000 => clk_5600000_sg_x7,
monit_amp_ch_in => delay2_q_net_x4,
monit_amp_din => register_q_net_x5,
monit_amp_data0_out => down_sample2_q_net_x4,
monit_amp_data1_out => down_sample1_q_net_x4,
monit_amp_data2_out => down_sample3_q_net_x4,
monit_amp_data3_out => down_sample4_q_net_x4
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_5b94be40c5 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_5b94be40c5;
architecture structural of tddm_tbt_cordic_entity_5b94be40c5 is
signal ce_35_sg_x0: std_logic;
signal ce_70_sg_x4: std_logic;
signal clk_35_sg_x0: std_logic;
signal clk_70_sg_x4: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_amp_out_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x0: std_logic;
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x0 <= ce_35;
ce_70_sg_x4 <= ce_70;
p_ch_out_x0 <= ch_in;
clk_35_sg_x0 <= clk_35;
clk_70_sg_x4 <= clk_70;
p_amp_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x4,
dest_clk => clk_70_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x0,
src_clk => clk_35_sg_x0,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
d => p_amp_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x0,
b(0) => constant1_op_net,
ce => ce_35_sg_x0,
clk => clk_35_sg_x0,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic/TDDM_tbt_cordic1"
entity tddm_tbt_cordic1_entity_d3f44a687c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic1_entity_d3f44a687c;
architecture structural of tddm_tbt_cordic1_entity_d3f44a687c is
signal ce_35_sg_x1: std_logic;
signal ce_70_sg_x5: std_logic;
signal clk_35_sg_x1: std_logic;
signal clk_70_sg_x5: std_logic;
signal constant1_op_net: std_logic;
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal p_ch_out_x1: std_logic;
signal p_phase_out_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register_q_net: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x1 <= ce_35;
ce_70_sg_x5 <= ce_70;
p_ch_out_x1 <= ch_in;
clk_35_sg_x1 <= clk_35;
clk_70_sg_x5 <= clk_70;
p_phase_out_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x5,
dest_clk => clk_70_sg_x5,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x1,
src_clk => clk_35_sg_x1,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
d => p_phase_out_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_a892e1bf40
port map (
a(0) => p_ch_out_x1,
b(0) => constant1_op_net,
ce => ce_35_sg_x1,
clk => clk_35_sg_x1,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_18d3979a26 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_data0_out: out std_logic_vector(23 downto 0);
tbt_cordic_data1_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_18d3979a26;
architecture structural of tddm_tbt_cordic_entity_18d3979a26 is
signal ce_35_sg_x2: std_logic;
signal ce_70_sg_x6: std_logic;
signal clk_35_sg_x2: std_logic;
signal clk_70_sg_x6: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x2 <= ce_35;
ce_70_sg_x6 <= ce_70;
clk_35_sg_x2 <= clk_35;
clk_70_sg_x6 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_data0_out <= down_sample2_q_net_x2;
tbt_cordic_data1_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d3f44a687c: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_5b94be40c5: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x2,
ce_70 => ce_70_sg_x6,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x2,
clk_70 => clk_70_sg_x6,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_CORDIC"
entity tbt_cordic_entity_232cb2e43e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_232cb2e43e;
architecture structural of tbt_cordic_entity_232cb2e43e is
signal ce_1_sg_x26: std_logic;
signal ce_35_sg_x3: std_logic;
signal ce_70_sg_x7: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x26: std_logic;
signal clk_35_sg_x3: std_logic;
signal clk_70_sg_x7: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x26 <= ce_1;
ce_35_sg_x3 <= ce_35;
ce_70_sg_x7 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x26 <= clk_1;
clk_35_sg_x3 <= clk_35;
clk_70_sg_x7 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x3,
dest_clk => clk_35_sg_x3,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x26,
src_clk => clk_1_sg_x26,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x26,
clk => clk_1_sg_x26,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_18d3979a26: entity work.tddm_tbt_cordic_entity_18d3979a26
port map (
ce_35 => ce_35_sg_x3,
ce_70 => ce_70_sg_x7,
clk_35 => clk_35_sg_x3,
clk_70 => clk_70_sg_x7,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_data0_out => down_sample2_q_net_x4,
tbt_cordic_data1_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x26,
dest_clk => clk_1_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x3,
src_clk => clk_35_sg_x3,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT/TDDM_tbt_poly_i"
entity tddm_tbt_poly_i_entity_469601736c is
port (
ce_35: in std_logic;
ce_70: in std_logic;
ch_in: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
din: in std_logic_vector(23 downto 0);
dout_ch0: out std_logic_vector(23 downto 0);
dout_ch1: out std_logic_vector(23 downto 0)
);
end tddm_tbt_poly_i_entity_469601736c;
architecture structural of tddm_tbt_poly_i_entity_469601736c is
signal ce_35_sg_x4: std_logic;
signal ce_70_sg_x8: std_logic;
signal clk_35_sg_x4: std_logic;
signal clk_70_sg_x8: std_logic;
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic;
signal down_sample1_q_net_x0: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic_vector(23 downto 0);
signal register2_q_net_x1: std_logic;
signal register_q_net: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x0: std_logic_vector(23 downto 0);
signal relational1_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_35_sg_x4 <= ce_35;
ce_70_sg_x8 <= ce_70;
register2_q_net_x1 <= ch_in;
clk_35_sg_x4 <= clk_35;
clk_70_sg_x8 <= clk_70;
reinterpret_output_port_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant_x0: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register1_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 2,
latency => 1,
phase => 1,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register_q_net,
dest_ce => ce_70_sg_x8,
dest_clk => clk_70_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x4,
src_clk => clk_35_sg_x4,
src_clr => '0',
q => down_sample2_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
d => reinterpret_output_port_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net
);
relational: entity work.relational_a892e1bf40
port map (
a(0) => register2_q_net_x1,
b(0) => constant_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_d29d27b7b3
port map (
a(0) => register2_q_net_x1,
b => constant1_op_net,
ce => ce_35_sg_x4,
clk => clk_35_sg_x4,
clr => '0',
op(0) => relational1_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_9ac9f65b0b is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch0_i_out: out std_logic_vector(23 downto 0);
poly35_ch0_q_out: out std_logic_vector(23 downto 0);
poly35_ch1_i_out: out std_logic_vector(23 downto 0);
poly35_ch1_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_9ac9f65b0b;
architecture structural of tddm_tbt_entity_9ac9f65b0b is
signal ce_35_sg_x6: std_logic;
signal ce_70_sg_x10: std_logic;
signal clk_35_sg_x6: std_logic;
signal clk_70_sg_x10: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x6 <= ce_35;
ce_70_sg_x10 <= ce_70;
clk_35_sg_x6 <= clk_35;
clk_70_sg_x10 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch0_i_out <= down_sample2_q_net_x2;
poly35_ch0_q_out <= down_sample2_q_net_x3;
poly35_ch1_i_out <= down_sample1_q_net_x2;
poly35_ch1_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_469601736c: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_8011b4e29e: entity work.tddm_tbt_poly_i_entity_469601736c
port map (
ce_35 => ce_35_sg_x6,
ce_70 => ce_70_sg_x10,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x6,
clk_70 => clk_70_sg_x10,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim/Trunc"
entity trunc_entity_e5eda8a5ac is
port (
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end trunc_entity_e5eda8a5ac;
architecture structural of trunc_entity_e5eda8a5ac is
signal register1_q_net_x2: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal slice_y_net: std_logic_vector(23 downto 0);
begin
register1_q_net_x2 <= din;
dout <= reinterpret_output_port_net_x3;
reinterpret: entity work.reinterpret_4bf1ad328a
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => slice_y_net,
output_port => reinterpret_output_port_net_x3
);
slice: entity work.xlslice
generic map (
new_lsb => 1,
new_msb => 24,
x_width => 25,
y_width => 24
)
port map (
x => register1_q_net_x2,
y => slice_y_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0/TBT_poly_decim"
entity tbt_poly_decim_entity_4477ec06c2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_4477ec06c2;
architecture structural of tbt_poly_decim_entity_4477ec06c2 is
signal ce_1_sg_x27: std_logic;
signal ce_35_sg_x7: std_logic;
signal ce_70_sg_x11: std_logic;
signal ce_logic_1_sg_x12: std_logic;
signal clk_1_sg_x27: std_logic;
signal clk_35_sg_x7: std_logic;
signal clk_70_sg_x11: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x12: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x11: std_logic_vector(23 downto 0);
signal register5_q_net_x11: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x27 <= ce_1;
ce_35_sg_x7 <= ce_35;
ce_70_sg_x11 <= ce_70;
ce_logic_1_sg_x12 <= ce_logic_1;
register3_q_net_x12 <= ch_in;
clk_1_sg_x27 <= clk_1;
clk_35_sg_x7 <= clk_35;
clk_70_sg_x11 <= clk_70;
register4_q_net_x11 <= i_in;
register5_q_net_x11 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x7,
clk => clk_35_sg_x7,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_516bd78992d05073446d2f0e193ec7f1
port map (
ce => ce_1_sg_x27,
ce_35 => ce_35_sg_x7,
ce_logic_1 => ce_logic_1_sg_x12,
clk => clk_1_sg_x27,
clk_35 => clk_35_sg_x7,
clk_logic_1 => clk_1_sg_x27,
s_axis_data_tdata_path0 => register4_q_net_x11,
s_axis_data_tdata_path1 => register5_q_net_x11,
s_axis_data_tuser_chanid(0) => register3_q_net_x12,
src_ce => ce_1_sg_x27,
src_clk => clk_1_sg_x27,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_9ac9f65b0b: entity work.tddm_tbt_entity_9ac9f65b0b
port map (
ce_35 => ce_35_sg_x7,
ce_70 => ce_70_sg_x11,
clk_35 => clk_35_sg_x7,
clk_70 => clk_70_sg_x11,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch0_i_out => down_sample2_q_net_x4,
poly35_ch0_q_out => down_sample2_q_net_x5,
poly35_ch1_i_out => down_sample1_q_net_x4,
poly35_ch1_q_out => down_sample1_q_net_x5
);
trunc1_841a61ebcc: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_e5eda8a5ac: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp0"
entity tbt_amp0_entity_88b1c45f0e is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp0_entity_88b1c45f0e;
architecture structural of tbt_amp0_entity_88b1c45f0e is
signal ce_1_sg_x28: std_logic;
signal ce_35_sg_x8: std_logic;
signal ce_70_sg_x12: std_logic;
signal ce_logic_1_sg_x13: std_logic;
signal clk_1_sg_x28: std_logic;
signal clk_35_sg_x8: std_logic;
signal clk_70_sg_x12: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x28 <= ce_1;
ce_35_sg_x8 <= ce_35;
ce_70_sg_x12 <= ce_70;
ce_logic_1_sg_x13 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x28 <= clk_1;
clk_35_sg_x8 <= clk_35;
clk_70_sg_x12 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_232cb2e43e: entity work.tbt_cordic_entity_232cb2e43e
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_4477ec06c2: entity work.tbt_poly_decim_entity_4477ec06c2
port map (
ce_1 => ce_1_sg_x28,
ce_35 => ce_35_sg_x8,
ce_70 => ce_70_sg_x12,
ce_logic_1 => ce_logic_1_sg_x13,
ch_in => register3_q_net_x13,
clk_1 => clk_1_sg_x28,
clk_35 => clk_35_sg_x8,
clk_70 => clk_70_sg_x12,
i_in => register4_q_net_x12,
q_in => register5_q_net_x12,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC/TDDM_tbt_cordic"
entity tddm_tbt_cordic_entity_9e99bd206d is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_cordic_ch_in: in std_logic;
tbt_cordic_din: in std_logic_vector(23 downto 0);
tbt_cordic_pin: in std_logic_vector(23 downto 0);
tbt_cordic_ch2_out: out std_logic_vector(23 downto 0);
tbt_cordic_ch3_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase0_out: out std_logic_vector(23 downto 0);
tbt_cordic_phase1_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_cordic_entity_9e99bd206d;
architecture structural of tddm_tbt_cordic_entity_9e99bd206d is
signal ce_35_sg_x11: std_logic;
signal ce_70_sg_x15: std_logic;
signal clk_35_sg_x11: std_logic;
signal clk_70_sg_x15: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x1: std_logic_vector(23 downto 0);
signal p_ch_out_x2: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
begin
ce_35_sg_x11 <= ce_35;
ce_70_sg_x15 <= ce_70;
clk_35_sg_x11 <= clk_35;
clk_70_sg_x15 <= clk_70;
p_ch_out_x2 <= tbt_cordic_ch_in;
p_amp_out_x1 <= tbt_cordic_din;
p_phase_out_x1 <= tbt_cordic_pin;
tbt_cordic_ch2_out <= down_sample2_q_net_x2;
tbt_cordic_ch3_out <= down_sample1_q_net_x2;
tbt_cordic_phase0_out <= down_sample2_q_net_x3;
tbt_cordic_phase1_out <= down_sample1_q_net_x3;
tddm_tbt_cordic1_d22fbdac88: entity work.tddm_tbt_cordic1_entity_d3f44a687c
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_phase_out_x1,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
tddm_tbt_cordic_f04a48283a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x11,
ce_70 => ce_70_sg_x15,
ch_in => p_ch_out_x2,
clk_35 => clk_35_sg_x11,
clk_70 => clk_70_sg_x15,
din => p_amp_out_x1,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_CORDIC"
entity tbt_cordic_entity_9dc3371de2 is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ch_in_x0: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(24 downto 0);
q_in: in std_logic_vector(24 downto 0);
valid_in_x0: in std_logic;
amp_out: out std_logic_vector(23 downto 0);
ch_out_x0: out std_logic;
tddm_tbt_cordic: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x0: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x1: out std_logic_vector(23 downto 0);
tddm_tbt_cordic_x2: out std_logic_vector(23 downto 0)
);
end tbt_cordic_entity_9dc3371de2;
architecture structural of tbt_cordic_entity_9dc3371de2 is
signal ce_1_sg_x29: std_logic;
signal ce_35_sg_x12: std_logic;
signal ce_70_sg_x16: std_logic;
signal ch_in: std_logic;
signal ch_out: std_logic;
signal clk_1_sg_x29: std_logic;
signal clk_35_sg_x12: std_logic;
signal clk_70_sg_x16: std_logic;
signal down_sample1_q_net: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net: std_logic;
signal i: std_logic_vector(24 downto 0);
signal p_amp_out_x2: std_logic_vector(23 downto 0);
signal p_ch_out_x3: std_logic;
signal p_phase_out_x1: std_logic_vector(23 downto 0);
signal phase: std_logic_vector(23 downto 0);
signal q: std_logic_vector(24 downto 0);
signal real_x0: std_logic_vector(23 downto 0);
signal register1_q_net: std_logic;
signal register1_q_net_x1: std_logic_vector(24 downto 0);
signal register2_q_net_x0: std_logic;
signal register3_q_net_x0: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(23 downto 0);
signal register5_q_net: std_logic_vector(23 downto 0);
signal register6_q_net_x0: std_logic;
signal reinterpret2_output_port_net: std_logic_vector(23 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(23 downto 0);
signal valid_in: std_logic;
signal valid_out: std_logic;
begin
ce_1_sg_x29 <= ce_1;
ce_35_sg_x12 <= ce_35;
ce_70_sg_x16 <= ce_70;
register2_q_net_x0 <= ch_in_x0;
clk_1_sg_x29 <= clk_1;
clk_35_sg_x12 <= clk_35;
clk_70_sg_x16 <= clk_70;
register3_q_net_x0 <= i_in;
register1_q_net_x1 <= q_in;
register6_q_net_x0 <= valid_in_x0;
amp_out <= p_amp_out_x2;
ch_out_x0 <= p_ch_out_x3;
tddm_tbt_cordic <= down_sample1_q_net_x4;
tddm_tbt_cordic_x0 <= down_sample2_q_net_x4;
tddm_tbt_cordic_x1 <= down_sample1_q_net_x5;
tddm_tbt_cordic_x2 <= down_sample2_q_net_x5;
assert1: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample1_q_net,
dout => p_phase_out_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 24,
dout_width => 24
)
port map (
din => down_sample2_q_net,
dout => p_amp_out_x2
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => p_ch_out_x3
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 24
)
port map (
d => register4_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => register5_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q => down_sample2_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register1_q_net,
dest_ce => ce_35_sg_x12,
dest_clk => clk_35_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x29,
src_clk => clk_1_sg_x29,
src_clr => '0',
q(0) => down_sample4_q_net
);
rect2pol: entity work.xlcordic_1700ad0af26476326977e0830172a2c4
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
s_axis_cartesian_tdata_imag => q,
s_axis_cartesian_tdata_real => i,
s_axis_cartesian_tuser_user(0) => ch_in,
s_axis_cartesian_tvalid => valid_in,
m_axis_dout_tdata_phase => phase,
m_axis_dout_tdata_real => real_x0,
m_axis_dout_tuser_cartesian_tuser(0) => ch_out,
m_axis_dout_tvalid => valid_out
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d(0) => ch_out,
en(0) => valid_out,
rst => "0",
q(0) => register1_q_net
);
register4: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret2_output_port_net,
en(0) => valid_out,
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x29,
clk => clk_1_sg_x29,
d => reinterpret3_output_port_net,
en(0) => valid_out,
rst => "0",
q => register5_q_net
);
reinterpret2: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => phase,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_b62f4240f0
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => real_x0,
output_port => reinterpret3_output_port_net
);
tddm_tbt_cordic_9e99bd206d: entity work.tddm_tbt_cordic_entity_9e99bd206d
port map (
ce_35 => ce_35_sg_x12,
ce_70 => ce_70_sg_x16,
clk_35 => clk_35_sg_x12,
clk_70 => clk_70_sg_x16,
tbt_cordic_ch_in => p_ch_out_x3,
tbt_cordic_din => p_amp_out_x2,
tbt_cordic_pin => p_phase_out_x1,
tbt_cordic_ch2_out => down_sample2_q_net_x4,
tbt_cordic_ch3_out => down_sample1_q_net_x4,
tbt_cordic_phase0_out => down_sample2_q_net_x5,
tbt_cordic_phase1_out => down_sample1_q_net_x5
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register6_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => valid_in
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register1_q_net_x1,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => q
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 23,
d_width => 25,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 23,
q_width => 25
)
port map (
d => register3_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q => i
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => register2_q_net_x0,
dest_ce => ce_1_sg_x29,
dest_clk => clk_1_sg_x29,
dest_clr => '0',
en => "1",
src_ce => ce_35_sg_x12,
src_clk => clk_35_sg_x12,
src_clr => '0',
q(0) => ch_in
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim/TDDM_TBT"
entity tddm_tbt_entity_1f4b61e651 is
port (
ce_35: in std_logic;
ce_70: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
tbt_ch_in: in std_logic;
tbt_i_in: in std_logic_vector(23 downto 0);
tbt_q_in: in std_logic_vector(23 downto 0);
poly35_ch2_i_out: out std_logic_vector(23 downto 0);
poly35_ch2_q_out: out std_logic_vector(23 downto 0);
poly35_ch3_i_out: out std_logic_vector(23 downto 0);
poly35_ch3_q_out: out std_logic_vector(23 downto 0)
);
end tddm_tbt_entity_1f4b61e651;
architecture structural of tddm_tbt_entity_1f4b61e651 is
signal ce_35_sg_x15: std_logic;
signal ce_70_sg_x19: std_logic;
signal clk_35_sg_x15: std_logic;
signal clk_70_sg_x19: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal register2_q_net_x3: std_logic;
signal reinterpret_output_port_net_x2: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
begin
ce_35_sg_x15 <= ce_35;
ce_70_sg_x19 <= ce_70;
clk_35_sg_x15 <= clk_35;
clk_70_sg_x19 <= clk_70;
register2_q_net_x3 <= tbt_ch_in;
reinterpret_output_port_net_x3 <= tbt_i_in;
reinterpret_output_port_net_x2 <= tbt_q_in;
poly35_ch2_i_out <= down_sample2_q_net_x2;
poly35_ch2_q_out <= down_sample2_q_net_x3;
poly35_ch3_i_out <= down_sample1_q_net_x2;
poly35_ch3_q_out <= down_sample1_q_net_x3;
tddm_tbt_poly_i_b74b709553: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x3,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_poly_q_4f85d7362a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x15,
ce_70 => ce_70_sg_x19,
ch_in => register2_q_net_x3,
clk_35 => clk_35_sg_x15,
clk_70 => clk_70_sg_x19,
din => reinterpret_output_port_net_x2,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1/TBT_poly_decim"
entity tbt_poly_decim_entity_bb6f6b5b6a is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
ch_out: out std_logic;
i_out: out std_logic_vector(24 downto 0);
q_out: out std_logic_vector(24 downto 0);
tbt_poly_x0: out std_logic;
tddm_tbt: out std_logic_vector(23 downto 0);
tddm_tbt_x0: out std_logic_vector(23 downto 0);
tddm_tbt_x1: out std_logic_vector(23 downto 0);
tddm_tbt_x2: out std_logic_vector(23 downto 0);
valid_out: out std_logic
);
end tbt_poly_decim_entity_bb6f6b5b6a;
architecture structural of tbt_poly_decim_entity_bb6f6b5b6a is
signal ce_1_sg_x30: std_logic;
signal ce_35_sg_x16: std_logic;
signal ce_70_sg_x20: std_logic;
signal ce_logic_1_sg_x14: std_logic;
signal clk_1_sg_x30: std_logic;
signal clk_35_sg_x16: std_logic;
signal clk_70_sg_x20: std_logic;
signal down_sample1_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x4: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x13: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x12: std_logic_vector(23 downto 0);
signal register5_q_net_x12: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret_output_port_net_x3: std_logic_vector(23 downto 0);
signal reinterpret_output_port_net_x4: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x0: std_logic;
signal tbt_poly_m_axis_data_tdata_path0_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tdata_path1_net: std_logic_vector(24 downto 0);
signal tbt_poly_m_axis_data_tuser_chanid_net: std_logic;
signal tbt_poly_m_axis_data_tvalid_net: std_logic;
begin
ce_1_sg_x30 <= ce_1;
ce_35_sg_x16 <= ce_35;
ce_70_sg_x20 <= ce_70;
ce_logic_1_sg_x14 <= ce_logic_1;
register3_q_net_x13 <= ch_in;
clk_1_sg_x30 <= clk_1;
clk_35_sg_x16 <= clk_35;
clk_70_sg_x20 <= clk_70;
register4_q_net_x12 <= i_in;
register5_q_net_x12 <= q_in;
ch_out <= register2_q_net_x4;
i_out <= register3_q_net_x2;
q_out <= register1_q_net_x3;
tbt_poly_x0 <= tbt_poly_event_s_data_chanid_incorrect_net_x0;
tddm_tbt <= down_sample1_q_net_x4;
tddm_tbt_x0 <= down_sample2_q_net_x4;
tddm_tbt_x1 <= down_sample1_q_net_x5;
tddm_tbt_x2 <= down_sample2_q_net_x5;
valid_out <= register6_q_net_x1;
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register1_q_net_x3
);
register2: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q(0) => register2_q_net_x4
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d => reinterpret1_output_port_net,
en(0) => tbt_poly_m_axis_data_tvalid_net,
rst => "0",
q => register3_q_net_x2
);
register6: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_35_sg_x16,
clk => clk_35_sg_x16,
d(0) => tbt_poly_m_axis_data_tvalid_net,
en => "1",
rst => "0",
q(0) => register6_q_net_x1
);
reinterpret: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path1_net,
output_port => reinterpret_output_port_net
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => tbt_poly_m_axis_data_tdata_path0_net,
output_port => reinterpret1_output_port_net
);
tbt_poly: entity work.xlfir_compiler_dadbc7b58cb62c04fef420f4c58ee0d3
port map (
ce => ce_1_sg_x30,
ce_35 => ce_35_sg_x16,
ce_logic_1 => ce_logic_1_sg_x14,
clk => clk_1_sg_x30,
clk_35 => clk_35_sg_x16,
clk_logic_1 => clk_1_sg_x30,
s_axis_data_tdata_path0 => register4_q_net_x12,
s_axis_data_tdata_path1 => register5_q_net_x12,
s_axis_data_tuser_chanid(0) => register3_q_net_x13,
src_ce => ce_1_sg_x30,
src_clk => clk_1_sg_x30,
event_s_data_chanid_incorrect => tbt_poly_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata_path0 => tbt_poly_m_axis_data_tdata_path0_net,
m_axis_data_tdata_path1 => tbt_poly_m_axis_data_tdata_path1_net,
m_axis_data_tuser_chanid(0) => tbt_poly_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => tbt_poly_m_axis_data_tvalid_net
);
tddm_tbt_1f4b61e651: entity work.tddm_tbt_entity_1f4b61e651
port map (
ce_35 => ce_35_sg_x16,
ce_70 => ce_70_sg_x20,
clk_35 => clk_35_sg_x16,
clk_70 => clk_70_sg_x20,
tbt_ch_in => register2_q_net_x4,
tbt_i_in => reinterpret_output_port_net_x4,
tbt_q_in => reinterpret_output_port_net_x3,
poly35_ch2_i_out => down_sample2_q_net_x4,
poly35_ch2_q_out => down_sample2_q_net_x5,
poly35_ch3_i_out => down_sample1_q_net_x4,
poly35_ch3_q_out => down_sample1_q_net_x5
);
trunc1_c3e3bdeec5: entity work.trunc_entity_e5eda8a5ac
port map (
din => register3_q_net_x2,
dout => reinterpret_output_port_net_x4
);
trunc_6a2a4db298: entity work.trunc_entity_e5eda8a5ac
port map (
din => register1_q_net_x3,
dout => reinterpret_output_port_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TBT_amp1"
entity tbt_amp1_entity_6e98f85f9f is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in: in std_logic_vector(23 downto 0);
q_in: in std_logic_vector(23 downto 0);
amp_out: out std_logic_vector(23 downto 0);
ch_out: out std_logic;
tbt_cordic: out std_logic_vector(23 downto 0);
tbt_cordic_x0: out std_logic_vector(23 downto 0);
tbt_cordic_x1: out std_logic_vector(23 downto 0);
tbt_cordic_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim: out std_logic;
tbt_poly_decim_x0: out std_logic_vector(23 downto 0);
tbt_poly_decim_x1: out std_logic_vector(23 downto 0);
tbt_poly_decim_x2: out std_logic_vector(23 downto 0);
tbt_poly_decim_x3: out std_logic_vector(23 downto 0)
);
end tbt_amp1_entity_6e98f85f9f;
architecture structural of tbt_amp1_entity_6e98f85f9f is
signal ce_1_sg_x31: std_logic;
signal ce_35_sg_x17: std_logic;
signal ce_70_sg_x21: std_logic;
signal ce_logic_1_sg_x15: std_logic;
signal clk_1_sg_x31: std_logic;
signal clk_35_sg_x17: std_logic;
signal clk_70_sg_x21: std_logic;
signal down_sample1_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x9: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x10: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x11: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x8: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x9: std_logic_vector(23 downto 0);
signal p_amp_out_x3: std_logic_vector(23 downto 0);
signal p_ch_out_x4: std_logic;
signal register1_q_net_x3: std_logic_vector(24 downto 0);
signal register2_q_net_x4: std_logic;
signal register3_q_net_x14: std_logic;
signal register3_q_net_x2: std_logic_vector(24 downto 0);
signal register4_q_net_x13: std_logic_vector(23 downto 0);
signal register5_q_net_x13: std_logic_vector(23 downto 0);
signal register6_q_net_x1: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x1: std_logic;
begin
ce_1_sg_x31 <= ce_1;
ce_35_sg_x17 <= ce_35;
ce_70_sg_x21 <= ce_70;
ce_logic_1_sg_x15 <= ce_logic_1;
register3_q_net_x14 <= ch_in;
clk_1_sg_x31 <= clk_1;
clk_35_sg_x17 <= clk_35;
clk_70_sg_x21 <= clk_70;
register4_q_net_x13 <= i_in;
register5_q_net_x13 <= q_in;
amp_out <= p_amp_out_x3;
ch_out <= p_ch_out_x4;
tbt_cordic <= down_sample1_q_net_x8;
tbt_cordic_x0 <= down_sample2_q_net_x8;
tbt_cordic_x1 <= down_sample1_q_net_x9;
tbt_cordic_x2 <= down_sample2_q_net_x9;
tbt_poly_decim <= tbt_poly_event_s_data_chanid_incorrect_net_x1;
tbt_poly_decim_x0 <= down_sample1_q_net_x10;
tbt_poly_decim_x1 <= down_sample2_q_net_x10;
tbt_poly_decim_x2 <= down_sample1_q_net_x11;
tbt_poly_decim_x3 <= down_sample2_q_net_x11;
tbt_cordic_9dc3371de2: entity work.tbt_cordic_entity_9dc3371de2
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ch_in_x0 => register2_q_net_x4,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register3_q_net_x2,
q_in => register1_q_net_x3,
valid_in_x0 => register6_q_net_x1,
amp_out => p_amp_out_x3,
ch_out_x0 => p_ch_out_x4,
tddm_tbt_cordic => down_sample1_q_net_x8,
tddm_tbt_cordic_x0 => down_sample2_q_net_x8,
tddm_tbt_cordic_x1 => down_sample1_q_net_x9,
tddm_tbt_cordic_x2 => down_sample2_q_net_x9
);
tbt_poly_decim_bb6f6b5b6a: entity work.tbt_poly_decim_entity_bb6f6b5b6a
port map (
ce_1 => ce_1_sg_x31,
ce_35 => ce_35_sg_x17,
ce_70 => ce_70_sg_x21,
ce_logic_1 => ce_logic_1_sg_x15,
ch_in => register3_q_net_x14,
clk_1 => clk_1_sg_x31,
clk_35 => clk_35_sg_x17,
clk_70 => clk_70_sg_x21,
i_in => register4_q_net_x13,
q_in => register5_q_net_x13,
ch_out => register2_q_net_x4,
i_out => register3_q_net_x2,
q_out => register1_q_net_x3,
tbt_poly_x0 => tbt_poly_event_s_data_chanid_incorrect_net_x1,
tddm_tbt => down_sample1_q_net_x10,
tddm_tbt_x0 => down_sample2_q_net_x10,
tddm_tbt_x1 => down_sample1_q_net_x11,
tddm_tbt_x2 => down_sample2_q_net_x11,
valid_out => register6_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp/TDDM_tbt_amp_4ch"
entity tddm_tbt_amp_4ch_entity_9f3ac0073e is
port (
amp_in0: in std_logic_vector(23 downto 0);
amp_in1: in std_logic_vector(23 downto 0);
ce_35: in std_logic;
ce_70: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0)
);
end tddm_tbt_amp_4ch_entity_9f3ac0073e;
architecture structural of tddm_tbt_amp_4ch_entity_9f3ac0073e is
signal ce_35_sg_x20: std_logic;
signal ce_70_sg_x24: std_logic;
signal clk_35_sg_x20: std_logic;
signal clk_70_sg_x24: std_logic;
signal down_sample1_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x3: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x2: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x3: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
begin
p_amp_out_x6 <= amp_in0;
p_amp_out_x7 <= amp_in1;
ce_35_sg_x20 <= ce_35;
ce_70_sg_x24 <= ce_70;
p_ch_out_x7 <= ch_in0;
p_ch_out_x8 <= ch_in1;
clk_35_sg_x20 <= clk_35;
clk_70_sg_x24 <= clk_70;
amp_out0 <= down_sample2_q_net_x2;
amp_out1 <= down_sample1_q_net_x2;
amp_out2 <= down_sample2_q_net_x3;
amp_out3 <= down_sample1_q_net_x3;
tddm_tbt_amp0_8f2b25894a: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x7,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x6,
dout_ch0 => down_sample2_q_net_x2,
dout_ch1 => down_sample1_q_net_x2
);
tddm_tbt_amp1_0c4a2e4770: entity work.tddm_tbt_cordic_entity_5b94be40c5
port map (
ce_35 => ce_35_sg_x20,
ce_70 => ce_70_sg_x24,
ch_in => p_ch_out_x8,
clk_35 => clk_35_sg_x20,
clk_70 => clk_70_sg_x24,
din => p_amp_out_x7,
dout_ch0 => down_sample2_q_net_x3,
dout_ch1 => down_sample1_q_net_x3
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TBT_amp"
entity tbt_amp_entity_cbd277bb0c is
port (
ce_1: in std_logic;
ce_35: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ch_in0: in std_logic;
ch_in1: in std_logic;
clk_1: in std_logic;
clk_35: in std_logic;
clk_70: in std_logic;
i_in0: in std_logic_vector(23 downto 0);
i_in1: in std_logic_vector(23 downto 0);
q_in0: in std_logic_vector(23 downto 0);
q_in1: in std_logic_vector(23 downto 0);
amp_out0: out std_logic_vector(23 downto 0);
amp_out1: out std_logic_vector(23 downto 0);
amp_out2: out std_logic_vector(23 downto 0);
amp_out3: out std_logic_vector(23 downto 0);
tbt_amp0: out std_logic_vector(23 downto 0);
tbt_amp0_x0: out std_logic_vector(23 downto 0);
tbt_amp0_x1: out std_logic_vector(23 downto 0);
tbt_amp0_x2: out std_logic_vector(23 downto 0);
tbt_amp0_x3: out std_logic;
tbt_amp0_x4: out std_logic_vector(23 downto 0);
tbt_amp0_x5: out std_logic_vector(23 downto 0);
tbt_amp0_x6: out std_logic_vector(23 downto 0);
tbt_amp0_x7: out std_logic_vector(23 downto 0);
tbt_amp1: out std_logic_vector(23 downto 0);
tbt_amp1_x0: out std_logic_vector(23 downto 0);
tbt_amp1_x1: out std_logic_vector(23 downto 0);
tbt_amp1_x2: out std_logic_vector(23 downto 0);
tbt_amp1_x3: out std_logic;
tbt_amp1_x4: out std_logic_vector(23 downto 0);
tbt_amp1_x5: out std_logic_vector(23 downto 0);
tbt_amp1_x6: out std_logic_vector(23 downto 0);
tbt_amp1_x7: out std_logic_vector(23 downto 0)
);
end tbt_amp_entity_cbd277bb0c;
architecture structural of tbt_amp_entity_cbd277bb0c is
signal ce_1_sg_x32: std_logic;
signal ce_35_sg_x21: std_logic;
signal ce_70_sg_x25: std_logic;
signal ce_logic_1_sg_x16: std_logic;
signal clk_1_sg_x32: std_logic;
signal clk_35_sg_x21: std_logic;
signal clk_70_sg_x25: std_logic;
signal down_sample1_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x25: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x16: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x17: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x22: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x23: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x24: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x25: std_logic_vector(23 downto 0);
signal p_amp_out_x6: std_logic_vector(23 downto 0);
signal p_amp_out_x7: std_logic_vector(23 downto 0);
signal p_ch_out_x7: std_logic;
signal p_ch_out_x8: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal tbt_poly_event_s_data_chanid_incorrect_net_x3: std_logic;
signal tbt_poly_event_s_data_chanid_incorrect_net_x4: std_logic;
begin
ce_1_sg_x32 <= ce_1;
ce_35_sg_x21 <= ce_35;
ce_70_sg_x25 <= ce_70;
ce_logic_1_sg_x16 <= ce_logic_1;
register3_q_net_x15 <= ch_in0;
register3_q_net_x16 <= ch_in1;
clk_1_sg_x32 <= clk_1;
clk_35_sg_x21 <= clk_35;
clk_70_sg_x25 <= clk_70;
register4_q_net_x14 <= i_in0;
register4_q_net_x15 <= i_in1;
register5_q_net_x14 <= q_in0;
register5_q_net_x15 <= q_in1;
amp_out0 <= down_sample2_q_net_x24;
amp_out1 <= down_sample1_q_net_x24;
amp_out2 <= down_sample2_q_net_x25;
amp_out3 <= down_sample1_q_net_x25;
tbt_amp0 <= down_sample1_q_net_x16;
tbt_amp0_x0 <= down_sample2_q_net_x16;
tbt_amp0_x1 <= down_sample1_q_net_x17;
tbt_amp0_x2 <= down_sample2_q_net_x17;
tbt_amp0_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x3;
tbt_amp0_x4 <= down_sample1_q_net_x18;
tbt_amp0_x5 <= down_sample2_q_net_x18;
tbt_amp0_x6 <= down_sample1_q_net_x19;
tbt_amp0_x7 <= down_sample2_q_net_x19;
tbt_amp1 <= down_sample1_q_net_x20;
tbt_amp1_x0 <= down_sample2_q_net_x20;
tbt_amp1_x1 <= down_sample1_q_net_x21;
tbt_amp1_x2 <= down_sample2_q_net_x21;
tbt_amp1_x3 <= tbt_poly_event_s_data_chanid_incorrect_net_x4;
tbt_amp1_x4 <= down_sample1_q_net_x22;
tbt_amp1_x5 <= down_sample2_q_net_x22;
tbt_amp1_x6 <= down_sample1_q_net_x23;
tbt_amp1_x7 <= down_sample2_q_net_x23;
tbt_amp0_88b1c45f0e: entity work.tbt_amp0_entity_88b1c45f0e
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x15,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x14,
q_in => register5_q_net_x14,
amp_out => p_amp_out_x6,
ch_out => p_ch_out_x7,
tbt_cordic => down_sample1_q_net_x16,
tbt_cordic_x0 => down_sample2_q_net_x16,
tbt_cordic_x1 => down_sample1_q_net_x17,
tbt_cordic_x2 => down_sample2_q_net_x17,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x3,
tbt_poly_decim_x0 => down_sample1_q_net_x18,
tbt_poly_decim_x1 => down_sample2_q_net_x18,
tbt_poly_decim_x2 => down_sample1_q_net_x19,
tbt_poly_decim_x3 => down_sample2_q_net_x19
);
tbt_amp1_6e98f85f9f: entity work.tbt_amp1_entity_6e98f85f9f
port map (
ce_1 => ce_1_sg_x32,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ce_logic_1 => ce_logic_1_sg_x16,
ch_in => register3_q_net_x16,
clk_1 => clk_1_sg_x32,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
i_in => register4_q_net_x15,
q_in => register5_q_net_x15,
amp_out => p_amp_out_x7,
ch_out => p_ch_out_x8,
tbt_cordic => down_sample1_q_net_x20,
tbt_cordic_x0 => down_sample2_q_net_x20,
tbt_cordic_x1 => down_sample1_q_net_x21,
tbt_cordic_x2 => down_sample2_q_net_x21,
tbt_poly_decim => tbt_poly_event_s_data_chanid_incorrect_net_x4,
tbt_poly_decim_x0 => down_sample1_q_net_x22,
tbt_poly_decim_x1 => down_sample2_q_net_x22,
tbt_poly_decim_x2 => down_sample1_q_net_x23,
tbt_poly_decim_x3 => down_sample2_q_net_x23
);
tddm_tbt_amp_4ch_9f3ac0073e: entity work.tddm_tbt_amp_4ch_entity_9f3ac0073e
port map (
amp_in0 => p_amp_out_x6,
amp_in1 => p_amp_out_x7,
ce_35 => ce_35_sg_x21,
ce_70 => ce_70_sg_x25,
ch_in0 => p_ch_out_x7,
ch_in1 => p_ch_out_x8,
clk_35 => clk_35_sg_x21,
clk_70 => clk_70_sg_x25,
amp_out0 => down_sample2_q_net_x24,
amp_out1 => down_sample1_q_net_x24,
amp_out2 => down_sample2_q_net_x25,
amp_out3 => down_sample1_q_net_x25
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix/TDM_mix_ch0_1"
entity tdm_mix_ch0_1_entity_b9bb73dd5f is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic;
dout: out std_logic_vector(23 downto 0)
);
end tdm_mix_ch0_1_entity_b9bb73dd5f;
architecture structural of tdm_mix_ch0_1_entity_b9bb73dd5f is
signal ce_1_sg_x33: std_logic;
signal ce_2_sg_x31: std_logic;
signal ce_logic_1_sg_x17: std_logic;
signal clk_1_sg_x33: std_logic;
signal clk_2_sg_x31: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal mux_sel1_op_net: std_logic;
signal mux_y_net: std_logic_vector(23 downto 0);
signal register1_q_net_x4: std_logic;
signal register_q_net_x17: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x8: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x9: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x33 <= ce_1;
ce_2_sg_x31 <= ce_2;
ce_logic_1_sg_x17 <= ce_logic_1;
clk_1_sg_x33 <= clk_1;
clk_2_sg_x31 <= clk_2;
reinterpret2_output_port_net_x9 <= din_ch0;
reinterpret2_output_port_net_x8 <= din_ch1;
constant10_op_net_x0 <= rst;
ch_out <= register1_q_net_x4;
dout <= register_q_net_x17;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_1_sg_x17,
clk => clk_1_sg_x33,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
mux: entity work.mux_a2121d82da
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
sel(0) => mux_sel1_op_net,
y => mux_y_net
);
mux_sel1: entity work.counter_41314d726b
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op(0) => mux_sel1_op_net
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d(0) => mux_sel1_op_net,
en => "1",
rst => "0",
q(0) => register1_q_net_x4
);
register_x0: entity work.xlregister
generic map (
d_width => 24,
init_value => b"000000000000000000000000"
)
port map (
ce => ce_1_sg_x33,
clk => clk_1_sg_x33,
d => mux_y_net,
en => "1",
rst => "0",
q => register_q_net_x17
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x9,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => reinterpret2_output_port_net_x8,
dest_ce => ce_1_sg_x33,
dest_clk => clk_1_sg_x33,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x31,
src_clk => clk_2_sg_x31,
src_clr => '0',
q => up_sample_ch1_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_mix"
entity tdm_mix_entity_54ce67e6e8 is
port (
ce_1: in std_logic;
ce_2: in std_logic;
ce_logic_1: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
ch_out0: out std_logic;
ch_out1: out std_logic;
dout0: out std_logic_vector(23 downto 0);
dout1: out std_logic_vector(23 downto 0)
);
end tdm_mix_entity_54ce67e6e8;
architecture structural of tdm_mix_entity_54ce67e6e8 is
signal ce_1_sg_x35: std_logic;
signal ce_2_sg_x33: std_logic;
signal ce_logic_1_sg_x19: std_logic;
signal clk_1_sg_x35: std_logic;
signal clk_2_sg_x33: std_logic;
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register_q_net_x19: std_logic_vector(23 downto 0);
signal register_q_net_x20: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x11: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x12: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x13: std_logic_vector(23 downto 0);
signal reinterpret2_output_port_net_x14: std_logic_vector(23 downto 0);
begin
ce_1_sg_x35 <= ce_1;
ce_2_sg_x33 <= ce_2;
ce_logic_1_sg_x19 <= ce_logic_1;
clk_1_sg_x35 <= clk_1;
clk_2_sg_x33 <= clk_2;
reinterpret2_output_port_net_x14 <= din_ch0;
reinterpret2_output_port_net_x11 <= din_ch1;
reinterpret2_output_port_net_x12 <= din_ch2;
reinterpret2_output_port_net_x13 <= din_ch3;
ch_out0 <= register1_q_net_x6;
ch_out1 <= register1_q_net_x7;
dout0 <= register_q_net_x19;
dout1 <= register_q_net_x20;
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
tdm_mix_ch0_1_b9bb73dd5f: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x14,
din_ch1 => reinterpret2_output_port_net_x11,
rst => constant10_op_net_x0,
ch_out => register1_q_net_x6,
dout => register_q_net_x19
);
tdm_mix_ch0_2_e9327141fc: entity work.tdm_mix_ch0_1_entity_b9bb73dd5f
port map (
ce_1 => ce_1_sg_x35,
ce_2 => ce_2_sg_x33,
ce_logic_1 => ce_logic_1_sg_x19,
clk_1 => clk_1_sg_x35,
clk_2 => clk_2_sg_x33,
din_ch0 => reinterpret2_output_port_net_x12,
din_ch1 => reinterpret2_output_port_net_x13,
rst => constant11_op_net_x0,
ch_out => register1_q_net_x7,
dout => register_q_net_x20
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit"
entity tdm_monit_entity_6e38292ecb is
port (
ce_1: in std_logic;
ce_2240: in std_logic;
ce_560: in std_logic;
ce_logic_560: in std_logic;
clk_1: in std_logic;
clk_2240: in std_logic;
clk_560: in std_logic;
din_ch0: in std_logic_vector(23 downto 0);
din_ch1: in std_logic_vector(23 downto 0);
din_ch2: in std_logic_vector(23 downto 0);
din_ch3: in std_logic_vector(23 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(23 downto 0)
);
end tdm_monit_entity_6e38292ecb;
architecture structural of tdm_monit_entity_6e38292ecb is
signal ce_1_sg_x36: std_logic;
signal ce_2240_sg_x26: std_logic;
signal ce_560_sg_x2: std_logic;
signal ce_logic_560_sg_x2: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal clk_1_sg_x36: std_logic;
signal clk_2240_sg_x26: std_logic;
signal clk_560_sg_x2: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal constant10_op_net_x0: std_logic;
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x19: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x18: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x19: std_logic_vector(23 downto 0);
signal mux_sel_op_net: std_logic_vector(1 downto 0);
signal mux_y_net: std_logic_vector(23 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(23 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(23 downto 0);
begin
ce_1_sg_x36 <= ce_1;
ce_2240_sg_x26 <= ce_2240;
ce_560_sg_x2 <= ce_560;
ce_logic_560_sg_x2 <= ce_logic_560;
clk_1_sg_x36 <= clk_1;
clk_2240_sg_x26 <= clk_2240;
clk_560_sg_x2 <= clk_560;
down_sample2_q_net_x18 <= din_ch0;
down_sample1_q_net_x18 <= din_ch1;
down_sample2_q_net_x19 <= din_ch2;
down_sample1_q_net_x19 <= din_ch3;
constant10_op_net_x0 <= rst;
ch_out <= ch_out_x2;
dout <= dout_x2;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 24,
q_width => 1
)
port map (
ce => ce_logic_560_sg_x2,
clk => clk_560_sg_x2,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => ch_out_x2
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
ds_ratio => 560,
latency => 1,
phase => 559,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => mux_y_net,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x36,
src_clk => clk_1_sg_x36,
src_clr => '0',
q => dout_x2
);
mux: entity work.mux_f062741975
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net,
y => mux_y_net
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3166d4cc5b09c744",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x36,
clk => clk_1_sg_x36,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant10_op_net_x0,
op => mux_sel_op_net
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x18,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample2_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 24,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 24
)
port map (
d => down_sample1_q_net_x19,
dest_ce => ce_560_sg_x2,
dest_clk => clk_560_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x26,
src_clk => clk_2240_sg_x26,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample"
entity downsample_entity_f33f90217c is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(1 downto 0);
dout: out std_logic_vector(1 downto 0)
);
end downsample_entity_f33f90217c;
architecture structural of downsample_entity_f33f90217c is
signal ce_1_sg_x37: std_logic;
signal ce_2500_sg_x0: std_logic;
signal ce_5600000_sg_x8: std_logic;
signal clk_1_sg_x37: std_logic;
signal clk_2500_sg_x0: std_logic;
signal clk_5600000_sg_x8: std_logic;
signal down_sample5_q_net: std_logic_vector(1 downto 0);
signal down_sample_q_net_x0: std_logic_vector(1 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
begin
ce_1_sg_x37 <= ce_1;
ce_2500_sg_x0 <= ce_2500;
ce_5600000_sg_x8 <= ce_5600000;
clk_1_sg_x37 <= clk_1;
clk_2500_sg_x0 <= clk_2500;
clk_5600000_sg_x8 <= clk_5600000;
mux_sel_op_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x8,
dest_clk => clk_5600000_sg_x8,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x0,
src_clk => clk_2500_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 2,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 2
)
port map (
d => mux_sel_op_net_x0,
dest_ce => ce_2500_sg_x0,
dest_clk => clk_2500_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x37,
src_clk => clk_1_sg_x37,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1/downsample1"
entity downsample1_entity_312d531c6b is
port (
ce_1: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
clk_1: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample1_entity_312d531c6b;
architecture structural of downsample1_entity_312d531c6b is
signal ce_1_sg_x38: std_logic;
signal ce_2500_sg_x1: std_logic;
signal ce_5600000_sg_x9: std_logic;
signal clk_1_sg_x38: std_logic;
signal clk_2500_sg_x1: std_logic;
signal clk_5600000_sg_x9: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
begin
ce_1_sg_x38 <= ce_1;
ce_2500_sg_x1 <= ce_2500;
ce_5600000_sg_x9 <= ce_5600000;
clk_1_sg_x38 <= clk_1;
clk_2500_sg_x1 <= clk_2500;
clk_5600000_sg_x9 <= clk_5600000;
mux_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_5600000_sg_x9,
dest_clk => clk_5600000_sg_x9,
dest_clr => '0',
en => "1",
src_ce => ce_2500_sg_x1,
src_clk => clk_2500_sg_x1,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 2500,
latency => 1,
phase => 2499,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => mux_y_net_x0,
dest_ce => ce_2500_sg_x1,
dest_clk => clk_2500_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x38,
src_clk => clk_1_sg_x38,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/TDM_monit_1"
entity tdm_monit_1_entity_746ecf54b0 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_2500: in std_logic;
ce_5600000: in std_logic;
ce_logic_5600000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_2500: in std_logic;
clk_5600000: in std_logic;
din_ch0: in std_logic_vector(25 downto 0);
din_ch1: in std_logic_vector(25 downto 0);
din_ch2: in std_logic_vector(25 downto 0);
din_ch3: in std_logic_vector(25 downto 0);
rst: in std_logic;
ch_out: out std_logic_vector(1 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end tdm_monit_1_entity_746ecf54b0;
architecture structural of tdm_monit_1_entity_746ecf54b0 is
signal ce_1_sg_x39: std_logic;
signal ce_22400000_sg_x10: std_logic;
signal ce_2500_sg_x2: std_logic;
signal ce_5600000_sg_x10: std_logic;
signal ce_logic_5600000_sg_x0: std_logic;
signal clk_1_sg_x39: std_logic;
signal clk_22400000_sg_x10: std_logic;
signal clk_2500_sg_x2: std_logic;
signal clk_5600000_sg_x10: std_logic;
signal clock_enable_probe_q_net: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant11_op_net_x0: std_logic;
signal down_sample_q_net_x2: std_logic_vector(1 downto 0);
signal down_sample_q_net_x3: std_logic_vector(25 downto 0);
signal mux_sel_op_net_x0: std_logic_vector(1 downto 0);
signal mux_y_net_x0: std_logic_vector(25 downto 0);
signal up_sample_ch0_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch1_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch2_q_net: std_logic_vector(25 downto 0);
signal up_sample_ch3_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x39 <= ce_1;
ce_22400000_sg_x10 <= ce_22400000;
ce_2500_sg_x2 <= ce_2500;
ce_5600000_sg_x10 <= ce_5600000;
ce_logic_5600000_sg_x0 <= ce_logic_5600000;
clk_1_sg_x39 <= clk_1;
clk_22400000_sg_x10 <= clk_22400000;
clk_2500_sg_x2 <= clk_2500;
clk_5600000_sg_x10 <= clk_5600000;
concat_y_net_x0 <= din_ch0;
concat1_y_net_x0 <= din_ch1;
concat2_y_net_x0 <= din_ch2;
concat3_y_net_x0 <= din_ch3;
constant11_op_net_x0 <= rst;
ch_out <= down_sample_q_net_x2;
dout <= down_sample_q_net_x3;
clock_enable_probe: entity work.xlceprobe
generic map (
d_width => 26,
q_width => 1
)
port map (
ce => ce_logic_5600000_sg_x0,
clk => clk_5600000_sg_x10,
d => up_sample_ch0_q_net,
q(0) => clock_enable_probe_q_net
);
downsample1_312d531c6b: entity work.downsample1_entity_312d531c6b
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_y_net_x0,
dout => down_sample_q_net_x3
);
downsample_f33f90217c: entity work.downsample_entity_f33f90217c
port map (
ce_1 => ce_1_sg_x39,
ce_2500 => ce_2500_sg_x2,
ce_5600000 => ce_5600000_sg_x10,
clk_1 => clk_1_sg_x39,
clk_2500 => clk_2500_sg_x2,
clk_5600000 => clk_5600000_sg_x10,
din => mux_sel_op_net_x0,
dout => down_sample_q_net_x2
);
mux: entity work.mux_187c900130
port map (
ce => '0',
clk => '0',
clr => '0',
d0 => up_sample_ch0_q_net,
d1 => up_sample_ch1_q_net,
d2 => up_sample_ch2_q_net,
d3 => up_sample_ch3_q_net,
sel => mux_sel_op_net_x0,
y => mux_y_net_x0
);
mux_sel: entity work.xlcounter_free
generic map (
core_name0 => "cntr_11_0_3166d4cc5b09c744",
op_arith => xlUnsigned,
op_width => 2
)
port map (
ce => ce_1_sg_x39,
clk => clk_1_sg_x39,
clr => '0',
en(0) => clock_enable_probe_q_net,
rst(0) => constant11_op_net_x0,
op => mux_sel_op_net_x0
);
up_sample_ch0: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch0_q_net
);
up_sample_ch1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat1_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch1_q_net
);
up_sample_ch2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat2_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch2_q_net
);
up_sample_ch3: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => concat3_y_net_x0,
dest_ce => ce_5600000_sg_x10,
dest_clk => clk_5600000_sg_x10,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x10,
src_clk => clk_22400000_sg_x10,
src_clr => '0',
q => up_sample_ch3_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/convert_filt"
entity convert_filt_entity_fda412c1bf is
port (
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end convert_filt_entity_fda412c1bf;
architecture structural of convert_filt_entity_fda412c1bf is
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x0: std_logic_vector(24 downto 0);
begin
down_sample_q_net_x4 <= din;
dout <= reinterpret5_output_port_net_x0;
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample_q_net_x4,
dout => extractor1_dout_net
);
reinterpret5: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret5_output_port_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En"
entity datareg_en_entity_79473f9ed1 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en_entity_79473f9ed1;
architecture structural of datareg_en_entity_79473f9ed1 is
signal ce_1_sg_x40: std_logic;
signal clk_1_sg_x40: std_logic;
signal divider_dout_valid_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x40 <= ce_1;
clk_1_sg_x40 <= clk_1;
reinterpret1_output_port_net_x0 <= din;
divider_dout_valid_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d(0) => divider_dout_valid_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x40,
clk => clk_1_sg_x40,
d => reinterpret1_output_port_net_x0,
en(0) => divider_dout_valid_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/DataReg_En3"
entity datareg_en3_entity_6643090018 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
din: in std_logic_vector(24 downto 0);
en: in std_logic;
dout: out std_logic_vector(24 downto 0);
valid: out std_logic
);
end datareg_en3_entity_6643090018;
architecture structural of datareg_en3_entity_6643090018 is
signal ce_1_sg_x43: std_logic;
signal clk_1_sg_x43: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal delay1_q_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x43 <= ce_1;
clk_1_sg_x43 <= clk_1;
convert_dout_net_x0 <= din;
delay1_q_net_x0 <= en;
dout <= register_q_net_x0;
valid <= register1_q_net_x0;
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d(0) => delay1_q_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x43,
clk => clk_1_sg_x43,
d => convert_dout_net_x0,
en(0) => delay1_q_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb/pulse_stretcher"
entity pulse_stretcher_entity_9893378b63 is
port (
ce_1: in std_logic;
clk_1: in std_logic;
clr: in std_logic;
pulse_in: in std_logic;
extd_out: out std_logic
);
end pulse_stretcher_entity_9893378b63;
architecture structural of pulse_stretcher_entity_9893378b63 is
signal ce_1_sg_x44: std_logic;
signal ce_70_x0: std_logic;
signal clk_1_sg_x44: std_logic;
signal inverter_op_net: std_logic;
signal logical1_y_net: std_logic;
signal logical2_y_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal register1_q_net_x1: std_logic;
signal register_q_net: std_logic;
begin
ce_1_sg_x44 <= ce_1;
clk_1_sg_x44 <= clk_1;
ce_70_x0 <= clr;
register1_q_net_x1 <= pulse_in;
extd_out <= logical3_y_net_x0;
inverter: entity work.inverter_e5b38cca3b
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
clr => '0',
ip(0) => ce_70_x0,
op(0) => inverter_op_net
);
logical1: entity work.logical_80f90b97d0
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register_q_net,
d1(0) => inverter_op_net,
y(0) => logical1_y_net
);
logical2: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => logical1_y_net,
y(0) => logical2_y_net
);
logical3: entity work.logical_aacf6e1b0e
port map (
ce => '0',
clk => '0',
clr => '0',
d0(0) => register1_q_net_x1,
d1(0) => register_q_net,
y(0) => logical3_y_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_1_sg_x44,
clk => clk_1_sg_x44,
d(0) => logical2_y_net,
en => "1",
rst => "0",
q(0) => register_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_fofb"
entity delta_sigma_fofb_entity_ee61e649ea is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_logic_2240: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_fofb_entity_ee61e649ea;
architecture structural of delta_sigma_fofb_entity_ee61e649ea is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x52: std_logic;
signal ce_2240_sg_x27: std_logic;
signal ce_2_sg_x34: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_2240_sg_x0: std_logic;
signal clk_1_sg_x52: std_logic;
signal clk_2240_sg_x27: std_logic;
signal clk_2_sg_x34: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_fofb_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x20 <= a;
down_sample1_q_net_x20 <= b;
down_sample2_q_net_x21 <= c;
ce_1_sg_x52 <= ce_1;
ce_2_sg_x34 <= ce_2;
ce_2240_sg_x27 <= ce_2240;
ce_logic_2240_sg_x0 <= ce_logic_2240;
clk_1_sg_x52 <= clk_1;
clk_2_sg_x34 <= clk_2;
clk_2240_sg_x27 <= clk_2240;
down_sample1_q_net_x21 <= d;
del_sig_div_fofb_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample2_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x20,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x21,
b => down_sample1_q_net_x21,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_2240_sg_x0,
clk => clk_2240_sg_x27,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_3225c09afc: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_5b5f4b61b7: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_6643090018: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_79473f9ed1: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 1120,
latency => 1,
phase => 1119,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x34,
src_clk => clk_2_sg_x34,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 2240,
latency => 1,
phase => 2239,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_2240_sg_x27,
dest_clk => clk_2240_sg_x27,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x52,
src_clk => clk_1_sg_x52,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_f6401a1a3d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_38948aaba0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_816d954034: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_5d505b900f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_bee4540339: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_f82d879b1c: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_2406c4a105: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_9893378b63: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x52,
clk_1 => clk_1_sg_x52,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x34,
clk => clk_2_sg_x34,
d => del_sig_div_fofb_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_239e4f614ba09ab1",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_2240_sg_x27,
clk => clk_2240_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x52,
dest_clk => clk_1_sg_x52,
dest_clr => '0',
en => "1",
src_ce => ce_2240_sg_x27,
src_clk => clk_2240_sg_x27,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x52,
clk => clk_1_sg_x52,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample1"
entity downsample1_entity_4c88924603 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample1_entity_4c88924603;
architecture structural of downsample1_entity_4c88924603 is
signal ce_1_sg_x57: std_logic;
signal ce_22400000_sg_x11: std_logic;
signal ce_5000_sg_x0: std_logic;
signal clk_1_sg_x57: std_logic;
signal clk_22400000_sg_x11: std_logic;
signal clk_5000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x57 <= ce_1;
ce_22400000_sg_x11 <= ce_22400000;
ce_5000_sg_x0 <= ce_5000;
clk_1_sg_x57 <= clk_1;
clk_22400000_sg_x11 <= clk_22400000;
clk_5000_sg_x0 <= clk_5000;
register13_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x11,
dest_clk => clk_22400000_sg_x11,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x0,
src_clk => clk_5000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net_x0,
dest_ce => ce_5000_sg_x0,
dest_clk => clk_5000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x57,
src_clk => clk_1_sg_x57,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample2"
entity downsample2_entity_891f07b1a7 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic;
dout: out std_logic
);
end downsample2_entity_891f07b1a7;
architecture structural of downsample2_entity_891f07b1a7 is
signal ce_1_sg_x58: std_logic;
signal ce_22400000_sg_x12: std_logic;
signal ce_5000_sg_x1: std_logic;
signal clk_1_sg_x58: std_logic;
signal clk_22400000_sg_x12: std_logic;
signal clk_5000_sg_x1: std_logic;
signal down_sample5_q_net: std_logic;
signal down_sample_q_net_x0: std_logic;
signal logical3_y_net_x0: std_logic;
begin
ce_1_sg_x58 <= ce_1;
ce_22400000_sg_x12 <= ce_22400000;
ce_5000_sg_x1 <= ce_5000;
clk_1_sg_x58 <= clk_1;
clk_22400000_sg_x12 <= clk_22400000;
clk_5000_sg_x1 <= clk_5000;
logical3_y_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => down_sample5_q_net,
dest_ce => ce_22400000_sg_x12,
dest_clk => clk_22400000_sg_x12,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x1,
src_clk => clk_5000_sg_x1,
src_clr => '0',
q(0) => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_5000_sg_x1,
dest_clk => clk_5000_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x58,
src_clk => clk_1_sg_x58,
src_clr => '0',
q(0) => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample3"
entity downsample3_entity_dba589aaee is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_5000: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_5000: in std_logic;
din: in std_logic_vector(24 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end downsample3_entity_dba589aaee;
architecture structural of downsample3_entity_dba589aaee is
signal ce_1_sg_x59: std_logic;
signal ce_22400000_sg_x13: std_logic;
signal ce_5000_sg_x2: std_logic;
signal clk_1_sg_x59: std_logic;
signal clk_22400000_sg_x13: std_logic;
signal clk_5000_sg_x2: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_1_sg_x59 <= ce_1;
ce_22400000_sg_x13 <= ce_22400000;
ce_5000_sg_x2 <= ce_5000;
clk_1_sg_x59 <= clk_1;
clk_22400000_sg_x13 <= clk_22400000;
clk_5000_sg_x2 <= clk_5000;
register12_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => down_sample5_q_net,
dest_ce => ce_22400000_sg_x13,
dest_clk => clk_22400000_sg_x13,
dest_clr => '0',
en => "1",
src_ce => ce_5000_sg_x2,
src_clk => clk_5000_sg_x2,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net_x0,
dest_ce => ce_5000_sg_x2,
dest_clk => clk_5000_sg_x2,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x59,
src_clk => clk_1_sg_x59,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/downsample7"
entity downsample7_entity_b85055cb62 is
port (
ce_10000: in std_logic;
ce_2: in std_logic;
ce_44800000: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_44800000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end downsample7_entity_b85055cb62;
architecture structural of downsample7_entity_b85055cb62 is
signal ce_10000_sg_x0: std_logic;
signal ce_2_sg_x35: std_logic;
signal ce_44800000_sg_x0: std_logic;
signal clk_10000_sg_x0: std_logic;
signal clk_2_sg_x35: std_logic;
signal clk_44800000_sg_x0: std_logic;
signal down_sample5_q_net: std_logic_vector(25 downto 0);
signal down_sample_q_net_x0: std_logic_vector(25 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
begin
ce_10000_sg_x0 <= ce_10000;
ce_2_sg_x35 <= ce_2;
ce_44800000_sg_x0 <= ce_44800000;
clk_10000_sg_x0 <= clk_10000;
clk_2_sg_x35 <= clk_2;
clk_44800000_sg_x0 <= clk_44800000;
register14_q_net_x0 <= din;
dout <= down_sample_q_net_x0;
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 4480,
latency => 1,
phase => 4479,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => down_sample5_q_net,
dest_ce => ce_44800000_sg_x0,
dest_clk => clk_44800000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_10000_sg_x0,
src_clk => clk_10000_sg_x0,
src_clr => '0',
q => down_sample_q_net_x0
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 5000,
latency => 1,
phase => 4999,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net_x0,
dest_ce => ce_10000_sg_x0,
dest_clk => clk_10000_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x35,
src_clk => clk_2_sg_x35,
src_clr => '0',
q => down_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad"
entity upsample_copy_pad_entity_86c97eac4f is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad_entity_86c97eac4f;
architecture structural of upsample_copy_pad_entity_86c97eac4f is
signal ce_1_sg_x73: std_logic;
signal ce_22400000_sg_x19: std_logic;
signal ce_4480_sg_x0: std_logic;
signal clk_1_sg_x73: std_logic;
signal clk_22400000_sg_x19: std_logic;
signal clk_4480_sg_x0: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x73 <= ce_1;
ce_22400000_sg_x19 <= ce_22400000;
ce_4480_sg_x0 <= ce_4480;
clk_1_sg_x73 <= clk_1;
clk_22400000_sg_x19 <= clk_22400000;
clk_4480_sg_x0 <= clk_4480;
register10_q_net_x0 <= din;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x73,
dest_clk => clk_1_sg_x73,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x0,
src_clk => clk_4480_sg_x0,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net_x0,
dest_ce => ce_4480_sg_x0,
dest_clk => clk_4480_sg_x0,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x19,
src_clk => clk_22400000_sg_x19,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_copy_pad1"
entity upsample_copy_pad1_entity_edde199d79 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din_x0: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(25 downto 0)
);
end upsample_copy_pad1_entity_edde199d79;
architecture structural of upsample_copy_pad1_entity_edde199d79 is
signal ce_1_sg_x74: std_logic;
signal ce_22400000_sg_x20: std_logic;
signal ce_4480_sg_x1: std_logic;
signal clk_1_sg_x74: std_logic;
signal clk_22400000_sg_x20: std_logic;
signal clk_4480_sg_x1: std_logic;
signal din_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample5_q_net: std_logic_vector(25 downto 0);
begin
ce_1_sg_x74 <= ce_1;
ce_22400000_sg_x20 <= ce_22400000;
ce_4480_sg_x1 <= ce_4480;
clk_1_sg_x74 <= clk_1;
clk_22400000_sg_x20 <= clk_22400000;
clk_4480_sg_x1 <= clk_4480;
din_x1 <= din_x0;
dout <= up_sample1_q_net_x0;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => up_sample5_q_net,
dest_ce => ce_1_sg_x74,
dest_clk => clk_1_sg_x74,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x1,
src_clk => clk_4480_sg_x1,
src_clr => '0',
q => up_sample1_q_net_x0
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din_x1,
dest_ce => ce_4480_sg_x1,
dest_clk => clk_4480_sg_x1,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x20,
src_clk => clk_22400000_sg_x20,
src_clr => '0',
q => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit/upsample_zero_pad"
entity upsample_zero_pad_entity_e334b63be9 is
port (
ce_1: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
clk_1: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
din: in std_logic;
dout: out std_logic
);
end upsample_zero_pad_entity_e334b63be9;
architecture structural of upsample_zero_pad_entity_e334b63be9 is
signal assert13_dout_net_x0: std_logic;
signal ce_1_sg_x77: std_logic;
signal ce_22400000_sg_x23: std_logic;
signal ce_4480_sg_x4: std_logic;
signal clk_1_sg_x77: std_logic;
signal clk_22400000_sg_x23: std_logic;
signal clk_4480_sg_x4: std_logic;
signal up_sample1_q_net_x1: std_logic;
signal up_sample5_q_net: std_logic;
begin
ce_1_sg_x77 <= ce_1;
ce_22400000_sg_x23 <= ce_22400000;
ce_4480_sg_x4 <= ce_4480;
clk_1_sg_x77 <= clk_1;
clk_22400000_sg_x23 <= clk_22400000;
clk_4480_sg_x4 <= clk_4480;
assert13_dout_net_x0 <= din;
dout <= up_sample1_q_net_x1;
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => up_sample5_q_net,
dest_ce => ce_1_sg_x77,
dest_clk => clk_1_sg_x77,
dest_clr => '0',
en => "1",
src_ce => ce_4480_sg_x4,
src_clk => clk_4480_sg_x4,
src_clr => '0',
q(0) => up_sample1_q_net_x1
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert13_dout_net_x0,
dest_ce => ce_4480_sg_x4,
dest_clk => clk_4480_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_22400000_sg_x23,
src_clk => clk_22400000_sg_x23,
src_clr => '0',
q(0) => up_sample5_q_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_monit"
entity delta_sigma_monit_entity_a8f8b81626 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_2: in std_logic;
ce_22400000: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_logic_22400000: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_2: in std_logic;
clk_22400000: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_monit_entity_a8f8b81626;
architecture structural of delta_sigma_monit_entity_a8f8b81626 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert13_dout_net_x3: std_logic;
signal assert2_dout_net_x0: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert9_dout_net_x1: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_10000_sg_x1: std_logic;
signal ce_1_sg_x81: std_logic;
signal ce_22400000_sg_x27: std_logic;
signal ce_2_sg_x36: std_logic;
signal ce_44800000_sg_x1: std_logic;
signal ce_4480_sg_x8: std_logic;
signal ce_5000_sg_x8: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_22400000_sg_x0: std_logic;
signal clk_10000_sg_x1: std_logic;
signal clk_1_sg_x81: std_logic;
signal clk_22400000_sg_x27: std_logic;
signal clk_2_sg_x36: std_logic;
signal clk_44800000_sg_x1: std_logic;
signal clk_4480_sg_x8: std_logic;
signal clk_5000_sg_x8: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_monit_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din_x1: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch_x0: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x0: std_logic_vector(24 downto 0);
signal down_sample_q_net_x1: std_logic;
signal down_sample_q_net_x2: std_logic_vector(24 downto 0);
signal down_sample_q_net_x3: std_logic;
signal down_sample_q_net_x4: std_logic_vector(24 downto 0);
signal down_sample_q_net_x5: std_logic;
signal down_sample_q_net_x6: std_logic_vector(25 downto 0);
signal down_sample_q_net_x7: std_logic_vector(24 downto 0);
signal down_sample_q_net_x8: std_logic;
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net_x0: std_logic_vector(25 downto 0);
signal register11_q_net_x0: std_logic_vector(24 downto 0);
signal register12_q_net_x0: std_logic_vector(24 downto 0);
signal register13_q_net_x0: std_logic_vector(24 downto 0);
signal register14_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x2: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x3: std_logic_vector(25 downto 0);
signal up_sample1_q_net_x4: std_logic;
signal up_sample1_q_net_x5: std_logic;
signal up_sample1_q_net_x6: std_logic;
signal up_sample1_q_net_x7: std_logic;
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x5 <= a;
down_sample1_q_net_x5 <= b;
down_sample3_q_net_x5 <= c;
ce_1_sg_x81 <= ce_1;
ce_10000_sg_x1 <= ce_10000;
ce_2_sg_x36 <= ce_2;
ce_22400000_sg_x27 <= ce_22400000;
ce_4480_sg_x8 <= ce_4480;
ce_44800000_sg_x1 <= ce_44800000;
ce_5000_sg_x8 <= ce_5000;
ce_logic_22400000_sg_x0 <= ce_logic_22400000;
clk_1_sg_x81 <= clk_1;
clk_10000_sg_x1 <= clk_10000;
clk_2_sg_x36 <= clk_2;
clk_22400000_sg_x27 <= clk_22400000;
clk_4480_sg_x8 <= clk_4480;
clk_44800000_sg_x1 <= clk_44800000;
clk_5000_sg_x8 <= clk_5000;
down_sample4_q_net_x5 <= d;
del_sig_div_monit_thres_i_net_x0 <= ds_thres;
q <= assert4_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert10_dout_net_x1;
sum_x0 <= assert5_dout_net_x1;
x <= assert11_dout_net_x1;
x_valid <= assert12_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x1,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x2,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x3,
dout(0) => assert12_dout_net_x1
);
assert13: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert13_dout_net_x3
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert2_dout_net_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x7,
dout => assert4_dout_net_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x0,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample_q_net_x4,
dout => dout_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x5,
dout(0) => valid_ds_down_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample_q_net_x8,
dout(0) => assert9_dout_net_x1
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample3_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample3_q_net_x5,
b => down_sample4_q_net_x5,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_22400000_sg_x0,
clk => clk_22400000_sg_x27,
d(0) => assert13_dout_net_x3,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_0658df0e73: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_b216d22f41: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_352b935ccb: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_8be792d5b9: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d(0) => logical3_y_net_x0,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => delta_y_s_net
);
downsample1_4c88924603: entity work.downsample1_entity_4c88924603
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register13_q_net_x0,
dout => down_sample_q_net_x0
);
downsample2_891f07b1a7: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x4,
dout => down_sample_q_net_x1
);
downsample3_dba589aaee: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register12_q_net_x0,
dout => down_sample_q_net_x2
);
downsample4_c9912c17cb: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x3,
dout => down_sample_q_net_x3
);
downsample5_5d411d5dea: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => dout_stretch_x0,
dout => down_sample_q_net_x4
);
downsample6_d7e68015e5: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x1,
dout => down_sample_q_net_x5
);
downsample7_b85055cb62: entity work.downsample7_entity_b85055cb62
port map (
ce_10000 => ce_10000_sg_x1,
ce_2 => ce_2_sg_x36,
ce_44800000 => ce_44800000_sg_x1,
clk_10000 => clk_10000_sg_x1,
clk_2 => clk_2_sg_x36,
clk_44800000 => clk_44800000_sg_x1,
din => register14_q_net_x0,
dout => down_sample_q_net_x6
);
downsample8_69d7284f0d: entity work.downsample3_entity_dba589aaee
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => register11_q_net_x0,
dout => down_sample_q_net_x7
);
downsample9_f5ac9b8db2: entity work.downsample2_entity_891f07b1a7
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_5000 => ce_5000_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_5000 => clk_5000_sg_x8,
din => logical3_y_net_x2,
dout => down_sample_q_net_x8
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_427f70e3c7: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x2
);
pulse_stretcher2_9a61283281: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x3
);
pulse_stretcher3_864c3e16a6: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x4
);
pulse_stretcher4_8dfd1c8928: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert6_dout_net_x0,
pulse_in => up_sample1_q_net_x6,
extd_out => logical3_y_net_x0
);
pulse_stretcher5_ac376595d0: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x0,
pulse_in => up_sample1_q_net_x5,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_694b81e6b2: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => assert2_dout_net_x0,
pulse_in => up_sample1_q_net_x4,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_bb8174efbd: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => re_x1,
pulse_in => up_sample1_q_net_x7,
extd_out => logical3_y_net_x7
);
pulse_stretcher_6bf297451d: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x81,
clk_1 => clk_1_sg_x81,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x1
);
q_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net_x0
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net_x0
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net_x0
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net_x0
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x36,
clk => clk_2_sg_x36,
d => del_sig_div_monit_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net_x0
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net_x0
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data_x0
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din_x1
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch_x0
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x3,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x2,
output_port => divisor_data
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x1,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample1_q_net_x0,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data_x0,
b => down_sample_q_net_x6,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_239e4f614ba09ab1",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_22400000_sg_x27,
clk => clk_22400000_sg_x27,
clr => '0',
en => "1",
s => sum_s_net
);
upsample_copy_pad1_edde199d79: entity work.upsample_copy_pad1_entity_edde199d79
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din_x0 => din_x1,
dout => up_sample1_q_net_x1
);
upsample_copy_pad2_46599e345b: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => divisor_data_x0,
dout => up_sample1_q_net_x2
);
upsample_copy_pad3_3571daa38f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register7_q_net_x0,
dout => up_sample1_q_net_x3
);
upsample_copy_pad_86c97eac4f: entity work.upsample_copy_pad_entity_86c97eac4f
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => register10_q_net_x0,
dout => up_sample1_q_net_x0
);
upsample_zero_pad1_2044d1ec3f: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x5
);
upsample_zero_pad2_7f2f8f8620: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x6
);
upsample_zero_pad3_f0b4acbf28: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x7
);
upsample_zero_pad_e334b63be9: entity work.upsample_zero_pad_entity_e334b63be9
port map (
ce_1 => ce_1_sg_x81,
ce_22400000 => ce_22400000_sg_x27,
ce_4480 => ce_4480_sg_x8,
clk_1 => clk_1_sg_x81,
clk_22400000 => clk_22400000_sg_x27,
clk_4480 => clk_4480_sg_x8,
din => assert13_dout_net_x3,
dout => up_sample1_q_net_x4
);
x_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x81,
clk => clk_1_sg_x81,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data,
s_axis_divisor_tvalid => logical3_y_net_x0,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/delta-sigma_tbt"
entity delta_sigma_tbt_entity_bbfa8a8a69 is
port (
a: in std_logic_vector(23 downto 0);
b: in std_logic_vector(23 downto 0);
c: in std_logic_vector(23 downto 0);
ce_1: in std_logic;
ce_2: in std_logic;
ce_70: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_2: in std_logic;
clk_70: in std_logic;
d: in std_logic_vector(23 downto 0);
ds_thres: in std_logic_vector(25 downto 0);
q: out std_logic_vector(24 downto 0);
q_valid: out std_logic;
sum_valid: out std_logic;
sum_x0: out std_logic_vector(24 downto 0);
x: out std_logic_vector(24 downto 0);
x_valid: out std_logic;
y: out std_logic_vector(24 downto 0);
y_valid: out std_logic
);
end delta_sigma_tbt_entity_bbfa8a8a69;
architecture structural of delta_sigma_tbt_entity_bbfa8a8a69 is
signal a_plus_b_s_net: std_logic_vector(24 downto 0);
signal a_plus_c_s_net: std_logic_vector(24 downto 0);
signal a_plus_d_s_net: std_logic_vector(24 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert1_dout_net_x0: std_logic;
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert6_dout_net_x0: std_logic;
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert_dout_net: std_logic;
signal b_plus_c_s_net: std_logic_vector(24 downto 0);
signal b_plus_d_s_net: std_logic_vector(24 downto 0);
signal c_plus_d_s_net: std_logic_vector(24 downto 0);
signal ce_1_sg_x94: std_logic;
signal ce_2_sg_x37: std_logic;
signal ce_70_sg_x26: std_logic;
signal ce_70_x3: std_logic;
signal ce_logic_70_sg_x0: std_logic;
signal clk_1_sg_x94: std_logic;
signal clk_2_sg_x37: std_logic;
signal clk_70_sg_x26: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal del_sig_div_tbt_thres_i_net_x0: std_logic_vector(25 downto 0);
signal delay1_q_net_x0: std_logic;
signal delay_q_net: std_logic_vector(25 downto 0);
signal delta_q_s_net: std_logic_vector(25 downto 0);
signal delta_x_s_net: std_logic_vector(25 downto 0);
signal delta_y_s_net: std_logic_vector(25 downto 0);
signal din: std_logic_vector(25 downto 0);
signal dividend_data: std_logic_vector(25 downto 0);
signal dividend_ready: std_logic;
signal dividend_ready_x0: std_logic;
signal dividend_valid_x0: std_logic;
signal dividend_valid_x1: std_logic;
signal dividend_valid_x2: std_logic;
signal divider_dout_fracc: std_logic_vector(24 downto 0);
signal divider_dout_valid_x0: std_logic;
signal divisor_data: std_logic_vector(25 downto 0);
signal divisor_data_x0: std_logic_vector(25 downto 0);
signal divisor_ready: std_logic;
signal divisor_valid_x0: std_logic;
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_stretch: std_logic_vector(24 downto 0);
signal down_sample1_q_net: std_logic_vector(24 downto 0);
signal down_sample1_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample2_q_net: std_logic;
signal down_sample2_q_net_x26: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x27: std_logic_vector(23 downto 0);
signal down_sample3_q_net: std_logic_vector(24 downto 0);
signal down_sample4_q_net: std_logic;
signal down_sample5_q_net: std_logic_vector(24 downto 0);
signal down_sample6_q_net: std_logic;
signal down_sample7_q_net: std_logic_vector(24 downto 0);
signal down_sample8_q_net: std_logic;
signal down_sample_q_net: std_logic_vector(25 downto 0);
signal expression1_dout_net: std_logic;
signal logical3_y_net_x0: std_logic;
signal logical3_y_net_x1: std_logic;
signal logical3_y_net_x2: std_logic;
signal logical3_y_net_x3: std_logic;
signal logical3_y_net_x4: std_logic;
signal logical3_y_net_x5: std_logic;
signal logical3_y_net_x6: std_logic;
signal logical3_y_net_x7: std_logic;
signal q_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal q_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal q_divider_s_axis_dividend_tready_net: std_logic;
signal q_divider_s_axis_divisor_tready_net: std_logic;
signal re_x0: std_logic;
signal re_x1: std_logic;
signal register10_q_net: std_logic_vector(25 downto 0);
signal register11_q_net: std_logic_vector(24 downto 0);
signal register12_q_net: std_logic_vector(24 downto 0);
signal register13_q_net: std_logic_vector(24 downto 0);
signal register14_q_net: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(24 downto 0);
signal register1_q_net_x1: std_logic;
signal register1_q_net_x2: std_logic;
signal register1_q_net_x3: std_logic;
signal register1_q_net_x4: std_logic;
signal register2_q_net: std_logic_vector(24 downto 0);
signal register3_q_net: std_logic_vector(24 downto 0);
signal register4_q_net: std_logic_vector(24 downto 0);
signal register5_q_net: std_logic_vector(24 downto 0);
signal register6_q_net: std_logic_vector(24 downto 0);
signal register7_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x1: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(24 downto 0);
signal register_q_net_x3: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x0: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret7_output_port_net: std_logic_vector(25 downto 0);
signal reinterpret8_output_port_net: std_logic_vector(25 downto 0);
signal relational_op_net: std_logic;
signal sum_s_net: std_logic_vector(25 downto 0);
signal up_sample2_q_net: std_logic_vector(25 downto 0);
signal up_sample4_q_net: std_logic_vector(25 downto 0);
signal up_sample6_q_net: std_logic_vector(25 downto 0);
signal up_sample_q_net: std_logic_vector(25 downto 0);
signal valid_ds_down_x1: std_logic;
signal x_divider_m_axis_dout_tdata_fractional_net: std_logic_vector(24 downto 0);
signal x_divider_m_axis_dout_tvalid_net_x0: std_logic;
signal x_divider_s_axis_divisor_tready_net: std_logic;
begin
down_sample2_q_net_x26 <= a;
down_sample1_q_net_x26 <= b;
down_sample2_q_net_x27 <= c;
ce_1_sg_x94 <= ce_1;
ce_2_sg_x37 <= ce_2;
ce_70_sg_x26 <= ce_70;
ce_logic_70_sg_x0 <= ce_logic_70;
clk_1_sg_x94 <= clk_1;
clk_2_sg_x37 <= clk_2;
clk_70_sg_x26 <= clk_70;
down_sample1_q_net_x27 <= d;
del_sig_div_tbt_thres_i_net_x0 <= ds_thres;
q <= assert8_dout_net_x1;
q_valid <= assert9_dout_net_x1;
sum_valid <= assert12_dout_net_x1;
sum_x0 <= assert11_dout_net_x1;
x <= assert5_dout_net_x1;
x_valid <= assert10_dout_net_x1;
y <= dout_down_x1;
y_valid <= valid_ds_down_x1;
a_plus_b: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x26,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_b_s_net
);
a_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_c_s_net
);
a_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => a_plus_d_s_net
);
assert1: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => q_divider_s_axis_dividend_tready_net,
dout(0) => assert1_dout_net_x0
);
assert10: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample6_q_net,
dout(0) => assert10_dout_net_x1
);
assert11: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample7_q_net,
dout => assert11_dout_net_x1
);
assert12: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample8_q_net,
dout(0) => assert12_dout_net_x1
);
assert2: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready_x0,
dout(0) => re_x0
);
assert3: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => dividend_ready,
dout(0) => re_x1
);
assert4: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample1_q_net,
dout => dout_down_x1
);
assert5: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample5_q_net,
dout => assert5_dout_net_x1
);
assert6: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => expression1_dout_net,
dout(0) => assert6_dout_net_x0
);
assert7: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample2_q_net,
dout(0) => valid_ds_down_x1
);
assert8: entity work.xlpassthrough
generic map (
din_width => 25,
dout_width => 25
)
port map (
din => down_sample3_q_net,
dout => assert8_dout_net_x1
);
assert9: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => down_sample4_q_net,
dout(0) => assert9_dout_net_x1
);
assert_x0: entity work.xlpassthrough
generic map (
din_width => 1,
dout_width => 1
)
port map (
din(0) => relational_op_net,
dout(0) => assert_dout_net
);
b_plus_c: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample2_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_c_s_net
);
b_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample1_q_net_x26,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => b_plus_d_s_net
);
c_plus_d: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 24,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 24,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 25,
core_name0 => "addsb_11_0_26986301a9f671cd",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 25,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 25
)
port map (
a => down_sample2_q_net_x27,
b => down_sample1_q_net_x27,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => c_plus_d_s_net
);
ce1: entity work.xlceprobe
generic map (
d_width => 1,
q_width => 1
)
port map (
ce => ce_logic_70_sg_x0,
clk => clk_70_sg_x26,
d(0) => assert_dout_net,
q(0) => ce_70_x3
);
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 22,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 21,
dout_width => 25,
latency => 0,
overflow => xlSaturate,
quantization => xlRound
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
clr => '0',
din => delay_q_net,
en => "1",
dout => convert_dout_net_x0
);
datareg_en1_e5d0399944: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret2_output_port_net_x0,
en => q_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x1,
valid => register1_q_net_x2
);
datareg_en2_02a2053e69: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret3_output_port_net_x0,
en => x_divider_m_axis_dout_tvalid_net_x0,
dout => register_q_net_x2,
valid => register1_q_net_x3
);
datareg_en3_78179f99cc: entity work.datareg_en3_entity_6643090018
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => convert_dout_net_x0,
en => delay1_q_net_x0,
dout => register_q_net_x3,
valid => register1_q_net_x4
);
datareg_en_ed948c360a: entity work.datareg_en_entity_79473f9ed1
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
din => reinterpret1_output_port_net_x0,
en => divider_dout_valid_x0,
dout => register_q_net_x0,
valid => register1_q_net_x1
);
delay: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 26
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => reinterpret8_output_port_net,
en => '1',
rst => '1',
q => delay_q_net
);
delay1: entity work.xldelay
generic map (
latency => 56,
reg_retiming => 0,
reset => 0,
width => 1
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d(0) => logical3_y_net_x4,
en => '1',
rst => '1',
q(0) => delay1_q_net_x0
);
delta_q: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register5_q_net,
b => register6_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_q_s_net
);
delta_x: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register1_q_net,
b => register3_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_x_s_net
);
delta_y: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_8b0747970e52f130",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register2_q_net,
b => register4_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => delta_y_s_net
);
down_sample: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
ds_ratio => 35,
latency => 1,
phase => 34,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register14_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_2_sg_x37,
src_clk => clk_2_sg_x37,
src_clr => '0',
q => down_sample_q_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => dout_stretch,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample1_q_net
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x0,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample2_q_net
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register11_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample3_q_net
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x1,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample4_q_net
);
down_sample5: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 24,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 24,
q_width => 25
)
port map (
d => register12_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample5_q_net
);
down_sample6: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x2,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample6_q_net
);
down_sample7: entity work.xldsamp
generic map (
d_arith => xlSigned,
d_bin_pt => 21,
d_width => 25,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlSigned,
q_bin_pt => 21,
q_width => 25
)
port map (
d => register13_q_net,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q => down_sample7_q_net
);
down_sample8: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
ds_ratio => 70,
latency => 1,
phase => 69,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => logical3_y_net_x3,
dest_ce => ce_70_sg_x26,
dest_clk => clk_70_sg_x26,
dest_clr => '0',
en => "1",
src_ce => ce_1_sg_x94,
src_clk => clk_1_sg_x94,
src_clr => '0',
q(0) => down_sample8_q_net
);
expression1: entity work.expr_375d7bbece
port map (
a(0) => x_divider_s_axis_divisor_tready_net,
b(0) => divisor_ready,
c(0) => q_divider_s_axis_divisor_tready_net,
ce => '0',
clk => '0',
clr => '0',
dout(0) => expression1_dout_net
);
pulse_stretcher1_eef5ee33be: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x2,
extd_out => logical3_y_net_x1
);
pulse_stretcher2_6f5c3f41cf: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x3,
extd_out => logical3_y_net_x2
);
pulse_stretcher3_e720dfd76f: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x4,
extd_out => logical3_y_net_x3
);
pulse_stretcher4_0a5eb3f903: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert6_dout_net_x0,
pulse_in => divisor_valid_x0,
extd_out => logical3_y_net_x4
);
pulse_stretcher5_b95a604b09: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x0,
pulse_in => dividend_valid_x0,
extd_out => logical3_y_net_x5
);
pulse_stretcher6_e7fb2961d9: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => assert1_dout_net_x0,
pulse_in => dividend_valid_x1,
extd_out => logical3_y_net_x6
);
pulse_stretcher7_6e7eb70147: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => re_x1,
pulse_in => dividend_valid_x2,
extd_out => logical3_y_net_x7
);
pulse_stretcher_f661707a58: entity work.pulse_stretcher_entity_9893378b63
port map (
ce_1 => ce_1_sg_x94,
clk_1 => clk_1_sg_x94,
clr => ce_70_x3,
pulse_in => register1_q_net_x1,
extd_out => logical3_y_net_x0
);
q_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret7_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x6,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => q_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => q_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => q_divider_s_axis_dividend_tready_net,
s_axis_divisor_tready => q_divider_s_axis_divisor_tready_net
);
register1: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_c_s_net,
en => "1",
rst => "0",
q => register1_q_net
);
register10: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_q_s_net,
en => "1",
rst => "0",
q => register10_q_net
);
register11: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x1,
en => "1",
rst => "0",
q => register11_q_net
);
register12: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x2,
en => "1",
rst => "0",
q => register12_q_net
);
register13: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x3,
en => "1",
rst => "0",
q => register13_q_net
);
register14: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_2_sg_x37,
clk => clk_2_sg_x37,
d => del_sig_div_tbt_thres_i_net_x0,
en => "1",
rst => "0",
q => register14_q_net
);
register2: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_b_s_net,
en => "1",
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_d_s_net,
en => "1",
rst => "0",
q => register3_q_net
);
register4: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => c_plus_d_s_net,
en => "1",
rst => "0",
q => register4_q_net
);
register5: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => a_plus_c_s_net,
en => "1",
rst => "0",
q => register5_q_net
);
register6: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => b_plus_d_s_net,
en => "1",
rst => "0",
q => register6_q_net
);
register7: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_x_s_net,
en => "1",
rst => "0",
q => register7_q_net
);
register8: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => sum_s_net,
en => "1",
rst => "0",
q => divisor_data
);
register9: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
d => delta_y_s_net,
en => "1",
rst => "0",
q => din
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
d => register_q_net_x0,
en => "1",
rst => "0",
q => dout_stretch
);
reinterpret1: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divider_dout_fracc,
output_port => reinterpret1_output_port_net_x0
);
reinterpret2: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => q_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret2_output_port_net_x0
);
reinterpret3: entity work.reinterpret_31a4235b32
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => x_divider_m_axis_dout_tdata_fractional_net,
output_port => reinterpret3_output_port_net_x0
);
reinterpret4: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample6_q_net,
output_port => reinterpret4_output_port_net
);
reinterpret5: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample2_q_net,
output_port => divisor_data_x0
);
reinterpret6: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample_q_net,
output_port => dividend_data
);
reinterpret7: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => up_sample4_q_net,
output_port => reinterpret7_output_port_net
);
reinterpret8: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => divisor_data_x0,
output_port => reinterpret8_output_port_net
);
relational: entity work.relational_416cfcae1e
port map (
a => divisor_data,
b => down_sample_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
op(0) => relational_op_net
);
sum: entity work.xladdsub
generic map (
a_arith => xlSigned,
a_bin_pt => 22,
a_width => 25,
b_arith => xlSigned,
b_bin_pt => 22,
b_width => 25,
c_has_c_out => 0,
c_latency => 0,
c_output_width => 26,
core_name0 => "addsb_11_0_239e4f614ba09ab1",
extra_registers => 0,
full_s_arith => 2,
full_s_width => 26,
latency => 0,
overflow => 1,
quantization => 1,
s_arith => xlSigned,
s_bin_pt => 22,
s_width => 26
)
port map (
a => register3_q_net,
b => register1_q_net,
ce => ce_70_sg_x26,
clk => clk_70_sg_x26,
clr => '0',
en => "1",
s => sum_s_net
);
up_sample: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => din,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample_q_net
);
up_sample1: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x0
);
up_sample2: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => divisor_data,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample2_q_net
);
up_sample3: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => divisor_valid_x0
);
up_sample4: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register10_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample4_q_net
);
up_sample5: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x1
);
up_sample6: entity work.xlusamp
generic map (
copy_samples => 1,
d_arith => xlSigned,
d_bin_pt => 22,
d_width => 26,
latency => 0,
q_arith => xlSigned,
q_bin_pt => 22,
q_width => 26
)
port map (
d => register7_q_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q => up_sample6_q_net
);
up_sample7: entity work.xlusamp
generic map (
copy_samples => 0,
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 1,
latency => 0,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 1
)
port map (
d(0) => assert_dout_net,
dest_ce => ce_1_sg_x94,
dest_clk => clk_1_sg_x94,
dest_clr => '0',
en => "1",
src_ce => ce_70_sg_x26,
src_clk => clk_70_sg_x26,
src_clr => '0',
q(0) => dividend_valid_x2
);
x_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => reinterpret4_output_port_net,
s_axis_dividend_tvalid => logical3_y_net_x7,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => x_divider_m_axis_dout_tdata_fractional_net,
m_axis_dout_tvalid => x_divider_m_axis_dout_tvalid_net_x0,
s_axis_dividend_tready => dividend_ready,
s_axis_divisor_tready => x_divider_s_axis_divisor_tready_net
);
y_divider: entity work.xldivider_generator_ee95dc360423b121d9ecd626691cc2ae
port map (
ce => ce_1_sg_x94,
clk => clk_1_sg_x94,
s_axis_dividend_tdata_dividend => dividend_data,
s_axis_dividend_tvalid => logical3_y_net_x5,
s_axis_divisor_tdata_divisor => divisor_data_x0,
s_axis_divisor_tvalid => logical3_y_net_x4,
m_axis_dout_tdata_fractional => divider_dout_fracc,
m_axis_dout_tvalid => divider_dout_valid_x0,
s_axis_dividend_tready => dividend_ready_x0,
s_axis_divisor_tready => divisor_ready
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1/format1"
entity format1_entity_a98b06306e is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout: out std_logic_vector(24 downto 0)
);
end format1_entity_a98b06306e;
architecture structural of format1_entity_a98b06306e is
signal ce_56000000_sg_x0: std_logic;
signal clk_56000000_sg_x0: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x0: std_logic_vector(25 downto 0);
signal reinterpret_output_port_net: std_logic_vector(25 downto 0);
begin
ce_56000000_sg_x0 <= ce_56000000;
clk_56000000_sg_x0 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x0 <= din;
dout <= convert_dout_net_x0;
convert: entity work.xlconvert
generic map (
bool_conversion => 0,
din_arith => 2,
din_bin_pt => 24,
din_width => 26,
dout_arith => 2,
dout_bin_pt => 24,
dout_width => 25,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_56000000_sg_x0,
clk => clk_56000000_sg_x0,
clr => '0',
din => reinterpret_output_port_net,
en => "1",
dout => convert_dout_net_x0
);
reinterpret: entity work.reinterpret_040ef1b598
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => monit_pos_1_c_m_axis_data_tdata_net_x0,
output_port => reinterpret_output_port_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/Cast1"
entity cast1_entity_3d447d0833 is
port (
ce_56000000: in std_logic;
clk_56000000: in std_logic;
data_in: in std_logic_vector(25 downto 0);
en: in std_logic;
out_x0: out std_logic_vector(24 downto 0);
vld_out: out std_logic
);
end cast1_entity_3d447d0833;
architecture structural of cast1_entity_3d447d0833 is
signal ce_56000000_sg_x1: std_logic;
signal clk_56000000_sg_x1: std_logic;
signal convert_dout_net_x0: std_logic_vector(24 downto 0);
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
begin
ce_56000000_sg_x1 <= ce_56000000;
clk_56000000_sg_x1 <= clk_56000000;
monit_pos_1_c_m_axis_data_tdata_net_x1 <= data_in;
monit_pos_1_c_m_axis_data_tvalid_net_x0 <= en;
out_x0 <= register_q_net_x0;
vld_out <= register1_q_net_x0;
format1_a98b06306e: entity work.format1_entity_a98b06306e
port map (
ce_56000000 => ce_56000000_sg_x1,
clk_56000000 => clk_56000000_sg_x1,
din => monit_pos_1_c_m_axis_data_tdata_net_x1,
dout => convert_dout_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 1,
init_value => b"0"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
en => "1",
rst => "0",
q(0) => register1_q_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 25,
init_value => b"0000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x1,
clk => clk_56000000_sg_x1,
d => convert_dout_net_x0,
en(0) => monit_pos_1_c_m_axis_data_tvalid_net_x0,
rst => "0",
q => register_q_net_x0
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out/TDDM_monit_pos_1_out_int"
entity tddm_monit_pos_1_out_int_entity_3405798202 is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_224000000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(25 downto 0);
dout_ch0: out std_logic_vector(25 downto 0);
dout_ch1: out std_logic_vector(25 downto 0);
dout_ch2: out std_logic_vector(25 downto 0);
dout_ch3: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_int_entity_3405798202;
architecture structural of tddm_monit_pos_1_out_int_entity_3405798202 is
signal ce_224000000_sg_x4: std_logic;
signal ce_56000000_sg_x2: std_logic;
signal clk_224000000_sg_x4: std_logic;
signal clk_56000000_sg_x2: std_logic;
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant1_op_net: std_logic_vector(1 downto 0);
signal constant3_op_net: std_logic_vector(1 downto 0);
signal constant4_op_net: std_logic_vector(1 downto 0);
signal constant_op_net: std_logic_vector(1 downto 0);
signal down_sample1_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x0: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x0: std_logic_vector(25 downto 0);
signal register1_q_net: std_logic_vector(25 downto 0);
signal register2_q_net: std_logic_vector(25 downto 0);
signal register3_q_net: std_logic_vector(25 downto 0);
signal register_q_net_x0: std_logic_vector(25 downto 0);
signal register_q_net_x1: std_logic_vector(1 downto 0);
signal relational1_op_net: std_logic;
signal relational2_op_net: std_logic;
signal relational3_op_net: std_logic;
signal relational_op_net: std_logic;
begin
ce_224000000_sg_x4 <= ce_224000000;
ce_56000000_sg_x2 <= ce_56000000;
register_q_net_x1 <= ch_in;
clk_224000000_sg_x4 <= clk_224000000;
clk_56000000_sg_x2 <= clk_56000000;
concat_y_net_x0 <= din;
dout_ch0 <= down_sample2_q_net_x0;
dout_ch1 <= down_sample1_q_net_x0;
dout_ch2 <= down_sample3_q_net_x0;
dout_ch3 <= down_sample4_q_net_x0;
constant1: entity work.constant_cda50df78a
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant1_op_net
);
constant3: entity work.constant_a7e2bb9e12
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant3_op_net
);
constant4: entity work.constant_e8ddc079e9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant4_op_net
);
constant_x0: entity work.constant_3a9a3daeb9
port map (
ce => '0',
clk => '0',
clr => '0',
op => constant_op_net
);
down_sample1: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register1_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample1_q_net_x0
);
down_sample2: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register_q_net_x0,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample2_q_net_x0
);
down_sample3: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register2_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample3_q_net_x0
);
down_sample4: entity work.xldsamp
generic map (
d_arith => xlUnsigned,
d_bin_pt => 0,
d_width => 26,
ds_ratio => 4,
latency => 1,
phase => 3,
q_arith => xlUnsigned,
q_bin_pt => 0,
q_width => 26
)
port map (
d => register3_q_net,
dest_ce => ce_224000000_sg_x4,
dest_clk => clk_224000000_sg_x4,
dest_clr => '0',
en => "1",
src_ce => ce_56000000_sg_x2,
src_clk => clk_56000000_sg_x2,
src_clr => '0',
q => down_sample4_q_net_x0
);
register1: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational1_op_net,
rst => "0",
q => register1_q_net
);
register2: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational2_op_net,
rst => "0",
q => register2_q_net
);
register3: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational3_op_net,
rst => "0",
q => register3_q_net
);
register_x0: entity work.xlregister
generic map (
d_width => 26,
init_value => b"00000000000000000000000000"
)
port map (
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
d => concat_y_net_x0,
en(0) => relational_op_net,
rst => "0",
q => register_q_net_x0
);
relational: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational_op_net
);
relational1: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant1_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational1_op_net
);
relational2: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant3_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational2_op_net
);
relational3: entity work.relational_367321bc0c
port map (
a => register_q_net_x1,
b => constant4_op_net,
ce => ce_56000000_sg_x2,
clk => clk_56000000_sg_x2,
clr => '0',
op(0) => relational3_op_net
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1/TDDM_monit_pos_1_out"
entity tddm_monit_pos_1_out_entity_1d58a51dbf is
port (
ce_224000000: in std_logic;
ce_56000000: in std_logic;
clk_224000000: in std_logic;
clk_56000000: in std_logic;
monit_pos_1_ch_in: in std_logic_vector(1 downto 0);
monit_pos_1_din: in std_logic_vector(25 downto 0);
monit_pos_1_q_out: out std_logic_vector(25 downto 0);
monit_pos_1_sum_out: out std_logic_vector(25 downto 0);
monit_pos_1_x_out: out std_logic_vector(25 downto 0);
monit_pos_1_y_out: out std_logic_vector(25 downto 0)
);
end tddm_monit_pos_1_out_entity_1d58a51dbf;
architecture structural of tddm_monit_pos_1_out_entity_1d58a51dbf is
signal ce_224000000_sg_x5: std_logic;
signal ce_56000000_sg_x3: std_logic;
signal clk_224000000_sg_x5: std_logic;
signal clk_56000000_sg_x3: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
begin
ce_224000000_sg_x5 <= ce_224000000;
ce_56000000_sg_x3 <= ce_56000000;
clk_224000000_sg_x5 <= clk_224000000;
clk_56000000_sg_x3 <= clk_56000000;
register_q_net_x2 <= monit_pos_1_ch_in;
concat_y_net_x1 <= monit_pos_1_din;
monit_pos_1_q_out <= down_sample3_q_net_x1;
monit_pos_1_sum_out <= down_sample4_q_net_x1;
monit_pos_1_x_out <= down_sample2_q_net_x1;
monit_pos_1_y_out <= down_sample1_q_net_x1;
tddm_monit_pos_1_out_int_3405798202: entity work.tddm_monit_pos_1_out_int_entity_3405798202
port map (
ce_224000000 => ce_224000000_sg_x5,
ce_56000000 => ce_56000000_sg_x3,
ch_in => register_q_net_x2,
clk_224000000 => clk_224000000_sg_x5,
clk_56000000 => clk_56000000_sg_x3,
din => concat_y_net_x1,
dout_ch0 => down_sample2_q_net_x1,
dout_ch1 => down_sample1_q_net_x1,
dout_ch2 => down_sample3_q_net_x1,
dout_ch3 => down_sample4_q_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066/monit_pos_1"
entity monit_pos_1_entity_522c8cf08d is
port (
ce_1: in std_logic;
ce_224000000: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_logic_5600000: in std_logic;
ch_in: in std_logic_vector(1 downto 0);
clk_1: in std_logic;
clk_224000000: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
din: in std_logic_vector(24 downto 0);
monit_1_pos_q: out std_logic_vector(24 downto 0);
monit_1_pos_x: out std_logic_vector(24 downto 0);
monit_1_pos_y: out std_logic_vector(24 downto 0);
monit_1_sum: out std_logic_vector(24 downto 0);
monit_1_vld_q: out std_logic;
monit_1_vld_sum: out std_logic;
monit_1_vld_x: out std_logic;
monit_1_vld_y: out std_logic;
monit_pos_1_c_x0: out std_logic
);
end monit_pos_1_entity_522c8cf08d;
architecture structural of monit_pos_1_entity_522c8cf08d is
signal ce_1_sg_x95: std_logic;
signal ce_224000000_sg_x6: std_logic;
signal ce_56000000_sg_x4: std_logic;
signal ce_5600000_sg_x11: std_logic;
signal ce_logic_5600000_sg_x1: std_logic;
signal clk_1_sg_x95: std_logic;
signal clk_224000000_sg_x6: std_logic;
signal clk_56000000_sg_x4: std_logic;
signal clk_5600000_sg_x11: std_logic;
signal concat_y_net_x1: std_logic_vector(25 downto 0);
signal down_sample1_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample2_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample3_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample4_q_net_x1: std_logic_vector(25 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal extractor1_dout_net: std_logic_vector(24 downto 0);
signal extractor1_vld_out_net: std_logic;
signal extractor2_dout_net: std_logic_vector(24 downto 0);
signal extractor2_vld_out_net: std_logic;
signal extractor3_dout_net: std_logic_vector(24 downto 0);
signal extractor3_vld_out_net: std_logic;
signal extractor4_dout_net: std_logic_vector(24 downto 0);
signal extractor4_vld_out_net: std_logic;
signal monit_pos_1_c_event_s_data_chanid_incorrect_net_x0: std_logic;
signal monit_pos_1_c_m_axis_data_tdata_net_x1: std_logic_vector(25 downto 0);
signal monit_pos_1_c_m_axis_data_tuser_chanid_net: std_logic_vector(1 downto 0);
signal monit_pos_1_c_m_axis_data_tvalid_net_x0: std_logic;
signal register1_q_net_x0: std_logic;
signal register_q_net_x0: std_logic_vector(24 downto 0);
signal register_q_net_x2: std_logic_vector(1 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
begin
ce_1_sg_x95 <= ce_1;
ce_224000000_sg_x6 <= ce_224000000;
ce_5600000_sg_x11 <= ce_5600000;
ce_56000000_sg_x4 <= ce_56000000;
ce_logic_5600000_sg_x1 <= ce_logic_5600000;
down_sample_q_net_x3 <= ch_in;
clk_1_sg_x95 <= clk_1;
clk_224000000_sg_x6 <= clk_224000000;
clk_5600000_sg_x11 <= clk_5600000;
clk_56000000_sg_x4 <= clk_56000000;
reinterpret5_output_port_net_x1 <= din;
monit_1_pos_q <= reinterpret2_output_port_net_x1;
monit_1_pos_x <= reinterpret3_output_port_net_x1;
monit_1_pos_y <= reinterpret1_output_port_net_x1;
monit_1_sum <= reinterpret4_output_port_net_x1;
monit_1_vld_q <= ufix_to_bool2_dout_net_x1;
monit_1_vld_sum <= ufix_to_bool3_dout_net_x1;
monit_1_vld_x <= ufix_to_bool_dout_net_x1;
monit_1_vld_y <= ufix_to_bool1_dout_net_x1;
monit_pos_1_c_x0 <= monit_pos_1_c_event_s_data_chanid_incorrect_net_x0;
cast1_3d447d0833: entity work.cast1_entity_3d447d0833
port map (
ce_56000000 => ce_56000000_sg_x4,
clk_56000000 => clk_56000000_sg_x4,
data_in => monit_pos_1_c_m_axis_data_tdata_net_x1,
en => monit_pos_1_c_m_axis_data_tvalid_net_x0,
out_x0 => register_q_net_x0,
vld_out => register1_q_net_x0
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => register1_q_net_x0,
in1 => reinterpret5_output_port_net,
y => concat_y_net_x1
);
extractor1: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample3_q_net_x1,
dout => extractor1_dout_net,
vld_out(0) => extractor1_vld_out_net
);
extractor2: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample1_q_net_x1,
dout => extractor2_dout_net,
vld_out(0) => extractor2_vld_out_net
);
extractor3: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample4_q_net_x1,
dout => extractor3_dout_net,
vld_out(0) => extractor3_vld_out_net
);
extractor4: entity work.bitbasher_a756ba0096
port map (
ce => '0',
clk => '0',
clr => '0',
din => down_sample2_q_net_x1,
dout => extractor4_dout_net,
vld_out(0) => extractor4_vld_out_net
);
monit_pos_1_c: entity work.xlfir_compiler_c8ab56fde252f177c3a1ef23ff29e49a
port map (
ce => ce_1_sg_x95,
ce_5600000 => ce_5600000_sg_x11,
ce_56000000 => ce_56000000_sg_x4,
ce_logic_5600000 => ce_logic_5600000_sg_x1,
clk => clk_1_sg_x95,
clk_5600000 => clk_5600000_sg_x11,
clk_56000000 => clk_56000000_sg_x4,
clk_logic_5600000 => clk_5600000_sg_x11,
s_axis_data_tdata => reinterpret5_output_port_net_x1,
s_axis_data_tuser_chanid => down_sample_q_net_x3,
src_ce => ce_5600000_sg_x11,
src_clk => clk_5600000_sg_x11,
event_s_data_chanid_incorrect => monit_pos_1_c_event_s_data_chanid_incorrect_net_x0,
m_axis_data_tdata => monit_pos_1_c_m_axis_data_tdata_net_x1,
m_axis_data_tuser_chanid => monit_pos_1_c_m_axis_data_tuser_chanid_net,
m_axis_data_tvalid => monit_pos_1_c_m_axis_data_tvalid_net_x0
);
register_x0: entity work.xlregister
generic map (
d_width => 2,
init_value => b"00"
)
port map (
ce => ce_56000000_sg_x4,
clk => clk_56000000_sg_x4,
d => monit_pos_1_c_m_axis_data_tuser_chanid_net,
en => "1",
rst => "0",
q => register_q_net_x2
);
reinterpret1: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor2_dout_net,
output_port => reinterpret1_output_port_net_x1
);
reinterpret2: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor1_dout_net,
output_port => reinterpret2_output_port_net_x1
);
reinterpret3: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor4_dout_net,
output_port => reinterpret3_output_port_net_x1
);
reinterpret4: entity work.reinterpret_60ea556961
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => extractor3_dout_net,
output_port => reinterpret4_output_port_net_x1
);
reinterpret5: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => register_q_net_x0,
output_port => reinterpret5_output_port_net
);
tddm_monit_pos_1_out_1d58a51dbf: entity work.tddm_monit_pos_1_out_entity_1d58a51dbf
port map (
ce_224000000 => ce_224000000_sg_x6,
ce_56000000 => ce_56000000_sg_x4,
clk_224000000 => clk_224000000_sg_x6,
clk_56000000 => clk_56000000_sg_x4,
monit_pos_1_ch_in => register_q_net_x2,
monit_pos_1_din => concat_y_net_x1,
monit_pos_1_q_out => down_sample3_q_net_x1,
monit_pos_1_sum_out => down_sample4_q_net_x1,
monit_pos_1_x_out => down_sample2_q_net_x1,
monit_pos_1_y_out => down_sample1_q_net_x1
);
ufix_to_bool: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor4_vld_out_net,
en => "1",
dout(0) => ufix_to_bool_dout_net_x1
);
ufix_to_bool1: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor2_vld_out_net,
en => "1",
dout(0) => ufix_to_bool1_dout_net_x1
);
ufix_to_bool2: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor1_vld_out_net,
en => "1",
dout(0) => ufix_to_bool2_dout_net_x1
);
ufix_to_bool3: entity work.xlconvert
generic map (
bool_conversion => 1,
din_arith => 1,
din_bin_pt => 0,
din_width => 1,
dout_arith => 1,
dout_bin_pt => 0,
dout_width => 1,
latency => 0,
overflow => xlWrap,
quantization => xlRound
)
port map (
ce => ce_224000000_sg_x6,
clk => clk_224000000_sg_x6,
clr => '0',
din(0) => extractor3_vld_out_net,
en => "1",
dout(0) => ufix_to_bool3_dout_net_x1
);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- Generated from Simulink block "ddc_bpm_476_066"
entity ddc_bpm_476_066 is
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce_1: in std_logic;
ce_10000: in std_logic;
ce_1120: in std_logic;
ce_1400000: in std_logic;
ce_2: in std_logic;
ce_2240: in std_logic;
ce_22400000: in std_logic;
ce_224000000: in std_logic;
ce_2500: in std_logic;
ce_2800000: in std_logic;
ce_35: in std_logic;
ce_4480: in std_logic;
ce_44800000: in std_logic;
ce_5000: in std_logic;
ce_560: in std_logic;
ce_5600000: in std_logic;
ce_56000000: in std_logic;
ce_70: in std_logic;
ce_logic_1: in std_logic;
ce_logic_1400000: in std_logic;
ce_logic_2240: in std_logic;
ce_logic_22400000: in std_logic;
ce_logic_2800000: in std_logic;
ce_logic_560: in std_logic;
ce_logic_5600000: in std_logic;
ce_logic_70: in std_logic;
clk_1: in std_logic;
clk_10000: in std_logic;
clk_1120: in std_logic;
clk_1400000: in std_logic;
clk_2: in std_logic;
clk_2240: in std_logic;
clk_22400000: in std_logic;
clk_224000000: in std_logic;
clk_2500: in std_logic;
clk_2800000: in std_logic;
clk_35: in std_logic;
clk_4480: in std_logic;
clk_44800000: in std_logic;
clk_5000: in std_logic;
clk_560: in std_logic;
clk_5600000: in std_logic;
clk_56000000: in std_logic;
clk_70: in std_logic;
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end ddc_bpm_476_066;
architecture structural of ddc_bpm_476_066 is
attribute core_generation_info: string;
attribute core_generation_info of structural : architecture is "ddc_bpm_476_066,sysgen_core,{clock_period=4.44116092,clocking=Clock_Enables,compilation=HDL_Netlist,sample_periods=1.00000000000 2.00000000000 35.00000000000 70.00000000000 560.00000000000 1120.00000000000 2240.00000000000 2500.00000000000 4480.00000000000 5000.00000000000 10000.00000000000 1400000.00000000000 2800000.00000000000 5600000.00000000000 22400000.00000000000 44800000.00000000000 56000000.00000000000 224000000.00000000000,testbench=0,total_blocks=3351,xilinx_adder_subtracter_block=30,xilinx_arithmetic_relational_operator_block=66,xilinx_assert_block=55,xilinx_bit_slice_extractor_block=20,xilinx_bitbasher_block=5,xilinx_bitwise_expression_evaluator_block=3,xilinx_black_box_block=1,xilinx_bus_concatenator_block=9,xilinx_bus_multiplexer_block=8,xilinx_cic_compiler_3_0_block=5,xilinx_clock_enable_probe_block=11,xilinx_complex_multiplier_5_0__block=2,xilinx_constant_block_block=83,xilinx_cordic_5_0_block=4,xilinx_counter_block=8,xilinx_delay_block=59,xilinx_divider_generator_4_0_block=9,xilinx_down_sampler_block=118,xilinx_fir_compiler_6_3_block=5,xilinx_gateway_in_block=22,xilinx_gateway_out_block=233,xilinx_inverter_block=24,xilinx_logical_block_block=72,xilinx_multiplier_block=16,xilinx_register_block=264,xilinx_sample_time_block_block=88,xilinx_system_generator_block=1,xilinx_type_converter_block=23,xilinx_type_reinterpreter_block=94,xilinx_up_sampler_block=68,xilinx_wavescope_block=2,}";
signal adc_ch0_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch0_i_net: std_logic_vector(15 downto 0);
signal adc_ch1_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch1_i_net: std_logic_vector(15 downto 0);
signal adc_ch2_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch2_i_net: std_logic_vector(15 downto 0);
signal adc_ch3_dbg_data_o_net: std_logic_vector(15 downto 0);
signal adc_ch3_i_net: std_logic_vector(15 downto 0);
signal assert10_dout_net_x1: std_logic;
signal assert10_dout_net_x2: std_logic;
signal assert10_dout_net_x3: std_logic;
signal assert11_dout_net_x1: std_logic_vector(24 downto 0);
signal assert11_dout_net_x2: std_logic_vector(24 downto 0);
signal assert11_dout_net_x3: std_logic_vector(24 downto 0);
signal assert12_dout_net_x1: std_logic;
signal assert12_dout_net_x2: std_logic;
signal assert12_dout_net_x3: std_logic;
signal assert4_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x1: std_logic_vector(24 downto 0);
signal assert5_dout_net_x2: std_logic_vector(24 downto 0);
signal assert5_dout_net_x3: std_logic_vector(24 downto 0);
signal assert8_dout_net_x1: std_logic_vector(24 downto 0);
signal assert8_dout_net_x2: std_logic_vector(24 downto 0);
signal assert9_dout_net_x1: std_logic;
signal assert9_dout_net_x2: std_logic;
signal assert9_dout_net_x3: std_logic;
signal bpf_ch0_o_net: std_logic_vector(23 downto 0);
signal bpf_ch1_o_net: std_logic_vector(23 downto 0);
signal bpf_ch2_o_net: std_logic_vector(23 downto 0);
signal bpf_ch3_o_net: std_logic_vector(23 downto 0);
signal ce_10000_sg_x2: std_logic;
signal ce_1120_sg_x32: std_logic;
signal ce_1400000_sg_x3: std_logic;
signal ce_1_sg_x96: std_logic;
signal ce_224000000_sg_x7: std_logic;
signal ce_22400000_sg_x28: std_logic;
signal ce_2240_sg_x28: std_logic;
signal ce_2500_sg_x3: std_logic;
signal ce_2800000_sg_x4: std_logic;
signal ce_2_sg_x38: std_logic;
signal ce_35_sg_x22: std_logic;
signal ce_44800000_sg_x2: std_logic;
signal ce_4480_sg_x9: std_logic;
signal ce_5000_sg_x9: std_logic;
signal ce_56000000_sg_x5: std_logic;
signal ce_5600000_sg_x12: std_logic;
signal ce_560_sg_x3: std_logic;
signal ce_70_sg_x27: std_logic;
signal ce_logic_1400000_sg_x2: std_logic;
signal ce_logic_1_sg_x20: std_logic;
signal ce_logic_22400000_sg_x1: std_logic;
signal ce_logic_2240_sg_x1: std_logic;
signal ce_logic_2800000_sg_x2: std_logic;
signal ce_logic_5600000_sg_x2: std_logic;
signal ce_logic_560_sg_x3: std_logic;
signal ce_logic_70_sg_x1: std_logic;
signal ch_out_x2: std_logic_vector(1 downto 0);
signal cic_fofb_q_01_missing_o_net: std_logic;
signal cic_fofb_q_23_missing_o_net: std_logic;
signal clk_10000_sg_x2: std_logic;
signal clk_1120_sg_x32: std_logic;
signal clk_1400000_sg_x3: std_logic;
signal clk_1_sg_x96: std_logic;
signal clk_224000000_sg_x7: std_logic;
signal clk_22400000_sg_x28: std_logic;
signal clk_2240_sg_x28: std_logic;
signal clk_2500_sg_x3: std_logic;
signal clk_2800000_sg_x4: std_logic;
signal clk_2_sg_x38: std_logic;
signal clk_35_sg_x22: std_logic;
signal clk_44800000_sg_x2: std_logic;
signal clk_4480_sg_x9: std_logic;
signal clk_5000_sg_x9: std_logic;
signal clk_56000000_sg_x5: std_logic;
signal clk_5600000_sg_x12: std_logic;
signal clk_560_sg_x3: std_logic;
signal clk_70_sg_x27: std_logic;
signal concat1_y_net_x0: std_logic_vector(25 downto 0);
signal concat2_y_net_x0: std_logic_vector(25 downto 0);
signal concat3_y_net_x0: std_logic_vector(25 downto 0);
signal concat_y_net_x0: std_logic_vector(25 downto 0);
signal constant10_op_net_x0: std_logic;
signal constant11_op_net_x0: std_logic;
signal constant15_op_net_x1: std_logic;
signal constant3_op_net_x1: std_logic;
signal dds_config_valid_ch0_i_net: std_logic;
signal dds_config_valid_ch1_i_net: std_logic;
signal dds_config_valid_ch2_i_net: std_logic;
signal dds_config_valid_ch3_i_net: std_logic;
signal dds_pinc_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_pinc_ch3_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch0_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch1_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch2_i_net: std_logic_vector(29 downto 0);
signal dds_poff_ch3_i_net: std_logic_vector(29 downto 0);
signal del_sig_div_fofb_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_monit_thres_i_net: std_logic_vector(25 downto 0);
signal del_sig_div_tbt_thres_i_net: std_logic_vector(25 downto 0);
signal dout_down_x1: std_logic_vector(24 downto 0);
signal dout_down_x2: std_logic_vector(24 downto 0);
signal dout_down_x3: std_logic_vector(24 downto 0);
signal dout_x2: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample1_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x20: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x21: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x34: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x35: std_logic_vector(23 downto 0);
signal down_sample2_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample3_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample4_q_net_x5: std_logic_vector(23 downto 0);
signal down_sample_q_net_x3: std_logic_vector(1 downto 0);
signal down_sample_q_net_x4: std_logic_vector(25 downto 0);
signal fofb_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal fofb_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal fofb_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ksum_i_net: std_logic_vector(24 downto 0);
signal kx_i_net: std_logic_vector(24 downto 0);
signal ky_i_net: std_logic_vector(24 downto 0);
signal mix_ch0_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch0_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch1_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch2_q_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_i_o_net: std_logic_vector(23 downto 0);
signal mix_ch3_q_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal monit_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal monit_cfir_incorrect_o_net: std_logic;
signal monit_cic_unexpected_o_net: std_logic;
signal monit_pfir_incorrect_o_net: std_logic;
signal monit_pos_1_incorrect_o_net: std_logic;
signal q_fofb_o_net: std_logic_vector(25 downto 0);
signal q_fofb_valid_o_net: std_logic;
signal q_monit_1_o_net: std_logic_vector(25 downto 0);
signal q_monit_1_valid_o_net: std_logic;
signal q_monit_o_net: std_logic_vector(25 downto 0);
signal q_monit_valid_o_net: std_logic;
signal q_tbt_o_net: std_logic_vector(25 downto 0);
signal q_tbt_valid_o_net: std_logic;
signal register1_q_net_x6: std_logic;
signal register1_q_net_x7: std_logic;
signal register3_q_net_x15: std_logic;
signal register3_q_net_x16: std_logic;
signal register4_q_net_x14: std_logic_vector(23 downto 0);
signal register4_q_net_x15: std_logic_vector(23 downto 0);
signal register5_q_net_x14: std_logic_vector(23 downto 0);
signal register5_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x12: std_logic_vector(23 downto 0);
signal register_q_net_x13: std_logic_vector(23 downto 0);
signal register_q_net_x14: std_logic_vector(23 downto 0);
signal register_q_net_x15: std_logic_vector(23 downto 0);
signal register_q_net_x31: std_logic_vector(23 downto 0);
signal register_q_net_x32: std_logic_vector(23 downto 0);
signal reinterpret1_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret1_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret2_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret3_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net: std_logic_vector(24 downto 0);
signal reinterpret4_output_port_net_x1: std_logic_vector(24 downto 0);
signal reinterpret5_output_port_net_x1: std_logic_vector(24 downto 0);
signal sum_fofb_o_net: std_logic_vector(25 downto 0);
signal sum_fofb_valid_o_net: std_logic;
signal sum_monit_1_o_net: std_logic_vector(25 downto 0);
signal sum_monit_1_valid_o_net: std_logic;
signal sum_monit_o_net: std_logic_vector(25 downto 0);
signal sum_monit_valid_o_net: std_logic;
signal sum_tbt_o_net: std_logic_vector(25 downto 0);
signal sum_tbt_valid_o_net: std_logic;
signal tbt_amp_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_amp_ch3_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch01_incorrect_o_net: std_logic;
signal tbt_decim_ch0_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch0_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch1_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch23_incorrect_o_net: std_logic;
signal tbt_decim_ch2_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch2_q_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_i_o_net: std_logic_vector(23 downto 0);
signal tbt_decim_ch3_q_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch0_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch1_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch2_o_net: std_logic_vector(23 downto 0);
signal tbt_pha_ch3_o_net: std_logic_vector(23 downto 0);
signal ufix_to_bool1_dout_net_x1: std_logic;
signal ufix_to_bool2_dout_net_x1: std_logic;
signal ufix_to_bool3_dout_net_x1: std_logic;
signal ufix_to_bool_dout_net_x1: std_logic;
signal valid_ds_down_x1: std_logic;
signal valid_ds_down_x2: std_logic;
signal valid_ds_down_x3: std_logic;
signal x_fofb_o_net: std_logic_vector(25 downto 0);
signal x_fofb_valid_o_net: std_logic;
signal x_monit_1_o_net: std_logic_vector(25 downto 0);
signal x_monit_1_valid_o_net: std_logic;
signal x_monit_o_net: std_logic_vector(25 downto 0);
signal x_monit_valid_o_net: std_logic;
signal x_tbt_o_net: std_logic_vector(25 downto 0);
signal x_tbt_valid_o_net: std_logic;
signal y_fofb_o_net: std_logic_vector(25 downto 0);
signal y_fofb_valid_o_net: std_logic;
signal y_monit_1_o_net: std_logic_vector(25 downto 0);
signal y_monit_1_valid_o_net: std_logic;
signal y_monit_o_net: std_logic_vector(25 downto 0);
signal y_monit_valid_o_net: std_logic;
signal y_tbt_o_net: std_logic_vector(25 downto 0);
signal y_tbt_valid_o_net: std_logic;
begin
adc_ch0_i_net <= adc_ch0_i;
adc_ch1_i_net <= adc_ch1_i;
adc_ch2_i_net <= adc_ch2_i;
adc_ch3_i_net <= adc_ch3_i;
ce_1_sg_x96 <= ce_1;
ce_10000_sg_x2 <= ce_10000;
ce_1120_sg_x32 <= ce_1120;
ce_1400000_sg_x3 <= ce_1400000;
ce_2_sg_x38 <= ce_2;
ce_2240_sg_x28 <= ce_2240;
ce_22400000_sg_x28 <= ce_22400000;
ce_224000000_sg_x7 <= ce_224000000;
ce_2500_sg_x3 <= ce_2500;
ce_2800000_sg_x4 <= ce_2800000;
ce_35_sg_x22 <= ce_35;
ce_4480_sg_x9 <= ce_4480;
ce_44800000_sg_x2 <= ce_44800000;
ce_5000_sg_x9 <= ce_5000;
ce_560_sg_x3 <= ce_560;
ce_5600000_sg_x12 <= ce_5600000;
ce_56000000_sg_x5 <= ce_56000000;
ce_70_sg_x27 <= ce_70;
ce_logic_1_sg_x20 <= ce_logic_1;
ce_logic_1400000_sg_x2 <= ce_logic_1400000;
ce_logic_2240_sg_x1 <= ce_logic_2240;
ce_logic_22400000_sg_x1 <= ce_logic_22400000;
ce_logic_2800000_sg_x2 <= ce_logic_2800000;
ce_logic_560_sg_x3 <= ce_logic_560;
ce_logic_5600000_sg_x2 <= ce_logic_5600000;
ce_logic_70_sg_x1 <= ce_logic_70;
clk_1_sg_x96 <= clk_1;
clk_10000_sg_x2 <= clk_10000;
clk_1120_sg_x32 <= clk_1120;
clk_1400000_sg_x3 <= clk_1400000;
clk_2_sg_x38 <= clk_2;
clk_2240_sg_x28 <= clk_2240;
clk_22400000_sg_x28 <= clk_22400000;
clk_224000000_sg_x7 <= clk_224000000;
clk_2500_sg_x3 <= clk_2500;
clk_2800000_sg_x4 <= clk_2800000;
clk_35_sg_x22 <= clk_35;
clk_4480_sg_x9 <= clk_4480;
clk_44800000_sg_x2 <= clk_44800000;
clk_5000_sg_x9 <= clk_5000;
clk_560_sg_x3 <= clk_560;
clk_5600000_sg_x12 <= clk_5600000;
clk_56000000_sg_x5 <= clk_56000000;
clk_70_sg_x27 <= clk_70;
dds_config_valid_ch0_i_net <= dds_config_valid_ch0_i;
dds_config_valid_ch1_i_net <= dds_config_valid_ch1_i;
dds_config_valid_ch2_i_net <= dds_config_valid_ch2_i;
dds_config_valid_ch3_i_net <= dds_config_valid_ch3_i;
dds_pinc_ch0_i_net <= dds_pinc_ch0_i;
dds_pinc_ch1_i_net <= dds_pinc_ch1_i;
dds_pinc_ch2_i_net <= dds_pinc_ch2_i;
dds_pinc_ch3_i_net <= dds_pinc_ch3_i;
dds_poff_ch0_i_net <= dds_poff_ch0_i;
dds_poff_ch1_i_net <= dds_poff_ch1_i;
dds_poff_ch2_i_net <= dds_poff_ch2_i;
dds_poff_ch3_i_net <= dds_poff_ch3_i;
del_sig_div_fofb_thres_i_net <= del_sig_div_fofb_thres_i;
del_sig_div_monit_thres_i_net <= del_sig_div_monit_thres_i;
del_sig_div_tbt_thres_i_net <= del_sig_div_tbt_thres_i;
ksum_i_net <= ksum_i;
kx_i_net <= kx_i;
ky_i_net <= ky_i;
adc_ch0_dbg_data_o <= adc_ch0_dbg_data_o_net;
adc_ch1_dbg_data_o <= adc_ch1_dbg_data_o_net;
adc_ch2_dbg_data_o <= adc_ch2_dbg_data_o_net;
adc_ch3_dbg_data_o <= adc_ch3_dbg_data_o_net;
bpf_ch0_o <= bpf_ch0_o_net;
bpf_ch1_o <= bpf_ch1_o_net;
bpf_ch2_o <= bpf_ch2_o_net;
bpf_ch3_o <= bpf_ch3_o_net;
cic_fofb_q_01_missing_o <= cic_fofb_q_01_missing_o_net;
cic_fofb_q_23_missing_o <= cic_fofb_q_23_missing_o_net;
fofb_amp_ch0_o <= fofb_amp_ch0_o_net;
fofb_amp_ch1_o <= fofb_amp_ch1_o_net;
fofb_amp_ch2_o <= fofb_amp_ch2_o_net;
fofb_amp_ch3_o <= fofb_amp_ch3_o_net;
fofb_decim_ch0_i_o <= fofb_decim_ch0_i_o_net;
fofb_decim_ch0_q_o <= fofb_decim_ch0_q_o_net;
fofb_decim_ch1_i_o <= fofb_decim_ch1_i_o_net;
fofb_decim_ch1_q_o <= fofb_decim_ch1_q_o_net;
fofb_decim_ch2_i_o <= fofb_decim_ch2_i_o_net;
fofb_decim_ch2_q_o <= fofb_decim_ch2_q_o_net;
fofb_decim_ch3_i_o <= fofb_decim_ch3_i_o_net;
fofb_decim_ch3_q_o <= fofb_decim_ch3_q_o_net;
fofb_pha_ch0_o <= fofb_pha_ch0_o_net;
fofb_pha_ch1_o <= fofb_pha_ch1_o_net;
fofb_pha_ch2_o <= fofb_pha_ch2_o_net;
fofb_pha_ch3_o <= fofb_pha_ch3_o_net;
mix_ch0_i_o <= mix_ch0_i_o_net;
mix_ch0_q_o <= mix_ch0_q_o_net;
mix_ch1_i_o <= mix_ch1_i_o_net;
mix_ch1_q_o <= mix_ch1_q_o_net;
mix_ch2_i_o <= mix_ch2_i_o_net;
mix_ch2_q_o <= mix_ch2_q_o_net;
mix_ch3_i_o <= mix_ch3_i_o_net;
mix_ch3_q_o <= mix_ch3_q_o_net;
monit_amp_ch0_o <= monit_amp_ch0_o_net;
monit_amp_ch1_o <= monit_amp_ch1_o_net;
monit_amp_ch2_o <= monit_amp_ch2_o_net;
monit_amp_ch3_o <= monit_amp_ch3_o_net;
monit_cfir_incorrect_o <= monit_cfir_incorrect_o_net;
monit_cic_unexpected_o <= monit_cic_unexpected_o_net;
monit_pfir_incorrect_o <= monit_pfir_incorrect_o_net;
monit_pos_1_incorrect_o <= monit_pos_1_incorrect_o_net;
q_fofb_o <= q_fofb_o_net;
q_fofb_valid_o <= q_fofb_valid_o_net;
q_monit_1_o <= q_monit_1_o_net;
q_monit_1_valid_o <= q_monit_1_valid_o_net;
q_monit_o <= q_monit_o_net;
q_monit_valid_o <= q_monit_valid_o_net;
q_tbt_o <= q_tbt_o_net;
q_tbt_valid_o <= q_tbt_valid_o_net;
sum_fofb_o <= sum_fofb_o_net;
sum_fofb_valid_o <= sum_fofb_valid_o_net;
sum_monit_1_o <= sum_monit_1_o_net;
sum_monit_1_valid_o <= sum_monit_1_valid_o_net;
sum_monit_o <= sum_monit_o_net;
sum_monit_valid_o <= sum_monit_valid_o_net;
sum_tbt_o <= sum_tbt_o_net;
sum_tbt_valid_o <= sum_tbt_valid_o_net;
tbt_amp_ch0_o <= tbt_amp_ch0_o_net;
tbt_amp_ch1_o <= tbt_amp_ch1_o_net;
tbt_amp_ch2_o <= tbt_amp_ch2_o_net;
tbt_amp_ch3_o <= tbt_amp_ch3_o_net;
tbt_decim_ch01_incorrect_o <= tbt_decim_ch01_incorrect_o_net;
tbt_decim_ch0_i_o <= tbt_decim_ch0_i_o_net;
tbt_decim_ch0_q_o <= tbt_decim_ch0_q_o_net;
tbt_decim_ch1_i_o <= tbt_decim_ch1_i_o_net;
tbt_decim_ch1_q_o <= tbt_decim_ch1_q_o_net;
tbt_decim_ch23_incorrect_o <= tbt_decim_ch23_incorrect_o_net;
tbt_decim_ch2_i_o <= tbt_decim_ch2_i_o_net;
tbt_decim_ch2_q_o <= tbt_decim_ch2_q_o_net;
tbt_decim_ch3_i_o <= tbt_decim_ch3_i_o_net;
tbt_decim_ch3_q_o <= tbt_decim_ch3_q_o_net;
tbt_pha_ch0_o <= tbt_pha_ch0_o_net;
tbt_pha_ch1_o <= tbt_pha_ch1_o_net;
tbt_pha_ch2_o <= tbt_pha_ch2_o_net;
tbt_pha_ch3_o <= tbt_pha_ch3_o_net;
x_fofb_o <= x_fofb_o_net;
x_fofb_valid_o <= x_fofb_valid_o_net;
x_monit_1_o <= x_monit_1_o_net;
x_monit_1_valid_o <= x_monit_1_valid_o_net;
x_monit_o <= x_monit_o_net;
x_monit_valid_o <= x_monit_valid_o_net;
x_tbt_o <= x_tbt_o_net;
x_tbt_valid_o <= x_tbt_valid_o_net;
y_fofb_o <= y_fofb_o_net;
y_fofb_valid_o <= y_fofb_valid_o_net;
y_monit_1_o <= y_monit_1_o_net;
y_monit_1_valid_o <= y_monit_1_valid_o_net;
y_monit_o <= y_monit_o_net;
y_monit_valid_o <= y_monit_valid_o_net;
y_tbt_o <= y_tbt_o_net;
y_tbt_valid_o <= y_tbt_valid_o_net;
bpf_d31c4af409: entity work.bpf_entity_d31c4af409
port map (
din_ch0 => adc_ch0_dbg_data_o_net,
din_ch1 => adc_ch1_dbg_data_o_net,
din_ch2 => adc_ch2_dbg_data_o_net,
din_ch3 => adc_ch3_dbg_data_o_net,
dout_ch0 => bpf_ch0_o_net,
dout_ch1 => bpf_ch1_o_net,
dout_ch2 => bpf_ch2_o_net,
dout_ch3 => bpf_ch3_o_net
);
concat: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert12_dout_net_x2,
in1 => reinterpret1_output_port_net,
y => concat_y_net_x0
);
concat1: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => valid_ds_down_x2,
in1 => reinterpret2_output_port_net,
y => concat1_y_net_x0
);
concat2: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert9_dout_net_x2,
in1 => reinterpret3_output_port_net,
y => concat2_y_net_x0
);
concat3: entity work.concat_43e7f055fa
port map (
ce => '0',
clk => '0',
clr => '0',
in0(0) => assert10_dout_net_x2,
in1 => reinterpret4_output_port_net,
y => concat3_y_net_x0
);
constant10: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant10_op_net_x0
);
constant11: entity work.constant_963ed6358a
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant11_op_net_x0
);
constant15: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant15_op_net_x1
);
constant3: entity work.constant_6293007044
port map (
ce => '0',
clk => '0',
clr => '0',
op(0) => constant3_op_net_x1
);
convert_filt_fda412c1bf: entity work.convert_filt_entity_fda412c1bf
port map (
din => down_sample_q_net_x4,
dout => reinterpret5_output_port_net_x1
);
dds_sub_a4b6b880f6: entity work.dds_sub_entity_a4b6b880f6
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_01_cosine => register_q_net_x12,
dds_01_sine => register_q_net_x13,
dds_23_cosine => register_q_net_x14,
dds_23_sine => register_q_net_x15
);
delta_sigma_fofb_ee61e649ea: entity work.delta_sigma_fofb_entity_ee61e649ea
port map (
a => down_sample2_q_net_x20,
b => down_sample1_q_net_x20,
c => down_sample2_q_net_x21,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
ce_logic_2240 => ce_logic_2240_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
d => down_sample1_q_net_x21,
ds_thres => del_sig_div_fofb_thres_i_net,
q => assert8_dout_net_x1,
q_valid => assert9_dout_net_x1,
sum_valid => assert12_dout_net_x1,
sum_x0 => assert11_dout_net_x1,
x => assert5_dout_net_x1,
x_valid => assert10_dout_net_x1,
y => dout_down_x1,
y_valid => valid_ds_down_x1
);
delta_sigma_monit_a8f8b81626: entity work.delta_sigma_monit_entity_a8f8b81626
port map (
a => down_sample2_q_net_x5,
b => down_sample1_q_net_x5,
c => down_sample3_q_net_x5,
ce_1 => ce_1_sg_x96,
ce_10000 => ce_10000_sg_x2,
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
ce_4480 => ce_4480_sg_x9,
ce_44800000 => ce_44800000_sg_x2,
ce_5000 => ce_5000_sg_x9,
ce_logic_22400000 => ce_logic_22400000_sg_x1,
clk_1 => clk_1_sg_x96,
clk_10000 => clk_10000_sg_x2,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
clk_4480 => clk_4480_sg_x9,
clk_44800000 => clk_44800000_sg_x2,
clk_5000 => clk_5000_sg_x9,
d => down_sample4_q_net_x5,
ds_thres => del_sig_div_monit_thres_i_net,
q => assert4_dout_net_x1,
q_valid => assert9_dout_net_x2,
sum_valid => assert10_dout_net_x2,
sum_x0 => assert5_dout_net_x2,
x => assert11_dout_net_x2,
x_valid => assert12_dout_net_x2,
y => dout_down_x2,
y_valid => valid_ds_down_x2
);
delta_sigma_tbt_bbfa8a8a69: entity work.delta_sigma_tbt_entity_bbfa8a8a69
port map (
a => down_sample2_q_net_x34,
b => down_sample1_q_net_x34,
c => down_sample2_q_net_x35,
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
ce_logic_70 => ce_logic_70_sg_x1,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
d => down_sample1_q_net_x35,
ds_thres => del_sig_div_tbt_thres_i_net,
q => assert8_dout_net_x2,
q_valid => assert9_dout_net_x3,
sum_valid => assert12_dout_net_x3,
sum_x0 => assert11_dout_net_x3,
x => assert5_dout_net_x3,
x_valid => assert10_dout_net_x3,
y => dout_down_x3,
y_valid => valid_ds_down_x3
);
fofb_amp_8b25d4b0b6: entity work.fofb_amp_entity_8b25d4b0b6
port map (
ce_1 => ce_1_sg_x96,
ce_1120 => ce_1120_sg_x32,
ce_2240 => ce_2240_sg_x28,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_1120 => clk_1120_sg_x32,
clk_2240 => clk_2240_sg_x28,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x20,
amp_out1 => down_sample1_q_net_x20,
amp_out2 => down_sample2_q_net_x21,
amp_out3 => down_sample1_q_net_x21,
fofb_amp0 => fofb_amp_ch1_o_net,
fofb_amp0_x0 => fofb_amp_ch0_o_net,
fofb_amp0_x1 => fofb_pha_ch1_o_net,
fofb_amp0_x2 => fofb_pha_ch0_o_net,
fofb_amp0_x3 => fofb_decim_ch1_i_o_net,
fofb_amp0_x4 => fofb_decim_ch0_i_o_net,
fofb_amp0_x5 => fofb_decim_ch1_q_o_net,
fofb_amp0_x6 => fofb_decim_ch0_q_o_net,
fofb_amp0_x7 => cic_fofb_q_01_missing_o_net,
fofb_amp1 => fofb_amp_ch3_o_net,
fofb_amp1_x0 => fofb_amp_ch2_o_net,
fofb_amp1_x1 => fofb_pha_ch3_o_net,
fofb_amp1_x2 => fofb_pha_ch2_o_net,
fofb_amp1_x3 => fofb_decim_ch3_i_o_net,
fofb_amp1_x4 => fofb_decim_ch2_i_o_net,
fofb_amp1_x5 => fofb_decim_ch3_q_o_net,
fofb_amp1_x6 => fofb_decim_ch2_q_o_net,
fofb_amp1_x7 => cic_fofb_q_23_missing_o_net
);
k_fofb_mult3_697accc8e2: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert5_dout_net_x1,
in2 => kx_i_net,
vld_in => assert10_dout_net_x1,
out1 => x_fofb_o_net,
vld_out => x_fofb_valid_o_net
);
k_fofb_mult4_102b49a84e: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => dout_down_x1,
in2 => ky_i_net,
vld_in => valid_ds_down_x1,
out1 => y_fofb_o_net,
vld_out => y_fofb_valid_o_net
);
k_fofb_mult5_ed47def699: entity work.k_fofb_mult3_entity_697accc8e2
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert8_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x1,
out1 => q_fofb_o_net,
vld_out => q_fofb_valid_o_net
);
k_monit_1_mult2_30ad492eba: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret1_output_port_net_x1,
in2 => ky_i_net,
vld_in => ufix_to_bool1_dout_net_x1,
out1 => y_monit_1_o_net,
vld_out => y_monit_1_valid_o_net
);
k_monit_1_mult6_71da64dfef: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret2_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool2_dout_net_x1,
out1 => q_monit_1_o_net,
vld_out => q_monit_1_valid_o_net
);
k_monit_1_mult_016885a3ac: entity work.k_monit_1_mult_entity_016885a3ac
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret3_output_port_net_x1,
in2 => kx_i_net,
vld_in => ufix_to_bool_dout_net_x1,
out1 => x_monit_1_o_net,
vld_out => x_monit_1_valid_o_net
);
k_monit_mult3_8a778fb5f4: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert11_dout_net_x2,
in2 => kx_i_net,
vld_in => assert12_dout_net_x2,
out1 => x_monit_o_net,
vld_out => x_monit_valid_o_net
);
k_monit_mult4_1b07b5102a: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => dout_down_x2,
in2 => ky_i_net,
vld_in => valid_ds_down_x2,
out1 => y_monit_o_net,
vld_out => y_monit_valid_o_net
);
k_monit_mult5_a064f6aaae: entity work.k_monit_mult3_entity_8a778fb5f4
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert4_dout_net_x1,
in2 => kx_i_net,
vld_in => assert9_dout_net_x2,
out1 => q_monit_o_net,
vld_out => q_monit_valid_o_net
);
k_tbt_mult1_cebfa469e3: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => dout_down_x3,
in2 => ky_i_net,
vld_in => valid_ds_down_x3,
out1 => y_tbt_o_net,
vld_out => y_tbt_valid_o_net
);
k_tbt_mult2_2b721a52a5: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert8_dout_net_x2,
in2 => kx_i_net,
vld_in => assert9_dout_net_x3,
out1 => q_tbt_o_net,
vld_out => q_tbt_valid_o_net
);
k_tbt_mult_b8fafff255: entity work.k_tbt_mult_entity_b8fafff255
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert5_dout_net_x3,
in2 => kx_i_net,
vld_in => assert10_dout_net_x3,
out1 => x_tbt_o_net,
vld_out => x_tbt_valid_o_net
);
ksum_fofb_mult4_ac3ed97096: entity work.ksum_fofb_mult4_entity_ac3ed97096
port map (
ce_2 => ce_2_sg_x38,
ce_2240 => ce_2240_sg_x28,
clk_2 => clk_2_sg_x38,
clk_2240 => clk_2240_sg_x28,
in1 => assert11_dout_net_x1,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x1,
out1 => sum_fofb_o_net,
vld_out => sum_fofb_valid_o_net
);
ksum_monit_1_mult1_c66dc07078: entity work.ksum_monit_1_mult1_entity_c66dc07078
port map (
ce_2 => ce_2_sg_x38,
ce_224000000 => ce_224000000_sg_x7,
clk_2 => clk_2_sg_x38,
clk_224000000 => clk_224000000_sg_x7,
in1 => reinterpret4_output_port_net_x1,
in2 => ksum_i_net,
vld_in => ufix_to_bool3_dout_net_x1,
out1 => sum_monit_1_o_net,
vld_out => sum_monit_1_valid_o_net
);
ksum_monit_mult2_31877b6d2b: entity work.ksum_monit_mult2_entity_31877b6d2b
port map (
ce_2 => ce_2_sg_x38,
ce_22400000 => ce_22400000_sg_x28,
clk_2 => clk_2_sg_x38,
clk_22400000 => clk_22400000_sg_x28,
in1 => assert5_dout_net_x2,
in2 => ksum_i_net,
vld_in => assert10_dout_net_x2,
out1 => sum_monit_o_net,
vld_out => sum_monit_valid_o_net
);
ksum_tbt_mult3_e0be30d675: entity work.ksum_tbt_mult3_entity_e0be30d675
port map (
ce_2 => ce_2_sg_x38,
ce_70 => ce_70_sg_x27,
clk_2 => clk_2_sg_x38,
clk_70 => clk_70_sg_x27,
in1 => assert11_dout_net_x3,
in2 => ksum_i_net,
vld_in => assert12_dout_net_x3,
out1 => sum_tbt_o_net,
vld_out => sum_tbt_valid_o_net
);
mixer_a1cd828545: entity work.mixer_entity_a1cd828545
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ch_in0 => register1_q_net_x6,
ch_in1 => register1_q_net_x7,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
dds_cosine_0 => register_q_net_x12,
dds_cosine_1 => register_q_net_x14,
dds_msine_0 => register_q_net_x13,
dds_msine_1 => register_q_net_x15,
dds_valid_0 => constant15_op_net_x1,
dds_valid_1 => constant3_op_net_x1,
din0 => register_q_net_x31,
din1 => register_q_net_x32,
ch_out0 => register3_q_net_x15,
ch_out1 => register3_q_net_x16,
i_out0 => register4_q_net_x14,
i_out1 => register4_q_net_x15,
q_out0 => register5_q_net_x14,
q_out1 => register5_q_net_x15,
tddm_mixer => mix_ch1_i_o_net,
tddm_mixer_x0 => mix_ch0_i_o_net,
tddm_mixer_x1 => mix_ch1_q_o_net,
tddm_mixer_x2 => mix_ch0_q_o_net,
tddm_mixer_x3 => mix_ch3_i_o_net,
tddm_mixer_x4 => mix_ch2_i_o_net,
tddm_mixer_x5 => mix_ch3_q_o_net,
tddm_mixer_x6 => mix_ch2_q_o_net
);
monit_amp_44da74e268: entity work.monit_amp_entity_44da74e268
port map (
ce_1 => ce_1_sg_x96,
ce_1400000 => ce_1400000_sg_x3,
ce_22400000 => ce_22400000_sg_x28,
ce_2800000 => ce_2800000_sg_x4,
ce_560 => ce_560_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_1400000 => ce_logic_1400000_sg_x2,
ce_logic_2800000 => ce_logic_2800000_sg_x2,
ce_logic_560 => ce_logic_560_sg_x3,
ch_in => ch_out_x2,
clk_1 => clk_1_sg_x96,
clk_1400000 => clk_1400000_sg_x3,
clk_22400000 => clk_22400000_sg_x28,
clk_2800000 => clk_2800000_sg_x4,
clk_560 => clk_560_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din => dout_x2,
amp_out0 => down_sample2_q_net_x5,
amp_out1 => down_sample1_q_net_x5,
amp_out2 => down_sample3_q_net_x5,
amp_out3 => down_sample4_q_net_x5,
monit_amp_c => monit_amp_ch1_o_net,
monit_amp_c_x0 => monit_amp_ch0_o_net,
monit_amp_c_x1 => monit_amp_ch2_o_net,
monit_amp_c_x2 => monit_amp_ch3_o_net,
monit_amp_c_x3 => monit_cfir_incorrect_o_net,
monit_amp_c_x4 => monit_cic_unexpected_o_net,
monit_amp_c_x5 => monit_pfir_incorrect_o_net
);
monit_pos_1_522c8cf08d: entity work.monit_pos_1_entity_522c8cf08d
port map (
ce_1 => ce_1_sg_x96,
ce_224000000 => ce_224000000_sg_x7,
ce_5600000 => ce_5600000_sg_x12,
ce_56000000 => ce_56000000_sg_x5,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
ch_in => down_sample_q_net_x3,
clk_1 => clk_1_sg_x96,
clk_224000000 => clk_224000000_sg_x7,
clk_5600000 => clk_5600000_sg_x12,
clk_56000000 => clk_56000000_sg_x5,
din => reinterpret5_output_port_net_x1,
monit_1_pos_q => reinterpret2_output_port_net_x1,
monit_1_pos_x => reinterpret3_output_port_net_x1,
monit_1_pos_y => reinterpret1_output_port_net_x1,
monit_1_sum => reinterpret4_output_port_net_x1,
monit_1_vld_q => ufix_to_bool2_dout_net_x1,
monit_1_vld_sum => ufix_to_bool3_dout_net_x1,
monit_1_vld_x => ufix_to_bool_dout_net_x1,
monit_1_vld_y => ufix_to_bool1_dout_net_x1,
monit_pos_1_c_x0 => monit_pos_1_incorrect_o_net
);
register1: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch1_i_net,
en => "1",
rst => "0",
q => adc_ch1_dbg_data_o_net
);
register2: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch2_i_net,
en => "1",
rst => "0",
q => adc_ch2_dbg_data_o_net
);
register3: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch3_i_net,
en => "1",
rst => "0",
q => adc_ch3_dbg_data_o_net
);
register_x0: entity work.xlregister
generic map (
d_width => 16,
init_value => b"0000000000000000"
)
port map (
ce => ce_2_sg_x38,
clk => clk_2_sg_x38,
d => adc_ch0_i_net,
en => "1",
rst => "0",
q => adc_ch0_dbg_data_o_net
);
reinterpret1: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert11_dout_net_x2,
output_port => reinterpret1_output_port_net
);
reinterpret2: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => dout_down_x2,
output_port => reinterpret2_output_port_net
);
reinterpret3: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert4_dout_net_x1,
output_port => reinterpret3_output_port_net
);
reinterpret4: entity work.reinterpret_c3c0e847be
port map (
ce => '0',
clk => '0',
clr => '0',
input_port => assert5_dout_net_x2,
output_port => reinterpret4_output_port_net
);
tbt_amp_cbd277bb0c: entity work.tbt_amp_entity_cbd277bb0c
port map (
ce_1 => ce_1_sg_x96,
ce_35 => ce_35_sg_x22,
ce_70 => ce_70_sg_x27,
ce_logic_1 => ce_logic_1_sg_x20,
ch_in0 => register3_q_net_x15,
ch_in1 => register3_q_net_x16,
clk_1 => clk_1_sg_x96,
clk_35 => clk_35_sg_x22,
clk_70 => clk_70_sg_x27,
i_in0 => register4_q_net_x14,
i_in1 => register4_q_net_x15,
q_in0 => register5_q_net_x14,
q_in1 => register5_q_net_x15,
amp_out0 => down_sample2_q_net_x34,
amp_out1 => down_sample1_q_net_x34,
amp_out2 => down_sample2_q_net_x35,
amp_out3 => down_sample1_q_net_x35,
tbt_amp0 => tbt_amp_ch1_o_net,
tbt_amp0_x0 => tbt_amp_ch0_o_net,
tbt_amp0_x1 => tbt_pha_ch1_o_net,
tbt_amp0_x2 => tbt_pha_ch0_o_net,
tbt_amp0_x3 => tbt_decim_ch01_incorrect_o_net,
tbt_amp0_x4 => tbt_decim_ch1_i_o_net,
tbt_amp0_x5 => tbt_decim_ch0_i_o_net,
tbt_amp0_x6 => tbt_decim_ch1_q_o_net,
tbt_amp0_x7 => tbt_decim_ch0_q_o_net,
tbt_amp1 => tbt_amp_ch3_o_net,
tbt_amp1_x0 => tbt_amp_ch2_o_net,
tbt_amp1_x1 => tbt_pha_ch3_o_net,
tbt_amp1_x2 => tbt_pha_ch2_o_net,
tbt_amp1_x3 => tbt_decim_ch23_incorrect_o_net,
tbt_amp1_x4 => tbt_decim_ch3_i_o_net,
tbt_amp1_x5 => tbt_decim_ch2_i_o_net,
tbt_amp1_x6 => tbt_decim_ch3_q_o_net,
tbt_amp1_x7 => tbt_decim_ch2_q_o_net
);
tdm_mix_54ce67e6e8: entity work.tdm_mix_entity_54ce67e6e8
port map (
ce_1 => ce_1_sg_x96,
ce_2 => ce_2_sg_x38,
ce_logic_1 => ce_logic_1_sg_x20,
clk_1 => clk_1_sg_x96,
clk_2 => clk_2_sg_x38,
din_ch0 => bpf_ch0_o_net,
din_ch1 => bpf_ch1_o_net,
din_ch2 => bpf_ch2_o_net,
din_ch3 => bpf_ch3_o_net,
ch_out0 => register1_q_net_x6,
ch_out1 => register1_q_net_x7,
dout0 => register_q_net_x31,
dout1 => register_q_net_x32
);
tdm_monit_1_746ecf54b0: entity work.tdm_monit_1_entity_746ecf54b0
port map (
ce_1 => ce_1_sg_x96,
ce_22400000 => ce_22400000_sg_x28,
ce_2500 => ce_2500_sg_x3,
ce_5600000 => ce_5600000_sg_x12,
ce_logic_5600000 => ce_logic_5600000_sg_x2,
clk_1 => clk_1_sg_x96,
clk_22400000 => clk_22400000_sg_x28,
clk_2500 => clk_2500_sg_x3,
clk_5600000 => clk_5600000_sg_x12,
din_ch0 => concat_y_net_x0,
din_ch1 => concat1_y_net_x0,
din_ch2 => concat2_y_net_x0,
din_ch3 => concat3_y_net_x0,
rst => constant11_op_net_x0,
ch_out => down_sample_q_net_x3,
dout => down_sample_q_net_x4
);
tdm_monit_6e38292ecb: entity work.tdm_monit_entity_6e38292ecb
port map (
ce_1 => ce_1_sg_x96,
ce_2240 => ce_2240_sg_x28,
ce_560 => ce_560_sg_x3,
ce_logic_560 => ce_logic_560_sg_x3,
clk_1 => clk_1_sg_x96,
clk_2240 => clk_2240_sg_x28,
clk_560 => clk_560_sg_x3,
din_ch0 => down_sample2_q_net_x20,
din_ch1 => down_sample1_q_net_x20,
din_ch2 => down_sample2_q_net_x21,
din_ch3 => down_sample1_q_net_x21,
rst => constant10_op_net_x0,
ch_out => ch_out_x2,
dout => dout_x2
);
end structural;
| lgpl-3.0 | dc84cda343d2ca0c9843fde6bed83731 | 0.592972 | 2.658169 | false | false | false | false |
wltr/common-vhdl | communication/uart/src/rtl/uart_tx.vhd | 1 | 4,957 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Send asynchronous serial data.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.lfsr_pkg.all;
entity uart_tx is
generic (
-- Data bit width
data_width_g : positive := 8;
-- Parity bit: 0 = None, 1 = Odd, 2 = Even
parity_g : natural range 0 to 2 := 0;
-- Number of stop bits
stop_bits_g : positive range 1 to 2 := 1;
-- Number of clock cycles per bit
num_ticks_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
data_i : in std_ulogic_vector(data_width_g - 1 downto 0);
data_en_i : in std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Transmission line
tx_o : out std_ulogic);
end entity uart_tx;
architecture rtl of uart_tx is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- Transmission bit length
constant tx_len_c : natural := 1 + data_width_g + stop_bits_g + natural(ceil(real(parity_g / 2)));
-- LFSR counter bit length
constant len_c : natural := lfsr_length(tx_len_c);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : std_ulogic_vector(len_c - 1 downto 0);
signal data : std_ulogic_vector(tx_len_c - 1 downto 0);
signal busy : std_ulogic;
signal done : std_ulogic;
signal tx : std_ulogic;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal parity_init : std_ulogic;
signal parity_bit : std_ulogic;
signal parity : std_ulogic_vector(data_i'range);
signal bit_strobe : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= busy;
done_o <= done;
tx_o <= tx;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Set parity bit's initial value
parity_init <= '1' when parity_g = 1 else '0';
-- Compute parity bit
parity(0) <= data_i(0) xor parity_init;
parity_gen : for i in 1 to parity'high generate
parity(i) <= data_i(i) xor parity(i - 1);
end generate parity_gen;
parity_bit <= parity(parity'high);
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Generate bit strobe
lfsr_strobe_gen_inst : entity work.lfsr_strobe_generator
generic map (
period_g => num_ticks_g,
preset_value_g => 0)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => busy,
pre_i => done,
strobe_o => bit_strobe);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Transmit
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= seed_c;
data <= (others => '1');
busy <= '0';
done <= '0';
tx <= '1';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
--Defaults
done <= '0';
if rst_syn_i = '1' then
reset;
else
if busy = '0' and data_en_i = '1' then
if parity_g = 0 then
data(data_i'high + 1 downto 0) <= data_i & '0';
else
data(data_i'high + 2 downto 0) <= parity_bit & data_i & '0';
end if;
busy <= '1';
elsif busy = '1' and bit_strobe = '1' then
data <= '1' & data(data'high downto data'low + 1);
tx <= data(data'low);
if count = lfsr_shift(seed_c, tx_len_c - 1) then
reset;
done <= '1';
else
count <= lfsr_shift(count);
end if;
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 21baf272bba3d84e51f1541a165b69a1 | 0.415776 | 4.288062 | false | false | false | false |
wltr/common-vhdl | platforms/microsemi/reset_generator/src/rtl/microsemi_reset_generator.vhd | 1 | 2,963 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Generate reset according to Microsemi application note AC380.
-- The reset is activated asynchronously and deactivated synchronously.
-- The asynchronous reset input is supposed to be connected to a weak
-- external pull-up resistor.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Component library
-- TODO: Has to be adjusted to the used device
library proasic3;
use proasic3.all;
entity microsemi_reset_generator is
generic (
-- Number of delay stages
num_delay_g : positive := 4;
-- Reset active state
active_g : std_ulogic := '0');
port (
-- Clock
clk_i : in std_ulogic;
-- Asynchronous reset input
rst_asy_io : inout std_logic;
-- Reset output
rst_o : out std_ulogic);
end entity microsemi_reset_generator;
architecture rtl of microsemi_reset_generator is
------------------------------------------------------------------------------
-- Components
------------------------------------------------------------------------------
-- Bi-directional buffer
component BIBUF_LVCMOS33
port (
PAD : inout std_logic;
D : in std_logic;
E : in std_logic;
Y : out std_logic);
end component;
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal rst : std_ulogic_vector(num_delay_g - 1 downto 0);
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal rst_asy : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
rst_o <= rst(rst'high);
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
-- Bi-directional buffer with enabled output forced to '0'
BIBUF_LVCMOS33_inst : BIBUF_LVCMOS33
port map (
PAD => rst_asy_io,
D => '0',
E => '1',
Y => rst_asy);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy) is
begin -- process regs
if rst_asy = '1' then
rst <= (others => active_g);
elsif rising_edge(clk_i) then
rst <= rst(rst'high - 1 downto rst'low) & (not active_g);
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 443332bf4fa2933732cadf4d6c73bdaf | 0.39622 | 5.487037 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_un_cross/cross_uncross_core/delay_inv_ch.vhd | 1 | 2,845 | ------------------------------------------------------------------------------
-- Title : Delay to Invert one Channel pair
------------------------------------------------------------------------------
-- Author : José Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This design counts a delay time which is the cnt_lmt_i input
-- multiplied by period of clk_i input.
-- The trigger input (trg_i) is a pulse what represents a change
-- in state of crossbar switch.
-- Only one pair of channels is covered by this core.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-02-18 1.0 jose.berkenbrock Created
-- 2013-02-22 2.0 jose.berkenbrock Swap_i supressed
-- 2013-07-01 2.1 lucas.russo Changed to synchronous resets
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library unisim;
--use unisim.vcomponents.all;
entity delay_inv_ch is
generic(
g_delay_vec_width : natural range 0 to 16 := 10
);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
trg_i : in std_logic; -- trigger
cnt_lmt_i : in std_logic_vector(g_delay_vec_width-1 downto 0);
-- counter limit
en_o : out std_logic
);
end delay_inv_ch;
architecture rtl of delay_inv_ch is
signal count : natural range 0 to 2**g_delay_vec_width-1;
signal cnst_cnt_lmt : natural range 0 to 2**g_delay_vec_width-1;
signal en : std_logic;
begin
cnst_cnt_lmt <= (to_integer(unsigned(cnt_lmt_i))+1);
p_counter: process(clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
count <= 0;
else
if trg_i = '1' then
count <= cnst_cnt_lmt;
elsif count /= 0 then
count <= count - 1;
end if;
end if;
end if;
end process p_counter;
p_output : process(clk_i)
begin
if (rising_edge(clk_i)) then
if rst_n_i = '0' then
en <= '0';
else
if count = 1 then
en <= '1';
elsif count = 0 then
en <= '0';
end if;
end if;
end if;
end process p_output;
en_o <= en;
end rtl;
| lgpl-3.0 | e52bda052b5687ba4462b75b5d603595 | 0.445851 | 4.163982 | false | false | false | false |
wltr/common-vhdl | generic/strobe_generator/src/rtl/strobe_generator.vhd | 1 | 2,652 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Generate a strobe when a counter reaches a certain value.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity strobe_generator is
generic (
-- Initial value of counter
init_value_g : natural := 0;
-- Counter bit width
bit_width_g : positive := 8);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Number of clock cycles in between strobes
period_i : in std_ulogic_vector(bit_width_g - 1 downto 0);
-- Preset inputs
pre_i : in std_ulogic;
pre_value_i : in std_ulogic_vector(bit_width_g - 1 downto 0);
-- Strobe signal
strobe_o : out std_ulogic);
end entity strobe_generator;
architecture rtl of strobe_generator is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal count : unsigned(bit_width_g - 1 downto 0) := (others => '0');
signal strobe : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
strobe_o <= strobe;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Generate strobe
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
count <= to_unsigned(init_value_g, count'length);
strobe <= '0';
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
-- Defaults
strobe <= '0';
if rst_syn_i = '1' then
reset;
elsif pre_i = '1' then
-- Preset counter to specified value
count <= unsigned(pre_value_i);
elsif en_i = '1' then
if count < unsigned(period_i) - 1 then
-- Increment counter
count <= count + 1;
else
-- Reset counter
count <= to_unsigned(init_value_g, count'length);
-- Generate strobe signal
strobe <= '1';
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 75d3abfcd6fb231c6f8799ad9794b1ad | 0.447964 | 4.612174 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/space_shooter_demo/de2_space_shooter_demo_top.vhd | 1 | 2,429 | library ieee;
use ieee.std_logic_1164.all;
-- VAGE (VHDL Advanced Game Engine) demo using the 'Space Shooter' game demo
-- and the Altera DE2 board as a hardware platform. The purpose of this file
-- is simply to instantiate the game top entity. It should not contain any -
-- gamerelated code. This is also a perfect place for vendor-specific and
-- board-specific code, such as PLLs.
entity de2_space_shooter_demo_top is
-- Port names as defined in the standard DE2 settings file.
port (
-- 50 MHz clock provided by the DE2 board
clock_50: in std_logic;
-- Input toggle switches
sw: in std_logic_vector(17 downto 0);
-- Input push-button switches, active low
key: in std_logic_vector(3 downto 0);
-- Green leds
ledg: out std_logic_vector(7 downto 0);
vga_clk: out std_logic;
vga_blank: out std_logic;
vga_hs: out std_logic;
vga_vs: out std_logic;
vga_sync: out std_logic;
vga_r: out std_logic_vector(9 downto 0);
vga_g: out std_logic_vector(9 downto 0);
vga_b: out std_logic_vector(9 downto 0)
);
end;
architecture rtl of de2_space_shooter_demo_top is
-- Component declaration for the PLL used to generate the 25 MHz pixel
-- clock from the board 50 MHz system clock
component video_pll
port(
inclk0: in std_logic := '0';
c0: out std_logic
);
end component;
signal vga_pll_clock_out: std_logic;
begin
-- Instantiate the game top entity
game: entity work.space_shooter_demo_top
port map(
clock_50_Mhz => clock_50,
reset => sw(17),
debug_bits => ledg,
vga_clock_in => vga_pll_clock_out,
vga_clock_out => vga_clk,
vga_blank => vga_blank,
vga_n_hsync => vga_hs,
vga_n_vsync => vga_vs,
vga_n_sync => vga_sync,
vga_red => vga_r,
vga_green => vga_g,
vga_blue => vga_b,
input_switches => sw(1 downto 0),
input_buttons => not key
);
-- Instantiate a PLL to generate the pixel clock frequency (~25 MHZ),
-- using the DE2 50Mhz clock as input
video_PLL_inst : video_PLL port map (
inclk0 => clock_50,
c0 => vga_pll_clock_out
);
end; | unlicense | 0ba687e828a30015b314dd4bab31df9b | 0.570193 | 3.719755 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_un_cross/xwb_bpm_swap.vhd | 1 | 6,151 | ------------------------------------------------------------------------------
-- Title : Wishbone BPM SWAP interface
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: Wishbone interface with BPM Swap core.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-04-11 1.0 jose.berkenbrock Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
-- DSP Cores
use work.dsp_cores_pkg.all;
-- Register Bank
use work.bpm_swap_wbgen2_pkg.all;
entity xwb_bpm_swap is
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
mode1_o : out std_logic_vector(1 downto 0);
mode2_o : out std_logic_vector(1 downto 0);
wdw_rst_o : out std_logic; -- Reset Windowing module
wdw_sw_clk_i : in std_logic; -- Switching clock from Windowing module
wdw_use_o : out std_logic; -- Use Windowing module
wdw_dly_o : out std_logic_vector(15 downto 0); -- Delay to apply the window
-- Output to RFFE board
clk_swap_o : out std_logic;
clk_swap_en_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end xwb_bpm_swap;
architecture rtl of xwb_bpm_swap is
begin
cmp_wb_bpm_swap : wb_bpm_swap
generic map
(
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
fs_rst_n_i => fs_rst_n_i,
fs_clk_i => fs_clk_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_slv_i.adr,
wb_dat_i => wb_slv_i.dat,
wb_dat_o => wb_slv_o.dat,
wb_sel_i => wb_slv_i.sel,
wb_we_i => wb_slv_i.we,
wb_cyc_i => wb_slv_i.cyc,
wb_stb_i => wb_slv_i.stb,
wb_ack_o => wb_slv_o.ack,
wb_stall_o => wb_slv_o.stall,
-----------------------------
-- External ports
-----------------------------
-- input from ADC FMC board:
cha_i => cha_i,
chb_i => chb_i,
chc_i => chc_i,
chd_i => chd_i,
-- output to data processing level:
cha_o => cha_o,
chb_o => chb_o,
chc_o => chc_o,
chd_o => chd_o,
mode1_o => mode1_o,
mode2_o => mode2_o,
wdw_rst_o => wdw_rst_o,
wdw_sw_clk_i => wdw_sw_clk_i,
wdw_use_o => wdw_use_o,
wdw_dly_o => wdw_dly_o,
-- output to RFFE board:
clk_swap_o => clk_swap_o,
clk_swap_en_o => clk_swap_en_o,
flag1_o => flag1_o,
flag2_o => flag2_o,
ctrl1_o => ctrl1_o,
ctrl2_o => ctrl2_o
);
end rtl;
| lgpl-3.0 | 4f17fe64d6758cf5be55f9f4f318b2e9 | 0.334742 | 4.71341 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/cc_cmplr_v3_0_e85aeee534196d83.vhd | 1 | 6,150 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_e85aeee534196d83.vhd when simulating
-- the core, cc_cmplr_v3_0_e85aeee534196d83. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_e85aeee534196d83 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_e85aeee534196d83;
ARCHITECTURE cc_cmplr_v3_0_e85aeee534196d83_a OF cc_cmplr_v3_0_e85aeee534196d83 IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_e85aeee534196d83
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_e85aeee534196d83 USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 61,
c_c2 => 61,
c_c3 => 61,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2240,
c_component_name => "cc_cmplr_v3_0_e85aeee534196d83",
c_diff_delay => 2,
c_family => "virtex6",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 61,
c_i2 => 61,
c_i3 => 61,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 2500,
c_min_rate => 2500,
c_num_channels => 4,
c_num_stages => 3,
c_output_width => 61,
c_rate => 2500,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "virtex6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_e85aeee534196d83
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_e85aeee534196d83_a;
| lgpl-3.0 | 82dab79a4a2bc3ee1351993f843e61fb | 0.557724 | 3.662895 | false | false | false | false |
lerwys/GitTest | hdl/platform/artix7/multiplier_u16x16_DSP.vhd | 1 | 4,286 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file multiplier_u16x16_DSP.vhd when simulating
-- the core, multiplier_u16x16_DSP. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY multiplier_u16x16_DSP IS
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END multiplier_u16x16_DSP;
ARCHITECTURE multiplier_u16x16_DSP_a OF multiplier_u16x16_DSP IS
-- synthesis translate_off
COMPONENT wrapped_multiplier_u16x16_DSP
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_multiplier_u16x16_DSP USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 16,
c_b_type => 1,
c_b_value => "10000001",
c_b_width => 16,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 3,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 31,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_multiplier_u16x16_DSP
PORT MAP (
clk => clk,
a => a,
b => b,
p => p
);
-- synthesis translate_on
END multiplier_u16x16_DSP_a;
| lgpl-3.0 | 573e750517b7297fa048d0f43cb778b7 | 0.545497 | 4.478579 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/adventure_demo/adventure_demo_top.vhd | 1 | 9,161 | library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.input_types_pkg.all;
use work.graphics_types_pkg.all;
use work.text_mode_pkg.all;
use work.sprites_pkg.all;
use work.game_state_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.resource_data_pkg.all;
use work.resource_data_helper_pkg.all;
use work.npc_pkg.all;
use work.vga_pkg.all;
-- Top-level entity for the "Adventure" game demo using VAGE. On top of this
-- entity, there should be only a very simple wrapper intantiating this entity
-- and connecting its ports to the board used. It should be fairly easy to use
-- this entity in other hardware platforms, without any modifications.
entity adventure_demo_top is
port (
-- synchronous reset, used by all user logic
reset: in std_logic;
-- system clock used for all user logic
clock_50_Mhz: in std_logic;
-- VGA clock used by the video renderer; should be approximately
-- 25.715 MHz (25 MHz is acceptable)
vga_clock_in: in std_logic;
-- Same as VGA input clock, must be passed along to the video DAC chip
vga_clock_out: out std_logic;
-- VGA blank, low during horizontal or vertical retrace (pixels should be blank)
vga_blank: out std_logic;
-- VGA Hsync, low during horizontal synchronism pulse
vga_n_hsync: out std_logic;
-- VGA Vsync, low during vertical synchronism pulse
vga_n_vsync: out std_logic;
-- Composite sync for the ADV7123; if not used, should be tied low
vga_n_sync: out std_logic;
-- VGA red channel output
vga_red: out std_logic_vector(9 downto 0);
-- VGA green channel output
vga_green: out std_logic_vector(9 downto 0);
-- VGA blue channel output
vga_blue: out std_logic_vector(9 downto 0);
-- Input toggle switches, active high
input_switches: in std_logic_vector(1 downto 0);
-- Input push-button switches, active high
input_buttons: in std_logic_vector(3 downto 0);
-- Debug pins for debugging game logic (e.g., connecting to board leds)
debug_bits: out std_logic_vector(7 downto 0)
);
end;
architecture rtl of adventure_demo_top is
-- Medium-resolution time base (used for game state updates and
-- reading the inputs switches)
signal time_base_50_ms: std_logic;
-- Maximum value for the game time counter
constant GAME_TIMER_50_MS_MAX: integer := 1000;
-- Monotonic game time counter, updated every 50 ms. Can be used by
-- the game logic (eg., to animate or move sprites)
signal elapsed_time: integer range 0 to GAME_TIMER_50_MS_MAX;
-- Video engine output uses custom data type; we'll convert here to std_logic
signal vga_output_signals: vga_output_signals_type;
-- Array containing the position of each sprite on the screen; generated by
-- the game logic module and used as an input by the sprites engine
signal sprite_positions: point_array_type(GAME_SPRITES'range);
-- Each element is 'true' while the two corresponding sprites are colliding.
signal sprite_collisions: bool_vector(GAME_COLLISIONS'range);
-- Background image to be used by the video engine; currently, the game
-- logic is responsible for providing the video engine with a background tile
signal background_bitmap: paletted_bitmap_type(0 to 7, 0 to 7);
-- User logic must inform the NPC engine what are the target positions
-- for the NPCs; some types of AI (e.g., AI_FOLLOWER) use this value to
-- calculate their next position
signal npc_target_positions: point_array_type(GAME_NPCS'range);
-- The game engine (NPC engine, actually) calculates the NPC positions
-- and these values are handed over to the game logic
signal npc_positions: point_array_type(GAME_NPCS'range);
signal in_buttons: input_buttons_type;
signal game_state: game_state_type;
-- Text strgins displayed on the screen
signal text_mode_strings: text_mode_strings_type(0 to game_strings_count-1);
begin
----------------------------------------------------------------------------
-- Overall architecture description:
-- 1) Instantiate the game logic
-- 2) Instantiate the NPC engine
-- 3) Instantiate the game engine
-- 4) Select a background bitmap based on the current game state
-- 5) Convert signals between std_logic and custom data types. Internally,
-- we use custom types for better abstraction; at the interface, we use
-- std_logic for better portability and easier instantiation
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Section 1) Instantiate the game logic. This entity receives the raw game
-- data and events, and updates the game state accordingly.
----------------------------------------------------------------------------
logic: entity work.game_logic
port map(
clock => clock_50_Mhz,
reset => reset,
time_base_50_ms => time_base_50_ms,
npc_positions => npc_positions,
npc_target_positions => npc_target_positions,
sprite_collisions => sprite_collisions,
sprites_positions => sprite_positions,
input_buttons => in_buttons,
game_state => game_state,
debug_bits => debug_bits,
text_mode_strings => text_mode_strings
);
----------------------------------------------------------------------------
-- Section 2) Instantiate the NPC engine. This entity receives low-level
-- game data, and updates the NPC positions.
----------------------------------------------------------------------------
npc: entity work.npcs_engine
generic map (
NPC_DEFINITIONS => make_npcs_initial_values(GAME_NPCS)
) port map (
clock => clock_50_Mhz,
reset => reset,
time_base => time_base_50_ms,
npc_enables => (GAME_NPCS'range => true),
npc_target_positions => npc_target_positions,
npc_positions => npc_positions
);
----------------------------------------------------------------------------
-- Section 3) Instantiate the game engine. The game engine
-- performs basic functions such as calculating sprite collisions and
-- rendering the video output.
----------------------------------------------------------------------------
engine: entity work.game_engine
generic map (
SPRITES_INITIAL_VALUES => make_sprites_initial_values(GAME_SPRITES),
SPRITES_COLLISION_QUERY => make_sprites_collision_query(GAME_COLLISIONS)
) port map (
clock_50MHz => clock_50_Mhz,
reset => reset,
sprites_enabled => (GAME_SPRITES'range => true),
sprites_coordinates => sprite_positions,
sprite_collisions_results => sprite_collisions,
elapsed_time => elapsed_time,
time_base_50_ms => time_base_50_ms,
game_state => game_state,
background_bitmap => background_bitmap,
vga_clock_in => vga_clock_in,
vga_signals => vga_output_signals,
text_mode_strings => text_mode_strings
);
----------------------------------------------------------------------------
-- Section 4)
-- Select a background bitmap based on current game state (currently, this
-- is the only feedback we provide the player with)
with game_state select background_bitmap <=
get_bitmap_from_handle(BITMAP_GAME_OVER_TILE) when GS_GAME_OVER,
get_bitmap_from_handle(BITMAP_GAME_WON_TILE) when GS_GAME_WON,
get_bitmap_from_handle(BITMAP_FOREST_TILE) when others;
----------------------------------------------------------------------------
-- Section 5) Convert signals between std_logic and custom data types.
-- Internally, we use custom types for better abstraction; at the interface,
-- we use std_logic for better portability and easier instantiation.
-- Connect each pushbutton to the corresponding game input function
in_buttons <= (
up => input_buttons(3),
down => input_buttons(2),
left => input_buttons(1),
right => input_buttons(0),
fire => input_switches(0)
);
-- Connect each VGA output signal to the correspoding VGA pin or port
vga_clock_out <= vga_output_signals.vga_clock_out;
vga_blank <= vga_output_signals.blank;
vga_n_hsync <= vga_output_signals.hsync;
vga_n_vsync <= vga_output_signals.vsync;
vga_n_sync <= vga_output_signals.sync;
vga_red <= vga_output_signals.red;
vga_green <= vga_output_signals.green;
vga_blue <= vga_output_signals.blue;
end; | unlicense | 70eba8c8ef7da716fb4b79a999ecfe8a | 0.586726 | 4.364459 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/graphics_types_pkg.vhd | 1 | 2,329 | use work.colors_pkg.all;
-- Data types and functions for graphics operations.
package graphics_types_pkg is
subtype zoom_factor_type is integer range 1 to 2;
constant ZOOM_FACTOR: zoom_factor_type := 2;
constant SCREEN_WIDTH: integer := 640;
constant SCREEN_HEIGHT: integer := 480;
constant GAME_VIEWPORT_WIDTH: integer := SCREEN_WIDTH / ZOOM_FACTOR;
constant GAME_VIEWPORT_HEIGHT: integer := SCREEN_HEIGHT / ZOOM_FACTOR;
-- Maximum value for any screen coordinate
constant COORDINATE_VALUE_MAX: integer := 2047;
-- Pixel coordinates may be negative to represent objects off the screen
-- and to represent deltas (like a negative speed to make a sprite move left or up)
subtype pixel_coordinate_type is integer range -COORDINATE_VALUE_MAX to COORDINATE_VALUE_MAX;
-- Data type representing a point on the screen or in a graphics data
-- structure (e.g., bitmap)
type point_type is record
x, y: pixel_coordinate_type;
end record;
-- Data type for an array of pixel coordinates
type point_array_type is array (natural range <>) of point_type;
type rectangle_type is record
left, top, right, bottom: pixel_coordinate_type;
end record;
-- A bitmap is a 2D array in which each element is a value from the palette
type paletted_bitmap_type is array (natural range <>, natural range <>) of palette_color_type;
function "+" (lhs, rhs: point_type) return point_type;
function "/" (lhs: point_type; rhs: integer) return point_type;
function is_in_view(position: point_type) return boolean;
end;
package body graphics_types_pkg is
-- Add two points by summing each axis' coordinates
function "+" (lhs, rhs: point_type) return point_type is begin
return (lhs.x + rhs.x, lhs.y + rhs.y);
end;
-- Divide a point by a scalar by dividing each coordinate by the scalar value
function "/" (lhs: point_type; rhs: integer) return point_type is begin
return (lhs.x / rhs, lhs.y / rhs);
end;
function is_in_view(position: point_type) return boolean is begin
return
position.x > 0 and position.x < GAME_VIEWPORT_WIDTH and
position.y > 0 and position.y < GAME_VIEWPORT_HEIGHT;
end;
end;
| unlicense | e0eb3737dd101cfa853d4562ff599e51 | 0.667669 | 3.981197 | false | false | false | false |
freecores/raggedstone | source/top_pci_7seg.vhd | 1 | 8,025 | --+-------------------------------------------------------------------------------------------------+
--| |
--| File: top.vhd |
--| |
--| Components: pci32lite.vhd |
--| pciwbsequ.vhd |
--| pcidmux.vhd |
--| pciregs.vhd |
--| pcipargen.vhd |
--| -- Libs -- |
--| ona.vhd |
--| |
--| Description: RS1 PCI Demo : (TOP) Main file. |
--| |
--| |
--| |
--+-------------------------------------------------------------------------------------------------+
--| |
--| Revision history : |
--| Date Version Author Description |
--| |
--| |
--| To do: |
--| |
--+-------------------------------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| LIBRARIES |
--+-----------------------------------------------------------------------------+
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--+-----------------------------------------------------------------------------+
--| ENTITY |
--+-----------------------------------------------------------------------------+
entity pci_7seg is
port (
-- General
PCI_CLK : in std_logic;
PCI_nRES : in std_logic;
-- PCI target 32bits
PCI_AD : inout std_logic_vector(31 downto 0);
PCI_CBE : in std_logic_vector(3 downto 0);
PCI_PAR : out std_logic;
PCI_nFRAME : in std_logic;
PCI_nIRDY : in std_logic;
PCI_nTRDY : out std_logic;
PCI_nDEVSEL : out std_logic;
PCI_nSTOP : out std_logic;
PCI_IDSEL : in std_logic;
PCI_nPERR : out std_logic;
PCI_nSERR : out std_logic;
PCI_nINT : out std_logic;
-- 7seg
DISP_SEL : inout std_logic_vector(3 downto 0);
DISP_LED : out std_logic_vector(6 downto 0);
-- debug signals
LED_INIT : out std_logic;
LED_ACCESS : out std_logic;
LED_ALIVE : out std_logic;
-- vga signals
hs : out std_logic;
vs : out std_logic;
red, grn, blu : out std_logic;
mclk : in std_logic
);
end pci_7seg;
--+-----------------------------------------------------------------------------+
--| ARCHITECTURE |
--+-----------------------------------------------------------------------------+
architecture pci_7seg_arch of pci_7seg is
--+-----------------------------------------------------------------------------+
--| COMPONENTS |
--+-----------------------------------------------------------------------------+
component pci32tlite
port (
-- General
clk33 : in std_logic;
nrst : in std_logic;
-- PCI target 32bits
ad : inout std_logic_vector(31 downto 0);
cbe : in std_logic_vector(3 downto 0);
par : out std_logic;
frame : in std_logic;
irdy : in std_logic;
trdy : out std_logic;
devsel : out std_logic;
stop : out std_logic;
idsel : in std_logic;
perr : out std_logic;
serr : out std_logic;
intb : out std_logic;
-- Master whisbone
wb_adr_o : out std_logic_vector(24 downto 1);
wb_dat_i : in std_logic_vector(15 downto 0);
wb_dat_o : out std_logic_vector(15 downto 0);
wb_sel_o : out std_logic_vector(1 downto 0);
wb_we_o : out std_logic;
wb_stb_o : out std_logic;
wb_cyc_o : out std_logic;
wb_ack_i : in std_logic;
wb_err_i : in std_logic;
wb_int_i : in std_logic;
-- debug signals
debug_init : out std_logic;
debug_access : out std_logic
);
end component;
component wb_7seg_new
port (
-- General
clk_i : in std_logic;
nrst_i : in std_logic;
-- Master whisbone
wb_adr_i : in std_logic_vector(24 downto 1);
wb_dat_o : out std_logic_vector(15 downto 0);
wb_dat_i : in std_logic_vector(15 downto 0);
wb_sel_i : in std_logic_vector(1 downto 0);
wb_we_i : in std_logic;
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
-- 7seg
DISP_SEL : inout std_logic_vector(3 downto 0);
DISP_LED : out std_logic_vector(6 downto 0)
);
end component;
component vgaController is
Port ( mclk : in std_logic;
hs : out std_logic;
vs : out std_logic;
red : out std_logic;
grn : out std_logic;
blu : out std_logic);
end component;
--+-----------------------------------------------------------------------------+
--| CONSTANTS |
--+-----------------------------------------------------------------------------+
--+-----------------------------------------------------------------------------+
--| SIGNALS |
--+-----------------------------------------------------------------------------+
signal wb_adr : std_logic_vector(24 downto 1);
signal wb_dat_out : std_logic_vector(15 downto 0);
signal wb_dat_in : std_logic_vector(15 downto 0);
signal wb_sel : std_logic_vector(1 downto 0);
signal wb_we : std_logic;
signal wb_stb : std_logic;
signal wb_cyc : std_logic;
signal wb_ack : std_logic;
signal wb_err : std_logic;
signal wb_int : std_logic;
begin
LED_ALIVE <= '1';
--+-------------------------------------------------------------------------+
--| Component instances |
--+-------------------------------------------------------------------------+
vga1: vgaController port map (mclk => mclk,
hs => hs,
vs => vs,
red => red,
grn => grn,
blu => blu);
--+-----------------------------------------+
--| PCI Target |
--+-----------------------------------------+
u_pci: component pci32tlite
port map(
clk33 => PCI_CLK,
nrst => PCI_nRES,
ad => PCI_AD,
cbe => PCI_CBE,
par => PCI_PAR,
frame => PCI_nFRAME,
irdy => PCI_nIRDY,
trdy => PCI_nTRDY,
devsel => PCI_nDEVSEL,
stop => PCI_nSTOP,
idsel => PCI_IDSEL,
perr => PCI_nPERR,
serr => PCI_nSERR,
intb => PCI_nINT,
wb_adr_o => wb_adr,
wb_dat_i => wb_dat_out,
wb_dat_o => wb_dat_in,
wb_sel_o => wb_sel,
wb_we_o => wb_we,
wb_stb_o => wb_stb,
wb_cyc_o => wb_cyc,
wb_ack_i => wb_ack,
wb_err_i => wb_err,
wb_int_i => wb_int,
debug_init => LED_INIT,
debug_access => LED_ACCESS
);
--+-----------------------------------------+
--| WB-7seg |
--+-----------------------------------------+
u_wb: component wb_7seg_new
port map(
clk_i => PCI_CLK,
nrst_i => PCI_nRES,
wb_adr_i => wb_adr,
wb_dat_o => wb_dat_out,
wb_dat_i => wb_dat_in,
wb_sel_i => wb_sel,
wb_we_i => wb_we,
wb_stb_i => wb_stb,
wb_cyc_i => wb_cyc,
wb_ack_o => wb_ack,
wb_err_o => wb_err,
wb_int_o => wb_int,
DISP_SEL => DISP_SEL,
DISP_LED => DISP_LED
);
end pci_7seg_arch;
| gpl-2.0 | a28e2829f9d1c3094d71992af994a499 | 0.35676 | 3.524374 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/npc_pkg.vhd | 1 | 3,936 | use work.graphics_types_pkg.all;
package npc_pkg is
constant NPC_SPEED_MAX: integer := 12;
type npc_ai_type is (AI_BOUNCER, AI_FOLLOWER, AI_PROJECTILE);
type npc_type is record
-- start position for the NPC
initial_position: point_type;
-- start velocity for the NPC
initial_speed: point_type;
absolute_speed: integer range 0 to NPC_SPEED_MAX;
slowdown_factor: integer range 0 to NPC_SPEED_MAX;
-- boundaries for NPC movement
allowed_region: rectangle_type;
-- type of artificial intelligence for NPC movement
ai_type: npc_ai_type;
end record;
type npc_array_type is array (natural range <>) of npc_type;
function make_npc_bouncer(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type;
function make_npc_projectile(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type;
function make_npc_follower(
initial_position: point_type := (0, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1);
absolute_speed: integer range 0 to NPC_SPEED_MAX := 1;
slowdown_factor: integer range 0 to NPC_SPEED_MAX := 0
) return npc_type;
end;
package body npc_pkg is
function make_npc_bouncer(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type is
begin
return (
-- some parameters are copied from the input
initial_position => initial_position,
initial_speed => initial_speed,
allowed_region => allowed_region,
-- some parameters are constant
ai_type => AI_BOUNCER,
-- remaining parameters are unsused, but must have any arbitrary value
absolute_speed => 0,
slowdown_factor => 0
);
end;
function make_npc_projectile(
initial_position: point_type := (0, 0);
initial_speed: point_type := (1, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1)
) return npc_type is
begin
return (
-- some parameters are copied from the input
initial_position => initial_position,
initial_speed => initial_speed,
allowed_region => allowed_region,
-- some parameters are constant
ai_type => AI_PROJECTILE,
-- remaining parameters are unsused, but must have any arbitrary value
absolute_speed => 0,
slowdown_factor => 0
);
end;
function make_npc_follower(
initial_position: point_type := (0, 0);
allowed_region: rectangle_type := (0, 0, GAME_VIEWPORT_WIDTH-1, GAME_VIEWPORT_HEIGHT-1);
absolute_speed: integer range 0 to NPC_SPEED_MAX := 1;
slowdown_factor: integer range 0 to NPC_SPEED_MAX := 0
) return npc_type is
begin
return (
-- some parameters are copied from the input
initial_position => initial_position,
absolute_speed => absolute_speed,
slowdown_factor => slowdown_factor,
allowed_region => allowed_region,
-- some parameters are constant
ai_type => AI_FOLLOWER,
-- remaining parameters are unsused, but must have any arbitrary value
initial_speed => (0, 0)
);
end;
end;
| unlicense | 66608e63237a9c1bd3a34f3c0ff271af | 0.583079 | 4.012232 | false | false | false | false |
wltr/common-vhdl | packages/lfsr/src/pkg/galois_lfsr_pkg.vhd | 1 | 6,826 | -------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2015 Johannes Walter <[email protected]>
--
-- Description:
-- Galois Linear Feedback Shift Register (LFSR) package.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
package lfsr_pkg is
-- Maximum LFSR length supported by package
constant lfsr_max_length_c : natural range 2 to natural'high := 32;
-- LFSR data type to be used with package functions
type lfsr_t is array (natural range <>) of std_ulogic;
-- Get LFSR bit length for a given period, period = 2^n - 1
function lfsr_length(period : positive)
return natural;
-- Get LFSR maximum period polynomial for a given bit length
function lfsr_polynomial(length : natural range 2 to lfsr_max_length_c)
return std_ulogic_vector;
-- Get LFSR seed value for a given bit length
function lfsr_seed(length : natural range 2 to lfsr_max_length_c)
return lfsr_t;
-- Compute the LFSR value after a given number of shifts using the maximum period polynomial
function lfsr_shift(lfsr : lfsr_t; num_shifts : natural := 1)
return lfsr_t;
-- Compute the LFSR value with the provided polynomial after the given number of shifts
function lfsr_shift(lfsr : lfsr_t; polynomial : std_ulogic_vector;
num_shifts : natural := 1)
return lfsr_t;
-- Compute the LFSR value after a given number of shifts using the "+" operator and maximum period polynomial
function "+"(lfsr : lfsr_t; num_shifts : natural)
return lfsr_t;
end package lfsr_pkg;
package body lfsr_pkg is
function lfsr_length(period : positive)
return natural is
begin
if period < 3 then
return 2;
else
return natural(ceil(log2(real(period + 1))));
end if;
end function lfsr_length;
function lfsr_polynomial(length : natural range 2 to lfsr_max_length_c)
return std_ulogic_vector is
variable polynomial : std_ulogic_vector(length - 1 downto 0);
begin
case length is
when 2 => polynomial := "11"; -- x^2 + x + 1
when 3 => polynomial := "110"; -- x^3 + x^2 + 1
when 4 => polynomial := "1100"; -- x^4 + x^3 + 1
when 5 => polynomial := "10100"; -- x^5 + x^3 + 1
when 6 => polynomial := "110000"; -- x^6 + x^5 + 1
when 7 => polynomial := "1100000"; -- x^7 + x^6 + 1
when 8 => polynomial := "10111000"; -- x^8 + x^6 + x^5 + x^4 + 1
when 9 => polynomial := "100010000"; -- x^9 + x^5 + 1
when 10 => polynomial := "1001000000"; -- x^10 + x^7 + 1
when 11 => polynomial := "10100000000"; -- x^11 + x^9 + 1
when 12 => polynomial := "111000001000"; -- x^12 + x^11 + x^10 + x^4 + 1
when 13 => polynomial := "1110010000000"; -- x^13 + x^12 + x^11 + x^8 + 1
when 14 => polynomial := "11100000000010"; -- x^14 + x^13 + x^12 + x^2 + 1
when 15 => polynomial := "110000000000000"; -- x^15 + x^14 + 1
when 16 => polynomial := "1011010000000000"; -- x^16 + x^14 + x^13 + x^11 + 1
when 17 => polynomial := "10010000000000000"; -- x^17 + x^14 + 1
when 18 => polynomial := "100000010000000000"; -- x^18 + x^11 + 1
when 19 => polynomial := "1110010000000000000"; -- x^19 + x^18 + x^17 + x^14 + 1
when 20 => polynomial := "10010000000000000000"; -- x^20 + x^17 + 1
when 21 => polynomial := "101000000000000000000"; -- x^21 + x^19 + 1
when 22 => polynomial := "1100000000000000000000"; -- x^22 + x^21 + 1
when 23 => polynomial := "10000100000000000000000"; -- x^23 + x^18 + 1
when 24 => polynomial := "110110000000000000000000"; -- x^24 + x^23 + x^21 + x^20 + 1
when 25 => polynomial := "1001000000000000000000000"; -- x^25 + x^22 + 1
when 26 => polynomial := "11100010000000000000000000"; -- x^26 + x^25 + x^24 + x^20 + 1
when 27 => polynomial := "111001000000000000000000000"; -- x^27 + x^26 + x^25 + x^22 + 1
when 28 => polynomial := "1001000000000000000000000000"; -- x^28 + x^25 + 1
when 29 => polynomial := "10100000000000000000000000000"; -- x^29 + x^27 + 1
when 30 => polynomial := "110010100000000000000000000000"; -- x^30 + x^29 + x^26 + x^24 + 1
when 31 => polynomial := "1001000000000000000000000000000"; -- x^31 + x^28 + 1
when 32 => polynomial := "10100011000000000000000000000000"; -- x^32 + x^30 + x^26 + x^25 + 1
end case;
return polynomial;
end function lfsr_polynomial;
function lfsr_seed(length : natural range 2 to lfsr_max_length_c)
return lfsr_t is
begin
return (length - 1 downto 0 => '1');
end function lfsr_seed;
function lfsr_shift(lfsr : lfsr_t; num_shifts : natural := 1)
return lfsr_t is
begin
assert lfsr'length >= 2
report "LFSR vector is too short."
severity error;
assert lfsr'length <= lfsr_max_length_c
report "LFSR vector is too long."
severity error;
return lfsr_shift(lfsr, lfsr_polynomial(lfsr'length), num_shifts);
end function lfsr_shift;
function lfsr_shift(lfsr : lfsr_t; polynomial : std_ulogic_vector;
num_shifts : natural := 1)
return lfsr_t is
variable tmp : lfsr_t(lfsr'range) := lfsr;
variable res : lfsr_t(lfsr'range) := (others => '0');
begin
assert lfsr'left > lfsr'right
report "Package requires an LFSR with DOWNTO range and minimum length of 2."
severity error;
assert polynomial'left > polynomial'right
report "Package requires a polynomial with DOWNTO range and minimum length of 2."
severity error;
assert lfsr'left = polynomial'left and lfsr'right = polynomial'right
report "Ranges of LFSR and polynomial have to be equal."
severity error;
assert polynomial(polynomial'high) = '1'
report "Highest bit of polynomial has to be 1 as it represents its order."
severity error;
for i in 1 to num_shifts loop
res(res'high) := tmp(tmp'low);
for j in res'high - 1 downto res'low loop
if polynomial(j) = '1' then
res(j) := tmp(j + 1) xor tmp(tmp'low);
else
res(j) := tmp(j + 1);
end if;
end loop;
tmp := res;
end loop;
return res;
end function lfsr_shift;
function "+"(lfsr : lfsr_t; num_shifts : natural)
return lfsr_t is
begin
return lfsr_shift(lfsr, num_shifts);
end function "+";
end package body lfsr_pkg;
| lgpl-2.1 | 24be1cbeecf4db389bd7144bb18e3e9f | 0.573396 | 3.900571 | false | false | false | false |
freecores/raggedstone | source/vga_main.vhd | 1 | 4,181 | ---------------------------------------------------------------------
-- vga_main.vhd Demo VGA configuration module.
---------------------------------------------------------------------
-- Author: Barron Barnett
-- Copyright 2004 Digilent, Inc.
---------------------------------------------------------------------
--
-- This project is compatible with Xilinx ISE or Xilinx WebPack tools.
--
-- Inputs:
-- mclk - System Clock
-- Outputs:
-- hs - Horizontal Sync
-- vs - Vertical Sync
-- red - Red Output
-- grn - Green Output
-- blu - Blue Output
--
-- This module creates a three line pattern on a vga display using a
-- a vertical refresh rate of 60Hz. This is done by dividing the
-- system clock in half and using that for the pixel clock. This in
-- turn drives the vertical sync when the horizontal sync has reached
-- its reset point. All data displayed is done by basic value
-- comparisons.
------------------------------------------------------------------------
-- Revision History:
-- 07/01/2004(BarronB): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vgaController is
Port ( mclk : in std_logic;
hs : out std_logic;
vs : out std_logic;
red : out std_logic;
grn : out std_logic;
blu : out std_logic);
end vgaController;
architecture Behavioral of vgaController is
constant hpixels : std_logic_vector(9 downto 0) := "1100100000"; --Value of pixels in a horizontal line
constant vlines : std_logic_vector(9 downto 0) := "1000001001"; --Number of horizontal lines in the display
constant hbp : std_logic_vector(9 downto 0) := "0010010000"; --Horizontal back porch
constant hfp : std_logic_vector(9 downto 0) := "1100010000"; --Horizontal front porch
constant vbp : std_logic_vector(9 downto 0) := "0000011111"; --Vertical back porch
constant vfp : std_logic_vector(9 downto 0) := "0111111111"; --Vertical front porch
signal hc, vc : std_logic_vector(9 downto 0); --These are the Horizontal and Vertical counters
signal clkdiv : std_logic; --Clock divider
signal vidon : std_logic; --Tells whether or not its ok to display data
signal vsenable : std_logic; --Enable for the Vertical counter
begin
--This cuts the 50Mhz clock in half
process(mclk)
begin
if(mclk = '1' and mclk'EVENT) then
clkdiv <= not clkdiv;
end if;
end process;
--Runs the horizontal counter
process(clkdiv)
begin
if(clkdiv = '1' and clkdiv'EVENT) then
if hc = hpixels then --If the counter has reached the end of pixel count
hc <= "0000000000"; --reset the counter
vsenable <= '1'; --Enable the vertical counter to increment
else
hc <= hc + 1; --Increment the horizontal counter
vsenable <= '0'; --Leave the vsenable off
end if;
end if;
end process;
hs <= '1' when hc(9 downto 7) = "000" else '0'; --Horizontal Sync Pulse
process(clkdiv)
begin
if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then --Increment when enabled
if vc = vlines then --Reset when the number of lines is reached
vc <= "0000000000";
else vc <= vc + 1; --Increment the vertical counter
end if;
end if;
end process;
vs <= '1' when vc(9 downto 1) = "000000000" else '0'; --Vertical Sync Pulse
red <= '1' when (hc = "1010101100" and vidon ='1') else '0'; --Red pixel on at a specific horizontal count
grn <= '1' when (hc = "0100000100" and vidon ='1') else '0'; --Green pixel on at a specific horizontal count
blu <= '1' when (vc = "0100100001" and vidon ='1') else '0'; --Blue pixel on at a specific vertical count
vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0'; --Enable video out when within the porches
end Behavioral;
| gpl-2.0 | 4cfe185c06938b9efc2e8e8e8ac0251f | 0.564219 | 3.832264 | false | false | false | false |
wltr/common-vhdl | memory/single_port_ram/src/rtl/single_port_ram_tmr.vhd | 1 | 3,204 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Single port block RAM with TMR.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity single_port_ram_tmr is
generic (
-- Memory depth
depth_g : positive := 32;
-- Data bit width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
rd_en_i : in std_ulogic;
wr_en_i : in std_ulogic;
data_i : in std_ulogic_vector(width_g - 1 downto 0);
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic);
end entity single_port_ram_tmr;
architecture rtl of single_port_ram_tmr is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal mem_addr : std_ulogic_vector(natural(ceil(log2(real(depth_g * 3)))) - 1 downto 0);
signal mem_rd_en : std_ulogic;
signal mem_wr_en : std_ulogic;
signal mem_data_in : std_ulogic_vector(width_g - 1 downto 0);
signal mem_data_out : std_ulogic_vector(width_g - 1 downto 0);
signal mem_data_out_en : std_ulogic;
signal mem_done : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
tmr_inst : entity work.mem_data_triplicator
generic map (
depth_g => (depth_g * 3),
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => addr_i,
rd_en_i => rd_en_i,
wr_en_i => wr_en_i,
data_i => data_i,
data_o => data_o,
data_en_o => data_en_o,
busy_o => busy_o,
done_o => done_o,
voted_o => open,
mem_addr_o => mem_addr,
mem_rd_en_o => mem_rd_en,
mem_wr_en_o => mem_wr_en,
mem_data_o => mem_data_in,
mem_data_i => mem_data_out,
mem_data_en_i => mem_data_out_en,
mem_busy_i => '0',
mem_done_i => mem_done);
ram_inst : entity work.single_port_ram
generic map (
depth_g => (depth_g * 3),
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => mem_addr,
rd_en_i => mem_rd_en,
wr_en_i => mem_wr_en,
data_i => mem_data_in,
data_o => mem_data_out,
data_en_o => mem_data_out_en,
done_o => mem_done);
end architecture rtl;
| lgpl-2.1 | 635516af23a74e3a97697de79975872e | 0.442884 | 3.372632 | false | false | false | false |
wltr/common-vhdl | communication/serial_3wire_transceiver/src/rtl/serial_3wire_tx.vhd | 1 | 6,033 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Send synchronous serial data over 3 wires.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
entity serial_3wire_tx is
generic (
-- Data bit width
data_width_g : positive := 32;
-- Number of clock cycles per bit
num_ticks_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
data_i : in std_ulogic_vector(data_width_g - 1 downto 0);
data_en_i : in std_ulogic;
busy_o : out std_ulogic;
done_o : out std_ulogic;
-- Transmission lines
tx_frame_o : out std_ulogic;
tx_bit_en_o : out std_ulogic;
tx_o : out std_ulogic);
end entity serial_3wire_tx;
architecture rtl of serial_3wire_tx is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- Using odd parity detects empty frames as errors
constant parity_init_c : std_ulogic := '1';
-- LFSR counter bit length
constant len_c : natural := lfsr_length(data_width_g + 1);
-- LFSR counter initial values
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- FSM states
type state_t is (IDLE, EN_HIGH, EN_LOW);
-- FSM registers
type reg_t is record
state : state_t;
count : std_ulogic_vector(len_c - 1 downto 0);
data : std_ulogic_vector(data_width_g - 1 downto 0);
parity : std_ulogic;
frame : std_ulogic;
bit_en : std_ulogic;
done : std_ulogic;
end record reg_t;
-- FSM initial state
constant init_c : reg_t := (
state => IDLE,
count => seed_c,
data => (others => '0'),
parity => parity_init_c,
frame => '0',
bit_en => '0',
done => '0');
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal reg : reg_t := init_c;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
signal strobe_en : std_ulogic;
signal bit_strobe : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
busy_o <= reg.frame;
done_o <= reg.done;
tx_frame_o <= reg.frame;
tx_bit_en_o <= reg.bit_en;
tx_o <= reg.data(reg.data'low);
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
lfsr_strobe_gen_inst : entity work.lfsr_strobe_generator
generic map (
period_g => num_ticks_g / 2,
preset_value_g => 0)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => strobe_en,
pre_i => '0',
strobe_o => bit_strobe);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- FSM registering
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
-- FSM combinatorics
comb : process (reg, data_i, data_en_i, bit_strobe) is
begin -- process comb
-- Defaults
next_reg <= reg;
strobe_en <= '1';
next_reg.done <= init_c.done;
case reg.state is
when IDLE =>
strobe_en <= '0';
-- Wait for data
if data_en_i = '1' then
-- Start transmission
next_reg.data <= data_i;
next_reg.frame <= '1';
next_reg.state <= EN_LOW;
end if;
when EN_LOW =>
-- Bit enable is low
if bit_strobe = '1' then
-- Set bit enable high after a specific number of clock cycles
next_reg.bit_en <= '1';
next_reg.state <= EN_HIGH;
end if;
when EN_HIGH =>
-- Bit enable is high
if bit_strobe = '1' then
if reg.count = lfsr_shift(seed_c, data_width_g) then
-- Reset if all bits were sent
next_reg <= init_c;
next_reg.done <= '1';
else
if reg.count = lfsr_shift(seed_c, data_width_g - 1) then
-- Attach parity bit at the end of every transmission
next_reg.data(next_reg.data'low) <= reg.parity xor reg.data(reg.data'low);
else
-- Calculate parity bit
next_reg.parity <= reg.parity xor reg.data(reg.data'low);
-- Transmit next data bit
next_reg.data <= '0' & reg.data(reg.data'high downto reg.data'low + 1);
end if;
next_reg.count <= lfsr_shift(reg.count);
-- Set bit enable low after a specific number of clock cycles
next_reg.bit_en <= '0';
next_reg.state <= EN_LOW;
end if;
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | dc6ec1855c80337cb8dec5eff74be5a6 | 0.433947 | 4.166436 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/artix7/cc_cmplr_v3_0_964aa42461b15ac2.vhd | 1 | 6,145 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file cc_cmplr_v3_0_964aa42461b15ac2.vhd when simulating
-- the core, cc_cmplr_v3_0_964aa42461b15ac2. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY cc_cmplr_v3_0_964aa42461b15ac2 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END cc_cmplr_v3_0_964aa42461b15ac2;
ARCHITECTURE cc_cmplr_v3_0_964aa42461b15ac2_a OF cc_cmplr_v3_0_964aa42461b15ac2 IS
-- synthesis translate_off
COMPONENT wrapped_cc_cmplr_v3_0_964aa42461b15ac2
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
event_tlast_unexpected : OUT STD_LOGIC;
event_tlast_missing : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_cc_cmplr_v3_0_964aa42461b15ac2 USE ENTITY XilinxCoreLib.cic_compiler_v3_0(behavioral)
GENERIC MAP (
c_c1 => 58,
c_c2 => 58,
c_c3 => 58,
c_c4 => 0,
c_c5 => 0,
c_c6 => 0,
c_clk_freq => 2,
c_component_name => "cc_cmplr_v3_0_964aa42461b15ac2",
c_diff_delay => 2,
c_family => "artix7",
c_filter_type => 1,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_dout_tready => 0,
c_has_rounding => 0,
c_i1 => 58,
c_i2 => 58,
c_i3 => 58,
c_i4 => 0,
c_i5 => 0,
c_i6 => 0,
c_input_width => 24,
c_m_axis_data_tdata_width => 64,
c_m_axis_data_tuser_width => 16,
c_max_rate => 1120,
c_min_rate => 1120,
c_num_channels => 2,
c_num_stages => 3,
c_output_width => 58,
c_rate => 1120,
c_rate_type => 0,
c_s_axis_config_tdata_width => 1,
c_s_axis_data_tdata_width => 24,
c_sample_freq => 1,
c_use_dsp => 1,
c_use_streaming_interface => 1,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_cc_cmplr_v3_0_964aa42461b15ac2
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tdata => s_axis_data_tdata,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => s_axis_data_tlast,
m_axis_data_tdata => m_axis_data_tdata,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tlast => m_axis_data_tlast,
event_tlast_unexpected => event_tlast_unexpected,
event_tlast_missing => event_tlast_missing
);
-- synthesis translate_on
END cc_cmplr_v3_0_964aa42461b15ac2_a;
| lgpl-3.0 | 185ac999de2c14985f93d6a0877032bc | 0.557364 | 3.655562 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_pattern_generator.vhd | 1 | 3,440 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Generate predefined values for filter input bit streams.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ads1281_pattern_generator is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Load selected pattern
sel_i : in std_ulogic_vector(2 downto 0);
load_i : in std_ulogic;
-- Generated bit stream
gen_o : out std_ulogic);
end entity ads1281_pattern_generator;
architecture rtl of ads1281_pattern_generator is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
type lut_t is array (0 to 2**sel_i'length - 1) of std_ulogic_vector(7 downto 0);
-- Predefined patterns
constant lut : lut_t := (
"00000000", -- 0.0 %
"00010001", -- 25.0 %
"00100101", -- 37.5 %
"01010101", -- 50.0 %
"01011011", -- 62.5 %
"01110111", -- 75.0 %
"01111111", -- 87.5 %
"11111111"); -- 100.0 %
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal gen : std_ulogic_vector(7 downto 0);
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal strb : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
gen_o <= gen(gen'high);
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
lfsr_strobe_generator_inst : entity work.lfsr_strobe_generator
generic map (
period_g => 40,
preset_value_g => 0)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
en_i => en_i,
pre_i => '0',
strobe_o => strb);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
gen <= (others => '0');
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
elsif load_i = '1' then
-- Select predefined pattern
gen <= lut(to_integer(unsigned(sel_i)));
elsif strb = '1' then
gen <= gen(gen'high - 1 downto gen'low) & gen(gen'high);
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | d3f0d5f9c2475c270b4bdbb211468491 | 0.362209 | 4.851904 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/colors_pkg.vhd | 1 | 7,913 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Data types and conversion functions for handling colors in paletted and true
-- color modes. There are 3 distinct color representations:
-- #1. A 5-bit palette index. This is the least expensive memorywise.
-- #2. A 24-bit RGB truecolor value. Each palette color maps to one truecolor value.
-- #3. A 30-bit RGB value in the format expected by some video chips.
-- All bitmaps are stored in paletted mode. Convenience functions are
-- provided to convert between the color types as necessary.
package colors_pkg is
-- Internally, each color channel (red, green, blue) is encoded
-- with 8 bits (256 levels)
subtype color_channel_type is integer range 0 to 255;
-- Data type for a RGB pixel encoded with 24bpp
type rgb_color_type is record
r, g, b: color_channel_type;
end record;
-- At the output interface, each color is encoded with 10 bits
subtype output_pixel_channel_type is std_logic_vector(9 downto 0);
-- Data types for a RGB pixel encoded with 30bpp and that can be
-- output to the video display device
type output_pixel_type is record
r, g, b: output_pixel_channel_type;
end record;
-- Our color palette is an array of 24bpp RGB values.
-- Color names come mostly from http://goo.gl/UxWjIU.
-- Note: a pixel with a color value of #0 is transparent, and is not
-- shown on the screen (the background pixel will be shown instead)
type palette_type is array (natural range <>) of rgb_color_type;
constant PALETTE: palette_type := (
( 0, 0, 0), -- 0: TRANSPARENT (Note: for black, use color #34)
( 47, 42, 33), -- 1: BISTRE ......... dark grayish brown, with a yellowish cast
( 77, 70, 44), -- 2: DARK_LAVA ...... grayish brown, with a yellowish cast
(163, 153, 96), -- 3: LIGHT_TAUPE .... light grayish brown
(168, 236, 182), -- 4: CELADON ........ pale greyish shade of green
( 6, 13, 69), -- 5: OXFORD_BLUE .... very dark azure
( 13, 33, 133), -- 6: PHTHALO BLUE ... bright, greenish-blue
( 16, 60, 255), -- 7: BLUE_RYB
( 18, 141, 254), -- 8: DODGER_BLUE
( 18, 187, 255), -- 9: SPIRO_DISCO_BALL
( 16, 237, 254), -- 10: AQUA
( 18, 33, 18), -- 11: DARK_JUNGLE_GREEN
( 17, 68, 25), -- 12: MYRTLE
( 11, 166, 6), -- 13: ISLAMIC_GREEN
( 96, 248, 17), -- 14: BRIGHT_GREEN
( 41, 17, 47), -- 15: ST_PATRICKS_BLUE
( 85, 54, 104), -- 16: DARK_BYZANTIUM
( 54, 54, 54), -- 17: GRAY_21
( 98, 98, 98), -- 18: GRAY_38
(149, 149, 149), -- 19: GRAY_58
(193, 193, 193), -- 20: GRAY_76
( 36, 15, 9), -- 21: ZINNWALDITE_BROWN
( 74, 17, 12), -- 22: BULGARIAN_ROSE
(165, 26, 20), -- 23: RUFOUS
(228, 32, 21), -- 24: LUST
(236, 92, 24), -- 25: FLAME
(255, 158, 19), -- 26: DARK_TANGERINE
(171, 222, 98), -- 27: INCHWORM
( 50, 106, 37), -- 28: HUNTER_GREEN
( 97, 160, 30), -- 29: OLIVE_DRAB_3
(182, 209, 35), -- 30: ANDROID_GREEN
( 88, 7, 128), -- 31: INDIGO
(213, 43, 255), -- 32: PHLOX
( 29, 29, 29), -- 33: GRAY_11
( 0, 0, 0), -- 34: BLACK
(105, 145, 175), -- 35: AIR_FORCE_BLUE_RAF
(183, 228, 236), -- 36: POWDER_BLUE
(119, 46, 36), -- 37: BURNT_UMBER
(157, 90, 32), -- 38: GOLDEN_BROWN
(255, 223, 23), -- 39: GOLDEN_YELLOW
(255, 255, 35), -- 40: LASER_LEMON
(226, 101, 83), -- 41: TERRA_COTTA
(234, 163, 95), -- 42: SANDY_BROWN
( 30, 176, 158), -- 43: LIGHT_SEA GREEN
( 95, 97, 20), -- 44: FIELD_DRAB
(161, 153, 21), -- 45: DARK_GOLDENROD
(238, 229, 87), -- 46: CORN
(206, 93, 169), -- 47: SKY_MAGENTA
(242, 169, 224), -- 48: LAVENDER_ROSE
( 24, 33, 52), -- 49: DARK_MIDNIGHT_BLUE
( 35, 83, 115), -- 50: DARK_CERULEAN
( 63, 137, 178), -- 51: STEEL_BLUE
(112, 231, 241), -- 52: ELECTRIC_BLUE
(255, 255, 255), -- 53: WHITE
(117, 119, 220), -- 54: MEDIUM_SLATE_BLUE
(169, 94, 86), -- 55: REDWOOD
(226, 166, 155), -- 56: TUMBLEWEED .......... skin pink
(244, 229, 160), -- 57: MEDIUM_CHAMPAGNE .... skin beige
( 20, 88, 92), -- 58: MIDNIGHT_GREEN
( 0, 146, 103), -- 59: GREEN_NCS
( 8, 214, 109), -- 60: MALACHITE
( 97, 232, 164), -- 61: MEDIUM_AQUAMARINE
(167, 22, 121), -- 62: JAZZBERRY_JAM
(255, 0, 128) -- 63: BRIGHT_PINK
);
-- Total number of colors in the system palette (including #0 = TRANSPARENT)
constant PALETTE_COLORS_COUNT: integer := PALETTE'length;
-- Index of a color entry in the system fixed palette
subtype palette_color_type is integer range PALETTE'range;
-- -- A bitmap is a 2D array in which each element is a value from the palette
-- type paletted_bitmap_type is array (natural range <>, natural range <>) of palette_color_type;
-- Convert a palette color to an RGB value; performs a color lookup
function palette_to_rgb(palette_color: palette_color_type) return rgb_color_type;
-- Convenience constants for referring to specific colors by name
constant PC_TRANSPARENT: palette_color_type := 0;
constant PC_DARK_JUNGLE_GREEN: palette_color_type := 11;
constant PC_BLACK: palette_color_type := 34;
constant PC_WHITE: palette_color_type := 53;
constant RGB_BLACK: rgb_color_type := (0, 0, 0);
function output_pixel_from_rgb_color(rgb_pixel: rgb_color_type) return output_pixel_type;
function output_pixel_from_palette_color(palette_color: palette_color_type) return output_pixel_type;
function color_channel_to_10_bits(channel_value: color_channel_type) return std_logic_vector;
end;
package body colors_pkg is
-- Convert a color channel value from a short integer (0..255) to a
-- 10-bit std_logic_vector, which can be output to the video DAC
function color_channel_to_10_bits(channel_value: color_channel_type) return std_logic_vector is
variable channel_value_slv: std_logic_vector(7 downto 0);
begin
channel_value_slv := std_logic_vector(to_unsigned(channel_value, 8));
return channel_value_slv & channel_value_slv(7 downto 6);
end;
-- Perform a color lookup in the system palette, returning an RGB value from
-- a palette index.
function palette_to_rgb(palette_color: palette_color_type) return rgb_color_type is
begin
return PALETTE(palette_color);
end;
-- Convert a pixel from the 24-bit RGB representation used internally in the system
-- to the 30-bit RGB used by the video DAC.
function output_pixel_from_rgb_color(rgb_pixel: rgb_color_type) return output_pixel_type is
begin
return (
color_channel_to_10_bits(rgb_pixel.r),
color_channel_to_10_bits(rgb_pixel.g),
color_channel_to_10_bits(rgb_pixel.b)
);
end;
-- Convert a pixel from the paletted 5-bit representation used internally in the system
-- to the 30-bit RGB used by the video DAC.
function output_pixel_from_palette_color(palette_color: palette_color_type) return output_pixel_type is
variable rgb_color: rgb_color_type;
begin
rgb_color := palette_to_rgb(palette_color);
return output_pixel_from_rgb_color(rgb_color);
end;
end;
| unlicense | 01cbc8666a9be9852f463edebf65f73c | 0.571338 | 3.269835 | false | false | false | false |
wltr/common-vhdl | memory/two_port_ram/src/rtl/two_port_ram_tmr.vhd | 1 | 3,835 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Two port block RAM with TMR.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity two_port_ram_tmr is
generic (
-- Memory depth
depth_g : positive := 32;
-- Data bit width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Write port
wr_addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
wr_en_i : in std_ulogic;
wr_data_i : in std_ulogic_vector(width_g - 1 downto 0);
wr_done_o : out std_ulogic;
wr_busy_o : out std_ulogic;
-- Read port
rd_addr_i : in std_ulogic_vector(natural(ceil(log2(real(depth_g)))) - 1 downto 0);
rd_en_i : in std_ulogic;
rd_data_o : out std_ulogic_vector(width_g - 1 downto 0);
rd_data_en_o : out std_ulogic;
rd_busy_o : out std_ulogic);
end entity two_port_ram_tmr;
architecture rtl of two_port_ram_tmr is
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal mem_wr_addr : std_ulogic_vector(natural(ceil(log2(real(depth_g * 3)))) - 1 downto 0);
signal mem_wr_en : std_ulogic;
signal mem_wr_data : std_ulogic_vector(width_g - 1 downto 0);
signal mem_wr_done : std_ulogic;
signal mem_rd_addr : std_ulogic_vector(natural(ceil(log2(real(depth_g * 3)))) - 1 downto 0);
signal mem_rd_en : std_ulogic;
signal mem_rd_data : std_ulogic_vector(width_g - 1 downto 0);
signal mem_rd_data_en : std_ulogic;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
rd_tmr_inst : entity work.mem_data_triplicator_rd_only
generic map (
depth_g => (depth_g * 3),
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => rd_addr_i,
rd_en_i => rd_en_i,
data_o => rd_data_o,
data_en_o => rd_data_en_o,
busy_o => rd_busy_o,
done_o => open,
voted_o => open,
mem_addr_o => mem_rd_addr,
mem_rd_en_o => mem_rd_en,
mem_data_i => mem_rd_data,
mem_data_en_i => mem_rd_data_en,
mem_busy_i => '0',
mem_done_i => mem_rd_data_en);
wr_tmr_inst : entity work.mem_data_triplicator_wr_only
generic map (
depth_g => (depth_g * 3),
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
addr_i => wr_addr_i,
wr_en_i => wr_en_i,
data_i => wr_data_i,
busy_o => wr_busy_o,
done_o => wr_done_o,
mem_addr_o => mem_wr_addr,
mem_wr_en_o => mem_wr_en,
mem_data_o => mem_wr_data,
mem_busy_i => '0',
mem_done_i => mem_wr_done);
ram_inst : entity work.two_port_ram
generic map (
depth_g => (depth_g * 3),
width_g => width_g)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
wr_addr_i => mem_wr_addr,
wr_en_i => mem_wr_en,
wr_data_i => mem_wr_data,
wr_done_o => mem_wr_done,
rd_addr_i => mem_rd_addr,
rd_en_i => mem_rd_en,
rd_data_o => mem_rd_data,
rd_data_en_o => mem_rd_data_en);
end architecture rtl;
| lgpl-2.1 | 059ac0181f4776bf60a686081ac0e89e | 0.473794 | 3.080321 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/adventure_demo/game_logic.vhd | 1 | 7,788 | library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.input_types_pkg.all;
use work.graphics_types_pkg.all;
use work.text_mode_pkg.all;
use work.resource_data_helper_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.game_state_pkg.all;
entity game_logic is
port (
clock: in std_logic;
reset: in std_logic;
time_base_50_ms: in std_logic;
npc_positions: in point_array_type;
npc_target_positions: out point_array_type;
-- Each element is 'true' while the two corresponding sprites are colliding.
sprite_collisions: in bool_vector;
sprites_positions: out point_array_type;
-- Text strings displayed on the screen
text_mode_strings: out text_mode_strings_type;
input_buttons: in input_buttons_type;
game_state: out game_state_type;
-- debug pins to help debug game logic (e.g., connecting to board leds)
debug_bits: out std_logic_vector(7 downto 0)
);
end;
architecture rtl of game_logic is
-- Each sprite must have a position, which may be constant or changeable.
-- For static items (chest, axe) we may use a constant or a hardcoded value
-- in the sprite positions array. For the player and NPC sprites, we declare
-- signals and update them in the game logic to make them move.
signal player_position: point_type;
constant CHEST_POSITION: point_type := (144, 80);
constant AXE_POSITION: point_type := (8, 8);
-- Signals to help us keep track of the game state.
signal game_state_signal: game_state_type;
signal game_over, game_won: boolean;
-- Aliases to help us work with the NPC positions
alias scorpion_position: point_type is npc_positions(get_id(NPC_SCORPION));
alias ghost_position: point_type is npc_positions(get_id(NPC_GHOST));
alias bat_position: point_type is npc_positions(get_id(NPC_BAT));
alias oryx_position: point_type is npc_positions(get_id(NPC_ORYX));
alias archer_position: point_type is npc_positions(get_id(NPC_ARCHER));
alias reaper_position: point_type is npc_positions(get_id(NPC_REAPER));
-- Aliases to help us monitor the game state. The player dies when an
-- enemy is touched.
alias death_by_ghost: boolean is sprite_collisions(get_id(COLLISION_PLAYER_GHOST));
alias death_by_scorpion: boolean is sprite_collisions(get_id(COLLISION_PLAYER_SCORPION));
alias death_by_oryx: boolean is sprite_collisions(get_id(COLLISION_PLAYER_ORYX));
alias treasure_found: boolean is sprite_collisions(get_id(COLLISION_PLAYER_CHEST));
begin
----------------------------------------------------------------------------
-- Overall architecture description:
-- 1) Update player position
-- 2) Update NPC inputs (target positions)
-- 3) Provide a screen position for each sprite
-- 4) Update text strings displayed on the screen
-- 5) Update game state
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Section 1: Update player position based on input buttons
----------------------------------------------------------------------------
update_player_position: process (clock, reset) begin
if reset then
player_position <= (128, 128);
elsif rising_edge(clock) then
if time_base_50_ms then
if input_buttons.right then
player_position.x <= player_position.x + 1;
elsif input_buttons.left then
player_position.x <= player_position.x - 1;
end if;
if input_buttons.down then
player_position.y <= player_position.y + 1;
elsif input_buttons.up then
player_position.y <= player_position.y - 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------
-- Section 2) Update NPC positions.
----------------------------------------------------------------------------
-- We only need to assign the values correspoding to followers
npc_target_positions( get_id(NPC_ORYX) ) <= player_position;
npc_target_positions( get_id(NPC_ARCHER) ) <= player_position + (-12,0);
npc_target_positions( get_id(NPC_REAPER) ) <= player_position + (12, -4);
----------------------------------------------------------------------------
-- Section 3) Provide a screen position for each sprite. For static objects,
-- we can use constants or hardcoded values. For moving objects and NPCs,
-- we use signals.
----------------------------------------------------------------------------
sprites_positions <= make_sprite_positions((
(SPRITE_PLAYER, player_position),
(SPRITE_AXE, AXE_POSITION),
(SPRITE_ARCHER, archer_position),
(SPRITE_CHEST, CHEST_POSITION),
(SPRITE_GHOST, ghost_position),
(SPRITE_SCORPION, scorpion_position),
(SPRITE_ORYX_11, oryx_position),
(SPRITE_ORYX_12, oryx_position + point_type'(8,0)),
(SPRITE_ORYX_21, oryx_position + point_type'(0,8)),
(SPRITE_ORYX_22, oryx_position + point_type'(8,8)),
(SPRITE_BAT, bat_position),
(SPRITE_REAPER, reaper_position)
));
----------------------------------------------------------------------------
-- Section 4) Update text strings displayed on the screen.
text_mode_strings <= (
( x => 30,
y => 0,
text => "Mighty Heroes ",
visible => true
),
( x => 1,
y => 24,
text => " HP:64 MP:23 ",
visible => true
)
);
----------------------------------------------------------------------------
-- Section 5) Update game state. This game has a very simple state logic:
-- RESET --> PLAY --> GAME_WON or GAME_OVER
----------------------------------------------------------------------------
game_won <= treasure_found;
game_over <= death_by_ghost or death_by_scorpion or death_by_oryx;
process (clock, reset) begin
if reset then
game_state_signal <= GS_RESET;
elsif rising_edge(clock) then
case game_state_signal is
when GS_RESET =>
if input_buttons /= (others => '0') then
game_state_signal <= GS_PLAY;
end if;
when GS_PLAY =>
if game_won then
game_state_signal <= GS_GAME_WON;
elsif game_over then
game_state_signal <= GS_GAME_OVER;
end if;
when others =>
null;
end case;
end if;
end process;
game_state <= game_state_signal;
-- Connect debug signals
debug_bits(0) <= '1' when death_by_scorpion else '0';
debug_bits(1) <= '1' when death_by_ghost else '0';
debug_bits(2) <= '1' when death_by_oryx else '0';
debug_bits(3) <= '1' when game_state_signal = GS_RESET else '0';
debug_bits(4) <= '1' when game_state_signal = GS_PLAY else '0';
debug_bits(5) <= '1' when game_state_signal = GS_GAME_OVER else '0';
debug_bits(6) <= '1' when game_state_signal = GS_GAME_WON else '0';
debug_bits(7) <= '0';
end; | unlicense | 113a0523065632ec5c022dc2f5f7e1dd | 0.518747 | 4.164706 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_un_cross/cross_uncross_core/dyn_mult_2chs.vhd | 1 | 4,712 | ------------------------------------------------------------------------------
-- Title : Dynamic Multiplication in One Channel Pair
------------------------------------------------------------------------------
-- Author : Jose Alvim Berkenbrock
-- Company : CNPEM LNLS-DAC-DIG
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: This design does what we call, dynamic multiplication. It
-- means that we have a specific multiplicator for each
-- different RF channel took by signal.
-------------------------------------------------------------------------------
-- Copyright (c) 2013 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-03-12 1.0 jose.berkenbrock Created
-- 2013-03-17 1.1 jose.berkenbrock Output Changed
-- 2013-07-01 1.2 lucas.russo Changed to synchronous resets
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dyn_mult_2chs is
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
const_11_i : in std_logic_vector(15 downto 0);
const_22_i : in std_logic_vector(15 downto 0);
const_12_i : in std_logic_vector(15 downto 0);
const_21_i : in std_logic_vector(15 downto 0);
ch1_i : in std_logic_vector(15 downto 0);
ch2_i : in std_logic_vector(15 downto 0);
ch1_o : out std_logic_vector(15 downto 0);
ch2_o : out std_logic_vector(15 downto 0)
);
end dyn_mult_2chs;
architecture rtl of dyn_mult_2chs is
signal en, en_old : std_logic;
signal flag : std_logic;
signal ch11_mult : std_logic_vector(31 downto 0);
signal ch22_mult : std_logic_vector(31 downto 0);
signal ch12_mult : std_logic_vector(31 downto 0);
signal ch21_mult : std_logic_vector(31 downto 0);
----------------------------------------------------------------
-- Component Declaration
----------------------------------------------------------------
component multiplier_u16x16_DSP
port (
clk : in std_logic;
a : in std_logic_vector(15 downto 0);
b : in std_logic_vector(15 downto 0);
p : out std_logic_vector(31 downto 0)
);
end component;
begin
----------------------------------------------------------------
-- Component instantiation
----------------------------------------------------------------
mult11 : multiplier_u16x16_DSP -- Signal 1 by channel 1
port map (
clk => clk_i,
a => ch1_i,
b => const_11_i, -- UFIX_16_15
p => ch11_mult
);
mult22 : multiplier_u16x16_DSP -- Signal 2 by channel 2
port map (
clk => clk_i,
a => ch2_i,
b => const_22_i,-- UFIX_16_15
p => ch22_mult
);
mult12 : multiplier_u16x16_DSP -- Signal 1 by channel 2
port map (
clk => clk_i,
a => ch1_i,
b => const_12_i,-- UFIX_16_15
p => ch12_mult
);
mult21 : multiplier_u16x16_DSP -- Signal 2 by channel 1
port map (
clk => clk_i,
a => ch2_i,
b => const_21_i,-- UFIX_16_15
p => ch21_mult
);
reg_en_proc: process(clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
en <= '0';
en_old <= '0';
else
en <= en_i;
en_old <= en;
end if;
end if;
end process reg_en_proc;
inv_proc: process(clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
flag <= '0';
else
if ((en = '1') and (en_old = '0')) then
flag <= not flag;
end if;
end if;
end if;
end process inv_proc;
output_proc: process (clk_i)
begin
if (rising_edge(clk_i)) then
if (rst_n_i = '0') then
ch1_o <= ch11_mult(31 downto 16);
ch2_o <= ch22_mult(31 downto 16);
else
if (flag = '1') then -- inverted
ch1_o <= ch12_mult(31 downto 16);
ch2_o <= ch21_mult(31 downto 16);
else
ch1_o <= ch11_mult(31 downto 16);
ch2_o <= ch22_mult(31 downto 16);
end if;
end if;
end if;
end process output_proc;
end rtl;
| lgpl-3.0 | 43aaa54ee42bbc9a5aff3de1b1737da1 | 0.442699 | 3.790829 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/fr_cmplr_v6_3_54d148b4178eb862.vhd | 1 | 6,978 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file fr_cmplr_v6_3_54d148b4178eb862.vhd when simulating
-- the core, fr_cmplr_v6_3_54d148b4178eb862. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY fr_cmplr_v6_3_54d148b4178eb862 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END fr_cmplr_v6_3_54d148b4178eb862;
ARCHITECTURE fr_cmplr_v6_3_54d148b4178eb862_a OF fr_cmplr_v6_3_54d148b4178eb862 IS
-- synthesis translate_off
COMPONENT wrapped_fr_cmplr_v6_3_54d148b4178eb862
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_chanid_incorrect : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_fr_cmplr_v6_3_54d148b4178eb862 USE ENTITY XilinxCoreLib.fir_compiler_v6_3(behavioral)
GENERIC MAP (
c_accum_op_path_widths => "42",
c_accum_path_widths => "42",
c_channel_pattern => "fixed",
c_coef_file => "fr_cmplr_v6_3_54d148b4178eb862.mif",
c_coef_file_lines => 18,
c_coef_mem_packing => 0,
c_coef_memtype => 2,
c_coef_path_sign => "0",
c_coef_path_src => "0",
c_coef_path_widths => "16",
c_coef_reload => 0,
c_coef_width => 16,
c_col_config => "1",
c_col_mode => 1,
c_col_pipe_len => 4,
c_component_name => "fr_cmplr_v6_3_54d148b4178eb862",
c_config_packet_size => 0,
c_config_sync_mode => 0,
c_config_tdata_width => 1,
c_data_has_tlast => 0,
c_data_mem_packing => 1,
c_data_memtype => 1,
c_data_path_sign => "0",
c_data_path_src => "0",
c_data_path_widths => "24",
c_data_width => 24,
c_datapath_memtype => 2,
c_decim_rate => 2,
c_ext_mult_cnfg => "none",
c_filter_type => 1,
c_filts_packed => 0,
c_has_aclken => 1,
c_has_aresetn => 0,
c_has_config_channel => 0,
c_input_rate => 1400000,
c_interp_rate => 1,
c_ipbuff_memtype => 2,
c_latency => 18,
c_m_data_has_tready => 0,
c_m_data_has_tuser => 1,
c_m_data_tdata_width => 32,
c_m_data_tuser_width => 2,
c_mem_arrangement => 1,
c_num_channels => 4,
c_num_filts => 1,
c_num_madds => 1,
c_num_reload_slots => 1,
c_num_taps => 35,
c_opbuff_memtype => 0,
c_opt_madds => "none",
c_optimization => 0,
c_output_path_widths => "25",
c_output_rate => 2800000,
c_output_width => 25,
c_oversampling_rate => 9,
c_reload_tdata_width => 1,
c_round_mode => 4,
c_s_data_has_fifo => 0,
c_s_data_has_tuser => 1,
c_s_data_tdata_width => 24,
c_s_data_tuser_width => 2,
c_symmetry => 1,
c_xdevicefamily => "virtex6",
c_zero_packing_factor => 1
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_fr_cmplr_v6_3_54d148b4178eb862
PORT MAP (
aclk => aclk,
aclken => aclken,
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tuser => s_axis_data_tuser,
s_axis_data_tdata => s_axis_data_tdata,
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tuser => m_axis_data_tuser,
m_axis_data_tdata => m_axis_data_tdata,
event_s_data_chanid_incorrect => event_s_data_chanid_incorrect
);
-- synthesis translate_on
END fr_cmplr_v6_3_54d148b4178eb862_a;
| lgpl-3.0 | 4bfcb827283def116fc1c6c6eca9f655 | 0.55288 | 3.569309 | false | false | false | false |
wltr/common-vhdl | generic/majority_glitch_filter/src/rtl/majority_glitch_filter.vhd | 1 | 3,203 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Detect Filter glitches by counting bit occurrences.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity majority_glitch_filter is
generic (
-- Initial value of input signal
init_value_g : std_ulogic := '0';
-- Length of window
max_value_g : positive := 16;
-- Number of '1' within window for output to be '1'
high_threshold_g : positive := 12;
-- Number of '0' within window for output to be '0'
low_threshold_g : natural := 4);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Enable
en_i : in std_ulogic;
-- Input signal
sig_i : in std_ulogic;
-- Filtered output signal
sig_o : out std_ulogic);
end entity majority_glitch_filter;
architecture rtl of majority_glitch_filter is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal cnt : unsigned(integer(ceil(log2(real(max_value_g)))) - 1 downto 0) := (others => '0');
signal sig : std_ulogic := init_value_g;
begin -- architecture rtl
------------------------------------------------------------------------------
-- Assertions
------------------------------------------------------------------------------
assert high_threshold_g < max_value_g
report "high_threshold_g needs to be smaller than max_value_g."
severity error;
assert low_threshold_g < max_value_g
report "low_threshold_g needs to be smaller than max_value_g."
severity error;
assert high_threshold_g > low_threshold_g
report "high_threshold_g needs to be bigger than low_threshold_g."
severity error;
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
sig_o <= sig;
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- Filter signal
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
cnt <= to_unsigned(0, cnt'length);
sig <= init_value_g;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
elsif en_i = '1' then
if sig_i = '1' and to_integer(cnt) < max_value_g - 1 then
cnt <= cnt + 1;
elsif sig_i = '0' and to_integer(cnt) > 0 then
cnt <= cnt - 1;
end if;
if to_integer(cnt) >= high_threshold_g then
sig <= '1';
elsif to_integer(cnt) <= low_threshold_g then
sig <= '0';
end if;
end if;
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 8a9adb977f93460de562182c562f4d2d | 0.458008 | 4.387671 | false | false | false | false |
lerwys/GitTest | hdl/modules/position_calc/generated/virtex6/perl_results.vhd | 1 | 215,753 |
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package conv_pkg is
constant simulating : boolean := false
-- synopsys translate_off
or true
-- synopsys translate_on
;
constant xlUnsigned : integer := 1;
constant xlSigned : integer := 2;
constant xlFloat : integer := 3;
constant xlWrap : integer := 1;
constant xlSaturate : integer := 2;
constant xlTruncate : integer := 1;
constant xlRound : integer := 2;
constant xlRoundBanker : integer := 3;
constant xlAddMode : integer := 1;
constant xlSubMode : integer := 2;
attribute black_box : boolean;
attribute syn_black_box : boolean;
attribute fpga_dont_touch: string;
attribute box_type : string;
attribute keep : string;
attribute syn_keep : boolean;
function std_logic_vector_to_unsigned(inp : std_logic_vector) return unsigned;
function unsigned_to_std_logic_vector(inp : unsigned) return std_logic_vector;
function std_logic_vector_to_signed(inp : std_logic_vector) return signed;
function signed_to_std_logic_vector(inp : signed) return std_logic_vector;
function unsigned_to_signed(inp : unsigned) return signed;
function signed_to_unsigned(inp : signed) return unsigned;
function pos(inp : std_logic_vector; arith : INTEGER) return boolean;
function all_same(inp: std_logic_vector) return boolean;
function all_zeros(inp: std_logic_vector) return boolean;
function is_point_five(inp: std_logic_vector) return boolean;
function all_ones(inp: std_logic_vector) return boolean;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector;
function cast (inp : std_logic_vector; old_bin_pt,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned;
function s2s_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function u2s_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return signed;
function s2u_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2u_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return unsigned;
function u2v_cast (inp : unsigned; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function s2v_cast (inp : signed; old_bin_pt,
new_width, new_bin_pt : INTEGER)
return std_logic_vector;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt,
new_arith : INTEGER) return std_logic_vector;
function max_signed(width : INTEGER) return std_logic_vector;
function min_signed(width : INTEGER) return std_logic_vector;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER) return std_logic_vector;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return std_logic_vector;
function pad_LSB(inp : std_logic_vector; new_width, arith : integer)
return std_logic_vector;
function max(L, R: INTEGER) return INTEGER;
function min(L, R: INTEGER) return INTEGER;
function "="(left,right: STRING) return boolean;
function boolean_to_signed (inp : boolean; width: integer)
return signed;
function boolean_to_unsigned (inp : boolean; width: integer)
return unsigned;
function boolean_to_vector (inp : boolean)
return std_logic_vector;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector;
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector;
function hex_string_to_std_logic_vector (inp : string; width : integer)
return std_logic_vector;
function makeZeroBinStr (width : integer) return STRING;
function and_reduce(inp: std_logic_vector) return std_logic;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean;
function is_binary_string_undefined (inp : string)
return boolean;
function is_XorU(inp : std_logic_vector)
return boolean;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector;
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector;
constant display_precision : integer := 20;
function real_to_string (inp : real) return string;
function valid_bin_string(inp : string) return boolean;
function std_logic_vector_to_bin_string(inp : std_logic_vector) return string;
function std_logic_to_bin_string(inp : std_logic) return string;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string;
type stdlogic_to_char_t is array(std_logic) of character;
constant to_char : stdlogic_to_char_t := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => 'L',
'H' => 'H',
'-' => '-');
-- synopsys translate_on
end conv_pkg;
package body conv_pkg is
function std_logic_vector_to_unsigned(inp : std_logic_vector)
return unsigned
is
begin
return unsigned (inp);
end;
function unsigned_to_std_logic_vector(inp : unsigned)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function std_logic_vector_to_signed(inp : std_logic_vector)
return signed
is
begin
return signed (inp);
end;
function signed_to_std_logic_vector(inp : signed)
return std_logic_vector
is
begin
return std_logic_vector(inp);
end;
function unsigned_to_signed (inp : unsigned)
return signed
is
begin
return signed(std_logic_vector(inp));
end;
function signed_to_unsigned (inp : signed)
return unsigned
is
begin
return unsigned(std_logic_vector(inp));
end;
function pos(inp : std_logic_vector; arith : INTEGER)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
return true;
else
if vec(width-1) = '0' then
return true;
else
return false;
end if;
end if;
return true;
end;
function max_signed(width : INTEGER)
return std_logic_vector
is
variable ones : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
ones := (others => '1');
result(width-1) := '0';
result(width-2 downto 0) := ones;
return result;
end;
function min_signed(width : INTEGER)
return std_logic_vector
is
variable zeros : std_logic_vector(width-2 downto 0);
variable result : std_logic_vector(width-1 downto 0);
begin
zeros := (others => '0');
result(width-1) := '1';
result(width-2 downto 0) := zeros;
return result;
end;
function and_reduce(inp: std_logic_vector) return std_logic
is
variable result: std_logic;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := vec(0);
if width > 1 then
for i in 1 to width-1 loop
result := result and vec(i);
end loop;
end if;
return result;
end;
function all_same(inp: std_logic_vector) return boolean
is
variable result: boolean;
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := true;
if width > 0 then
for i in 1 to width-1 loop
if vec(i) /= vec(0) then
result := false;
end if;
end loop;
end if;
return result;
end;
function all_zeros(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable zero : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
zero := (others => '0');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(zero)) then
result := true;
else
result := false;
end if;
return result;
end;
function is_point_five(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (width > 1) then
if ((vec(width-1) = '1') and (all_zeros(vec(width-2 downto 0)) = true)) then
result := true;
else
result := false;
end if;
else
if (vec(width-1) = '1') then
result := true;
else
result := false;
end if;
end if;
return result;
end;
function all_ones(inp: std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable one : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
one := (others => '1');
vec := inp;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if (std_logic_vector_to_unsigned(vec) = std_logic_vector_to_unsigned(one)) then
result := true;
else
result := false;
end if;
return result;
end;
function full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return integer
is
variable result : integer;
begin
result := old_width + 2;
return result;
end;
function quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return integer
is
variable right_of_dp, left_of_dp, result : integer;
begin
right_of_dp := max(new_bin_pt, old_bin_pt);
left_of_dp := max((new_width - new_bin_pt), (old_width - old_bin_pt));
result := (old_width + 2) + (new_bin_pt - old_bin_pt);
return result;
end;
function convert_type (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith,
quantization, overflow : INTEGER)
return std_logic_vector
is
constant fp_width : integer :=
full_precision_num_width(quantization, overflow, old_width,
old_bin_pt, old_arith, new_width,
new_bin_pt, new_arith);
constant fp_bin_pt : integer := old_bin_pt;
constant fp_arith : integer := old_arith;
variable full_precision_result : std_logic_vector(fp_width-1 downto 0);
constant q_width : integer :=
quantized_num_width(quantization, overflow, old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith);
constant q_bin_pt : integer := new_bin_pt;
constant q_arith : integer := old_arith;
variable quantized_result : std_logic_vector(q_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
result := (others => '0');
full_precision_result := cast(inp, old_bin_pt, fp_width, fp_bin_pt,
fp_arith);
if (quantization = xlRound) then
quantized_result := round_towards_inf(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
elsif (quantization = xlRoundBanker) then
quantized_result := round_towards_even(full_precision_result,
fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt,
q_arith);
else
quantized_result := trunc(full_precision_result, fp_width, fp_bin_pt,
fp_arith, q_width, q_bin_pt, q_arith);
end if;
if (overflow = xlSaturate) then
result := saturation_arith(quantized_result, q_width, q_bin_pt,
q_arith, new_width, new_bin_pt, new_arith);
else
result := wrap_arith(quantized_result, q_width, q_bin_pt, q_arith,
new_width, new_bin_pt, new_arith);
end if;
return result;
end;
function cast (inp : std_logic_vector; old_bin_pt, new_width,
new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
constant left_of_dp : integer := (new_width - new_bin_pt)
- (old_width - old_bin_pt);
constant right_of_dp : integer := (new_bin_pt - old_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable j : integer;
begin
vec := inp;
for i in new_width-1 downto 0 loop
j := i - right_of_dp;
if ( j > old_width-1) then
if (new_arith = xlUnsigned) then
result(i) := '0';
else
result(i) := vec(old_width-1);
end if;
elsif ( j >= 0) then
result(i) := vec(j);
else
result(i) := '0';
end if;
end loop;
return result;
end;
function shift_division_result(quotient, fraction: std_logic_vector;
fraction_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant q_width : integer := quotient'length;
constant f_width : integer := fraction'length;
constant vec_MSB : integer := q_width+f_width-1;
constant result_MSB : integer := q_width+fraction_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := ( quotient & fraction );
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function shift_op (inp: std_logic_vector;
result_width, shift_value, shift_dir: INTEGER)
return std_logic_vector
is
constant inp_width : integer := inp'length;
constant vec_MSB : integer := inp_width-1;
constant result_MSB : integer := result_width-1;
constant result_LSB : integer := vec_MSB-result_MSB;
variable vec : std_logic_vector(vec_MSB downto 0);
variable result : std_logic_vector(result_MSB downto 0);
begin
vec := inp;
if shift_dir = 1 then
for i in vec_MSB downto 0 loop
if (i < shift_value) then
vec(i) := '0';
else
vec(i) := vec(i-shift_value);
end if;
end loop;
else
for i in 0 to vec_MSB loop
if (i > vec_MSB-shift_value) then
vec(i) := vec(vec_MSB);
else
vec(i) := vec(i+shift_value);
end if;
end loop;
end if;
result := vec(vec_MSB downto result_LSB);
return result;
end;
function vec_slice (inp : std_logic_vector; upper, lower : INTEGER)
return std_logic_vector
is
begin
return inp(upper downto lower);
end;
function s2u_slice (inp : signed; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function u2u_slice (inp : unsigned; upper, lower : INTEGER)
return unsigned
is
begin
return unsigned(vec_slice(std_logic_vector(inp), upper, lower));
end;
function s2s_cast (inp : signed; old_bin_pt, new_width, new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function s2u_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned));
end;
function u2s_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return signed
is
begin
return signed(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2u_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return unsigned
is
begin
return unsigned(cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned));
end;
function u2v_cast (inp : unsigned; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlUnsigned);
end;
function s2v_cast (inp : signed; old_bin_pt, new_width,
new_bin_pt : INTEGER)
return std_logic_vector
is
begin
return cast(std_logic_vector(inp), old_bin_pt, new_width, new_bin_pt, xlSigned);
end;
function boolean_to_signed (inp : boolean; width : integer)
return signed
is
variable result : signed(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_unsigned (inp : boolean; width : integer)
return unsigned
is
variable result : unsigned(width - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function boolean_to_vector (inp : boolean)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result := (others => '0');
if inp then
result(0) := '1';
else
result(0) := '0';
end if;
return result;
end;
function std_logic_to_vector (inp : std_logic)
return std_logic_vector
is
variable result : std_logic_vector(1 - 1 downto 0);
begin
result(0) := inp;
return result;
end;
function trunc (inp : std_logic_vector; old_width, old_bin_pt, old_arith,
new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
result := zero_ext(vec(old_width-1 downto right_of_dp), new_width);
else
result := sign_ext(vec(old_width-1 downto right_of_dp), new_width);
end if;
else
if new_arith = xlUnsigned then
result := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
result := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
return result;
end;
function round_towards_inf (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (new_arith = xlSigned) then
if (vec(old_width-1) = '0') then
one_or_zero(0) := '1';
end if;
if (right_of_dp >= 2) and (right_of_dp <= old_width) then
if (all_zeros(vec(right_of_dp-2 downto 0)) = false) then
one_or_zero(0) := '1';
end if;
end if;
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if vec(right_of_dp-1) = '0' then
one_or_zero(0) := '0';
end if;
else
one_or_zero(0) := '0';
end if;
else
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
one_or_zero(0) := vec(right_of_dp-1);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function round_towards_even (inp : std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant right_of_dp : integer := (old_bin_pt - new_bin_pt);
constant expected_new_width : integer := old_width - right_of_dp + 1;
variable vec : std_logic_vector(old_width-1 downto 0);
variable one_or_zero : std_logic_vector(new_width-1 downto 0);
variable truncated_val : std_logic_vector(new_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if right_of_dp >= 0 then
if new_arith = xlUnsigned then
truncated_val := zero_ext(vec(old_width-1 downto right_of_dp),
new_width);
else
truncated_val := sign_ext(vec(old_width-1 downto right_of_dp),
new_width);
end if;
else
if new_arith = xlUnsigned then
truncated_val := zero_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
else
truncated_val := sign_ext(pad_LSB(vec, old_width +
abs(right_of_dp)), new_width);
end if;
end if;
one_or_zero := (others => '0');
if (right_of_dp >= 1) and (right_of_dp <= old_width) then
if (is_point_five(vec(right_of_dp-1 downto 0)) = false) then
one_or_zero(0) := vec(right_of_dp-1);
else
one_or_zero(0) := vec(right_of_dp);
end if;
end if;
if new_arith = xlSigned then
result := signed_to_std_logic_vector(std_logic_vector_to_signed(truncated_val) +
std_logic_vector_to_signed(one_or_zero));
else
result := unsigned_to_std_logic_vector(std_logic_vector_to_unsigned(truncated_val) +
std_logic_vector_to_unsigned(one_or_zero));
end if;
return result;
end;
function saturation_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith
: INTEGER)
return std_logic_vector
is
constant left_of_dp : integer := (old_width - old_bin_pt) -
(new_width - new_bin_pt);
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable overflow : boolean;
begin
vec := inp;
overflow := true;
result := (others => '0');
if (new_width >= old_width) then
overflow := false;
end if;
if ((old_arith = xlSigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if (old_arith = xlSigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
if (vec(new_width-1) = '0') then
overflow := false;
end if;
end if;
end if;
end if;
if (old_arith = xlUnsigned and new_arith = xlUnsigned) then
if (old_width > new_width) then
if all_zeros(vec(old_width-1 downto new_width)) then
overflow := false;
end if;
else
if (old_width = new_width) then
overflow := false;
end if;
end if;
end if;
if ((old_arith = xlUnsigned and new_arith = xlSigned) and (old_width > new_width)) then
if all_same(vec(old_width-1 downto new_width-1)) then
overflow := false;
end if;
end if;
if overflow then
if new_arith = xlSigned then
if vec(old_width-1) = '0' then
result := max_signed(new_width);
else
result := min_signed(new_width);
end if;
else
if ((old_arith = xlSigned) and vec(old_width-1) = '1') then
result := (others => '0');
else
result := (others => '1');
end if;
end if;
else
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
if (vec(old_width-1) = '1') then
vec := (others => '0');
end if;
end if;
if new_width <= old_width then
result := vec(new_width-1 downto 0);
else
if new_arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
end if;
end if;
return result;
end;
function wrap_arith(inp: std_logic_vector; old_width, old_bin_pt,
old_arith, new_width, new_bin_pt, new_arith : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
variable result_arith : integer;
begin
if (old_arith = xlSigned) and (new_arith = xlUnsigned) then
result_arith := xlSigned;
end if;
result := cast(inp, old_bin_pt, new_width, new_bin_pt, result_arith);
return result;
end;
function fractional_bits(a_bin_pt, b_bin_pt: INTEGER) return INTEGER is
begin
return max(a_bin_pt, b_bin_pt);
end;
function integer_bits(a_width, a_bin_pt, b_width, b_bin_pt: INTEGER)
return INTEGER is
begin
return max(a_width - a_bin_pt, b_width - b_bin_pt);
end;
function pad_LSB(inp : std_logic_vector; new_width: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
constant pad_pos : integer := new_width - orig_width - 1;
begin
vec := inp;
pos := new_width-1;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pad_pos >= 0 then
for i in pad_pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function sign_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := vec(old_width-1);
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic_vector; new_width : INTEGER)
return std_logic_vector
is
constant old_width : integer := inp'length;
variable vec : std_logic_vector(old_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if new_width >= old_width then
result(old_width-1 downto 0) := vec;
if new_width-1 >= old_width then
for i in new_width-1 downto old_width loop
result(i) := '0';
end loop;
end if;
else
result(new_width-1 downto 0) := vec(new_width-1 downto 0);
end if;
return result;
end;
function zero_ext(inp : std_logic; new_width : INTEGER)
return std_logic_vector
is
variable result : std_logic_vector(new_width-1 downto 0);
begin
result(0) := inp;
for i in new_width-1 downto 1 loop
result(i) := '0';
end loop;
return result;
end;
function extend_MSB(inp : std_logic_vector; new_width, arith : INTEGER)
return std_logic_vector
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if arith = xlUnsigned then
result := zero_ext(vec, new_width);
else
result := sign_ext(vec, new_width);
end if;
return result;
end;
function pad_LSB(inp : std_logic_vector; new_width, arith: integer)
return STD_LOGIC_VECTOR
is
constant orig_width : integer := inp'length;
variable vec : std_logic_vector(orig_width-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
variable pos : integer;
begin
vec := inp;
pos := new_width-1;
if (arith = xlUnsigned) then
result(pos) := '0';
pos := pos - 1;
else
result(pos) := vec(orig_width-1);
pos := pos - 1;
end if;
if (new_width >= orig_width) then
for i in orig_width-1 downto 0 loop
result(pos) := vec(i);
pos := pos - 1;
end loop;
if pos >= 0 then
for i in pos downto 0 loop
result(i) := '0';
end loop;
end if;
end if;
return result;
end;
function align_input(inp : std_logic_vector; old_width, delta, new_arith,
new_width: INTEGER)
return std_logic_vector
is
variable vec : std_logic_vector(old_width-1 downto 0);
variable padded_inp : std_logic_vector((old_width + delta)-1 downto 0);
variable result : std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if delta > 0 then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
function max(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
function "="(left,right: STRING) return boolean is
begin
if (left'length /= right'length) then
return false;
else
test : for i in 1 to left'length loop
if left(i) /= right(i) then
return false;
end if;
end loop test;
return true;
end if;
end;
-- synopsys translate_off
function is_binary_string_invalid (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'X' ) then
result := true;
end if;
end loop;
return result;
end;
function is_binary_string_undefined (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 1 to vec'length loop
if ( vec(i) = 'U' ) then
result := true;
end if;
end loop;
return result;
end;
function is_XorU(inp : std_logic_vector)
return boolean
is
constant width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable result : boolean;
begin
vec := inp;
result := false;
for i in 0 to width-1 loop
if (vec(i) = 'U') or (vec(i) = 'X') then
result := true;
end if;
end loop;
return result;
end;
function to_real(inp : std_logic_vector; bin_pt : integer; arith : integer)
return real
is
variable vec : std_logic_vector(inp'length-1 downto 0);
variable result, shift_val, undefined_real : real;
variable neg_num : boolean;
begin
vec := inp;
result := 0.0;
neg_num := false;
if vec(inp'length-1) = '1' then
neg_num := true;
end if;
for i in 0 to inp'length-1 loop
if vec(i) = 'U' or vec(i) = 'X' then
return undefined_real;
end if;
if arith = xlSigned then
if neg_num then
if vec(i) = '0' then
result := result + 2.0**i;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
else
if vec(i) = '1' then
result := result + 2.0**i;
end if;
end if;
end loop;
if arith = xlSigned then
if neg_num then
result := result + 1.0;
result := result * (-1.0);
end if;
end if;
shift_val := 2.0**(-1*bin_pt);
result := result * shift_val;
return result;
end;
function std_logic_to_real(inp : std_logic; bin_pt : integer; arith : integer)
return real
is
variable result : real := 0.0;
begin
if inp = '1' then
result := 1.0;
end if;
if arith = xlSigned then
assert false
report "It doesn't make sense to convert a 1 bit number to a signed real.";
end if;
return result;
end;
-- synopsys translate_on
function integer_to_std_logic_vector (inp : integer; width, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
begin
if (arith = xlSigned) then
signed_val := to_signed(inp, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(inp, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
function std_logic_vector_to_integer (inp : std_logic_vector; arith : integer)
return integer
is
constant width : integer := inp'length;
variable unsigned_val : unsigned(width-1 downto 0);
variable signed_val : signed(width-1 downto 0);
variable result : integer;
begin
if (arith = xlSigned) then
signed_val := std_logic_vector_to_signed(inp);
result := to_integer(signed_val);
else
unsigned_val := std_logic_vector_to_unsigned(inp);
result := to_integer(unsigned_val);
end if;
return result;
end;
function std_logic_to_integer(constant inp : std_logic := '0')
return integer
is
begin
if inp = '1' then
return 1;
else
return 0;
end if;
end;
function makeZeroBinStr (width : integer) return STRING is
variable result : string(1 to width+3);
begin
result(1) := '0';
result(2) := 'b';
for i in 3 to width+2 loop
result(i) := '0';
end loop;
result(width+3) := '.';
return result;
end;
-- synopsys translate_off
function real_string_to_std_logic_vector (inp : string; width, bin_pt, arith : integer)
return std_logic_vector
is
variable result : std_logic_vector(width-1 downto 0);
begin
result := (others => '0');
return result;
end;
function real_to_std_logic_vector (inp : real; width, bin_pt, arith : integer)
return std_logic_vector
is
variable real_val : real;
variable int_val : integer;
variable result : std_logic_vector(width-1 downto 0) := (others => '0');
variable unsigned_val : unsigned(width-1 downto 0) := (others => '0');
variable signed_val : signed(width-1 downto 0) := (others => '0');
begin
real_val := inp;
int_val := integer(real_val * 2.0**(bin_pt));
if (arith = xlSigned) then
signed_val := to_signed(int_val, width);
result := signed_to_std_logic_vector(signed_val);
else
unsigned_val := to_unsigned(int_val, width);
result := unsigned_to_std_logic_vector(unsigned_val);
end if;
return result;
end;
-- synopsys translate_on
function valid_bin_string (inp : string)
return boolean
is
variable vec : string(1 to inp'length);
begin
vec := inp;
if (vec(1) = '0' and vec(2) = 'b') then
return true;
else
return false;
end if;
end;
function hex_string_to_std_logic_vector(inp: string; width : integer)
return std_logic_vector is
constant strlen : integer := inp'LENGTH;
variable result : std_logic_vector(width-1 downto 0);
variable bitval : std_logic_vector((strlen*4)-1 downto 0);
variable posn : integer;
variable ch : character;
variable vec : string(1 to strlen);
begin
vec := inp;
result := (others => '0');
posn := (strlen*4)-1;
for i in 1 to strlen loop
ch := vec(i);
case ch is
when '0' => bitval(posn downto posn-3) := "0000";
when '1' => bitval(posn downto posn-3) := "0001";
when '2' => bitval(posn downto posn-3) := "0010";
when '3' => bitval(posn downto posn-3) := "0011";
when '4' => bitval(posn downto posn-3) := "0100";
when '5' => bitval(posn downto posn-3) := "0101";
when '6' => bitval(posn downto posn-3) := "0110";
when '7' => bitval(posn downto posn-3) := "0111";
when '8' => bitval(posn downto posn-3) := "1000";
when '9' => bitval(posn downto posn-3) := "1001";
when 'A' | 'a' => bitval(posn downto posn-3) := "1010";
when 'B' | 'b' => bitval(posn downto posn-3) := "1011";
when 'C' | 'c' => bitval(posn downto posn-3) := "1100";
when 'D' | 'd' => bitval(posn downto posn-3) := "1101";
when 'E' | 'e' => bitval(posn downto posn-3) := "1110";
when 'F' | 'f' => bitval(posn downto posn-3) := "1111";
when others => bitval(posn downto posn-3) := "XXXX";
-- synopsys translate_off
ASSERT false
REPORT "Invalid hex value" SEVERITY ERROR;
-- synopsys translate_on
end case;
posn := posn - 4;
end loop;
if (width <= strlen*4) then
result := bitval(width-1 downto 0);
else
result((strlen*4)-1 downto 0) := bitval;
end if;
return result;
end;
function bin_string_to_std_logic_vector (inp : string)
return std_logic_vector
is
variable pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(inp'length-1 downto 0);
begin
vec := inp;
pos := inp'length-1;
result := (others => '0');
for i in 1 to vec'length loop
-- synopsys translate_off
if (pos < 0) and (vec(i) = '0' or vec(i) = '1' or vec(i) = 'X' or vec(i) = 'U') then
assert false
report "Input string is larger than output std_logic_vector. Truncating output.";
return result;
end if;
-- synopsys translate_on
if vec(i) = '0' then
result(pos) := '0';
pos := pos - 1;
end if;
if vec(i) = '1' then
result(pos) := '1';
pos := pos - 1;
end if;
-- synopsys translate_off
if (vec(i) = 'X' or vec(i) = 'U') then
result(pos) := 'U';
pos := pos - 1;
end if;
-- synopsys translate_on
end loop;
return result;
end;
function bin_string_element_to_std_logic_vector (inp : string; width, index : integer)
return std_logic_vector
is
constant str_width : integer := width + 4;
constant inp_len : integer := inp'length;
constant num_elements : integer := (inp_len + 1)/str_width;
constant reverse_index : integer := (num_elements-1) - index;
variable left_pos : integer;
variable right_pos : integer;
variable vec : string(1 to inp'length);
variable result : std_logic_vector(width-1 downto 0);
begin
vec := inp;
result := (others => '0');
if (reverse_index = 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := 1;
right_pos := width + 3;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
if (reverse_index > 0) and (reverse_index < num_elements) and (inp_len-3 >= width) then
left_pos := (reverse_index * str_width) + 1;
right_pos := left_pos + width + 2;
result := bin_string_to_std_logic_vector(vec(left_pos to right_pos));
end if;
return result;
end;
-- synopsys translate_off
function std_logic_vector_to_bin_string(inp : std_logic_vector)
return string
is
variable vec : std_logic_vector(1 to inp'length);
variable result : string(vec'range);
begin
vec := inp;
for i in vec'range loop
result(i) := to_char(vec(i));
end loop;
return result;
end;
function std_logic_to_bin_string(inp : std_logic)
return string
is
variable result : string(1 to 3);
begin
result(1) := '0';
result(2) := 'b';
result(3) := to_char(inp);
return result;
end;
function std_logic_vector_to_bin_string_w_point(inp : std_logic_vector; bin_pt : integer)
return string
is
variable width : integer := inp'length;
variable vec : std_logic_vector(width-1 downto 0);
variable str_pos : integer;
variable result : string(1 to width+3);
begin
vec := inp;
str_pos := 1;
result(str_pos) := '0';
str_pos := 2;
result(str_pos) := 'b';
str_pos := 3;
for i in width-1 downto 0 loop
if (((width+3) - bin_pt) = str_pos) then
result(str_pos) := '.';
str_pos := str_pos + 1;
end if;
result(str_pos) := to_char(vec(i));
str_pos := str_pos + 1;
end loop;
if (bin_pt = 0) then
result(str_pos) := '.';
end if;
return result;
end;
function real_to_bin_string(inp : real; width, bin_pt, arith : integer)
return string
is
variable result : string(1 to width);
variable vec : std_logic_vector(width-1 downto 0);
begin
vec := real_to_std_logic_vector(inp, width, bin_pt, arith);
result := std_logic_vector_to_bin_string(vec);
return result;
end;
function real_to_string (inp : real) return string
is
variable result : string(1 to display_precision) := (others => ' ');
begin
result(real'image(inp)'range) := real'image(inp);
return result;
end;
-- synopsys translate_on
end conv_pkg;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity srl17e is
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end srl17e;
architecture structural of srl17e is
component SRL16E
port (D : in STD_ULOGIC;
CE : in STD_ULOGIC;
CLK : in STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
Q : out STD_ULOGIC);
end component;
attribute syn_black_box of SRL16E : component is true;
attribute fpga_dont_touch of SRL16E : component is "true";
component FDE
port(
Q : out STD_ULOGIC;
D : in STD_ULOGIC;
C : in STD_ULOGIC;
CE : in STD_ULOGIC);
end component;
attribute syn_black_box of FDE : component is true;
attribute fpga_dont_touch of FDE : component is "true";
constant a : std_logic_vector(4 downto 0) :=
integer_to_std_logic_vector(latency-2,5,xlSigned);
signal d_delayed : std_logic_vector(width-1 downto 0);
signal srl16_out : std_logic_vector(width-1 downto 0);
begin
d_delayed <= d after 200 ps;
reg_array : for i in 0 to width-1 generate
srl16_used: if latency > 1 generate
u1 : srl16e port map(clk => clk,
d => d_delayed(i),
q => srl16_out(i),
ce => ce,
a0 => a(0),
a1 => a(1),
a2 => a(2),
a3 => a(3));
end generate;
srl16_not_used: if latency <= 1 generate
srl16_out(i) <= d_delayed(i);
end generate;
fde_used: if latency /= 0 generate
u2 : fde port map(c => clk,
d => srl16_out(i),
q => q(i),
ce => ce);
end generate;
fde_not_used: if latency = 0 generate
q(i) <= srl16_out(i);
end generate;
end generate;
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg;
architecture structural of synth_reg is
component srl17e
generic (width : integer:=16;
latency : integer :=8);
port (clk : in std_logic;
ce : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0));
end component;
function calc_num_srl17es (latency : integer)
return integer
is
variable remaining_latency : integer;
variable result : integer;
begin
result := latency / 17;
remaining_latency := latency - (result * 17);
if (remaining_latency /= 0) then
result := result + 1;
end if;
return result;
end;
constant complete_num_srl17es : integer := latency / 17;
constant num_srl17es : integer := calc_num_srl17es(latency);
constant remaining_latency : integer := latency - (complete_num_srl17es * 17);
type register_array is array (num_srl17es downto 0) of
std_logic_vector(width-1 downto 0);
signal z : register_array;
begin
z(0) <= i;
complete_ones : if complete_num_srl17es > 0 generate
srl17e_array: for i in 0 to complete_num_srl17es-1 generate
delay_comp : srl17e
generic map (width => width,
latency => 17)
port map (clk => clk,
ce => ce,
d => z(i),
q => z(i+1));
end generate;
end generate;
partial_one : if remaining_latency > 0 generate
last_srl17e : srl17e
generic map (width => width,
latency => remaining_latency)
port map (clk => clk,
ce => ce,
d => z(num_srl17es-1),
q => z(num_srl17es));
end generate;
o <= z(num_srl17es);
end structural;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_reg is
generic (width : integer := 8;
latency : integer := 1);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end synth_reg_reg;
architecture behav of synth_reg_reg is
type reg_array_type is array (latency-1 downto 0) of std_logic_vector(width -1 downto 0);
signal reg_bank : reg_array_type := (others => (others => '0'));
signal reg_bank_in : reg_array_type := (others => (others => '0'));
attribute syn_allow_retiming : boolean;
attribute syn_srlstyle : string;
attribute syn_allow_retiming of reg_bank : signal is true;
attribute syn_allow_retiming of reg_bank_in : signal is true;
attribute syn_srlstyle of reg_bank : signal is "registers";
attribute syn_srlstyle of reg_bank_in : signal is "registers";
begin
latency_eq_0: if latency = 0 generate
o <= i;
end generate latency_eq_0;
latency_gt_0: if latency >= 1 generate
o <= reg_bank(latency-1);
reg_bank_in(0) <= i;
loop_gen: for idx in latency-2 downto 0 generate
reg_bank_in(idx+1) <= reg_bank(idx);
end generate loop_gen;
sync_loop: for sync_idx in latency-1 downto 0 generate
sync_proc: process (clk)
begin
if clk'event and clk = '1' then
if clr = '1' then
reg_bank_in <= (others => (others => '0'));
elsif ce = '1' then
reg_bank(sync_idx) <= reg_bank_in(sync_idx);
end if;
end if;
end process sync_proc;
end generate sync_loop;
end generate latency_gt_0;
end behav;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity single_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end single_reg_w_init;
architecture structural of single_reg_w_init is
function build_init_const(width: integer;
init_index: integer;
init_value: bit_vector)
return std_logic_vector
is
variable result: std_logic_vector(width - 1 downto 0);
begin
if init_index = 0 then
result := (others => '0');
elsif init_index = 1 then
result := (others => '0');
result(0) := '1';
else
result := to_stdlogicvector(init_value);
end if;
return result;
end;
component fdre
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
r: in std_ulogic
);
end component;
attribute syn_black_box of fdre: component is true;
attribute fpga_dont_touch of fdre: component is "true";
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
ce: in std_ulogic;
s: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
constant init_const: std_logic_vector(width - 1 downto 0)
:= build_init_const(width, init_index, init_value);
begin
fd_prim_array: for index in 0 to width - 1 generate
bit_is_0: if (init_const(index) = '0') generate
fdre_comp: fdre
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
r => clr
);
end generate;
bit_is_1: if (init_const(index) = '1') generate
fdse_comp: fdse
port map (
c => clk,
d => i(index),
q => o(index),
ce => ce,
s => clr
);
end generate;
end generate;
end architecture structural;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity synth_reg_w_init is
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000";
latency: integer := 1
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end synth_reg_w_init;
architecture structural of synth_reg_w_init is
component single_reg_w_init
generic (
width: integer := 8;
init_index: integer := 0;
init_value: bit_vector := b"0000"
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
signal dly_i: std_logic_vector((latency + 1) * width - 1 downto 0);
signal dly_clr: std_logic;
begin
latency_eq_0: if (latency = 0) generate
o <= i;
end generate;
latency_gt_0: if (latency >= 1) generate
dly_i((latency + 1) * width - 1 downto latency * width) <= i
after 200 ps;
dly_clr <= clr after 200 ps;
fd_array: for index in latency downto 1 generate
reg_comp: single_reg_w_init
generic map (
width => width,
init_index => init_index,
init_value => init_value
)
port map (
clk => clk,
i => dly_i((index + 1) * width - 1 downto index * width),
o => dly_i(index * width - 1 downto (index - 1) * width),
ce => ce,
clr => dly_clr
);
end generate;
o <= dly_i(width - 1 downto 0);
end generate;
end structural;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlclockenablegenerator is
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5
);
port (
clk: in std_logic;
clr: in std_logic;
ce: out std_logic
);
end xlclockenablegenerator;
architecture behavior of xlclockenablegenerator is
component synth_reg_w_init
generic (
width: integer;
init_index: integer;
init_value: bit_vector;
latency: integer
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function size_of_uint(inp: integer; power_of_2: boolean)
return integer
is
constant inp_vec: std_logic_vector(31 downto 0) :=
integer_to_std_logic_vector(inp,32, xlUnsigned);
variable result: integer;
begin
result := 32;
for i in 0 to 31 loop
if inp_vec(i) = '1' then
result := i;
end if;
end loop;
if power_of_2 then
return result;
else
return result+1;
end if;
end;
function is_power_of_2(inp: std_logic_vector)
return boolean
is
constant width: integer := inp'length;
variable vec: std_logic_vector(width - 1 downto 0);
variable single_bit_set: boolean;
variable more_than_one_bit_set: boolean;
variable result: boolean;
begin
vec := inp;
single_bit_set := false;
more_than_one_bit_set := false;
-- synopsys translate_off
if (is_XorU(vec)) then
return false;
end if;
-- synopsys translate_on
if width > 0 then
for i in 0 to width - 1 loop
if vec(i) = '1' then
if single_bit_set then
more_than_one_bit_set := true;
end if;
single_bit_set := true;
end if;
end loop;
end if;
if (single_bit_set and not(more_than_one_bit_set)) then
result := true;
else
result := false;
end if;
return result;
end;
function ce_reg_init_val(index, period : integer)
return integer
is
variable result: integer;
begin
result := 0;
if ((index mod period) = 0) then
result := 1;
end if;
return result;
end;
function remaining_pipe_regs(num_pipeline_regs, period : integer)
return integer
is
variable factor, result: integer;
begin
factor := (num_pipeline_regs / period);
result := num_pipeline_regs - (period * factor) + 1;
return result;
end;
function sg_min(L, R: INTEGER) return INTEGER is
begin
if L < R then
return L;
else
return R;
end if;
end;
constant max_pipeline_regs : integer := 8;
constant pipe_regs : integer := 5;
constant num_pipeline_regs : integer := sg_min(pipeline_regs, max_pipeline_regs);
constant rem_pipeline_regs : integer := remaining_pipe_regs(num_pipeline_regs,period);
constant period_floor: integer := max(2, period);
constant power_of_2_counter: boolean :=
is_power_of_2(integer_to_std_logic_vector(period_floor,32, xlUnsigned));
constant cnt_width: integer :=
size_of_uint(period_floor, power_of_2_counter);
constant clk_for_ce_pulse_minus1: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector((period_floor - 2),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus2: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - 3),cnt_width, xlUnsigned);
constant clk_for_ce_pulse_minus_regs: std_logic_vector(cnt_width - 1 downto 0) :=
integer_to_std_logic_vector(max(0,period - rem_pipeline_regs),cnt_width, xlUnsigned);
signal clk_num: unsigned(cnt_width - 1 downto 0) := (others => '0');
signal ce_vec : std_logic_vector(num_pipeline_regs downto 0);
signal internal_ce: std_logic_vector(0 downto 0);
signal cnt_clr, cnt_clr_dly: std_logic_vector (0 downto 0);
begin
cntr_gen: process(clk)
begin
if clk'event and clk = '1' then
if ((cnt_clr_dly(0) = '1') or (clr = '1')) then
clk_num <= (others => '0');
else
clk_num <= clk_num + 1;
end if;
end if;
end process;
clr_gen: process(clk_num, clr)
begin
if power_of_2_counter then
cnt_clr(0) <= clr;
else
if (unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus1
or clr = '1') then
cnt_clr(0) <= '1';
else
cnt_clr(0) <= '0';
end if;
end if;
end process;
clr_reg: synth_reg_w_init
generic map (
width => 1,
init_index => 0,
init_value => b"0000",
latency => 1
)
port map (
i => cnt_clr,
ce => '1',
clr => clr,
clk => clk,
o => cnt_clr_dly
);
pipelined_ce : if period > 1 generate
ce_gen: process(clk_num)
begin
if unsigned_to_std_logic_vector(clk_num) = clk_for_ce_pulse_minus_regs then
ce_vec(num_pipeline_regs) <= '1';
else
ce_vec(num_pipeline_regs) <= '0';
end if;
end process;
ce_pipeline: for index in num_pipeline_regs downto 1 generate
ce_reg : synth_reg_w_init
generic map (
width => 1,
init_index => ce_reg_init_val(index, period),
init_value => b"0000",
latency => 1
)
port map (
i => ce_vec(index downto index),
ce => '1',
clr => clr,
clk => clk,
o => ce_vec(index-1 downto index-1)
);
end generate;
internal_ce <= ce_vec(0 downto 0);
end generate;
generate_clock_enable: if period > 1 generate
ce <= internal_ce(0);
end generate;
generate_clock_enable_constant: if period = 1 generate
ce <= '1';
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_cd3162dc0d is
port (
in0 : in std_logic_vector((16 - 1) downto 0);
in1 : in std_logic_vector((8 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_cd3162dc0d;
architecture behavior of concat_cd3162dc0d is
signal in0_1_23: unsigned((16 - 1) downto 0);
signal in1_1_27: unsigned((8 - 1) downto 0);
signal y_2_1_concat: unsigned((24 - 1) downto 0);
begin
in0_1_23 <= std_logic_vector_to_unsigned(in0);
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_91ef1678ca is
port (
op : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_91ef1678ca;
architecture behavior of constant_91ef1678ca is
begin
op <= "00000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_7025463ea8 is
port (
input_port : in std_logic_vector((16 - 1) downto 0);
output_port : out std_logic_vector((16 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_7025463ea8;
architecture behavior of reinterpret_7025463ea8 is
signal input_port_1_40: signed((16 - 1) downto 0);
signal output_port_5_5_force: unsigned((16 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_f21e7f2ddf is
port (
input_port : in std_logic_vector((8 - 1) downto 0);
output_port : out std_logic_vector((8 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_f21e7f2ddf;
architecture behavior of reinterpret_f21e7f2ddf is
signal input_port_1_40: unsigned((8 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
output_port <= unsigned_to_std_logic_vector(input_port_1_40);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_4bf1ad328a is
port (
input_port : in std_logic_vector((24 - 1) downto 0);
output_port : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_4bf1ad328a;
architecture behavior of reinterpret_4bf1ad328a is
signal input_port_1_40: unsigned((24 - 1) downto 0);
signal output_port_5_5_force: signed((24 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlceprobe is
generic (d_width : integer := 8;
q_width : integer := 1);
port (d : in std_logic_vector (d_width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (q_width-1 downto 0));
end xlceprobe;
architecture behavior of xlceprobe is
component BUF
port(
O : out STD_ULOGIC;
I : in STD_ULOGIC);
end component;
attribute syn_black_box of BUF : component is true;
attribute fpga_dont_touch of BUF : component is "true";
signal ce_vec : std_logic_vector(0 downto 0);
begin
buf_comp : buf port map(i => ce, o => ce_vec(0));
q <= ce_vec;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_a2121d82da is
port (
sel : in std_logic_vector((1 - 1) downto 0);
d0 : in std_logic_vector((24 - 1) downto 0);
d1 : in std_logic_vector((24 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_a2121d82da;
architecture behavior of mux_a2121d82da is
signal sel_1_20: std_logic_vector((1 - 1) downto 0);
signal d0_1_24: std_logic_vector((24 - 1) downto 0);
signal d1_1_27: std_logic_vector((24 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((24 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
proc_switch_6_1: process (d0_1_24, d1_1_27, sel_1_20)
is
begin
case sel_1_20 is
when "0" =>
unregy_join_6_1 <= d0_1_24;
when others =>
unregy_join_6_1 <= d1_1_27;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlregister is
generic (d_width : integer := 5;
init_value : bit_vector := b"00");
port (d : in std_logic_vector (d_width-1 downto 0);
rst : in std_logic_vector(0 downto 0) := "0";
en : in std_logic_vector(0 downto 0) := "1";
ce : in std_logic;
clk : in std_logic;
q : out std_logic_vector (d_width-1 downto 0));
end xlregister;
architecture behavior of xlregister is
component synth_reg_w_init
generic (width : integer;
init_index : integer;
init_value : bit_vector;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
-- synopsys translate_off
signal real_d, real_q : real;
-- synopsys translate_on
signal internal_clr : std_logic;
signal internal_ce : std_logic;
begin
internal_clr <= rst(0) and ce;
internal_ce <= en(0) and ce;
synth_reg_inst : synth_reg_w_init
generic map (width => d_width,
init_index => 2,
init_value => init_value,
latency => 1)
port map (i => d,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => q);
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity counter_41314d726b is
port (
rst : in std_logic_vector((1 - 1) downto 0);
en : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end counter_41314d726b;
architecture behavior of counter_41314d726b is
signal rst_1_40: boolean;
signal en_1_45: boolean;
signal count_reg_20_23: unsigned((1 - 1) downto 0) := "0";
signal count_reg_20_23_rst: std_logic;
signal count_reg_20_23_en: std_logic;
signal bool_44_4: boolean;
signal rst_limit_join_44_1: boolean;
signal count_reg_join_44_1: unsigned((2 - 1) downto 0);
signal count_reg_join_44_1_en: std_logic;
signal count_reg_join_44_1_rst: std_logic;
begin
rst_1_40 <= ((rst) = "1");
en_1_45 <= ((en) = "1");
proc_count_reg_20_23: process (clk)
is
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (count_reg_20_23_rst = '1')) then
count_reg_20_23 <= "0";
elsif ((ce = '1') and (count_reg_20_23_en = '1')) then
count_reg_20_23 <= count_reg_20_23 + std_logic_vector_to_unsigned("1");
end if;
end if;
end process proc_count_reg_20_23;
bool_44_4 <= rst_1_40 or false;
proc_if_44_1: process (bool_44_4, count_reg_20_23, en_1_45)
is
begin
if bool_44_4 then
count_reg_join_44_1_rst <= '1';
elsif en_1_45 then
count_reg_join_44_1_rst <= '0';
else
count_reg_join_44_1_rst <= '0';
end if;
if en_1_45 then
count_reg_join_44_1_en <= '1';
else
count_reg_join_44_1_en <= '0';
end if;
if bool_44_4 then
rst_limit_join_44_1 <= false;
elsif en_1_45 then
rst_limit_join_44_1 <= false;
else
rst_limit_join_44_1 <= false;
end if;
end process proc_if_44_1;
count_reg_20_23_rst <= count_reg_join_44_1_rst;
count_reg_20_23_en <= count_reg_join_44_1_en;
op <= unsigned_to_std_logic_vector(count_reg_20_23);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xlusamp is
generic (
d_width : integer := 5;
d_bin_pt : integer := 2;
d_arith : integer := xlUnsigned;
q_width : integer := 5;
q_bin_pt : integer := 2;
q_arith : integer := xlUnsigned;
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
sampling_ratio : integer := 2;
latency : integer := 1;
copy_samples : integer := 0);
port (
d : in std_logic_vector (d_width-1 downto 0);
src_clk : in std_logic;
src_ce : in std_logic;
src_clr : in std_logic;
dest_clk : in std_logic;
dest_ce : in std_logic;
dest_clr : in std_logic;
en : in std_logic_vector(en_width-1 downto 0);
q : out std_logic_vector (q_width-1 downto 0)
);
end xlusamp;
architecture struct of xlusamp is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component FDSE
port (q : out std_ulogic;
d : in std_ulogic;
c : in std_ulogic;
s : in std_ulogic;
ce : in std_ulogic);
end component;
attribute syn_black_box of FDSE : component is true;
attribute fpga_dont_touch of FDSE : component is "true";
signal zero : std_logic_vector (d_width-1 downto 0);
signal mux_sel : std_logic;
signal sampled_d : std_logic_vector (d_width-1 downto 0);
signal internal_ce : std_logic;
begin
sel_gen : FDSE
port map (q => mux_sel,
d => src_ce,
c => src_clk,
s => src_clr,
ce => dest_ce);
internal_ce <= src_ce and en(0);
copy_samples_false : if (copy_samples = 0) generate
zero <= (others => '0');
gen_q_cp_smpls_0_and_lat_0: if (latency = 0) generate
cp_smpls_0_and_lat_0: process (mux_sel, d, zero)
begin
if (mux_sel = '1') then
q <= d;
else
q <= zero;
end if;
end process cp_smpls_0_and_lat_0;
end generate;
gen_q_cp_smpls_0_and_lat_gt_0: if (latency > 0) generate
sampled_d_reg: synth_reg
generic map (
width => d_width,
latency => latency
)
port map (
i => d,
ce => internal_ce,
clr => src_clr,
clk => src_clk,
o => sampled_d
);
gen_q_check_mux_sel: process (mux_sel, sampled_d, zero)
begin
if (mux_sel = '1') then
q <= sampled_d;
else
q <= zero;
end if;
end process gen_q_check_mux_sel;
end generate;
end generate;
copy_samples_true : if (copy_samples = 1) generate
gen_q_cp_smpls_1_and_lat_0: if (latency = 0) generate
q <= d;
end generate;
gen_q_cp_smpls_1_and_lat_gt_0: if (latency > 0) generate
q <= sampled_d;
sampled_d_reg2: synth_reg
generic map (
width => d_width,
latency => latency
)
port map (
i => d,
ce => internal_ce,
clr => src_clr,
clk => src_clk,
o => sampled_d
);
end generate;
end generate;
end architecture struct;
-------------------------------------------------------------------------------
-- Title : Look-up table sweeper
-- Project :
-------------------------------------------------------------------------------
-- File : lut_sweep.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tool for sweeping through look-up table addresses
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity lut_sweep is
generic (
g_bus_size : natural := 8;
g_first_address : natural := 0;
g_last_address : natural := 147;
g_sweep_mode : string := "sawtooth"
);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0));
end entity lut_sweep;
-------------------------------------------------------------------------------
architecture str of lut_sweep is
begin -- architecture str
counting : process(clk_i)
variable count : natural := 0;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count := 0;
elsif ce_i = '1' then
if count = g_last_address then
count := g_first_address;
else
count := count + 1;
end if; --count = last_address
address_o <= std_logic_vector(to_unsigned(count, g_bus_size));
end if; -- reset
end if; -- rising_edge
end process counting;
end architecture str;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Title : Fixed sin-cos DDS
-- Project :
-------------------------------------------------------------------------------
-- File : fixed_dds.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Fixed frequency phase and quadrature DDS for use in tuned DDCs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity fixed_dds is
generic (
g_number_of_points : natural := 148;
g_output_width : natural := 24;
g_dither : boolean := false;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram"
);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0)
);
end entity fixed_dds;
-------------------------------------------------------------------------------
architecture str of fixed_dds is
constant c_bus_size : natural := f_log2_size(g_number_of_points);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0);
component generic_simple_dpram is
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(c_bus_size-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_bus_size-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component generic_simple_dpram;
component lut_sweep is
generic (
g_bus_size : natural;
g_first_address : natural;
g_last_address : natural;
g_sweep_mode : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(c_bus_size-1 downto 0));
end component lut_sweep;
begin -- architecture str
cmp_sin_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_sin_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => sin_o
);
cmp_cos_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_cos_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => cos_o
);
cmp_sweep : lut_sweep
generic map (
g_bus_size => c_bus_size,
g_first_address => 0,
g_last_address => g_number_of_points-1,
g_sweep_mode => "sawtooth")
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
ce_i => ce_i,
address_o => cur_address);
end architecture str;
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_963ed6358a is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_963ed6358a;
architecture behavior of constant_963ed6358a is
begin
op <= "0";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_6293007044 is
port (
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_6293007044;
architecture behavior of constant_6293007044 is
begin
op <= "1";
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
-- synopsys translate_off
library unisim;
use unisim.vcomponents.all;
-- synopsys translate_on
entity xldsamp is
generic (
d_width: integer := 12;
d_bin_pt: integer := 0;
d_arith: integer := xlUnsigned;
q_width: integer := 12;
q_bin_pt: integer := 0;
q_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
ds_ratio: integer := 2;
phase: integer := 0;
latency: integer := 1
);
port (
d: in std_logic_vector(d_width - 1 downto 0);
src_clk: in std_logic;
src_ce: in std_logic;
src_clr: in std_logic;
dest_clk: in std_logic;
dest_ce: in std_logic;
dest_clr: in std_logic;
en: in std_logic_vector(en_width - 1 downto 0);
q: out std_logic_vector(q_width - 1 downto 0)
);
end xldsamp;
architecture struct of xldsamp is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component fdse
port (
q: out std_ulogic;
d: in std_ulogic;
c: in std_ulogic;
s: in std_ulogic;
ce: in std_ulogic
);
end component;
attribute syn_black_box of fdse: component is true;
attribute fpga_dont_touch of fdse: component is "true";
signal adjusted_dest_ce: std_logic;
signal adjusted_dest_ce_w_en: std_logic;
signal dest_ce_w_en: std_logic;
signal smpld_d: std_logic_vector(d_width-1 downto 0);
begin
adjusted_ce_needed: if ((latency = 0) or (phase /= (ds_ratio - 1))) generate
dest_ce_reg: fdse
port map (
q => adjusted_dest_ce,
d => dest_ce,
c => src_clk,
s => src_clr,
ce => src_ce
);
end generate;
latency_eq_0: if (latency = 0) generate
shutter_d_reg: synth_reg
generic map (
width => d_width,
latency => 1
)
port map (
i => d,
ce => adjusted_dest_ce,
clr => src_clr,
clk => src_clk,
o => smpld_d
);
shutter_mux: process (adjusted_dest_ce, d, smpld_d)
begin
if adjusted_dest_ce = '0' then
q <= smpld_d;
else
q <= d;
end if;
end process;
end generate;
latency_gt_0: if (latency > 0) generate
dbl_reg_test: if (phase /= (ds_ratio-1)) generate
smpl_d_reg: synth_reg
generic map (
width => d_width,
latency => 1
)
port map (
i => d,
ce => adjusted_dest_ce_w_en,
clr => src_clr,
clk => src_clk,
o => smpld_d
);
end generate;
sngl_reg_test: if (phase = (ds_ratio -1)) generate
smpld_d <= d;
end generate;
latency_pipe: synth_reg
generic map (
width => d_width,
latency => latency
)
port map (
i => smpld_d,
ce => dest_ce_w_en,
clr => src_clr,
clk => dest_clk,
o => q
);
end generate;
dest_ce_w_en <= dest_ce and en(0);
adjusted_dest_ce_w_en <= adjusted_dest_ce and en(0);
end architecture struct;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_a892e1bf40 is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_a892e1bf40;
architecture behavior of relational_a892e1bf40 is
signal a_1_31: unsigned((1 - 1) downto 0);
signal b_1_34: unsigned((1 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlpassthrough is
generic (
din_width : integer := 16;
dout_width : integer := 16
);
port (
din : in std_logic_vector (din_width-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0));
end xlpassthrough;
architecture passthrough_arch of xlpassthrough is
begin
dout <= din;
end passthrough_arch;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_b62f4240f0 is
port (
input_port : in std_logic_vector((24 - 1) downto 0);
output_port : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_b62f4240f0;
architecture behavior of reinterpret_b62f4240f0 is
signal input_port_1_40: signed((24 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port <= signed_to_std_logic_vector(input_port_1_40);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcordic_1700ad0af26476326977e0830172a2c4 is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_dout_tdata_phase:out std_logic_vector(23 downto 0);
m_axis_dout_tdata_real:out std_logic_vector(23 downto 0);
m_axis_dout_tuser_cartesian_tuser:out std_logic_vector(0 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_cartesian_tdata_imag:in std_logic_vector(24 downto 0);
s_axis_cartesian_tdata_real:in std_logic_vector(24 downto 0);
s_axis_cartesian_tready:out std_logic;
s_axis_cartesian_tuser_user:in std_logic_vector(0 downto 0);
s_axis_cartesian_tvalid:in std_logic
);
end xlcordic_1700ad0af26476326977e0830172a2c4;
architecture behavior of xlcordic_1700ad0af26476326977e0830172a2c4 is
component crdc_v5_0_951922a7ad5d425e
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_dout_tdata:out std_logic_vector(47 downto 0);
m_axis_dout_tuser:out std_logic_vector(0 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_cartesian_tdata:in std_logic_vector(63 downto 0);
s_axis_cartesian_tready:out std_logic;
s_axis_cartesian_tuser:in std_logic_vector(0 downto 0);
s_axis_cartesian_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal m_axis_dout_tuser_net: std_logic_vector(0 downto 0) := (others=>'0');
signal s_axis_cartesian_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
signal s_axis_cartesian_tuser_net: std_logic_vector(0 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_phase <= m_axis_dout_tdata_net(47 downto 24);
m_axis_dout_tdata_real <= m_axis_dout_tdata_net(23 downto 0);
m_axis_dout_tuser_cartesian_tuser <= m_axis_dout_tuser_net(0 downto 0);
s_axis_cartesian_tdata_net(56 downto 32) <= s_axis_cartesian_tdata_imag;
s_axis_cartesian_tdata_net(24 downto 0) <= s_axis_cartesian_tdata_real;
s_axis_cartesian_tuser_net(0 downto 0) <= s_axis_cartesian_tuser_user;
crdc_v5_0_951922a7ad5d425e_instance : crdc_v5_0_951922a7ad5d425e
port map(
aclk=>clk,
aclken=>ce,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tuser=>m_axis_dout_tuser_net,
m_axis_dout_tvalid=>m_axis_dout_tvalid,
s_axis_cartesian_tdata=>s_axis_cartesian_tdata_net,
s_axis_cartesian_tready=>s_axis_cartesian_tready,
s_axis_cartesian_tuser=>s_axis_cartesian_tuser_net,
s_axis_cartesian_tvalid=>s_axis_cartesian_tvalid
);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity convert_func_call is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end convert_func_call;
architecture behavior of convert_func_call is
begin
result <= convert_type(din, din_width, din_bin_pt, din_arith,
dout_width, dout_bin_pt, dout_arith,
quantization, overflow);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlconvert is
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
en_width : integer := 1;
en_bin_pt : integer := 0;
en_arith : integer := xlUnsigned;
bool_conversion : integer :=0;
latency : integer := 0;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
en : in std_logic_vector (en_width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
dout : out std_logic_vector (dout_width-1 downto 0));
end xlconvert;
architecture behavior of xlconvert is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component convert_func_call
generic (
din_width : integer := 16;
din_bin_pt : integer := 4;
din_arith : integer := xlUnsigned;
dout_width : integer := 8;
dout_bin_pt : integer := 2;
dout_arith : integer := xlUnsigned;
quantization : integer := xlTruncate;
overflow : integer := xlWrap);
port (
din : in std_logic_vector (din_width-1 downto 0);
result : out std_logic_vector (dout_width-1 downto 0));
end component;
-- synopsys translate_off
-- synopsys translate_on
signal result : std_logic_vector(dout_width-1 downto 0);
signal internal_ce : std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
bool_conversion_generate : if (bool_conversion = 1)
generate
result <= din;
end generate;
std_conversion_generate : if (bool_conversion = 0)
generate
convert : convert_func_call
generic map (
din_width => din_width,
din_bin_pt => din_bin_pt,
din_arith => din_arith,
dout_width => dout_width,
dout_bin_pt => dout_bin_pt,
dout_arith => dout_arith,
quantization => quantization,
overflow => overflow)
port map (
din => din,
result => result);
end generate;
latency_test : if (latency > 0) generate
reg : synth_reg
generic map (
width => dout_width,
latency => latency
)
port map (
i => result,
ce => internal_ce,
clr => clr,
clk => clk,
o => dout
);
end generate;
latency0 : if (latency = 0)
generate
dout <= result;
end generate latency0;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_31a4235b32 is
port (
input_port : in std_logic_vector((25 - 1) downto 0);
output_port : out std_logic_vector((25 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_31a4235b32;
architecture behavior of reinterpret_31a4235b32 is
signal input_port_1_40: signed((25 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port <= signed_to_std_logic_vector(input_port_1_40);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_fa01b5fd95 is
port (
input_port : in std_logic_vector((58 - 1) downto 0);
output_port : out std_logic_vector((58 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_fa01b5fd95;
architecture behavior of reinterpret_fa01b5fd95 is
signal input_port_1_40: signed((58 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port <= signed_to_std_logic_vector(input_port_1_40);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_cda50df78a is
port (
op : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_cda50df78a;
architecture behavior of constant_cda50df78a is
begin
op <= "00";
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xldelay is
generic(width : integer := -1;
latency : integer := -1;
reg_retiming : integer := 0;
reset : integer := 0);
port(d : in std_logic_vector (width-1 downto 0);
ce : in std_logic;
clk : in std_logic;
en : in std_logic;
rst : in std_logic;
q : out std_logic_vector (width-1 downto 0));
end xldelay;
architecture behavior of xldelay is
component synth_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
component synth_reg_reg
generic (width : integer;
latency : integer);
port (i : in std_logic_vector(width-1 downto 0);
ce : in std_logic;
clr : in std_logic;
clk : in std_logic;
o : out std_logic_vector(width-1 downto 0));
end component;
signal internal_ce : std_logic;
begin
internal_ce <= ce and en;
srl_delay: if ((reg_retiming = 0) and (reset = 0)) or (latency < 1) generate
synth_reg_srl_inst : synth_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => '0',
clk => clk,
o => q);
end generate srl_delay;
reg_delay: if ((reg_retiming = 1) or (reset = 1)) and (latency >= 1) generate
synth_reg_reg_inst : synth_reg_reg
generic map (
width => width,
latency => latency)
port map (
i => d,
ce => internal_ce,
clr => rst,
clk => clk,
o => q);
end generate reg_delay;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_d29d27b7b3 is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((2 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_d29d27b7b3;
architecture behavior of relational_d29d27b7b3 is
signal a_1_31: unsigned((1 - 1) downto 0);
signal b_1_34: unsigned((2 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal cast_12_12: unsigned((2 - 1) downto 0);
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
cast_12_12 <= u2u_cast(a_1_31, 0, 2, 0);
result_12_3_rel <= cast_12_12 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266 is
port(
ce:in std_logic;
ce_1120:in std_logic;
ce_logic_1:in std_logic;
clk:in std_logic;
clk_1120:in std_logic;
clk_logic_1:in std_logic;
event_tlast_missing:out std_logic;
event_tlast_unexpected:out std_logic;
m_axis_data_tdata_data:out std_logic_vector(57 downto 0);
m_axis_data_tlast:out std_logic;
m_axis_data_tuser_chan_out:out std_logic_vector(0 downto 0);
m_axis_data_tuser_chan_sync:out std_logic_vector(0 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata_data:in std_logic_vector(23 downto 0);
s_axis_data_tlast:in std_logic;
s_axis_data_tready:out std_logic
);
end xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266;
architecture behavior of xlcic_compiler_691a78f3d9f6f4d23a2519dbc0c21266 is
component cc_cmplr_v3_0_2717b25e8a23e5e2
port(
aclk:in std_logic;
aclken:in std_logic;
event_tlast_missing:out std_logic;
event_tlast_unexpected:out std_logic;
m_axis_data_tdata:out std_logic_vector(63 downto 0);
m_axis_data_tlast:out std_logic;
m_axis_data_tuser:out std_logic_vector(15 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(23 downto 0);
s_axis_data_tlast:in std_logic;
s_axis_data_tready:out std_logic;
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
signal m_axis_data_tdata_data_ps_net: std_logic_vector(57 downto 0) := (others=>'0');
signal m_axis_data_tdata_data_ps_net_captured: std_logic_vector(57 downto 0) := (others=>'0');
signal m_axis_data_tdata_data_ps_net_or_captured_net: std_logic_vector(57 downto 0) := (others=>'0');
signal m_axis_data_tlast_ps_net: std_logic := '0';
signal m_axis_data_tlast_ps_net_captured: std_logic := '0';
signal m_axis_data_tlast_ps_net_or_captured_net: std_logic := '0';
signal m_axis_data_tuser_net: std_logic_vector(15 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_sync_ps_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_sync_ps_net_captured: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_sync_ps_net_or_captured_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_out_ps_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_out_ps_net_captured: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_out_ps_net_or_captured_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(23 downto 0) := (others=>'0');
begin
m_axis_data_tdata_data_ps_net <= m_axis_data_tdata_net(57 downto 0);
m_axis_data_tuser_chan_sync_ps_net <= m_axis_data_tuser_net(8 downto 8);
m_axis_data_tuser_chan_out_ps_net <= m_axis_data_tuser_net(0 downto 0);
s_axis_data_tdata_net(23 downto 0) <= s_axis_data_tdata_data;
m_axis_data_tdata_data_ps_net_or_captured_net <= m_axis_data_tdata_data_ps_net or m_axis_data_tdata_data_ps_net_captured;
m_axis_data_tdata_data_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 58,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_data_ps_net_or_captured_net,
ce => ce_1120,
clr => '0',
clk => clk_1120,
o => m_axis_data_tdata_data
);
m_axis_data_tdata_data_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 58,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_data_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1120,
o => m_axis_data_tdata_data_ps_net_captured
);
m_axis_data_tlast_ps_net_or_captured_net <= m_axis_data_tlast_ps_net or m_axis_data_tlast_ps_net_captured;
m_axis_data_tlast_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tlast_ps_net_or_captured_net,
ce => ce_1120,
clr => '0',
clk => clk_1120,
o(0) => m_axis_data_tlast
);
m_axis_data_tlast_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tlast_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1120,
o(0) => m_axis_data_tlast_ps_net_captured
);
m_axis_data_tuser_chan_sync_ps_net_or_captured_net <= m_axis_data_tuser_chan_sync_ps_net or m_axis_data_tuser_chan_sync_ps_net_captured;
m_axis_data_tuser_chan_sync_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_sync_ps_net_or_captured_net,
ce => ce_1120,
clr => '0',
clk => clk_1120,
o => m_axis_data_tuser_chan_sync
);
m_axis_data_tuser_chan_sync_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_sync_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1120,
o => m_axis_data_tuser_chan_sync_ps_net_captured
);
m_axis_data_tuser_chan_out_ps_net_or_captured_net <= m_axis_data_tuser_chan_out_ps_net or m_axis_data_tuser_chan_out_ps_net_captured;
m_axis_data_tuser_chan_out_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_out_ps_net_or_captured_net,
ce => ce_1120,
clr => '0',
clk => clk_1120,
o => m_axis_data_tuser_chan_out
);
m_axis_data_tuser_chan_out_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_out_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1120,
o => m_axis_data_tuser_chan_out_ps_net_captured
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_1120,
clr => '0',
clk => clk_1120,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1120,
o(0) => m_axis_data_tvalid_ps_net_captured
);
cc_cmplr_v3_0_2717b25e8a23e5e2_instance : cc_cmplr_v3_0_2717b25e8a23e5e2
port map(
aclk=>clk,
aclken=>ce,
event_tlast_missing=>event_tlast_missing,
event_tlast_unexpected=>event_tlast_unexpected,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tlast=>m_axis_data_tlast_ps_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tlast=>s_axis_data_tlast,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tvalid=>ce_logic_1
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_9934b94a22 is
port (
input_port : in std_logic_vector((26 - 1) downto 0);
output_port : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_9934b94a22;
architecture behavior of reinterpret_9934b94a22 is
signal input_port_1_40: unsigned((26 - 1) downto 0);
signal output_port_5_5_force: signed((26 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlslice is
generic (
new_msb : integer := 9;
new_lsb : integer := 1;
x_width : integer := 16;
y_width : integer := 8);
port (
x : in std_logic_vector (x_width-1 downto 0);
y : out std_logic_vector (y_width-1 downto 0));
end xlslice;
architecture behavior of xlslice is
begin
y <= x(new_msb downto new_lsb);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xlmult is
generic (
core_name0: string := "";
a_width: integer := 4;
a_bin_pt: integer := 2;
a_arith: integer := xlSigned;
b_width: integer := 4;
b_bin_pt: integer := 1;
b_arith: integer := xlSigned;
p_width: integer := 8;
p_bin_pt: integer := 2;
p_arith: integer := xlSigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
extra_registers: integer := 0;
c_a_width: integer := 7;
c_b_width: integer := 7;
c_type: integer := 0;
c_a_type: integer := 0;
c_b_type: integer := 0;
c_pipelined: integer := 1;
c_baat: integer := 4;
multsign: integer := xlSigned;
c_output_width: integer := 16
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
core_ce: in std_logic := '0';
core_clr: in std_logic := '0';
core_clk: in std_logic := '0';
rst: in std_logic_vector(rst_width - 1 downto 0);
en: in std_logic_vector(en_width - 1 downto 0);
p: out std_logic_vector(p_width - 1 downto 0)
);
end xlmult;
architecture behavior of xlmult is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
component mult_11_2_eb6becd4c4c6b065
port (
b: in std_logic_vector(c_b_width - 1 downto 0);
p: out std_logic_vector(c_output_width - 1 downto 0);
clk: in std_logic;
ce: in std_logic;
sclr: in std_logic;
a: in std_logic_vector(c_a_width - 1 downto 0)
);
end component;
attribute syn_black_box of mult_11_2_eb6becd4c4c6b065:
component is true;
attribute fpga_dont_touch of mult_11_2_eb6becd4c4c6b065:
component is "true";
attribute box_type of mult_11_2_eb6becd4c4c6b065:
component is "black_box";
signal tmp_a: std_logic_vector(c_a_width - 1 downto 0);
signal conv_a: std_logic_vector(c_a_width - 1 downto 0);
signal tmp_b: std_logic_vector(c_b_width - 1 downto 0);
signal conv_b: std_logic_vector(c_b_width - 1 downto 0);
signal tmp_p: std_logic_vector(c_output_width - 1 downto 0);
signal conv_p: std_logic_vector(p_width - 1 downto 0);
-- synopsys translate_off
signal real_a, real_b, real_p: real;
-- synopsys translate_on
signal rfd: std_logic;
signal rdy: std_logic;
signal nd: std_logic;
signal internal_ce: std_logic;
signal internal_clr: std_logic;
signal internal_core_ce: std_logic;
begin
-- synopsys translate_off
-- synopsys translate_on
internal_ce <= ce and en(0);
internal_core_ce <= core_ce and en(0);
internal_clr <= (clr or rst(0)) and ce;
nd <= internal_ce;
input_process: process (a,b)
begin
tmp_a <= zero_ext(a, c_a_width);
tmp_b <= zero_ext(b, c_b_width);
end process;
output_process: process (tmp_p)
begin
conv_p <= convert_type(tmp_p, c_output_width, a_bin_pt+b_bin_pt, multsign,
p_width, p_bin_pt, p_arith, quantization, overflow);
end process;
comp0: if ((core_name0 = "mult_11_2_eb6becd4c4c6b065")) generate
core_instance0: mult_11_2_eb6becd4c4c6b065
port map (
a => tmp_a,
clk => clk,
ce => internal_ce,
sclr => internal_clr,
p => tmp_p,
b => tmp_b
);
end generate;
latency_gt_0: if (extra_registers > 0) generate
reg: synth_reg
generic map (
width => p_width,
latency => extra_registers
)
port map (
i => conv_p,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o => p
);
end generate;
latency_eq_0: if (extra_registers = 0) generate
p <= conv_p;
end generate;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcomplex_multiplier_9420c9297365b1438cc1e8469b8205e1 is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_dout_tdata_imag:out std_logic_vector(23 downto 0);
m_axis_dout_tdata_real:out std_logic_vector(23 downto 0);
m_axis_dout_tuser:out std_logic_vector(0 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_a_tdata_imag:in std_logic_vector(23 downto 0);
s_axis_a_tdata_real:in std_logic_vector(23 downto 0);
s_axis_a_tvalid:in std_logic;
s_axis_b_tdata_imag:in std_logic_vector(23 downto 0);
s_axis_b_tdata_real:in std_logic_vector(23 downto 0);
s_axis_b_tuser:in std_logic_vector(0 downto 0);
s_axis_b_tvalid:in std_logic
);
end xlcomplex_multiplier_9420c9297365b1438cc1e8469b8205e1;
architecture behavior of xlcomplex_multiplier_9420c9297365b1438cc1e8469b8205e1 is
component cmpy_v5_0_fc1d91881e8e8ae6
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_dout_tdata:out std_logic_vector(47 downto 0);
m_axis_dout_tuser:out std_logic_vector(0 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_a_tdata:in std_logic_vector(47 downto 0);
s_axis_a_tvalid:in std_logic;
s_axis_b_tdata:in std_logic_vector(47 downto 0);
s_axis_b_tuser:in std_logic_vector(0 downto 0);
s_axis_b_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_a_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_b_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_imag <= m_axis_dout_tdata_net(47 downto 24);
m_axis_dout_tdata_real <= m_axis_dout_tdata_net(23 downto 0);
s_axis_a_tdata_net(47 downto 24) <= s_axis_a_tdata_imag;
s_axis_a_tdata_net(23 downto 0) <= s_axis_a_tdata_real;
s_axis_b_tdata_net(47 downto 24) <= s_axis_b_tdata_imag;
s_axis_b_tdata_net(23 downto 0) <= s_axis_b_tdata_real;
cmpy_v5_0_fc1d91881e8e8ae6_instance : cmpy_v5_0_fc1d91881e8e8ae6
port map(
aclk=>clk,
aclken=>ce,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tuser=>m_axis_dout_tuser,
m_axis_dout_tvalid=>m_axis_dout_tvalid,
s_axis_a_tdata=>s_axis_a_tdata_net,
s_axis_a_tvalid=>s_axis_a_tvalid,
s_axis_b_tdata=>s_axis_b_tdata_net,
s_axis_b_tuser=>s_axis_b_tuser,
s_axis_b_tvalid=>s_axis_b_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity delay_961b43f67a is
port (
d : in std_logic_vector((24 - 1) downto 0);
q : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end delay_961b43f67a;
architecture behavior of delay_961b43f67a is
signal d_1_22: std_logic_vector((24 - 1) downto 0);
begin
d_1_22 <= d;
q <= d_1_22;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_f394f3309c is
port (
op : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_f394f3309c;
architecture behavior of constant_f394f3309c is
begin
op <= "000000000000000000000000";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_c88e29aa6b is
port (
input_port : in std_logic_vector((61 - 1) downto 0);
output_port : out std_logic_vector((61 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_c88e29aa6b;
architecture behavior of reinterpret_c88e29aa6b is
signal input_port_1_40: signed((61 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port <= signed_to_std_logic_vector(input_port_1_40);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_3a9a3daeb9 is
port (
op : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_3a9a3daeb9;
architecture behavior of constant_3a9a3daeb9 is
begin
op <= "11";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_a7e2bb9e12 is
port (
op : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_a7e2bb9e12;
architecture behavior of constant_a7e2bb9e12 is
begin
op <= "01";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity constant_e8ddc079e9 is
port (
op : out std_logic_vector((2 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end constant_e8ddc079e9;
architecture behavior of constant_e8ddc079e9 is
begin
op <= "10";
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_367321bc0c is
port (
a : in std_logic_vector((2 - 1) downto 0);
b : in std_logic_vector((2 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_367321bc0c;
architecture behavior of relational_367321bc0c is
signal a_1_31: unsigned((2 - 1) downto 0);
signal b_1_34: unsigned((2 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_83ca2c6a3c is
port (
a : in std_logic_vector((2 - 1) downto 0);
b : in std_logic_vector((2 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_83ca2c6a3c;
architecture behavior of relational_83ca2c6a3c is
signal a_1_31: unsigned((2 - 1) downto 0);
signal b_1_34: unsigned((2 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (4 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
false,
false,
false,
false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_12_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_unsigned(a);
b_1_34 <= std_logic_vector_to_unsigned(b);
op_mem_32_22_back <= op_mem_32_22(3);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
for i in 3 downto 1 loop
op_mem_32_22(i) <= op_mem_32_22(i-1);
end loop;
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_12_3_rel <= a_1_31 = b_1_34;
op_mem_32_22_front_din <= result_12_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_9c8746ef58b9fecaf8fa2bea81370554 is
port(
ce:in std_logic;
ce_1400000:in std_logic;
ce_2800000:in std_logic;
ce_logic_1400000:in std_logic;
clk:in std_logic;
clk_1400000:in std_logic;
clk_2800000:in std_logic;
clk_logic_1400000:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(24 downto 0);
m_axis_data_tuser_chanid:out std_logic_vector(1 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(23 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser_chanid:in std_logic_vector(1 downto 0);
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_9c8746ef58b9fecaf8fa2bea81370554;
architecture behavior of xlfir_compiler_9c8746ef58b9fecaf8fa2bea81370554 is
component fr_cmplr_v6_3_54d148b4178eb862
port(
aclk:in std_logic;
aclken:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(31 downto 0);
m_axis_data_tuser:out std_logic_vector(1 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(23 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser:in std_logic_vector(1 downto 0);
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
signal m_axis_data_tdata_ps_net: std_logic_vector(24 downto 0) := (others=>'0');
signal m_axis_data_tuser_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tuser_chanid_ps_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(23 downto 0) := (others=>'0');
signal s_axis_data_tuser_net: std_logic_vector(1 downto 0) := (others=>'0');
begin
m_axis_data_tdata_ps_net <= m_axis_data_tdata_net(24 downto 0);
m_axis_data_tuser_chanid_ps_net <= m_axis_data_tuser_net(1 downto 0);
s_axis_data_tdata_net(23 downto 0) <= s_axis_data_tdata;
s_axis_data_tuser_net(1 downto 0) <= s_axis_data_tuser_chanid;
m_axis_data_tdata_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 25,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_ps_net,
ce => ce_2800000,
clr => '0',
clk => clk_2800000,
o => m_axis_data_tdata
);
m_axis_data_tuser_chanid_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 2,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chanid_ps_net,
ce => ce_2800000,
clr => '0',
clk => clk_2800000,
o => m_axis_data_tuser_chanid
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_2800000,
clr => '0',
clk => clk_2800000,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_2800000,
o(0) => m_axis_data_tvalid_ps_net_captured
);
fr_cmplr_v6_3_54d148b4178eb862_instance : fr_cmplr_v6_3_54d148b4178eb862
port map(
aclk=>clk,
aclken=>ce,
event_s_data_chanid_incorrect=>event_s_data_chanid_incorrect,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tuser=>s_axis_data_tuser_net,
s_axis_data_tvalid=>ce_logic_1400000
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlcic_compiler_1c97a249b004729f66738a648c4f9593 is
port(
ce:in std_logic;
ce_1400000:in std_logic;
ce_560:in std_logic;
ce_logic_560:in std_logic;
clk:in std_logic;
clk_1400000:in std_logic;
clk_560:in std_logic;
clk_logic_560:in std_logic;
event_tlast_missing:out std_logic;
event_tlast_unexpected:out std_logic;
m_axis_data_tdata_data:out std_logic_vector(60 downto 0);
m_axis_data_tlast:out std_logic;
m_axis_data_tuser_chan_out:out std_logic_vector(1 downto 0);
m_axis_data_tuser_chan_sync:out std_logic_vector(0 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata_data:in std_logic_vector(23 downto 0);
s_axis_data_tlast:in std_logic;
s_axis_data_tready:out std_logic
);
end xlcic_compiler_1c97a249b004729f66738a648c4f9593;
architecture behavior of xlcic_compiler_1c97a249b004729f66738a648c4f9593 is
component cc_cmplr_v3_0_e85aeee534196d83
port(
aclk:in std_logic;
aclken:in std_logic;
event_tlast_missing:out std_logic;
event_tlast_unexpected:out std_logic;
m_axis_data_tdata:out std_logic_vector(63 downto 0);
m_axis_data_tlast:out std_logic;
m_axis_data_tuser:out std_logic_vector(15 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(23 downto 0);
s_axis_data_tlast:in std_logic;
s_axis_data_tready:out std_logic;
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
signal m_axis_data_tdata_data_ps_net: std_logic_vector(60 downto 0) := (others=>'0');
signal m_axis_data_tdata_data_ps_net_captured: std_logic_vector(60 downto 0) := (others=>'0');
signal m_axis_data_tdata_data_ps_net_or_captured_net: std_logic_vector(60 downto 0) := (others=>'0');
signal m_axis_data_tlast_ps_net: std_logic := '0';
signal m_axis_data_tlast_ps_net_captured: std_logic := '0';
signal m_axis_data_tlast_ps_net_or_captured_net: std_logic := '0';
signal m_axis_data_tuser_net: std_logic_vector(15 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_sync_ps_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_sync_ps_net_captured: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_sync_ps_net_or_captured_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_out_ps_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_out_ps_net_captured: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tuser_chan_out_ps_net_or_captured_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(23 downto 0) := (others=>'0');
begin
m_axis_data_tdata_data_ps_net <= m_axis_data_tdata_net(60 downto 0);
m_axis_data_tuser_chan_sync_ps_net <= m_axis_data_tuser_net(8 downto 8);
m_axis_data_tuser_chan_out_ps_net <= m_axis_data_tuser_net(1 downto 0);
s_axis_data_tdata_net(23 downto 0) <= s_axis_data_tdata_data;
m_axis_data_tdata_data_ps_net_or_captured_net <= m_axis_data_tdata_data_ps_net or m_axis_data_tdata_data_ps_net_captured;
m_axis_data_tdata_data_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 61,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_data_ps_net_or_captured_net,
ce => ce_1400000,
clr => '0',
clk => clk_1400000,
o => m_axis_data_tdata_data
);
m_axis_data_tdata_data_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 61,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_data_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1400000,
o => m_axis_data_tdata_data_ps_net_captured
);
m_axis_data_tlast_ps_net_or_captured_net <= m_axis_data_tlast_ps_net or m_axis_data_tlast_ps_net_captured;
m_axis_data_tlast_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tlast_ps_net_or_captured_net,
ce => ce_1400000,
clr => '0',
clk => clk_1400000,
o(0) => m_axis_data_tlast
);
m_axis_data_tlast_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tlast_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1400000,
o(0) => m_axis_data_tlast_ps_net_captured
);
m_axis_data_tuser_chan_sync_ps_net_or_captured_net <= m_axis_data_tuser_chan_sync_ps_net or m_axis_data_tuser_chan_sync_ps_net_captured;
m_axis_data_tuser_chan_sync_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_sync_ps_net_or_captured_net,
ce => ce_1400000,
clr => '0',
clk => clk_1400000,
o => m_axis_data_tuser_chan_sync
);
m_axis_data_tuser_chan_sync_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_sync_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1400000,
o => m_axis_data_tuser_chan_sync_ps_net_captured
);
m_axis_data_tuser_chan_out_ps_net_or_captured_net <= m_axis_data_tuser_chan_out_ps_net or m_axis_data_tuser_chan_out_ps_net_captured;
m_axis_data_tuser_chan_out_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 2,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_out_ps_net_or_captured_net,
ce => ce_1400000,
clr => '0',
clk => clk_1400000,
o => m_axis_data_tuser_chan_out
);
m_axis_data_tuser_chan_out_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 2,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chan_out_ps_net,
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1400000,
o => m_axis_data_tuser_chan_out_ps_net_captured
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_1400000,
clr => '0',
clk => clk_1400000,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_1400000,
o(0) => m_axis_data_tvalid_ps_net_captured
);
cc_cmplr_v3_0_e85aeee534196d83_instance : cc_cmplr_v3_0_e85aeee534196d83
port map(
aclk=>clk,
aclken=>ce,
event_tlast_missing=>event_tlast_missing,
event_tlast_unexpected=>event_tlast_unexpected,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tlast=>m_axis_data_tlast_ps_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tlast=>s_axis_data_tlast,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tvalid=>ce_logic_560
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_ef89cacae87a636bad21e5ee1476453a is
port(
ce:in std_logic;
ce_2800000:in std_logic;
ce_5600000:in std_logic;
ce_logic_2800000:in std_logic;
clk:in std_logic;
clk_2800000:in std_logic;
clk_5600000:in std_logic;
clk_logic_2800000:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(24 downto 0);
m_axis_data_tuser_chanid:out std_logic_vector(1 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(23 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser_chanid:in std_logic_vector(1 downto 0);
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_ef89cacae87a636bad21e5ee1476453a;
architecture behavior of xlfir_compiler_ef89cacae87a636bad21e5ee1476453a is
component fr_cmplr_v6_3_05afd5373121e2a3
port(
aclk:in std_logic;
aclken:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(31 downto 0);
m_axis_data_tuser:out std_logic_vector(1 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(23 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser:in std_logic_vector(1 downto 0);
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
signal m_axis_data_tdata_ps_net: std_logic_vector(24 downto 0) := (others=>'0');
signal m_axis_data_tuser_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tuser_chanid_ps_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(23 downto 0) := (others=>'0');
signal s_axis_data_tuser_net: std_logic_vector(1 downto 0) := (others=>'0');
begin
m_axis_data_tdata_ps_net <= m_axis_data_tdata_net(24 downto 0);
m_axis_data_tuser_chanid_ps_net <= m_axis_data_tuser_net(1 downto 0);
s_axis_data_tdata_net(23 downto 0) <= s_axis_data_tdata;
s_axis_data_tuser_net(1 downto 0) <= s_axis_data_tuser_chanid;
m_axis_data_tdata_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 25,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_ps_net,
ce => ce_5600000,
clr => '0',
clk => clk_5600000,
o => m_axis_data_tdata
);
m_axis_data_tuser_chanid_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 2,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chanid_ps_net,
ce => ce_5600000,
clr => '0',
clk => clk_5600000,
o => m_axis_data_tuser_chanid
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_5600000,
clr => '0',
clk => clk_5600000,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_5600000,
o(0) => m_axis_data_tvalid_ps_net_captured
);
fr_cmplr_v6_3_05afd5373121e2a3_instance : fr_cmplr_v6_3_05afd5373121e2a3
port map(
aclk=>clk,
aclken=>ce,
event_s_data_chanid_incorrect=>event_s_data_chanid_incorrect,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tuser=>s_axis_data_tuser_net,
s_axis_data_tvalid=>ce_logic_2800000
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_516bd78992d05073446d2f0e193ec7f1 is
port(
ce:in std_logic;
ce_35:in std_logic;
ce_logic_1:in std_logic;
clk:in std_logic;
clk_35:in std_logic;
clk_logic_1:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata_path0:out std_logic_vector(24 downto 0);
m_axis_data_tdata_path1:out std_logic_vector(24 downto 0);
m_axis_data_tuser_chanid:out std_logic_vector(0 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata_path0:in std_logic_vector(23 downto 0);
s_axis_data_tdata_path1:in std_logic_vector(23 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser_chanid:in std_logic_vector(0 downto 0);
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_516bd78992d05073446d2f0e193ec7f1;
architecture behavior of xlfir_compiler_516bd78992d05073446d2f0e193ec7f1 is
component fr_cmplr_v6_3_a7495039d232075b
port(
aclk:in std_logic;
aclken:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(63 downto 0);
m_axis_data_tuser:out std_logic_vector(0 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(47 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser:in std_logic_vector(0 downto 0);
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
signal m_axis_data_tdata_path1_ps_net: std_logic_vector(24 downto 0) := (others=>'0');
signal m_axis_data_tdata_path0_ps_net: std_logic_vector(24 downto 0) := (others=>'0');
signal m_axis_data_tuser_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chanid_ps_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_data_tuser_net: std_logic_vector(0 downto 0) := (others=>'0');
begin
m_axis_data_tdata_path1_ps_net <= m_axis_data_tdata_net(56 downto 32);
m_axis_data_tdata_path0_ps_net <= m_axis_data_tdata_net(24 downto 0);
m_axis_data_tuser_chanid_ps_net <= m_axis_data_tuser_net(0 downto 0);
s_axis_data_tdata_net(47 downto 24) <= s_axis_data_tdata_path1;
s_axis_data_tdata_net(23 downto 0) <= s_axis_data_tdata_path0;
s_axis_data_tuser_net(0 downto 0) <= s_axis_data_tuser_chanid;
m_axis_data_tdata_path1_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 25,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_path1_ps_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o => m_axis_data_tdata_path1
);
m_axis_data_tdata_path0_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 25,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_path0_ps_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o => m_axis_data_tdata_path0
);
m_axis_data_tuser_chanid_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chanid_ps_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o => m_axis_data_tuser_chanid
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_35,
o(0) => m_axis_data_tvalid_ps_net_captured
);
fr_cmplr_v6_3_a7495039d232075b_instance : fr_cmplr_v6_3_a7495039d232075b
port map(
aclk=>clk,
aclken=>ce,
event_s_data_chanid_incorrect=>event_s_data_chanid_incorrect,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tuser=>s_axis_data_tuser_net,
s_axis_data_tvalid=>ce_logic_1
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_dadbc7b58cb62c04fef420f4c58ee0d3 is
port(
ce:in std_logic;
ce_35:in std_logic;
ce_logic_1:in std_logic;
clk:in std_logic;
clk_35:in std_logic;
clk_logic_1:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata_path0:out std_logic_vector(24 downto 0);
m_axis_data_tdata_path1:out std_logic_vector(24 downto 0);
m_axis_data_tuser_chanid:out std_logic_vector(0 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata_path0:in std_logic_vector(23 downto 0);
s_axis_data_tdata_path1:in std_logic_vector(23 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser_chanid:in std_logic_vector(0 downto 0);
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_dadbc7b58cb62c04fef420f4c58ee0d3;
architecture behavior of xlfir_compiler_dadbc7b58cb62c04fef420f4c58ee0d3 is
component fr_cmplr_v6_3_eb3f5e21c238e176
port(
aclk:in std_logic;
aclken:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(63 downto 0);
m_axis_data_tuser:out std_logic_vector(0 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(47 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser:in std_logic_vector(0 downto 0);
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(63 downto 0) := (others=>'0');
signal m_axis_data_tdata_path1_ps_net: std_logic_vector(24 downto 0) := (others=>'0');
signal m_axis_data_tdata_path0_ps_net: std_logic_vector(24 downto 0) := (others=>'0');
signal m_axis_data_tuser_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tuser_chanid_ps_net: std_logic_vector(0 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(47 downto 0) := (others=>'0');
signal s_axis_data_tuser_net: std_logic_vector(0 downto 0) := (others=>'0');
begin
m_axis_data_tdata_path1_ps_net <= m_axis_data_tdata_net(56 downto 32);
m_axis_data_tdata_path0_ps_net <= m_axis_data_tdata_net(24 downto 0);
m_axis_data_tuser_chanid_ps_net <= m_axis_data_tuser_net(0 downto 0);
s_axis_data_tdata_net(47 downto 24) <= s_axis_data_tdata_path1;
s_axis_data_tdata_net(23 downto 0) <= s_axis_data_tdata_path0;
s_axis_data_tuser_net(0 downto 0) <= s_axis_data_tuser_chanid;
m_axis_data_tdata_path1_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 25,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_path1_ps_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o => m_axis_data_tdata_path1
);
m_axis_data_tdata_path0_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 25,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_path0_ps_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o => m_axis_data_tdata_path0
);
m_axis_data_tuser_chanid_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chanid_ps_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o => m_axis_data_tuser_chanid
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_35,
clr => '0',
clk => clk_35,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_35,
o(0) => m_axis_data_tvalid_ps_net_captured
);
fr_cmplr_v6_3_eb3f5e21c238e176_instance : fr_cmplr_v6_3_eb3f5e21c238e176
port map(
aclk=>clk,
aclken=>ce,
event_s_data_chanid_incorrect=>event_s_data_chanid_incorrect,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tuser=>s_axis_data_tuser_net,
s_axis_data_tvalid=>ce_logic_1
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_f062741975 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((24 - 1) downto 0);
d1 : in std_logic_vector((24 - 1) downto 0);
d2 : in std_logic_vector((24 - 1) downto 0);
d3 : in std_logic_vector((24 - 1) downto 0);
y : out std_logic_vector((24 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_f062741975;
architecture behavior of mux_f062741975 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((24 - 1) downto 0);
signal d1_1_27: std_logic_vector((24 - 1) downto 0);
signal d2_1_30: std_logic_vector((24 - 1) downto 0);
signal d3_1_33: std_logic_vector((24 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((24 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use work.conv_pkg.all;
entity xlcounter_free is
generic (
core_name0: string := "";
op_width: integer := 5;
op_arith: integer := xlSigned
);
port (
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
op: out std_logic_vector(op_width - 1 downto 0);
up: in std_logic_vector(0 downto 0) := (others => '0');
load: in std_logic_vector(0 downto 0) := (others => '0');
din: in std_logic_vector(op_width - 1 downto 0) := (others => '0');
en: in std_logic_vector(0 downto 0);
rst: in std_logic_vector(0 downto 0)
);
end xlcounter_free ;
architecture behavior of xlcounter_free is
component cntr_11_0_3166d4cc5b09c744
port (
clk: in std_logic;
ce: in std_logic;
SINIT: in std_logic;
q: out std_logic_vector(op_width - 1 downto 0)
);
end component;
attribute syn_black_box of cntr_11_0_3166d4cc5b09c744:
component is true;
attribute fpga_dont_touch of cntr_11_0_3166d4cc5b09c744:
component is "true";
attribute box_type of cntr_11_0_3166d4cc5b09c744:
component is "black_box";
-- synopsys translate_off
constant zeroVec: std_logic_vector(op_width - 1 downto 0) := (others => '0');
constant oneVec: std_logic_vector(op_width - 1 downto 0) := (others => '1');
constant zeroStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(zeroVec);
constant oneStr: string(1 to op_width) :=
std_logic_vector_to_bin_string(oneVec);
-- synopsys translate_on
signal core_sinit: std_logic;
signal core_ce: std_logic;
signal op_net: std_logic_vector(op_width - 1 downto 0);
begin
core_ce <= ce and en(0);
core_sinit <= (clr or rst(0)) and ce;
op <= op_net;
comp0: if ((core_name0 = "cntr_11_0_3166d4cc5b09c744")) generate
core_instance0: cntr_11_0_3166d4cc5b09c744
port map (
clk => clk,
ce => core_ce,
SINIT => core_sinit,
q => op_net
);
end generate;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity mux_187c900130 is
port (
sel : in std_logic_vector((2 - 1) downto 0);
d0 : in std_logic_vector((26 - 1) downto 0);
d1 : in std_logic_vector((26 - 1) downto 0);
d2 : in std_logic_vector((26 - 1) downto 0);
d3 : in std_logic_vector((26 - 1) downto 0);
y : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end mux_187c900130;
architecture behavior of mux_187c900130 is
signal sel_1_20: std_logic_vector((2 - 1) downto 0);
signal d0_1_24: std_logic_vector((26 - 1) downto 0);
signal d1_1_27: std_logic_vector((26 - 1) downto 0);
signal d2_1_30: std_logic_vector((26 - 1) downto 0);
signal d3_1_33: std_logic_vector((26 - 1) downto 0);
signal unregy_join_6_1: std_logic_vector((26 - 1) downto 0);
begin
sel_1_20 <= sel;
d0_1_24 <= d0;
d1_1_27 <= d1;
d2_1_30 <= d2;
d3_1_33 <= d3;
proc_switch_6_1: process (d0_1_24, d1_1_27, d2_1_30, d3_1_33, sel_1_20)
is
begin
case sel_1_20 is
when "00" =>
unregy_join_6_1 <= d0_1_24;
when "01" =>
unregy_join_6_1 <= d1_1_27;
when "10" =>
unregy_join_6_1 <= d2_1_30;
when others =>
unregy_join_6_1 <= d3_1_33;
end case;
end process proc_switch_6_1;
y <= unregy_join_6_1;
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_60ea556961 is
port (
input_port : in std_logic_vector((25 - 1) downto 0);
output_port : out std_logic_vector((25 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_60ea556961;
architecture behavior of reinterpret_60ea556961 is
signal input_port_1_40: unsigned((25 - 1) downto 0);
signal output_port_5_5_force: signed((25 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_unsigned(input_port);
output_port_5_5_force <= unsigned_to_signed(input_port_1_40);
output_port <= signed_to_std_logic_vector(output_port_5_5_force);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity bitbasher_a756ba0096 is
port (
din : in std_logic_vector((26 - 1) downto 0);
dout : out std_logic_vector((25 - 1) downto 0);
vld_out : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end bitbasher_a756ba0096;
architecture behavior of bitbasher_a756ba0096 is
signal din_1_37: unsigned((26 - 1) downto 0);
signal slice_5_31: unsigned((25 - 1) downto 0);
signal fulldout_5_1_concat: unsigned((25 - 1) downto 0);
signal slice_6_44: unsigned((1 - 1) downto 0);
signal concat_6_35: unsigned((1 - 1) downto 0);
signal fullvld_out_6_1_concat: unsigned((1 - 1) downto 0);
begin
din_1_37 <= std_logic_vector_to_unsigned(din);
slice_5_31 <= u2u_slice(din_1_37, 24, 0);
fulldout_5_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_5_31));
slice_6_44 <= u2u_slice(din_1_37, 25, 25);
concat_6_35 <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(slice_6_44));
fullvld_out_6_1_concat <= std_logic_vector_to_unsigned(unsigned_to_std_logic_vector(concat_6_35));
dout <= unsigned_to_std_logic_vector(fulldout_5_1_concat);
vld_out <= unsigned_to_std_logic_vector(fullvld_out_6_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity inverter_e5b38cca3b is
port (
ip : in std_logic_vector((1 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end inverter_e5b38cca3b;
architecture behavior of inverter_e5b38cca3b is
signal ip_1_26: boolean;
type array_type_op_mem_22_20 is array (0 to (1 - 1)) of boolean;
signal op_mem_22_20: array_type_op_mem_22_20 := (
0 => false);
signal op_mem_22_20_front_din: boolean;
signal op_mem_22_20_back: boolean;
signal op_mem_22_20_push_front_pop_back_en: std_logic;
signal internal_ip_12_1_bitnot: boolean;
begin
ip_1_26 <= ((ip) = "1");
op_mem_22_20_back <= op_mem_22_20(0);
proc_op_mem_22_20: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_22_20_push_front_pop_back_en = '1')) then
op_mem_22_20(0) <= op_mem_22_20_front_din;
end if;
end if;
end process proc_op_mem_22_20;
internal_ip_12_1_bitnot <= ((not boolean_to_vector(ip_1_26)) = "1");
op_mem_22_20_push_front_pop_back_en <= '0';
op <= boolean_to_vector(internal_ip_12_1_bitnot);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_80f90b97d0 is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_80f90b97d0;
architecture behavior of logical_80f90b97d0 is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 and d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity logical_aacf6e1b0e is
port (
d0 : in std_logic_vector((1 - 1) downto 0);
d1 : in std_logic_vector((1 - 1) downto 0);
y : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end logical_aacf6e1b0e;
architecture behavior of logical_aacf6e1b0e is
signal d0_1_24: std_logic;
signal d1_1_27: std_logic;
signal fully_2_1_bit: std_logic;
begin
d0_1_24 <= d0(0);
d1_1_27 <= d1(0);
fully_2_1_bit <= d0_1_24 or d1_1_27;
y <= std_logic_to_vector(fully_2_1_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity expr_375d7bbece is
port (
a : in std_logic_vector((1 - 1) downto 0);
b : in std_logic_vector((1 - 1) downto 0);
c : in std_logic_vector((1 - 1) downto 0);
dout : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end expr_375d7bbece;
architecture behavior of expr_375d7bbece is
signal a_1_24: boolean;
signal b_1_27: boolean;
signal c_1_30: boolean;
signal bit_6_36: boolean;
signal fulldout_6_2_bit: boolean;
begin
a_1_24 <= ((a) = "1");
b_1_27 <= ((b) = "1");
c_1_30 <= ((c) = "1");
bit_6_36 <= ((boolean_to_vector(b_1_27) and boolean_to_vector(a_1_24)) = "1");
fulldout_6_2_bit <= ((boolean_to_vector(c_1_30) and boolean_to_vector(bit_6_36)) = "1");
dout <= boolean_to_vector(fulldout_6_2_bit);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xldivider_generator_ee95dc360423b121d9ecd626691cc2ae is
port(
ce:in std_logic;
clk:in std_logic;
m_axis_dout_tdata_fractional:out std_logic_vector(24 downto 0);
m_axis_dout_tdata_quotient:out std_logic_vector(25 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_dividend_tdata_dividend:in std_logic_vector(25 downto 0);
s_axis_dividend_tready:out std_logic;
s_axis_dividend_tvalid:in std_logic;
s_axis_divisor_tdata_divisor:in std_logic_vector(25 downto 0);
s_axis_divisor_tready:out std_logic;
s_axis_divisor_tvalid:in std_logic
);
end xldivider_generator_ee95dc360423b121d9ecd626691cc2ae;
architecture behavior of xldivider_generator_ee95dc360423b121d9ecd626691cc2ae is
component dv_gn_v4_0_e1825854b6ed410d
port(
aclk:in std_logic;
aclken:in std_logic;
m_axis_dout_tdata:out std_logic_vector(55 downto 0);
m_axis_dout_tvalid:out std_logic;
s_axis_dividend_tdata:in std_logic_vector(31 downto 0);
s_axis_dividend_tready:out std_logic;
s_axis_dividend_tvalid:in std_logic;
s_axis_divisor_tdata:in std_logic_vector(31 downto 0);
s_axis_divisor_tready:out std_logic;
s_axis_divisor_tvalid:in std_logic
);
end component;
signal m_axis_dout_tdata_net: std_logic_vector(55 downto 0) := (others=>'0');
signal s_axis_dividend_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
signal s_axis_divisor_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
begin
m_axis_dout_tdata_quotient <= m_axis_dout_tdata_net(50 downto 25);
m_axis_dout_tdata_fractional <= m_axis_dout_tdata_net(24 downto 0);
s_axis_dividend_tdata_net(25 downto 0) <= s_axis_dividend_tdata_dividend;
s_axis_divisor_tdata_net(25 downto 0) <= s_axis_divisor_tdata_divisor;
dv_gn_v4_0_e1825854b6ed410d_instance : dv_gn_v4_0_e1825854b6ed410d
port map(
aclk=>clk,
aclken=>ce,
m_axis_dout_tdata=>m_axis_dout_tdata_net,
m_axis_dout_tvalid=>m_axis_dout_tvalid,
s_axis_dividend_tdata=>s_axis_dividend_tdata_net,
s_axis_dividend_tready=>s_axis_dividend_tready,
s_axis_dividend_tvalid=>s_axis_dividend_tvalid,
s_axis_divisor_tdata=>s_axis_divisor_tdata_net,
s_axis_divisor_tready=>s_axis_divisor_tready,
s_axis_divisor_tvalid=>s_axis_divisor_tvalid
);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_040ef1b598 is
port (
input_port : in std_logic_vector((26 - 1) downto 0);
output_port : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_040ef1b598;
architecture behavior of reinterpret_040ef1b598 is
signal input_port_1_40: signed((26 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port <= signed_to_std_logic_vector(input_port_1_40);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity relational_416cfcae1e is
port (
a : in std_logic_vector((26 - 1) downto 0);
b : in std_logic_vector((26 - 1) downto 0);
op : out std_logic_vector((1 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end relational_416cfcae1e;
architecture behavior of relational_416cfcae1e is
signal a_1_31: signed((26 - 1) downto 0);
signal b_1_34: signed((26 - 1) downto 0);
type array_type_op_mem_32_22 is array (0 to (1 - 1)) of boolean;
signal op_mem_32_22: array_type_op_mem_32_22 := (
0 => false);
signal op_mem_32_22_front_din: boolean;
signal op_mem_32_22_back: boolean;
signal op_mem_32_22_push_front_pop_back_en: std_logic;
signal result_18_3_rel: boolean;
begin
a_1_31 <= std_logic_vector_to_signed(a);
b_1_34 <= std_logic_vector_to_signed(b);
op_mem_32_22_back <= op_mem_32_22(0);
proc_op_mem_32_22: process (clk)
is
variable i: integer;
begin
if (clk'event and (clk = '1')) then
if ((ce = '1') and (op_mem_32_22_push_front_pop_back_en = '1')) then
op_mem_32_22(0) <= op_mem_32_22_front_din;
end if;
end if;
end process proc_op_mem_32_22;
result_18_3_rel <= a_1_31 > b_1_34;
op_mem_32_22_front_din <= result_18_3_rel;
op_mem_32_22_push_front_pop_back_en <= '1';
op <= boolean_to_vector(op_mem_32_22_back);
end behavior;
-------------------------------------------------------------------
-- System Generator version 13.4 VHDL source file.
--
-- Copyright(C) 2011 by Xilinx, Inc. All rights reserved. This
-- text/file contains proprietary, confidential information of Xilinx,
-- Inc., is distributed under license from Xilinx, Inc., and may be used,
-- copied and/or disclosed only pursuant to the terms of a valid license
-- agreement with Xilinx, Inc. Xilinx hereby grants you a license to use
-- this text/file solely for design, simulation, implementation and
-- creation of design files limited to Xilinx devices or technologies.
-- Use with non-Xilinx devices or technologies is expressly prohibited
-- and immediately terminates your license unless covered by a separate
-- agreement.
--
-- Xilinx is providing this design, code, or information "as is" solely
-- for use in developing programs and solutions for Xilinx devices. By
-- providing this design, code, or information as one possible
-- implementation of this feature, application or standard, Xilinx is
-- making no representation that this implementation is free from any
-- claims of infringement. You are responsible for obtaining any rights
-- you may require for your implementation. Xilinx expressly disclaims
-- any warranty whatsoever with respect to the adequacy of the
-- implementation, including but not limited to warranties of
-- merchantability or fitness for a particular purpose.
--
-- Xilinx products are not intended for use in life support appliances,
-- devices, or systems. Use in such applications is expressly prohibited.
--
-- Any modifications that are made to the source code are done at the user's
-- sole risk and will be unsupported.
--
-- This copyright and support notice must be retained as part of this
-- text at all times. (c) Copyright 1995-2011 Xilinx, Inc. All rights
-- reserved.
-------------------------------------------------------------------
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.conv_pkg.all;
entity xladdsub is
generic (
core_name0: string := "";
a_width: integer := 16;
a_bin_pt: integer := 4;
a_arith: integer := xlUnsigned;
c_in_width: integer := 16;
c_in_bin_pt: integer := 4;
c_in_arith: integer := xlUnsigned;
c_out_width: integer := 16;
c_out_bin_pt: integer := 4;
c_out_arith: integer := xlUnsigned;
b_width: integer := 8;
b_bin_pt: integer := 2;
b_arith: integer := xlUnsigned;
s_width: integer := 17;
s_bin_pt: integer := 4;
s_arith: integer := xlUnsigned;
rst_width: integer := 1;
rst_bin_pt: integer := 0;
rst_arith: integer := xlUnsigned;
en_width: integer := 1;
en_bin_pt: integer := 0;
en_arith: integer := xlUnsigned;
full_s_width: integer := 17;
full_s_arith: integer := xlUnsigned;
mode: integer := xlAddMode;
extra_registers: integer := 0;
latency: integer := 0;
quantization: integer := xlTruncate;
overflow: integer := xlWrap;
c_latency: integer := 0;
c_output_width: integer := 17;
c_has_c_in : integer := 0;
c_has_c_out : integer := 0
);
port (
a: in std_logic_vector(a_width - 1 downto 0);
b: in std_logic_vector(b_width - 1 downto 0);
c_in : in std_logic_vector (0 downto 0) := "0";
ce: in std_logic;
clr: in std_logic := '0';
clk: in std_logic;
rst: in std_logic_vector(rst_width - 1 downto 0) := "0";
en: in std_logic_vector(en_width - 1 downto 0) := "1";
c_out : out std_logic_vector (0 downto 0);
s: out std_logic_vector(s_width - 1 downto 0)
);
end xladdsub;
architecture behavior of xladdsub is
component synth_reg
generic (
width: integer := 16;
latency: integer := 5
);
port (
i: in std_logic_vector(width - 1 downto 0);
ce: in std_logic;
clr: in std_logic;
clk: in std_logic;
o: out std_logic_vector(width - 1 downto 0)
);
end component;
function format_input(inp: std_logic_vector; old_width, delta, new_arith,
new_width: integer)
return std_logic_vector
is
variable vec: std_logic_vector(old_width-1 downto 0);
variable padded_inp: std_logic_vector((old_width + delta)-1 downto 0);
variable result: std_logic_vector(new_width-1 downto 0);
begin
vec := inp;
if (delta > 0) then
padded_inp := pad_LSB(vec, old_width+delta);
result := extend_MSB(padded_inp, new_width, new_arith);
else
result := extend_MSB(vec, new_width, new_arith);
end if;
return result;
end;
constant full_s_bin_pt: integer := fractional_bits(a_bin_pt, b_bin_pt);
constant full_a_width: integer := full_s_width;
constant full_b_width: integer := full_s_width;
signal full_a: std_logic_vector(full_a_width - 1 downto 0);
signal full_b: std_logic_vector(full_b_width - 1 downto 0);
signal core_s: std_logic_vector(full_s_width - 1 downto 0);
signal conv_s: std_logic_vector(s_width - 1 downto 0);
signal temp_cout : std_logic;
signal internal_clr: std_logic;
signal internal_ce: std_logic;
signal extra_reg_ce: std_logic;
signal override: std_logic;
signal logic1: std_logic_vector(0 downto 0);
component addsb_11_0_26986301a9f671cd
port (
a: in std_logic_vector(25 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(25 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_26986301a9f671cd:
component is true;
attribute fpga_dont_touch of addsb_11_0_26986301a9f671cd:
component is "true";
attribute box_type of addsb_11_0_26986301a9f671cd:
component is "black_box";
component addsb_11_0_8b0747970e52f130
port (
a: in std_logic_vector(26 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(26 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_8b0747970e52f130:
component is true;
attribute fpga_dont_touch of addsb_11_0_8b0747970e52f130:
component is "true";
attribute box_type of addsb_11_0_8b0747970e52f130:
component is "black_box";
component addsb_11_0_239e4f614ba09ab1
port (
a: in std_logic_vector(26 - 1 downto 0);
s: out std_logic_vector(c_output_width - 1 downto 0);
b: in std_logic_vector(26 - 1 downto 0)
);
end component;
attribute syn_black_box of addsb_11_0_239e4f614ba09ab1:
component is true;
attribute fpga_dont_touch of addsb_11_0_239e4f614ba09ab1:
component is "true";
attribute box_type of addsb_11_0_239e4f614ba09ab1:
component is "black_box";
begin
internal_clr <= (clr or (rst(0))) and ce;
internal_ce <= ce and en(0);
logic1(0) <= '1';
addsub_process: process (a, b, core_s)
begin
full_a <= format_input (a, a_width, b_bin_pt - a_bin_pt, a_arith,
full_a_width);
full_b <= format_input (b, b_width, a_bin_pt - b_bin_pt, b_arith,
full_b_width);
conv_s <= convert_type (core_s, full_s_width, full_s_bin_pt, full_s_arith,
s_width, s_bin_pt, s_arith, quantization, overflow);
end process addsub_process;
comp0: if ((core_name0 = "addsb_11_0_26986301a9f671cd")) generate
core_instance0: addsb_11_0_26986301a9f671cd
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp1: if ((core_name0 = "addsb_11_0_8b0747970e52f130")) generate
core_instance1: addsb_11_0_8b0747970e52f130
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
comp2: if ((core_name0 = "addsb_11_0_239e4f614ba09ab1")) generate
core_instance2: addsb_11_0_239e4f614ba09ab1
port map (
a => full_a,
s => core_s,
b => full_b
);
end generate;
latency_test: if (extra_registers > 0) generate
override_test: if (c_latency > 1) generate
override_pipe: synth_reg
generic map (
width => 1,
latency => c_latency
)
port map (
i => logic1,
ce => internal_ce,
clr => internal_clr,
clk => clk,
o(0) => override);
extra_reg_ce <= ce and en(0) and override;
end generate override_test;
no_override: if ((c_latency = 0) or (c_latency = 1)) generate
extra_reg_ce <= ce and en(0);
end generate no_override;
extra_reg: synth_reg
generic map (
width => s_width,
latency => extra_registers
)
port map (
i => conv_s,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => s
);
cout_test: if (c_has_c_out = 1) generate
c_out_extra_reg: synth_reg
generic map (
width => 1,
latency => extra_registers
)
port map (
i(0) => temp_cout,
ce => extra_reg_ce,
clr => internal_clr,
clk => clk,
o => c_out
);
end generate cout_test;
end generate;
latency_s: if ((latency = 0) or (extra_registers = 0)) generate
s <= conv_s;
end generate latency_s;
latency0: if (((latency = 0) or (extra_registers = 0)) and
(c_has_c_out = 1)) generate
c_out(0) <= temp_cout;
end generate latency0;
tie_dangling_cout: if (c_has_c_out = 0) generate
c_out <= "0";
end generate tie_dangling_cout;
end architecture behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity concat_43e7f055fa is
port (
in0 : in std_logic_vector((1 - 1) downto 0);
in1 : in std_logic_vector((25 - 1) downto 0);
y : out std_logic_vector((26 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end concat_43e7f055fa;
architecture behavior of concat_43e7f055fa is
signal in0_1_23: boolean;
signal in1_1_27: unsigned((25 - 1) downto 0);
signal y_2_1_concat: unsigned((26 - 1) downto 0);
begin
in0_1_23 <= ((in0) = "1");
in1_1_27 <= std_logic_vector_to_unsigned(in1);
y_2_1_concat <= std_logic_vector_to_unsigned(boolean_to_vector(in0_1_23) & unsigned_to_std_logic_vector(in1_1_27));
y <= unsigned_to_std_logic_vector(y_2_1_concat);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity reinterpret_c3c0e847be is
port (
input_port : in std_logic_vector((25 - 1) downto 0);
output_port : out std_logic_vector((25 - 1) downto 0);
clk : in std_logic;
ce : in std_logic;
clr : in std_logic);
end reinterpret_c3c0e847be;
architecture behavior of reinterpret_c3c0e847be is
signal input_port_1_40: signed((25 - 1) downto 0);
signal output_port_5_5_force: unsigned((25 - 1) downto 0);
begin
input_port_1_40 <= std_logic_vector_to_signed(input_port);
output_port_5_5_force <= signed_to_unsigned(input_port_1_40);
output_port <= unsigned_to_std_logic_vector(output_port_5_5_force);
end behavior;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.conv_pkg.all;
entity xlfir_compiler_c8ab56fde252f177c3a1ef23ff29e49a is
port(
ce:in std_logic;
ce_5600000:in std_logic;
ce_56000000:in std_logic;
ce_logic_5600000:in std_logic;
clk:in std_logic;
clk_5600000:in std_logic;
clk_56000000:in std_logic;
clk_logic_5600000:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(25 downto 0);
m_axis_data_tuser_chanid:out std_logic_vector(1 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(24 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser_chanid:in std_logic_vector(1 downto 0);
src_ce:in std_logic;
src_clk:in std_logic
);
end xlfir_compiler_c8ab56fde252f177c3a1ef23ff29e49a;
architecture behavior of xlfir_compiler_c8ab56fde252f177c3a1ef23ff29e49a is
component fr_cmplr_v6_3_f22a7e3f4b613ff0
port(
aclk:in std_logic;
aclken:in std_logic;
event_s_data_chanid_incorrect:out std_logic;
m_axis_data_tdata:out std_logic_vector(31 downto 0);
m_axis_data_tuser:out std_logic_vector(1 downto 0);
m_axis_data_tvalid:out std_logic;
s_axis_data_tdata:in std_logic_vector(31 downto 0);
s_axis_data_tready:out std_logic;
s_axis_data_tuser:in std_logic_vector(1 downto 0);
s_axis_data_tvalid:in std_logic
);
end component;
signal m_axis_data_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
signal m_axis_data_tdata_ps_net: std_logic_vector(25 downto 0) := (others=>'0');
signal m_axis_data_tuser_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tuser_chanid_ps_net: std_logic_vector(1 downto 0) := (others=>'0');
signal m_axis_data_tvalid_ps_net: std_logic := '0';
signal m_axis_data_tvalid_ps_net_captured: std_logic := '0';
signal m_axis_data_tvalid_ps_net_or_captured_net: std_logic := '0';
signal s_axis_data_tdata_net: std_logic_vector(31 downto 0) := (others=>'0');
signal s_axis_data_tuser_net: std_logic_vector(1 downto 0) := (others=>'0');
begin
m_axis_data_tdata_ps_net <= m_axis_data_tdata_net(25 downto 0);
m_axis_data_tuser_chanid_ps_net <= m_axis_data_tuser_net(1 downto 0);
s_axis_data_tdata_net(24 downto 0) <= s_axis_data_tdata;
s_axis_data_tuser_net(1 downto 0) <= s_axis_data_tuser_chanid;
m_axis_data_tdata_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 26,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tdata_ps_net,
ce => ce_56000000,
clr => '0',
clk => clk_56000000,
o => m_axis_data_tdata
);
m_axis_data_tuser_chanid_ps_net_synchronizer : entity work.synth_reg_w_init
generic map(
width => 2,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i => m_axis_data_tuser_chanid_ps_net,
ce => ce_56000000,
clr => '0',
clk => clk_56000000,
o => m_axis_data_tuser_chanid
);
m_axis_data_tvalid_ps_net_or_captured_net <= m_axis_data_tvalid_ps_net or m_axis_data_tvalid_ps_net_captured;
m_axis_data_tvalid_ps_net_synchronizer_1 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => m_axis_data_tvalid_ps_net_or_captured_net,
ce => ce_56000000,
clr => '0',
clk => clk_56000000,
o(0) => m_axis_data_tvalid
);
m_axis_data_tvalid_ps_net_synchronizer_2 : entity work.synth_reg_w_init
generic map(
width => 1,
init_index => 0,
init_value => "0",
latency => 1
)
port map (
i(0) => '1',
ce => m_axis_data_tvalid_ps_net,
clr => '0',
clk => clk_56000000,
o(0) => m_axis_data_tvalid_ps_net_captured
);
fr_cmplr_v6_3_f22a7e3f4b613ff0_instance : fr_cmplr_v6_3_f22a7e3f4b613ff0
port map(
aclk=>clk,
aclken=>ce,
event_s_data_chanid_incorrect=>event_s_data_chanid_incorrect,
m_axis_data_tdata=>m_axis_data_tdata_net,
m_axis_data_tuser=>m_axis_data_tuser_net,
m_axis_data_tvalid=>m_axis_data_tvalid_ps_net,
s_axis_data_tdata=>s_axis_data_tdata_net,
s_axis_data_tready=>s_axis_data_tready,
s_axis_data_tuser=>s_axis_data_tuser_net,
s_axis_data_tvalid=>ce_logic_5600000
);
end behavior;
| lgpl-3.0 | 5b6e02d264c54f9f9beb2bbc06922b86 | 0.595584 | 3.374198 | false | false | false | false |
lerwys/GitTest | hdl/modules/dsp_cores_pkg.vhd | 1 | 52,147 | library ieee;
use ieee.std_logic_1164.all;
library std;
use std.textio.all;
library work;
-- Main Wishbone Definitions
use work.wishbone_pkg.all;
package dsp_cores_pkg is
--------------------------------------------------------------------
-- Constants
--------------------------------------------------------------------
constant c_dsp_ref_num_bits : natural := 24;
constant c_dsp_pos_num_bits : natural := 26;
constant c_machine_name : string := "UVX";
-------------------------------------------------------------------------------
-- Functions Declaration
-------------------------------------------------------------------------------
function f_window_file(g_rffe_version : string) return string;
function f_dds_cos_file(g_machine_name : string) return string;
function f_dds_sin_file(g_machine_name : string) return string;
function f_dds_num_points(g_machine_name : string) return natural;
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component position_calc
generic (
g_pipeline_regs : integer := 5
);
port(
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
clk : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
clr : in std_logic; -- clear signal
del_sig_div_fofb_thres_i : in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i : in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i : in std_logic_vector(25 downto 0);
ksum_i : in std_logic_vector(24 downto 0);
kx_i : in std_logic_vector(24 downto 0);
ky_i : in std_logic_vector(24 downto 0);
dds_config_valid_ch0_i : in std_logic;
dds_config_valid_ch1_i : in std_logic;
dds_config_valid_ch2_i : in std_logic;
dds_config_valid_ch3_i : in std_logic;
dds_pinc_ch0_i : in std_logic_vector(29 downto 0);
dds_pinc_ch1_i : in std_logic_vector(29 downto 0);
dds_pinc_ch2_i : in std_logic_vector(29 downto 0);
dds_pinc_ch3_i : in std_logic_vector(29 downto 0);
dds_poff_ch0_i : in std_logic_vector(29 downto 0);
dds_poff_ch1_i : in std_logic_vector(29 downto 0);
dds_poff_ch2_i : in std_logic_vector(29 downto 0);
dds_poff_ch3_i : in std_logic_vector(29 downto 0);
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_q_ch01_incorrect_o : out std_logic;
tbt_decim_q_ch23_incorrect_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_q_01_missing_o : out std_logic;
fofb_decim_q_23_missing_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_cic_unexpected_o : out std_logic;
monit_cfir_incorrect_o : out std_logic;
monit_pfir_incorrect_o : out std_logic;
x_tbt_o : out std_logic_vector(25 downto 0);
x_tbt_valid_o : out std_logic;
y_tbt_o : out std_logic_vector(25 downto 0);
y_tbt_valid_o : out std_logic;
q_tbt_o : out std_logic_vector(25 downto 0);
q_tbt_valid_o : out std_logic;
sum_tbt_o : out std_logic_vector(25 downto 0);
sum_tbt_valid_o : out std_logic;
x_fofb_o : out std_logic_vector(25 downto 0);
x_fofb_valid_o : out std_logic;
y_fofb_o : out std_logic_vector(25 downto 0);
y_fofb_valid_o : out std_logic;
q_fofb_o : out std_logic_vector(25 downto 0);
q_fofb_valid_o : out std_logic;
sum_fofb_o : out std_logic_vector(25 downto 0);
sum_fofb_valid_o : out std_logic;
x_monit_o : out std_logic_vector(25 downto 0);
x_monit_valid_o : out std_logic;
y_monit_o : out std_logic_vector(25 downto 0);
y_monit_valid_o : out std_logic;
q_monit_o : out std_logic_vector(25 downto 0);
q_monit_valid_o : out std_logic;
sum_monit_o : out std_logic_vector(25 downto 0);
sum_monit_valid_o : out std_logic;
x_monit_1_o : out std_logic_vector(25 downto 0);
x_monit_1_valid_o : out std_logic;
y_monit_1_o : out std_logic_vector(25 downto 0);
y_monit_1_valid_o : out std_logic;
q_monit_1_o : out std_logic_vector(25 downto 0);
q_monit_1_valid_o : out std_logic;
sum_monit_1_o : out std_logic_vector(25 downto 0);
sum_monit_1_valid_o : out std_logic;
monit_pos_1_incorrect_o : out std_logic;
-- Clock drivers for various rates
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic
);
end component;
component ddc_bpm_476_066_cw
-- start of user modification here!
generic (
pipeline_regs: integer := 5
);
-- end of user modification here!
port (
adc_ch0_i: in std_logic_vector(15 downto 0);
adc_ch1_i: in std_logic_vector(15 downto 0);
adc_ch2_i: in std_logic_vector(15 downto 0);
adc_ch3_i: in std_logic_vector(15 downto 0);
ce: in std_logic := '1';
ce_clr: in std_logic := '1';
clk: in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
dds_config_valid_ch0_i: in std_logic;
dds_config_valid_ch1_i: in std_logic;
dds_config_valid_ch2_i: in std_logic;
dds_config_valid_ch3_i: in std_logic;
dds_pinc_ch0_i: in std_logic_vector(29 downto 0);
dds_pinc_ch1_i: in std_logic_vector(29 downto 0);
dds_pinc_ch2_i: in std_logic_vector(29 downto 0);
dds_pinc_ch3_i: in std_logic_vector(29 downto 0);
dds_poff_ch0_i: in std_logic_vector(29 downto 0);
dds_poff_ch1_i: in std_logic_vector(29 downto 0);
dds_poff_ch2_i: in std_logic_vector(29 downto 0);
dds_poff_ch3_i: in std_logic_vector(29 downto 0);
del_sig_div_fofb_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_monit_thres_i: in std_logic_vector(25 downto 0);
del_sig_div_tbt_thres_i: in std_logic_vector(25 downto 0);
ksum_i: in std_logic_vector(24 downto 0);
kx_i: in std_logic_vector(24 downto 0);
ky_i: in std_logic_vector(24 downto 0);
adc_ch0_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o: out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o: out std_logic_vector(15 downto 0);
bpf_ch0_o: out std_logic_vector(23 downto 0);
bpf_ch1_o: out std_logic_vector(23 downto 0);
bpf_ch2_o: out std_logic_vector(23 downto 0);
bpf_ch3_o: out std_logic_vector(23 downto 0);
cic_fofb_q_01_missing_o: out std_logic;
cic_fofb_q_23_missing_o: out std_logic;
fofb_amp_ch0_o: out std_logic_vector(23 downto 0);
fofb_amp_ch1_o: out std_logic_vector(23 downto 0);
fofb_amp_ch2_o: out std_logic_vector(23 downto 0);
fofb_amp_ch3_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o: out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o: out std_logic_vector(23 downto 0);
fofb_pha_ch0_o: out std_logic_vector(23 downto 0);
fofb_pha_ch1_o: out std_logic_vector(23 downto 0);
fofb_pha_ch2_o: out std_logic_vector(23 downto 0);
fofb_pha_ch3_o: out std_logic_vector(23 downto 0);
mix_ch0_i_o: out std_logic_vector(23 downto 0);
mix_ch0_q_o: out std_logic_vector(23 downto 0);
mix_ch1_i_o: out std_logic_vector(23 downto 0);
mix_ch1_q_o: out std_logic_vector(23 downto 0);
mix_ch2_i_o: out std_logic_vector(23 downto 0);
mix_ch2_q_o: out std_logic_vector(23 downto 0);
mix_ch3_i_o: out std_logic_vector(23 downto 0);
mix_ch3_q_o: out std_logic_vector(23 downto 0);
monit_amp_ch0_o: out std_logic_vector(23 downto 0);
monit_amp_ch1_o: out std_logic_vector(23 downto 0);
monit_amp_ch2_o: out std_logic_vector(23 downto 0);
monit_amp_ch3_o: out std_logic_vector(23 downto 0);
monit_cfir_incorrect_o: out std_logic;
monit_cic_unexpected_o: out std_logic;
monit_pfir_incorrect_o: out std_logic;
monit_pos_1_incorrect_o: out std_logic;
q_fofb_o: out std_logic_vector(25 downto 0);
q_fofb_valid_o: out std_logic;
q_monit_1_o: out std_logic_vector(25 downto 0);
q_monit_1_valid_o: out std_logic;
q_monit_o: out std_logic_vector(25 downto 0);
q_monit_valid_o: out std_logic;
q_tbt_o: out std_logic_vector(25 downto 0);
q_tbt_valid_o: out std_logic;
sum_fofb_o: out std_logic_vector(25 downto 0);
sum_fofb_valid_o: out std_logic;
sum_monit_1_o: out std_logic_vector(25 downto 0);
sum_monit_1_valid_o: out std_logic;
sum_monit_o: out std_logic_vector(25 downto 0);
sum_monit_valid_o: out std_logic;
sum_tbt_o: out std_logic_vector(25 downto 0);
sum_tbt_valid_o: out std_logic;
tbt_amp_ch0_o: out std_logic_vector(23 downto 0);
tbt_amp_ch1_o: out std_logic_vector(23 downto 0);
tbt_amp_ch2_o: out std_logic_vector(23 downto 0);
tbt_amp_ch3_o: out std_logic_vector(23 downto 0);
tbt_decim_ch01_incorrect_o: out std_logic;
tbt_decim_ch0_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch23_incorrect_o: out std_logic;
tbt_decim_ch2_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o: out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o: out std_logic_vector(23 downto 0);
tbt_pha_ch0_o: out std_logic_vector(23 downto 0);
tbt_pha_ch1_o: out std_logic_vector(23 downto 0);
tbt_pha_ch2_o: out std_logic_vector(23 downto 0);
tbt_pha_ch3_o: out std_logic_vector(23 downto 0);
x_fofb_o: out std_logic_vector(25 downto 0);
x_fofb_valid_o: out std_logic;
x_monit_1_o: out std_logic_vector(25 downto 0);
x_monit_1_valid_o: out std_logic;
x_monit_o: out std_logic_vector(25 downto 0);
x_monit_valid_o: out std_logic;
x_tbt_o: out std_logic_vector(25 downto 0);
x_tbt_valid_o: out std_logic;
y_fofb_o: out std_logic_vector(25 downto 0);
y_fofb_valid_o: out std_logic;
y_monit_1_o: out std_logic_vector(25 downto 0);
y_monit_1_valid_o: out std_logic;
y_monit_o: out std_logic_vector(25 downto 0);
y_monit_valid_o: out std_logic;
y_tbt_o: out std_logic_vector(25 downto 0);
y_tbt_valid_o: out std_logic
);
end component;
component wb_bpm_swap
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
mode1_o : out std_logic_vector(1 downto 0);
mode2_o : out std_logic_vector(1 downto 0);
wdw_rst_o : out std_logic; -- Reset Windowing module
wdw_sw_clk_i : in std_logic; -- Switching clock from Windowing module
wdw_use_o : out std_logic; -- Use Windowing module
wdw_dly_o : out std_logic_vector(15 downto 0); -- Delay to apply the window
-- Output to RFFE board
clk_swap_o : out std_logic;
clk_swap_en_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end component;
component xwb_bpm_swap
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
fs_rst_n_i : in std_logic;
fs_clk_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
-- Input from ADC FMC board
cha_i : in std_logic_vector(15 downto 0);
chb_i : in std_logic_vector(15 downto 0);
chc_i : in std_logic_vector(15 downto 0);
chd_i : in std_logic_vector(15 downto 0);
-- Output to data processing level
cha_o : out std_logic_vector(15 downto 0);
chb_o : out std_logic_vector(15 downto 0);
chc_o : out std_logic_vector(15 downto 0);
chd_o : out std_logic_vector(15 downto 0);
mode1_o : out std_logic_vector(1 downto 0);
mode2_o : out std_logic_vector(1 downto 0);
wdw_rst_o : out std_logic; -- Reset Windowing module
wdw_sw_clk_i : in std_logic; -- Switching clock from Windowing module
wdw_use_o : out std_logic; -- Use Windowing module
wdw_dly_o : out std_logic_vector(15 downto 0); -- Delay to apply the window
-- Output to RFFE board
clk_swap_o : out std_logic;
clk_swap_en_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0)
);
end component;
component input_conditioner
generic (
--g_clk_freq : real := 120.0e6; -- System clock frequency
--g_sw_freq : real := 100.0e3; -- Desired switching frequency
g_sw_interval : natural := 1000;
g_input_width : natural := 16;
g_output_width : natural := 24;
g_window_width : natural := 24;
g_input_delay : natural := 2;
g_window_coef_file : string);
port (
reset_n_i : in std_logic; -- Reset data
clk_i : in std_logic; -- Main clock
adc_a_i : in std_logic_vector(g_input_width-1 downto 0);
adc_b_i : in std_logic_vector(g_input_width-1 downto 0);
adc_c_i : in std_logic_vector(g_input_width-1 downto 0);
adc_d_i : in std_logic_vector(g_input_width-1 downto 0);
switch_o : out std_logic; -- Switch position output
switch_en_i : in std_logic;
switch_delay_i : in std_logic_vector(15 downto 0);
a_o : out std_logic_vector(g_output_width-1 downto 0);
b_o : out std_logic_vector(g_output_width-1 downto 0);
c_o : out std_logic_vector(g_output_width-1 downto 0);
d_o : out std_logic_vector(g_output_width-1 downto 0);
dbg_cur_address_o : out std_logic_vector(31 downto 0));
end component;
component wb_position_calc_core
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_rffe_version : string := "V2";
g_with_switching : natural := 0
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
-----------------------------
-- BPF Data
-----------------------------
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
bpf_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
pos_x_tbt_o : out std_logic_vector(25 downto 0);
pos_y_tbt_o : out std_logic_vector(25 downto 0);
pos_q_tbt_o : out std_logic_vector(25 downto 0);
pos_sum_tbt_o : out std_logic_vector(25 downto 0);
pos_tbt_valid_o : out std_logic;
pos_x_fofb_o : out std_logic_vector(25 downto 0);
pos_y_fofb_o : out std_logic_vector(25 downto 0);
pos_q_fofb_o : out std_logic_vector(25 downto 0);
pos_sum_fofb_o : out std_logic_vector(25 downto 0);
pos_fofb_valid_o : out std_logic;
pos_x_monit_o : out std_logic_vector(25 downto 0);
pos_y_monit_o : out std_logic_vector(25 downto 0);
pos_q_monit_o : out std_logic_vector(25 downto 0);
pos_sum_monit_o : out std_logic_vector(25 downto 0);
pos_monit_valid_o : out std_logic;
pos_x_monit_1_o : out std_logic_vector(25 downto 0);
pos_y_monit_1_o : out std_logic_vector(25 downto 0);
pos_q_monit_1_o : out std_logic_vector(25 downto 0);
pos_sum_monit_1_o : out std_logic_vector(25 downto 0);
pos_monit_1_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0);
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_11120000_o : out std_logic;
clk_ce_111200000_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic;
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(15 downto 0)
);
end component;
component xwb_position_calc_core
generic
(
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_rffe_version : string := "V2";
g_with_switching : natural := 0
);
port
(
rst_n_i : in std_logic;
clk_i : in std_logic; -- Wishbone clock
fs_rst_n_i : in std_logic; -- FS reset
fs_rst2x_n_i : in std_logic; -- FS 2x reset
fs_clk_i : in std_logic; -- clock period = 8.8823218389287 ns (112.583175675676 Mhz)
fs_clk2x_i : in std_logic; -- clock period = 4.4411609194644 ns (225.166351351351 Mhz)
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out;
-----------------------------
-- Raw ADC signals
-----------------------------
adc_ch0_i : in std_logic_vector(15 downto 0);
adc_ch1_i : in std_logic_vector(15 downto 0);
adc_ch2_i : in std_logic_vector(15 downto 0);
adc_ch3_i : in std_logic_vector(15 downto 0);
-----------------------------
-- Position calculation at various rates
-----------------------------
adc_ch0_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch1_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch2_dbg_data_o : out std_logic_vector(15 downto 0);
adc_ch3_dbg_data_o : out std_logic_vector(15 downto 0);
-----------------------------
-- BPF Data
-----------------------------
bpf_ch0_o : out std_logic_vector(23 downto 0);
bpf_ch1_o : out std_logic_vector(23 downto 0);
bpf_ch2_o : out std_logic_vector(23 downto 0);
bpf_ch3_o : out std_logic_vector(23 downto 0);
bpf_valid_o : out std_logic;
-----------------------------
-- MIX Data
-----------------------------
mix_ch0_i_o : out std_logic_vector(23 downto 0);
mix_ch0_q_o : out std_logic_vector(23 downto 0);
mix_ch1_i_o : out std_logic_vector(23 downto 0);
mix_ch1_q_o : out std_logic_vector(23 downto 0);
mix_ch2_i_o : out std_logic_vector(23 downto 0);
mix_ch2_q_o : out std_logic_vector(23 downto 0);
mix_ch3_i_o : out std_logic_vector(23 downto 0);
mix_ch3_q_o : out std_logic_vector(23 downto 0);
mix_valid_o : out std_logic;
-----------------------------
-- TBT Data
-----------------------------
tbt_decim_ch0_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch0_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch1_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch2_q_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_i_o : out std_logic_vector(23 downto 0);
tbt_decim_ch3_q_o : out std_logic_vector(23 downto 0);
tbt_decim_valid_o : out std_logic;
tbt_amp_ch0_o : out std_logic_vector(23 downto 0);
tbt_amp_ch1_o : out std_logic_vector(23 downto 0);
tbt_amp_ch2_o : out std_logic_vector(23 downto 0);
tbt_amp_ch3_o : out std_logic_vector(23 downto 0);
tbt_amp_valid_o : out std_logic;
tbt_pha_ch0_o : out std_logic_vector(23 downto 0);
tbt_pha_ch1_o : out std_logic_vector(23 downto 0);
tbt_pha_ch2_o : out std_logic_vector(23 downto 0);
tbt_pha_ch3_o : out std_logic_vector(23 downto 0);
tbt_pha_valid_o : out std_logic;
-----------------------------
-- FOFB Data
-----------------------------
fofb_decim_ch0_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch0_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch1_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch2_q_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_i_o : out std_logic_vector(23 downto 0);
fofb_decim_ch3_q_o : out std_logic_vector(23 downto 0);
fofb_decim_valid_o : out std_logic;
fofb_amp_ch0_o : out std_logic_vector(23 downto 0);
fofb_amp_ch1_o : out std_logic_vector(23 downto 0);
fofb_amp_ch2_o : out std_logic_vector(23 downto 0);
fofb_amp_ch3_o : out std_logic_vector(23 downto 0);
fofb_amp_valid_o : out std_logic;
fofb_pha_ch0_o : out std_logic_vector(23 downto 0);
fofb_pha_ch1_o : out std_logic_vector(23 downto 0);
fofb_pha_ch2_o : out std_logic_vector(23 downto 0);
fofb_pha_ch3_o : out std_logic_vector(23 downto 0);
fofb_pha_valid_o : out std_logic;
-----------------------------
-- Monit. Data
-----------------------------
monit_amp_ch0_o : out std_logic_vector(23 downto 0);
monit_amp_ch1_o : out std_logic_vector(23 downto 0);
monit_amp_ch2_o : out std_logic_vector(23 downto 0);
monit_amp_ch3_o : out std_logic_vector(23 downto 0);
monit_amp_valid_o : out std_logic;
-----------------------------
-- Position Data
-----------------------------
pos_x_tbt_o : out std_logic_vector(25 downto 0);
pos_y_tbt_o : out std_logic_vector(25 downto 0);
pos_q_tbt_o : out std_logic_vector(25 downto 0);
pos_sum_tbt_o : out std_logic_vector(25 downto 0);
pos_tbt_valid_o : out std_logic;
pos_x_fofb_o : out std_logic_vector(25 downto 0);
pos_y_fofb_o : out std_logic_vector(25 downto 0);
pos_q_fofb_o : out std_logic_vector(25 downto 0);
pos_sum_fofb_o : out std_logic_vector(25 downto 0);
pos_fofb_valid_o : out std_logic;
pos_x_monit_o : out std_logic_vector(25 downto 0);
pos_y_monit_o : out std_logic_vector(25 downto 0);
pos_q_monit_o : out std_logic_vector(25 downto 0);
pos_sum_monit_o : out std_logic_vector(25 downto 0);
pos_monit_valid_o : out std_logic;
pos_x_monit_1_o : out std_logic_vector(25 downto 0);
pos_y_monit_1_o : out std_logic_vector(25 downto 0);
pos_q_monit_1_o : out std_logic_vector(25 downto 0);
pos_sum_monit_1_o : out std_logic_vector(25 downto 0);
pos_monit_1_valid_o : out std_logic;
-----------------------------
-- Output to RFFE board
-----------------------------
clk_swap_o : out std_logic;
flag1_o : out std_logic;
flag2_o : out std_logic;
ctrl1_o : out std_logic_vector(7 downto 0);
ctrl2_o : out std_logic_vector(7 downto 0);
-----------------------------
-- Clock drivers for various rates
-----------------------------
clk_ce_1_o : out std_logic;
clk_ce_1112_o : out std_logic;
clk_ce_11120000_o : out std_logic;
clk_ce_111200000_o : out std_logic;
clk_ce_1390000_o : out std_logic;
clk_ce_2_o : out std_logic;
clk_ce_2224_o : out std_logic;
clk_ce_22240000_o : out std_logic;
clk_ce_222400000_o : out std_logic;
clk_ce_2780000_o : out std_logic;
clk_ce_35_o : out std_logic;
clk_ce_5000_o : out std_logic;
clk_ce_556_o : out std_logic;
clk_ce_5560000_o : out std_logic;
clk_ce_70_o : out std_logic;
dbg_cur_address_o : out std_logic_vector(31 downto 0);
dbg_adc_ch0_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch1_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch2_cond_o : out std_logic_vector(15 downto 0);
dbg_adc_ch3_cond_o : out std_logic_vector(15 downto 0)
);
end component;
component position_calc_cdc_fifo
generic
(
g_data_width : natural;
g_size : natural
);
port
(
clk_wr_i : in std_logic;
data_i : in std_logic_vector(g_data_width-1 downto 0);
valid_i : in std_logic;
clk_rd_i : in std_logic;
data_o : out std_logic_vector(g_data_width-1 downto 0);
valid_o : out std_logic
);
end component;
component default_clock_driver
generic (
pipeline_regs: integer := 5
);
port (
sysce: in std_logic;
sysce_clr: in std_logic;
sysclk: in std_logic;
ce_1: out std_logic;
ce_10000: out std_logic;
ce_1120: out std_logic;
ce_1400000: out std_logic;
ce_2: out std_logic;
ce_2240: out std_logic;
ce_22400000: out std_logic;
ce_224000000: out std_logic;
ce_2500: out std_logic;
ce_2800000: out std_logic;
ce_35: out std_logic;
ce_4480: out std_logic;
ce_44800000: out std_logic;
ce_5000: out std_logic;
ce_560: out std_logic;
ce_5600000: out std_logic;
ce_56000000: out std_logic;
ce_70: out std_logic;
ce_logic_1: out std_logic;
ce_logic_1400000: out std_logic;
ce_logic_2240: out std_logic;
ce_logic_22400000: out std_logic;
ce_logic_2800000: out std_logic;
ce_logic_560: out std_logic;
ce_logic_5600000: out std_logic;
ce_logic_70: out std_logic;
clk_1: out std_logic;
clk_10000: out std_logic;
clk_1120: out std_logic;
clk_1400000: out std_logic;
clk_2: out std_logic;
clk_2240: out std_logic;
clk_22400000: out std_logic;
clk_224000000: out std_logic;
clk_2500: out std_logic;
clk_2800000: out std_logic;
clk_35: out std_logic;
clk_4480: out std_logic;
clk_44800000: out std_logic;
clk_5000: out std_logic;
clk_560: out std_logic;
clk_5600000: out std_logic;
clk_56000000: out std_logic;
clk_70: out std_logic
);
end component;
component xlclockdriver
generic (
period: integer := 2;
log_2_period: integer := 0;
pipeline_regs: integer := 5;
use_bufg: integer := 0
);
port (
sysclk: in std_logic;
sysclr: in std_logic;
sysce: in std_logic;
clk: out std_logic;
clr: out std_logic;
ce: out std_logic;
ce_logic: out std_logic
);
end component;
end dsp_cores_pkg;
package body dsp_cores_pkg is
function f_window_file(g_rffe_version : string)
return string
is
variable filepath : line;
begin
case g_rffe_version is
when "V1" =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window_n_500.ram");
when "V2" =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window_n_500_tukey_0_2.ram");
when others =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/sw_windowing/window_n_500_tukey_0_2.ram");
end case;
return filepath.all;
end f_window_file;
function f_dds_cos_file(g_machine_name : string)
return string
is
variable filepath : line;
begin
case g_machine_name is
when "SLC" => -- SLAC
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos_slac_50_372.ram");
when "UVX" =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos_uvx_35_148.ram");
when others =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_cos_uvx_35_148.ram");
end case;
return filepath.all;
end f_dds_cos_file;
function f_dds_sin_file(g_machine_name : string)
return string
is
variable filepath : line;
begin
case g_machine_name is
when "SLC" => -- SLAC
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin_slac_50_372.ram");
when "UVX" =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin_uvx_35_148.ram");
when others =>
WRITE(filepath, "../../../ip_cores/dsp-cores/hdl/modules/position_calc/dds_lut/dds_sin_uvx_35_148.ram");
end case;
return filepath.all;
end f_dds_sin_file;
function f_dds_num_points(g_machine_name : string)
return natural
is
variable num_points : natural;
begin
case g_machine_name is
when "SLC" => -- SLAC
num_points := 50;
when "UVX" =>
num_points := 35;
when others =>
num_points := 35;
end case;
return num_points;
end f_dds_num_points;
end dsp_cores_pkg;
| lgpl-3.0 | d041efbde240ea1670b2ea3d5f699b93 | 0.443132 | 3.840268 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/game/space_shooter_demo/space_shooter_demo_top.vhd | 1 | 9,447 | library ieee;
use ieee.std_logic_1164.all;
use work.basic_types_pkg.all;
use work.input_types_pkg.all;
use work.colors_pkg.all;
use work.graphics_types_pkg.all;
use work.text_mode_pkg.all;
use work.sprites_pkg.all;
use work.game_state_pkg.all;
use work.resource_handles_pkg.all;
use work.resource_handles_helper_pkg.all;
use work.resource_data_pkg.all;
use work.resource_data_helper_pkg.all;
use work.vga_pkg.all;
-- Top-level entity for the "Space shooter" game demo using VAGE. On top of this
-- entity, there should be only a very simple wrapper intantiating this entity
-- and connecting its ports to the board used. It should be fairly easy to use
-- this entity in other hardware platforms, without any modifications.
entity space_shooter_demo_top is
port (
-- synchronous reset, used by all user logic
reset: in std_logic;
-- system clock used for all user logic
clock_50_Mhz: in std_logic;
-- VGA clock used by the video renderer; should be approximately
-- 25.715 MHz (25 MHz is acceptable)
vga_clock_in: in std_logic;
-- Same as VGA input clock, must be passed along to the video DAC chip
vga_clock_out: out std_logic;
-- VGA blank, low during horizontal or vertical retrace (pixels should be blank)
vga_blank: out std_logic;
-- VGA Hsync, low during horizontal synchronism pulse
vga_n_hsync: out std_logic;
-- VGA Vsync, low during vertical synchronism pulse
vga_n_vsync: out std_logic;
-- Composite sync for the ADV7123; if this feature is not used, should
-- be tied to '0'
vga_n_sync: out std_logic;
-- VGA red channel output
vga_red: out std_logic_vector(9 downto 0);
-- VGA green channel output
vga_green: out std_logic_vector(9 downto 0);
-- VGA blue channel output
vga_blue: out std_logic_vector(9 downto 0);
-- Input toggle switches, active high
input_switches: in std_logic_vector(1 downto 0);
-- Input push-button switches, active high
input_buttons: in std_logic_vector(3 downto 0);
-- Debug pins for debugging game logic (e.g., connecting to board leds)
debug_bits: out std_logic_vector(7 downto 0)
);
end;
architecture rtl of space_shooter_demo_top is
-- Medium-resolution time base (used for game state updates and
-- reading the inputs switches)
signal time_base_50_ms: std_logic;
-- Maximum value for the game time counter
constant GAME_TIMER_50_MS_MAX: integer := 1000;
-- Monotonic game time counter, updated every 50 ms. Can be used by
-- the game logic (eg., to animate or move sprites)
signal elapsed_time: integer range 0 to GAME_TIMER_50_MS_MAX;
-- Video engine output uses custom data type; we'll convert here to std_logic
signal vga_output_signals: vga_output_signals_type;
-- True if sprite is active in the game and must be updated by sprite engine
signal sprites_enabled: bool_vector(GAME_SPRITES'range);
-- True if NPC is active in the game and must be updated by NPC engine
signal npcs_enabled: bool_vector(GAME_NPCS'range);
-- Array containing the position of each sprite on the screen; generated by
-- the game logic module and used as an input by the sprites engine
signal sprite_positions: point_array_type(GAME_SPRITES'range);
-- Each element is 'true' while the two corresponding sprites are colliding;
-- values are calculated by the game engine and used by game logic
signal sprite_collisions: bool_vector(GAME_COLLISIONS'range);
-- Background image to be used by the video engine; currently, the game
-- logic is responsible for providing the video engine with background tile
signal background_bitmap: paletted_bitmap_type(0 to 7, 0 to 7);
-- User logic must inform the NPC engine what are the target positions
-- for the NPCs; some types of AI (e.g., AI_FOLLOWER) use this value to
-- calculate their next position
signal npc_target_positions: point_array_type(GAME_NPCS'range);
-- The game engine (NPC engine, actually) calculates the NPC positions
-- and these values are handed over to the game logic
signal npc_positions: point_array_type(GAME_NPCS'range);
signal in_buttons: input_buttons_type;
signal game_state: game_state_type;
-- Text strgins displayed on the screen
signal text_mode_strings: text_mode_strings_type(0 to game_strings_count-1);
begin
----------------------------------------------------------------------------
-- Overall architecture description:
-- 1) Instantiate the game logic
-- 2) Instantiate the NPC engine
-- 3) Instantiate the game engine
-- 4) Select a background bitmap based on the current game state
-- 5) Convert signals between std_logic and custom data types. Internally,
-- we use custom types for better abstraction; at the interface, we use
-- std_logic for better portability and easier instantiation
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Section 1) Instantiate the game logic. This entity receives the raw game
-- data and events, and updates the game state accordingly.
logic: entity work.game_logic
port map(
clock => clock_50_Mhz,
reset => reset,
time_base_50_ms => time_base_50_ms,
npc_enables => npcs_enabled,
npc_assigned_positions => npc_target_positions,
npc_positions => npc_positions,
sprites_enabled => sprites_enabled,
sprite_collisions => sprite_collisions,
sprites_positions => sprite_positions,
input_buttons => in_buttons,
game_state => game_state,
debug_bits => debug_bits,
text_mode_strings => text_mode_strings
);
----------------------------------------------------------------------------
-- Section 2) Instantiate the NPC engine. This entity receives low-level
-- game data, and updates the NPC positions.
npc: entity work.npcs_engine
generic map (
NPC_DEFINITIONS => make_npcs_initial_values(GAME_NPCS)
) port map (
clock => clock_50_Mhz,
reset => reset,
time_base => time_base_50_ms,
npc_enables => npcs_enabled,
npc_target_positions => npc_target_positions,
npc_positions => npc_positions
);
----------------------------------------------------------------------------
-- Section 3) Instantiate the game engine. While game logic performs
-- functions that are more related with the game itself, the game engine
-- performs basic functions such as calculating sprite collisions and
-- rendering the video output.
----------------------------------------------------------------------------
engine: entity work.game_engine
generic map (
SPRITES_INITIAL_VALUES => make_sprites_initial_values(GAME_SPRITES),
SPRITES_COLLISION_QUERY => make_sprites_collision_query(GAME_COLLISIONS)
) port map (
clock_50MHz => clock_50_Mhz,
reset => reset,
sprites_enabled => sprites_enabled,
sprites_coordinates => sprite_positions,
sprite_collisions_results => sprite_collisions,
elapsed_time => elapsed_time,
time_base_50_ms => time_base_50_ms,
game_state => game_state,
background_bitmap => background_bitmap,
vga_clock_in => vga_clock_in,
vga_signals => vga_output_signals,
text_mode_strings => text_mode_strings
);
----------------------------------------------------------------------------
-- Section 4) Select a background bitmap based on current game state
----------------------------------------------------------------------------
background_bitmap <= (others => (others => PC_BLACK));
----------------------------------------------------------------------------
-- Section 5) Convert signals between std_logic and custom data types.
-- Internally, we use custom types for better abstraction; at the interface,
-- we use std_logic for better portability and easier instantiation.
----------------------------------------------------------------------------
-- Connect each pushbutton to the corresponding game input function
in_buttons <= (
up => input_buttons(3),
down => input_buttons(2),
left => input_buttons(1),
right => input_buttons(0),
fire => input_switches(0)
);
-- Connect each VGA output signal to the corresponding VGA pin or port
vga_clock_out <= vga_output_signals.vga_clock_out;
vga_blank <= vga_output_signals.blank;
vga_n_hsync <= vga_output_signals.hsync;
vga_n_vsync <= vga_output_signals.vsync;
vga_n_sync <= vga_output_signals.sync;
vga_red <= vga_output_signals.red;
vga_green <= vga_output_signals.green;
vga_blue <= vga_output_signals.blue;
end; | unlicense | b04c899025ca8f1b8b3cfdb549711c76 | 0.588335 | 4.428973 | false | false | false | false |
wltr/common-vhdl | generic/reset_generator/src/rtl/reset_generator.vhd | 1 | 1,719 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Activate reset asynchronously and deactivate it synchronously.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity reset_generator is
generic (
-- Number of delay stages
num_delay_g : positive := 4;
-- Reset active state
active_g : std_ulogic := '0');
port (
-- Clock
clk_i : in std_ulogic;
-- Asynchronous reset input
rst_asy_i : in std_ulogic;
-- Reset output
rst_o : out std_ulogic);
end entity reset_generator;
architecture rtl of reset_generator is
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal rst : std_ulogic_vector(num_delay_g - 1 downto 0) := (others => active_g);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
rst_o <= rst(rst'high);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_i) is
begin -- process regs
if rst_asy_i = active_g then
rst <= (others => active_g);
elsif rising_edge(clk_i) then
rst <= rst(rst'high - 1 downto rst'low) & (not active_g);
end if;
end process regs;
end architecture rtl;
| lgpl-2.1 | 2b9bc7d70e22b29d875fe6005f3e815e | 0.399651 | 5.289231 | false | false | false | false |
ricardo-jasinski/vhdl-game-engine | hdl/implementation/engine/game_engine.vhd | 1 | 2,613 | library ieee;
use ieee.std_logic_1164.all;
use work.graphics_types_pkg.all;
use work.sprites_pkg.all;
use work.game_state_pkg.all;
use work.vga_pkg.all;
use work.basic_types_pkg.all;
use work.text_mode_pkg.all;
-- The game engine handles all operations that are independent from the game.
-- The entity cooperates with game_logic in order to make most of the game
-- work automatically, from the initial definitions provided by th designer.
--
-- Missing/wanted features:
-- * sprite movement (done!)
-- * sprite animation
-- * sprite collision (done!)
-- * named sprites (done!)
-- * transparency (done!)
-- * background (done!)
-- * scroll
-- * enable/disable each sprite
-- * zoom factor (done!)
-- * user input (done!)
-- * text output
entity game_engine is
generic (
SPRITES_INITIAL_VALUES: sprites_array_type;
SPRITES_COLLISION_QUERY: sprite_collision_query_type
);
port (
-- system clock used for all user logic
clock_50MHz: in std_logic;
-- synchronous reset for all user logic
reset: in std_logic;
sprites_coordinates: in point_array_type(SPRITES_INITIAL_VALUES'range);
sprites_enabled: in bool_vector;
sprite_collisions_results: out bool_vector;
elapsed_time: out integer range 0 to 1000;
time_base_50_ms: out std_logic;
game_state: in game_state_type;
background_bitmap: in paletted_bitmap_type;
text_mode_strings: in text_mode_strings_type;
vga_clock_in: in std_logic;
vga_signals: out vga_output_signals_type
);
end;
architecture rtl of game_engine is
begin
system_timer: entity work.system_timing
port map(
clock_50MHz => clock_50MHz,
reset => reset,
time_base_50_ms_out => time_base_50_ms,
elapsed_time_out => elapsed_time
);
vdp: entity work.video_engine
generic map (
SPRITES_INITIAL_VALUES => SPRITES_INITIAL_VALUES,
SPRITES_COLLISION_QUERY => SPRITES_COLLISION_QUERY
) port map(
clock_50MHz => clock_50MHz,
reset => reset,
vga_clock_in => vga_clock_in,
vga_signals => vga_signals,
sprites_coordinates => sprites_coordinates,
sprites_enabled => sprites_enabled,
sprite_collisions_results => sprite_collisions_results,
background_bitmap => background_bitmap,
text_mode_strings => text_mode_strings
);
end; | unlicense | 8ae0cfe9c02333d803e67e712e4d20e5 | 0.607348 | 3.722222 | false | false | false | false |
wltr/common-vhdl | dsp/ads1281_filter/src/rtl/ads1281_filter/ads1281_filter_coefficients.vhd | 1 | 7,389 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2014 Johannes Walter <[email protected]>
--
-- Description:
-- Generate FIR filter coefficients on the fly.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.lfsr_pkg.all;
entity ads1281_filter_coefficients is
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Compute next coefficient
start_i : in std_ulogic;
next_i : in std_ulogic;
-- Coefficient
coeff_o : out unsigned(23 downto 0);
coeff_en_o : out std_ulogic;
-- Control flags
done_o : out std_ulogic);
end entity ads1281_filter_coefficients;
architecture rtl of ads1281_filter_coefficients is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- Filter length
constant filter_len_c : natural := 2000;
-- LFSR counter bit length
constant len_c : natural := lfsr_length(filter_len_c);
-- LFSR counter initial value
constant seed_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_seed(len_c);
-- LFSR counter maximum value
constant max_c : std_ulogic_vector(len_c - 1 downto 0) := lfsr_shift(seed_c, filter_len_c - 10);
type state_t is (IDLE, ACC_1, ACC_2, ACC_3_1, ACC_3_2, ACC_4_1, ACC_4_2, ACC_4_3);
type reg_t is record
state : state_t;
lfsr : std_ulogic_vector(len_c - 1 downto 0);
carry : std_ulogic;
acc_1 : signed(1 downto 0);
acc_2 : signed(8 downto 0);
acc_3 : signed(15 downto 0);
acc_4 : unsigned(23 downto 0);
en : std_ulogic;
done : std_ulogic;
end record reg_t;
constant init_c : reg_t := (
state => IDLE,
lfsr => seed_c,
carry => '0',
acc_1 => (others => '0'),
acc_2 => (others => '0'),
acc_3 => (others => '0'),
acc_4 => (others => '0'),
en => '0',
done => '0');
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
signal root : signed(1 downto 0);
signal a : unsigned(9 downto 0);
signal b : unsigned(9 downto 0);
signal y : unsigned(9 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
coeff_o <= reg.acc_4;
coeff_en_o <= reg.en;
done_o <= reg.done;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Shared adder: 3rd accumulator + 2nd accumulator (split in 2 parts)
-- and 4th accumulator + 3rd accumulator (split in 3 parts)
y <= a + b;
------------------------------------------------------------------------------
-- Instances
------------------------------------------------------------------------------
ads1281_filter_roots : entity work.ads1281_filter_roots
generic map (
seed_g => seed_c)
port map (
clk_i => clk_i,
rst_asy_n_i => rst_asy_n_i,
rst_syn_i => rst_syn_i,
lfsr_i => reg.lfsr,
root_o => root);
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
comb : process(reg, next_i, start_i, root, y) is
begin -- process comb
-- Defaults
next_reg <= reg;
a <= (others => '0');
b <= (others => '0');
next_reg.en <= '0';
next_reg.done <= '0';
-- Save carry of shared adder for consecutive states
next_reg.carry <= y(y'high);
case reg.state is
when IDLE => null;
when ACC_1 =>
if next_i = '1' then
-- Save value for 1st accumulator
next_reg.acc_1 <= reg.acc_1 + root;
next_reg.state <= ACC_2;
end if;
when ACC_2 =>
-- Save value for 2nd accumulator
next_reg.acc_2 <= reg.acc_2 + reg.acc_1;
next_reg.state <= ACC_3_1;
when ACC_3_1 =>
a <= '0' & unsigned(reg.acc_3(7 downto 0)) & '0';
b <= '0' & unsigned(reg.acc_2(7 downto 0)) & '0';
-- Save 1st partial result for 3rd accumulator
next_reg.acc_3(7 downto 0) <= signed(y(8 downto 1));
next_reg.state <= ACC_3_2;
when ACC_3_2 =>
a <= '0' & unsigned(reg.acc_3(15 downto 8)) & reg.carry;
b <= (8 downto 0 => reg.acc_2(reg.acc_2'high)) & '1';
-- Save 2nd partial result for 3rd accumulator
next_reg.acc_3(15 downto 8) <= signed(y(8 downto 1));
next_reg.state <= ACC_4_1;
when ACC_4_1 =>
a <= '0' & unsigned(reg.acc_4(7 downto 0)) & '0';
b <= '0' & unsigned(reg.acc_3(7 downto 0)) & '0';
-- Save 1st partial result for 4th accumulator
next_reg.acc_4(7 downto 0) <= y(8 downto 1);
next_reg.state <= ACC_4_2;
when ACC_4_2 =>
a <= '0' & unsigned(reg.acc_4(15 downto 8)) & reg.carry;
b <= '0' & unsigned(reg.acc_3(15 downto 8)) & '1';
-- Save 2nd partial result for 4th accumulator
next_reg.acc_4(15 downto 8) <= y(8 downto 1);
next_reg.state <= ACC_4_3;
when ACC_4_3 =>
a <= '0' & unsigned(reg.acc_4(23 downto 16)) & reg.carry;
b <= (8 downto 0 => reg.acc_3(reg.acc_3'high)) & '1';
-- Save 3rd partial result for 4th accumulator
next_reg.acc_4(23 downto 16) <= y(8 downto 1);
next_reg.state <= ACC_1;
if reg.lfsr = max_c then
-- Reset calculation cycle and wait
next_reg <= init_c;
-- Emit strobe when filter cycle is done
next_reg.done <= '1';
else
next_reg.lfsr <= lfsr_shift(reg.lfsr);
end if;
next_reg.en <= '1';
end case;
-- Start the next calculation cycle
if start_i = '1' then
next_reg <= init_c;
next_reg.state <= ACC_1;
end if;
end process comb;
end architecture rtl;
| lgpl-2.1 | 12eeff10f6cff10661327a46e0dae1fa | 0.426174 | 3.989741 | false | false | false | false |
lerwys/GitTest | hdl/modules/wb_position_calc/position_calc_core_pkg.vhd | 1 | 5,759 | ------------------------------------------------------------------------------
-- Title : Wishbone FMC516 ADC Interface
------------------------------------------------------------------------------
-- Author : Lucas Maziero Russo
-- Company : CNPEM LNLS-DIG
-- Created : 2013-12-07
-- Platform : FPGA-generic
-------------------------------------------------------------------------------
-- Description: General definitions package for position calc core
-------------------------------------------------------------------------------
-- Copyright (c) 2012 CNPEM
-- Licensed under GNU Lesser General Public License (LGPL) v3.0
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2013-12-07 1.0 lucas.russo Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
package position_calc_core_pkg is
-------------------------------------------------------------------------------
-- Components Declaration
-------------------------------------------------------------------------------
component position_calc_counters_single
generic (
g_cntr_size : natural := 16
);
port (
fs_clk2x_i : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
fs_rst2x_n_i : in std_logic;
-- Clock enable
ce_i : in std_logic;
-- Error inputs (one clock cycle long)
err1_i : in std_logic;
-- Counter clear
cntr_clr_i : in std_logic;
-- Output counter
cntr_o : out std_logic_vector(g_cntr_size-1 downto 0)
);
end component;
component position_calc_counters
generic (
g_cntr_size : natural := 16
);
port (
fs_clk2x_i : in std_logic; -- clock period = 4.44116091946435 ns (225.16635135135124 Mhz)
fs_rst2x_n_i : in std_logic;
-- Clock enables for various rates
tbt_ce_i : in std_logic;
fofb_ce_i : in std_logic;
monit_cic_ce_i : in std_logic;
monit_cfir_ce_i : in std_logic;
monit_pfir_ce_i : in std_logic;
monit_01_ce_i : in std_logic;
tbt_decim_q_ch01_incorrect_i : in std_logic;
tbt_decim_q_ch23_incorrect_i : in std_logic;
tbt_decim_err_clr_i : in std_logic;
fofb_decim_q_ch01_missing_i : in std_logic;
fofb_decim_q_ch23_missing_i : in std_logic;
fofb_decim_err_clr_i : in std_logic;
monit_cic_unexpected_i : in std_logic;
monit_cfir_incorrect_i : in std_logic;
monit_part1_err_clr_i : in std_logic;
monit_pfir_incorrect_i : in std_logic;
monit_pos_1_incorrect_i : in std_logic;
monit_part2_err_clr_i : in std_logic;
tbt_incorrect_ctnr_ch01_o : out std_logic_vector(g_cntr_size-1 downto 0);
tbt_incorrect_ctnr_ch23_o : out std_logic_vector(g_cntr_size-1 downto 0);
fofb_incorrect_ctnr_ch01_o : out std_logic_vector(g_cntr_size-1 downto 0);
fofb_incorrect_ctnr_ch23_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_cic_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_cfir_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_pfir_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0);
monit_01_incorrect_ctnr_o : out std_logic_vector(g_cntr_size-1 downto 0)
);
end component;
--------------------------------------------------------------------
-- SDB Devices Structures
--------------------------------------------------------------------
constant c_xwb_bpm_swap_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"12897592",
version => x"00000001",
date => x"20130703",
name => "LNLS_BPM_SWAP ")));
constant c_xwb_pos_calc_core_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 8/16/32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"1bafbf1e",
version => x"00000001",
date => x"20130703",
name => "LNLS_POS_CALC_REGS ")));
end position_calc_core_pkg;
| lgpl-3.0 | a488888069bc1206b0d3c32614607dff | 0.432367 | 4.228341 | false | false | false | false |
wltr/common-vhdl | generic/mem_data_triplicator/src/rtl/mem_data_triplicator/mem_data_triplicator_rd.vhd | 1 | 5,326 | --------------------------------------------------------------------------------
-- LGPL v2.1, Copyright (c) 2013 Johannes Walter <[email protected]>
--
-- Description:
-- Perform majority voting on read.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity mem_data_triplicator_rd is
generic (
-- Memory data width
width_g : positive := 16);
port (
-- Clock and resets
clk_i : in std_ulogic;
rst_asy_n_i : in std_ulogic;
rst_syn_i : in std_ulogic;
-- Interface
rd_en_i : in std_ulogic;
data_o : out std_ulogic_vector(width_g - 1 downto 0);
data_en_o : out std_ulogic;
busy_o : out std_ulogic;
voted_o : out std_ulogic;
-- Memory interface
mem_rd_en_o : out std_ulogic;
mem_data_i : in std_ulogic_vector(width_g - 1 downto 0);
mem_data_en_i : in std_ulogic);
end entity mem_data_triplicator_rd;
architecture rtl of mem_data_triplicator_rd is
------------------------------------------------------------------------------
-- Types and Constants
------------------------------------------------------------------------------
-- Data type to store the three data outputs for comparison
type data_t is array (0 to 2) of std_ulogic_vector(width_g - 1 downto 0);
-- FSM states
type state_t is (IDLE, A_READY, B_READY, C_READY, CHECK);
-- FSM registers
type reg_t is record
state : state_t;
mem_rd_en : std_ulogic;
data : std_ulogic_vector(width_g - 1 downto 0);
data_en : std_ulogic;
busy : std_ulogic;
err : std_ulogic;
check : data_t;
end record reg_t;
-- FSM initial state
constant init_c : reg_t := (
state => IDLE,
mem_rd_en => '0',
data => (others => '0'),
data_en => '0',
busy => '0',
err => '0',
check => (others => (others => '0')));
------------------------------------------------------------------------------
-- Internal Registers
------------------------------------------------------------------------------
signal reg : reg_t;
------------------------------------------------------------------------------
-- Internal Wires
------------------------------------------------------------------------------
signal next_reg : reg_t;
signal corr : std_ulogic_vector(width_g - 1 downto 0);
signal err : std_ulogic_vector(width_g - 1 downto 0);
begin -- architecture rtl
------------------------------------------------------------------------------
-- Outputs
------------------------------------------------------------------------------
data_o <= reg.data;
data_en_o <= reg.data_en;
busy_o <= reg.busy;
voted_o <= reg.err;
mem_rd_en_o <= reg.mem_rd_en;
------------------------------------------------------------------------------
-- Signal Assignments
------------------------------------------------------------------------------
-- Determine correct data
corr <= (reg.check(0) and reg.check(1)) or (reg.check(1) and reg.check(2)) or (reg.check(0) and reg.check(2));
-- Check for errors
err <= (reg.check(0) xor reg.check(1)) or (reg.check(1) xor reg.check(2)) or (reg.check(0) xor reg.check(2));
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
-- FSM registering
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
------------------------------------------------------------------------------
-- Combinatorics
------------------------------------------------------------------------------
-- FSM combinatorics
comb : process(reg, rd_en_i, mem_data_i, mem_data_en_i, corr, err) is
begin -- process comb
-- Defaults
next_reg <= reg;
next_reg.data_en <= init_c.data_en;
next_reg.mem_rd_en <= init_c.mem_rd_en;
next_reg.err <= init_c.err;
case reg.state is
when IDLE =>
if rd_en_i = '1' then
next_reg.mem_rd_en <= '1';
next_reg.busy <= '1';
next_reg.state <= A_READY;
end if;
when A_READY =>
if mem_data_en_i = '1' then
next_reg.check(0) <= mem_data_i;
next_reg.mem_rd_en <= '1';
next_reg.state <= B_READY;
end if;
when B_READY =>
if mem_data_en_i = '1' then
next_reg.check(1) <= mem_data_i;
next_reg.mem_rd_en <= '1';
next_reg.state <= C_READY;
end if;
when C_READY =>
if mem_data_en_i = '1' then
next_reg.check(2) <= mem_data_i;
next_reg.state <= CHECK;
end if;
when CHECK =>
next_reg <= init_c;
next_reg.data <= corr;
next_reg.data_en <= '1';
if err /= (err'range => '0') then
next_reg.err <= '1';
end if;
end case;
end process comb;
end architecture rtl;
| lgpl-2.1 | d673d9d35f249a71f62710deda76d182 | 0.414007 | 3.965748 | false | false | false | false |
lerwys/GitTest | models/blackboxes/lut_sweep.vhd | 2 | 2,231 | -------------------------------------------------------------------------------
-- Title : Look-up table sweeper
-- Project :
-------------------------------------------------------------------------------
-- File : lut_sweep.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Tool for sweeping through look-up table addresses
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
-------------------------------------------------------------------------------
entity lut_sweep is
generic (
g_bus_size : natural := 8;
g_first_address : natural := 0;
g_last_address : natural := 147;
g_sweep_mode : string := "sawtooth"
);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(g_bus_size-1 downto 0));
end entity lut_sweep;
-------------------------------------------------------------------------------
architecture str of lut_sweep is
begin -- architecture str
counting : process(clk_i)
variable count : natural := 0;
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
count := 0;
elsif ce_i = '1' then
if count = g_last_address then
count := g_first_address;
else
count := count + 1;
end if; --count = last_address
address_o <= std_logic_vector(to_unsigned(count, g_bus_size));
end if; -- reset
end if; -- rising_edge
end process counting;
end architecture str;
-------------------------------------------------------------------------------
| lgpl-3.0 | 3158d7ba80bf7c52f487b3b825737b25 | 0.397131 | 4.562372 | false | false | false | false |
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