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sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/arith/int_mul.vhd | 1 | 9,049 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity IntMul is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_ena : in std_logic; -- Enable bit
i_unsigned : in std_logic; -- Unsigned operands
i_hsu : in std_logic; -- MULHSU instruction signed * unsigned
i_high : in std_logic; -- High multiplied bits [127:64]
i_rv32 : in std_logic; -- 32-bits operands enable
i_a1 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
i_a2 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
o_res : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Result
o_valid : out std_logic; -- Result is valid
o_busy : out std_logic -- Multiclock instruction under processing
);
end;
architecture arch_IntMul of IntMul is
type Level0Type is array (0 to 31) of std_logic_vector(65 downto 0);
type Level1Type is array (0 to 15) of std_logic_vector(68 downto 0);
type Level2Type is array (0 to 7) of std_logic_vector(73 downto 0);
type Level3Type is array (0 to 3) of std_logic_vector(82 downto 0);
type Level4Type is array (0 to 1) of std_logic_vector(99 downto 0);
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(3 downto 0);
a1 : std_logic_vector(RISCV_ARCH-1 downto 0);
a2 : std_logic_vector(RISCV_ARCH-1 downto 0);
unsign : std_logic;
high : std_logic;
rv32 : std_logic;
zero : std_logic;
inv : std_logic;
result : std_logic_vector(127 downto 0);
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), '0', -- a1, a2, unsign
'0', '0', -- high, rv32,
'0', '0', -- zero, inv
(others => '0') -- result
);
-- Some synthezators crush when try to initialize two-dimensional array
-- so exclude from register type and avoid using (others => (others =>))
signal r_lvl1, rin_lvl1 : Level1Type;
signal r_lvl3, rin_lvl3 : Level3Type;
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_ena, i_unsigned, i_hsu, i_high, i_rv32, i_a1, i_a2,
r, r_lvl1, r_lvl3)
variable v : RegistersType;
variable v_lvl1 : Level1Type;
variable v_lvl3 : Level3Type;
variable wb_mux_lvl0 : std_logic_vector(1 downto 0);
variable wb_lvl0 : Level0Type;
variable wb_lvl2 : Level2Type;
variable wb_lvl4 : Level4Type;
variable wb_lvl5 : std_logic_vector(127 downto 0);
variable wb_res32 : std_logic_vector(127 downto 0);
variable wb_res : std_logic_vector(RISCV_ARCH-1 downto 0);
variable vb_a1s : std_logic_vector(63 downto 0);
variable vb_a2s : std_logic_vector(63 downto 0);
variable v_a1s_nzero : std_logic;
variable v_a2s_nzero : std_logic;
begin
v := r;
v_a1s_nzero := or_reduce(i_a1(62 downto 0));
if v_a1s_nzero = '1' and i_a1(63) = '1' then
vb_a1s := (not i_a1) + 1;
else
vb_a1s := i_a1;
end if;
v_a2s_nzero := or_reduce(i_a2(62 downto 0));
if v_a2s_nzero = '1' and i_a2(63) = '1' then
vb_a2s := (not i_a2) + 1;
else
vb_a2s := i_a2;
end if;
v_lvl1 := r_lvl1;
v_lvl3 := r_lvl3;
for i in 0 to 7 loop
wb_lvl2(i) := (others => '0');
end loop;
for i in 0 to 1 loop
wb_lvl4(i) := (others => '0');
end loop;
wb_lvl5 := (others => '0');
wb_res32 := (others => '0');
v.ena := r.ena(2 downto 0) & (i_ena and not r.busy);
if i_ena = '1' then
v.busy := '1';
v.inv := '0';
v.zero := '0';
if i_rv32 = '1' then
v.a1(31 downto 0) := i_a1(31 downto 0);
if (not i_unsigned and i_a1(31)) = '1' then
v.a1(63 downto 32) := (others => '1');
end if;
v.a2(31 downto 0) := i_a2(31 downto 0);
if (not i_unsigned and i_a2(31)) = '1' then
v.a2(63 downto 32) := (others => '1');
end if;
elsif i_high = '1' then
if i_hsu = '1' then
v.zero := (not v_a1s_nzero) or (not or_reduce(i_a2));
v.inv := i_a1(63);
v.a1 := vb_a1s;
v.a2 := i_a2;
elsif i_unsigned = '1' then
v.a1 := i_a1;
v.a2 := i_a2;
else
v.zero := (not v_a1s_nzero) or (not v_a2s_nzero);
v.inv := i_a1(63) xor i_a2(63);
v.a1 := vb_a1s;
v.a2 := vb_a2s;
end if;
else
v.a1 := i_a1;
v.a2 := i_a2;
end if;
v.rv32 := i_rv32;
v.unsign := i_unsigned;
v.high := i_high;
end if;
if r.ena(0) = '1' then
for i in 0 to 31 loop
wb_mux_lvl0 := r.a2(2*i + 1 downto 2*i);
if wb_mux_lvl0 = "00" then
wb_lvl0(i) := (others => '0');
elsif wb_mux_lvl0 = "01" then
wb_lvl0(i) := ("00" & r.a1);
elsif wb_mux_lvl0 = "10" then
wb_lvl0(i) := ("0" & r.a1 & "0");
else
wb_lvl0(i) := ("00" & r.a1) + ("0" & r.a1 & "0");
end if;
end loop;
for i in 0 to 15 loop
v_lvl1(i) := ("0" & wb_lvl0(2*i + 1) & "00")
+ ("000" & wb_lvl0(2*i));
end loop;
end if;
if r.ena(1) = '1' then
for i in 0 to 7 loop
wb_lvl2(i) := ("0" & r_lvl1(2*i + 1) & "0000")
+ ("00000" & r_lvl1(2*i));
end loop;
for i in 0 to 3 loop
v_lvl3(i) := ("0" & wb_lvl2(2*i + 1) & "00000000")
+ ("000000000" & wb_lvl2(2*i));
end loop;
end if;
if r.ena(2) = '1' then
v.busy := '0';
for i in 0 to 1 loop
wb_lvl4(i) := ("0" & r_lvl3(2*i + 1) & "0000000000000000")
+ ("00000000000000000" & r_lvl3(2*i));
end loop;
wb_lvl5 := (wb_lvl4(1)(95 downto 0) & X"00000000")
+ (X"0000000" & wb_lvl4(0));
if r.rv32 = '1' then
wb_res32(31 downto 0) := wb_lvl5(31 downto 0);
if r.unsign = '1' or wb_lvl5(31) = '0' then
wb_res32(127 downto 32) := (others => '0');
else
wb_res32(127 downto 32) := (others => '1');
end if;
v.result := wb_res32;
elsif r.high = '1' then
v.result(63 downto 0) := wb_lvl5(63 downto 0); -- ignore low part
if r.zero = '1' then
v.result(127 downto 64) := (others => '0');
elsif r.inv = '1' then
v.result(127 downto 64) := not wb_lvl5(127 downto 64);
else
v.result(127 downto 64) := wb_lvl5(127 downto 64);
end if;
else
v.result := wb_lvl5;
end if;
end if;
wb_res := r.result(63 downto 0);
if r.high = '1' then
wb_res := r.result(127 downto 64); --! not tested yet
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
for i in 0 to 15 loop
v_lvl1(i) := (others => '0');
end loop;
for i in 0 to 3 loop
v_lvl3(i) := (others => '0');
end loop;
end if;
o_res <= wb_res;
o_valid <= r.ena(3);
o_busy <= r.busy;
rin <= v;
rin_lvl1 <= v_lvl1;
rin_lvl3 <= v_lvl3;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
for i in 0 to 15 loop
r_lvl1(i) <= (others => '0');
end loop;
for i in 0 to 3 loop
r_lvl3(i) <= (others => '0');
end loop;
elsif rising_edge(i_clk) then
r <= rin;
r_lvl1 <= rin_lvl1;
r_lvl3 <= rin_lvl3;
end if;
end process;
end;
| apache-2.0 | a198a806eab0c9286f818576204f02e9 | 0.495966 | 3.124655 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/ram32_tech.vhd | 1 | 2,199 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Technology specific RAM selector
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity Ram32_tech is
generic (
generic_tech : integer := 0;
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end;
architecture rtl of Ram32_tech is
component Ram32_inferred
generic (
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
-- micron 180 nm tech
component micron180_syncram
generic (abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
-- TODO: add there other ASIC components
begin
genmem0 : if generic_tech = inferred or is_fpga(generic_tech) /= 0 generate
ram_infer : Ram32_inferred generic map
(
generic_abits => generic_abits
) port map
(
i_clk,
i_address,
i_wr_ena,
i_data,
o_data
);
end generate;
genmem1 : if generic_tech = mikron180 generate
x0 : micron180_syncram
generic map (generic_abits, 32)
port map (i_clk, i_address, i_data, o_data, '1', i_wr_ena);
end generate;
end;
| apache-2.0 | 525e3ad6d28d5559fa351a00b824694a | 0.572533 | 3.581433 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/sim/asic_top.vhd | 1 | 12,600 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
-- "Virtual" memory banks
use techmap.types_mem.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
entity asic_top is port
(
--! Input reset. Active HIGH.
i_rst : in std_logic;
--! Differential clock (LVDS) positive/negaive signal.
i_sclk_p : in std_logic;
i_sclk_n : in std_logic;
--! GPIO: [11:4] LEDs; [3:0] DIP switch
io_gpio : inout std_logic_vector(11 downto 0);
--! Timers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 TAP (debug port) signals: DO NOT SUPPORT FIRMWARE OUTPUT!
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! SPI Flash/ext OTP
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
-- OTP power
io_otp_gnd : inout std_logic;
io_otp_vdd : inout std_logic;
io_otp_vdd18 : inout std_logic;
io_otp_upp : inout std_logic;
--! Ethernet MAC PHY interface signals
i_gmiiclk_p : in std_ulogic;
i_gmiiclk_n : in std_ulogic;
o_egtx_clk : out std_ulogic;
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
io_emdio : inout std_logic;
o_erstn : out std_ulogic
);
end asic_top;
architecture arch_asic_top of asic_top is
component riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
signal ib_rst : std_logic;
signal ib_clk_tcxo : std_logic;
signal ib_sclk_n : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
signal ob_pwm : std_logic_vector(1 downto 0);
signal ib_uart1_rd : std_logic;
signal ob_uart1_td : std_logic;
signal ib_uart2_rd : std_logic;
signal ob_uart2_td : std_logic;
signal ib_flash_si : std_logic;
signal ob_flash_so : std_logic;
signal ob_flash_sck : std_logic;
signal ob_flash_csn : std_logic;
--! JTAG signals:
signal ib_jtag_tck : std_logic;
signal ib_jtag_ntrst : std_logic;
signal ib_jtag_tms : std_logic;
signal ib_jtag_tdi : std_logic;
signal ob_jtag_tdo : std_logic;
signal ob_jtag_vref : std_logic;
signal ib_gmiiclk : std_logic;
signal ib_eth_mdio : std_logic;
signal ob_eth_mdio : std_logic;
signal ob_eth_mdio_oe : std_logic;
signal w_eth_gtx_clk : std_logic;
signal w_eth_gtx_clk_90 : std_logic;
signal w_ext_reset : std_ulogic; -- External system reset or PLL unlcoked. MUST NOT USED BY DEVICES.
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal w_clk_bus : std_ulogic; -- bus clock from the internal PLL (100MHz virtex6/40MHz Spartan6)
signal w_pll_lock : std_ulogic; -- PLL status signal. 0=Unlocked; 1=locked.
signal wb_otp_wdata : std_logic_vector(15 downto 0);
signal wb_otp_addr : std_logic_vector(11 downto 0);
signal w_otp_we : std_logic;
signal w_otp_re : std_logic;
signal wb_otp_rdata : std_logic_vector(15 downto 0);
begin
--! PAD buffers:
irst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_rst, i_rst);
iclk0 : idsbuf_tech generic map (CFG_PADTECH) port map (
i_sclk_p, i_sclk_n, ib_clk_tcxo);
ird1 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart1_rd, i_uart1_rd);
otd1 : obuf_tech generic map(CFG_PADTECH) port map (o_uart1_td, ob_uart1_td);
ird2 : ibuf_tech generic map(CFG_PADTECH) port map (ib_uart2_rd, i_uart2_rd);
otd2 : obuf_tech generic map(CFG_PADTECH) port map (o_uart2_td, ob_uart2_td);
iflshsi : ibuf_tech generic map(CFG_PADTECH) port map (ib_flash_si, i_flash_si);
oflshso : obuf_tech generic map(CFG_PADTECH) port map (o_flash_so, ob_flash_so);
oflshsck : obuf_tech generic map(CFG_PADTECH) port map (o_flash_sck, ob_flash_sck);
oflshcsn : obuf_tech generic map(CFG_PADTECH) port map (o_flash_csn, ob_flash_csn);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(CFG_PADTECH)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
pwmx : for i in 0 to 1 generate
opwm0 : obuf_tech generic map(CFG_PADTECH) port map (o_pwm(i), ob_pwm(i));
end generate;
--! JTAG signals:
ijtck0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tck, i_jtag_tck);
ijtrst0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_ntrst, i_jtag_ntrst);
ijtms0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tms, i_jtag_tms);
ijtdi0 : ibuf_tech generic map(CFG_PADTECH) port map (ib_jtag_tdi, i_jtag_tdi);
ojtdo0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_tdo, ob_jtag_tdo);
ojvrf0 : obuf_tech generic map(CFG_PADTECH) port map (o_jtag_vref, ob_jtag_vref);
igbebuf0 : igdsbuf_tech generic map (CFG_PADTECH) port map (
i_gmiiclk_p, i_gmiiclk_n, ib_gmiiclk);
iomdio : iobuf_tech generic map(CFG_PADTECH)
port map (ib_eth_mdio, io_emdio, ob_eth_mdio, ob_eth_mdio_oe);
--! Gigabit clock phase rotator with buffers
clkrot90 : clkp90_tech generic map (
tech => CFG_FABTECH,
freq => 125000 -- KHz = 125 MHz
) port map (
i_rst => ib_rst,
i_clk => ib_gmiiclk,
o_clk => w_eth_gtx_clk,
o_clkp90 => w_eth_gtx_clk_90,
o_clk2x => open, -- used in gbe 'io_ref'
o_lock => open
);
o_egtx_clk <= w_eth_gtx_clk;
------------------------------------
-- @brief Internal PLL device instance.
pll0 : SysPLL_tech generic map (
tech => CFG_FABTECH
) port map (
i_reset => ib_rst,
i_clk_tcxo => ib_clk_tcxo,
o_clk_bus => w_clk_bus,
o_locked => w_pll_lock
);
w_ext_reset <= ib_rst or not w_pll_lock;
otp0 : otp_tech generic map (
memtech => CFG_MEMTECH
) port map (
clk => w_clk_bus, -- only for FPGA
i_we => w_otp_we,
i_re => w_otp_re,
i_addr => wb_otp_addr,
i_wdata => wb_otp_wdata,
o_rdata => wb_otp_rdata,
io_gnd => io_otp_gnd,
io_vdd => io_otp_vdd,
io_vdd18 => io_otp_vdd18,
io_upp => io_otp_upp
);
soc0 : riscv_soc port map
(
i_rst => w_ext_reset,
i_clk => w_clk_bus,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GP Timers
o_pwm => ob_pwm,
--! JTAG signals:
i_jtag_tck => ib_jtag_tck,
i_jtag_ntrst => ib_jtag_ntrst,
i_jtag_tms => ib_jtag_tms,
i_jtag_tdi => ib_jtag_tdi,
o_jtag_tdo => ob_jtag_tdo,
o_jtag_vref => ob_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => ib_uart1_rd,
o_uart1_td => ob_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => ib_uart2_rd,
o_uart2_td => ob_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => ib_flash_si,
o_flash_so => ob_flash_so,
o_flash_sck => ob_flash_sck,
o_flash_csn => ob_flash_csn,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => wb_otp_rdata,
o_otp_d => wb_otp_wdata,
o_otp_a => wb_otp_addr,
o_otp_we => w_otp_we,
o_otp_re => w_otp_re,
--! Ethernet MAC PHY interface signals
i_etx_clk => i_etx_clk,
i_erx_clk => i_erx_clk,
i_erxd => i_erxd,
i_erx_dv => i_erx_dv,
i_erx_er => i_erx_er,
i_erx_col => i_erx_col,
i_erx_crs => i_erx_crs,
i_emdint => i_emdint,
o_etxd => o_etxd,
o_etx_en => o_etx_en,
o_etx_er => o_etx_er,
o_emdc => o_emdc,
i_eth_mdio => ib_eth_mdio,
o_eth_mdio => ob_eth_mdio,
o_eth_mdio_oe => ob_eth_mdio_oe,
i_eth_gtx_clk => w_eth_gtx_clk,
i_eth_gtx_clk_90 => w_eth_gtx_clk_90,
o_erstn => o_erstn,
-- GNSS Sub-system signals:
i_clk_adc => '0',
i_gps_I => "00",
i_gps_Q => "00",
i_glo_I => "00",
i_glo_Q => "00",
o_pps => open,
i_gps_ld => '0',
i_glo_ld => '0',
o_max_sclk => open,
o_max_sdata => open,
o_max_ncs => open,
i_antext_stat => '0',
i_antext_detect => '0',
o_antext_ena => open,
o_antint_contr => open
);
end arch_asic_top;
| apache-2.0 | afca496aaa1286fa6e407314a1149c81 | 0.612063 | 2.798756 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/wr_logic_pkt_fifo.vhd | 19 | 31,831 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | 70b9a0514a6a57bd5349fee762084bef | 0.947158 | 1.841859 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_smple_sm.vhd | 1 | 16,883 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_smple_sm.vhd
-- Description: This entity contains the DMA Controller State Machine for
-- Simple DMA mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_smple_sm is
generic (
C_M_AXI_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_MICRO_DMA : integer range 0 to 1 := 0
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
run_stop : in std_logic ; --
keyhole : in std_logic ;
stop : in std_logic ; --
cmnd_idle : out std_logic ; --
sts_idle : out std_logic ; --
--
-- DataMover Status --
sts_received : in std_logic ; --
sts_received_clr : out std_logic ; --
--
-- DataMover Command --
cmnd_wr : out std_logic ; --
cmnd_data : out std_logic_vector --
((C_M_AXI_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
cmnd_pending : in std_logic ; --
--
-- Trasnfer Qualifiers --
xfer_length_wren : in std_logic ; --
xfer_address : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH-1 downto 0) ; --
xfer_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) --
);
end axi_dma_smple_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_smple_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Command Destination Stream Offset
constant CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_ADDR_WIDTH)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SMPL_STATE_TYPE is (
IDLE,
EXECUTE_XFER,
WAIT_STATUS
);
signal smpl_cs : SMPL_STATE_TYPE;
signal smpl_ns : SMPL_STATE_TYPE;
-- State Machine Signals
signal write_cmnd_cmb : std_logic := '0';
signal cmnd_wr_i : std_logic := '0';
signal sts_received_clr_cmb : std_logic := '0';
signal cmnds_queued : std_logic := '0';
signal cmd_dumb : std_logic_vector (31 downto 0) := (others => '0');
signal zeros : std_logic_vector (45 downto 0) := (others => '0');
signal burst_type : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Pass command write control out
cmnd_wr <= cmnd_wr_i;
burst_type <= '1' and (not keyhole);
-- 0 means fixed burst
-- 1 means increment burst
-------------------------------------------------------------------------------
-- MM2S Transfer State Machine
-------------------------------------------------------------------------------
MM2S_MACHINE : process(smpl_cs,
run_stop,
xfer_length_wren,
sts_received,
cmnd_pending,
cmnds_queued,
stop
)
begin
-- Default signal assignment
write_cmnd_cmb <= '0';
sts_received_clr_cmb <= '0';
cmnd_idle <= '0';
smpl_ns <= smpl_cs;
case smpl_cs is
-------------------------------------------------------------------
when IDLE =>
-- Running, no errors, and new length written,then execute
-- transfer
if( run_stop = '1' and xfer_length_wren = '1' and stop = '0'
and cmnds_queued = '0') then
smpl_ns <= EXECUTE_XFER;
else
cmnd_idle <= '1';
end if;
-------------------------------------------------------------------
when EXECUTE_XFER =>
-- error detected
if(stop = '1')then
smpl_ns <= IDLE;
-- Write another command if there is not one already pending
elsif(cmnd_pending = '0')then
write_cmnd_cmb <= '1';
smpl_ns <= WAIT_STATUS;
else
smpl_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- wait until desc update complete or error occurs
if(sts_received = '1' or stop = '1')then
sts_received_clr_cmb <= '1';
smpl_ns <= IDLE;
else
smpl_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
smpl_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
-------------------------------------------------------------------------------
-- register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
smpl_cs <= IDLE;
else
smpl_cs <= smpl_ns;
end if;
end if;
end process REGISTER_STATE;
-- Register state machine signals
REGISTER_STATE_SIGS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn ='0')then
sts_received_clr <= '0';
else
sts_received_clr <= sts_received_clr_cmb;
end if;
end if;
end process REGISTER_STATE_SIGS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- Key Hole Operation'1' -- Not Used
& PAD_VALUE
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to mm2s_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmnd_wr_i <= '0';
cmnd_data <= (others => '0');
-- SM issued a command write
elsif(write_cmnd_cmb = '1')then
cmnd_wr_i <= '1';
cmnd_data <= zeros
& cmd_dumb
& CMD_RSVD
-- Command Tag
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
& '0' -- Tag Not Used in Simple Mode
-- Command
& xfer_address -- Command Address
& '1' -- Command SOF
& '1' -- Command EOF
& CMD_DSA -- Stream Offset
& burst_type -- key Hole Operation '1' -- Not Used
& xfer_length;
else
cmnd_wr_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
-------------------------------------------------------------------------------
-- Flag indicating command being processed by Datamover
-------------------------------------------------------------------------------
-- count number of queued commands to keep track of what datamover is still
-- working on
CMD2STS_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or stop = '1')then
cmnds_queued <= '0';
elsif(cmnd_wr_i = '1')then
cmnds_queued <= '1';
elsif(sts_received = '1')then
cmnds_queued <= '0';
end if;
end if;
end process CMD2STS_COUNTER;
-- Indicate status is idle when no cmnd/sts queued
sts_idle <= '1' when cmnds_queued = '0'
else '0';
end implementation;
| mit | a4bb8158dfb7f390abb7ce767151a7db | 0.382337 | 5.447886 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/river_amba.vhd | 1 | 10,568 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief "River" CPU Top level with AXI4 interface.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
entity river_amba is
generic (
memtech : integer;
hartid : integer;
async_reset : boolean;
fpu_ena : boolean;
coherence_ena : boolean;
tracer_ena : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_msti : in axi4_l1_in_type;
o_msto : out axi4_l1_out_type;
i_dport : in dport_in_type;
o_dport : out dport_out_type;
i_ext_irq : in std_logic
);
end;
architecture arch_river_amba of river_amba is
type state_type is (
state_idle,
state_ar,
state_r,
state_aw,
state_w,
state_b
);
type snoopstate_type is (
snoop_idle,
snoop_ac_wait_accept,
snoop_cr,
snoop_cr_wait_accept,
snoop_cd,
snoop_cd_wait_accept
);
type RegistersType is record
state : state_type;
req_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
req_path : std_logic;
req_cached : std_logic_vector(3 downto 0);
req_wdata : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
req_wstrb : std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
req_size : std_logic_vector(2 downto 0);
req_prot : std_logic_vector(2 downto 0);
req_ar_snoop : std_logic_vector(3 downto 0);
req_aw_snoop : std_logic_vector(2 downto 0);
end record;
constant R_RESET : RegistersType := (
state_idle,
(others => '0'), -- req_addr
'0', -- req_path
(others => '0'), -- req_cached
(others => '0'), -- req_wdata
(others => '0'), -- req_wstrb
(others => '0'), -- req_size
(others => '0'), -- req_prot
(others => '0'), -- req_ar_snoop
(others => '0') -- req_aw_snoop
);
signal r, rin : RegistersType;
signal req_mem_ready_i : std_logic;
signal req_mem_path_o : std_logic;
signal req_mem_valid_o : std_logic;
signal req_mem_type_o : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
signal req_mem_addr_o : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal req_mem_strob_o : std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
signal req_mem_data_o : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
signal resp_mem_valid_i : std_logic;
signal resp_mem_load_fault_i : std_logic;
signal resp_mem_store_fault_i : std_logic;
-- D$ Snoop interface
signal req_snoop_valid_i : std_logic;
signal req_snoop_type_i : std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
signal req_snoop_ready_o : std_logic;
signal req_snoop_addr_i : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal resp_snoop_ready_i : std_logic;
signal resp_snoop_valid_o : std_logic;
signal resp_snoop_data_o : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
signal resp_snoop_flags_o : std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
begin
o_dport.available <= '1';
river0 : RiverTop generic map (
memtech => memtech,
hartid => hartid,
async_reset => async_reset,
fpu_ena => fpu_ena,
coherence_ena => coherence_ena,
tracer_ena => tracer_ena
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_req_mem_ready => req_mem_ready_i,
o_req_mem_path => req_mem_path_o,
o_req_mem_valid => req_mem_valid_o,
o_req_mem_type => req_mem_type_o,
o_req_mem_addr => req_mem_addr_o,
o_req_mem_strob => req_mem_strob_o,
o_req_mem_data => req_mem_data_o,
i_resp_mem_valid => resp_mem_valid_i,
i_resp_mem_path => r.req_path,
i_resp_mem_data => i_msti.r_data,
i_resp_mem_load_fault => resp_mem_load_fault_i,
i_resp_mem_store_fault => resp_mem_store_fault_i,
i_req_snoop_valid => req_snoop_valid_i,
i_req_snoop_type => req_snoop_type_i,
o_req_snoop_ready => req_snoop_ready_o,
i_req_snoop_addr => req_snoop_addr_i,
i_resp_snoop_ready => resp_snoop_ready_i,
o_resp_snoop_valid => resp_snoop_valid_o,
o_resp_snoop_data => resp_snoop_data_o,
o_resp_snoop_flags => resp_snoop_flags_o,
i_ext_irq => i_ext_irq,
i_dport_req_valid => i_dport.req_valid,
i_dport_write => i_dport.write,
i_dport_addr => i_dport.addr,
i_dport_wdata => i_dport.wdata,
o_dport_req_ready => o_dport.req_ready,
i_dport_resp_ready => i_dport.resp_ready,
o_dport_resp_valid => o_dport.resp_valid,
o_dport_rdata => o_dport.rdata,
o_halted => o_dport.halted
);
comb : process(i_nrst, req_mem_path_o, req_mem_valid_o, req_mem_type_o,
req_mem_addr_o, req_mem_strob_o, req_mem_data_o,
i_msti, r)
variable v : RegistersType;
variable v_resp_mem_valid : std_logic;
variable v_mem_er_load_fault : std_logic;
variable v_mem_er_store_fault : std_logic;
variable v_next_ready : std_logic;
variable vmsto : axi4_l1_out_type;
begin
v := r;
v_resp_mem_valid := '0';
v_mem_er_load_fault := '0';
v_mem_er_store_fault := '0';
v_next_ready := '0';
vmsto := axi4_l1_out_none;
vmsto.ar_bits.burst := "01"; -- INCR (possible any value)
vmsto.aw_bits.burst := "01"; -- INCR (possible any value)
case r.state is
when state_idle =>
v_next_ready := '1';
if req_mem_valid_o = '1' then
v.req_path := req_mem_path_o;
v.req_addr := req_mem_addr_o;
if req_mem_type_o(REQ_MEM_TYPE_CACHED) = '1' then
v.req_size := "101"; -- 32 Bytes
elsif req_mem_path_o = '1' then
v.req_size := "100"; -- 16 Bytes: Uncached Instruction
else
v.req_size := "011"; -- 8 Bytes: Uncached Data
end if;
-- [0] 0=Unpriv/1=Priv;
-- [1] 0=Secure/1=Non-secure;
-- [2] 0=Data/1=Instruction
v.req_prot := req_mem_path_o & "00";
if req_mem_type_o(REQ_MEM_TYPE_WRITE) = '0' then
v.state := state_ar;
v.req_wdata := (others => '0');
v.req_wstrb := (others => '0');
if req_mem_type_o(REQ_MEM_TYPE_CACHED) = '1' then
v.req_cached := ARCACHE_WRBACK_READ_ALLOCATE;
else
v.req_cached := ARCACHE_DEVICE_NON_BUFFERABLE;
end if;
--if coherence_ena then
-- v.req_ar_snoop := reqtype2arsnoop(req_mem_type_o);
--end if;
else
v.state := state_aw;
v.req_wdata := req_mem_data_o;
v.req_wstrb := req_mem_strob_o;
if req_mem_type_o(REQ_MEM_TYPE_CACHED) = '1' then
v.req_cached := AWCACHE_WRBACK_WRITE_ALLOCATE;
else
v.req_cached := AWCACHE_DEVICE_NON_BUFFERABLE;
end if;
--if coherence_ena then
-- v.req_aw_snoop := reqtype2awsnoop(req_mem_type_o);
--end if;
end if;
end if;
when state_ar =>
vmsto.ar_valid := '1';
vmsto.ar_bits.addr := r.req_addr;
vmsto.ar_bits.cache := r.req_cached;
vmsto.ar_bits.size := r.req_size;
vmsto.ar_bits.prot := r.req_prot;
vmsto.ar_snoop := r.req_ar_snoop;
if i_msti.ar_ready = '1' then
v.state := state_r;
end if;
when state_r =>
vmsto.r_ready := '1';
v_mem_er_load_fault := i_msti.r_resp(1);
v_resp_mem_valid := i_msti.r_valid;
-- r_valid and r_last always should be in the same time
if i_msti.r_valid = '1' and i_msti.r_last = '1' then
v.state := state_idle;
end if;
when state_aw =>
vmsto.aw_valid := '1';
vmsto.aw_bits.addr := r.req_addr;
vmsto.aw_bits.cache := r.req_cached;
vmsto.aw_bits.size := r.req_size;
vmsto.aw_bits.prot := r.req_prot;
--vmsto.aw_snoop := r.req_aw_snoop;
-- axi lite to simplify L2-cache
vmsto.w_valid := '1';
vmsto.w_last := '1';
vmsto.w_data := r.req_wdata;
vmsto.w_strb := r.req_wstrb;
if i_msti.aw_ready = '1' then
if i_msti.w_ready = '1' then
v.state := state_b;
else
v.state := state_w;
end if;
end if;
when state_w =>
-- Shoudln't get here because of Lite interface:
vmsto.w_valid := '1';
vmsto.w_last := '1';
vmsto.w_data := r.req_wdata;
vmsto.w_strb := r.req_wstrb;
if i_msti.w_ready = '1' then
v.state := state_b;
end if;
when state_b =>
vmsto.b_ready := '1';
v_resp_mem_valid := i_msti.b_valid;
v_mem_er_store_fault := i_msti.b_resp(1);
if i_msti.b_valid = '1' then
v.state := state_idle;
end if;
when others =>
end case;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
o_msto <= vmsto;
req_mem_ready_i <= v_next_ready;
resp_mem_valid_i <= v_resp_mem_valid;
resp_mem_load_fault_i <= v_mem_er_load_fault;
resp_mem_store_fault_i <= v_mem_er_store_fault;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | d55c0fc75dcd2bfa11670ab8ae03ee81 | 0.5581 | 3.085547 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/fifo_generator_v11_0_synth.vhd | 19 | 237,901 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
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`protect key_block
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`protect end_protected
| bsd-2-clause | 16a11e5c829f269bddfa67a3969683a0 | 0.954313 | 1.808047 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/d2l_d.vhd | 1 | 6,109 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity Double2Long is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_overflow : out std_logic;
o_underflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_Double2Long of Double2Long is
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(2 downto 0);
signA : std_logic;
expA : std_logic_vector(10 downto 0);
mantA : std_logic_vector(52 downto 0);
result : std_logic_vector(63 downto 0);
op_signed : std_logic;
w32 : std_logic;
mantPostScale : std_logic_vector(63 downto 0);
overflow : std_logic;
underflow : std_logic;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
'0', (others => '0'), (others => '0'), -- signA, expA, mantA
(others => '0'), '0', '0', -- result, op_signed, w32
(others => '0'), '0', '0' -- mantPostScale, overflow, underflow
);
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
signal r, rin : RegistersType;
begin
-- registers:
comb : process(i_nrst, i_ena, i_signed, i_w32, i_a, r)
variable v : RegistersType;
variable expDif : std_logic_vector(11 downto 0);
variable mantPreScale : std_logic_vector(63 downto 0);
variable mantPostScale : std_logic_vector(63 downto 0);
variable mantA : std_logic_vector(52 downto 0);
variable expDif_gr : std_logic; -- greater than 1023 + 63
variable expDif_lt : std_logic; -- less than 1023
variable overflow : std_logic;
variable underflow : std_logic;
variable expMax : std_logic_vector(10 downto 0);
variable expShift : std_logic_vector(5 downto 0);
variable resSign : std_logic;
variable resMant : std_logic_vector(63 downto 0);
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena := r.ena(1 downto 0) & (i_ena and not r.busy);
mantA(51 downto 0) := i_a(51 downto 0);
mantA(52) := '0';
if i_a(62 downto 52) /= zero64(10 downto 0) then
mantA(52) := '1';
end if;
if i_ena = '1' then
v.busy := '1';
v.signA := i_a(63);
v.expA := i_a(62 downto 52);
v.mantA := mantA;
v.op_signed := i_signed;
v.w32 := i_w32;
v.overflow := '0';
v.underflow := '0';
end if;
-- expShift = (1086 - expA)[5:0]
expShift := "111110" - r.expA(5 downto 0);
if r.w32 = '1' then
if r.op_signed = '1' then
expMax := conv_std_logic_vector(1053, 11);
else
expMax := conv_std_logic_vector(1085, 11);
end if;
else
if r.op_signed = '1' or r.signA = '1' then
expMax := conv_std_logic_vector(1085, 11);
else
expMax := conv_std_logic_vector(1086, 11);
end if;
end if;
expDif := ('0' & expMax) - ('0' & r.expA);
expDif_gr := expDif(11);
expDif_lt := '0';
if r.expA /= "01111111111" and r.expA(10) = '0' then
expDif_lt := '1';
end if;
mantPreScale := r.mantA & "00000000000";
mantPostScale := (others => '0');
if expDif_gr = '1' then
overflow := '1';
underflow := '0';
elsif expDif_lt = '1' then
overflow := '0';
underflow := '1';
else
overflow := '0';
underflow := '0';
-- Multiplexer, probably switch case in rtl
if expShift = "000000" then
mantPostScale := mantPreScale;
else
for i in 1 to 63 loop
if conv_integer(expShift) = i then
mantPostScale := zero64(i-1 downto 0) & mantPreScale(63 downto i);
end if;
end loop;
end if;
end if;
if r.ena(0) = '1' then
v.overflow := overflow;
v.underflow := underflow;
v.mantPostScale := mantPostScale;
end if;
-- Result multiplexers:
resSign := (r.signA or r.overflow) and not r.underflow;
if r.signA = '1' then
resMant := not r.mantPostScale + 1;
else
resMant := r.mantPostScale;
end if;
res := resMant;
if r.op_signed = '1' then
if resSign = '1' then
if r.w32 = '1' then
res(63 downto 31) := (others => '1');
else
res(63) := '1';
end if;
end if;
else
if r.w32 = '1' then
res(63 downto 32) := (others => '0');
elsif r.overflow = '1' then
res(63) := '1';
end if;
end if;
if r.ena(1) = '1' then
v.result := res;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_overflow <= r.overflow;
o_underflow <= r.underflow;
o_valid <= r.ena(2);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | b45dadd64001450c2a14aa1a8f100da7 | 0.549353 | 3.345564 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_v8_1.vhd | 27 | 19,382 | `protect begin_protected
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12608)
`protect data_block
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`protect end_protected
| bsd-2-clause | 2c8cbb2ac6a5411b98769fc953ca5366 | 0.940099 | 1.859006 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_v8_1_pkg.vhd | 27 | 123,409 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 89616)
`protect data_block
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`protect end_protected
| bsd-2-clause | 5ab00585faf85be46cc73956fb7a229e | 0.952953 | 1.814758 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_handshaking_flags.vhd | 19 | 13,954 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8592)
`protect data_block
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`protect end_protected
| bsd-2-clause | d6556c9119edee234098bc8cc789adae | 0.933926 | 1.87453 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/axi4_flashspi.vhd | 1 | 18,637 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_flashspi is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
wait_while_write : boolean := true -- hold AXI bus response until end of write cycle
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_spi : in spi_in_type;
o_spi : out spi_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type );
end;
architecture arch_axi4_flashspi of axi4_flashspi is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_SPI_FLASH
);
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
type state_type is (idle, wsetup, rsetup, txcmd, rbyte, wbyte, rd_complete, wr_complete, wr_accept);
type page_buf_type is array (0 to 31) of std_logic_vector(31 downto 0); --128 bytes
type registers is record
scaler : std_logic_vector(31 downto 0);
scaler_cnt : std_logic_vector(31 downto 0);
state : state_type;
rready : std_logic;
wready : std_logic;
-- Access to control registers always 4 bytes only
raddr : std_logic_vector(17 downto 2);
rdata : std_logic_vector(63 downto 0);
waddr : std_logic_vector(7 downto 2);
wdata : std_logic_vector(31 downto 0);
csn : std_logic;
sck : std_logic;
op64 : std_logic;
so_shifter : std_logic_vector(31 downto 0);
si_shifter : std_logic_vector(63 downto 0);
cmdbit_cnt : integer range 0 to 31;
databyte_cnt : integer range 0 to 255;
databyte_mask : std_logic_vector(6 downto 0);
wraccess : std_logic;
bytes_received : integer range 0 to 8;
buf_addr : std_logic_vector(6 downto 0);
end record;
constant R_RESET : registers := (
(others => '0'), (others => '0'), idle, -- scaler, scaler_cnt, state
'0', '0', -- rready, wready
(others => '0'), (others => '0'), -- raddr, rdata
(others => '0'), (others => '0'), -- waddr, wdata
'1', '0', '0', -- csn, sck, op64
(others => '0'), (others => '0'), -- so_shifter, si_shifter
0, 0, -- cmdbit_cnt, databyte_cnt
(others => '0'), '0', -- databyte_mask, wraccess
0, (others => '0') -- bytes_received, buf_addr
);
signal wb_page_addr : std_logic_vector(4 downto 0);
signal wb_page_rdata0 : std_logic_vector(31 downto 0);
signal wb_page_wdata0 : std_logic_vector(31 downto 0);
signal w_page_we0 : std_logic;
signal pagebuf0 : page_buf_type;
signal wb_page_rdata1 : std_logic_vector(31 downto 0);
signal wb_page_wdata1 : std_logic_vector(31 downto 0);
signal w_page_we1 : std_logic;
signal pagebuf1 : page_buf_type;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal w_data_ready : std_logic;
signal r, rin : registers;
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => w_data_ready,
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_spi, r, wb_page_rdata0, wb_page_rdata1,
w_bus_re, wb_bus_raddr, wb_bus_waddr, w_bus_we,
wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable posedge_flag : std_logic;
variable negedge_flag : std_logic;
variable vb_page_addr_mux : std_logic_vector(4 downto 0);
variable vb_page_addr : std_logic_vector(4 downto 0);
variable vb_page_wdata0 : std_logic_vector(31 downto 0);
variable v_page_we0 : std_logic;
variable vb_page_wdata1 : std_logic_vector(31 downto 0);
variable v_page_we1 : std_logic;
begin
v := r;
vb_page_addr := (others => '0');
vb_page_wdata0 := (others => '0');
v_page_we0 := '0';
vb_page_wdata1 := (others => '0');
v_page_we1 := '0';
v.rready := '0';
v.wready := '0';
w_data_ready <= r.rready or r.wready;
-- system bus clock scaler to baudrate:
posedge_flag := '0';
negedge_flag := '0';
if r.scaler /= zero32 then
if r.csn = '1' then
v.scaler_cnt := zero32;
v.sck := '0';
elsif r.scaler_cnt = (r.scaler-1) then
v.scaler_cnt := zero32;
v.sck := not r.sck;
posedge_flag := not r.sck;
negedge_flag := r.sck;
else
v.scaler_cnt := r.scaler_cnt + 1;
end if;
end if;
case r.state is
when idle =>
v.so_shifter := (others => '0');
v.csn := '1';
v.sck := '0';
when rsetup =>
v.wraccess := '0';
v.bytes_received := 0;
if r.raddr(17) = '1' then
-- Control registers:
case conv_integer(r.raddr(16 downto 2)) is
when 0 =>
v.state := rd_complete;
v.si_shifter(31 downto 0) := r.scaler;
v.si_shifter(63 downto 32) := (others => '0');
v.bytes_received := 1; -- to avoid bytes swapping
when 4 => -- Read Flash STATUS
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '0'); -- Clear mask to enable 'rbyte' state
v.so_shifter := X"05000000";
v.si_shifter := (others => '0');
when 6 => -- Read Flash ID and Release from Deep Power-down
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0; -- Read one Byte Manufacturer ID = 0x29
v.databyte_mask := (others => '0'); -- Clear mask to enable 'rbyte' state
v.so_shifter := X"AB000000";
v.si_shifter := (others => '0');
when others =>
v.state := rd_complete;
v.si_shifter := (others => '0');
end case;
else
-- Access to SPI
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
if r.op64 = '1' then
v.databyte_cnt := 7;
else
v.databyte_cnt := 3;
end if;
v.databyte_mask := (others => '0');
-- [31:24] - command 0x3 = READ
-- [23:17] - ignored by flash
-- [16:0] - address
v.so_shifter := X"03" & "0000000" & r.raddr(16 downto 2) & "00";
end if;
when wsetup =>
-- Only control request. Write to page buffer doesn't get here:
v.wraccess := '1';
case conv_integer(r.waddr) is
when 0 =>
v.state := wr_complete;
v.scaler := r.wdata;
when 4 => -- Write Flash STATUS
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 15;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"01" & r.wdata(7 downto 0) & X"0000";
when 8 => -- Write Enable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"06000000";
when 10 => -- Page Write
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '0'); -- Clear mask to enter 'wbyte' state
v.so_shifter := X"02" & r.wdata(23 downto 8) & X"00";
v.buf_addr := (others => '0');
when 12 => -- Write Disable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"04000000";
when 14 => -- Page Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"42" & r.wdata(23 downto 0);
when 16 => -- Sector Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 31;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"D8" & r.wdata(23 downto 0);
when 18 => -- Chip Erase
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"C7000000";
when 20 => -- Deep Power-Down mode enable
v.state := txcmd;
v.csn := '0';
v.cmdbit_cnt := 7;
v.databyte_cnt := 0;
v.databyte_mask := (others => '1'); -- Set mask to skip 'wbyte' state
v.so_shifter := X"B9000000";
when others =>
v.state := wr_complete;
end case;
when txcmd =>
if negedge_flag = '1' then
v.so_shifter := r.so_shifter(30 downto 0) & "0";
if r.cmdbit_cnt = 0 then
if r.databyte_mask = "0000000" then
if r.wraccess = '1' then
v.state := wbyte;
-- Transmit 256 bytes of page buffer starting from 0 offset
v.so_shifter := wb_page_rdata0(7 downto 0) & wb_page_rdata0(15 downto 8)
& wb_page_rdata0(23 downto 16) & wb_page_rdata0(31 downto 24);
v.buf_addr := r.buf_addr + 1;
v.databyte_cnt := 3;
else
v.state := rbyte;
end if;
else
if r.wraccess = '1' then
v.state := wr_complete;
else
v.state := rd_complete;
end if;
end if;
else
v.cmdbit_cnt := r.cmdbit_cnt - 1;
end if;
end if;
when rbyte =>
if posedge_flag = '1' then
v.si_shifter := r.si_shifter(62 downto 0) & i_spi.SDI;
v.databyte_mask := r.databyte_mask(5 downto 0) & '1';
if r.databyte_mask = "1111111" then
v.bytes_received := r.bytes_received + 1;
if r.databyte_cnt = 0 then
v.state := rd_complete;
else
v.databyte_cnt := r.databyte_cnt - 1;
v.databyte_mask := (others => '0');
end if;
end if;
end if;
when rd_complete =>
v.rready := '1'; -- End of access wait-states
if r.bytes_received = 8 then
v.rdata := r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24)
& r.si_shifter(39 downto 32) & r.si_shifter(47 downto 40)
& r.si_shifter(55 downto 48) & r.si_shifter(63 downto 56);
elsif r.bytes_received = 4 then
v.rdata := r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24)
& r.si_shifter(7 downto 0) & r.si_shifter(15 downto 8)
& r.si_shifter(23 downto 16) & r.si_shifter(31 downto 24);
else
v.rdata := r.si_shifter;
end if;
v.state := idle;
when wbyte =>
if negedge_flag = '1' then
v.so_shifter := r.so_shifter(30 downto 0) & "0";
v.databyte_mask := r.databyte_mask(5 downto 0) & '1';
if r.databyte_mask = "1111111" then
v.databyte_mask := (others => '0');
if r.databyte_cnt = 0 then
v.buf_addr := r.buf_addr + 1;
if conv_integer(r.buf_addr) = 64 then
v.state := wr_complete;
elsif r.buf_addr(0) = '1' then
v.databyte_cnt := 3;
v.so_shifter := wb_page_rdata1(7 downto 0) & wb_page_rdata1(15 downto 8)
& wb_page_rdata1(23 downto 16) & wb_page_rdata1(31 downto 24);
else
v.databyte_cnt := 3;
v.so_shifter := wb_page_rdata0(7 downto 0) & wb_page_rdata0(15 downto 8)
& wb_page_rdata0(23 downto 16) & wb_page_rdata0(31 downto 24);
end if;
else
v.databyte_cnt := r.databyte_cnt - 1;
end if;
end if;
end if;
when wr_complete =>
if wait_while_write then
v.wready := '1'; -- End of access wait-states
end if;
v.state := wr_accept;
v.csn := '1';
when wr_accept =>
-- To avoid re-accept the same write request
v.state := idle;
when others =>
end case;
if w_bus_re = '1' then
v.state := rsetup;
v.raddr := wb_bus_raddr(0)(17 downto 2);
if wb_bus_raddr(0)(2) = '1' then
v.op64 := '0';
else
v.op64 := '1';
end if;
end if;
-- Wait states: Read and Write transaction takes at least 1 wait state, except
-- 0 clocks (no wait states). Writing into page buffer
-- 1 clock. Read/Write control register without access to SPI Flash (scaler, example)
-- N clocks. When access to Flash, depending length of SPI sequence and scaler.
if w_bus_we = '1' then
wstrb := wb_bus_wstrb;
if wb_bus_waddr(0)(17) = '0' then
-- Write to page buffer
v.wready := '1'; -- No wait states needed
vb_page_addr := wb_bus_waddr(0)(7 downto 3);
if wb_bus_waddr(0)(2) = '0' then
-- 4 or 8 bytes
v_page_we0 := wstrb(3) or wstrb(2) or wstrb(1) or wstrb(0);
vb_page_wdata0 := wb_bus_wdata(31 downto 0);
v_page_we1 := wstrb(7) or wstrb(6) or wstrb(5) or wstrb(4);
vb_page_wdata1 := wb_bus_wdata(63 downto 32);
else
-- 4-bytes only
v_page_we0 := '0';
vb_page_wdata0 := (others => '0');
v_page_we1 := wstrb(3) or wstrb(2) or wstrb(1) or wstrb(0);
vb_page_wdata1 := wb_bus_wdata(31 downto 0);
end if;
elsif r.state = idle then
if not wait_while_write then
v.wready := '1';
end if;
v.state := wsetup;
-- Only 4-bytes access to control registers:
if wb_bus_waddr(0)(2) = '0' and wstrb = X"F0" then
v.waddr := wb_bus_waddr(1)(7 downto 2);
v.wdata := wb_bus_wdata(63 downto 32);
else
v.waddr := wb_bus_waddr(0)(7 downto 2);
v.wdata := wb_bus_wdata(31 downto 0);
end if;
end if;
end if;
if r.state = txcmd or r.state = wbyte then
vb_page_addr_mux := r.buf_addr(5 downto 1);
else
vb_page_addr_mux := vb_page_addr;
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
wb_page_addr <= vb_page_addr_mux;
wb_page_wdata0 <= vb_page_wdata0;
w_page_we0 <= v_page_we0;
wb_page_wdata1 <= vb_page_wdata1;
w_page_we1 <= v_page_we1;
end process;
cfg <= xconfig;
o_spi.SDO <= r.so_shifter(31);
o_spi.SCK <= r.sck;
o_spi.nCS <= r.csn;
o_spi.nWP <= '1';
o_spi.nHOLD <= '1';
o_spi.RESET <= '0';
reg : process (nrst, clk, wb_page_addr, w_page_we0, wb_page_wdata0,
w_page_we1, wb_page_wdata1)
begin
if nrst = '0' then
pagebuf0 <= (others => (others => '1'));
pagebuf1 <= (others => (others => '1'));
elsif rising_edge(clk) then
if w_page_we0 = '1' then
pagebuf0(conv_integer(wb_page_addr)) <= wb_page_wdata0;
end if;
if w_page_we1 = '1' then
pagebuf1(conv_integer(wb_page_addr)) <= wb_page_wdata1;
end if;
end if;
end process;
wb_page_rdata0 <= pagebuf0(conv_integer(wb_page_addr));
wb_page_rdata1 <= pagebuf1(conv_integer(wb_page_addr));
-- registers:
regs : process(nrst, clk)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; | apache-2.0 | 499e474635ab4750c2f9dbc554b4a16d | 0.506949 | 3.431596 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/ibuf_tech.vhd | 1 | 1,073 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple input buffer.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ibuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of ibuf_tech is
component ibuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component ibuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = mikron180 generate
bufm : ibuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= mikron180 generate
bufinf : ibuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
| apache-2.0 | 3a6ceb6fb6b4c98a5a99d60ca7742849 | 0.512582 | 3.859712 | false | false | false | false |
szanni/aeshw | aes-core/aes_module.vhd | 1 | 4,006 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:26:10 07/21/2014
-- Design Name:
-- Module Name: aes_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aes_module is
port ( clk : in std_logic;
reset : in std_logic;
din : in state; -- 128 bit key or plaintext/cyphertext block
dout : out state; -- 128 bit plaintext/cyphertext block
mode : in aes_mode;
aes_start : in std_logic;
aes_done : out std_logic
);
end aes_module;
architecture Behavioral of aes_module is
signal rkey : state;
signal rkey_addr, rkey_addr_enc, rkey_addr_dec : std_logic_vector(3 downto 0);
signal dout_enc, dout_dec : state;
signal start_enc, start_dec, start_exp : std_logic;
signal end_enc, end_dec, end_exp : std_logic;
signal mux_ctrl : aes_mode;
signal result_valid : std_logic;
signal aes_result, dout_in : state;
begin
dout <= dout_in;
dout_reg : process (reset, clk, aes_result, result_valid)
begin
if reset = '1' then
dout_in <= (others => '0');
elsif rising_edge(clk) then
if result_valid = '1' then
dout_in <= aes_result;
end if;
end if;
end process dout_reg;
dout_mux : process(mux_ctrl, dout_enc, dout_dec)
begin
case mux_ctrl is
when ENCRYPT => aes_result <= dout_enc;
when others => aes_result <= dout_dec;
end case;
end process dout_mux;
rkey_addr_mux : process(mux_ctrl, rkey_addr_enc, rkey_addr_dec)
begin
case mux_ctrl is
when ENCRYPT => rkey_addr <= rkey_addr_enc;
when others => rkey_addr <= rkey_addr_dec;
end case;
end process rkey_addr_mux;
encryption_module: entity work.encryption_module port map (clk => clk,
reset => reset,
enc_start => start_enc,
enc_end => end_enc,
din => din,
dout => dout_enc,
addr_rkey => rkey_addr_enc,
rkey_in => rkey
);
decryption_module: entity work.decryption_module port map (clk => clk,
reset => reset,
dec_start => start_dec,
dec_end => end_dec,
din => din,
dout => dout_dec,
addr_rkey => rkey_addr_dec,
rkey_in => rkey
);
key_expansion: entity work.key_expansion port map (clk => clk,
reset => reset,
exp_start => start_exp,
exp_end => end_exp,
address_in => rkey_addr,
key_in => din,
key_out => rkey
);
control_unit: entity work.aes_module_cu port map(clk => clk,
reset => reset,
x_start => aes_start,
x_mode => mode,
x_end_enc => end_enc,
x_end_dec => end_dec,
x_end_exp => end_exp,
y_done => aes_done,
y_start_enc => start_enc,
y_start_dec => start_dec,
y_start_exp => start_exp,
y_mux_ctrl => mux_ctrl,
y_end => result_valid
);
end Behavioral;
| bsd-2-clause | ab8ae460a822a8f13f0023c4dbd12d2d | 0.500749 | 3.695572 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_rst_processing_system7_0_50M_0/synth/dma_loopback_rst_processing_system7_0_50M_0.vhd | 1 | 6,793 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 9
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY dma_loopback_rst_processing_system7_0_50M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END dma_loopback_rst_processing_system7_0_50M_0;
ARCHITECTURE dma_loopback_rst_processing_system7_0_50M_0_arch OF dma_loopback_rst_processing_system7_0_50M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dma_loopback_rst_processing_system7_0_50M_0_arch : ARCHITECTURE IS "dma_loopback_rst_processing_system7_0_50M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dma_loopback_rst_processing_system7_0_50M_0_arch: ARCHITECTURE IS "dma_loopback_rst_processing_system7_0_50M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END dma_loopback_rst_processing_system7_0_50M_0_arch;
| mit | 8e7ae6e244a8e43029b2300e9dcfb630 | 0.718681 | 3.476459 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_axi_read_wrapper.vhd | 27 | 57,813 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 41056)
`protect data_block
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| bsd-2-clause | 42f32058fb077126f841c8a4244ba674 | 0.950738 | 1.81779 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/dsu/ic_dport_2s_1m.vhd | 1 | 8,021 | --!
--! Copyright 2020 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! @brief DPort interconnect to provided access for 2 sources:
--! 1. Direct access from DSU to all cores
--! 2. DMI registers access
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_river.all;
entity ic_dport_2s_1m is
generic (
async_reset : boolean := false
);
port
(
clk : in std_logic;
nrst : in std_logic;
-- Group <=> DMI interface
i_sdport0i : in dport_in_vector;
o_sdport0o : out dport_out_vector;
-- Group <=> DSU interface
i_sdport1i : in dport_in_vector;
o_sdport1o : out dport_out_vector;
-- Group connection
o_mdporti : out dport_in_vector;
i_mdporto : in dport_out_vector
);
end;
architecture arch_ic_dport_2s_1m of ic_dport_2s_1m is
type state_type is (
idle,
dport_request,
dport_response,
slave_accept
);
type rdata_type is array (0 to CFG_TOTAL_CPU_MAX-1)
of std_logic_vector(RISCV_ARCH-1 downto 0);
type registers is record
state : state_type;
idx : std_logic;
mst_req_valid : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
mst_resp_ready : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
dporti : dport_in_vector;
rdata : rdata_type;
end record;
signal r, rin: registers;
begin
comblogic : process(nrst, i_sdport0i, i_sdport1i, i_mdporto, r)
variable v : registers;
variable vb_req_valid : std_logic_vector(1 downto 0);
variable vb_ic_req_ready : std_logic_vector(1 downto 0);
variable v_dport_request : std_logic;
variable v_dport_response : std_logic;
variable vb_slv0_resp_valid : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
variable vb_slv1_resp_valid : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
variable vb_ic_req_valid : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
begin
v := r;
-- Slave request 0:
vb_req_valid(0) := '0';
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
vb_req_valid(0) := vb_req_valid(0) or i_sdport0i(n).req_valid;
end loop;
-- Slave request 1:
vb_req_valid(1) := '0';
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
vb_req_valid(1) := vb_req_valid(1) or i_sdport1i(n).req_valid;
end loop;
vb_ic_req_ready := (others => '0');
v_dport_request := '0';
v_dport_response := '0';
vb_slv0_resp_valid := (others => '0');
vb_slv1_resp_valid := (others => '0');
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
vb_ic_req_valid(n) := r.dporti(n).req_valid;
end loop;
case (r.state) is
when idle =>
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
v.mst_req_valid := (others => '0');
v.mst_resp_ready := (others => '0');
end loop;
-- Slave request 1 has low priority than 0:
if vb_req_valid(0) = '1' then
vb_ic_req_ready(0) := '1';
v.idx := '0';
v.state := dport_request;
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
v.mst_req_valid(n) := i_sdport0i(n).req_valid;
v.mst_resp_ready(n) := i_sdport0i(n).req_valid;
v.dporti(n).req_valid := i_sdport0i(n).req_valid;
v.dporti(n).write := i_sdport0i(n).write;
v.dporti(n).addr := i_sdport0i(n).addr;
v.dporti(n).wdata := i_sdport0i(n).wdata;
end loop;
elsif vb_req_valid(1) = '1' then
vb_ic_req_ready(1) := '1';
v.idx := '1';
v.state := dport_request;
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
v.mst_req_valid(n) := i_sdport1i(n).req_valid;
v.mst_resp_ready(n) := i_sdport1i(n).req_valid;
v.dporti(n).req_valid := i_sdport1i(n).req_valid;
v.dporti(n).write := i_sdport1i(n).write;
v.dporti(n).addr := i_sdport1i(n).addr;
v.dporti(n).wdata := i_sdport1i(n).wdata;
end loop;
end if;
when dport_request =>
v_dport_request := '1';
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
if i_mdporto(n).req_ready = '1' then
v.mst_req_valid(n) := '0';
end if;
end loop;
if or_reduce(v.mst_req_valid) = '0' then
v.state := dport_response;
end if;
when dport_response =>
v_dport_response := '1';
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
if i_mdporto(n).resp_valid = '1' then
v.mst_resp_ready(n) := '0';
v.rdata(n) := i_mdporto(n).rdata;
end if;
end loop;
if or_reduce(v.mst_resp_ready) = '0' then
v.state := slave_accept;
end if;
when slave_accept =>
if r.idx = '0' then
vb_slv0_resp_valid := vb_ic_req_valid;
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
if i_sdport0i(n).resp_ready = '1' then
v.dporti(n).req_valid := '0';
end if;
end loop;
else
vb_slv1_resp_valid := vb_ic_req_valid;
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
if i_sdport1i(n).resp_ready = '1' then
v.dporti(n).req_valid := '0';
end if;
end loop;
end if;
if or_reduce(vb_ic_req_valid) = '0' then
v.state := idle;
end if;
when others =>
end case;
if not async_reset and nrst = '0' then
v.state := idle;
v.idx := '0';
v.mst_req_valid := (others => '0');
v.mst_resp_ready := (others => '0');
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
v.dporti(n) := dport_in_none;
v.rdata(n) := (others => '0');
end loop;
end if;
rin <= v;
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
o_sdport0o(n).halted <= i_mdporto(n).halted;
o_sdport0o(n).available <= i_mdporto(n).available;
o_sdport0o(n).req_ready <= vb_ic_req_ready(0);
o_sdport0o(n).resp_valid <= vb_slv0_resp_valid(n);
o_sdport0o(n).rdata <= r.rdata(n);
o_sdport1o(n).halted <= i_mdporto(n).halted;
o_sdport1o(n).available <= i_mdporto(n).available;
o_sdport1o(n).req_ready <= vb_ic_req_ready(1);
o_sdport1o(n).resp_valid <= vb_slv1_resp_valid(n);
o_sdport1o(n).rdata <= r.rdata(n);
o_mdporti(n).req_valid <= r.mst_req_valid(n) and v_dport_request;
o_mdporti(n).resp_ready <= r.mst_resp_ready(n) and v_dport_response;
o_mdporti(n).write <= r.dporti(n).write;
o_mdporti(n).addr <= r.dporti(n).addr;
o_mdporti(n).wdata <= r.dporti(n).wdata;
end loop;
end process;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r.state <= idle;
r.idx <= '0';
r.mst_req_valid <= (others => '0');
r.mst_resp_ready <= (others => '0');
for n in 0 to CFG_TOTAL_CPU_MAX-1 loop
r.dporti(n) <= dport_in_none;
r.rdata(n) <= (others => '0');
end loop;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 7923d7768db9fd624ca8c37c103e3cae | 0.54669 | 3.012017 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_queue.vhd | 1 | 41,099 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
--use axi_sg_v4_1_3.axi_sg_afifo_autord.all;
library lib_fifo_v1_0_5;
use lib_fifo_v1_0_5.sync_fifo_fg;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_primary_aclk : in std_logic ;
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
-- Channel Control --
desc1_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
desc2_flush : in std_logic ; --
ftch1_active : in std_logic ; --
ftch2_active : in std_logic ; --
ftch1_queue_empty : out std_logic ; --
ftch2_queue_empty : out std_logic ; --
ftch1_queue_full : out std_logic ; --
ftch2_queue_full : out std_logic ; --
ftch1_pause : out std_logic ; --
ftch2_pause : out std_logic ; --
--
writing_nxtdesc_in : in std_logic ; --
writing1_curdesc_out : out std_logic ; --
writing2_curdesc_out : out std_logic ; --
--
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
sof_ftch_desc : in std_logic ;
m_axis1_mm2s_tready : out std_logic ; --
m_axis2_mm2s_tready : out std_logic ; --
--
data_concat_64 : in std_logic_vector --
(31 downto 0) ; --
data_concat_64_cdma : in std_logic_vector --
(31 downto 0) ; --
data_concat : in std_logic_vector --
(95 downto 0) ; --
data_concat_mcdma : in std_logic_vector --
(63 downto 0) ; --
data_concat_tlast : in std_logic ; --
next_bd : in std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0);
data_concat_valid : in std_logic ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ftch_aclk : in std_logic ; --
m_axis_ftch1_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch1_tvalid : out std_logic ; --
m_axis_ftch1_tready : in std_logic ; --
m_axis_ftch1_tlast : out std_logic ; --
m_axis_ftch1_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch1_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch1_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
m_axis_ftch2_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ftch2_tvalid : out std_logic ; --
m_axis_ftch2_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ftch2_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ftch2_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
m_axis_ftch2_tready : in std_logic ; --
m_axis_ftch2_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Number of words deep fifo needs to be
-- 6 is subtracted as BD address are always 16 word aligned
constant FIFO_WIDTH : integer := (128*C_ENABLE_CDMA + 97*(1-C_ENABLE_CDMA) -6);
constant C_SG_WORDS_TO_FETCH1 : integer := C_SG_WORDS_TO_FETCH + 2*C_ENABLE_MULTI_CHANNEL;
--constant FETCH_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
-- * C_SG_WORDS_TO_FETCH1));
constant FETCH_QUEUE_DEPTH : integer := 16;
-- Select between BRAM or Logic Memory Type
constant MEMORY_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG_WORDS_TO_FETCH1 > 16);
constant FETCH_QUEUE_CNT_WIDTH : integer := clog2(FETCH_QUEUE_DEPTH+1);
constant DCNT_LO_INDEX : integer := max2(1,clog2(C_SG_WORDS_TO_FETCH1)) - 1;
constant DCNT_HI_INDEX : integer := FETCH_QUEUE_CNT_WIDTH-1; -- CR616461
constant C_SG2_WORDS_TO_FETCH1 : integer := C_SG2_WORDS_TO_FETCH;
constant FETCH2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1));
-- Select between BRAM or Logic Memory Type
constant MEMORY2_TYPE : integer := bo2int(C_SG_FTCH_DESC2QUEUE
* C_SG2_WORDS_TO_FETCH1 > 16);
constant FETCH2_QUEUE_CNT_WIDTH : integer := clog2(FETCH2_QUEUE_DEPTH+1);
constant DCNT2_LO_INDEX : integer := max2(1,clog2(C_SG2_WORDS_TO_FETCH1)) - 1;
constant DCNT2_HI_INDEX : integer := FETCH2_QUEUE_CNT_WIDTH-1; -- CR616461
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant DESC2QUEUE_VECT_WIDTH : integer := 4;
--constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
-- := std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
constant SG_FTCH_DESC2QUEUE_VECT : std_logic_vector(DESC2QUEUE_VECT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(C_SG_FTCH_DESC2QUEUE,DESC2QUEUE_VECT_WIDTH)); -- CR616461
--constant DCNT_HI_INDEX : integer := (DCNT_LO_INDEX + DESC2QUEUE_VECT_WIDTH) - 1; -- CR616461
constant ZERO_COUNT : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
constant ZERO_COUNT1 : std_logic_vector(FETCH2_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Internal signals
signal curdesc_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_tvalid : std_logic := '0';
signal ftch_tvalid : std_logic := '0';
signal ftch_tvalid_new : std_logic := '0';
signal ftch_tdata : std_logic_vector
(31 downto 0) := (others => '0');
signal ftch_tdata_new, reg1, reg2 : std_logic_vector
(FIFO_WIDTH-1 downto 0) := (others => '0');
signal ftch_tdata_new_64, reg1_64, reg2_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal ftch_tdata_new_bd, reg2_bd_64, reg1_bd_64 : std_logic_vector (31 downto 0) := (others => '0');
signal ftch_tlast : std_logic := '0';
signal ftch_tlast_new : std_logic := '0';
signal ftch_tready : std_logic := '0';
signal ftch_tready_ch1 : std_logic := '0';
signal ftch_tready_ch2 : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal writing_nxtdesc : std_logic := '0';
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal writing_lsb : std_logic := '0';
signal writing_msb : std_logic := '0';
-- FIFO signals
signal queue_rden2 : std_logic := '0';
signal queue_rden2_new : std_logic := '0';
signal queue_wren2 : std_logic := '0';
signal queue_wren2_new : std_logic := '0';
signal queue_empty2 : std_logic := '0';
signal queue_empty2_new : std_logic := '0';
signal queue_rden : std_logic := '0';
signal queue_rden_new : std_logic := '0';
signal queue_wren : std_logic := '0';
signal queue_wren_new : std_logic := '0';
signal queue_empty : std_logic := '0';
signal queue_empty_new : std_logic := '0';
signal queue_dout_valid : std_logic := '0';
signal queue_dout2_valid : std_logic := '0';
signal queue_full_new : std_logic := '0';
signal queue_full2_new : std_logic := '0';
signal queue_full, queue_full2 : std_logic := '0';
signal queue_din_new : std_logic_vector
(127 downto 0) := (others => '0');
signal queue_dout_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_dout2_new_64 : std_logic_vector ((1+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) -1 downto 0) := (others => '0');
signal queue_dout2_new_bd : std_logic_vector (31 downto 0) := (others => '0');
signal queue_dout2_new : std_logic_vector
(96+31*C_ENABLE_CDMA-6 downto 0) := (others => '0');
signal queue_dout2_mcdma_new : std_logic_vector
(63 downto 0) := (others => '0');
signal queue_din : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_dout2 : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH downto 0) := (others => '0');
signal queue_sinit : std_logic := '0';
signal queue_sinit2 : std_logic := '0';
signal queue_dcount_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal queue_dcount2_new : std_logic_vector(FETCH_QUEUE_CNT_WIDTH-1 downto 0) := (others => '0');
signal ftch_no_room : std_logic;
signal ftch_active : std_logic := '0';
signal ftch_tvalid_mult : std_logic := '0';
signal ftch_tdata_mult : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal ftch_tlast_mult : std_logic := '0';
signal counter : std_logic_vector (3 downto 0) := (others => '0');
signal wr_cntl : std_logic := '0';
signal sof_ftch_desc_del : std_logic;
signal sof_ftch_desc_del1 : std_logic;
signal sof_ftch_desc_pulse : std_logic;
signal current_bd : std_logic_vector (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal xfer_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
SOF_DEL_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_ftch_desc_del <= '0';
else
sof_ftch_desc_del <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL_PROCESS;
SOF_DEL1_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1'))then
sof_ftch_desc_del1 <= '0';
elsif (m_axis_mm2s_tvalid = '1') then
sof_ftch_desc_del1 <= sof_ftch_desc;
end if;
end if;
end process SOF_DEL1_PROCESS;
sof_ftch_desc_pulse <= sof_ftch_desc and (not sof_ftch_desc_del1);
ftch_active <= ftch1_active or ftch2_active;
---------------------------------------------------------------------------
-- Write current descriptor to FIFO or out channel port
---------------------------------------------------------------------------
CURRENT_BD_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(32+DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_64;
CURRENT_BD_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
CMDDATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
current_bd <= (others => '0');
elsif (ftch2_active = '1' and C_ENABLE_MULTI_CHANNEL = 1) then
current_bd <= next_bd;
elsif (ftch_cmnd_wr = '1' and ftch_active = '1') then
current_bd <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT
downto DATAMOVER_CMD_ADDRLSB_BIT);
end if;
end if;
end process CMDDATA_PROCESS;
end generate CURRENT_BD_32;
GEN_MULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
ftch_tvalid_mult <= m_axis_mm2s_tvalid;
ftch_tdata_mult <= m_axis_mm2s_tdata;
ftch_tlast_mult <= m_axis_mm2s_tlast;
wr_cntl <= m_axis_mm2s_tvalid;
end generate GEN_MULT_CHANNEL;
GEN_NOMULT_CHANNEL : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
ftch_tvalid_mult <= '0'; --m_axis_mm2s_tvalid;
ftch_tdata_mult <= (others => '0'); --m_axis_mm2s_tdata;
ftch_tlast_mult <= '0'; --m_axis_mm2s_tlast;
m_axis_ftch1_tdata_mcdma_new <= (others => '0');
m_axis_ftch2_tdata_mcdma_new <= (others => '0');
COUNTER_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or m_axis_mm2s_tlast = '1')then
counter <= (others => '0');
elsif (m_axis_mm2s_tvalid = '1') then
counter <= std_logic_vector(unsigned(counter) + 1);
end if;
end if;
end process COUNTER_PROCESS;
end generate GEN_NOMULT_CHANNEL;
---------------------------------------------------------------------------
-- TVALID MUX
-- MUX tvalid out channel port
---------------------------------------------------------------------------
CDMA_FIELDS : if C_ENABLE_CDMA = 1 generate
begin
CDMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (63 downto 0) <= data_concat_64_cdma & data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate CDMA_FIELDS_64;
ftch_tdata_new (95 downto 0) <= data_concat;
-- BD is always 16 word aligned
ftch_tdata_new (121 downto 96) <= current_bd (31 downto 6);
end generate CDMA_FIELDS;
DMA_FIELDS : if C_ENABLE_CDMA = 0 generate
begin
DMA_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
ftch_tdata_new_64 (31 downto 0) <= data_concat_64;
ftch_tdata_new_bd (31 downto 0) <= current_bd (C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
end generate DMA_FIELDS_64;
ftch_tdata_new (64 downto 0) <= data_concat (95) & data_concat (63 downto 0);-- when (ftch_active = '1') else (others =>'0');
-- BD is always 16 word aligned
ftch_tdata_new (90 downto 65) <= current_bd (31 downto 6);
end generate DMA_FIELDS;
ftch_tvalid_new <= data_concat_valid and ftch_active;
ftch_tlast_new <= data_concat_tlast and ftch_active;
GEN_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_rden_new = '1') then
queue_empty_new <= '1';
queue_full_new <= '0';
elsif (queue_wren_new = '1') then
queue_empty_new <= '0';
queue_full_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
reg1 <= (others => '0');
reg1_64 <= (others => '0');
reg1_bd_64 <= (others => '0');
elsif (queue_wren_new = '1') then
reg1 <= ftch_tdata_new;
reg1_64 <= ftch_tdata_new_64;
reg1_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1') then
queue_dout_new <= (others => '0');
queue_dout_new_64 <= (others => '0');
queue_dout_new_bd <= (others => '0');
elsif (queue_rden_new = '1') then
queue_dout_new <= reg1;
queue_dout_new_64 <= reg1_64;
queue_dout_new_bd <= reg1_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit = '1' or queue_dout_valid = '1') then
queue_dout_valid <= '0';
elsif (queue_rden_new = '1') then
queue_dout_valid <= '1';
end if;
end if;
end process;
MCDMA_MM2S : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH1_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren_new ,
Rd_en => queue_rden_new ,
Dout => queue_dout_mcdma_new ,
Full => open, --queue_full_new ,
Empty => open, --queue_empty_new ,
Almost_full => open ,
Data_count => open, --queue_dcount_new ,
Rd_ack => open, --queue_dout_valid, --open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch1_tdata_mcdma_new <= queue_dout_mcdma_new;
end generate MCDMA_MM2S;
CONTROL_STREAM : if C_SG_WORDS_TO_FETCH = 13 generate
begin
I_MM2S_CNTRL_STREAM : entity axi_sg_v4_1_3.axi_sg_cntrl_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_ASYNC ,
C_PRMY_CMDFIFO_DEPTH => FETCH_QUEUE_DEPTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Secondary clock / reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Primary clock / reset
axi_prmry_aclk => m_axi_primary_aclk ,
p_reset_n => p_reset_n ,
-- MM2S Error
mm2s_stop => ch1_cntrl_strm_stop ,
-- Control Stream input
cntrlstrm_fifo_wren => queue_wren ,
cntrlstrm_fifo_full => queue_full ,
cntrlstrm_fifo_din => queue_din ,
-- Memory Map to Stream Control Stream Interface
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
end generate CONTROL_STREAM;
end generate GEN_MM2S;
GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_rden2_new = '1') then
queue_empty2_new <= '1';
queue_full2_new <= '0';
elsif (queue_wren2_new = '1') then
queue_empty2_new <= '0';
queue_full2_new <= '1';
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
reg2 <= (others => '0');
reg2_64 <= (others => '0');
reg2_bd_64 <= (others => '0');
elsif (queue_wren2_new = '1') then
reg2 <= ftch_tdata_new;
reg2_64 <= ftch_tdata_new_64;
reg2_bd_64 <= ftch_tdata_new_bd;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1') then
queue_dout2_new <= (others => '0');
queue_dout2_new_64 <= (others => '0');
queue_dout2_new_bd <= (others => '0');
elsif (queue_rden2_new = '1') then
queue_dout2_new <= reg2;
queue_dout2_new_64 <= reg2_64;
queue_dout2_new_bd <= reg2_bd_64;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (queue_sinit2 = '1' or queue_dout2_valid = '1') then
queue_dout2_valid <= '0';
elsif (queue_rden2_new = '1') then
queue_dout2_valid <= '1';
end if;
end if;
end process;
MCDMA_S2MM : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
-- Generate Synchronous FIFO
I_CH2_FTCH_MCDMA_FIFO_NEW : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => 0, --MEMORY_TYPE ,
C_WRITE_DATA_WIDTH => 64,
C_WRITE_DEPTH => FETCH_QUEUE_DEPTH ,
C_READ_DATA_WIDTH => 64,
C_READ_DEPTH => FETCH_QUEUE_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0,
C_DCOUNT_WIDTH => FETCH_QUEUE_CNT_WIDTH,
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 0,-- 1 = first word fall through
C_PRELOAD_LATENCY => 1 -- 0 = first word fall through
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => queue_sinit2 ,
Din => data_concat_mcdma, --ftch_tdata_new, --queue_din ,
Wr_en => queue_wren2_new ,
Rd_en => queue_rden2_new ,
Dout => queue_dout2_new ,
Full => open, --queue_full2_new ,
Empty => open, --queue_empty2_new ,
Almost_full => open ,
Data_count => queue_dcount2_new ,
Rd_ack => open, --queue_dout2_valid ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
m_axis_ftch2_tdata_mcdma_new <= queue_dcount2_new;
end generate MCDMA_S2MM;
end generate GEN_S2MM;
-----------------------------------------------------------------------
-- Internal Side
-----------------------------------------------------------------------
-- Drive tready with fifo not full
ftch_tready <= ftch_tready_ch1 or ftch_tready_ch2;
-- Following is the APP data that goes into APP FIFO
queue_din(C_M_AXIS_SG_TDATA_WIDTH) <= m_axis_mm2s_tlast;
queue_din(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) <= x"A0000000" when (sof_ftch_desc_pulse = '1') else m_axis_mm2s_tdata;
GEN_CH1_CTRL : if C_INCLUDE_MM2S =1 generate
begin
--queue_full_new <= '1' when (queue_dcount_new = "00100") else '0';
queue_sinit <= desc1_flush or not m_axi_sg_aresetn;
ftch_tready_ch1 <= (not queue_full and ftch1_active);
m_axis1_mm2s_tready <= ftch_tready_ch1;
-- Wr_en to APP FIFO. Data is written only when BD with SOF is fetched.
queue_wren <= not queue_full
and sof_ftch_desc
and m_axis_mm2s_tvalid
and ftch1_active;
-- Wr_en of BD FIFO
queue_wren_new <= not queue_full_new
and ftch_tvalid_new
and ftch1_active;
ftch1_queue_empty <= queue_empty_new;
ftch1_queue_full <= queue_full_new;
ftch1_pause <= queue_full_new;
-- RD_en of APP FIFO based on empty and tready
-- RD_EN of BD FIFO based on empty and tready
queue_rden_new <= not queue_empty_new
and m_axis_ftch1_tready;
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
m_axis_ftch1_tvalid_new <= queue_dout_valid; --not queue_empty_new and (not ch2_sg_idle);
-- below signal triggers the fetch of BD in MM2S Mngr
m_axis_ftch1_desc_available <= not queue_empty_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
FTCH_FIELDS_64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new_bd & queue_dout_new_64 & queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64;
FTCH_FIELDS_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
m_axis_ftch1_tdata_new <= queue_dout_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32;
writing1_curdesc_out <= writing_curdesc and ftch1_active;
NOCONTROL_STREAM_ASST : if C_SG_WORDS_TO_FETCH = 8 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate NOCONTROL_STREAM_ASST;
end generate GEN_CH1_CTRL;
GEN_NO_CH1_CTRL : if C_INCLUDE_MM2S =0 generate
begin
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= "0000";
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
ftch_tready_ch1 <= '0';
m_axis1_mm2s_tready <= '0';
-- Write to fifo if it is not full and data is valid
queue_wren <= '0';
ftch1_queue_empty <= '0';
ftch1_queue_full <= '0';
ftch1_pause <= '0';
queue_rden <= '0';
-- drive valid if fifo is not empty
m_axis_ftch1_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch1_tlast <= '0';
m_axis_ftch1_tdata <= (others => '0');
writing1_curdesc_out <= '0';
m_axis_ftch1_tdata_new <= (others => '0');
m_axis_ftch1_tvalid_new <= '0';
m_axis_ftch1_desc_available <= '0';
end generate GEN_NO_CH1_CTRL;
GEN_CH2_CTRL : if C_INCLUDE_S2MM =1 generate
begin
queue_sinit2 <= desc2_flush or not m_axi_sg_aresetn;
ftch_tready_ch2 <= (not queue_full2_new and ftch2_active);
m_axis2_mm2s_tready <= ftch_tready_ch2;
queue_wren2 <= '0';
-- Wr_en for S2MM BD FIFO
queue_wren2_new <= not queue_full2_new
and ftch_tvalid_new
and ftch2_active;
--queue_full2_new <= '1' when (queue_dcount2_new = "00100") else '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
ftch2_queue_empty <= queue_empty2_new;
ftch2_queue_full <= queue_full2_new;
ftch2_pause <= queue_full2_new;
queue_rden2 <= '0';
-- Rd_en for S2MM BD FIFO
queue_rden2_new <= not queue_empty2_new
and m_axis_ftch2_tready;
m_axis_ftch2_tvalid <= '0';
m_axis_ftch2_tvalid_new <= queue_dout2_valid; -- not queue_empty2_new and (not ch2_sg_idle);
m_axis_ftch2_desc_available <= not queue_empty2_new and (not ch2_sg_idle);
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
FTCH_FIELDS_64_2 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new_bd & queue_dout2_new_64 & queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_64_2;
FTCH_FIELDS_32_2 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
m_axis_ftch2_tdata_new <= queue_dout2_new (FIFO_WIDTH-1 downto FIFO_WIDTH-26) & "000000" & queue_dout2_new (FIFO_WIDTH-27 downto 0);
end generate FTCH_FIELDS_32_2;
writing2_curdesc_out <= writing_curdesc and ftch2_active;
end generate GEN_CH2_CTRL;
GEN_NO_CH2_CTRL : if C_INCLUDE_S2MM =0 generate
begin
ftch_tready_ch2 <= '0';
m_axis2_mm2s_tready <= '0';
queue_wren2 <= '0';
-- Pass fifo status back to fetch sm for channel IDLE determination
--ftch_queue_empty <= queue_empty; CR 621600
ftch2_queue_empty <= '0';
ftch2_queue_full <= '0';
ftch2_pause <= '0';
queue_rden2 <= '0';
m_axis_ftch2_tvalid <= '0';
-- Pass data out to port channel with MSB driving tlast
m_axis_ftch2_tlast <= '0';
m_axis_ftch2_tdata <= (others => '0');
m_axis_ftch2_tdata_new <= (others => '0');
m_axis_ftch2_tvalid_new <= '0';
writing2_curdesc_out <= '0';
m_axis_ftch2_desc_available <= '0';
end generate GEN_NO_CH2_CTRL;
-- If writing curdesc out then flag for proper mux selection
writing_curdesc <= curdesc_tvalid;
-- Map intnal signal to port
-- Map port to internal signal
writing_nxtdesc <= writing_nxtdesc_in;
end implementation;
| mit | f085e6ace2cf8e48d97b88c0a6ea197d | 0.476143 | 3.680398 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cmd_status.vhd | 1 | 19,774 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
Use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
| mit | e32a8397c9fa06c45786ea73f94613c6 | 0.422929 | 4.909136 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/bufgmux_fpga.vhd | 1 | 1,280 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Clock multiplexer with buffered output for Xilinx FPGA.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity bufgmux_fpga is
generic (
rf_frontend_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of bufgmux_fpga is
begin
good : if rf_frontend_ena generate
--! @details BUFGMUX suits much better to switch clock depending DIP[0]
--! signal, but ISE studio doesn't properly synth. such logic.
--! So here we will use ADC signal only.
--mux_buf : BUFGMUX
--port map (
-- O => O,
-- I0 => I1,
-- I1 => I2,
-- S => S
--);
mux_buf : BUFG
port map (
O => O,
I => I1
);
end generate;
bad : if not rf_frontend_ena generate
mux_buf : BUFG
port map (
O => O,
I => I2
);
end generate;
end;
| apache-2.0 | d461c98de76ade77d130b9f0c25d5cde | 0.489063 | 3.914373 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/fadd_d.vhd | 1 | 17,003 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity DoubleAdd is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_add : in std_logic;
i_sub : in std_logic;
i_eq : in std_logic;
i_lt : in std_logic;
i_le : in std_logic;
i_max : in std_logic;
i_min : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_DoubleAdd of DoubleAdd is
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(7 downto 0);
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
illegal_op : std_logic;
overflow : std_logic;
add : std_logic;
sub : std_logic;
eq : std_logic;
lt : std_logic;
le : std_logic;
max : std_logic;
min : std_logic;
flMore : std_logic;
flEqual : std_logic;
flLess : std_logic;
preShift : integer range 0 to 4095;
signOpMore : std_logic;
expMore : std_logic_vector(10 downto 0);
mantMore : std_logic_vector(52 downto 0);
mantLess : std_logic_vector(52 downto 0);
mantLessScale : std_logic_vector(104 downto 0);
mantSum : std_logic_vector(105 downto 0);
lshift : integer range 0 to 127;
mantAlign : std_logic_vector(104 downto 0);
expPostScale : std_logic_vector(11 downto 0);
expPostScaleInv : integer range 0 to 4095;
mantPostScale : std_logic_vector(104 downto 0);
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), (others => '0'), -- a, b, result
'0', '0', '0', '0', -- illegal_op, overflow, add, sub
'0', '0', '0', '0', '0', -- eq, lt, le, max, min
'0', '0', '0', -- flMore, flEqual, flLess
0, '0', (others => '0'), -- preShift, signOpMore, expMore
(others => '0'), (others => '0'), (others => '0'), -- mantMore, mantLess, mantLessScale
(others => '0'), 0, (others => '0'), -- mantSum, lshift, mantAlign
(others => '0'), 0, (others => '0') -- expPostScale, expPostScaleInv, mantPostScale
);
constant zero105 : std_logic_vector(104 downto 0) := (others => '0');
signal r, rin : RegistersType;
begin
-- registers:
comb : process(i_nrst, i_ena, i_add, i_sub, i_eq, i_lt, i_le, i_max, i_min,
i_a, i_b, r)
variable v : RegistersType;
variable signOp : std_logic;
variable signA : std_logic;
variable signB : std_logic;
variable signOpB : std_logic;
variable mantA : std_logic_vector(52 downto 0);
variable mantB : std_logic_vector(52 downto 0);
variable mantDif : std_logic_vector(53 downto 0);
variable expDif : std_logic_vector(11 downto 0);
variable v_flMore : std_logic;
variable v_flEqual : std_logic;
variable v_flLess : std_logic;
variable vb_preShift : std_logic_vector(11 downto 0);
variable v_signOpMore : std_logic;
variable vb_expMore : std_logic_vector(10 downto 0);
variable vb_mantMore : std_logic_vector(52 downto 0);
variable vb_mantLess : std_logic_vector(52 downto 0);
variable mantMoreScale : std_logic_vector(104 downto 0);
variable mantLessScale : std_logic_vector(104 downto 0);
variable vb_mantSum : std_logic_vector(105 downto 0);
variable vb_mantSumInv : std_logic_vector(104 downto 0);
variable vb_lshift : integer range 0 to 127;
variable vb_lshift_p1 : integer range 0 to 127;
variable vb_lshift_p2 : integer range 0 to 127;
variable vb_mantAlign : std_logic_vector(104 downto 0);
variable vb_expPostScale : std_logic_vector(11 downto 0);
variable vb_mantPostScale : std_logic_vector(104 downto 0);
variable mantShort : std_logic_vector(52 downto 0);
variable tmpMant05 : std_logic_vector(51 downto 0);
variable mantOnes : std_logic;
variable mantEven : std_logic;
variable mant05 : std_logic;
variable rndBit : std_logic;
variable mantZeroA : std_logic;
variable mantZeroB : std_logic;
variable allZero : std_logic;
variable sumZero : std_logic;
variable nanA : std_logic;
variable nanB : std_logic;
variable nanAB : std_logic;
variable overflow : std_logic;
variable resAdd : std_logic_vector(63 downto 0);
variable resEQ : std_logic_vector(63 downto 0);
variable resLT : std_logic_vector(63 downto 0);
variable resLE : std_logic_vector(63 downto 0);
variable resMax : std_logic_vector(63 downto 0);
variable resMin : std_logic_vector(63 downto 0);
begin
v := r;
v.ena := r.ena(6 downto 0) & (i_ena and not r.busy);
if i_ena = '1' then
v.busy := '1';
v.add := i_add;
v.sub := i_sub;
v.eq := i_eq;
v.lt := i_lt;
v.le := i_le;
v.max := i_max;
v.min := i_min;
v.a := i_a;
v.b := i_b;
v.illegal_op := '0';
v.overflow := '0';
end if;
signOp := r.sub or r.le or r.lt;
signA := r.a(63);
signB := r.b(63);
signOpB := signB xor signOp;
mantA(51 downto 0) := r.a(51 downto 0);
mantA(52) := '0';
if r.a(62 downto 52) /= zero105(10 downto 0) then
mantA(52) := '1';
end if;
mantB(51 downto 0) := r.b(51 downto 0);
mantB(52) := '0';
if r.b(62 downto 52) /= zero105(10 downto 0) then
mantB(52) := '1';
end if;
if r.a(62 downto 52) /= "00000000000" and r.b(62 downto 52) = "00000000000" then
expDif := ('0' & r.a(62 downto 52)) - "000000000001";
elsif r.a(62 downto 52) = "00000000000" and r.b(62 downto 52) /= "00000000000" then
expDif := "000000000001" - ('0' & r.b(62 downto 52));
else
expDif := ('0' & r.a(62 downto 52)) - ('0' & r.b(62 downto 52));
end if;
mantDif := ('0' & mantA) - ('0' & mantB);
if expDif = X"000" then
vb_preShift := expDif;
if mantDif = zero105(53 downto 0) then
v_flMore := not signA and (signA xor signB);
v_flEqual := not (signA xor signB);
v_flLess := signA and (signA xor signB);
v_signOpMore := signA;
vb_expMore := r.a(62 downto 52);
vb_mantMore := mantA;
vb_mantLess := mantB;
elsif mantDif(53) = '0' then -- A > B
v_flMore := not signA;
v_flEqual := '0';
v_flLess := signA;
v_signOpMore := signA;
vb_expMore := r.a(62 downto 52);
vb_mantMore := mantA;
vb_mantLess := mantB;
else
v_flMore := signB;
v_flEqual := '0';
v_flLess := not signB;
v_signOpMore := signOpB;
vb_expMore := r.b(62 downto 52);
vb_mantMore := mantB;
vb_mantLess := mantA;
end if;
elsif expDif(11) = '0' then
v_flMore := not signA;
v_flEqual := '0';
v_flLess := signA;
vb_preShift := expDif;
v_signOpMore := signA;
vb_expMore := r.a(62 downto 52);
vb_mantMore := mantA;
vb_mantLess := mantB;
else
v_flMore := signB;
v_flEqual := '0';
v_flLess := not signB;
vb_preShift := not expDif + 1;
v_signOpMore := signOpB;
vb_expMore := r.b(62 downto 52);
vb_mantMore := mantB;
vb_mantLess := mantA;
end if;
if r.ena(0) = '1' then
v.flMore := v_flMore;
v.flEqual := v_flEqual;
v.flLess := v_flLess;
v.preShift := conv_integer(vb_preShift);
v.signOpMore := v_signOpMore;
v.expMore := vb_expMore;
v.mantMore := vb_mantMore;
v.mantLess := vb_mantLess;
end if;
-- Pre-scale 105-bits mantissa if preShift < 105:
-- M = {mantM, 52'd0}
mantLessScale := r.mantLess & zero105(51 downto 0);
if r.ena(1) = '1' then
if r.preShift = 0 then
v.mantLessScale := mantLessScale;
else
v.mantLessScale := (others => '0');
for i in 1 to 104 loop
if i = r.preShift then
v.mantLessScale := zero105(i-1 downto 0) & mantLessScale(104 downto i);
end if;
end loop;
end if;
end if;
mantMoreScale := r.mantMore & zero105(51 downto 0);
-- 106-bits adder/subtractor
if (signA xor signOpB) = '1' then
vb_mantSum := ('0' & mantMoreScale) - ('0' & r.mantLessScale);
else
vb_mantSum := ('0' & mantMoreScale) + ('0' & r.mantLessScale);
end if;
if r.ena(2) = '1' then
v.mantSum := vb_mantSum;
end if;
-- To avoid timing constrains violation occured in Vivado Studio
-- try to implement parallel demuxultiplexer splitted on 2 parts
vb_mantSumInv(0) := '0';
for i in 0 to 103 loop
vb_mantSumInv(i + 1) := r.mantSum(103 - i);
end loop;
vb_lshift_p1 := 0;
for i in 0 to 63 loop
if vb_lshift_p1 = 0 and vb_mantSumInv(i) = '1' then
vb_lshift_p1 := i;
end if;
end loop;
vb_lshift_p2 := 0;
for i in 0 to 40 loop
if vb_lshift_p2 = 0 and vb_mantSumInv(64 + i) = '1' then
vb_lshift_p2 := 64 + i;
end if;
end loop;
-- multiplexer
if r.mantSum(105) = '1' then
-- shift right
vb_lshift := 127;
elsif r.mantSum(104) = '1' then
vb_lshift := 0;
elsif vb_lshift_p1 /= 0 then
vb_lshift := vb_lshift_p1;
else
vb_lshift := vb_lshift_p2;
end if;
if r.ena(3) = '1' then
v.lshift := vb_lshift;
end if;
-- Prepare to mantissa post-scale
vb_mantAlign := (others => '0');
if r.lshift = 127 then
vb_mantAlign := r.mantSum(105 downto 1);
elsif r.lshift = 0 then
vb_mantAlign := r.mantSum(104 downto 0);
else
for i in 1 to 104 loop
if i = r.lshift then
vb_mantAlign := r.mantSum(104-i downto 0) & zero105(i-1 downto 0);
end if;
end loop;
end if;
if r.lshift = 127 then
if r.expMore = "11111111111" then
vb_expPostScale := ('0' & r.expMore);
else
vb_expPostScale := ('0' & r.expMore) + 1;
end if;
else
if r.expMore = "00000000000" and r.lshift = 0 then
vb_expPostScale := X"001";
else
vb_expPostScale := ('0' & r.expMore) - conv_std_logic_vector(r.lshift, 12);
end if;
end if;
if (signA xor signOpB) = '1' then
-- subtractor only: result value becomes with exp=0
if r.expMore /= "00000000000" and
(vb_expPostScale(11) = '1' or vb_expPostScale = X"000") then
vb_expPostScale := vb_expPostScale - 1;
end if;
end if;
if r.ena(4) = '1' then
v.mantAlign := vb_mantAlign;
v.expPostScale := vb_expPostScale;
v.expPostScaleInv := conv_integer((not vb_expPostScale) + 1);
end if;
-- Mantissa post-scale:
-- Scaled = SumScale>>(-ExpSum) only if ExpSum < 0;
vb_mantPostScale := r.mantAlign;
if r.expPostScale(11) = '1' then
for i in 1 to 104 loop
if i = r.expPostScaleInv then
vb_mantPostScale := zero105(i-1 downto 0) & r.mantAlign(104 downto i);
end if;
end loop;
end if;
if r.ena(5) = '1' then
v.mantPostScale := vb_mantPostScale;
end if;
-- Rounding bit
mantShort := r.mantPostScale(104 downto 52);
tmpMant05 := r.mantPostScale(51 downto 0);
mantOnes := '0';
if mantShort(52) = '1' and mantShort(51 downto 0) = X"fffffffffffff" then
mantOnes := '1';
end if;
mantEven := r.mantPostScale(52);
mant05 := '0';
if tmpMant05 = X"8000000000000" then
mant05 := '1';
end if;
rndBit := r.mantPostScale(51) and not(mant05 and not mantEven);
-- Check Borders
mantZeroA := '0';
if r.a(51 downto 0) = zero105(51 downto 0) then
mantZeroA := '1';
end if;
mantZeroB := '0';
if r.b(51 downto 0) = zero105(51 downto 0) then
mantZeroB := '1';
end if;
-- Exceptions
allZero := '0';
if r.a(62 downto 0) = zero105(62 downto 0) and
r.b(62 downto 0) = zero105(62 downto 0) then
allZero := '1';
end if;
sumZero := '0';
if r.mantPostScale = zero105 then
sumZero := '1';
end if;
nanA := '0';
if r.a(62 downto 52) = "11111111111" then
nanA := '1';
end if;
nanB := '0';
if r.b(62 downto 52) = "11111111111" then
nanB := '1';
end if;
nanAB := nanA and mantZeroA and nanB and mantZeroB;
overflow := '0';
if r.expPostScale = X"7FF" then -- positive
overflow := '1';
end if;
-- Result multiplexers:
if (nanAB and signOp) = '1' then
resAdd(63) := signA xor signOpB;
elsif nanA = '1' then
-- when both values are NaN, value B has higher priority if sign=1
resAdd(63) := signA or (nanB and signOpB);
elsif nanB = '1' then
resAdd(63) := signOpB xor (signOp and not mantZeroB);
elsif allZero = '1' then
resAdd(63) := signA and signOpB;
elsif sumZero = '1' then
resAdd(63) := '0';
else
resAdd(63) := r.signOpMore;
end if;
if (nanA or nanB) = '1' then
resAdd(62 downto 52) := (others => '1');
elsif r.expPostScale(11) = '1' or sumZero = '1' then
resAdd(62 downto 52) := (others => '0');
else
resAdd(62 downto 52) := r.expPostScale(10 downto 0)
+ (mantOnes and rndBit and not r.overflow);
end if;
if (nanA and mantZeroA and nanB and mantZeroB) = '1' then
resAdd(51) := '1';
resAdd(50 downto 0) := (others => '0');
elsif nanA = '1' and (nanB and signOpB) = '0' then
-- when both values are NaN, value B has higher priority if sign=1
resAdd(51) := '1';
resAdd(50 downto 0) := r.a(50 downto 0);
elsif nanB = '1' then
resAdd(51) := '1';
resAdd(50 downto 0) := r.b(50 downto 0);
elsif r.overflow = '1' then
resAdd(51 downto 0) := (others => '0');
else
resAdd(51 downto 0) := mantShort(51 downto 0) + rndBit;
end if;
resEQ(63 downto 1) := (others => '0');
resEQ(0) := r.flEqual;
resLT(63 downto 1) := (others => '0');
resLT(0) := r.flLess;
resLE(63 downto 1) := (others => '0');
resLE(0) := r.flLess or r.flEqual;
if (nanA or nanB) = '1' then
resMax := r.b;
elsif r.flMore = '1' then
resMax := r.a;
else
resMax := r.b;
end if;
if (nanA or nanB) = '1' then
resMin := r.b;
elsif r.flLess = '1' then
resMin := r.a;
else
resMin := r.b;
end if;
if r.ena(6) = '1' then
if r.eq = '1' then
v.result := resEQ;
elsif r.lt = '1' then
v.result := resLT;
elsif r.le = '1' then
v.result := resLE;
elsif r.max = '1' then
v.result := resMax;
elsif r.min = '1' then
v.result := resMin;
else
v.result := resAdd;
end if;
v.illegal_op := nanA or nanB;
v.overflow := overflow;
v.busy := '0';
v.add := '0';
v.sub := '0';
v.eq := '0';
v.lt := '0';
v.le := '0';
v.max := '0';
v.min := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_illegal_op <= r.illegal_op;
o_overflow <= r.overflow;
o_valid <= r.ena(7);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | cf4c88fb6e4049cd6f1227ddf59ca0ea | 0.543081 | 3.218436 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_TELEGRAM_FILTER_SD1/DEB_50MZ_100MS_SRC.vhd | 38 | 2,643 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--Enprelleinheit
--entprellt bei 50 MHZ etw mit 100 ms
entity DEB_50MZ_100MS_SRC is
Port ( IN_DEB : in std_logic;
F_50MHZ : in std_logic;
OUT_DEB : out std_logic);
end DEB_50MZ_100MS_SRC;
architecture Behavioral of DEB_50MZ_100MS_SRC is
type SV_TYPE is (DEB0, DEB1);
signal SV, n_SV, SV_M : SV_TYPE;
signal COUNT_DEB, n_COUNT_DEB, COUNT_DEB_M: std_logic_vector (23 downto 0);
signal NOT_F_50MHZ : std_logic;
signal IN_DEB_S : std_logic;
constant CONST_DEB_max: std_logic_vector := x"4C4B40";
begin
IREG_PROC: process (IN_DEB, NOT_F_50MHZ)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then IN_DEB_S <= IN_DEB;
end if;
end process;
SREG_M_PROC: process (F_50MHZ, n_SV, n_COUNT_DEB, SV_M)
begin
if (F_50MHZ'event and F_50MHZ = '1')
then
SV_M <= n_SV;
COUNT_DEB_M <= n_COUNT_DEB;
else
COUNT_DEB_M <= COUNT_DEB_M;
end if;
end process;
NOT_F_50MHZ_PROC: process (F_50MHZ)
begin
NOT_F_50MHZ <= not F_50MHZ;
end process;
SREG_S_PROC: process (NOT_F_50MHZ, SV_M, COUNT_DEB_M)
begin
if (NOT_F_50MHZ'event and NOT_F_50MHZ = '1')
then
SV <= SV_M;
COUNT_DEB <= COUNT_DEB_M;
end if;
end process;
IL_OL_PROC: process (IN_DEB_S, SV, COUNT_DEB)
begin
case SV is
when DEB0 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB1;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB0;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '0';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB0;
end if;
end if;
when DEB1 =>
if (IN_DEB_S = '1')
then
if COUNT_DEB >= CONST_DEB_max
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB1;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB+1;
n_SV <= DEB1;
end if;
else
if COUNT_DEB = x"000000"
then
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB;
n_SV <= DEB0;
else
OUT_DEB <= '1';
n_COUNT_DEB <= COUNT_DEB-1;
n_SV <= DEB1;
end if;
end if;
when Others =>
OUT_DEB <= '0';
n_COUNT_DEB <= x"000000";
n_SV <= DEB0;
end case;
end process;
end Behavioral;
| gpl-2.0 | 6d0b1464262c74e7e150d6d65ec11b61 | 0.525161 | 2.790919 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_skid2mm_buf.vhd | 1 | 17,071 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_wr_demux;
-------------------------------------------------------------------------------
entity axi_sg_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_sg_skid2mm_buf;
architecture implementation of axi_sg_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_sg_v4_1_3.axi_sg_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
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`protect end_protected
| bsd-2-clause | 83e1929f14df817bf0b278aa332ea875 | 0.953091 | 1.817537 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_gen_prim_width.vhd | 27 | 70,652 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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M8AKmBfOkw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 50560)
`protect data_block
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`protect end_protected
| bsd-2-clause | a0ca8fe40ebbaa1e1fe21b181f373902 | 0.951778 | 1.819943 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_input_block.vhd | 27 | 45,404 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 31872)
`protect data_block
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| bsd-2-clause | 15fb47ced0ed723e9efbc0cf0b8920e0 | 0.948903 | 1.82492 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/commonlib/types_util.vhd | 1 | 5,905 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
| apache-2.0 | 6857ec6305a94ccacf92b2bf0e3bda37 | 0.588992 | 3.43314 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/reset_blk_ramfifo.vhd | 19 | 38,101 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26464)
`protect data_block
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`protect end_protected
| bsd-2-clause | 4c2d80ef972d49e3acd93dda1251cfae | 0.948269 | 1.833189 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/builtin_top.vhd | 19 | 47,568 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 33472)
`protect data_block
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`protect end_protected
| bsd-2-clause | 0a517125c6a650d729097fef1d1a9039 | 0.950408 | 1.82743 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/reset_builtin.vhd | 19 | 19,078 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
| bsd-2-clause | 55dd84be90515662f75ca2826027499a | 0.93904 | 1.841506 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/zynq/config_zynq.vhd | 1 | 2,583 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := zynq7000;
constant CFG_MEMTECH : integer := zynq7000;
constant CFG_PADTECH : integer := zynq7000;
constant CFG_JTAGTECH : integer := zynq7000;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20191206";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := false;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := false;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := false;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := false;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
| apache-2.0 | 16981d7df75358e550ecc954e4708914 | 0.69067 | 3.95559 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/builtin_top_v6.vhd | 19 | 52,905 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 37424)
`protect data_block
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`protect end_protected
| bsd-2-clause | d4fea298437b8ba5c932acd47fc35a21 | 0.95095 | 1.824562 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_datamover.vhd | 1 | 51,616 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
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-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
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-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
--
-- Description:
-- Top level VHDL wrapper for the AXI DataMover
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_mm2s_basic_wrap;
use axi_sg_v4_1_3.axi_sg_s2mm_basic_wrap;
-------------------------------------------------------------------------------
entity axi_sg_datamover is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- MM2S (Read) Store and Forward function
-- 0 = Omit MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_S2MM : Integer range 0 to 4 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1;
-- Specifies the constant value to output on
-- the ARID output port
C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the S2MM Command Interface
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if support for indeterminate packet lengths
-- are to be received on the input Stream interface
-- 0 = Omit support (User MUST transfer the exact number of
-- bytes on the Stream interface as specified in the BTT
-- field of the Corresponding DataMover Command)
-- 1 = Include support for indeterminate packet lengths
-- This causes FIFOs to be added and "Store and Forward"
-- behavior of the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ;
-- This parameter specifies the inclusion/omission of the
-- S2MM (Write) Store and Forward function
-- 0 = Omit S2MM Store and Forward
-- 1 = Include S2MM Store and Forward
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock input ----------------------------------
m_axi_mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
m_axi_mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0) ;
-- MM2S Halt request input control --------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------
-- Error discrete output -------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O ---------
m_axis_mm2s_cmdsts_aclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
s_axis_mm2s_cmd_tvalid : in std_logic; --
s_axis_mm2s_cmd_tready : out std_logic; --
s_axis_mm2s_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_MM2S_ADDR_WIDTH+40)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
m_axis_mm2s_sts_tvalid : out std_logic; --
m_axis_mm2s_sts_tready : in std_logic; --
m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); --
m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); --
m_axis_mm2s_sts_tlast : out std_logic; --
--------------------------------------------------------------------
-- Address Posting contols -----------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
--------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------------------
m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); --
-- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); --
-- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); --
-- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------
m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); --
m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); --
m_axi_mm2s_rlast : In std_logic; --
m_axi_mm2s_rvalid : In std_logic; --
m_axi_mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -------------------------------------------------------
m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : Out std_logic; --
m_axis_mm2s_tvalid : Out std_logic; --
m_axis_mm2s_tready : In std_logic; --
----------------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) ; --
-------------------------------------------------------------------------------
-- S2MM Primary Clock input ---------------------------------
m_axi_s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
m_axi_s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
-------------------------------------------------------------
-- S2MM Halt request input control ------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
-----------------------------------------------------
-- S2MM Error discrete output ------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
------------------------------------------------
-- Memory Map to Stream Command FIFO and Status FIFO I/O -----------------
m_axis_s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
m_axis_s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) --------------------------------------------------
s_axis_s2mm_cmd_tvalid : in std_logic; --
s_axis_s2mm_cmd_tready : out std_logic; --
s_axis_s2mm_cmd_tdata : in std_logic_vector(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+40)-1 downto 0); --
-----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------------------------------------------------
m_axis_s2mm_sts_tvalid : out std_logic; --
m_axis_s2mm_sts_tready : in std_logic; --
m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
m_axis_s2mm_sts_tlast : out std_logic; --
-------------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O ----------------------------------------------------
m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
m_axi_s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
m_axi_s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-------------------------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); --
-- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); --
-- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); --
-- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O --------------------------------------------------
m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); --
m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); --
m_axi_s2mm_wlast : Out std_logic; --
m_axi_s2mm_wvalid : Out std_logic; --
m_axi_s2mm_wready : In std_logic; --
-------------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -------------------------
m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); --
m_axi_s2mm_bvalid : In std_logic; --
m_axi_s2mm_bready : Out std_logic; --
----------------------------------------------------------------------
-- S2MM AXI Slave Stream Channel I/O -------------------------------------------------------
s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_tlast : In std_logic; --
s_axis_s2mm_tvalid : In std_logic; --
s_axis_s2mm_tready : Out std_logic; --
---------------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
------------------------------------------------------------------------
);
end entity axi_sg_datamover;
architecture implementation of axi_sg_datamover is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_clip_brst_len
--
-- Function Description:
-- This function is used to limit the parameterized max burst
-- databeats when the tranfer data width is 256 bits or greater.
-- This is required to keep from crossing the 4K byte xfer
-- boundary required by AXI. This process is further complicated
-- by the inclusion/omission of upsizers or downsizers in the
-- data path.
--
-------------------------------------------------------------------
function funct_clip_brst_len (param_burst_beats : integer;
mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0);
Variable fvar_max_burst_dbeats : Integer;
begin
-- coverage off
if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc
If (mmap_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (mmap_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (mmap_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit mmap width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
End if;
else -- use stream dwidth for calc
If (stream_transfer_bit_width <= 128) Then -- allowed
fvar_max_burst_dbeats := param_burst_beats;
Elsif (stream_transfer_bit_width <= 256) Then
If (param_burst_beats <= 128) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 128;
End if;
Elsif (stream_transfer_bit_width <= 512) Then
If (param_burst_beats <= 64) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 64;
End if;
Else -- 1024 bit stream width case
If (param_burst_beats <= 32) Then
fvar_max_burst_dbeats := param_burst_beats;
Else
fvar_max_burst_dbeats := 32;
End if;
-- coverage on
End if;
end if;
Return (fvar_max_burst_dbeats);
end function funct_clip_brst_len;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_depth_16
--
-- Function Description:
-- This function is used to fix the Command and Status FIFO depths to
-- 16 entries when Async clocking mode is enabled. This is required
-- due to the way the async_fifo_fg.vhd design in proc_common is
-- implemented.
-------------------------------------------------------------------
function funct_fix_depth_16 (async_clocking_mode : integer;
requested_depth : integer) return integer is
Variable fvar_depth_2_use : Integer;
begin
-- coverage off
If (async_clocking_mode = 1) Then -- async mode so fix at 16
fvar_depth_2_use := 16;
Elsif (requested_depth > 16) Then -- limit at 16
fvar_depth_2_use := 16;
-- coverage on
Else -- use requested depth
fvar_depth_2_use := requested_depth;
End if;
Return (fvar_depth_2_use);
end function funct_fix_depth_16;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_min_btt_width
--
-- Function Description:
-- This function calculates the minimum required value
-- for the used width of the command BTT field.
--
-------------------------------------------------------------------
function funct_get_min_btt_width (max_burst_beats : integer;
bytes_per_beat : integer ) return integer is
Variable var_min_btt_needed : Integer;
Variable var_max_bytes_per_burst : Integer;
begin
var_max_bytes_per_burst := max_burst_beats*bytes_per_beat;
-- coverage off
if (var_max_bytes_per_burst <= 16) then
var_min_btt_needed := 5;
elsif (var_max_bytes_per_burst <= 32) then
var_min_btt_needed := 6;
-- coverage on
elsif (var_max_bytes_per_burst <= 64) then
var_min_btt_needed := 7;
-- coverage off
elsif (var_max_bytes_per_burst <= 128) then
var_min_btt_needed := 8;
elsif (var_max_bytes_per_burst <= 256) then
var_min_btt_needed := 9;
elsif (var_max_bytes_per_burst <= 512) then
var_min_btt_needed := 10;
elsif (var_max_bytes_per_burst <= 1024) then
var_min_btt_needed := 11;
elsif (var_max_bytes_per_burst <= 2048) then
var_min_btt_needed := 12;
elsif (var_max_bytes_per_burst <= 4096) then
var_min_btt_needed := 13;
else -- 8K byte range
var_min_btt_needed := 14;
end if;
-- coverage on
Return (var_min_btt_needed);
end function funct_get_min_btt_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_xfer_bytes_per_dbeat
--
-- Function Description:
-- Calculates the nuber of bytes that will transfered per databeat
-- on the AXI4 MMap Bus.
--
-------------------------------------------------------------------
function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer;
stream_transfer_bit_width : integer;
down_up_sizers_enabled : integer) return integer is
Variable temp_bytes_per_dbeat : Integer := 4;
begin
-- coverage off
if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth
temp_bytes_per_dbeat := mmap_transfer_bit_width/8;
-- coverage on
else -- No down/up sizers so use Stream data width
temp_bytes_per_dbeat := stream_transfer_bit_width/8;
end if;
Return (temp_bytes_per_dbeat);
end function funct_get_xfer_bytes_per_dbeat;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_fix_btt_used
--
-- Function Description:
-- THis function makes sure the BTT width used is at least the
-- minimum needed.
--
-------------------------------------------------------------------
function funct_fix_btt_used (requested_btt_width : integer;
min_btt_width : integer) return integer is
Variable var_corrected_btt_width : Integer;
begin
-- coverage off
If (requested_btt_width < min_btt_width) Then
var_corrected_btt_width := min_btt_width;
-- coverage on
else
var_corrected_btt_width := requested_btt_width;
End if;
Return (var_corrected_btt_width);
end function funct_fix_btt_used;
-------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------
Constant MM2S_TAG_WIDTH : integer := 4;
Constant S2MM_TAG_WIDTH : integer := 4;
Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF;
Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT;
Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE,
C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE,
C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC,
C_MM2S_STSCMD_FIFO_DEPTH);
Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC,
C_S2MM_STSCMD_FIFO_DEPTH);
Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH,
C_M_AXIS_MM2S_TDATA_WIDTH,
MM2S_DOWNSIZER_ENABLED);
Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS,
MM2S_BYTES_PER_BEAT);
Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED,
MM2S_MIN_BTT_NEEDED);
Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH,
C_S_AXIS_S2MM_TDATA_WIDTH,
S2MM_UPSIZER_ENABLED);
Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS,
S2MM_BYTES_PER_BEAT);
Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED,
S2MM_MIN_BTT_NEEDED);
-- Signals
signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0');
signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0');
begin --(architecture implementation)
-------------------------------------------------------------
-- Conversion to tkeep for external stream connnections
-------------------------------------------------------------
-- MM2S Stream Output
m_axis_mm2s_tkeep <= sig_mm2s_tstrb ;
-- MM2S Status Stream Output
m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ;
-- S2MM Stream Input
sig_s2mm_tstrb <= s_axis_s2mm_tkeep ;
-- S2MM Status Stream Output
m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_MM2S_BASIC
--
-- If Generate Description:
-- Instantiate the MM2S Basic Wrapper
--
--
------------------------------------------------------------
GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate
begin
------------------------------------------------------------
-- Instance: I_MM2S_BASIC_WRAPPER
--
-- Description:
-- Read Basic Wrapper Instance
--
------------------------------------------------------------
I_MM2S_BASIC_WRAPPER : entity axi_sg_v4_1_3.axi_sg_mm2s_basic_wrap
generic map (
C_INCLUDE_MM2S => C_INCLUDE_MM2S ,
C_MM2S_ARID => C_M_AXI_MM2S_ARID ,
C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH ,
C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH ,
C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH ,
C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO ,
C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH ,
C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC ,
C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE ,
C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS ,
C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED ,
C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => MM2S_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
mm2s_aclk => m_axi_mm2s_aclk ,
mm2s_aresetn => m_axi_mm2s_aresetn ,
sg_ctl => sg_ctl ,
mm2s_halt => mm2s_halt ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
mm2s_err => mm2s_err ,
mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk ,
mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn ,
mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid ,
mm2s_cmd_wready => s_axis_mm2s_cmd_tready ,
mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata ,
mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid ,
mm2s_sts_wready => m_axis_mm2s_sts_tready ,
mm2s_sts_wdata => m_axis_mm2s_sts_tdata ,
mm2s_sts_wstrb => sig_mm2s_sts_tstrb ,
mm2s_sts_wlast => m_axis_mm2s_sts_tlast ,
mm2s_allow_addr_req => mm2s_allow_addr_req ,
mm2s_addr_req_posted => mm2s_addr_req_posted ,
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
mm2s_arid => m_axi_mm2s_arid ,
mm2s_araddr => m_axi_mm2s_araddr ,
mm2s_arlen => m_axi_mm2s_arlen ,
mm2s_arsize => m_axi_mm2s_arsize ,
mm2s_arburst => m_axi_mm2s_arburst ,
mm2s_arprot => m_axi_mm2s_arprot ,
mm2s_arcache => m_axi_mm2s_arcache ,
mm2s_aruser => m_axi_mm2s_aruser ,
mm2s_arvalid => m_axi_mm2s_arvalid ,
mm2s_arready => m_axi_mm2s_arready ,
mm2s_rdata => m_axi_mm2s_rdata ,
mm2s_rresp => m_axi_mm2s_rresp ,
mm2s_rlast => m_axi_mm2s_rlast ,
mm2s_rvalid => m_axi_mm2s_rvalid ,
mm2s_rready => m_axi_mm2s_rready ,
mm2s_strm_wdata => m_axis_mm2s_tdata ,
mm2s_strm_wstrb => sig_mm2s_tstrb ,
mm2s_strm_wlast => m_axis_mm2s_tlast ,
mm2s_strm_wvalid => m_axis_mm2s_tvalid ,
mm2s_strm_wready => m_axis_mm2s_tready ,
mm2s_dbg_sel => mm2s_dbg_sel ,
mm2s_dbg_data => mm2s_dbg_data
);
end generate GEN_MM2S_BASIC;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_S2MM_BASIC
--
-- If Generate Description:
-- Instantiate the S2MM Basic Wrapper
--
--
------------------------------------------------------------
GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate
begin
------------------------------------------------------------
-- Instance: I_S2MM_BASIC_WRAPPER
--
-- Description:
-- Write Basic Wrapper Instance
--
------------------------------------------------------------
I_S2MM_BASIC_WRAPPER : entity axi_sg_v4_1_3.axi_sg_s2mm_basic_wrap
generic map (
C_INCLUDE_S2MM => C_INCLUDE_S2MM ,
C_S2MM_AWID => C_M_AXI_S2MM_AWID ,
C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH ,
C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH ,
C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH ,
C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO ,
C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH ,
C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC ,
C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE ,
C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS ,
C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH ,
C_TAG_WIDTH => S2MM_TAG_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_FAMILY => C_FAMILY
)
port map (
s2mm_aclk => m_axi_s2mm_aclk ,
s2mm_aresetn => m_axi_s2mm_aresetn ,
sg_ctl => sg_ctl ,
s2mm_halt => s2mm_halt ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
s2mm_err => s2mm_err ,
s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk ,
s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn ,
s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid ,
s2mm_cmd_wready => s_axis_s2mm_cmd_tready ,
s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata ,
s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid ,
s2mm_sts_wready => m_axis_s2mm_sts_tready ,
s2mm_sts_wdata => m_axis_s2mm_sts_tdata ,
s2mm_sts_wstrb => sig_s2mm_sts_tstrb ,
s2mm_sts_wlast => m_axis_s2mm_sts_tlast ,
s2mm_allow_addr_req => s2mm_allow_addr_req ,
s2mm_addr_req_posted => s2mm_addr_req_posted ,
s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
s2mm_awid => m_axi_s2mm_awid ,
s2mm_awaddr => m_axi_s2mm_awaddr ,
s2mm_awlen => m_axi_s2mm_awlen ,
s2mm_awsize => m_axi_s2mm_awsize ,
s2mm_awburst => m_axi_s2mm_awburst ,
s2mm_awprot => m_axi_s2mm_awprot ,
s2mm_awcache => m_axi_s2mm_awcache ,
s2mm_awuser => m_axi_s2mm_awuser ,
s2mm_awvalid => m_axi_s2mm_awvalid ,
s2mm_awready => m_axi_s2mm_awready ,
s2mm_wdata => m_axi_s2mm_wdata ,
s2mm_wstrb => m_axi_s2mm_wstrb ,
s2mm_wlast => m_axi_s2mm_wlast ,
s2mm_wvalid => m_axi_s2mm_wvalid ,
s2mm_wready => m_axi_s2mm_wready ,
s2mm_bresp => m_axi_s2mm_bresp ,
s2mm_bvalid => m_axi_s2mm_bvalid ,
s2mm_bready => m_axi_s2mm_bready ,
s2mm_strm_wdata => s_axis_s2mm_tdata ,
s2mm_strm_wstrb => sig_s2mm_tstrb ,
s2mm_strm_wlast => s_axis_s2mm_tlast ,
s2mm_strm_wvalid => s_axis_s2mm_tvalid ,
s2mm_strm_wready => s_axis_s2mm_tready ,
s2mm_dbg_sel => s2mm_dbg_sel ,
s2mm_dbg_data => s2mm_dbg_data
);
end generate GEN_S2MM_BASIC;
end implementation;
| mit | ca94f829f61e4f8bf509863c0c7b9e09 | 0.407645 | 4.605693 | false | false | false | false |
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`protect end_protected
| bsd-2-clause | a3b83778b9d992b173e230f5c270aac8 | 0.939322 | 1.866074 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/common/rd_pe_ss.vhd | 19 | 28,350 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 19248)
`protect data_block
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| bsd-2-clause | 891a51ce4d52df1ccaba92500deaec47 | 0.944868 | 1.837568 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/pll/clkp90_v6.vhd | 3 | 943 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Clock phase offset generator (90 deg) for FPGA Virtex6.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clkp90_virtex6 is port (
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic
);
end clkp90_virtex6;
architecture rtl of clkp90_virtex6 is
signal clk_buf : std_logic;
begin
x0 : BUFG port map (
O => clk_buf,
I => i_clk
);
x1 : ODDR port map (
Q => o_clkp90,
C => clk_buf,
CE => '1',
D1 => '0',
D2 => '1',
R => '0',
S => '0'
);
o_clk <= clk_buf;
end;
| apache-2.0 | 2b6218863e3b400e4ea8bd284f5969f9 | 0.4772 | 3.698039 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/rocketlib/tl2axi.vhd | 1 | 9,203 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief TileLink-to-AXI4 bridge implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library rocketlib;
use rocketlib.types_rocket.all;
entity Tile2Axi is
port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_in_type
);
end;
architecture arch_Tile2Axi of Tile2Axi is
component TLToAXI4
port (
clock : in std_logic;
reset : in std_logic;
io_in_0_a_ready : out std_logic;
io_in_0_a_valid : in std_logic;
io_in_0_a_bits_opcode : in std_logic_vector(2 downto 0);
io_in_0_a_bits_param : in std_logic_vector(2 downto 0);
io_in_0_a_bits_size : in std_logic_vector(3 downto 0);
io_in_0_a_bits_source : in std_logic_vector(5 downto 0);
io_in_0_a_bits_address : in std_logic_vector(31 downto 0);
io_in_0_a_bits_mask : in std_logic_vector(7 downto 0);
io_in_0_a_bits_data : in std_logic_vector(63 downto 0);
io_in_0_b_ready : in std_logic;
io_in_0_b_valid : out std_logic;
io_in_0_b_bits_opcode : out std_logic_vector(2 downto 0);
io_in_0_b_bits_param : out std_logic_vector(1 downto 0);
io_in_0_b_bits_size : out std_logic_vector(3 downto 0);
io_in_0_b_bits_source : out std_logic_vector(5 downto 0);
io_in_0_b_bits_address : out std_logic_vector(31 downto 0);
io_in_0_b_bits_mask : out std_logic_vector(7 downto 0);
io_in_0_b_bits_data : out std_logic_vector(63 downto 0);
io_in_0_c_ready : out std_logic;
io_in_0_c_valid : in std_logic;
io_in_0_c_bits_opcode : in std_logic_vector(2 downto 0);
io_in_0_c_bits_param : in std_logic_vector(2 downto 0);
io_in_0_c_bits_size : in std_logic_vector(3 downto 0);
io_in_0_c_bits_source : in std_logic_vector(5 downto 0);
io_in_0_c_bits_address : in std_logic_vector(31 downto 0);
io_in_0_c_bits_data : in std_logic_vector(63 downto 0);
io_in_0_c_bits_error : in std_logic;
io_in_0_d_ready : in std_logic;
io_in_0_d_valid : out std_logic;
io_in_0_d_bits_opcode : out std_logic_vector(2 downto 0);
io_in_0_d_bits_param : out std_logic_vector(1 downto 0);
io_in_0_d_bits_size : out std_logic_vector(3 downto 0);
io_in_0_d_bits_source : out std_logic_vector(5 downto 0);
io_in_0_d_bits_sink : out std_logic;
io_in_0_d_bits_addr_lo : out std_logic_vector(2 downto 0);
io_in_0_d_bits_data : out std_logic_vector(63 downto 0);
io_in_0_d_bits_error : out std_logic;
io_in_0_e_ready : out std_logic;
io_in_0_e_valid : in std_logic;
io_in_0_e_bits_sink : in std_logic;
io_out_0_aw_ready : in std_logic;
io_out_0_aw_valid : out std_logic;
io_out_0_aw_bits_id : out std_logic_vector(3 downto 0);
io_out_0_aw_bits_addr : out std_logic_vector(31 downto 0);
io_out_0_aw_bits_len : out std_logic_vector(7 downto 0);
io_out_0_aw_bits_size : out std_logic_vector(2 downto 0);
io_out_0_aw_bits_burst : out std_logic_vector(1 downto 0);
io_out_0_aw_bits_lock : out std_logic;
io_out_0_aw_bits_cache : out std_logic_vector(3 downto 0);
io_out_0_aw_bits_prot : out std_logic_vector(2 downto 0);
io_out_0_aw_bits_qos : out std_logic_vector(3 downto 0);
io_out_0_w_ready : in std_logic;
io_out_0_w_valid : out std_logic;
io_out_0_w_bits_data : out std_logic_vector(63 downto 0);
io_out_0_w_bits_strb : out std_logic_vector(7 downto 0);
io_out_0_w_bits_last : out std_logic;
io_out_0_b_ready : out std_logic;
io_out_0_b_valid : in std_logic;
io_out_0_b_bits_id : in std_logic_vector(3 downto 0);
io_out_0_b_bits_resp : in std_logic_vector(1 downto 0);
io_out_0_ar_ready : in std_logic;
io_out_0_ar_valid : out std_logic;
io_out_0_ar_bits_id : out std_logic_vector(3 downto 0);
io_out_0_ar_bits_addr : out std_logic_vector(31 downto 0);
io_out_0_ar_bits_len : out std_logic_vector(7 downto 0);
io_out_0_ar_bits_size : out std_logic_vector(2 downto 0);
io_out_0_ar_bits_burst : out std_logic_vector(1 downto 0);
io_out_0_ar_bits_lock : out std_logic;
io_out_0_ar_bits_cache : out std_logic_vector(3 downto 0);
io_out_0_ar_bits_prot : out std_logic_vector(2 downto 0);
io_out_0_ar_bits_qos : out std_logic_vector(3 downto 0);
io_out_0_r_ready : out std_logic;
io_out_0_r_valid : in std_logic;
io_out_0_r_bits_id : in std_logic_vector(3 downto 0);
io_out_0_r_bits_data : in std_logic_vector(63 downto 0);
io_out_0_r_bits_resp : in std_logic_vector(1 downto 0);
io_out_0_r_bits_last : in std_logic
);
end component;
signal reset : std_logic;
signal wb_a_source : std_logic_vector(5 downto 0);
signal wb_b_source : std_logic_vector(5 downto 0);
signal wb_c_source : std_logic_vector(5 downto 0);
signal wb_d_source : std_logic_vector(5 downto 0);
signal wb_aw_bits_addr : std_logic_vector(31 downto 0);
signal wb_ar_bits_addr : std_logic_vector(31 downto 0);
begin
reset <= not nrst;
wb_a_source <= "000" & tloi.a_source;
tlio.b_source <= wb_b_source(2 downto 0);
wb_c_source <= "000" & tloi.c_source;
tlio.d_source <= wb_d_source(2 downto 0);
tlio.d_sink(3 downto 1) <= "000";
ver0 : TLToAXI4 port map (
clock => clk,
reset => reset,
io_in_0_a_ready => tlio.a_ready,
io_in_0_a_valid => tloi.a_valid,
io_in_0_a_bits_opcode => tloi.a_opcode,
io_in_0_a_bits_param => tloi.a_param,
io_in_0_a_bits_size => tloi.a_size,
io_in_0_a_bits_source => wb_a_source,
io_in_0_a_bits_address => tloi.a_address,
io_in_0_a_bits_mask => tloi.a_mask,
io_in_0_a_bits_data => tloi.a_data,
io_in_0_b_ready => tloi.b_ready,
io_in_0_b_valid => tlio.b_valid,
io_in_0_b_bits_opcode => tlio.b_opcode,
io_in_0_b_bits_param => tlio.b_param,
io_in_0_b_bits_size => tlio.b_size,
io_in_0_b_bits_source => wb_b_source,
io_in_0_b_bits_address => tlio.b_address,
io_in_0_b_bits_mask => tlio.b_mask,
io_in_0_b_bits_data => tlio.b_data,
io_in_0_c_ready => tlio.c_ready,
io_in_0_c_valid => tloi.c_valid,
io_in_0_c_bits_opcode => tloi.c_opcode,
io_in_0_c_bits_param => tloi.c_param,
io_in_0_c_bits_size => tloi.c_size,
io_in_0_c_bits_source => wb_c_source,
io_in_0_c_bits_address => tloi.c_address,
io_in_0_c_bits_data => tloi.c_data,
io_in_0_c_bits_error => tloi.c_error,
io_in_0_d_ready => tloi.d_ready,
io_in_0_d_valid => tlio.d_valid,
io_in_0_d_bits_opcode => tlio.d_opcode,
io_in_0_d_bits_param => tlio.d_param,
io_in_0_d_bits_size => tlio.d_size,
io_in_0_d_bits_source => wb_d_source,
io_in_0_d_bits_sink => tlio.d_sink(0),
io_in_0_d_bits_addr_lo => tlio.d_addr_lo,
io_in_0_d_bits_data => tlio.d_data,
io_in_0_d_bits_error => tlio.d_error,
io_in_0_e_ready => tlio.e_ready,
io_in_0_e_valid => tloi.e_valid,
io_in_0_e_bits_sink => tloi.e_sink(0),
io_out_0_aw_ready => msti.aw_ready,
io_out_0_aw_valid => msto.aw_valid,
io_out_0_aw_bits_id => msto.aw_id(3 downto 0),
io_out_0_aw_bits_addr => wb_aw_bits_addr,
io_out_0_aw_bits_len => msto.aw_bits.len,
io_out_0_aw_bits_size => msto.aw_bits.size,
io_out_0_aw_bits_burst => msto.aw_bits.burst,
io_out_0_aw_bits_lock => msto.aw_bits.lock,
io_out_0_aw_bits_cache => msto.aw_bits.cache,
io_out_0_aw_bits_prot => msto.aw_bits.prot,
io_out_0_aw_bits_qos => msto.aw_bits.qos,
io_out_0_w_ready => msti.w_ready,
io_out_0_w_valid => msto.w_valid,
io_out_0_w_bits_data => msto.w_data,
io_out_0_w_bits_strb => msto.w_strb,
io_out_0_w_bits_last => msto.w_last,
io_out_0_b_ready => msto.b_ready,
io_out_0_b_valid => msti.b_valid,
io_out_0_b_bits_id => msti.b_id(3 downto 0),
io_out_0_b_bits_resp => msti.b_resp,
io_out_0_ar_ready => msti.ar_ready,
io_out_0_ar_valid => msto.ar_valid,
io_out_0_ar_bits_id => msto.ar_id(3 downto 0),
io_out_0_ar_bits_addr => wb_ar_bits_addr,
io_out_0_ar_bits_len => msto.ar_bits.len,
io_out_0_ar_bits_size => msto.ar_bits.size,
io_out_0_ar_bits_burst => msto.ar_bits.burst,
io_out_0_ar_bits_lock => msto.ar_bits.lock,
io_out_0_ar_bits_cache => msto.ar_bits.cache,
io_out_0_ar_bits_prot => msto.ar_bits.prot,
io_out_0_ar_bits_qos => msto.ar_bits.qos,
io_out_0_r_ready => msto.r_ready,
io_out_0_r_valid => msti.r_valid,
io_out_0_r_bits_id => msti.r_id(3 downto 0),
io_out_0_r_bits_data => msti.r_data,
io_out_0_r_bits_resp => msti.r_resp,
io_out_0_r_bits_last => msti.r_last
);
msto.aw_bits.addr <= wb_aw_bits_addr(31 downto 3) & "000";
msto.ar_bits.addr <= wb_ar_bits_addr(31 downto 3) & "000";
end;
| apache-2.0 | 8ff3809c1087dbd6e9ab4c08915aeef5 | 0.616538 | 2.472595 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_queue.vhd | 1 | 53,326 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_queue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_MM2S : integer range 0 to 1 := 0;
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s_axis_updt_aclk : in std_logic ; --
--
--********************************-- --
--** Control and Status **-- --
--********************************-- --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--********************************-- --
--** Update Interfaces In **-- --
--********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--********************************-- --
--** Update Interfaces Out **-- --
--********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_queue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_queue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-- Number of words deep fifo needs to be. Depth required to store 2 word
-- porters for each descriptor is C_SG_UPDT_DESC2QUEUE x 2
--constant UPDATE_QUEUE_DEPTH : integer := max2(16,C_SG_UPDT_DESC2QUEUE * 2);
constant UPDATE_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE * 2));
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_QUEUE_CNT_WIDTH : integer := clog2(UPDATE_QUEUE_DEPTH+1);
-- Select between BRAM or LOGIC memory type
constant UPD_Q_MEMORY_TYPE : integer := bo2int(UPDATE_QUEUE_DEPTH > 16);
-- Number of words deep fifo needs to be. Depth required to store all update
-- words is C_SG_UPDT_DESC2QUEUE x C_SG_WORDS_TO_UPDATE
constant UPDATE_STS_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG_WORDS_TO_UPDATE));
constant UPDATE_STS2_QUEUE_DEPTH : integer := max2(16,pad_power2(C_SG_UPDT_DESC2QUEUE
* C_SG2_WORDS_TO_UPDATE));
-- Select between BRAM or LOGIC memory type
constant STS_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS_QUEUE_DEPTH > 16);
-- Select between BRAM or LOGIC memory type
constant STS2_Q_MEMORY_TYPE : integer := bo2int(UPDATE_STS2_QUEUE_DEPTH > 16);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant UPDATE_STS_QUEUE_CNT_WIDTH : integer := clog2(C_SG_UPDT_DESC2QUEUE+1);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_lsb_sm : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal write_curdesc_lsb1 : std_logic := '0';
signal write_curdesc_msb1 : std_logic := '0';
signal rden_del : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_d2 : std_logic := '0';
signal updt_active_re1 : std_logic := '0';
signal updt_active_re2 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
-- State Machine Signal
signal writing_status : std_logic := '0';
signal dataq_rden : std_logic := '0';
signal stsq_rden : std_logic := '0';
-- Pointer Queue FIFO Signals
signal ptr_queue_rden : std_logic := '0';
signal ptr_queue_wren : std_logic := '0';
signal ptr_queue_empty : std_logic := '0';
signal ptr_queue_full : std_logic := '0';
signal ptr_queue_din : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr_queue_dout_int : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts_queue_wren : std_logic := '0';
signal sts_queue_rden : std_logic := '0';
signal sts_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts_queue_dout_int : std_logic_vector (3 downto 0) := (others => '0');
signal sts_queue_full : std_logic := '0';
signal sts_queue_empty : std_logic := '0';
signal ptr2_queue_rden : std_logic := '0';
signal ptr2_queue_wren : std_logic := '0';
signal ptr2_queue_empty : std_logic := '0';
signal ptr2_queue_full : std_logic := '0';
signal ptr2_queue_din : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ptr2_queue_dout : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Status Queue FIFO Signals
signal sts2_queue_wren : std_logic := '0';
signal sts2_queue_rden : std_logic := '0';
signal sts2_queue_din : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_dout : std_logic_vector
(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal sts2_queue_full : std_logic := '0';
signal sts2_queue_empty : std_logic := '0';
signal sts2_queue_empty_del : std_logic := '0';
signal sts2_dout_valid : std_logic := '0';
signal sts_dout_valid : std_logic := '0';
signal sts2_dout_valid_del : std_logic := '0';
signal valid_new : std_logic := '0';
signal valid_latch : std_logic := '0';
signal valid1_new : std_logic := '0';
signal valid1_latch : std_logic := '0';
signal empty_low : std_logic := '0';
-- Misc Support Signals
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal sinit : std_logic := '0';
signal updt_tvalid : std_logic := '0';
signal updt_tlast : std_logic := '0';
signal updt2_tvalid : std_logic := '0';
signal updt2_tlast : std_logic := '0';
signal status_d1, status_d2 : std_logic := '0';
signal updt_tvalid_int : std_logic := '0';
signal updt_tlast_int : std_logic := '0';
signal ptr_queue_empty_int : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal follower_reg_mm2s : std_logic_vector (33 downto 0) := (others => '0');
signal follower_full_mm2s :std_logic := '0';
signal follower_empty_mm2s : std_logic := '0';
signal follower_reg_s2mm : std_logic_vector (33 downto 0) := (others => '0');
signal follower_full_s2mm :std_logic := '0';
signal follower_empty_s2mm : std_logic := '0';
signal follower_reg, m_axis_updt_tdata_tmp : std_logic_vector (33 downto 0);
signal follower_full :std_logic := '0';
signal follower_empty : std_logic := '0';
signal sts_rden : std_logic := '0';
signal sts2_rden : std_logic := '0';
signal follower_tlast : std_logic := '0';
signal follower_reg_image : std_logic := '0';
signal m_axis_updt_tready_mm2s, m_axis_updt_tready_s2mm : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= follower_reg_mm2s (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) when updt_active = '1'
else follower_reg_s2mm (C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0) ;
m_axis_updt_tvalid <= updt_tvalid when updt_active = '1'
else updt2_tvalid;
m_axis_updt_tlast <= updt_tlast when updt_active = '1'
else updt2_tlast;
m_axis_updt_tready_mm2s <= m_axis_updt_tready when updt_active = '1' else '0';
m_axis_updt_tready_s2mm <= m_axis_updt_tready when updt2_active = '1' else '0';
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- channel 1
updt_active_re <= updt_active_re1 or updt_active_re2;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_re,
ptr_queue_empty_int,
m_axis_updt_tready,
updt_tvalid_int,
updt_tlast_int)
begin
write_curdesc_lsb_sm <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
dataq_rden <= '0';
stsq_rden <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if(updt_active_re = '1')then
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor pointer
-- Reads one word from data queue fifo
---------------------------------------------------------------
when READ_CURDESC_LSB =>
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(ptr_queue_empty_int = '0')then
write_curdesc_lsb_sm <= '1';
dataq_rden <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS; --READ_CURDESC_MSB;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
---------------------------------------------------------------
-- Get upper current descriptor
-- Reads one word from data queue fifo
---------------------------------------------------------------
-- when READ_CURDESC_MSB =>
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
-- if(ptr_queue_empty_int = '0')then
-- dataq_rden <= '1';
-- write_curdesc_msb <= '1';
-- pntr_ns <= WRITE_STATUS;
-- else
-- -- coverage off
-- pntr_ns <= READ_CURDESC_MSB;
-- -- coverage on
-- end if;
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
-- De-MUX appropriage tvalid/tlast signals
writing_status <= '1';
-- Enable reading of Status Queue if datamover can
-- accept data
stsq_rden <= m_axis_updt_tready;
-- Hold in the status state until tlast is pulled
-- from status fifo
if(updt_tvalid_int = '1' and m_axis_updt_tready = '1'
and updt_tlast_int = '1')then
-- if(follower_full = '1' and m_axis_updt_tready = '1'
-- and follower_tlast = '1')then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
updt_tvalid_int <= updt_tvalid or updt2_tvalid;
updt_tlast_int <= updt_tlast or updt2_tlast;
ptr_queue_empty_int <= ptr_queue_empty when updt_active = '1' else
ptr2_queue_empty when updt2_active = '1' else
'1';
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
GEN_Q_FOR_SYNC : if C_AXIS_IS_ASYNC = 0 generate
begin
MM2S_CHANNEL : if C_INCLUDE_MM2S = 1 generate
updt_tvalid <= follower_full_mm2s and updt_active;
updt_tlast <= follower_reg_mm2s(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt_active;
sts_rden <= follower_empty_mm2s and (not sts_queue_empty); -- and updt_active;
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_mm2s = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (sts_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (sts_rden = '1') then
follower_reg_mm2s <= sts_queue_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re1 <= updt_active and not updt_active_d1;
-- I_UPDT_DATA_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr_queue_wren ,
-- Data_In => ptr_queue_din ,
-- FIFO_Read => ptr_queue_rden ,
-- Data_Out => ptr_queue_dout ,
-- FIFO_Empty => ptr_queue_empty ,
-- FIFO_Full => ptr_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr_queue_dout <= (others => '0');
elsif (ptr_queue_wren = '1') then
ptr_queue_dout <= ptr_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr_queue_rden = '1') then
ptr_queue_empty <= '1';
ptr_queue_full <= '0';
elsif (ptr_queue_wren = '1') then
ptr_queue_empty <= '0';
ptr_queue_full <= '1';
end if;
end if;
end process;
-- Channel Pointer Queue (Generate Synchronous FIFO)
-- I_UPDT_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
-- generic map (
-- C_DWIDTH => 34 ,
-- C_DEPTH => 4 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => sts_queue_wren ,
-- Data_In => sts_queue_din ,
-- FIFO_Read => sts_rden, --sts_queue_rden ,
-- Data_Out => sts_queue_dout ,
-- FIFO_Empty => sts_queue_empty ,
-- FIFO_Full => sts_queue_full ,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts_queue_dout <= (others => '0');
elsif (sts_queue_wren = '1') then
sts_queue_dout <= sts_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts_rden = '1') then
sts_queue_empty <= '1';
sts_queue_full <= '0';
elsif (sts_queue_wren = '1') then
sts_queue_empty <= '0';
sts_queue_full <= '1';
end if;
end if;
end process;
-- Channel Status Queue (Generate Synchronous FIFO)
--*****************************************
--** Channel Data Port Side of Queues
--*****************************************
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis_updtptr_tdata( -- DESC DATA
C_M_AXI_SG_ADDR_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr_queue_wren <= s_axis_updtptr_tvalid -- TValid
and not ptr_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis_updtptr_tready <= not ptr_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis_updtsts_tlast; -- Store with tlast
sts_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts_queue_wren <= s_axis_updtsts_tvalid
and not sts_queue_full;
-- Drive channel port with ready if room in status queue
s_axis_updtsts_tready <= not sts_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
-- updt_queue_empty <= ptr_queue_empty
-- or (sts_queue_empty and follower_empty and updt_active);
updt_queue_empty <= ptr_queue_empty
or follower_empty_mm2s; -- and updt_active);
-- Data queue read enable
ptr_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr_queue_empty = '0' -- Data Queue NOT empty
and updt_active = '1'
else '0';
-- Status queue read enable
sts_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts_queue_empty = '0' -- Status fifo NOT empty
and updt_active = '1'
else '0';
-----------------------------------------------------------------------
-- TVALID - status queue not empty and writing status
-----------------------------------------------------------------------
-----------------------------------------------------------------------
-- TLAST - status queue not empty, writing status, and last asserted
-----------------------------------------------------------------------
-- Drive last as long as tvalid is asserted and last from fifo
-- is asserted
end generate MM2S_CHANNEL;
NO_MM2S_CHANNEL : if C_INCLUDE_MM2S = 0 generate
begin
updt_active_re1 <= '0';
updt_queue_empty <= '0';
s_axis_updtptr_tready <= '0';
s_axis_updtsts_tready <= '0';
sts_queue_dout <= (others => '0');
sts_queue_full <= '0';
sts_queue_empty <= '0';
ptr_queue_dout <= (others => '0');
ptr_queue_empty <= '0';
ptr_queue_full <= '0';
end generate NO_MM2S_CHANNEL;
S2MM_CHANNEL : if C_INCLUDE_S2MM = 1 generate
begin
updt2_tvalid <= follower_full_s2mm and updt2_active;
updt2_tlast <= follower_reg_s2mm(C_S_AXIS_UPDSTS_TDATA_WIDTH) and updt2_active;
sts2_rden <= follower_empty_s2mm and (not sts2_queue_empty); -- and updt2_active;
VALID_REG_S2MM_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_updt_tready_s2mm = '1' and follower_full_s2mm = '1'))then
-- follower_reg_s2mm <= (others => '0');
follower_full_s2mm <= '0';
follower_empty_s2mm <= '1';
else
if (sts2_rden = '1') then
-- follower_reg_s2mm <= sts2_queue_dout;
follower_full_s2mm <= '1';
follower_empty_s2mm <= '0';
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE;
VALID_REG_S2MM_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_s2mm <= (others => '0');
else
if (sts2_rden = '1') then
follower_reg_s2mm <= sts2_queue_dout;
end if;
end if;
end if;
end process VALID_REG_S2MM_ACTIVE1;
REG2_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_active_d2 <= '0';
else
updt_active_d2 <= updt2_active;
end if;
end if;
end process REG2_ACTIVE;
updt_active_re2 <= updt2_active and not updt_active_d2;
-- I_UPDT2_DATA_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
-- generic map (
-- C_DWIDTH => 32 ,
-- C_DEPTH => 8 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => ptr2_queue_wren ,
-- Data_In => ptr2_queue_din ,
-- FIFO_Read => ptr2_queue_rden ,
-- Data_Out => ptr2_queue_dout ,
-- FIFO_Empty => ptr2_queue_empty ,
-- FIFO_Full => ptr2_queue_full,
-- Addr => open
-- );
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
ptr2_queue_dout <= (others => '0');
elsif (ptr2_queue_wren = '1') then
ptr2_queue_dout <= ptr2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or ptr2_queue_rden = '1') then
ptr2_queue_empty <= '1';
ptr2_queue_full <= '0';
elsif (ptr2_queue_wren = '1') then
ptr2_queue_empty <= '0';
ptr2_queue_full <= '1';
end if;
end if;
end process;
APP_UPDATE: if C_SG2_WORDS_TO_UPDATE /= 1 generate
begin
I_UPDT2_STS_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map (
C_DWIDTH => 34 ,
C_DEPTH => 12 ,
C_FAMILY => C_FAMILY
)
port map (
Clk => m_axi_sg_aclk ,
Reset => sinit ,
FIFO_Write => sts2_queue_wren ,
Data_In => sts2_queue_din ,
FIFO_Read => sts2_rden,
Data_Out => sts2_queue_dout ,
FIFO_Empty => sts2_queue_empty ,
FIFO_Full => sts2_queue_full ,
Addr => open
);
end generate APP_UPDATE;
NO_APP_UPDATE: if C_SG2_WORDS_TO_UPDATE = 1 generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1') then
sts2_queue_dout <= (others => '0');
elsif (sts2_queue_wren = '1') then
sts2_queue_dout <= sts2_queue_din;
end if;
end if;
end process;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (sinit = '1' or sts2_rden = '1') then
sts2_queue_empty <= '1';
sts2_queue_full <= '0';
elsif (sts2_queue_wren = '1') then
sts2_queue_empty <= '0';
sts2_queue_full <= '1';
end if;
end if;
end process;
end generate NO_APP_UPDATE;
-- Pointer Queue Update - Descriptor Pointer (32bits)
-- i.e. 2 current descriptor pointers and any app fields
ptr2_queue_din(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) <= s_axis2_updtptr_tdata( -- DESC DATA
C_M_AXI_SG_ADDR_WIDTH-1
downto 0);
-- Data Queue Write Enable - based on tvalid and queue not full
ptr2_queue_wren <= s_axis2_updtptr_tvalid -- TValid
and not ptr2_queue_full; -- Data Queue NOT Full
-- Drive channel port with ready if room in data queue
s_axis2_updtptr_tready <= not ptr2_queue_full;
--*****************************************
--** Channel Status Port Side of Queues
--*****************************************
-- Status Queue Update - TLAST(1bit) & Includes IOC(1bit) & Descriptor Status(32bits)
-- Note: Type field is stripped off
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH) <= s_axis2_updtsts_tlast; -- Store with tlast
sts2_queue_din(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) <= s_axis2_updtsts_tdata( -- IOC & DESC STS
C_S_AXIS_UPDSTS_TDATA_WIDTH-1
downto 0);
-- Status Queue Write Enable - based on tvalid and queue not full
sts2_queue_wren <= s_axis2_updtsts_tvalid
and not sts2_queue_full;
-- Drive channel port with ready if room in status queue
s_axis2_updtsts_tready <= not sts2_queue_full;
--*************************************
--** SG Engine Side of Queues
--*************************************
-- Indicate NOT empty if both status queue and data queue are not empty
updt2_queue_empty <= ptr2_queue_empty
or follower_empty_s2mm; --or (sts2_queue_empty and follower_empty and updt2_active);
-- Data queue read enable
ptr2_queue_rden <= '1' when dataq_rden = '1' -- Cur desc read enable
and ptr2_queue_empty = '0' -- Data Queue NOT empty
and updt2_active = '1'
else '0';
-- Status queue read enable
sts2_queue_rden <= '1' when stsq_rden = '1' -- Writing desc status
and sts2_queue_empty = '0' -- Status fifo NOT empty
and updt2_active = '1'
else '0';
end generate S2MM_CHANNEL;
NO_S2MM_CHANNEL : if C_INCLUDE_S2MM = 0 generate
begin
updt_active_re2 <= '0';
updt2_queue_empty <= '0';
s_axis2_updtptr_tready <= '0';
s_axis2_updtsts_tready <= '0';
sts2_queue_dout <= (others => '0');
sts2_queue_full <= '0';
sts2_queue_empty <= '0';
ptr2_queue_dout <= (others => '0');
ptr2_queue_empty <= '0';
ptr2_queue_full <= '0';
end generate NO_S2MM_CHANNEL;
end generate GEN_Q_FOR_SYNC;
-- FIFO Reset is active high
sinit <= not m_axi_sg_aresetn;
-- LSB_PROC : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' )then
-- write_curdesc_lsb <= '0';
-- -- Capture lower pointer from FIFO or channel port
-- else -- if(write_curdesc_lsb = '1' and updt_active_int = '1')then
write_curdesc_lsb <= write_curdesc_lsb_sm;
-- end if;
-- end if;
-- end process LSB_PROC;
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
ptr_queue_dout_int <= ptr2_queue_dout when (updt2_active = '1') else
ptr_queue_dout;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
updt_active_int <= updt_active or updt2_active;
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(31 downto 0) <= ptr_queue_dout_int(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
-- updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
updt_curdesc(C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= ptr_queue_dout_int(C_M_AXI_SG_ADDR_WIDTH-1 downto 32);
-- updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
-- updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1' and updt_active_int = '1')then
--elsif(write_curdesc_msb = '1' and updt_active_int = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
-- updt_ioc <= sts_queue_dout(DESC_IOC_TAG_BIT) and updt_active;
updt_ioc <= follower_reg_mm2s(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
--dma_interr <= sts_queue_dout(DESC_STS_INTERR_BIT) and updt_active;
dma_interr <= follower_reg_mm2s(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_slverr <= sts_queue_dout(DESC_STS_SLVERR_BIT) and updt_active;
dma_slverr <= follower_reg_mm2s(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
-- dma_decerr <= sts_queue_dout(DESC_STS_DECERR_BIT) and updt_active;
dma_decerr <= follower_reg_mm2s(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
-----------------------------------------------------------------------
-- Caputure IOC begin set
-----------------------------------------------------------------------
REG_IOC2_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
-- updt2_ioc <= sts2_queue_dout(DESC_IOC_TAG_BIT) and updt2_active;
updt2_ioc <= follower_reg_s2mm(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC2_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_interr <= sts2_queue_dout(DESC_STS_INTERR_BIT) and updt2_active;
dma2_interr <= follower_reg_s2mm (DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_slverr <= sts2_queue_dout(DESC_STS_SLVERR_BIT) and updt2_active;
dma2_slverr <= follower_reg_s2mm(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV2_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC2_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
-- dma2_decerr <= sts2_queue_dout(DESC_STS_DECERR_BIT) and updt2_active;
dma2_decerr <= follower_reg_s2mm(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC2_ERROR;
end implementation;
| mit | 28a2084a95b105bec8684b0bf180ea38 | 0.430465 | 4.271548 | false | false | false | false |
BBN-Q/VHDL-FIR-filters | test/FIR_tb.vhd | 1 | 3,139 | ----------------------------------------------------------------------------------
-- Testbench for ParallelPolyphase
-- Initial version: Colm Ryan ([email protected])
-- Create Date: 05/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use work.TestVectors.all;
entity FIR_tb is
-- Port ( );
end FIR_tb;
architecture Behavioral of FIR_tb is
constant coeffs : real_vector := (0.01662606, -0.00696415, -0.03403663, -0.04855056, -0.01434685, 0.08048669, 0.20301046, 0.28957738, 0.28957738, 0.20301046, 0.08048669, -0.01434685, -0.04855056, -0.03403663, -0.00696415, 0.01662606);
signal rst : std_logic := '0';
signal clk : std_logic := '0';
signal finished : boolean := false;
signal data_in : std_logic_vector(15 downto 0) := (others => '0');
signal data_out, data_check : std_logic_vector(15 downto 0) := (others => '0');
constant DATA_IN_WIDTH : natural := 16;
constant DATA_IN_SCALE : real := real(2 ** (DATA_IN_WIDTH-1)) - 1.0;
constant DATA_OUT_WIDTH : natural := 16;
constant DATA_OUT_SCALE : real := real(2 ** (DATA_OUT_WIDTH-1)) - 1.0;
constant FILTER_DELAY : natural := 1;
begin
dut : entity work.FIR_DirectTranspose
generic map(coeffs => coeffs, data_in_width=>DATA_IN_WIDTH, data_out_width=>DATA_OUT_WIDTH)
port map (
rst => rst,
clk => clk,
data_in => data_in,
data_in_vld => '0',
data_in_last => '0',
data_out => data_out);
stim : process
begin
rst <= '1';
wait for 100ns;
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
sampleDriver : for ct in chirp'range loop
data_in <= std_logic_vector(to_signed(integer(DATA_IN_SCALE*chirp(ct)), 16));
wait until rising_edge(clk);
end loop;
data_in <= (others => '0');
wait for 1us;
finished <= true;
end process;
check : process
variable curOutput : real;
begin
wait for 100ns;
wait until rising_edge(clk);
wait until rising_edge(clk);
for ct in 0 to FILTER_DELAY loop
wait until rising_edge(clk);
end loop;
for ct in 0 to chirp'high + coeffs'high loop
curOutput := 0.0;
for tap in coeffs'range loop
if (ct-tap >= 0) and (ct-tap <= chirp'high) then
curOutput := curOutput + chirp(ct-tap)*coeffs(tap);
end if;
end loop;
data_check <= std_logic_vector(to_signed(integer(trunc(DATA_OUT_SCALE * curOutput)), 16));
--Arbitrarly allow 2 differences due to fixed point errors
assert abs(signed(data_check) - signed(data_out)) <= 2 report "FIR filter output incorrect!";
wait until rising_edge(clk);
end loop;
data_check <= (others => '0');
wait for 1us;
end process;
--clock generation
clk <= not clk after 10ns when not finished;
end Behavioral;
| apache-2.0 | cb69f5c0cc8219afce8fcfd40d21f750 | 0.611341 | 3.342918 | false | false | false | false |
szanni/aeshw | aes-core/decrementor.vhd | 1 | 1,722 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:44:59 07/20/2014
-- Design Name:
-- Module Name: decrementor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity decrementor is
port(
clk : in std_logic;
reset : in std_logic;
y : in std_logic_vector(1 downto 0);
d_out : out byte;
x : out std_logic -- boolean indicating if the tenth round is reached (d_out = '0')
);
end decrementor;
architecture Behavioral of decrementor is
signal reg_D, reg_Q : byte;
begin
mux_3_1 : process(y, reg_Q)
begin
case y is
when "00" => reg_D <= x"0A";
when "01" => reg_D <= reg_Q - 1;
when others => reg_D <= reg_Q;
end case;
end process mux_3_1;
reg : process (reset, clk, reg_D)
begin
if reset = '1' then
reg_Q <= (others => '0');
elsif rising_edge(clk) then
reg_Q <= reg_D;
end if;
end process reg;
comp : process (reg_Q)
begin
if reg_Q = x"00" then
x <= '1';
else
x <= '0';
end if;
end process comp;
d_out <= reg_Q;
end Behavioral;
| bsd-2-clause | d70eb31754270a7c31c4dd9013c1dad9 | 0.57259 | 3.153846 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/l2d_d.vhd | 1 | 4,865 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity Long2Double is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_signed : in std_logic;
i_w32 : in std_logic;
i_a : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_Long2Double of Long2Double is
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(2 downto 0);
signA : std_logic;
absA : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
op_signed : std_logic;
mantAlign : std_logic_vector(63 downto 0);
lshift : integer range 0 to 63;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
'0', (others => '0'), (others => '0'), -- signA, absA, result
'0', (others => '0'), 0 -- op_signed, mantAlign, lshift
);
signal r, rin : RegistersType;
begin
-- registers:
comb : process(i_nrst, i_ena, i_signed, i_w32, i_a, r)
variable v : RegistersType;
variable mantAlign : std_logic_vector(63 downto 0);
variable lshift : integer range 0 to 63;
variable expAlign : std_logic_vector(10 downto 0);
variable mantEven : std_logic;
variable mant05 : std_logic;
variable mantOnes : std_logic;
variable rndBit : std_logic;
variable v_signA : std_logic;
variable vb_A : std_logic_vector(63 downto 0);
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena := r.ena(1 downto 0) & (i_ena and not r.busy);
if i_w32 = '0' then
v_signA := i_a(63);
vb_A := i_a;
elsif i_signed = '1' and i_a(31) = '1' then
v_signA := '1';
vb_A(63 downto 32) := (others => '1');
vb_A(31 downto 0) := i_a(31 downto 0);
else
v_signA := '0';
vb_A(31 downto 0) := i_a(31 downto 0);
vb_A(63 downto 32) := (others => '0');
end if;
if i_ena = '1' then
v.busy := '1';
if i_signed = '1' and v_signA = '1' then
v.signA := '1';
v.absA := not vb_A + 1;
else
v.signA := '0';
v.absA := vb_A;
end if;
v.op_signed := i_signed;
end if;
-- multiplexer, probably if/elsif in rtl:
mantAlign := (others => '0');
lshift := 63;
if r.absA(63) = '1' then
mantAlign := r.absA;
else
for i in 1 to 63 loop
if lshift = 63 and r.absA(63 - i) = '1' then
mantAlign := r.absA(63-i downto 0) & zero64(i-1 downto 0);
lshift := i;
end if;
end loop;
end if;
if r.ena(0) = '1' then
v.mantAlign := mantAlign;
v.lshift := lshift;
end if;
if r.absA = zero64 then
expAlign := (others => '0');
else
expAlign := conv_std_logic_vector(1086 - r.lshift, 11);
end if;
mantEven := r.mantAlign(11);
mant05 := '0';
if r.mantAlign(10 downto 0) = "11111111111" then
mant05 := '1';
end if;
rndBit := r.mantAlign(10) and not(mant05 and mantEven);
mantOnes := '0';
if r.mantAlign(63) = '1' and r.mantAlign(62 downto 11) = X"fffffffffffff" then
mantOnes := '1';
end if;
-- Result multiplexers:
res(63) := r.signA and r.op_signed;
res(62 downto 52) := expAlign + ("0000000000" & (mantOnes and rndBit));
res(51 downto 0) := r.mantAlign(62 downto 11) + rndBit;
if r.ena(1) = '1' then
v.result := res;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_valid <= r.ena(2);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | de604823980f47c08ca5008d779052a4 | 0.557246 | 3.226127 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/dcache_lru.vhd | 1 | 28,565 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_cache.all;
entity dcache_lru is generic (
memtech : integer;
async_reset : boolean;
coherence_ena : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
-- Control path:
i_req_valid : in std_logic;
i_req_write : in std_logic;
i_req_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_req_wdata : in std_logic_vector(63 downto 0);
i_req_wstrb : in std_logic_vector(7 downto 0);
o_req_ready : out std_logic;
o_resp_valid : out std_logic;
o_resp_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_resp_data : out std_logic_vector(63 downto 0);
o_resp_er_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_resp_er_load_fault : out std_logic;
o_resp_er_store_fault : out std_logic;
o_resp_er_mpu_load : out std_logic;
o_resp_er_mpu_store : out std_logic;
i_resp_ready : in std_logic;
-- Memory interface:
i_req_mem_ready : in std_logic;
o_req_mem_valid : out std_logic;
o_req_mem_type : out std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
o_req_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_req_mem_strob : out std_logic_vector(DCACHE_BYTES_PER_LINE-1 downto 0);
o_req_mem_data : out std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
i_mem_data_valid : in std_logic;
i_mem_data : in std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
i_mem_load_fault : in std_logic;
i_mem_store_fault : in std_logic;
-- MPU interface
o_mpu_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_mpu_flags : in std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
-- D$ Snoop interface
i_req_snoop_valid : in std_logic;
i_req_snoop_type : in std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
o_req_snoop_ready : out std_logic;
i_req_snoop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_resp_snoop_ready : in std_logic;
o_resp_snoop_valid : out std_logic;
o_resp_snoop_data : out std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
o_resp_snoop_flags : out std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
-- Debug Signals:
i_flush_address : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_flush_valid : in std_logic;
o_flush_end : out std_logic
);
end;
architecture arch_dcache_lru of dcache_lru is
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
constant State_Idle : std_logic_vector(3 downto 0) := "0000";
constant State_CheckHit : std_logic_vector(3 downto 0) := "0001";
constant State_TranslateAddress : std_logic_vector(3 downto 0) := "0010";
constant State_WaitGrant : std_logic_vector(3 downto 0) := "0011";
constant State_WaitResp : std_logic_vector(3 downto 0) := "0100";
constant State_CheckResp : std_logic_vector(3 downto 0) := "0101";
constant State_SetupReadAdr : std_logic_vector(3 downto 0) := "0110";
constant State_WriteBus : std_logic_vector(3 downto 0) := "0111";
constant State_FlushAddr : std_logic_vector(3 downto 0) := "1000";
constant State_FlushCheck : std_logic_vector(3 downto 0) := "1001";
constant State_ResetAddr : std_logic_vector(3 downto 0) := "1010";
constant State_ResetWrite : std_logic_vector(3 downto 0) := "1011";
constant State_SnoopSetupAddr : std_logic_vector(3 downto 0) := "1100";
constant State_SnoopReadData : std_logic_vector(3 downto 0) := "1101";
signal line_direct_access_i : std_logic;
signal line_invalidate_i : std_logic;
signal line_re_i : std_logic;
signal line_we_i : std_logic;
signal line_addr_i : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal line_wdata_i : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
signal line_wstrb_i : std_logic_vector(DCACHE_BYTES_PER_LINE-1 downto 0);
signal line_wflags_i : std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
signal line_raddr_o : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal line_rdata_o : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
signal line_rflags_o : std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
signal line_hit_o : std_logic;
-- Snoop signals:
signal line_snoop_addr_i : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal line_snoop_ready_o : std_logic;
signal line_snoop_flags_o : std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
type RegistersType is record
req_write : std_logic;
req_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
req_wdata : std_logic_vector(63 downto 0);
req_wstrb : std_logic_vector(7 downto 0);
state : std_logic_vector(3 downto 0);
req_mem_valid : std_logic;
req_mem_type : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
mem_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
mpu_er_store : std_logic;
mpu_er_load : std_logic;
load_fault : std_logic;
write_first : std_logic;
write_flush : std_logic;
write_share : std_logic;
mem_wstrb : std_logic_vector(DCACHE_BYTES_PER_LINE-1 downto 0);
req_flush : std_logic;
req_flush_all : std_logic;
req_flush_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
req_flush_cnt : std_logic_vector(CFG_DLOG2_LINES_PER_WAY + CFG_DLOG2_NWAYS-1 downto 0);
flush_cnt : std_logic_vector(CFG_DLOG2_LINES_PER_WAY + CFG_DLOG2_NWAYS-1 downto 0);
cache_line_i : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
cache_line_o : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
req_snoop_type : std_logic_vector(SNOOP_REQ_TYPE_BITS-1 downto 0);
snoop_flags_valid : std_logic;
snoop_restore_wait_resp : std_logic;
snoop_restore_write_bus : std_logic;
req_addr_restore : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
end record;
constant R_RESET : RegistersType := (
'0', -- req_write
(others => '0'), -- req_addr
(others => '0'), (others => '0'), -- req_wdata, req_wstrb
State_ResetAddr, -- state
'0', -- req_mem_valid
(others => '0'), -- req_mem_type
(others => '0'), -- mem_addr,
'0', -- mpu_er_store
'0', -- mpu_er_load
'0', -- load_fault
'0', -- write_first
'0', -- write_flush
'0', -- write_share
(others => '0'), -- mem_wstrb
'0', -- req_flush
'0', -- req_flush_all
(others => '0'), -- req_flush_addr [0]=1 flush all
(others => '0'), -- req_flush_cnt
(others => '1'), -- flush_cnt
(others => '0'), -- cache_line_i
(others => '0'), -- cache_line_o
(others => '0'), -- req_snoop_type
'0', -- snoop_flags_valid
'0', -- snoop_restore_wait_resp
'0', -- snoop_restore_write_bus
(others => '0') -- req_addr_restore
);
signal r, rin : RegistersType;
begin
tagmem0 : tagmemnway generic map (
memtech => memtech,
async_reset => async_reset,
abus => CFG_CPU_ADDR_BITS,
waybits => CFG_DLOG2_NWAYS,
ibits => CFG_DLOG2_LINES_PER_WAY,
lnbits => CFG_DLOG2_BYTES_PER_LINE,
flbits => DTAG_FL_TOTAL,
snoop => coherence_ena
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_direct_access => line_direct_access_i,
i_invalidate => line_invalidate_i,
i_re => line_re_i,
i_we => line_we_i,
i_addr => line_addr_i,
i_wdata => line_wdata_i,
i_wstrb => line_wstrb_i,
i_wflags => line_wflags_i,
o_raddr => line_raddr_o,
o_rdata => line_rdata_o,
o_rflags => line_rflags_o,
o_hit => line_hit_o,
i_snoop_addr => line_snoop_addr_i,
o_snoop_ready => line_snoop_ready_o,
o_snoop_flags => line_snoop_flags_o
);
comb : process(i_nrst, i_req_valid, i_req_write, i_req_addr, i_req_wdata, i_req_wstrb,
i_resp_ready, i_req_mem_ready,
i_mem_data_valid, i_mem_data, i_mem_load_fault, i_mem_store_fault,
i_mpu_flags, i_flush_address, i_flush_valid,
i_req_snoop_type, i_req_snoop_valid, i_req_snoop_addr,
line_raddr_o, line_rdata_o, line_hit_o, line_rflags_o,
line_snoop_ready_o, line_snoop_flags_o, r)
variable v : RegistersType;
variable vb_cache_line_i_modified : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
variable vb_line_rdata_o_modified : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
variable vb_line_rdata_o_wstrb : std_logic_vector(DCACHE_BYTES_PER_LINE-1 downto 0);
variable v_req_ready : std_logic;
variable vb_cached_data : std_logic_vector(63 downto 0);
variable vb_uncached_data : std_logic_vector(63 downto 0);
variable v_resp_valid : std_logic;
variable vb_resp_data : std_logic_vector(63 downto 0);
variable v_resp_er_load_fault : std_logic;
variable v_resp_er_store_fault : std_logic;
variable v_direct_access : std_logic;
variable v_invalidate : std_logic;
variable v_flush_end : std_logic;
variable v_line_cs_read : std_logic;
variable v_line_cs_write : std_logic;
variable vb_line_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_line_wdata : std_logic_vector(DCACHE_LINE_BITS-1 downto 0);
variable vb_line_wstrb : std_logic_vector(DCACHE_BYTES_PER_LINE-1 downto 0);
variable vb_req_mask : std_logic_vector(63 downto 0);
variable v_line_wflags : std_logic_vector(DTAG_FL_TOTAL-1 downto 0);
variable ridx : integer range 0 to (DCACHE_BYTES_PER_LINE/8)-1;
variable v_req_same_line : std_logic;
variable v_ready_next : std_logic;
variable v_req_snoop_ready : std_logic;
variable v_req_snoop_ready_on_wait : std_logic;
variable v_resp_snoop_valid : std_logic;
variable vb_addr_direct_next : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable v_req_snoop_cohena : std_logic;
begin
v := r;
v_ready_next := '0';
v_req_ready := '0';
v_resp_valid := '0';
vb_resp_data := (others => '0');
v_resp_er_load_fault := '0';
v_resp_er_store_fault := '0';
v_direct_access := '0';
v_invalidate := '0';
v_flush_end := '0';
v_req_snoop_ready := '0';
v_req_snoop_ready_on_wait := '0';
v_resp_snoop_valid := r.snoop_flags_valid;
ridx := conv_integer(r.req_addr(CFG_DLOG2_BYTES_PER_LINE-1 downto 3));
vb_cached_data := line_rdata_o((ridx+1)*64 - 1 downto
ridx*64);
vb_uncached_data := r.cache_line_i(63 downto 0);
v_req_same_line := '0';
if r.req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE)
= i_req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE) then
v_req_same_line := '1';
end if;
if i_flush_valid = '1' then
v.req_flush := '1';
v.req_flush_all := i_flush_address(0);
if i_flush_address(0) = '1' then
v.req_flush_cnt := (others => '1');
v.req_flush_addr := (others => '0');
else
v.req_flush_cnt := (others => '0');
v.req_flush_addr := i_flush_address;
end if;
end if;
for i in 0 to 7 loop
vb_req_mask(8*i+7 downto 8*i) := (others => r.req_wstrb(i));
end loop;
vb_line_rdata_o_modified := line_rdata_o;
vb_cache_line_i_modified := r.cache_line_i;
vb_line_rdata_o_wstrb := (others => '0');
for i in 0 to (DCACHE_BYTES_PER_LINE/8)-1 loop
if i = ridx then
vb_line_rdata_o_modified(64*(i+1)-1 downto 64*i) :=
(vb_line_rdata_o_modified(64*(i+1)-1 downto 64*i)
and not vb_req_mask) or (r.req_wdata and vb_req_mask);
vb_cache_line_i_modified(64*(i+1)-1 downto 64*i) :=
(vb_cache_line_i_modified(64*(i+1)-1 downto 64*i)
and not vb_req_mask) or (r.req_wdata and vb_req_mask);
vb_line_rdata_o_wstrb(8*(i+1)-1 downto 8*i) :=
r.req_wstrb;
end if;
end loop;
-- Flush counter when direct access
if r.req_addr(CFG_DLOG2_NWAYS-1 downto 0) =
conv_std_logic_vector(DCACHE_WAYS-1, CFG_DLOG2_NWAYS) then
vb_addr_direct_next(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE) :=
r.req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE) + 1;
vb_addr_direct_next(CFG_DLOG2_BYTES_PER_LINE-1 downto 0) := (others => '0');
else
vb_addr_direct_next := r.req_addr + 1;
end if;
v_line_cs_read := '0';
v_line_cs_write := '0';
vb_line_addr := r.req_addr;
vb_line_wdata := r.cache_line_i;
vb_line_wstrb := (others => '0');
v_line_wflags := (others => '0');
-- System Bus access state machine
case r.state is
when State_Idle =>
v.mpu_er_store := '0';
v.mpu_er_load := '0';
v_ready_next := '1';
when State_CheckHit =>
vb_resp_data := vb_cached_data;
if line_hit_o = '1' then
-- Hit
v_resp_valid := '1';
if i_resp_ready = '1' then
if r.req_write = '1' then
-- Modify tagged mem output with request and write back
v_line_cs_write := '1';
v_line_wflags(TAG_FL_VALID) := '1';
v_line_wflags(DTAG_FL_DIRTY) := '1';
v.req_write := '0';
vb_line_wstrb := vb_line_rdata_o_wstrb;
vb_line_wdata := vb_line_rdata_o_modified;
if coherence_ena and line_rflags_o(DTAG_FL_SHARED) = '1' then
-- Make line: 'shared' -> 'unique' using write request
v.write_share := '1';
v.state := State_TranslateAddress;
else
if v_req_same_line = '1' then
-- Write address is the same as the next requested, so use it to write
-- value and update state machine
v_ready_next := '1';
end if;
v.state := State_Idle;
end if;
else
v_ready_next := '1';
v.state := State_Idle;
end if;
end if;
else
-- Miss
v.state := State_TranslateAddress;
end if;
when State_TranslateAddress =>
if r.req_write = '1' and i_mpu_flags(CFG_MPU_FL_WR) = '0' then
v.mpu_er_store := '1';
v.cache_line_i := (others => '1');
v.state := State_CheckResp;
elsif r.req_write = '0' and i_mpu_flags(CFG_MPU_FL_RD) = '0' then
v.mpu_er_load := '1';
v.cache_line_i := (others => '1');
v.state := State_CheckResp;
else
v.req_mem_valid := '1';
v.state := State_WaitGrant;
if i_mpu_flags(CFG_MPU_FL_CACHABLE) = '1' then
-- Cached:
if r.write_share = '1' then
v.req_mem_type := WriteLineUnique;
v.mem_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE) :=
line_raddr_o(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE);
v.mem_addr(CFG_DLOG2_BYTES_PER_LINE-1 downto 0) := (others => '0');
elsif line_rflags_o(TAG_FL_VALID) = '1' and
line_rflags_o(DTAG_FL_DIRTY) = '1' then
v.write_first := '1';
v.req_mem_type := WriteBack;
v.mem_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE) :=
line_raddr_o(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE);
v.mem_addr(CFG_DLOG2_BYTES_PER_LINE-1 downto 0) := (others => '0');
else
-- 1. Read -> Save cache
-- 2. Read -> Modify -> Save cache
v.mem_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE) :=
r.req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE);
v.mem_addr(CFG_DLOG2_BYTES_PER_LINE-1 downto 0) := (others => '0');
if r.req_write = '1' then
v.req_mem_type := ReadMakeUnique;
else
v.req_mem_type := ReadShared;
end if;
end if;
v.mem_wstrb := (others => '1');
v.cache_line_o := line_rdata_o;
else
-- Uncached read/write
v.mem_addr := r.req_addr(CFG_CPU_ADDR_BITS-1 downto 3) & "000";
v.mem_wstrb := (others => '0');
v.mem_wstrb(7 downto 0) := r.req_wstrb;
if r.req_write = '1' then
v.req_mem_type := WriteNoSnoop;
else
v.req_mem_type := ReadNoSnoop;
end if;
v.cache_line_o := (others => '0');
v.cache_line_o(63 downto 0) := r.req_wdata;
end if;
end if;
v.cache_line_i := (others => '0');
v.load_fault := '0';
when State_WaitGrant =>
if i_req_mem_ready = '1' then
if r.write_flush = '1' or
r.write_first = '1' or
r.write_share = '1' or
(r.req_write = '1' and r.req_mem_type(REQ_MEM_TYPE_CACHED) = '0') then
v.state := State_WriteBus;
else
-- 1. uncached read
-- 2. cached read or write
v.state := State_WaitResp;
end if;
v.req_mem_valid := '0';
end if;
when State_WaitResp =>
if i_mem_data_valid = '1' then
v.cache_line_i := i_mem_data;
v.state := State_CheckResp;
if i_mem_load_fault = '1' then
v.load_fault := '1';
end if;
elsif coherence_ena and
i_req_snoop_valid = '1' and or_reduce(i_req_snoop_type) = '1' then
-- Access cache data
v_req_snoop_ready_on_wait := '1';
v.snoop_restore_wait_resp := '1';
v.req_addr_restore := r.req_addr;
v.req_addr := i_req_snoop_addr;
v.req_snoop_type := i_req_snoop_type;
v.state := State_SnoopSetupAddr;
end if;
when State_CheckResp =>
if r.req_mem_type(REQ_MEM_TYPE_CACHED) = '0'
or r.load_fault = '1' then
-- uncached read only (write goes to WriteBus) or cached load-modify fault
v_resp_valid := '1';
vb_resp_data := vb_uncached_data;
v_resp_er_load_fault := r.load_fault and (not r.req_write);
v_resp_er_store_fault := r.load_fault and r.req_write;
if i_resp_ready = '1' then
v.state := State_Idle;
end if;
else
v.state := State_SetupReadAdr;
v_line_cs_write := '1';
v_line_wflags(TAG_FL_VALID) := '1';
v_line_wflags(DTAG_FL_SHARED) := '1';
vb_line_wstrb := (others => '1'); -- write full line
if r.req_write = '1' then
-- Modify tagged mem output with request before write
v.req_write := '0';
v_line_wflags(DTAG_FL_DIRTY) := '1';
v_line_wflags(DTAG_FL_SHARED) := '0';
vb_line_wdata := vb_cache_line_i_modified;
v_resp_valid := '1';
v.state := State_Idle;
end if;
end if;
when State_SetupReadAdr =>
v.state := State_CheckHit;
when State_WriteBus =>
if i_mem_data_valid = '1' then
if r.write_share = '1' then
v.write_share := '0';
v.state := State_Idle;
elsif r.write_flush = '1' then
-- Offloading Cache line on flush request
v.state := State_FlushAddr;
elsif r.write_first = '1' then
v.mem_addr := r.req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE)
& zero64(CFG_DLOG2_BYTES_PER_LINE-1 downto 0);
v.req_mem_valid := '1';
v.write_first := '0';
if r.req_write = '1' then
-- read request: read-modify-save cache line
v.req_mem_type := ReadMakeUnique;
else
v.req_mem_type := ReadShared;
end if;
v.state := State_WaitGrant;
else
-- Non-cached write
v.state := State_Idle;
v_resp_valid := '1';
v_resp_er_store_fault := i_mem_store_fault;
end if;
elsif coherence_ena and
i_req_snoop_valid = '1' and or_reduce(i_req_snoop_type) = '1' then
-- Access cache data cannot be in the same clock as i_mem_data_valid
v_req_snoop_ready_on_wait := '1';
v.snoop_restore_write_bus := '1';
v.req_addr_restore := r.req_addr;
v.req_addr := i_req_snoop_addr;
v.req_snoop_type := i_req_snoop_type;
v.state := State_SnoopSetupAddr;
end if;
when State_FlushAddr =>
v.state := State_FlushCheck;
v_direct_access := r.req_flush_all; -- 0=only if hit; 1=will be applied ignoring hit
v_invalidate := '1'; -- generate: wstrb='1; wflags='0
v.write_flush := '0';
v.cache_line_i := (others => '0');
when State_FlushCheck =>
v.cache_line_o := line_rdata_o;
v_direct_access := r.req_flush_all;
v_line_cs_write := r.req_flush_all;
if line_rflags_o(TAG_FL_VALID) = '1' and
line_rflags_o(DTAG_FL_DIRTY) = '1' then
-- Off-load valid line
v.write_flush := '1';
v.mem_addr := line_raddr_o;
v.req_mem_valid := '1';
v.req_mem_type := WriteBack;
v.mem_wstrb := (others => '1');
v.state := State_WaitGrant;
else
-- Write clean line
v.state := State_FlushAddr;
if or_reduce(r.flush_cnt) = '0' then
v.state := State_Idle;
v_flush_end := '1';
end if;
end if;
if or_reduce(r.flush_cnt) = '1' then
v.flush_cnt := r.flush_cnt - 1;
if r.req_flush_all = '1' then
v.req_addr := vb_addr_direct_next;
else
v.req_addr := r.req_addr + DCACHE_BYTES_PER_LINE;
end if;
end if;
when State_ResetAddr =>
-- Write clean line
v_direct_access := '1';
v_invalidate := '1'; -- generate: wstrb='1; wflags='0
v.state := State_ResetWrite;
when State_ResetWrite =>
v_direct_access := '1';
v_line_cs_write := '1';
v.state := State_ResetAddr;
if or_reduce(r.flush_cnt) = '1' then
v.flush_cnt := r.flush_cnt - 1;
v.req_addr := vb_addr_direct_next;
else
v.state := State_Idle;
end if;
when State_SnoopSetupAddr =>
v.state := State_SnoopReadData;
v_invalidate := r.req_snoop_type(SNOOP_REQ_TYPE_READCLEAN);
when State_SnoopReadData =>
v_resp_snoop_valid := '1';
if r.req_snoop_type(SNOOP_REQ_TYPE_READCLEAN) = '0' then
v_line_cs_write := '1';
vb_line_wdata := line_rdata_o;
vb_line_wstrb := (others => '1');
v_line_wflags := line_rflags_o;
v_line_wflags(DTAG_FL_DIRTY) := '0';
v_line_wflags(DTAG_FL_SHARED) := '1';
end if;
-- restore state
v.snoop_restore_wait_resp := '0';
v.snoop_restore_write_bus := '0';
if r.snoop_restore_wait_resp = '1' then
v.req_addr := r.req_addr_restore;
v.state := State_WaitResp;
elsif r.snoop_restore_write_bus = '1' then
v.req_addr := r.req_addr_restore;
v.state := State_WriteBus;
else
v.state := State_Idle;
end if;
when others =>
end case;
v_req_snoop_cohena := '0';
if coherence_ena then
v_req_snoop_cohena := v_ready_next and or_reduce(i_req_snoop_type);
end if;
v_req_snoop_ready :=
(line_snoop_ready_o and (not or_reduce(i_req_snoop_type))) or
v_req_snoop_cohena or v_req_snoop_ready_on_wait;
v.snoop_flags_valid := i_req_snoop_valid and
line_snoop_ready_o and (not or_reduce(i_req_snoop_type));
if v_ready_next = '1' then
if coherence_ena and
i_req_snoop_valid = '1' and or_reduce(i_req_snoop_type) = '1' then
-- Access cache data
v.req_addr := i_req_snoop_addr;
v.req_snoop_type := i_req_snoop_type;
v.state := State_SnoopSetupAddr;
elsif r.req_flush = '1' then
v.state := State_FlushAddr;
v.req_flush := '0';
v.cache_line_i := (others => '0');
v.req_addr := r.req_flush_addr;
v.req_addr := r.req_flush_addr(CFG_CPU_ADDR_BITS-1 downto CFG_DLOG2_BYTES_PER_LINE)
& zero64(CFG_DLOG2_BYTES_PER_LINE-1 downto 0);
v.flush_cnt := r.req_flush_cnt;
else
v_req_ready := '1';
v_line_cs_read := i_req_valid;
vb_line_addr := i_req_addr;
if i_req_valid = '1' then
v.req_addr := i_req_addr;
v.req_wstrb := i_req_wstrb;
v.req_wdata := i_req_wdata;
v.req_write := i_req_write;
v.state := State_CheckHit;
end if;
end if;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
line_direct_access_i <= v_direct_access;
line_invalidate_i <= v_invalidate;
line_re_i <= v_line_cs_read;
line_we_i <= v_line_cs_write;
line_addr_i <= vb_line_addr;
line_wdata_i <= vb_line_wdata;
line_wstrb_i <= vb_line_wstrb;
line_wflags_i <= v_line_wflags;
line_snoop_addr_i <= i_req_snoop_addr;
o_req_ready <= v_req_ready;
o_req_mem_valid <= r.req_mem_valid;
o_req_mem_addr <= r.mem_addr;
o_req_mem_type <= r.req_mem_type;
o_req_mem_strob <= r.mem_wstrb;
o_req_mem_data <= r.cache_line_o;
o_resp_valid <= v_resp_valid;
o_resp_data <= vb_resp_data;
o_resp_addr <= r.req_addr;
o_resp_er_addr <= r.req_addr;
o_resp_er_load_fault <= v_resp_er_load_fault;
o_resp_er_store_fault <= v_resp_er_store_fault;
o_resp_er_mpu_load <= r.mpu_er_load;
o_resp_er_mpu_store <= r.mpu_er_store;
o_mpu_addr <= r.req_addr;
o_flush_end <= v_flush_end;
o_req_snoop_ready <= v_req_snoop_ready;
o_resp_snoop_valid <= v_resp_snoop_valid;
o_resp_snoop_data <= line_rdata_o;
o_resp_snoop_flags <= line_snoop_flags_o;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 39c9c3bb97191b2a5aadec72a14b75bf | 0.533415 | 3.238295 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/otp_tech.vhd | 1 | 2,608 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library commonlib;
use commonlib.types_common.all;
entity otp_tech is
generic (
memtech : integer := 0
);
port (
clk : in std_logic; -- only for FPGA
i_we : in std_ulogic;
i_re : in std_ulogic;
i_addr : in std_logic_vector(11 downto 0);
i_wdata : in std_logic_vector(15 downto 0);
o_rdata : out std_logic_vector(15 downto 0);
io_gnd : inout std_logic;
io_vdd : inout std_logic;
io_vdd18 : inout std_logic;
io_upp : inout std_logic
);
end;
architecture rtl of otp_tech is
component otp_clocked is
port (
clk : in std_ulogic;
we : in std_ulogic;
re : in std_ulogic;
address : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(15 downto 0);
rdata : out std_logic_vector(15 downto 0)
);
end component;
component OTP_MEM_BLOCK_CORE_AUG18_v1rev1 is
port (
D_I : in std_logic_vector(15 downto 0);
D_A : in std_logic_vector(11 downto 0);
WE_I : in std_logic;
RE_I : in std_logic;
D_O : out std_logic_vector(15 downto 0);
GND : inout std_logic;
VDD : inout std_logic;
VDD18 : inout std_logic;
UPP : inout std_logic
);
end component;
begin
genotp0 : if memtech = inferred or is_fpga(memtech) /= 0 generate
inf0 : otp_clocked port map (
clk => clk, -- FPGA only
we => i_we,
re => i_re,
address => i_addr,
wdata => i_wdata,
rdata => o_rdata
);
end generate;
genotp1 : if memtech = mikron180 generate
mik180 : OTP_MEM_BLOCK_CORE_AUG18_v1rev1 port map (
D_I => i_wdata,
D_A => i_addr,
WE_I => i_we,
RE_I => i_re,
D_O => o_rdata,
GND => io_gnd,
VDD => io_vdd,
VDD18 => io_vdd18,
UPP => io_upp
);
end generate;
end;
| apache-2.0 | 1bc46c16678e14aa7756aa64c3fec82a | 0.604678 | 3.292929 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/gnsslib/types_gnss.vhd | 1 | 2,593 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
package types_gnss is
component gnss_ss is
generic (
async_reset : boolean := false;
tech : integer := 0;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0
);
port (
i_nrst : in std_logic;
i_clk_bus : in std_logic;
i_clk_adc : in std_logic; -- GNSS ADC clock (4..40 MHz)
-- ADC samples (2 complex channels)
i_gps_I : in std_logic_vector(1 downto 0); -- Channel 0 sampled I value
i_gps_Q : in std_logic_vector(1 downto 0); -- Channel 0 sampled Q value
i_glo_I : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
i_glo_Q : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
o_pps : out std_logic; -- Pulse Per Second signal
-- MAX2769 SPIs and antenna controls signals:
i_gps_ld : in std_logic; -- Channel 0 RF front-end Lock detect
i_glo_ld : in std_logic; -- Channel 1 RF front-end Lock detect
o_max_sclk : out std_logic; -- RF synthesizer SPI clock
o_max_sdata : out std_logic; -- RF synthesizer SPI data
o_max_ncs : out std_logic_vector(1 downto 0); -- RF synthesizer channel 0/1 selector
i_antext_stat : in std_logic; -- Antenna powered status
i_antext_detect : in std_logic; -- Antenna connected status
o_antext_ena : out std_logic; -- Enabling/disabling antenna
o_antint_contr : out std_logic; -- Antenna Internal/External selector
-- AXI4 interface
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic
);
end component;
end;
| apache-2.0 | e2c41d30e6bde7fe9418659d33317376 | 0.612804 | 3.704286 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/eth_axi_mst.vhd | 1 | 8,015 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief AXI Master device implementing DMA access.
--! @details AMBA4 AXI Master interface module dedicated for the eth MAC.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library ethlib;
use ethlib.types_eth.all;
entity eth_axi_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
aximi : in axi4_master_in_type;
aximo : out axi4_master_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end entity;
architecture rtl of eth_axi_mst is
constant STATE_IDLE : integer := 0;
constant STATE_W : integer := STATE_IDLE+1;
constant STATE_R_WAIT_RESP : integer := STATE_W+1;
constant STATE_R_WAIT_NEXT : integer := STATE_R_WAIT_RESP+1;
constant STATE_B : integer := STATE_R_WAIT_NEXT+1;
constant Rx : integer := 0;
constant Tx : integer := 1;
type eth_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
type eth_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_out_vector is array (0 to 1) of eth_out_type;
type reg_type is record
state : integer range 0 to STATE_B;
len : integer;
x : integer range 0 to 1;
waddr2 : std_logic;
end record;
signal r, rin : reg_type;
begin
comb : process(rst, r, tmsti, rmsti, aximi) is
variable v : reg_type;
variable xmsti : eth_in_type;
variable xmsto : eth_out_vector;
variable vaximo : axi4_master_out_type;
variable rdata_lsb : std_logic_vector(31 downto 0);
variable wdata_lsb : std_logic_vector(31 downto 0);
begin
v := r;
vaximo := axi4_master_out_none;
vaximo.ar_user := (others => '0');
vaximo.ar_id := conv_std_logic_vector(0, CFG_SYSBUS_ID_BITS);
vaximo.ar_bits.size := "010"; -- 4 bytes
vaximo.ar_bits.burst := AXI_BURST_INCR;
vaximo.aw_user := (others => '0');
vaximo.aw_id := conv_std_logic_vector(0, CFG_SYSBUS_ID_BITS);
vaximo.aw_bits.size := "010"; -- 4 bytes
vaximo.aw_bits.burst := AXI_BURST_INCR;
xmsto := (others => ('0', rdata_lsb, '0', '0', '0'));
if r.x = Rx then
xmsti.req := rmsti.req;
xmsti.write := rmsti.write;
xmsti.addr := rmsti.addr;
xmsti.data := rmsti.data;
xmsti.burst_bytes := rmsti.burst_bytes;
else
xmsti.req := tmsti.req;
xmsti.write := tmsti.write;
xmsti.addr := tmsti.addr;
xmsti.data := tmsti.data;
xmsti.burst_bytes := tmsti.burst_bytes;
end if;
-- Pre-fix for SPARC byte order.
-- It is better to fix in MAC itselfm but for now it will be here.
wdata_lsb := xmsti.data(7 downto 0) & xmsti.data(15 downto 8)
& xmsti.data(23 downto 16) & xmsti.data(31 downto 24);
rdata_lsb := aximi.r_data(7 downto 0) & aximi.r_data(15 downto 8)
& aximi.r_data(23 downto 16) & aximi.r_data(31 downto 24);
case r.state is
when STATE_IDLE =>
if rmsti.req = '1' then
v.x := Rx;
vaximo.ar_valid := not rmsti.write;
vaximo.aw_valid := rmsti.write;
if rmsti.write = '1' then
vaximo.aw_bits.addr := rmsti.addr(31 downto 3) & "000";
v.waddr2 := rmsti.addr(2);
v.len := conv_integer(rmsti.burst_bytes(10 downto 2)) - 1;
vaximo.aw_bits.len := conv_std_logic_vector(v.len, 8);
if aximi.aw_ready = '1' then
xmsto(Rx).grant := '1';
v.state := STATE_W;
end if;
else
vaximo.ar_bits.addr := rmsti.addr;
v.len := conv_integer(rmsti.burst_bytes(10 downto 2)) - 1;
vaximo.ar_bits.len := conv_std_logic_vector(v.len, 8);
if aximi.ar_ready = '1' then
xmsto(Rx).grant := '1';
v.state := STATE_R_WAIT_RESP;
end if;
end if;
elsif tmsti.req = '1' then
v.x := Tx;
vaximo.ar_valid := not tmsti.write;
vaximo.aw_valid := tmsti.write;
if tmsti.write = '1' then
vaximo.aw_bits.addr := tmsti.addr(31 downto 3) & "000";
v.waddr2 := tmsti.addr(2);
v.len := conv_integer(tmsti.burst_bytes(10 downto 2)) - 1;
vaximo.aw_bits.len := conv_std_logic_vector(v.len, 8);
if aximi.aw_ready = '1' then
xmsto(Tx).grant := '1';
v.state := STATE_W;
end if;
else
vaximo.ar_bits.addr := tmsti.addr;
v.len := conv_integer(tmsti.burst_bytes(10 downto 2)) - 1;
vaximo.ar_bits.len := conv_std_logic_vector(v.len, 8);
if aximi.ar_ready = '1' then
xmsto(Tx).grant := '1';
v.state := STATE_R_WAIT_RESP;
end if;
end if;
end if;
when STATE_R_WAIT_RESP =>
vaximo.r_ready := '1';
if aximi.r_valid = '1' then
xmsto(r.x).ready := '1';
if aximi.r_last = '1' then
v.state := STATE_IDLE;
else
if xmsti.req = '1' then
xmsto(r.x).grant := '1';
else
v.state := STATE_R_WAIT_NEXT;
end if;
end if;
end if;
when STATE_R_WAIT_NEXT =>
if xmsti.req = '1' then
xmsto(r.x).grant := '1';
v.state := STATE_R_WAIT_RESP;
end if;
when STATE_W =>
vaximo.w_valid := '1';
case r.waddr2 is
when '0' => vaximo.w_strb := X"0f";
when '1' => vaximo.w_strb := X"f0";
when others =>
end case;
vaximo.w_data := wdata_lsb & wdata_lsb;
if aximi.w_ready = '1' then
xmsto(r.x).ready := '1';
if r.len = 0 then
v.state := STATE_B;
vaximo.w_last := '1';
else
xmsto(r.x).grant := '1';
v.len := r.len - 1;
-- Address will be incremented on slave side
--v.waddr2 := not r.waddr2;
end if;
end if;
when STATE_B =>
vaximo.w_last := '0';
vaximo.b_ready := '1';
if aximi.b_valid = '1' then
v.state := STATE_IDLE;
end if;
when others =>
end case;
if rst = '0' then
v.state := STATE_IDLE;
v.waddr2 := '0';
v.len := 0;
v.x := Rx;
end if;
rin <= v;
aximo <= vaximo;
tmsto.grant <= xmsto(Tx).grant;
tmsto.data <= xmsto(Tx).data;
tmsto.ready <= xmsto(Tx).ready;
tmsto.error <= xmsto(Tx).error;
tmsto.retry <= xmsto(Tx).retry;
rmsto.grant <= xmsto(Rx).grant;
rmsto.data <= xmsto(Rx).data;
rmsto.ready <= xmsto(Rx).ready;
rmsto.error <= xmsto(Rx).error;
rmsto.retry <= xmsto(Rx).retry;
end process;
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
end architecture;
| apache-2.0 | fb718b38a88ee45c835d961e9d8203be | 0.509669 | 3.343763 | false | false | false | false |
szanni/aeshw | aes-core/key_expansion_cu.vhd | 1 | 2,394 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:32:17 07/13/2014
-- Design Name:
-- Module Name: key_expansion_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key_expansion_cu is
port(
clk : in std_logic;
reset : in std_logic;
x_start : in std_logic; -- start key expansion
y_end : out std_logic; -- key expansion finished
x_comp : in std_logic; -- expansion finished (notification from operational unit)
y_we : out std_logic; -- controlling signal for write enable
y_1_2 : out std_logic_vector(1 downto 0); -- controlling signal for key empander mux
y_3_4 : out std_logic_vector(1 downto 0) -- controlling signal for counter mux
);
end key_expansion_cu;
architecture Behavioral of key_expansion_cu is
type States is (S0, S1, S2);
signal S, S_next : States;
begin
delta : process (S, x_start, x_comp)
begin
case S is
when S0 => y_1_2 <="00"; -- load into expander
y_3_4 <="00"; -- initialize counter
y_we <= '0';
y_end <= '0';
if x_start = '1' then
S_next <= S1;
else
S_next <= S0;
end if;
when S1 => y_1_2 <= "01"; -- feed back last round key
y_3_4 <= "01"; -- increment counter
y_we <= '1';
y_end <= '0';
if x_comp = '1' then
S_next <= S2;
else
S_next <= S1;
end if;
when S2 => y_1_2 <= "--";
y_3_4 <= "--";
y_we <= '0';
y_end <= '1';
S_next <= S0;
end case;
end process delta;
feedback_loop : process (clk, reset, S_next)
begin
if reset = '1' then
S <= S0;
elsif rising_edge(clk) then
S <= S_next;
end if;
end process feedback_loop;
end Behavioral;
| bsd-2-clause | 27ef549b4009bfc5c45f22fe2a76e944 | 0.548037 | 3.320388 | false | false | false | false |
szanni/aeshw | aes-core/math.vhd | 1 | 3,019 | library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
package math is
function mul2(din : byte) return byte;
function mul3(din : byte) return byte;
function mul9(din : byte) return byte;
function mulb(din : byte) return byte;
function muld(din : byte) return byte;
function mule(din : byte) return byte;
end math;
package body math is
function mul2(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(7);
ret(1) := din(0) xor din(7);
ret(2) := din(1);
ret(3) := din(2) xor din(7);
ret(4) := din(3) xor din(7);
ret(5) := din(4);
ret(6) := din(5);
ret(7) := din(6);
return ret;
end mul2;
function mul3(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(7);
ret(1) := din(0) xor din(1) xor din(7);
ret(2) := din(1) xor din(2);
ret(3) := din(2) xor din(3) xor din(7);
ret(4) := din(3) xor din(4) xor din(7);
ret(5) := din(4) xor din(5);
ret(6) := din(5) xor din(6);
ret(7) := din(6) xor din(7);
return ret;
end mul3;
function mul9(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(5);
ret(1) := din(1) xor din(5) xor din(6);
ret(2) := din(2) xor din(6) xor din(7);
ret(3) := din(0) xor din(3) xor din(5) xor din(7);
ret(4) := din(1) xor din(4) xor din(5) xor din(6);
ret(5) := din(2) xor din(5) xor din(6) xor din(7);
ret(6) := din(3) xor din(6) xor din(7);
ret(7) := din(4) xor din(7);
return ret;
end mul9;
function mulb(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(5) xor din(7);
ret(1) := din(0) xor din(1) xor din(5) xor din(6) xor din(7);
ret(2) := din(1) xor din(2) xor din(6) xor din(7);
ret(3) := din(0) xor din(2) xor din(3) xor din(5);
ret(4) := din(1) xor din(3) xor din(4) xor din(5) xor din(6) xor din(7);
ret(5) := din(2) xor din(4) xor din(5) xor din(6) xor din(7);
ret(6) := din(3) xor din(5) xor din(6) xor din(7);
ret(7) := din(4) xor din(6) xor din(7);
return ret;
end mulb;
function muld(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(0) xor din(5) xor din(6);
ret(1) := din(1) xor din(5) xor din(7);
ret(2) := din(0) xor din(2) xor din(6);
ret(3) := din(0) xor din(1) xor din(3) xor din(5) xor din(6) xor din(7);
ret(4) := din(1) xor din(2) xor din(4) xor din(5) xor din(7);
ret(5) := din(2) xor din(3) xor din(5) xor din(6);
ret(6) := din(3) xor din(4) xor din(6) xor din(7);
ret(7) := din(4) xor din(5) xor din(7);
return ret;
end muld;
function mule(din : byte) return byte is
variable ret : byte;
begin
ret(0) := din(5) xor din(6) xor din(7);
ret(1) := din(0) xor din(5);
ret(2) := din(0) xor din(1) xor din(6);
ret(3) := din(0) xor din(1) xor din(2) xor din(5) xor din(6);
ret(4) := din(1) xor din(2) xor din(3) xor din(5);
ret(5) := din(2) xor din(3) xor din(4) xor din(6);
ret(6) := din(3) xor din(4) xor din(5) xor din(7);
ret(7) := din(4) xor din(5) xor din(6);
return ret;
end mule;
end math;
| bsd-2-clause | 76648d670ffec4dcc21f1ea772aa15b8 | 0.580325 | 2.237954 | false | false | false | false |
AlessandroSpallina/CalcolatoriElettronici | VHDL/09-12-14/09-12-14_compito.vhd | 2 | 2,780 | -- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity antonella is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end antonella;
architecture beh of antonella is
type stati is (idle, getOP, codOP, exeLD, exeAND, exeADD);
type memory is array (0 to 1) of std_logic_vector(15 downto 0);
signal st : stati;
signal REG : memory;
signal OPE : std_logic_vector(1 downto 0); -- sto salvando su un registro OP poichè assumo che in ingresso il valore di OP sia presente solo per un ciclo di clock
signal enOP, enLD, enAND, enADD : std_logic;
-- signal enCOD : std_logic; non serve a niente, vedi segnali di controllo sotto :D
signal counter : integer range 2 downto 0;
function next_state (st: stati; start : std_logic; ope : std_logic_vector(1 downto 0); counter : integer range 2 downto 0)
return stati is
variable nxt : stati;
begin
case st is
when idle =>
if start = '1' then nxt := getOP;
else nxt := idle;
end if;
when getOP =>
nxt := codOP;
when codOP =>
case ope is
when "00" | "01" => nxt := exeLD;
when "10" => nxt := exeAND;
when others => nxt := exeADD;
end case;
when exeLD =>
nxt := idle;
when exeAND =>
if counter < 1 then nxt := exeAND;
else nxt := idle;
end if;
when exeADD =>
if counter < 2 then nxt := exeADD;
else nxt := idle;
end if;
end case;
return nxt;
end next_state;
begin
-- CU
process (clk) is
begin
if clk'event and clk = '0' then
st <= next_state(st, start, ope, counter);
end if;
end process;
-- State Control Bits
enOP <= '1' when st = getOP else '0';
-- enCOD <= '1' when st = codOP else '0'; non serve a niente, poichè la decodifica la faccio nella funct next_state
enLD <= '1' when st = exeLD else '0';
enAND <= '1' when st = exeAND else '0';
enADD <= '1' when st = exeADD else '0';
-- DATAPATH
process (clk) is
begin
if enOP = '1' then
ope <= op;
counter <= 0;
end if;
if enLD = '1' then
REG(conv_integer(ope)) <= din;
end if;
if enAND = '1' then
if counter = 1 then
REG(1) <= REG(0) and REG(1);
else
counter <= counter + 1;
end if;
end if;
if enADD = '1' then
if counter = 2 then
res <= REG(0) + REG(1);
else
counter <= counter +1;
end if;
end if;
if enLD = '1' or (enAND = '1' and counter = 1) or (enADD = '1' and counter = 2) then
fine <= '1';
else
fine <= '0';
end if;
end process;
end beh; | mit | b683bc0bf59ded84f1aa2bda4e9db42f | 0.592446 | 2.863028 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_axi_dma_0_0/synth/dma_loopback_axi_dma_0_0.vhd | 1 | 31,740 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_10;
USE axi_dma_v7_1_10.axi_dma;
ENTITY dma_loopback_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dma_loopback_axi_dma_0_0;
ARCHITECTURE dma_loopback_axi_dma_0_0_arch OF dma_loopback_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dma_loopback_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dma_loopback_axi_dma_0_0_arch: ARCHITECTURE IS "axi_dma,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dma_loopback_axi_dma_0_0_arch : ARCHITECTURE IS "dma_loopback_axi_dma_0_0,axi_dma,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dma_loopback_axi_dma_0_0_arch: ARCHITECTURE IS "dma_loopback_axi_dma_0_0,axi_dma,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dma,x_ipVersion=7.1,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_S_AXI_LITE_ADDR_WIDTH=10,C_S_AXI_LITE_DATA_WIDTH=32,C_DLYTMR_RESOLUTION=125,C_PRMRY_IS_ACLK_ASYNC=0,C_ENABLE_MULTI_CHANNEL=0,C_NUM_MM2S_CHANNELS=1,C_NUM_S2MM_CHANNELS=1,C_INCLUDE_SG=1,C_SG_INCLUDE_STSCNTRL_STRM=0,C_SG_USE_STSAPP_LENGTH=0,C_SG_LENGTH_WIDTH=23,C_M_AXI_SG_ADDR_WIDTH=32,C_M_AXI_SG_DATA_WIDTH" &
"=32,C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH=32,C_S_AXIS_S2MM_STS_TDATA_WIDTH=32,C_MICRO_DMA=0,C_INCLUDE_MM2S=1,C_INCLUDE_MM2S_SF=1,C_MM2S_BURST_SIZE=16,C_M_AXI_MM2S_ADDR_WIDTH=32,C_M_AXI_MM2S_DATA_WIDTH=32,C_M_AXIS_MM2S_TDATA_WIDTH=32,C_INCLUDE_MM2S_DRE=0,C_INCLUDE_S2MM=1,C_INCLUDE_S2MM_SF=1,C_S2MM_BURST_SIZE=16,C_M_AXI_S2MM_ADDR_WIDTH=32,C_M_AXI_S2MM_DATA_WIDTH=32,C_S_AXIS_S2MM_TDATA_WIDTH=32,C_INCLUDE_S2MM_DRE=0,C_FAMILY=zynq}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END dma_loopback_axi_dma_0_0_arch;
| mit | 01a43499358c7a7970829130704519ec | 0.682231 | 2.757363 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/types_river.vhd | 1 | 13,444 | --!
--! Copyright 2020 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
use ambalib.types_bus0.all; -- TODO: REMOVE ME when update dsu
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
--! @brief Declaration of components visible on SoC top level.
package types_river is
-- Number of CPU per one workgroup:
constant CFG_LOG2_CPU_MAX : integer := 2; -- 1=Dual-core (maximum); 2=Quad-core (maximum)
constant CFG_TOTAL_CPU_MAX : integer := 2**CFG_LOG2_CPU_MAX;
-- +1 Coherent SBA debug port (not available in River)
-- +1 ACP coherent port (not available in River)
constant CFG_SLOT_L1_TOTAL : integer := CFG_TOTAL_CPU_MAX + 0;
-- AXI4 with ACE channels
type axi4_l1_out_type is record
aw_valid : std_logic;
aw_bits : axi4_metadata_type;
aw_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
aw_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
w_valid : std_logic;
w_data : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
w_last : std_logic;
w_strb : std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
w_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
b_ready : std_logic;
ar_valid : std_logic;
ar_bits : axi4_metadata_type;
ar_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
ar_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
r_ready : std_logic;
-- ACE signals
ar_domain : std_logic_vector(1 downto 0); -- 00=Non-shareable (single master in domain)
ar_snoop : std_logic_vector(3 downto 0); -- Table C3-7:
ar_bar : std_logic_vector(1 downto 0); -- read barrier transaction
aw_domain : std_logic_vector(1 downto 0);
aw_snoop : std_logic_vector(3 downto 0); -- Table C3-8
aw_bar : std_logic_vector(1 downto 0); -- write barrier transaction
ac_ready : std_logic;
cr_valid : std_logic;
cr_resp : std_logic_vector(4 downto 0);
cd_valid : std_logic;
cd_data : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
cd_last : std_logic;
rack : std_logic;
wack : std_logic;
end record;
constant axi4_l1_out_none : axi4_l1_out_type := (
'0', META_NONE, (others=>'0'), (others => '0'),
'0', (others=>'0'), '0', (others=>'0'), (others => '0'),
'0', '0', META_NONE, (others=>'0'), (others => '0'), '0',
"00", X"0", "00", "00", X"0", "00", '0', '0',
"00000", '0', (others => '0'), '0', '0', '0');
type axi4_l1_in_type is record
aw_ready : std_logic;
w_ready : std_logic;
b_valid : std_logic;
b_resp : std_logic_vector(1 downto 0);
b_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
b_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
ar_ready : std_logic;
r_valid : std_logic;
r_resp : std_logic_vector(3 downto 0);
r_data : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
r_last : std_logic;
r_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
r_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
-- ACE signals
ac_valid : std_logic;
ac_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
ac_snoop : std_logic_vector(3 downto 0); -- Table C3-19
ac_prot : std_logic_vector(2 downto 0);
cr_ready : std_logic;
cd_ready : std_logic;
end record;
constant axi4_l1_in_none : axi4_l1_in_type := (
'0', '0', '0', AXI_RESP_OKAY, (others=>'0'), (others => '0'),
'0', '0', (others => '0'), (others=>'0'), '0', (others=>'0'), (others => '0'),
'0', (others => '0'), X"0", "000", '0', '0');
type axi4_l1_in_vector is array (0 to CFG_SLOT_L1_TOTAL-1) of axi4_l1_in_type;
type axi4_l1_out_vector is array (0 to CFG_SLOT_L1_TOTAL-1) of axi4_l1_out_type;
-- L2 AXI structure
type axi4_l2_out_type is record
aw_valid : std_logic;
aw_bits : axi4_metadata_type;
aw_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
aw_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
w_valid : std_logic;
w_data : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
w_last : std_logic;
w_strb : std_logic_vector(L1CACHE_BYTES_PER_LINE-1 downto 0);
w_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
b_ready : std_logic;
ar_valid : std_logic;
ar_bits : axi4_metadata_type;
ar_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
ar_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
r_ready : std_logic;
end record;
constant axi4_l2_out_none : axi4_l2_out_type := (
'0', META_NONE, (others=>'0'), (others => '0'),
'0', (others=>'0'), '0', (others=>'0'), (others => '0'),
'0', '0', META_NONE, (others=>'0'), (others => '0'), '0'
);
type axi4_l2_in_type is record
aw_ready : std_logic;
w_ready : std_logic;
b_valid : std_logic;
b_resp : std_logic_vector(1 downto 0);
b_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
b_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
ar_ready : std_logic;
r_valid : std_logic;
r_resp : std_logic_vector(1 downto 0);
r_data : std_logic_vector(L1CACHE_LINE_BITS-1 downto 0);
r_last : std_logic;
r_id : std_logic_vector(CFG_CPU_ID_BITS-1 downto 0);
r_user : std_logic_vector(CFG_CPU_USER_BITS-1 downto 0);
end record;
constant axi4_l2_in_none : axi4_l2_in_type := (
'0', '0', '0', AXI_RESP_OKAY, (others=>'0'), (others => '0'),
'0', '0', (others => '0'), (others=>'0'), '0', (others=>'0'), (others => '0')
);
-- River Debug port interface
type dport_in_type is record
req_valid : std_logic;
resp_ready : std_logic;
write : std_logic;
addr : std_logic_vector(CFG_DPORT_ADDR_BITS-1 downto 0);
wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
end record;
constant dport_in_none : dport_in_type := (
'0', '1', '0', (others => '0'), (others => '0'));
type dport_in_vector is array (0 to CFG_TOTAL_CPU_MAX-1)
of dport_in_type;
type dport_out_type is record
halted : std_logic;
available : std_logic;
req_ready : std_logic;
resp_valid : std_logic;
rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
end record;
constant dport_out_none : dport_out_type := (
'0', '0', '1', '1', (others => '0'));
type dport_out_vector is array (0 to CFG_TOTAL_CPU_MAX-1)
of dport_out_type;
--! @brief Declaration of the Debug Support Unit with the AXI interface.
--! @details This module provides access to processors CSRs via HostIO bus.
--! @param[in] clk System clock (BUS/CPU clock).
--! @param[in] rstn Reset signal with active LOW level.
--! @param[in] i_axi Slave slot input signals.
--! @param[out] o_axi Slave slot output signals.
--! @param[out] o_dporti Debug port output signals connected to River CPU.
--! @param[in] i_dporto River CPU debug port response signals.
--! @param[out] o_soft_rstn Software reset CPU and interrupt controller. Active HIGH
--! @param[in] i_bus_util_w Write bus access utilization per master statistic
--! @param[in] i_bus_util_r Write bus access utilization per master statistic
component axi_dsu is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_dporti : out dport_in_vector;
i_dporto : in dport_out_vector;
i_dmi_hartsel : in std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
o_dmi_req_valid : out std_logic;
i_dmi_req_ready : in std_logic;
o_dmi_write : out std_logic;
o_dmi_addr : out std_logic_vector(6 downto 0);
o_dmi_wdata : out std_logic_vector(31 downto 0);
i_dmi_resp_valid : in std_logic;
o_dmi_resp_ready : out std_logic;
i_dmi_rdata : in std_logic_vector(31 downto 0);
i_bus_util_w : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
i_bus_util_r : in std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0)
);
end component;
component dmi_regs is
generic (
async_reset : boolean := false;
cpu_available : integer := 1
);
port
(
clk : in std_logic;
nrst : in std_logic;
-- port[0] connected to JTAG TAP has access to AXI master interface (SBA registers)
i_dmi_jtag_req_valid : in std_logic;
o_dmi_jtag_req_ready : out std_logic;
i_dmi_jtag_write : in std_logic;
i_dmi_jtag_addr : in std_logic_vector(6 downto 0);
i_dmi_jtag_wdata : in std_logic_vector(31 downto 0);
o_dmi_jtag_resp_valid : out std_logic;
i_dmi_jtag_resp_ready : in std_logic;
o_dmi_jtag_rdata : out std_logic_vector(31 downto 0);
-- port[1] connected to DSU doesn't have access to AXI master interface
i_dmi_dsu_req_valid : in std_logic;
o_dmi_dsu_req_ready : out std_logic;
i_dmi_dsu_write : in std_logic;
i_dmi_dsu_addr : in std_logic_vector(6 downto 0);
i_dmi_dsu_wdata : in std_logic_vector(31 downto 0);
o_dmi_dsu_resp_valid : out std_logic;
i_dmi_dsu_resp_ready : in std_logic;
o_dmi_dsu_rdata : out std_logic_vector(31 downto 0);
-- Common signals
o_hartsel : out std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
o_dmstat : out std_logic_vector(1 downto 0);
o_ndmreset : out std_logic; -- non-debug module reset
o_cfg : out axi4_master_config_type;
i_xmsti : in axi4_master_in_type;
o_xmsto : out axi4_master_out_type;
o_dporti : out dport_in_vector;
i_dporto : in dport_out_vector
);
end component;
--! Dport interconnect to switch DSU and DMI access
component ic_dport_2s_1m is
generic (
async_reset : boolean := false
);
port
(
clk : in std_logic;
nrst : in std_logic;
-- Group <=> DMI interface
i_sdport0i : in dport_in_vector;
o_sdport0o : out dport_out_vector;
-- Group <=> DSU interface
i_sdport1i : in dport_in_vector;
o_sdport1o : out dport_out_vector;
-- Group connection
o_mdporti : out dport_in_vector;
i_mdporto : in dport_out_vector
);
end component;
--! @brief RIVER CPU component declaration.
--! @details This module implements Risc-V CPU Core named as
--! "RIVER" with AXI interface.
--! @param[in] xindex AXI master index
--! @param[in] i_rstn Reset signal with active LOW level.
--! @param[in] i_clk System clock (BUS/CPU clock).
--! @param[in] i_msti Bus-to-Master device signals.
--! @param[out] o_msto CachedTile-to-Bus request signals.
--! @param[in] i_ext_irq Interrupts line supported by Rocket chip.
component river_amba is
generic (
memtech : integer;
hartid : integer;
async_reset : boolean;
fpu_ena : boolean;
coherence_ena : boolean;
tracer_ena : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_msti : in axi4_l1_in_type;
o_msto : out axi4_l1_out_type;
i_dport : in dport_in_type;
o_dport : out dport_out_type;
i_ext_irq : in std_logic
);
end component;
-- Processor stub should be instantiated for unused CPU slot
component river_dummycpu is
port (
o_msto : out axi4_l1_out_type;
o_dport : out dport_out_type;
o_flush_l2 : out std_logic
);
end component;
-- L2 cache dummy implementation. Real L2 implemented in Wasserfall SoC.
component RiverL2Dummy is
generic (
async_reset : boolean := false
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
-- CPUs Workgroup
i_l1o : in axi4_l1_out_vector;
o_l1i : out axi4_l1_in_vector;
-- System bus
i_l2i : in axi4_l2_in_type;
o_l2o : out axi4_l2_out_type;
i_flush_valid : std_logic
);
end component;
-- Convert L2 cache lines into system bus transactions
component river_l2serdes is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_l2o : in axi4_l2_out_type;
o_l2i : out axi4_l2_in_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type
);
end component;
-- River CPU group with L2-cache (stub or real)
component river_workgroup is
generic (
cpunum : integer;
memtech : integer;
async_reset : boolean;
fpu_ena : boolean;
coherence_ena : boolean;
tracer_ena : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type;
i_dport : in dport_in_vector;
o_dport : out dport_out_vector;
i_ext_irq : in std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0)
);
end component;
end; -- package body
| apache-2.0 | 6cf6abb3c1e39abe968658c62ec56a41 | 0.632475 | 2.901165 | false | false | false | false |
szanni/aeshw | zybo-base/lib/Digilent/hdmi_tx_1.0/hdl/DVITransmitter.vhd | 1 | 13,805 | --------------------------------------------------------------------------------
--
-- File:
-- DVITransmitter.vhd
--
-- Module:
-- DVITransmitter
--
-- Author:
-- Elod Gyorgy
--
-- Date:
-- 04/06/2011
--
-- Description:
-- DVITransmitter takes 24-bit RGB video data with proper sync
-- signals and transmits them on a DVI or HDMI port. The encoding and serialization
-- is done according to the Digital Visual Interface (DVI) specifications Rev 1.0.
--
-- Copyright notice:
-- Copyright (C) 2014 Digilent Inc.
--
-- License:
-- This program is free software; distributed under the terms of
-- BSD 3-clause license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
-- IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
-- OF THE POSSIBILITY OF SUCH DAMAGE.
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--library digilent;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity DVITransmitter is
Generic (FAMILY : STRING := "spartan6");
Port ( RED_I : in STD_LOGIC_VECTOR (7 downto 0);
GREEN_I : in STD_LOGIC_VECTOR (7 downto 0);
BLUE_I : in STD_LOGIC_VECTOR (7 downto 0);
HS_I : in STD_LOGIC;
VS_I : in STD_LOGIC;
VDE_I : in STD_LOGIC;
RST_I : in STD_LOGIC;
PCLK_I : in STD_LOGIC;
PCLK_X5_I : in STD_LOGIC;
TMDS_TX_CLK_P : out STD_LOGIC;
TMDS_TX_CLK_N : out STD_LOGIC;
TMDS_TX_2_P : out STD_LOGIC;
TMDS_TX_2_N : out STD_LOGIC;
TMDS_TX_1_P : out STD_LOGIC;
TMDS_TX_1_N : out STD_LOGIC;
TMDS_TX_0_P : out STD_LOGIC;
TMDS_TX_0_N : out STD_LOGIC);
end DVITransmitter;
architecture Behavioral of DVITransmitter is
signal intTmdsRed, intTmdsGreen, intTmdsBlue : std_logic_vector(9 downto 0);
signal tmds_p, tmds_n : std_logic_vector(3 downto 0);
signal int_rst, SerClk : std_logic;
constant CLKIN_PERIOD : REAL := 13.468; --ns = 74.25MHz (maximum supported pixel clock)
constant N : NATURAL := 10; --serialization factor
constant PLLO0 : NATURAL := 1; -- SERCLK = PCLK * N
constant PLLO2 : NATURAL := PLLO0 * N; -- PCLK = PCLK * N / N
constant PLLO3 : NATURAL := PLLO0 * N / 2; -- PCLK_X2 = PLCK * N / (N/2)
signal intfb, intfb_buf, intpllout_x2, pllout_xs, pllout_x1, pllout_x2: std_logic;
signal PClk, PClk_x2, PllLckd, PllRst, intRst, BufPllLckd, SerStb : std_logic;
component SerializerN_1 is
Generic ( N : NATURAL := 10;
FAMILY : STRING := "spartan6");
Port ( DP_I : in STD_LOGIC_VECTOR (N-1 downto 0);
CLKDIV_I : in STD_LOGIC; --parallel slow clock
CLKDIV_X2_I : in STD_LOGIC; --double parallel slow clock (CLKDIV_I x 2) REQUIRED ONLY FOR Spartan-6
SERCLK_I : in STD_LOGIC; --serial fast clock (CLK_I = CLKDIV_I x N / 2)
SERSTB_I : in STD_LOGIC; -- REQUIRED ONLY FOR Spartan-6
RST_I : in STD_LOGIC; --async reset
DSP_O : out STD_LOGIC;
DSN_O : out STD_LOGIC);
end component;
component TMDSEncoder is
Port ( D_I : in STD_LOGIC_VECTOR (7 downto 0);
C0_I : in STD_LOGIC;
C1_I : in STD_LOGIC;
DE_I : in STD_LOGIC;
CLK_I: in STD_LOGIC;
RST_I: in STD_LOGIC;
D_O : out STD_LOGIC_VECTOR (9 downto 0));
end component;
begin
PllRst <= RST_I;
family_s6: if FAMILY = "spartan6" generate
begin
----------------------------------------------------------------------------------
-- Serialization PLL
-- This PLL generates the x2 and x10 pixel clock needed for TMDS serialization
----------------------------------------------------------------------------------
Inst_10_1_pll : PLL_BASE generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => N, -- multiplication factor for all output clocks
COMPENSATION => "INTERNAL", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => 1, -- division factor for all clocks (1 to 52)
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLK_FEEDBACK => "CLKFBOUT",
CLKIN_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKOUT0_DIVIDE => PLLO0, -- division factor for clkout0 (1 to 128)
CLKOUT2_DIVIDE => PLLO2, -- division factor for clkout2 (1 to 128)
CLKOUT3_DIVIDE => PLLO3, -- division factor for clkout3 (1 to 128)
REF_JITTER => 0.025) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBOUT => intfb, -- general output feedback signal
CLKFBIN => intfb_buf, -- clock feedback input
CLKOUT0 => pllout_xs, -- x10 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => pllout_x1, -- x1 clock for BUFG
CLKOUT3 => pllout_x2, -- x2 clock for BUFG
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
LOCKED => PllLckd, -- active high pll lock signal
CLKIN => PCLK_I, -- primary clock input
RST => PllRst); -- asynchronous pll reset
intfb_buf <= intfb;
----------------------------------------------------------------------------------
-- Route the pixel clock and 2x pixel clock through the global clock network
----------------------------------------------------------------------------------
BUFG_inst1 : BUFG port map ( O => PClk, I => pllout_x1 );
BUFG_inst2 : BUFG port map ( O => intpllout_x2, I => pllout_x2 );
PClk_x2 <= intpllout_x2;
----------------------------------------------------------------------------------
-- Route High-Speed serialization clock to OSERDES2 primitives in the whole bank
----------------------------------------------------------------------------------
BUFPLL_inst : BUFPLL
generic map (
DIVIDE => N/2, -- DIVCLK divider (1-8)
ENABLE_SYNC => TRUE -- Enable synchrnonization between PLL and GCLK (TRUE/FALSE)
)
port map (
IOCLK => SerClk, -- 1-bit Output I/O clock
LOCK => BufPllLckd, -- 1-bit Synchronized LOCK output
SERDESSTROBE => SerStb, -- 1-bit Output SERDES strobe (connect to ISERDES/OSERDES)
GCLK => intpllout_x2, -- 1-bit BUFG clock input
LOCKED => PllLckd, -- 1-bit LOCKED input from PLL
PLLIN => pllout_xs -- 1-bit Clock input from PLL
);
intRst <= not BufPllLckd or not PllLckd;
end generate family_s6;
family_7: if FAMILY = "kintex7" or FAMILY = "artix7" or FAMILY = "virtex7" generate
begin
----------------------------------------------------------------------------------
-- Serialization PLL
-- This PLL generates the x5 pixel clock needed for TMDS serialization on series-7
-- architectures.
----------------------------------------------------------------------------------
-- PLLE2_BASE_inst : PLLE2_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED", -- Jitter programming (OPTIMIZED, HIGH, LOW)
-- STARTUP_WAIT => "FALSE", -- Delays DONE until MMCM is locked (FALSE, TRUE)
--
-- CLKFBOUT_MULT => 10, -- Multiply value for all CLKOUT (2.000-64.000).
-- CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB (-360.000-360.000).
-- DIVCLK_DIVIDE => 1, -- Master division value (1-106)
-- CLKIN1_PERIOD => 9.259, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
--
-- CLKOUT0_DIVIDE => 2,
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DIVIDE => 10,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT1_DUTY_CYCLE => 0.500,
--
-- REF_JITTER1 => 0.010 -- Reference input jitter in UI (0.000-0.999).
-- )
-- port map (
-- -- Clock Outputs: 1-bit (each) output: User configurable clock outputs
-- CLKOUT0 => pllout_xs, -- Serial Clock = Parallel Clock x 5 (DDR)
-- CLKOUT1 => pllout_x1, -- Parallel Clock Buffered, Phase-aligned with Serial Clock
-- CLKOUT2 => open, -- 1-bit output: CLKOUT2
-- CLKOUT3 => open, -- 1-bit output: CLKOUT3
-- CLKOUT4 => open, -- 1-bit output: CLKOUT4
-- CLKOUT5 => open, -- 1-bit output: CLKOUT5
-- -- Feedback Clocks: 1-bit (each) output: Clock feedback ports
-- CLKFBOUT => intfb, -- 1-bit output: Feedback clock
-- -- Status Ports: 1-bit (each) output: MMCM status ports
-- LOCKED => PllLckd, -- 1-bit output: LOCK
-- -- Clock Inputs: 1-bit (each) input: Clock input
-- CLKIN1 => PCLK_I, -- 1-bit input: Clock
-- -- Control Ports: 1-bit (each) input: MMCM control ports
-- PWRDWN => '0', -- 1-bit input: Power-down
-- RST => PllRst, -- 1-bit input: Reset
-- -- Feedback Clocks: 1-bit (each) input: Clock feedback ports
-- CLKFBIN => intfb_buf -- 1-bit input: Feedback clock
-- );
-- -- Output buffering
-- -------------------------------------
-- clkf_buf : BUFG
-- port map
-- (O => intfb_buf,
-- I => intfb);
--
--
-- clkout0_buf : BUFG
-- port map
-- (O => SerClk,
-- I => pllout_xs);
--
--
--
-- clkout1_buf : BUFG
-- port map
-- (O => PClk,
-- I => pllout_x1);
--
--intRst <= not PllLckd;
PClk <= PCLK_I;
SerClk <= PCLK_X5_I;
intRst <= RST_I;
end generate family_7;
----------------------------------------------------------------------------------
-- DVI Encoder; DVI 1.0 Specifications
-- This component encodes 24-bit RGB video frames with sync signals into 10-bit
-- TMDS characters.
----------------------------------------------------------------------------------
Inst_TMDSEncoder_red: TMDSEncoder PORT MAP(
D_I => RED_I,
C0_I => '0',
C1_I => '0',
DE_I => VDE_I,
CLK_I => PClk,
RST_I => intRst,
D_O => intTmdsRed
);
Inst_TMDSEncoder_green: TMDSEncoder PORT MAP(
D_I => GREEN_I,
C0_I => '0',
C1_I => '0',
DE_I => VDE_I,
CLK_I => PClk,
RST_I => intRst,
D_O => intTmdsGreen
);
Inst_TMDSEncoder_blue: TMDSEncoder PORT MAP(
D_I => BLUE_I,
C0_I => HS_I,
C1_I => VS_I,
DE_I => VDE_I,
CLK_I => PClk,
RST_I => intRst,
D_O => intTmdsBlue
);
----------------------------------------------------------------------------------
-- TMDS serializer; ratio of 10:1; 3 data & 1 clock channel
-- Since the TMDS clock's period is character-long (10-bit periods), the
-- serialization of "1111100000" will result in a 10-bit long clock period.
----------------------------------------------------------------------------------
Inst_clk_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY)
PORT MAP(
DP_I => "1111100000",
CLKDIV_I => PClk,
CLKDIV_X2_I => PClk_x2,
SERCLK_I => SerClk,
SERSTB_I => SerStb,
RST_I => intRst,
DSP_O => TMDS_TX_CLK_P,
DSN_O => TMDS_TX_CLK_N
);
Inst_d2_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY)
PORT MAP(
DP_I => intTmdsRed,
CLKDIV_I => PClk,
CLKDIV_X2_I => PClk_x2,
SERCLK_I => SerClk,
SERSTB_I => SerStb,
RST_I => intRst,
DSP_O => TMDS_TX_2_P,
DSN_O => TMDS_TX_2_N
);
Inst_d1_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY)
PORT MAP(
DP_I => intTmdsGreen,
CLKDIV_I => PClk,
CLKDIV_X2_I => PClk_x2,
SERCLK_I => SerClk,
SERSTB_I => SerStb,
RST_I => intRst,
DSP_O => TMDS_TX_1_P,
DSN_O => TMDS_TX_1_N
);
Inst_d0_serializer_10_1: SerializerN_1 GENERIC MAP (10, FAMILY)
PORT MAP(
DP_I => intTmdsBlue,
CLKDIV_I => PClk,
CLKDIV_X2_I => PClk_x2,
SERCLK_I => SerClk,
SERSTB_I => SerStb,
RST_I => intRst,
DSP_O => TMDS_TX_0_P,
DSN_O => TMDS_TX_0_N
);
end Behavioral;
| bsd-2-clause | bc8ef3c7d2897e561c76fe55889ab4b6 | 0.55306 | 3.456435 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/common/shft_ram.vhd | 19 | 17,157 | `protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
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`protect end_protected
| bsd-2-clause | 094aa820726e4371e51ffada3852c755 | 0.938917 | 1.863473 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_logic_pkt_fifo.vhd | 19 | 44,022 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30848)
`protect data_block
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| bsd-2-clause | 9c03b37a0b2d6a80a11f532611b147d2 | 0.94789 | 1.82884 | false | false | false | false |
szanni/aeshw | aes-core/key_expansion_tb.vhd | 1 | 5,285 | --------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:02:57 07/14/2014
-- Design Name:
-- Module Name: /home/qfi/Documents/aeshw/aes-core/aes-core/key_expansion_tb.vhd
-- Project Name: aes-core
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: key_expansion
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY key_expansion_tb IS
END key_expansion_tb;
ARCHITECTURE behavior OF key_expansion_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT key_expansion
PORT(
clk : IN std_logic;
reset : IN std_logic;
exp_start : IN std_logic;
exp_end : OUT std_logic;
address_in : IN std_logic_vector(3 downto 0);
key_in : IN std_logic_vector(127 downto 0);
key_out : OUT std_logic_vector(127 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal exp_start : std_logic := '0';
signal address_in : std_logic_vector(3 downto 0) := (others => '0');
signal key_in : std_logic_vector(127 downto 0) := (others => '0');
--Outputs
signal exp_end : std_logic;
signal key_out : std_logic_vector(127 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: key_expansion PORT MAP (
clk => clk,
reset => reset,
exp_start => exp_start,
exp_end => exp_end,
address_in => address_in,
key_in => key_in,
key_out => key_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period;
exp_start <= '1';
key_in <= x"2b7e151628aed2a6abf7158809cf4f3c";
wait for clk_period;
assert exp_end = '0' report "key expansion module: failure" severity failure;
-- expander and counter now initialized
exp_start <= '0';
-- wait until expansion is finished
for i in 1 to 10 loop
wait for clk_period;
assert exp_end = '0' report "key expansion module: failure" severity failure;
end loop;
wait for clk_period;
-- expansion should now be finished
assert exp_end = '1' report "key expansion module: failure" severity failure;
wait for clk_period;
-- expansion is ready again
assert exp_end = '0' report "key expansion module: failure" severity failure;
wait for clk_period*10;
-- lookup ram values
address_in <= x"0";
wait for clk_period;
assert key_out = x"2b7e151628aed2a6abf7158809cf4f3c" report "ram module : lookup failure (address 0)" severity failure;
address_in <= x"1";
wait for clk_period;
assert key_out = x"a0fafe1788542cb123a339392a6c7605" report "ram module : lookup failure (address 1)" severity failure;
address_in <= x"2";
wait for clk_period;
assert key_out = x"f2c295f27a96b9435935807a7359f67f" report "ram module : lookup failure (address 2)" severity failure;
address_in <= x"3";
wait for clk_period;
assert key_out = x"3d80477d4716fe3e1e237e446d7a883b" report "ram module : lookup failure (address 3)" severity failure;
address_in <= x"4";
wait for clk_period;
assert key_out = x"ef44a541a8525b7fb671253bdb0bad00" report "ram module : lookup failure (address 4)" severity failure;
address_in <= x"5";
wait for clk_period;
assert key_out = x"d4d1c6f87c839d87caf2b8bc11f915bc" report "ram module : lookup failure (address 5)" severity failure;
address_in <= x"6";
wait for clk_period;
assert key_out = x"6d88a37a110b3efddbf98641ca0093fd" report "ram module : lookup failure (address 6)" severity failure;
address_in <= x"7";
wait for clk_period;
assert key_out = x"4e54f70e5f5fc9f384a64fb24ea6dc4f" report "ram module : lookup failure (address 7)" severity failure;
address_in <= x"8";
wait for clk_period;
assert key_out = x"ead27321b58dbad2312bf5607f8d292f" report "ram module : lookup failure (address 8)" severity failure;
address_in <= x"9";
wait for clk_period;
assert key_out = x"ac7766f319fadc2128d12941575c006e" report "ram module : lookup failure (address 9)" severity failure;
address_in <= x"A";
wait for clk_period;
assert key_out = x"d014f9a8c9ee2589e13f0cc8b6630ca6" report "ram module : lookup failure (address A)" severity failure;
wait;
end process;
END;
| bsd-2-clause | b6eb70eafdf6c9ab468985756930653d | 0.65071 | 3.338598 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_9P6_50MHZ_SCH/CTRL_RS232_TX_VHDL.vhd | 2 | 9,165 | -- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 14.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
--signal SEND_BYTE_S : std_logic_vector (7 downto 0); --Eingangsvariable, Zwischengespeichern im Eingangsregister
--signal SEND_S : std_logic; --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
--Konstanten, lang 9600 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
constant CNT01 : std_logic_vector := x"1458"; --16 Bit
constant CNT02 : std_logic_vector := x"2C98"; --usw.
constant CNT03 : std_logic_vector := x"3D08";
constant CNT04 : std_logic_vector := x"5160";
constant CNT05 : std_logic_vector := x"65B8";
constant CNT06 : std_logic_vector := x"7A10";
constant CNT07 : std_logic_vector := x"8E68";
constant CNT08 : std_logic_vector := x"A2C0";
constant CNT09 : std_logic_vector := x"B718";
constant CNT10 : std_logic_vector := x"CB70";
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
--NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
--IREG_PROC: process (not_CLK_IO) --Eingangsregister
--begin
-- if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
-- then SEND_BYTE_S <= SEND_BYTE;
-- SEND_S <= SEND;
--end if;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND, SEND_BYTE) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
end Behavioral;
| gpl-2.0 | 193fe70a309ff5c5c31a8934a47e1a7b | 0.544899 | 3.184503 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/delay.vhd | 19 | 10,088 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5728)
`protect data_block
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`protect end_protected
| bsd-2-clause | 6e7e6ac8a12600e7d325555c7b5ce098 | 0.925456 | 1.904474 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/async_fifo.vhd | 19 | 33,343 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 22944)
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48UBk62/+Mv275JWCvhrm8lG7TrS/wW2lMw0Gn6z
`protect end_protected
| bsd-2-clause | df9ad0e34817253b4be6421120721b1a | 0.945596 | 1.825913 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/ibufg_tech.vhd | 1 | 965 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual clock buffered output.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ibufg_tech is
generic
(
tech : integer := 0
);
port (
O : out std_ulogic;
I : in std_ulogic
);
end;
architecture rtl of ibufg_tech is
component ibufg_xilinx is
port (
O : out std_ulogic;
I : in std_ulogic
);
end component;
signal w_o : std_logic;
begin
inf : if tech = inferred generate
w_o <= I;
end generate;
xlnx : if tech = virtex6 or tech = kintex7 generate
x0 : ibufg_xilinx port map (
O => w_o,
I => I
);
end generate;
O <= w_o;
end;
| apache-2.0 | feccbbb254a1edb857cc175b84bc3cf6 | 0.489119 | 4.004149 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/sim_gnss/config_sim.vhd | 1 | 2,741 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := inferred;
constant CFG_MEMTECH : integer := inferred;
constant CFG_PADTECH : integer := inferred;
constant CFG_JTAGTECH : integer := inferred;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
-- CFG_TOPDIR & "examples/bootrom_tests/linuxbuild/bin/bootrom_tests.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
-- CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
CFG_TOPDIR & "examples/gnss_fw/makefiles/bin/gnssfw.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20190524";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := true;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := true;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := true;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := true;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
| apache-2.0 | d451eab1460663346ed8c071400fa3b7 | 0.686246 | 3.904558 | false | false | false | false |
szanni/aeshw | aes-core/key_expansion.vhd | 1 | 2,455 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:25:50 07/14/2014
-- Design Name:
-- Module Name: key_expansion_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key_expansion is
port(
clk : in std_logic;
reset : in std_logic;
exp_start : in std_logic;
exp_end : out std_logic;
address_in : in std_logic_vector(3 downto 0);
key_in : in state;
key_out : out state
);
end key_expansion;
architecture Structural of key_expansion is
signal y_1_2, y_3_4 : std_logic_vector (1 downto 0);
signal y_we : std_logic;
signal x_comp : std_logic;
signal count : byte;
signal round_key : state;
signal rcon_in : byte;
begin
rcon_in <= count + 1;
expander : entity work.key_expander port map(clk => clk,
reset => reset,
y => y_1_2,
rcon_in => rcon_in,
key_in => key_in,
key_out => round_key
);
counter : entity work.counter port map (clk => clk,
reset => reset,
y => y_3_4,
x => x_comp,
d_out => count
);
ram : entity work.dp_ram port map(clk => clk,
address_read => address_in,
address_write => count (3 downto 0),
en_write => y_we,
din_write => round_key,
q => key_out
);
control_unit : entity work.key_expansion_cu port map (clk => clk,
reset => reset,
y_1_2 => y_1_2,
y_3_4 => y_3_4,
y_we => y_we,
y_end => exp_end,
x_start => exp_start,
x_comp => x_comp
);
end Structural;
| bsd-2-clause | 9b45c93d840b9e7bb43ebc620b67e4a5 | 0.498574 | 3.67515 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_register.vhd | 1 | 49,420 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_register.vhd
--
-- Description: This entity encompasses the channel register set.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_register is
generic(
C_NUM_REGISTERS : integer := 11 ;
C_INCLUDE_SG : integer := 1 ;
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
C_MICRO_DMA : integer range 0 to 1 := 0 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
--C_CHANNEL_IS_S2MM : integer range 0 to 1 := 0 CR603034
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- AXI Interface Control --
axi2ip_wrce : in std_logic_vector --
(C_NUM_REGISTERS-1 downto 0) ; --
axi2ip_wrdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- DMASR Control --
stop_dma : in std_logic ; --
halted_clr : in std_logic ; --
halted_set : in std_logic ; --
idle_set : in std_logic ; --
idle_clr : in std_logic ; --
ioc_irq_set : in std_logic ; --
dly_irq_set : in std_logic ; --
irqdelay_status : in std_logic_vector(7 downto 0) ; --
irqthresh_status : in std_logic_vector(7 downto 0) ; --
irqthresh_wren : out std_logic ; --
irqdelay_wren : out std_logic ; --
dlyirq_dsble : out std_logic ; -- CR605888
--
-- Error Control --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
ftch_interr_set : in std_logic ; --
ftch_slverr_set : in std_logic ; --
ftch_decerr_set : in std_logic ; --
ftch_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_interr_set : in std_logic ; --
updt_slverr_set : in std_logic ; --
updt_decerr_set : in std_logic ; --
updt_error_addr : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
error_in : in std_logic ; --
error_out : out std_logic ; --
introut : out std_logic ; --
soft_reset_in : in std_logic ; --
soft_reset_clr : in std_logic ; --
--
-- CURDESC Update --
update_curdesc : in std_logic ; --
new_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- TAILDESC Update --
tailpntr_updated : out std_logic ; --
--
-- Channel Register Out --
sg_ctl : out std_logic_vector (7 downto 0) ;
dmacr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
dmasr : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
curdesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_lsb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
taildesc_msb : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
buffer_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
buffer_length : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
buffer_length_wren : out std_logic ; --
bytes_received : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
bytes_received_wren : in std_logic --
); --
end axi_dma_register;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_register is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant DMACR_INDEX : integer := 0; -- DMACR Register index
constant DMASR_INDEX : integer := 1; -- DMASR Register index
constant CURDESC_LSB_INDEX : integer := 2; -- CURDESC LSB Reg index
constant CURDESC_MSB_INDEX : integer := 3; -- CURDESC MSB Reg index
constant TAILDESC_LSB_INDEX : integer := 4; -- TAILDESC LSB Reg index
constant TAILDESC_MSB_INDEX : integer := 5; -- TAILDESC MSB Reg index
-- CR603034 moved s2mm back to offset 6
--constant SA_ADDRESS_INDEX : integer := 6; -- Buffer Address Reg (SA)
--constant DA_ADDRESS_INDEX : integer := 8; -- Buffer Address Reg (DA)
--
--
--constant BUFF_ADDRESS_INDEX : integer := address_index_select -- Buffer Address Reg (SA or DA)
-- (C_CHANNEL_IS_S2MM, -- Channel Type 1=rx 0=tx
-- SA_ADDRESS_INDEX, -- Source Address Index
-- DA_ADDRESS_INDEX); -- Destination Address Index
constant BUFF_ADDRESS_INDEX : integer := 6;
constant BUFF_ADDRESS_MSB_INDEX : integer := 7;
constant BUFF_LENGTH_INDEX : integer := 10; -- Buffer Length Reg
constant SGCTL_INDEX : integer := 11; -- Buffer Length Reg
constant ZERO_VALUE : std_logic_vector(31 downto 0) := (others => '0');
constant DMA_CONFIG : std_logic_vector(0 downto 0)
:= std_logic_vector(to_unsigned(C_INCLUDE_SG,1));
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal dmacr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal dmasr_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal curdesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal curdesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal taildesc_lsb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 6) := (others => '0');
signal taildesc_msb_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_address_i_64 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal buffer_length_i : std_logic_vector
(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
-- DMASR Signals
signal halted : std_logic := '0';
signal idle : std_logic := '0';
signal cmplt : std_logic := '0';
signal error : std_logic := '0';
signal dma_interr : std_logic := '0';
signal dma_slverr : std_logic := '0';
signal dma_decerr : std_logic := '0';
signal sg_interr : std_logic := '0';
signal sg_slverr : std_logic := '0';
signal sg_decerr : std_logic := '0';
signal ioc_irq : std_logic := '0';
signal dly_irq : std_logic := '0';
signal error_d1 : std_logic := '0';
signal error_re : std_logic := '0';
signal err_irq : std_logic := '0';
signal sg_ftch_error : std_logic := '0';
signal sg_updt_error : std_logic := '0';
signal error_pointer_set : std_logic := '0';
-- interrupt coalescing support signals
signal different_delay : std_logic := '0';
signal different_thresh : std_logic := '0';
signal threshold_is_zero : std_logic := '0';
-- soft reset support signals
signal soft_reset_i : std_logic := '0';
signal run_stop_clr : std_logic := '0';
signal sg_cache_info : std_logic_vector (7 downto 0);
signal diff_thresh_xor : std_logic_vector (7 downto 0);
signal sig_cur_updated : std_logic;
signal tmp11 : std_logic;
signal tailpntr_updated_d1 : std_logic;
signal tailpntr_updated_d2 : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
dmacr <= dmacr_i ;
dmasr <= dmasr_i ;
curdesc_lsb <= curdesc_lsb_i (31 downto 6) & "000000" ;
curdesc_msb <= curdesc_msb_i ;
taildesc_lsb <= taildesc_lsb_i (31 downto 6) & "000000" ;
taildesc_msb <= taildesc_msb_i ;
BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
buffer_address <= buffer_address_i_64 & buffer_address_i ;
end generate BUFF_ADDR_EQL64;
BUFF_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
buffer_address <= buffer_address_i ;
end generate BUFF_ADDR_EQL32;
buffer_length <= buffer_length_i ;
---------------------------------------------------------------------------
-- DMA Control Register
---------------------------------------------------------------------------
-- DMACR - Interrupt Delay Value
-------------------------------------------------------------------------------
DMACR_DELAY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT
downto DMACR_IRQDELAY_LSB_BIT);
end if;
end if;
end process DMACR_DELAY;
-- If written delay is different than previous value then assert write enable
different_delay <= '1' when dmacr_i(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQDELAY_MSB_BIT downto DMACR_IRQDELAY_LSB_BIT)
else '0';
-- delay value different, drive write of delay value to interrupt controller
NEW_DELAY_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqdelay_wren <= '0';
-- If AXI Lite write to DMACR and delay different than current
-- setting then update delay value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_delay = '1')then
irqdelay_wren <= '1';
else
irqdelay_wren <= '0';
end if;
end if;
end process NEW_DELAY_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Interrupt Threshold Value
-------------------------------------------------------------------------------
threshold_is_zero <= '1' when axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) = ZERO_THRESHOLD
else '0';
DMACR_THRESH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- On AXI Lite write
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
-- If value is 0 then set threshold to 1
if(threshold_is_zero='1')then
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= ONE_THRESHOLD;
-- else set threshold to axi lite wrdata value
else
dmacr_i(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT) <= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT
downto DMACR_IRQTHRESH_LSB_BIT);
end if;
end if;
end if;
end process DMACR_THRESH;
--diff_thresh_xor <= dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT) xor
-- axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT);
--different_thresh <= '0' when diff_thresh_xor = "00000000"
-- else '1';
-- If written threshold is different than previous value then assert write enable
different_thresh <= '1' when dmacr_i(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
/= axi2ip_wrdata(DMACR_IRQTHRESH_MSB_BIT downto DMACR_IRQTHRESH_LSB_BIT)
else '0';
-- new treshold written therefore drive write of threshold out
NEW_THRESH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
irqthresh_wren <= '0';
-- If AXI Lite write to DMACR and threshold different than current
-- setting then update threshold value
elsif(axi2ip_wrce(DMACR_INDEX) = '1' and different_thresh = '1')then
irqthresh_wren <= '1';
else
irqthresh_wren <= '0';
end if;
end if;
end process NEW_THRESH_WRITE;
-------------------------------------------------------------------------------
-- DMACR - Remainder of DMA Control Register, Bit 3 for Key hole operation
-------------------------------------------------------------------------------
DMACR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1
downto DMACR_RESERVED5_BIT) <= (others => '0');
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_IRQTHRESH_LSB_BIT-1 -- bit 15
downto DMACR_RESERVED5_BIT) <= ZERO_VALUE(DMACR_RESERVED15_BIT)
-- bit 14
& axi2ip_wrdata(DMACR_ERR_IRQEN_BIT)
-- bit 13
& axi2ip_wrdata(DMACR_DLY_IRQEN_BIT)
-- bit 12
& axi2ip_wrdata(DMACR_IOC_IRQEN_BIT)
-- bits 11 downto 3
& ZERO_VALUE(DMACR_RESERVED11_BIT downto DMACR_RESERVED5_BIT);
end if;
end if;
end process DMACR_REGISTER;
DMACR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or C_ENABLE_MULTI_CHANNEL = 1)then
dmacr_i(DMACR_KH_BIT) <= '0';
dmacr_i(CYCLIC_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_KH_BIT) <= axi2ip_wrdata(DMACR_KH_BIT);
dmacr_i(CYCLIC_BIT) <= axi2ip_wrdata(CYCLIC_BIT);
end if;
end if;
end process DMACR_REGISTER1;
-------------------------------------------------------------------------------
-- DMACR - Reset Bit
-------------------------------------------------------------------------------
DMACR_RESET : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(soft_reset_clr = '1')then
dmacr_i(DMACR_RESET_BIT) <= '0';
-- If soft reset set in other channel then set
-- reset bit here too
elsif(soft_reset_in = '1')then
dmacr_i(DMACR_RESET_BIT) <= '1';
-- If DMACR Write then pass axi lite write bus to DMARC reset bit
elsif(soft_reset_i = '0' and axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RESET_BIT) <= axi2ip_wrdata(DMACR_RESET_BIT);
end if;
end if;
end process DMACR_RESET;
soft_reset_i <= dmacr_i(DMACR_RESET_BIT);
-------------------------------------------------------------------------------
-- Tail Pointer Enable fixed at 1 for this release of axi dma
-------------------------------------------------------------------------------
dmacr_i(DMACR_TAILPEN_BIT) <= '1';
-------------------------------------------------------------------------------
-- DMACR - Run/Stop Bit
-------------------------------------------------------------------------------
run_stop_clr <= '1' when error = '1' -- MM2S DataMover Error
or error_in = '1' -- S2MM Error
or stop_dma = '1' -- Stop due to error
or soft_reset_i = '1' -- MM2S Soft Reset
or soft_reset_in = '1' -- S2MM Soft Reset
else '0';
DMACR_RUNSTOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dmacr_i(DMACR_RS_BIT) <= '0';
-- Clear on sg error (i.e. error) or other channel
-- error (i.e. error_in) or dma error or soft reset
elsif(run_stop_clr = '1')then
dmacr_i(DMACR_RS_BIT) <= '0';
elsif(axi2ip_wrce(DMACR_INDEX) = '1')then
dmacr_i(DMACR_RS_BIT) <= axi2ip_wrdata(DMACR_RS_BIT);
end if;
end if;
end process DMACR_RUNSTOP;
---------------------------------------------------------------------------
-- DMA Status Halted bit (BIT 0) - Set by dma controller indicating DMA
-- channel is halted.
---------------------------------------------------------------------------
DMASR_HALTED : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or halted_set = '1')then
halted <= '1';
elsif(halted_clr = '1')then
halted <= '0';
end if;
end if;
end process DMASR_HALTED;
---------------------------------------------------------------------------
-- DMA Status Idle bit (BIT 1) - Set by dma controller indicating DMA
-- channel is IDLE waiting at tail pointer. Update of Tail Pointer
-- will cause engine to resume. Note: Halted channels return to a
-- reset condition.
---------------------------------------------------------------------------
DMASR_IDLE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0'
or idle_clr = '1'
or halted_set = '1')then
idle <= '0';
elsif(idle_set = '1')then
idle <= '1';
end if;
end if;
end process DMASR_IDLE;
---------------------------------------------------------------------------
-- DMA Status Error bit (BIT 3)
-- Note: any error will cause entire engine to halt
---------------------------------------------------------------------------
error <= dma_interr
or dma_slverr
or dma_decerr
or sg_interr
or sg_slverr
or sg_decerr;
-- Scatter Gather Error
--sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
-- SG Update Errors or DMA errors assert flag on descriptor update
-- Used to latch current descriptor pointer
--sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
-- or dma_interr or dma_slverr or dma_decerr;
-- Map out to halt opposing channel
error_out <= error;
SG_FTCH_ERROR_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_ftch_error <= '0';
sg_updt_error <= '0';
else
sg_ftch_error <= ftch_interr_set or ftch_slverr_set or ftch_decerr_set;
sg_updt_error <= updt_interr_set or updt_slverr_set or updt_decerr_set
or dma_interr or dma_slverr or dma_decerr;
end if;
end if;
end process SG_FTCH_ERROR_PROC;
---------------------------------------------------------------------------
-- DMA Status DMA Internal Error bit (BIT 4)
---------------------------------------------------------------------------
DMASR_DMAINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_interr <= '0';
elsif(dma_interr_set = '1' )then
dma_interr <= '1';
end if;
end if;
end process DMASR_DMAINTERR;
---------------------------------------------------------------------------
-- DMA Status DMA Slave Error bit (BIT 5)
---------------------------------------------------------------------------
DMASR_DMASLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_slverr <= '0';
elsif(dma_slverr_set = '1' )then
dma_slverr <= '1';
end if;
end if;
end process DMASR_DMASLVERR;
---------------------------------------------------------------------------
-- DMA Status DMA Decode Error bit (BIT 6)
---------------------------------------------------------------------------
DMASR_DMADECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dma_decerr <= '0';
elsif(dma_decerr_set = '1' )then
dma_decerr <= '1';
end if;
end if;
end process DMASR_DMADECERR;
---------------------------------------------------------------------------
-- DMA Status SG Internal Error bit (BIT 8)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGINTERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_interr <= '0';
elsif(ftch_interr_set = '1' or updt_interr_set = '1')then
sg_interr <= '1';
end if;
end if;
end process DMASR_SGINTERR;
---------------------------------------------------------------------------
-- DMA Status SG Slave Error bit (BIT 9)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGSLVERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_slverr <= '0';
elsif(ftch_slverr_set = '1' or updt_slverr_set = '1')then
sg_slverr <= '1';
end if;
end if;
end process DMASR_SGSLVERR;
---------------------------------------------------------------------------
-- DMA Status SG Decode Error bit (BIT 10)
-- (SG Mode only - trimmed at build time if simple mode)
---------------------------------------------------------------------------
DMASR_SGDECERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_decerr <= '0';
elsif(ftch_decerr_set = '1' or updt_decerr_set = '1')then
sg_decerr <= '1';
end if;
end if;
end process DMASR_SGDECERR;
---------------------------------------------------------------------------
-- DMA Status IOC Interrupt status bit (BIT 11)
---------------------------------------------------------------------------
DMASR_IOCIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ioc_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
ioc_irq <= (ioc_irq and not(axi2ip_wrdata(DMASR_IOCIRQ_BIT)))
or ioc_irq_set;
elsif(ioc_irq_set = '1')then
ioc_irq <= '1';
end if;
end if;
end process DMASR_IOCIRQ;
---------------------------------------------------------------------------
-- DMA Status Delay Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
DMASR_DLYIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
dly_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
dly_irq <= (dly_irq and not(axi2ip_wrdata(DMASR_DLYIRQ_BIT)))
or dly_irq_set;
elsif(dly_irq_set = '1')then
dly_irq <= '1';
end if;
end if;
end process DMASR_DLYIRQ;
-- CR605888 Disable delay timer if halted or on delay irq set
--dlyirq_dsble <= dmasr_i(DMASR_HALTED_BIT) -- CR606348
dlyirq_dsble <= not dmacr_i(DMACR_RS_BIT) -- CR606348
or dmasr_i(DMASR_DLYIRQ_BIT);
---------------------------------------------------------------------------
-- DMA Status Error Interrupt status bit (BIT 12)
---------------------------------------------------------------------------
-- Delay error setting for generation of error strobe
GEN_ERROR_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
error_d1 <= '0';
else
error_d1 <= error;
end if;
end if;
end process GEN_ERROR_RE;
-- Generate rising edge pulse on error
error_re <= error and not error_d1;
DMASR_ERRIRQ : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
err_irq <= '0';
-- CPU Writing a '1' to clear - OR'ed with setting to prevent
-- missing a 'set' during the write.
elsif(axi2ip_wrce(DMASR_INDEX) = '1' )then
err_irq <= (err_irq and not(axi2ip_wrdata(DMASR_ERRIRQ_BIT)))
or error_re;
elsif(error_re = '1')then
err_irq <= '1';
end if;
end if;
end process DMASR_ERRIRQ;
---------------------------------------------------------------------------
-- DMA Interrupt OUT
---------------------------------------------------------------------------
REG_INTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or soft_reset_i = '1')then
introut <= '0';
else
introut <= (dly_irq and dmacr_i(DMACR_DLY_IRQEN_BIT))
or (ioc_irq and dmacr_i(DMACR_IOC_IRQEN_BIT))
or (err_irq and dmacr_i(DMACR_ERR_IRQEN_BIT));
end if;
end if;
end process;
---------------------------------------------------------------------------
-- DMA Status Register
---------------------------------------------------------------------------
dmasr_i <= irqdelay_status -- Bits 31 downto 24
& irqthresh_status -- Bits 23 downto 16
& '0' -- Bit 15
& err_irq -- Bit 14
& dly_irq -- Bit 13
& ioc_irq -- Bit 12
& '0' -- Bit 11
& sg_decerr -- Bit 10
& sg_slverr -- Bit 9
& sg_interr -- Bit 8
& '0' -- Bit 7
& dma_decerr -- Bit 6
& dma_slverr -- Bit 5
& dma_interr -- Bit 4
& DMA_CONFIG -- Bit 3
& '0' -- Bit 2
& idle -- Bit 1
& halted; -- Bit 0
-- Generate current descriptor and tail descriptor register for Scatter Gather Mode
GEN_DESC_REG_FOR_SG : if C_INCLUDE_SG = 1 generate
begin
GEN_SG_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
MM2S_SGCTL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sg_cache_info <= "00000011"; --(others => '0');
elsif(axi2ip_wrce(SGCTL_INDEX) = '1' ) then
sg_cache_info <= axi2ip_wrdata(11 downto 8) & axi2ip_wrdata(3 downto 0);
else
sg_cache_info <= sg_cache_info;
end if;
end if;
end process MM2S_SGCTL;
sg_ctl <= sg_cache_info;
end generate GEN_SG_CTL_REG;
GEN_SG_NO_CTL_REG : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
sg_ctl <= "00000011"; --(others => '0');
end generate GEN_SG_NO_CTL_REG;
-- Signals not used for Scatter Gather Mode, only simple mode
buffer_address_i <= (others => '0');
buffer_length_i <= (others => '0');
buffer_length_wren <= '0';
---------------------------------------------------------------------------
-- Current Descriptor LSB Register
---------------------------------------------------------------------------
CURDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_lsb_i <= (others => '0');
error_pointer_set <= '0';
-- Detected error has NOT register a desc pointer
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_lsb_i <= ftch_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '1';
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_lsb_i <= updt_error_addr(C_S_AXI_LITE_DATA_WIDTH-1 downto 0);
-- error_pointer_set <= '1';
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_lsb_i <= new_curdesc(C_S_AXI_LITE_DATA_WIDTH-1 downto 6);
error_pointer_set <= '0';
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_LSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_lsb_i <= axi2ip_wrdata(CURDESC_LOWER_MSB_BIT
downto CURDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(CURDESC_RESERVED_BIT5
-- downto CURDESC_RESERVED_BIT0);
error_pointer_set <= '0';
end if;
end if;
end if;
end process CURDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor LSB Register
---------------------------------------------------------------------------
TAILDESC_LSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_lsb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
taildesc_lsb_i <= axi2ip_wrdata(TAILDESC_LOWER_MSB_BIT
downto TAILDESC_LOWER_LSB_BIT);
-- & ZERO_VALUE(TAILDESC_RESERVED_BIT5
-- downto TAILDESC_RESERVED_BIT0);
end if;
end if;
end process TAILDESC_LSB_REGISTER;
---------------------------------------------------------------------------
-- Current Descriptor MSB Register
---------------------------------------------------------------------------
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_SG_ADDR_EQL64 :if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CURDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
curdesc_msb_i <= (others => '0');
elsif(error_pointer_set = '0')then
-- Scatter Gather Fetch Error
if(sg_ftch_error = '1' or sg_updt_error = '1')then
curdesc_msb_i <= ftch_error_addr(C_M_AXI_SG_ADDR_WIDTH - 1 downto C_S_AXI_LITE_DATA_WIDTH);
-- Scatter Gather Update Error
-- elsif(sg_updt_error = '1')then
-- curdesc_msb_i <= updt_error_addr((C_M_AXI_SG_ADDR_WIDTH
-- - C_S_AXI_LITE_DATA_WIDTH)-1
-- downto 0);
-- Commanded to update descriptor value - used for indicating
-- current descriptor begin processed by dma controller
elsif(update_curdesc = '1' and dmacr_i(DMACR_RS_BIT) = '1')then
curdesc_msb_i <= new_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto C_S_AXI_LITE_DATA_WIDTH);
-- CPU update of current descriptor pointer. CPU
-- only allowed to update when engine is halted.
elsif(axi2ip_wrce(CURDESC_MSB_INDEX) = '1' and dmasr_i(DMASR_HALTED_BIT) = '1')then
curdesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end if;
end process CURDESC_MSB_REGISTER;
---------------------------------------------------------------------------
-- Tail Descriptor MSB Register
---------------------------------------------------------------------------
TAILDESC_MSB_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
taildesc_msb_i <= (others => '0');
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
taildesc_msb_i <= axi2ip_wrdata;
end if;
end if;
end process TAILDESC_MSB_REGISTER;
end generate GEN_SG_ADDR_EQL64;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_SG_ADDR_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
curdesc_msb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
end generate GEN_SG_ADDR_EQL32;
-- Scatter Gather Interface configured for 32-Bit SG Addresses
GEN_TAILUPDATE_EQL32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_LSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL32;
-- Scatter Gather Interface configured for 64-Bit SG Addresses
GEN_TAILUPDATE_EQL64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
TAILPNTR_UPDT_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dmacr_i(DMACR_RS_BIT)='0')then
tailpntr_updated_d1 <= '0';
elsif(axi2ip_wrce(TAILDESC_MSB_INDEX) = '1')then
tailpntr_updated_d1 <= '1';
else
tailpntr_updated_d1 <= '0';
end if;
end if;
end process TAILPNTR_UPDT_PROCESS;
TAILPNTR_UPDT_PROCESS_DEL : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
tailpntr_updated_d2 <= '0';
else
tailpntr_updated_d2 <= tailpntr_updated_d1;
end if;
end if;
end process TAILPNTR_UPDT_PROCESS_DEL;
tailpntr_updated <= tailpntr_updated_d1 and (not tailpntr_updated_d2);
end generate GEN_TAILUPDATE_EQL64;
end generate GEN_DESC_REG_FOR_SG;
-- Generate Buffer Address and Length Register for Simple DMA Mode
GEN_REG_FOR_SMPL : if C_INCLUDE_SG = 0 generate
begin
-- Signals not used for simple dma mode, only for sg mode
curdesc_lsb_i <= (others => '0');
curdesc_msb_i <= (others => '0');
taildesc_lsb_i <= (others => '0');
taildesc_msb_i <= (others => '0');
tailpntr_updated <= '0';
error_pointer_set <= '0';
-- Buffer Address register. Used for Source Address (SA) if MM2S
-- and used for Destination Address (DA) if S2MM
BUFFER_ADDR_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_INDEX) = '1')then
buffer_address_i <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER;
GEN_BUFF_ADDR_EQL64 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
BUFFER_ADDR_REGISTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_address_i_64 <= (others => '0');
elsif(axi2ip_wrce(BUFF_ADDRESS_MSB_INDEX) = '1')then
buffer_address_i_64 <= axi2ip_wrdata;
end if;
end if;
end process BUFFER_ADDR_REGISTER1;
end generate GEN_BUFF_ADDR_EQL64;
-- Buffer Length register. Used for number of bytes to transfer if MM2S
-- and used for size of receive buffer is S2MM
BUFFER_LNGTH_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_i <= (others => '0');
-- Update with actual bytes received (Only for S2MM channel)
-- elsif(bytes_received_wren = '1')then
-- buffer_length_i <= bytes_received;
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1')then
buffer_length_i <= axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process BUFFER_LNGTH_REGISTER;
-- Buffer Length Write Enable control. Assertion of wren will
-- begin a transfer if channel is Idle.
BUFFER_LNGTH_WRITE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
buffer_length_wren <= '0';
-- Non-zero length value written
elsif(axi2ip_wrce(BUFF_LENGTH_INDEX) = '1'
and axi2ip_wrdata(C_SG_LENGTH_WIDTH-1 downto 0) /= ZERO_VALUE(C_SG_LENGTH_WIDTH-1 downto 0))then
buffer_length_wren <= '1';
else
buffer_length_wren <= '0';
end if;
end if;
end process BUFFER_LNGTH_WRITE;
end generate GEN_REG_FOR_SMPL;
end implementation;
| mit | f16236b878647eff56f7fa5447696f4d | 0.433853 | 4.421976 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/blk_mem_gen_v8_1/blk_mem_axi_regs_fwd.vhd | 27 | 9,545 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
| bsd-2-clause | 95576adf39d3b5286c58ac00e3c322f8 | 0.924777 | 1.915128 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/idiv53.vhd | 1 | 13,884 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity idiv53 is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_divident : in std_logic_vector(52 downto 0);
i_divisor : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(104 downto 0);
o_lshift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic;
o_zero_resid : out std_logic
);
end;
architecture arch_idiv53 of idiv53 is
constant zero53 : std_logic_vector(52 downto 0) := (others => '0');
component divstage53 is
port (
i_mux_ena : in std_logic; -- find first non-zero bit
i_muxind : in std_logic_vector(55 downto 0); -- bits indexes 8x7 bits bus
i_divident : in std_logic_vector(60 downto 0); -- integer value
i_divisor : in std_logic_vector(52 downto 0); -- integer value
o_dif : out std_logic_vector(52 downto 0); -- residual value
o_bits : out std_logic_vector(7 downto 0); -- resulting bits
o_muxind : out std_logic_vector(6 downto 0); -- first found non-zero bit
o_muxind_rdy : out std_logic -- seeking was successfull
);
end component;
type RegistersType is record
delay : std_logic_vector(14 downto 0);
lshift : std_logic_vector(6 downto 0);
lshift_rdy : std_logic;
divisor : std_logic_vector(52 downto 0);
divident : std_logic_vector(60 downto 0);
bits : std_logic_vector(104 downto 0);
overflow : std_logic;
zero_resid : std_logic;
end record;
constant R_RESET : RegistersType := (
(others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'),
'0', '0');
signal r, rin : RegistersType;
signal w_mux_ena_i : std_logic;
signal wb_muxind_i : std_logic_vector(55 downto 0);
signal wb_divident_i : std_logic_vector(60 downto 0);
signal wb_divisor_i : std_logic_vector(52 downto 0);
signal wb_dif_o : std_logic_vector(52 downto 0);
signal wb_bits_o : std_logic_vector(7 downto 0);
signal wb_muxind_o : std_logic_vector(6 downto 0);
signal w_muxind_rdy_o : std_logic;
begin
divstage0 : divstage53 port map (
i_mux_ena => w_mux_ena_i,
i_muxind => wb_muxind_i,
i_divident => wb_divident_i,
i_divisor => wb_divisor_i,
o_dif => wb_dif_o,
o_bits => wb_bits_o,
o_muxind => wb_muxind_o,
o_muxind_rdy => w_muxind_rdy_o
);
-- registers:
comb : process(i_nrst, i_ena, i_divident, i_divisor, r,
wb_dif_o, wb_bits_o, wb_muxind_o, w_muxind_rdy_o)
variable v : RegistersType;
variable vb_muxind : std_logic_vector(55 downto 0);
variable vb_bits : std_logic_vector(104 downto 0);
variable v_mux_ena_i : std_logic;
begin
v := r;
vb_bits := r.bits;
v_mux_ena_i := '0';
v.delay := r.delay(13 downto 0) & i_ena;
vb_muxind := (others => '0');
if i_ena = '1' then
v.divident := X"00" & i_divident;
v.divisor := i_divisor;
v.lshift_rdy := '0';
v.overflow := '0';
v.zero_resid := '0';
elsif r.delay(0) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_bits(104) := not wb_dif_o(52);
elsif r.delay(1) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(1, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(2, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(3, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(4, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(5, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(6, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(7, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(8, 7);
vb_bits(103 downto 96) := wb_bits_o;
elsif r.delay(2) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(9, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(10, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(11, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(12, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(13, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(14, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(15, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(16, 7);
vb_bits(95 downto 88) := wb_bits_o;
elsif r.delay(3) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(17, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(18, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(19, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(20, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(21, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(22, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(23, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(24, 7);
vb_bits(87 downto 80) := wb_bits_o;
elsif r.delay(4) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(25, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(26, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(27, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(28, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(29, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(30, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(31, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(32, 7);
vb_bits(79 downto 72) := wb_bits_o;
elsif r.delay(5) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(33, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(34, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(35, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(36, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(37, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(38, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(39, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(40, 7);
vb_bits(71 downto 64) := wb_bits_o;
elsif r.delay(6) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(41, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(42, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(43, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(44, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(45, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(46, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(47, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(48, 7);
vb_bits(63 downto 56) := wb_bits_o;
elsif r.delay(7) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(49, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(50, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(51, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(52, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(53, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(54, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(55, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(56, 7);
vb_bits(55 downto 48) := wb_bits_o;
elsif r.delay(8) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(57, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(58, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(59, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(60, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(61, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(62, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(63, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(64, 7);
vb_bits(47 downto 40) := wb_bits_o;
elsif r.delay(9) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(65, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(66, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(67, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(68, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(69, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(70, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(71, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(72, 7);
vb_bits(39 downto 32) := wb_bits_o;
elsif r.delay(10) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(73, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(74, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(75, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(76, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(77, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(78, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(79, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(80, 7);
vb_bits(31 downto 24) := wb_bits_o;
elsif r.delay(11) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(81, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(82, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(83, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(84, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(85, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(86, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(87, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(88, 7);
vb_bits(23 downto 16) := wb_bits_o;
elsif r.delay(12) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(89, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(90, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(91, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(92, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(93, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(94, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(95, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(96, 7);
vb_bits(15 downto 8) := wb_bits_o;
elsif r.delay(13) = '1' then
v_mux_ena_i := not r.lshift_rdy;
v.divident := wb_dif_o & X"00";
vb_muxind(55 downto 49) := conv_std_logic_vector(97, 7);
vb_muxind(48 downto 42) := conv_std_logic_vector(98, 7);
vb_muxind(41 downto 35) := conv_std_logic_vector(99, 7);
vb_muxind(34 downto 28) := conv_std_logic_vector(100, 7);
vb_muxind(27 downto 21) := conv_std_logic_vector(101, 7);
vb_muxind(20 downto 14) := conv_std_logic_vector(102, 7);
vb_muxind(13 downto 7) := conv_std_logic_vector(103, 7);
vb_muxind(6 downto 0) := conv_std_logic_vector(104, 7);
vb_bits(7 downto 0) := wb_bits_o;
if wb_dif_o = zero53 then
v.zero_resid := '1';
end if;
if r.lshift = "1111111" then
v.overflow := '1';
end if;
end if;
if r.lshift_rdy = '0' then
if w_muxind_rdy_o = '1' then
v.lshift_rdy := '1';
v.lshift := wb_muxind_o;
elsif r.delay(13) = '1' then
v.lshift_rdy := '1';
v.lshift := conv_std_logic_vector(104, 7);
end if;
end if;
w_mux_ena_i <= v_mux_ena_i;
wb_divident_i <= r.divident;
wb_divisor_i <= r.divisor;
wb_muxind_i <= vb_muxind;
v.bits := vb_bits;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_result <= r.bits;
o_lshift <= r.lshift;
o_overflow <= r.overflow;
o_zero_resid <= r.zero_resid;
o_rdy <= r.delay(14);
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 03107822aa203820b5b6e839d6289b11 | 0.57822 | 2.854441 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/types_eth.vhd | 1 | 35,905 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
package types_eth is
--gigabit sync types
type data_sync_type is array (0 to 3) of std_logic_vector(31 downto 0);
type ctrl_sync_type is array (0 to 3) of std_logic_vector(1 downto 0);
constant HTRANS_IDLE: std_logic_vector(1 downto 0) := "00";
constant HTRANS_NONSEQ: std_logic_vector(1 downto 0) := "10";
constant HTRANS_SEQ: std_logic_vector(1 downto 0) := "11";
constant HBURST_INCR: std_logic_vector(2 downto 0) := "001";
constant HSIZE_WORD: std_logic_vector(2 downto 0) := "010";
constant HRESP_OKAY: std_logic_vector(1 downto 0) := "00";
constant HRESP_ERROR: std_logic_vector(1 downto 0) := "01";
constant HRESP_RETRY: std_logic_vector(1 downto 0) := "10";
constant HRESP_SPLIT: std_logic_vector(1 downto 0) := "11";
--receiver constants
constant maxsizerx : std_logic_vector(15 downto 0) :=
conv_std_logic_vector(1500, 16);
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
type ahb_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(4 downto 0);
write : std_ulogic;
data : std_logic_vector(31 downto 0);
waddress : std_logic_vector(4 downto 0);
end record;
type ahb_fifo_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type nchar_fifo_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(5 downto 0);
write : std_ulogic;
data : std_logic_vector(8 downto 0);
waddress : std_logic_vector(5 downto 0);
end record;
type nchar_fifo_out_type is record
data : std_logic_vector(8 downto 0);
end record;
type rmapbuf_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(7 downto 0);
write : std_ulogic;
data : std_logic_vector(7 downto 0);
waddress : std_logic_vector(7 downto 0);
end record;
type rmapbuf_out_type is record
data : std_logic_vector(7 downto 0);
end record;
type ahbc_mst_in_type is record
hgrant : std_ulogic; -- bus grant
hready : std_ulogic; -- transfer done
hresp : std_logic_vector(1 downto 0); -- response type
hrdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type ahbc_mst_out_type is record
hbusreq : std_ulogic; -- bus request
hlock : std_ulogic; -- lock request
htrans : std_logic_vector(1 downto 0); -- transfer type
haddr : std_logic_vector(31 downto 0); -- address bus (byte)
hwrite : std_ulogic; -- read/write
hsize : std_logic_vector(2 downto 0); -- transfer size
hburst : std_logic_vector(2 downto 0); -- burst type
hprot : std_logic_vector(3 downto 0); -- protection control
hwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_in_type is record
psel : std_ulogic; -- slave select
penable : std_ulogic; -- strobe
paddr : std_logic_vector(31 downto 0); -- address bus (byte)
pwrite : std_ulogic; -- write
pwdata : std_logic_vector(31 downto 0); -- write data bus
end record;
type apbc_slv_out_type is record
prdata : std_logic_vector(31 downto 0); -- read data bus
end record;
type eth_tx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
type eth_tx_ahb_out_type is record
grant : std_ulogic;
data : std_logic_vector(31 downto 0);
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
end record;
type eth_rx_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
burst_bytes : std_logic_vector(10 downto 0);
end record;
constant eth_rx_in_none : eth_rx_ahb_in_type := (
'0', '0', (others => '0'), (others => '0'), (others => '0'));
type eth_rx_ahb_out_type is record
grant : std_ulogic;
ready : std_ulogic;
error : std_ulogic;
retry : std_ulogic;
data : std_logic_vector(31 downto 0);
end record;
type eth_rx_gbit_ahb_in_type is record
req : std_ulogic;
write : std_ulogic;
addr : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
size : std_logic_vector(1 downto 0);
end record;
type gbit_host_tx_type is record
full_duplex : std_ulogic;
start : std_ulogic;
read_ack : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
rx_col : std_ulogic;
rx_crs : std_ulogic;
end record;
type gbit_tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type gbit_rx_host_type is record
sync_start : std_ulogic;
done : std_ulogic;
write : std_logic_vector(3 downto 0);
dataout : data_sync_type;
byte_count : std_logic_vector(10 downto 0);
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
end record;
type gbit_host_rx_type is record
full_duplex : std_ulogic;
gbit : std_ulogic;
doneack : std_ulogic;
writeack : std_logic_vector(3 downto 0);
speed : std_ulogic;
writeok : std_logic_vector(3 downto 0);
rxenable : std_ulogic;
rxd : std_logic_vector(7 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_crs : std_ulogic;
rx_en : std_ulogic;
end record;
type gbit_gtx_host_type is record
txd : std_logic_vector(7 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
read : std_logic_vector(3 downto 0);
status : std_logic_vector(2 downto 0);
end record;
type gbit_host_gtx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
burstmode : std_ulogic;
txen : std_ulogic;
start_sync : std_ulogic;
readack : std_logic_vector(3 downto 0);
valid : std_logic_vector(3 downto 0);
data : data_sync_type;
len : std_logic_vector(10 downto 0);
end record;
type host_tx_type is record
rx_col : std_ulogic;
rx_crs : std_ulogic;
full_duplex : std_ulogic;
start : std_ulogic;
readack : std_ulogic;
speed : std_ulogic;
data : std_logic_vector(31 downto 0);
datavalid : std_ulogic;
valid : std_ulogic;
len : std_logic_vector(10 downto 0);
end record;
type tx_host_type is record
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
done : std_ulogic;
read : std_ulogic;
restart : std_ulogic;
status : std_logic_vector(1 downto 0);
end record;
type rx_host_type is record
dataout : std_logic_vector(31 downto 0);
start : std_ulogic;
done : std_ulogic;
write : std_ulogic;
status : std_logic_vector(3 downto 0);
gotframe : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
lentype : std_logic_vector(15 downto 0);
mcasthash : std_logic_vector(5 downto 0);
end record;
type host_rx_type is record
writeack : std_ulogic;
doneack : std_ulogic;
speed : std_ulogic;
writeok : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_crs : std_ulogic;
rx_er : std_ulogic;
enable : std_ulogic;
rx_en : std_ulogic;
end record;
component greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end component;
component greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
end component;
component eth_rstgen is
generic(acthigh : integer := 0);
port (
rstin : in std_ulogic;
clk : in std_ulogic;
clklock : in std_ulogic;
rstout : out std_ulogic;
rstoutraw : out std_ulogic
);
end component;
component greth_gbit_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in gbit_host_tx_type;
txo : out gbit_tx_host_type);
end component;
component greth_gbit_gtx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
iotest : integer := 0);
port(
rst : in std_ulogic;
clk : in std_ulogic;
gtxi : in gbit_host_gtx_type;
gtxo : out gbit_gtx_host_type;
iotmact : in std_ulogic;
iotdata : in std_logic_vector(9 downto 0)
);
end component;
component greth_gbit_rx is
generic(
multicast : integer range 0 to 1 := 0;
nsync : integer range 1 to 2 := 2;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in gbit_host_rx_type;
rxo : out gbit_rx_host_type;
iotdata : out std_logic_vector(9 downto 0));
end component;
component eth_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
component eth_ahb_mst_gbit is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_gbit_ahb_in_type;
rmsto : out eth_rx_ahb_out_type);
end component;
component eth_edcl_ahb_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahbc_mst_in_type;
ahbmo : out ahbc_mst_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type
);
end component;
component eth_axi_mst is
port(
rst : in std_ulogic;
clk : in std_ulogic;
aximi : in axi4_master_in_type;
aximo : out axi4_master_out_type;
tmsti : in eth_tx_ahb_in_type;
tmsto : out eth_tx_ahb_out_type;
rmsti : in eth_rx_ahb_in_type;
rmsto : out eth_rx_ahb_out_type
);
end component;
function mirror(din : in std_logic_vector) return std_logic_vector;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector;
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer;
function setburstlength(fifosize : in integer) return integer;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector;
-- ETH registers
type eth_mdio_command_type is record
valid : std_ulogic;
regadr : std_logic_vector(4 downto 0);
write : std_ulogic;
read : std_ulogic;
data : std_logic_vector(15 downto 0);
end record;
constant eth_mdio_command_none : eth_mdio_command_type := (
'0', (others => '0'), '0', '0', (others => '0')
);
type eth_mdio_status_type is record
cmd : eth_mdio_command_type;
busy : std_ulogic;
linkfail : std_ulogic;
end record;
type eth_mac_status_type is record
txdsel : std_logic_vector(9 downto 3);
rxdsel : std_logic_vector(9 downto 3);
txen : std_ulogic;
rxen : std_ulogic;
tx_int : std_ulogic;
rx_int : std_ulogic;
tx_err : std_ulogic;
rx_err : std_ulogic;
edcltx_idle : std_ulogic;
edclrx_idle : std_ulogic;
txahberr : std_ulogic;
rxahberr : std_ulogic;
toosmall : std_ulogic;
invaddr : std_ulogic;
phystat : std_ulogic;
full_duplex : std_ulogic;
speed : std_ulogic;
reset : std_ulogic;
mdio : eth_mdio_status_type;
end record;
--! Latched values set via external Bus Interface
type eth_control_type is record
tx_irqen : std_ulogic;
rx_irqen : std_ulogic;
prom : std_ulogic;
pstatirqen : std_ulogic;
mcasten : std_ulogic;
--! Enable access to the internal FIFOs via system BUS (disabled default)
ramdebugen : std_ulogic;
--! Disable EDCL access
edcldis : std_ulogic;
disableduplex : std_ulogic;
--! Physical address.
--! Can be changed in a runtime, but become actual only after system reset.
mdio_phyadr : std_logic_vector(4 downto 0);
mac_addr : std_logic_vector(47 downto 0);
--! Tx descriptor
txdesc : std_logic_vector(31 downto 10);
--! Rx descriptor
rxdesc : std_logic_vector(31 downto 10);
--! EDCL IP
edclip : std_logic_vector(31 downto 0);
--! Multicast enabling hash value
hash : std_logic_vector(63 downto 0);
emacaddr : std_logic_vector(47 downto 0);
end record;
--! @name DBG access unique IDs to the internal FIFOs blocks.
--! @{
constant DBG_ACCESS_NONE : std_logic_vector(1 downto 0) := "00";
constant DBG_ACCESS_TX_BUFFER : std_logic_vector(1 downto 0) := "01";
constant DBG_ACCESS_RX_BUFFER : std_logic_vector(1 downto 0) := "10";
constant DBG_ACCESS_EDCL_BUFFER : std_logic_vector(1 downto 0) := "11";
--! @}
--! Bus interface read/write actions transforming into these commands.
type eth_command_type is record
--! Tx/Rx can be enabled externally but they're cleared inside of MAC
--! in a case of disabled Descriptor or in a case of BUS error.
set_txena : std_ulogic;
clr_txena : std_ulogic;
set_rxena : std_ulogic;
clr_rxena : std_ulogic;
--! Set new descriptor index in the array of descriptors table
set_txdsel : std_ulogic;
set_rxdsel : std_ulogic;
txdsel : std_logic_vector(9 downto 3);
rxdsel : std_logic_vector(9 downto 3);
--! The following values can be changed during initialization stage.
set_full_duplex : std_ulogic;
clr_full_duplex : std_ulogic;
set_speed : std_ulogic;
clr_speed : std_ulogic;
set_reset : std_ulogic;
clr_reset : std_ulogic;
--! Clear status bits commands:
clr_status_tx_int : std_ulogic;
clr_status_rx_int : std_ulogic;
clr_status_tx_err : std_ulogic;
clr_status_rx_err : std_ulogic;
clr_status_txahberr : std_ulogic;
clr_status_rxahberr : std_ulogic;
clr_status_toosmall : std_ulogic;
clr_status_invaddr : std_ulogic;
clr_status_phystat : std_ulogic;
--! mdi interface command
mdio_cmd : eth_mdio_command_type;
--! Request ID values:
dbg_access_id : std_logic_vector(1 downto 0);
dbg_wr_ena : std_logic;
dbg_rd_ena : std_logic;
dbg_addr : std_logic_vector(13 downto 0);
dbg_wdata : std_logic_vector(31 downto 0);
end record;
constant eth_command_none : eth_command_type := (
'0', '0', '0', '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0',
'0', '0', '0', '0', '0', '0', '0', '0', '0', eth_mdio_command_none,
DBG_ACCESS_NONE, '0', '0', (others => '0'), (others => '0')
);
type eth_in_type is record
gtx_clk : std_ulogic;
rmii_clk : std_ulogic;
tx_clk : std_ulogic;
tx_clk_90 : std_ulogic;
rx_clk : std_ulogic;
tx_dv : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rx_dv : std_ulogic;
rx_er : std_ulogic;
rx_col : std_ulogic;
rx_en : std_ulogic;
rx_crs : std_ulogic;
mdio_i : std_ulogic;
mdint : std_ulogic;
phyrstaddr : std_logic_vector(4 downto 0);
edcladdr : std_logic_vector(3 downto 0);
edclsepahb : std_ulogic;
edcldisable : std_ulogic;
end record;
constant eth_in_none : eth_in_type := (
'0', '0', '0', '0', '0', '0', (others => '0'), '0', '0', '0', '0', '0',
'0', '0', (others => '0'), (others => '0'), '0', '0');
type eth_out_type is record
reset : std_ulogic;
txd : std_logic_vector(3 downto 0);
tx_en : std_ulogic;
tx_er : std_ulogic;
tx_clk : std_ulogic;
mdc : std_ulogic;
mdio_o : std_ulogic;
mdio_oe : std_ulogic;
gbit : std_ulogic;
speed : std_ulogic;
end record;
constant eth_out_none : eth_out_type := (
'0', (others => '0'), '0', '0', '0', '0', '0', '1', '0', '0');
component grethc64 is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in eth_control_type;
cmdi : in eth_command_type;
statuso : out eth_mac_status_type;
--! Debug value read from internal buffers suing external bus interface
rdbgdatao : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
tmsto : out eth_tx_ahb_in_type;
tmsti : in eth_tx_ahb_out_type;
tmsto2 : out eth_tx_ahb_in_type;
tmsti2 : in eth_tx_ahb_out_type;
rmsto : out eth_rx_ahb_in_type;
rmsti : in eth_rx_ahb_out_type
);
end component;
component grethaxi is
generic(
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#FFFFF#;
xirq : integer := 0;
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
msti : in axi4_master_in_type;
msto : out axi4_master_out_type;
mstcfg : out axi4_master_config_type;
msto2 : out axi4_master_out_type;
mstcfg2 : out axi4_master_config_type;
slvi : in axi4_slave_in_type;
slvo : out axi4_slave_out_type;
slvcfg : out axi4_slave_config_type;
ethi : in eth_in_type;
etho : out eth_out_type;
irq : out std_logic
);
end component;
end package;
package body types_eth is
function mirror(din : in std_logic_vector)
return std_logic_vector is
variable do : std_logic_vector(din'range);
begin
for i in 0 to din'length-1 loop
do(din'high-i) := din(i+din'low);
end loop;
return do;
end function;
function crc32_4(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--16-bit one's complement adder
function crc16(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(15 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(16 downto 0);
variable vd2 : std_logic_vector(16 downto 0);
variable sum : std_logic_vector(16 downto 0);
begin
vd1 := '0' & d1; vd2 := '0' & d2;
sum := vd1 + vd2;
sum(15 downto 0) := sum(15 downto 0) + sum(16);
return sum(15 downto 0);
end function;
--16-bit one's complement adder for ip/tcp checksum detection
function crc16_2(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(25 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(25 downto 0);
variable vd2 : std_logic_vector(25 downto 0);
variable sum : std_logic_vector(25 downto 0);
begin
vd1 := "0000000000" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
function validlen(len : in std_logic_vector(10 downto 0);
bcnt : in std_logic_vector(10 downto 0);
usesz : in std_ulogic)
return std_ulogic is
variable valid : std_ulogic;
begin
valid := '1';
if usesz = '1' then
if len > minpload then
if bcnt /= len then
valid := '0';
end if;
else
if bcnt /= minpload then
valid := '0';
end if;
end if;
end if;
return valid;
end function;
function setburstlength(fifosize : in integer) return integer is
begin
if fifosize <= 64 then
return fifosize/2;
else
return 32;
end if;
end function;
function getfifosize(edcl, fifosize, ebufsize : in integer) return integer is
begin
if (edcl /= 0) and (ebufsize > fifosize) then
return ebufsize;
else
return fifosize;
end if;
end function;
function calccrc(d : in std_logic_vector(3 downto 0);
crc : in std_logic_vector(31 downto 0))
return std_logic_vector is
variable ncrc : std_logic_vector(31 downto 0);
variable tc : std_logic_vector(3 downto 0);
begin
tc(0) := d(0) xor crc(31); tc(1) := d(1) xor crc(30);
tc(2) := d(2) xor crc(29); tc(3) := d(3) xor crc(28);
ncrc(31) := crc(27);
ncrc(30) := crc(26);
ncrc(29) := tc(0) xor crc(25);
ncrc(28) := tc(1) xor crc(24);
ncrc(27) := tc(2) xor crc(23);
ncrc(26) := tc(0) xor tc(3) xor crc(22);
ncrc(25) := tc(0) xor tc(1) xor crc(21);
ncrc(24) := tc(1) xor tc(2) xor crc(20);
ncrc(23) := tc(2) xor tc(3) xor crc(19);
ncrc(22) := tc(3) xor crc(18);
ncrc(21) := crc(17);
ncrc(20) := crc(16);
ncrc(19) := tc(0) xor crc(15);
ncrc(18) := tc(1) xor crc(14);
ncrc(17) := tc(2) xor crc(13);
ncrc(16) := tc(3) xor crc(12);
ncrc(15) := tc(0) xor crc(11);
ncrc(14) := tc(0) xor tc(1) xor crc(10);
ncrc(13) := tc(0) xor tc(1) xor tc(2) xor crc(9);
ncrc(12) := tc(1) xor tc(2) xor tc(3) xor crc(8);
ncrc(11) := tc(0) xor tc(2) xor tc(3) xor crc(7);
ncrc(10) := tc(0) xor tc(1) xor tc(3) xor crc(6);
ncrc(9) := tc(1) xor tc(2) xor crc(5);
ncrc(8) := tc(0) xor tc(2) xor tc(3) xor crc(4);
ncrc(7) := tc(0) xor tc(1) xor tc(3) xor crc(3);
ncrc(6) := tc(1) xor tc(2) xor crc(2);
ncrc(5) := tc(0) xor tc(2) xor tc(3) xor crc(1);
ncrc(4) := tc(0) xor tc(1) xor tc(3) xor crc(0);
ncrc(3) := tc(0) xor tc(1) xor tc(2);
ncrc(2) := tc(1) xor tc(2) xor tc(3);
ncrc(1) := tc(2) xor tc(3);
ncrc(0) := tc(3);
return ncrc;
end function;
--function calccrc_8(data : in std_logic_vector( 7 downto 0);
-- crc : in std_logic_vector(31 downto 0))
-- return std_logic_vector is
-- variable ncrc : std_logic_vector(31 downto 0);
-- variable d : std_logic_vector(7 downto 0);
--begin
-- d(7) := data(0); d(6) := data(1); d(5) := data(2); d(4) := data(3);
-- d(3) := data(4); d(2) := data(5); d(1) := data(6); d(0) := data(7);
-- ncrc(0) := d(6) xor d(0) xor crc(24) xor crc(30);
-- ncrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(30) xor crc(31);
-- ncrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(27) xor crc(31);
-- ncrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor crc(24) xor crc(26) xor crc(27) xor crc(29) xor crc(31);
-- ncrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor crc(0) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor crc(1) xor crc(25) xor crc(26) xor crc(28) xor crc(29);
-- ncrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor crc(2) xor crc(24) xor crc(26) xor crc(27) xor crc(29);
-- ncrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor crc(3) xor crc(24) xor crc(25) xor crc(27) xor crc(28);
-- ncrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor crc(4) xor crc(24) xor crc(25) xor crc(26) xor crc(28) xor crc(29) xor crc(30);
-- ncrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor crc(5) xor crc(25) xor crc(26) xor crc(27) xor crc(29) xor crc(30) xor crc(31);
-- ncrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor crc(6) xor crc(26) xor crc(27) xor crc(28) xor crc(30) xor crc(31);
-- ncrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor crc(7) xor crc(27) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(16) := d(5) xor d(4) xor d(0) xor crc(8) xor crc(24) xor crc(28) xor crc(29);
-- ncrc(17) := d(6) xor d(5) xor d(1) xor crc(9) xor crc(25) xor crc(29) xor crc(30);
-- ncrc(18) := d(7) xor d(6) xor d(2) xor crc(10) xor crc(26) xor crc(30) xor crc(31);
-- ncrc(19) := d(7) xor d(3) xor crc(11) xor crc(27) xor crc(31);
-- ncrc(20) := d(4) xor crc(12) xor crc(28);
-- ncrc(21) := d(5) xor crc(13) xor crc(29);
-- ncrc(22) := d(0) xor crc(14) xor crc(24);
-- ncrc(23) := d(6) xor d(1) xor d(0) xor crc(15) xor crc(24) xor crc(25) xor crc(30);
-- ncrc(24) := d(7) xor d(2) xor d(1) xor crc(16) xor crc(25) xor crc(26) xor crc(31);
-- ncrc(25) := d(3) xor d(2) xor crc(17) xor crc(26) xor crc(27);
-- ncrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor crc(18) xor crc(24) xor crc(27) xor crc(28) xor crc(30);
-- ncrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor crc(19) xor crc(25) xor crc(28) xor crc(29) xor crc(31);
-- ncrc(28) := d(6) xor d(5) xor d(2) xor crc(20) xor crc(26) xor crc(29) xor crc(30);
-- ncrc(29) := d(7) xor d(6) xor d(3) xor crc(21) xor crc(27) xor crc(30) xor crc(31);
-- ncrc(30) := d(7) xor d(4) xor crc(22) xor crc(28) xor crc(31);
-- ncrc(31) := d(5) xor crc(23) xor crc(29);
-- return ncrc;
--end function;
--16-bit one's complement adder
function crcadder(d1 : in std_logic_vector(15 downto 0);
d2 : in std_logic_vector(17 downto 0))
return std_logic_vector is
variable vd1 : std_logic_vector(17 downto 0);
variable vd2 : std_logic_vector(17 downto 0);
variable sum : std_logic_vector(17 downto 0);
begin
vd1 := "00" & d1; vd2 := d2;
sum := vd1 + vd2;
return sum;
end function;
end package body;
| apache-2.0 | 62fa698e9989e64e66564711cb51a572 | 0.544799 | 3.173782 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_mngr.vhd | 1 | 19,061 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_mngr.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_updt_cmd_tvalid : out std_logic ; --
s_axis_updt_cmd_tready : in std_logic ; --
s_axis_updt_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_updt_sts_tvalid : in std_logic ; --
m_axis_updt_sts_tready : out std_logic ; --
m_axis_updt_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_updt_sts_tkeep : in std_logic_vector(0 downto 0) ; --
s2mm_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal updt_cmnd_wr : std_logic := '0';
signal updt_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH
+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal updt_done : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal updt_interr : std_logic := '0';
signal updt_slverr : std_logic := '0';
signal updt_decerr : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_UPDT_SG : entity axi_sg_v4_1_3.axi_sg_updt_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ftch_error => ftch_error ,
-- Channel 1 Control and Status
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set ,
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set ,
ch1_dma_slverr_set => ch1_dma_slverr_set ,
ch1_dma_decerr_set => ch1_dma_decerr_set ,
ch1_updt_interr_set => ch1_updt_interr_set ,
ch1_updt_slverr_set => ch1_updt_slverr_set ,
ch1_updt_decerr_set => ch1_updt_decerr_set ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set ,
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set ,
ch2_dma_slverr_set => ch2_dma_slverr_set ,
ch2_dma_decerr_set => ch2_dma_decerr_set ,
ch2_updt_interr_set => ch2_updt_interr_set ,
ch2_updt_slverr_set => ch2_updt_slverr_set ,
ch2_updt_decerr_set => ch2_updt_decerr_set ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- DataMover Command
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- DataMover Status
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr ,
updt_error_addr => updt_error_addr
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_UPDT_CMDSTS_IF : entity axi_sg_v4_1_3.axi_sg_updt_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
updt_cmnd_wr => updt_cmnd_wr ,
updt_cmnd_data => updt_cmnd_data ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
-- Scatter Gather Fetch Status
s2mm_err => s2mm_err ,
updt_done => updt_done ,
updt_error => updt_error_i ,
updt_interr => updt_interr ,
updt_slverr => updt_slverr ,
updt_decerr => updt_decerr
);
end implementation;
| mit | b35e616d9b5e578977ff402c261c42ee | 0.362468 | 5.095162 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_cntrl_strm.vhd | 1 | 25,041 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_fifo_v1_0_5;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0_5.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1_3.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1_3.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1_3.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
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`protect end_protected
| bsd-2-clause | c628090b9aeaaebc5761c31259a601c4 | 0.947291 | 1.836892 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/axi4_gpio.vhd | 1 | 4,867 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
entity axi4_gpio is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
width : integer := 12
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i : in axi4_slave_in_type;
o : out axi4_slave_out_type;
i_gpio : in std_logic_vector(width-1 downto 0);
o_gpio : out std_logic_vector(width-1 downto 0);
o_gpio_dir : out std_logic_vector(width-1 downto 0)
);
end;
architecture arch_axi4_gpio of axi4_gpio is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(xirq, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_GPIO
);
type registers is record
direction : std_logic_vector(31 downto 0);
iuser : std_logic_vector(31 downto 0);
ouser : std_logic_vector(31 downto 0);
reg32_3 : std_logic_vector(31 downto 0);
raddr : global_addr_array_type;
end record;
constant R_RESET : registers := (
(others => '1'), (others => '0'),
(others => '0'), (others => '0'),
((others => '0'), (others => '0'))
);
signal r, rin : registers;
signal wb_dev_rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i,
o_xslvo => o,
i_ready => '1',
i_rdata => wb_dev_rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_gpio, r, w_bus_re, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable vrdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
begin
v := r;
v.raddr := wb_bus_raddr;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := (others => '0');
case conv_integer(r.raddr(n)(11 downto 2)) is
when 0 => tmp := r.direction;
when 1 => tmp := r.iuser;
when 2 => tmp := r.ouser;
when 3 => tmp := r.reg32_3;
when others =>
end case;
vrdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if w_bus_we = '1' then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := wb_bus_wdata(32*(n+1)-1 downto 32*n);
if conv_integer(wb_bus_wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
case conv_integer(wb_bus_waddr(n)(11 downto 2)) is
when 0 => v.direction := tmp;
--when 1 => v.iuser := tmp; -- [RO]
when 2 => v.ouser := tmp;
when 3 => v.reg32_3 := tmp;
when others =>
end case;
end if;
end loop;
end if;
v.iuser(width-1 downto 0) := i_gpio;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
wb_dev_rdata <= vrdata;
end process;
cfg <= xconfig;
o_gpio <= r.ouser(width-1 downto 0);
o_gpio_dir <= r.direction(width-1 downto 0);
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | feca7f85d0d5fd06fc7eff89b61af5c5 | 0.595028 | 3.178968 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/pll/clkp90_tech.vhd | 1 | 2,149 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Virtual clock phase offset generator (90 deg)
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity clkp90_tech is
generic (
tech : integer range 0 to NTECH := 0;
--! clock frequency in KHz
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_tech;
architecture rtl of clkp90_tech is
component clkp90_virtex6 is
port (
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic
);
end component;
component clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end component;
begin
xv6 : if tech = virtex6 generate
v1 : clkp90_virtex6 port map (
i_clk => i_clk,
o_clk => o_clk,
o_clkp90 => o_clkp90
);
o_clk2x <= '0';
o_lock <= '0';
end generate;
xl7 : if tech = kintex7 or tech = artix7 or tech = zynq7000 generate
v1 : clkp90_kintex7 generic map (
freq => freq
) port map (
i_rst => i_rst,
i_clk => i_clk,
o_clk => o_clk,
o_clkp90 => o_clkp90,
o_clk2x => o_clk2x,
o_lock => o_lock
);
end generate;
inf : if tech = inferred generate
o_clk <= i_clk;
o_clkp90 <= i_clk;
o_clk2x <= '0';
o_lock <= '0';
end generate;
m180 : if tech = mikron180 generate
end generate;
end;
| apache-2.0 | 0083b5c720fe3b6524ddbc0a72a84907 | 0.503955 | 3.421975 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/ram_inferred.vhd | 1 | 1,588 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity ram_inferred is generic (
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_addr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture rtl of ram_inferred is
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(dbits-1 downto 0);
signal ram : ram_type;
signal radr : std_logic_vector(abits-1 downto 0);
begin
reg : process (i_clk) begin
if rising_edge(i_clk) then
radr <= i_addr;
if i_wena = '1' then
ram(conv_integer(i_addr)) <= i_wdata;
end if;
end if;
end process;
o_rdata <= ram(conv_integer(radr));
end;
| apache-2.0 | d086c13bc7f94413d73a5f5b347daa09 | 0.678841 | 3.385928 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/sram8_inferred.vhd | 3 | 1,340 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief 8-bits memory block with the generic data size parameter.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity sram8_inferred is
generic (
abits : integer := 12;
byte_idx : integer := 0
);
port (
clk : in std_ulogic;
address : in std_logic_vector(abits-1 downto 0);
rdata : out std_logic_vector(7 downto 0);
we : in std_logic;
wdata : in std_logic_vector(7 downto 0)
);
end;
architecture arch_sram8_inferred of sram8_inferred is
constant SRAM_LENGTH : integer := 2**abits;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(7 downto 0);
signal ram : ram_type;
signal adr : std_logic_vector(abits-1 downto 0);
begin
reg : process (clk, address, wdata) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
adr <= address;
end if;
end process;
rdata <= ram(conv_integer(adr));
end;
| apache-2.0 | fdc48924f9ce082b659d33195124aede | 0.578358 | 3.661202 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/logic_builtin.vhd | 19 | 30,579 | `protect begin_protected
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| bsd-2-clause | 0cd1740958fd1585d283b2c4736184c5 | 0.94578 | 1.834263 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_wrdata_cntl.vhd | 1 | 91,473 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_sg_wrdata_cntl;
architecture implementation of axi_sg_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
-- coverage off
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-- coverage on
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
-- coverage off
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
-- coverage on
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_s2mm_strm_wready_del : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
-- sig_s2mm_strm_wready_del;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
sig_s2mm_strm_wready_del <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
sig_s2mm_strm_wready_del <= sig_s2mm_strm_wready;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= (others => '1') when mmap_reset = '0' else (others => '0'); --sig_strt_strb_reg
-- data2skid_wstrb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1')
-- Else sig_last_strb_reg
-- When (sig_last_dbeat = '1')
-- Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
-- coverage off
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
-- coverage on
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
-- coverage off
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
-- coverage on
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
-- GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
--
-- -- local constants
-- Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
-- Constant NUM_ZEROS_WIDTH : integer := 8;
-- Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
-- Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
-- funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
--
-- Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
--
--
--
-- -- local signals
-- signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
-- signal lsig_ld_byte_cntr : std_logic := '0';
-- signal lsig_incr_byte_cntr : std_logic := '0';
-- signal lsig_clr_byte_cntr : std_logic := '0';
-- signal lsig_end_of_cmd_reg : std_logic := '0';
-- signal lsig_eop_s_h_reg : std_logic := '0';
-- signal lsig_eop_reg : std_logic := '0';
-- signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
--
--
--
--
-- begin
--
--
-- -- Assign the outputs to the Write Status Controller
-- data2wsc_eop <= lsig_eop_reg and
-- not(sig_next_calc_error_reg);
--
-- data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
--
--
--
-- -- WRSTRB logic ------------------------------
--
--
--
-- --sig_strbgen_bytes <= (others => '1'); -- set to the max value
--
--
-- -- set the length to the max number of bytes per databeat
-- sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
--
--
--
--
--
--
-- sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
-- STRBGEN_ADDR_SLICE_WIDTH)) ;
--
--
--
--
-- ------------------------------------------------------------
-- -- Instance: I_STRT_STRB_GEN
-- --
-- -- Description:
-- -- Strobe generator used to generate the starting databeat
-- -- strobe value for soft shutdown case where the S2MM has to
-- -- flush out all of the transfers that have been committed
-- -- to the AXI Write address channel. Starting Strobes must
-- -- match the committed address offest for each transfer.
-- --
-- ------------------------------------------------------------
-- I_STRT_STRB_GEN : entity axi_sg_v4_1_3.axi_sg_strb_gen2
-- generic map (
--
-- C_OP_MODE => 0 , -- 0 = Offset/Length mode
-- C_STRB_WIDTH => BYTES_PER_DBEAT ,
-- C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
-- C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
--
-- )
-- port map (
--
-- start_addr_offset => sig_strbgen_addr ,
-- end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
-- num_valid_bytes => sig_strbgen_bytes ,
-- strb_out => sig_sfhalt_next_strt_strb
--
-- );
--
--
--
--
--
--
--
-- -- Generate the WSTRB to use during soft shutdown
-- sig_halt_strb <= sig_strt_strb_reg
-- When (sig_first_dbeat = '1' or
-- sig_single_dbeat = '1')
-- Else (others => '1');
--
--
--
-- -- Generate the Write Strobes for the MMap Write Data Channel
-- -- for the Indeterminate BTT case. Strobes come from the Stream
-- -- input from the Indeterminate BTT module during normal operation.
-- -- However, during soft shutdown, those strobes become unpredictable
-- -- so generated strobes have to be used.
-- data2skid_wstrb <= sig_halt_strb
-- When (sig_halt_reg = '1')
--
-- Else s2mm_strm_wstrb;
--
--
--
-- -- Generate the Stream Ready for the Stream input side
-- sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
-- (sig_mmap2data_ready and -- MMap is accepting the xfers
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
-- -- MMap Write Data Channel Valid Handshaking
-- sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
-- sig_halt_reg ) and -- force valid if halt requested
-- sig_addr_chan_rdy and -- xfers are commited on the address channel and
-- sig_dqual_rdy and -- there are commands in the command fifo
-- not(sig_calc_error_reg) and -- No internal error
-- not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- -- or when the soft shutdown has completed
--
--
--
-- -- TLAST Error housekeeping for Indeterminate BTT Mode
-- -- There is no Underrun/overrun in Stroe and Forward mode
--
-- sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
-- sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
-- sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
--
--
--
--
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_EOP_REG_FLOP
-- --
-- -- Process Description:
-- -- Register the End of Packet marker.
-- --
-- -------------------------------------------------------------
-- IMP_EOP_REG_FLOP : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1') then
--
-- lsig_end_of_cmd_reg <= '0';
-- lsig_eop_reg <= '0';
--
--
-- Elsif (sig_good_strm_dbeat = '1') Then
--
--
-- lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
-- s2mm_strm_wlast;
--
-- lsig_eop_reg <= s2mm_strm_eop;
--
-- else
--
-- null; -- hold current state
--
-- end if;
-- end if;
-- end process IMP_EOP_REG_FLOP;
--
--
--
--
--
-- ----- Byte Counter Logic -----------------------------------------------
-- -- The Byte counter reflects the actual byte count received on the
-- -- Stream input for each parent command loaded into the S2MM command
-- -- FIFO. Thus it counts input bytes until the command complete qualifier
-- -- is set and the TLAST input from the Stream input.
--
--
-- lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
-- not(sig_good_strm_dbeat); -- immediately after the previous one finished.
--
--
-- lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
-- sig_good_strm_dbeat; -- immediately after the previous one finished.
--
-- lsig_incr_byte_cntr <= sig_good_strm_dbeat;
--
--
-- lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
-- BYTE_CNTR_WIDTH);
--
-- -------------------------------------------------------------
-- -- Synchronous Process with Sync Reset
-- --
-- -- Label: IMP_BYTE_CMTR
-- --
-- -- Process Description:
-- -- Keeps a running byte count per burst packet loaded into the
-- -- xfer FIFO. It is based on the strobes set on the incoming
-- -- Stream dbeat.
-- --
-- -------------------------------------------------------------
-- IMP_BYTE_CMTR : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
-- if (mmap_reset = '1' or
-- lsig_clr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= (others => '0');
--
-- elsif (lsig_ld_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr_incr_value;
--
-- elsif (lsig_incr_byte_cntr = '1') then
--
-- lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
--
-- else
-- null; -- hold current value
-- end if;
-- end if;
-- end process IMP_BYTE_CMTR;
--
--
--
--
--
-- end generate GEN_INDET_BTT;
--
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_sg_v4_1_3.axi_sg_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
| mit | 9be158e40c767ee2f9decd788a96584b | 0.417544 | 4.924787 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/tracer.vhd | 1 | 3,177 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity tracer is generic (
async_reset : boolean;
trace_file : string := ""
);
port (
i_clk : in std_logic; -- CPU clock
i_nrst : in std_logic; -- Reset. Active LOW.
i_dbg_executed_cnt : in std_logic_vector(63 downto 0);
i_e_valid : in std_logic;
i_e_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_e_instr : in std_logic_vector(31 downto 0);
i_e_memop_store : in std_logic;
i_e_memop_load : in std_logic;
i_e_memop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_e_res_data : in std_logic_vector(RISCV_ARCH-1 downto 0);
i_e_res_addr : in std_logic_vector(5 downto 0);
i_m_wena : in std_logic;
i_m_waddr : in std_logic_vector(5 downto 0);
i_m_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0)
);
end;
architecture arch_tracer of tracer is
type regnames_type is array (0 to Reg_Total+RegFpu_Total-1) of string;
constant rname : regnames_type := (
"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
);
type RegistersType is record
load_reg : std_logic;
load_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
end record;
constant R_RESET : RegistersType := ('0', (others => '0'));
signal r, rin : RegistersType;
begin
comb : process(i_nrst, i_dbg_executed_cnt, i_e_valid, i_e_pc, i_e_instr,
i_e_memop_store, i_e_memop_load, i_e_memop_addr, i_e_res_data,
i_e_res_addr, i_m_wena, i_m_waddr, i_m_wdata, r)
variable v : RegistersType;
begin
v := r;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | dcc83528042ce1ca2839a039aa893eb6 | 0.58955 | 2.869919 | false | false | false | false |
szanni/aeshw | aes-core/aes_module_cu.vhd | 1 | 3,918 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:13 07/21/2014
-- Design Name:
-- Module Name: aes_module_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aes_module_cu is
port (clk : in std_logic;
reset : in std_logic;
x_start : in std_logic;
x_mode : in aes_mode;
x_end_enc : in std_logic;
x_end_dec : in std_logic;
x_end_exp : in std_logic;
y_end : out std_logic;
y_done : out std_logic;
y_start_enc : out std_logic;
y_start_dec : out std_logic;
y_start_exp : out std_logic;
y_mux_ctrl : out aes_mode
);
end aes_module_cu;
architecture Behavioral of aes_module_cu is
type States is (S_READY, S_ENC, S_DEC, S_EXP, S_DONE);
signal S, S_next : States;
begin
delta : process (S, x_start, x_mode, x_end_enc, x_end_dec, x_end_exp)
begin
case S is
when S_READY => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
if x_start = '1' then
case x_mode is
when ENCRYPT => y_start_enc <= '1';
S_next <= S_ENC;
when DECRYPT => y_start_dec <= '1';
S_next <= S_DEC;
when EXPAND_KEY => y_start_exp <= '1';
S_next <= S_EXP;
when others => S_next <= S_READY;
end case;
else
S_next <= S_READY;
end if;
when S_ENC => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
y_mux_ctrl <= ENCRYPT;
if x_end_enc = '1' then
y_end <= '1';
S_next <= S_DONE;
else
S_next <= S_ENC;
end if;
when S_DEC => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
y_mux_ctrl <= DECRYPT;
if x_end_dec = '1' then
y_end <= '1';
S_next <= S_DONE;
else
S_next <= S_DEC;
end if;
when S_EXP => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
if x_end_exp = '1' then
y_end <= '1';
S_next <= S_DONE;
else
S_next <= S_EXP;
end if;
when S_DONE => y_done <= '1';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
if x_start = '1' then
case x_mode is
when ENCRYPT => y_start_enc <= '1';
S_next <= S_ENC;
when DECRYPT => y_start_dec <= '1';
S_next <= S_DEC;
when EXPAND_KEY => y_start_exp <= '1';
S_next <= S_EXP;
when others => S_next <= S_DONE;
end case;
else
S_next <= S_DONE;
end if;
end case;
end process delta;
feedback_loop : process (clk, reset, S_next)
begin
if reset = '1' then
S <= S_READY;
elsif rising_edge(clk) then
S <= S_next;
end if;
end process feedback_loop;
end Behavioral;
| bsd-2-clause | 0c15830e395b0d1bf3493bd72504a1c2 | 0.449974 | 3.082612 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/clk_x_pntrs_builtin.vhd | 19 | 43,418 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 30400)
`protect data_block
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| bsd-2-clause | f810a5d3bb6aab944fe16d57e0738cc2 | 0.950205 | 1.829128 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_updt_sm.vhd | 1 | 41,813 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_sm.vhd
-- Description: This entity manages updating of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_sm is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0
-- Starting update word offset
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
ftch_error : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_updt_queue_empty : in std_logic ; --
ch1_updt_curdesc_wren : in std_logic ; --
ch1_updt_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_updt_ioc : in std_logic ; --
ch1_dma_interr : in std_logic ; --
ch1_dma_slverr : in std_logic ; --
ch1_dma_decerr : in std_logic ; --
ch1_updt_active : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_done : out std_logic ; --
--
-- Channel 2 Control and Status --
ch2_updt_queue_empty : in std_logic ; --
-- ch2_updt_curdesc_wren : in std_logic ; --
-- ch2_updt_curdesc : in std_logic_vector --
-- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_updt_ioc : in std_logic ; --
ch2_dma_interr : in std_logic ; --
ch2_dma_slverr : in std_logic ; --
ch2_dma_decerr : in std_logic ; --
ch2_updt_active : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_done : out std_logic ; --
--
-- DataMover Command --
updt_cmnd_wr : out std_logic ; --
updt_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-- DataMover Status --
updt_done : in std_logic ; --
updt_error : in std_logic ; --
updt_interr : in std_logic ; --
updt_slverr : in std_logic ; --
updt_decerr : in std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_updt_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant UPDATE_CMD_TAG : std_logic_vector(3 downto 0) := (others => '0');
-- DataMover Command Type
-- Always set to INCR type
constant UPDATE_CMD_TYPE : std_logic := '1';
-- DataMover Cmnd Reserved Bits
constant UPDATE_MSB_IGNORED : std_logic_vector(7 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant UPDATE_LSB_IGNORED : std_logic_vector(15 downto 0) := (others => '0');
-- DataMover Cmnd Bytes to Xfer for Channel 1
constant UPDATE_CH1_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH1_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Bytes to Xfer for Channel 2
constant UPDATE_CH2_CMD_BTT : std_logic_vector(SG_BTT_WIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(
(C_SG_CH2_WORDS_TO_UPDATE*4),SG_BTT_WIDTH));
-- DataMover Cmnd Reserved Bits
constant UPDATE_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_SG_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_SG_ADDR_WIDTH)
:= (others => '0');
-- DataMover Cmnd Address Offset for channel 1
constant UPDATE_CH1_ADDR_OFFSET : integer := C_SG_CH1_FIRST_UPDATE_WORD*4;
-- DataMover Cmnd Address Offset for channel 2
constant UPDATE_CH2_ADDR_OFFSET : integer := C_SG_CH2_FIRST_UPDATE_WORD*4;
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
type SG_UPDATE_STATE_TYPE is (
IDLE,
GET_UPDATE_PNTR,
UPDATE_DESCRIPTOR,
UPDATE_STATUS,
UPDATE_ERROR
);
signal updt_cs : SG_UPDATE_STATE_TYPE;
signal updt_ns : SG_UPDATE_STATE_TYPE;
-- State Machine Signals
signal ch1_active_set : std_logic := '0';
signal ch2_active_set : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal ch1_updt_sm_idle : std_logic := '0';
signal ch2_updt_sm_idle : std_logic := '0';
-- Misc Signals
signal ch1_active_i : std_logic := '0';
signal service_ch1 : std_logic := '0';
signal ch2_active_i : std_logic := '0';
signal service_ch2 : std_logic := '0';
signal update_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal update_cmd_btt : std_logic_vector
(SG_BTT_WIDTH-1 downto 0) := (others => '0');
signal update_tag : std_logic_vector (3 downto 0);
signal updt_ioc_irq_set : std_logic := '0';
signal ch1_interr_catch : std_logic := '0';
signal ch2_interr_catch : std_logic := '0';
signal ch1_decerr_catch : std_logic := '0';
signal ch2_decerr_catch : std_logic := '0';
signal ch1_slverr_catch : std_logic := '0';
signal ch2_slverr_catch : std_logic := '0';
signal updt_cmnd_data_int : std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH --
+CMD_BASE_WIDTH)-1 downto 0) ; --
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ch1_updt_active <= ch1_active_i;
ch2_updt_active <= ch2_active_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
SG_UPDT_MACHINE : process(updt_cs,
ch1_active_i,
ch2_active_i,
service_ch1,
service_ch2,
ch1_updt_curdesc_wren,
-- ch2_updt_curdesc_wren,
updt_error,
updt_done)
begin
-- Default signal assignment
ch1_active_set <= '0';
ch2_active_set <= '0';
write_cmnd_cmb <= '0';
ch1_updt_sm_idle <= '0';
ch2_updt_sm_idle <= '0';
updt_ns <= updt_cs;
case updt_cs is
-------------------------------------------------------------------
when IDLE =>
ch1_updt_sm_idle <= not service_ch1;
ch2_updt_sm_idle <= not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
updt_ns <= UPDATE_ERROR;
-- If channel 1 is running and not idle and queue is not full
-- then fetch descriptor for channel 1
elsif(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- If channel 2 is running and not idle and queue is not full
-- then fetch descriptor for channel 2
elsif(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
else
updt_ns <= IDLE;
end if;
when GET_UPDATE_PNTR =>
if(ch1_updt_curdesc_wren = '1')then
updt_ns <= UPDATE_DESCRIPTOR;
else
updt_ns <= GET_UPDATE_PNTR;
end if;
-- if(ch1_updt_curdesc_wren = '1' or ch2_updt_curdesc_wren = '1')then
-- updt_ns <= UPDATE_DESCRIPTOR;
-- else
-- updt_ns <= GET_UPDATE_PNTR;
-- end if;
-------------------------------------------------------------------
when UPDATE_DESCRIPTOR =>
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- write command
else
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
write_cmnd_cmb <= '1';
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_STATUS =>
ch1_updt_sm_idle <= not ch1_active_i and not service_ch1;
ch2_updt_sm_idle <= not ch2_active_i and not service_ch2;
-- error during update - therefore shut down
if(updt_error = '1')then
-- coverage off
updt_ns <= UPDATE_ERROR;
-- coverage on
-- wait until done with update
elsif(updt_done = '1')then
-- If just finished fethcing for channel 2 then...
if(ch2_active_i = '1')then
-- If ready, update descriptor for channel 1
if(service_ch1 = '1')then
ch1_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
-- If just finished fethcing for channel 1 then...
elsif(ch1_active_i = '1')then
-- If ready, update descriptor for channel 2
if(service_ch2 = '1')then
ch2_active_set <= '1';
updt_ns <= GET_UPDATE_PNTR;
-- Otherwise return to IDLE
else
updt_ns <= IDLE;
end if;
else
-- coverage off
updt_ns <= IDLE;
-- coverage on
end if;
else
updt_ns <= UPDATE_STATUS;
end if;
-------------------------------------------------------------------
when UPDATE_ERROR =>
ch1_updt_sm_idle <= '1';
ch2_updt_sm_idle <= '1';
updt_ns <= UPDATE_ERROR;
-------------------------------------------------------------------
-- coverage off
when others =>
updt_ns <= IDLE;
-- coverage on
end case;
end process SG_UPDT_MACHINE;
-------------------------------------------------------------------------------
-- Register states of state machine
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_cs <= IDLE;
else
updt_cs <= updt_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH1_UPDATE : if C_INCLUDE_CH1 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH1_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_active_i <= '0';
elsif(ch1_active_i = '1' and updt_done = '1')then
ch1_active_i <= '0';
elsif(ch1_active_set = '1')then
ch1_active_i <= '1';
end if;
end if;
end process CH1_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 ready to be serviced?
-------------------------------------------------------------------------------
service_ch1 <= '1' when ch1_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 1 Interrupt On Complete
-------------------------------------------------------------------------------
CH1_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch1_updt_ioc = '1')then
ch1_updt_ioc_irq_set <= '1';
else
ch1_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH1_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH1_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch1_dma_interr = '1')then
ch1_dma_interr_set <= '1';
end if;
end if;
end process CH1_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH1_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch1_dma_slverr = '1')then
ch1_dma_slverr_set <= '1';
end if;
end if;
end process CH1_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH1_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch1_dma_decerr = '1')then
ch1_dma_decerr_set <= '1';
end if;
end if;
end process CH1_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_slverr_set <= '0';
elsif(ch1_active_i = '1' and updt_slverr = '1')then
ch1_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_interr_set <= '0';
elsif(ch1_active_i = '1' and updt_interr = '1')then
-- coverage off
ch1_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_decerr_set <= '0';
elsif(ch1_active_i = '1' and updt_decerr = '1')then
ch1_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch1_updt_idle <= '1';
elsif(service_ch1 = '1')then
ch1_updt_idle <= '0';
elsif(service_ch1 = '0' and ch1_updt_sm_idle = '1')then
ch1_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH1_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_updt_done <= '0';
elsif(updt_done = '1' and ch1_active_i = '1')then
ch1_updt_done <= '1';
else
ch1_updt_done <= '0';
end if;
end if;
end process REG_CH1_DONE;
end generate GEN_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH1_UPDATE : if C_INCLUDE_CH1 = 0 generate
begin
service_ch1 <= '0';
ch1_active_i <= '0';
ch1_updt_idle <= '0';
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set <= '0';
ch1_dma_slverr_set <= '0';
ch1_dma_decerr_set <= '0';
ch1_updt_ioc_irq_set <= '0';
ch1_updt_done <= '0';
end generate GEN_NO_CH1_UPDATE;
-------------------------------------------------------------------------------
-- Channel included therefore generate fetch logic
-------------------------------------------------------------------------------
GEN_CH2_UPDATE : if C_INCLUDE_CH2 = 1 generate
begin
-------------------------------------------------------------------------------
-- Active channel flag. Indicates which channel is active.
-- 0 = channel active
-- 1 = channel active
-------------------------------------------------------------------------------
CH2_ACTIVE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_active_i <= '0';
elsif(ch2_active_i = '1' and updt_done = '1')then
ch2_active_i <= '0';
elsif(ch2_active_set = '1')then
ch2_active_i <= '1';
end if;
end if;
end process CH2_ACTIVE_PROCESS;
-------------------------------------------------------------------------------
-- Channel 2 ready to be serviced?
-------------------------------------------------------------------------------
service_ch2 <= '1' when ch2_updt_queue_empty = '0' -- Queue not empty
and ftch_error = '0' -- No SG Fetch Error
else '0';
-------------------------------------------------------------------------------
-- Channel 2 Interrupt On Complete
-------------------------------------------------------------------------------
CH2_INTR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_ioc_irq_set <= '0';
-- Set interrupt on Done and Descriptor IOC set
elsif(updt_done = '1' and ch2_updt_ioc = '1')then
ch2_updt_ioc_irq_set <= '1';
else
ch2_updt_ioc_irq_set <= '0';
end if;
end if;
end process CH2_INTR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Internal Error
-------------------------------------------------------------------------------
CH2_INTERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_interr_set <= '0';
-- Set internal error on desc updt Done and Internal Error
elsif(updt_done = '1' and ch2_dma_interr = '1')then
ch2_dma_interr_set <= '1';
end if;
end if;
end process CH2_INTERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Slave Error
-------------------------------------------------------------------------------
CH2_SLVERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_slverr_set <= '0';
-- Set slave error on desc updt Done and Slave Error
elsif(updt_done = '1' and ch2_dma_slverr = '1')then
ch2_dma_slverr_set <= '1';
end if;
end if;
end process CH2_SLVERR_PROCESS;
-------------------------------------------------------------------------------
-- Channel 1 DMA Decode Error
-------------------------------------------------------------------------------
CH2_DECERR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_dma_decerr_set <= '0';
-- Set decode error on desc updt Done and Decode Error
elsif(updt_done = '1' and ch2_dma_decerr = '1')then
ch2_dma_decerr_set <= '1';
end if;
end if;
end process CH2_DECERR_PROCESS;
-------------------------------------------------------------------------------
-- Log Fetch Errors
-------------------------------------------------------------------------------
-- Log Slave Errors reported during descriptor update
SLV_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_slverr_set <= '0';
elsif(ch2_active_i = '1' and updt_slverr = '1')then
ch2_updt_slverr_set <= '1';
end if;
end if;
end process SLV_SET_PROCESS;
-- Log Internal Errors reported during descriptor update
INT_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_interr_set <= '0';
elsif(ch2_active_i = '1' and updt_interr = '1')then
-- coverage off
ch2_updt_interr_set <= '1';
-- coverage on
end if;
end if;
end process INT_SET_PROCESS;
-- Log Decode Errors reported during descriptor update
DEC_SET_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_decerr_set <= '0';
elsif(ch2_active_i = '1' and updt_decerr = '1')then
ch2_updt_decerr_set <= '1';
end if;
end if;
end process DEC_SET_PROCESS;
-- Indicate update is idle if state machine is idle and update queue is empty
IDLE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_error = '1' or ftch_error = '1')then
ch2_updt_idle <= '1';
elsif(service_ch2 = '1')then
ch2_updt_idle <= '0';
elsif(service_ch2 = '0' and ch2_updt_sm_idle = '1')then
ch2_updt_idle <= '1';
end if;
end if;
end process IDLE_PROCESS;
---------------------------------------------------------------------------
-- Indicate update is done to allow fetch of next descriptor
-- This is needed to prevent a partial descriptor being fetched
-- and then axi read is throttled for extended periods until the
-- remainder of the descriptor is fetched.
--
-- Note: Only used when fetch queue not inluded otherwise
-- tools optimize out this process
---------------------------------------------------------------------------
REG_CH2_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_updt_done <= '0';
elsif(updt_done = '1' and ch2_active_i = '1')then
ch2_updt_done <= '1';
else
ch2_updt_done <= '0';
end if;
end if;
end process REG_CH2_DONE;
end generate GEN_CH2_UPDATE;
-------------------------------------------------------------------------------
-- Channel excluded therefore do not generate fetch logic
-------------------------------------------------------------------------------
GEN_NO_CH2_UPDATE : if C_INCLUDE_CH2 = 0 generate
begin
service_ch2 <= '0';
ch2_active_i <= '0';
ch2_updt_idle <= '0';
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set <= '0';
ch2_dma_slverr_set <= '0';
ch2_dma_decerr_set <= '0';
ch2_updt_ioc_irq_set <= '0';
ch2_updt_done <= '0';
end generate GEN_NO_CH2_UPDATE;
---------------------------------------------------------------------------
-- Register Current Update Address. Address captured from channel port
-- or queue by axi_sg_updt_queue
---------------------------------------------------------------------------
REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- Channel 1 descriptor update pointer
elsif(ch1_updt_curdesc_wren = '1')then
update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
+ 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
end if;
end if;
end process REG_UPDATE_ADDRESS;
update_tag <= "0000" when ch2_active_i = '1' else
"0001";
--REG_UPDATE_ADDRESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= (others => '0');
-- update_tag <= "0000";
-- -- Channel 1 descriptor update pointer
-- elsif(ch1_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch1_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0001";
-- -- Channel 2 descriptor update pointer
-- elsif(ch2_updt_curdesc_wren = '1')then
-- update_address (C_M_AXI_SG_ADDR_WIDTH-1 downto 4) <= std_logic_vector(unsigned(ch2_updt_curdesc (C_M_AXI_SG_ADDR_WIDTH-1 downto 4))
-- + 1);
-- update_tag <= "0000";
-- end if;
-- end if;
-- end process REG_UPDATE_ADDRESS;
update_address (3 downto 0) <= "1100";
-- Assigne Bytes to Transfer (BTT)
update_cmd_btt <= UPDATE_CH1_CMD_BTT when ch1_active_i = '1'
else UPDATE_CH2_CMD_BTT;
updt_cmnd_data <= updt_cmnd_data_int;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- When command by sm, drive command to updt_cmdsts_if
--GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- updt_cmnd_wr <= '0';
-- updt_cmnd_data_int <= (others => '0');
-- -- Fetch SM issued a command write
-- elsif(write_cmnd_cmb = '1')then
updt_cmnd_wr <= write_cmnd_cmb; --'1';
updt_cmnd_data_int <= UPDATE_CMD_RSVD
& update_tag --UPDATE_CMD_TAG
& update_address
& UPDATE_MSB_IGNORED
& UPDATE_CMD_TYPE
& UPDATE_LSB_IGNORED
& update_cmd_btt;
-- else
-- updt_cmnd_wr <= '0';
-- end if;
-- end if;
-- end process GEN_DATAMOVER_CMND;
-------------------------------------------------------------------------------
-- Capture and hold fetch address in case an error occurs
-------------------------------------------------------------------------------
LOG_ERROR_ADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= (others => '0');
elsif(write_cmnd_cmb = '1')then
updt_error_addr (C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB) <= update_address(C_M_AXI_SG_ADDR_WIDTH-1 downto SG_ADDR_LSB);
end if;
end if;
end process LOG_ERROR_ADDR;
updt_error_addr (5 downto 0) <= "000000";
end implementation;
| mit | b8ae1234320ec3e405061defa6bbb299 | 0.399589 | 4.608509 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sg_if.vhd | 1 | 81,373 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sg_if.vhd
-- Description: This entity is the S2MM Scatter Gather Interface for Descriptor
-- Fetches and Updates.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
library lib_srl_fifo_v1_0_2;
use lib_srl_fifo_v1_0_2.srl_fifo_f;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sg_if is
generic (
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Any one of the 4 clock inputs is not
-- synchronous to the other
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1 ;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0 ;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14 ;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 ;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32 ;
-- Slave AXI Status Stream Data Width
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1 ;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- S2MM Descriptor Fetch Request (from s2mm_sm) --
desc_available : out std_logic ; --
desc_fetch_req : in std_logic ; --
updt_pending : out std_logic ;
desc_fetch_done : out std_logic ; --
--
-- S2MM Descriptor Update Request (from s2mm_sm) --
desc_update_done : out std_logic ; --
s2mm_sts_received_clr : out std_logic ; --
s2mm_sts_received : in std_logic ; --
--
-- Scatter Gather Update Status --
s2mm_done : in std_logic ; --
s2mm_interr : in std_logic ; --
s2mm_slverr : in std_logic ; --
s2mm_decerr : in std_logic ; --
s2mm_tag : in std_logic_vector(3 downto 0) ; --
s2mm_brcvd : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_eof_set : in std_logic ; --
s2mm_packet_eof : in std_logic ; --
s2mm_halt : in std_logic ; --
--
-- S2MM Status Stream Interface --
stsstrm_fifo_rden : out std_logic ; --
stsstrm_fifo_empty : in std_logic ; --
stsstrm_fifo_dout : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0); --
--
-- DataMover Command --
s2mm_cmnd_wr : in std_logic ; --
s2mm_cmnd_data : in std_logic_vector --
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_S2MM_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- S2MM Descriptor Field Output --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
--
s2mm_desc_info : out std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : out std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_v : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_blength_s : out std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) ; --
s2mm_desc_cmplt : out std_logic ; --
s2mm_eof_micro : out std_logic ;
s2mm_sof_micro : out std_logic ;
s2mm_desc_app0 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app1 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app2 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app3 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
s2mm_desc_app4 : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sg_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sg_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE async_reg : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Status reserved bits
constant RESERVED_STS : std_logic_vector(2 downto 0)
:= (others => '0');
-- Zero value constant
constant ZERO_VALUE : std_logic_vector(31 downto 0)
:= (others => '0');
-- Zero length constant
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_shftenbl : std_logic := '0';
-- fetch descriptor holding registers
signal desc_reg12 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg11 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg10 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg9 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg8 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg7 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg6 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg5 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal desc_reg0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_lsb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_curdesc_msb_nxt : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_lsb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_baddr_msb : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_pending_update : std_logic := '0';
signal s2mm_new_curdesc_wren_i : std_logic := '0';
signal s2mm_ioc : std_logic := '0';
signal s2mm_pending_pntr_updt : std_logic := '0';
-- Descriptor Update Signals
signal s2mm_complete : std_logic := '0';
signal s2mm_xferd_bytes : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_v_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal s2mm_desc_blength_s_i : std_logic_vector(BUFFER_LENGTH_WIDTH - 1 downto 0) := (others => '0');
-- Signals for pointer support
-- Make 1 bit wider to allow tagging of LAST for use in generating tlast
signal updt_desc_reg0 : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal updt_desc_reg1 : std_logic_vector(C_S_AXIS_UPDPTR_TDATA_WIDTH downto 0) := (others => '0');
signal updt_shftenbl : std_logic := '0';
signal updtptr_tvalid : std_logic := '0';
signal updtptr_tlast : std_logic := '0';
signal updtptr_tdata : std_logic_vector(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
-- Signals for Status Stream Support
signal updt_desc_sts : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_desc_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg3 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg4 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg5 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg6 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal updt_zero_reg7 : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH downto 0) := (others => '0');
signal writing_app_fields : std_logic := '0';
signal stsstrm_fifo_rden_i : std_logic := '0';
signal sts_shftenbl : std_logic := '0';
signal sts_received : std_logic := '0';
signal sts_received_d1 : std_logic := '0';
signal sts_received_re : std_logic := '0';
-- Queued Update signals
signal updt_data_clr : std_logic := '0';
signal updt_sts_clr : std_logic := '0';
signal updt_data : std_logic := '0';
signal updt_sts : std_logic := '0';
signal ioc_tag : std_logic := '0';
signal s2mm_sof_set : std_logic := '0';
signal s2mm_in_progress : std_logic := '0';
signal eof_received : std_logic := '0';
signal sof_received : std_logic := '0';
signal updtsts_tvalid : std_logic := '0';
signal updtsts_tlast : std_logic := '0';
signal updtsts_tdata : std_logic_vector(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_halt_d1_cdc_tig : std_logic := '0';
signal s2mm_halt_cdc_d2 : std_logic := '0';
signal s2mm_halt_d2 : std_logic := '0';
--ATTRIBUTE async_reg OF s2mm_halt_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF s2mm_halt_cdc_d2 : SIGNAL IS "true";
signal desc_fetch_done_i : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Drive buffer length out
s2mm_desc_blength <= s2mm_desc_blength_i;
s2mm_desc_blength_v <= s2mm_desc_blength_v_i;
s2mm_desc_blength_s <= s2mm_desc_blength_s_i;
updt_pending <= s2mm_pending_update;
-- Drive ready if descriptor fetch request is being made
m_axis_s2mm_ftch_tready <= desc_fetch_req -- Request descriptor fetch
and not s2mm_pending_update; -- No pending pointer updates
desc_fetch_done <= desc_fetch_done_i;
-- Shift in data from SG engine if tvalid and fetch request
ftch_shftenbl <= m_axis_s2mm_ftch_tvalid_new
and desc_fetch_req
and not s2mm_pending_update;
-- Passed curdes write out to register module
s2mm_new_curdesc_wren <= s2mm_new_curdesc_wren_i;
-- tvalid asserted means descriptor availble
desc_available <= m_axis_ftch2_desc_available; --m_axis_s2mm_ftch_tvalid_new;
--***************************************************************************--
--** Register DataMover Halt to secondary if needed
--***************************************************************************--
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Double register to secondary clock domain. This is sufficient
-- because halt will remain asserted until halt_cmplt detected in
-- reset module in secondary clock domain.
REG_TO_SECONDARY : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => s2mm_halt,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => s2mm_halt_cdc_d2,
scndry_vect_out => open
);
-- REG_TO_SECONDARY : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- -- if(m_axi_sg_aresetn = '0')then
-- -- s2mm_halt_d1_cdc_tig <= '0';
-- -- s2mm_halt_d2 <= '0';
-- -- else
-- s2mm_halt_d1_cdc_tig <= s2mm_halt;
-- s2mm_halt_cdc_d2 <= s2mm_halt_d1_cdc_tig;
-- -- end if;
-- end if;
-- end process REG_TO_SECONDARY;
s2mm_halt_d2 <= s2mm_halt_cdc_d2;
end generate GEN_FOR_ASYNC;
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
-- No clock crossing required therefore simple pass through
s2mm_halt_d2 <= s2mm_halt;
end generate GEN_FOR_SYNC;
--***************************************************************************--
--** Descriptor Fetch Logic **--
--***************************************************************************--
s2mm_desc_curdesc_lsb <= desc_reg0;
--s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
--s2mm_desc_curdesc_msb_nxt <= desc_reg3;
s2mm_desc_baddr_lsb <= desc_reg4;
GEN_NO_MCDMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9( DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64);
desc_reg9(30 downto 0) <= (others => '0');
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
-- s2mm_desc_curdesc_msb_nxt <= (others => '0'); --desc_reg1;
s2mm_desc_info <= (others => '0');
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_sof_micro <= desc_reg8 (DESC_SOF_BIT);
s2mm_eof_micro <= desc_reg8 (DESC_EOF_BIT);
s2mm_desc_blength_i <= desc_reg8(DESC_BLENGTH_MSB_BIT downto DESC_BLENGTH_LSB_BIT);
s2mm_desc_blength_v_i <= (others => '0');
s2mm_desc_blength_s_i <= (others => '0') ;
ADDR_64BIT : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT;
ADDR_32BIT : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT;
ADDR_64BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_DMA;
ADDR_32BIT_DMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg0;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_DMA;
end generate GEN_NO_MCDMA;
GEN_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
desc_fetch_done_i <= m_axis_s2mm_ftch_tvalid_new; --ftch_shftenbl;
desc_reg0 <= m_axis_s2mm_ftch_tdata_new (96 downto 65); --127 downto 96);
desc_reg4 <= m_axis_s2mm_ftch_tdata_new (31 downto 0);
desc_reg8 <= m_axis_s2mm_ftch_tdata_new (63 downto 32);
desc_reg9(DESC_STS_CMPLTD_BIT) <= m_axis_s2mm_ftch_tdata_new (64); --95 downto 64);
desc_reg9(30 downto 0) <= (others => '0');
desc_reg2 <= m_axis_s2mm_ftch_tdata_mcdma_nxt (31 downto 0);
desc_reg6 <= m_axis_s2mm_ftch_tdata_mcdma_new (31 downto 0);
desc_reg7 <= m_axis_s2mm_ftch_tdata_mcdma_new (63 downto 32);
s2mm_desc_info <= desc_reg6 (31 downto 24) & desc_reg9 (23 downto 0);
-- desc 4 and desc 5 are reserved and thus don't care
s2mm_desc_blength_i <= "0000000" & desc_reg8(15 downto 0);
s2mm_desc_blength_v_i <= "0000000000" & desc_reg7(31 downto 19);
s2mm_desc_blength_s_i <= "0000000" & desc_reg7(15 downto 0);
ADDR_64BIT_1 : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (160 downto 129);
end generate ADDR_64BIT_1;
ADDR_32BIT_1 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_msb <= (others => '0');
s2mm_desc_baddr_msb <= (others => '0');
end generate ADDR_32BIT_1;
ADDR_64BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH > 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= m_axis_s2mm_ftch_tdata_mcdma_nxt (63 downto 32);
end generate ADDR_64BIT_MCDMA;
ADDR_32BIT_MCDMA : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
s2mm_desc_curdesc_lsb_nxt <= desc_reg2;
s2mm_desc_curdesc_msb_nxt <= (others => '0');
end generate ADDR_32BIT_MCDMA;
end generate GEN_MCDMA;
s2mm_desc_cmplt <= desc_reg9(DESC_STS_CMPLTD_BIT);
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-------------------------------------------------------------------------------
-- BUFFER ADDRESS
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 64 generate
s2mm_desc_baddress <= s2mm_desc_baddr_msb & s2mm_desc_baddr_lsb;
-- s2mm_desc_baddr_msb <= m_axis_s2mm_ftch_tdata_new (128 downto 97);
end generate GEN_NEW_64BIT_BUFADDR;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_BUFADDR : if C_M_AXI_S2MM_ADDR_WIDTH = 32 generate
s2mm_desc_baddress <= s2mm_desc_baddr_lsb;
end generate GEN_NEW_32BIT_BUFADDR;
-------------------------------------------------------------------------------
-- NEW CURRENT DESCRIPTOR
-------------------------------------------------------------------------------
-- If 64 bit addressing then concatinate msb to lsb
GEN_NEW_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_msb_nxt & s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_64BIT_CURDESC;
-- If 32 bit addressing then simply pass lsb out
GEN_NEW_32BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
s2mm_new_curdesc <= s2mm_desc_curdesc_lsb_nxt;
end generate GEN_NEW_32BIT_CURDESC;
s2mm_new_curdesc_wren_i <= desc_fetch_done_i; --ftch_shftenbl;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
-- SOF Flagging logic for when descriptor queues are enabled in SG Engine
GEN_SOF_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
-- SOF Queued one count value
constant ONE_COUNT : std_logic_vector(2 downto 0) := "001";
signal incr_sof_count : std_logic := '0';
signal decr_sof_count : std_logic := '0';
signal sof_count : std_logic_vector(2 downto 0) := (others => '0');
signal sof_received_set : std_logic := '0';
signal sof_received_clr : std_logic := '0';
signal cmd_wr_mask : std_logic := '0';
begin
-- Keep track of number of commands queued up in data mover to
-- allow proper setting of SOF's and EOF's when associated
-- descriptor is updated.
REG_SOF_COUNT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_count <= (others => '0');
elsif(incr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) + 1);
elsif(decr_sof_count = '1')then
sof_count <= std_logic_vector(unsigned(sof_count(2 downto 0)) - 1);
end if;
end if;
end process REG_SOF_COUNT;
-- Increment count on each command write that does NOT occur
-- coincident with a status received
incr_sof_count <= s2mm_cmnd_wr and not sts_received_re;
-- Decrement count on each status received that does NOT
-- occur coincident with a command write
decr_sof_count <= sts_received_re and not s2mm_cmnd_wr;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sof_received <= '0';
elsif(sof_received_set = '1')then
sof_received <= '1';
elsif(sof_received_clr = '1')then
sof_received <= '0';
end if;
end if;
end process REG_SOF_STATUS;
-- SOF Received
-- Case 1 (i.e. already running): EOF received therefore next has to be SOF
-- Case 2 (i.e. initial command): No commands in queue (count=0) therefore this must be an SOF command
sof_received_set <= '1' when (sts_received_re = '1' -- Status back from Datamover
and eof_received = '1') -- End of packet received
-- OR...
or (s2mm_cmnd_wr = '1' -- Command written to datamover
and cmd_wr_mask = '0' -- Not inner-packet command
and sof_count = ZERO_VALUE(2 downto 0)) -- No Queued SOF cmnds
else '0';
-- Done with SOF's
-- Status received and EOF received flag not set
-- Or status received and EOF received flag set and last SOF
sof_received_clr <= '1' when (sts_received_re = '1' and eof_received = '0')
or (sts_received_re = '1' and eof_received = '1' and sof_count = ONE_COUNT)
else '0';
-- Mask command writes if inner-packet command written. An inner packet
-- command is one where status if received and eof_received is not asserted.
-- This mask is only used for when a cmd_wr occurs and sof_count is zero, meaning
-- no commands happen to be queued in datamover.
WR_MASK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
cmd_wr_mask <= '0';
-- received data mover status, mask if EOF not set
-- clear mask if EOF set.
elsif(sts_received_re = '1')then
cmd_wr_mask <= not eof_received;
end if;
end if;
end process WR_MASK;
end generate GEN_SOF_QUEUE_MODE;
-- SOF Flagging logic for when descriptor queues are disabled in SG Engine
GEN_SOF_NO_QUEUE_MODE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
-----------------------------------------------------------------------
-- Assert window around receive packet in order to properly set
-- SOF and EOF bits in descriptor
--
-- SOF for S2MM determined by new command write to datamover, i.e.
-- command write receive packet not already in progress.
-----------------------------------------------------------------------
RX_IN_PROG_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_packet_eof = '1')then
s2mm_in_progress <= '0';
s2mm_sof_set <= '0';
elsif(s2mm_in_progress = '0' and s2mm_cmnd_wr = '1')then
s2mm_in_progress <= '1';
s2mm_sof_set <= '1';
else
s2mm_in_progress <= s2mm_in_progress;
s2mm_sof_set <= '0';
end if;
end if;
end process RX_IN_PROG_PROCESS;
-- Drive sof and eof setting to interrupt module for delay interrupt
--s2mm_packet_sof <= s2mm_sof_set;
REG_SOF_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
sof_received <= '0';
elsif(s2mm_sof_set = '1')then
sof_received <= '1';
end if;
end if;
end process REG_SOF_STATUS;
end generate GEN_SOF_NO_QUEUE_MODE;
-- IOC and EOF bits in desc update both set via packet eof flag from
-- command/status interface.
eof_received <= s2mm_packet_eof;
s2mm_ioc <= s2mm_packet_eof;
--***************************************************************************--
--** Descriptor Update Logic **--
--***************************************************************************--
--*****************************************************************************
--** Pointer Update Logic
--*****************************************************************************
-----------------------------------------------------------------------
-- Capture LSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
-----------------------------------------------------------------------
UPDT_DESC_WRD0: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (31 downto 0) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (31 downto 0) <= s2mm_desc_curdesc_lsb;
end if;
end if;
end process UPDT_DESC_WRD0;
---------------------------------------------------------------------------
-- Capture MSB cur descriptor on write for use on descriptor update.
-- This will be the address the descriptor is updated to
---------------------------------------------------------------------------
PTR_64BIT_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
UPDT_DESC_WRD1: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= (others => '0');
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_desc_reg0 (C_M_AXI_SG_ADDR_WIDTH-1 downto 32) <= s2mm_desc_curdesc_msb;
end if;
end if;
end process UPDT_DESC_WRD1;
end generate PTR_64BIT_CURDESC;
-- Shift in pointer to SG engine if tvalid, tready, and not on last word
updt_shftenbl <= updt_data and updtptr_tvalid and s_axis_s2mm_updtptr_tready;
-- Update data done when updating data and tlast received and target
-- (i.e. SG Engine) is ready
updt_data_clr <= '1' when updtptr_tvalid = '1'
and updtptr_tlast = '1'
and s_axis_s2mm_updtptr_tready = '1'
else '0';
---------------------------------------------------------------------------
-- When desc data ready for update set and hold flag until
-- data can be updated to queue. Note it may
-- be held off due to update of status
---------------------------------------------------------------------------
UPDT_DATA_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
updt_data <= '0';
-- clear flag when data update complete
-- elsif(updt_data_clr = '1')then
-- updt_data <= '0';
-- -- set flag when desc fetched as indicated
-- -- by curdesc wren
elsif(s2mm_new_curdesc_wren_i = '1')then
updt_data <= '1';
end if;
end if;
end process UPDT_DATA_PROCESS;
updtptr_tvalid <= updt_data;
updtptr_tlast <= DESC_LAST; --updt_desc_reg0(C_S_AXIS_UPDPTR_TDATA_WIDTH);
updtptr_tdata <= updt_desc_reg0;
-- Pass out to sg engine
s_axis_s2mm_updtptr_tdata <= updtptr_tdata;
s_axis_s2mm_updtptr_tlast <= updtptr_tlast and updtptr_tvalid;
s_axis_s2mm_updtptr_tvalid <= updtptr_tvalid;
--*****************************************************************************
--** Status Update Logic - DESCRIPTOR QUEUES INCLUDED **
--*****************************************************************************
GEN_DESC_UPDT_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
signal xb_fifo_reset : std_logic := '0';
signal xb_fifo_full : std_logic := '0';
begin
s2mm_complete <= '1'; -- Fixed at '1'
-----------------------------------------------------------------------
-- Need to flag a pending point update to prevent subsequent fetch of
-- descriptor from stepping on the stored pointer, and buffer length
-----------------------------------------------------------------------
REG_PENDING_UPDT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_data_clr = '1')then
s2mm_pending_pntr_updt <= '0';
elsif(s2mm_new_curdesc_wren_i = '1')then
s2mm_pending_pntr_updt <= '1';
end if;
end if;
end process REG_PENDING_UPDT;
-- Pending update on pointer not updated yet or xfer'ed bytes fifo full
s2mm_pending_update <= s2mm_pending_pntr_updt or xb_fifo_full;
-- Clear status received flag in cmdsts_if to
-- allow more status to be received from datamover
s2mm_sts_received_clr <= updt_sts_clr;
-- Generate a rising edge off status received in order to
-- flag status update
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= s2mm_sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= s2mm_sts_received and not sts_received_d1;
sts_received_re <= s2mm_sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_sts_clr = '1')then
updt_sts <= '0';
-- clear flag when status update done or
-- datamover halted
-- elsif(updt_sts_clr = '1')then
-- updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
xb_fifo_full <= '0'; -- Not used for indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_STATUS;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLast
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
GEN_DESC_UPDT_MCDMA : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA;
GEN_DESC_UPDT_DMA : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA;
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Get rx length is identical to command written, therefor store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
XFERRED_BYTE_FIFO : entity lib_srl_fifo_v1_0_2.srl_fifo_f
generic map(
C_DWIDTH => BUFFER_LENGTH_WIDTH ,
C_DEPTH => 16 ,
C_FAMILY => C_FAMILY
)
port map(
Clk => m_axi_sg_aclk ,
Reset => xb_fifo_reset ,
FIFO_Write => s2mm_cmnd_wr ,
Data_In => s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0) ,
FIFO_Read => sts_received_re ,
Data_Out => s2mm_xferd_bytes ,
FIFO_Empty => open ,
FIFO_Full => xb_fifo_full ,
Addr => open
);
xb_fifo_reset <= not m_axi_sg_aresetn;
end generate GEN_USING_STSAPP_LENGTH;
-- Not using status app length field therefore primary S2MM DataMover is
-- configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
xb_fifo_full <= '0'; -- Not used in Indeterminate BTT mode
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout (C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(s2mm_packet_eof = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
elsif(sts_shftenbl='1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_STATUS;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 and APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= DESC_NOT_LAST -- Not last word of stream
& '0' -- Don't set IOC
& ZERO_VALUE; -- Remainder is zero
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= DESC_LAST -- Last word of stream
& s2mm_ioc
& ZERO_VALUE; -- Remainder is zero
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_QUEUE;
--***************************************************************************--
--** Status Update Logic - NO DESCRIPTOR QUEUES **--
--***************************************************************************--
GEN_DESC_UPDT_NO_QUEUE : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
s2mm_sts_received_clr <= '1'; -- Not needed for the No Queue configuration
s2mm_complete <= '1'; -- Fixed at '1' for the No Queue configuration
s2mm_pending_update <= '0'; -- Not needed for the No Queue configuration
-- Status received based on a DONE or an ERROR from DataMover
sts_received <= s2mm_done or s2mm_interr or s2mm_decerr or s2mm_slverr;
-- Generate a rising edge off done for use in triggering an
-- update to the SG engine
REG_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_received_d1 <= '0';
else
sts_received_d1 <= sts_received;
end if;
end if;
end process REG_STATUS;
-- CR 566306 Status invalid during halt
-- sts_received_re <= sts_received and not sts_received_d1;
sts_received_re <= sts_received and not sts_received_d1 and not s2mm_halt_d2;
---------------------------------------------------------------------------
-- When status received set and hold flag until
-- status can be updated to queue. Note it may
-- be held off due to update of data
---------------------------------------------------------------------------
UPDT_STS_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_sts <= '0';
-- clear flag when status update done
elsif(updt_sts_clr = '1')then
updt_sts <= '0';
-- set flag when status received
elsif(sts_received_re = '1')then
updt_sts <= '1';
end if;
end if;
end process UPDT_STS_PROCESS;
-- Clear status update on acceptance of tlast by sg engine
updt_sts_clr <= '1' when updt_sts = '1'
and updtsts_tvalid = '1'
and updtsts_tlast = '1'
and s_axis_s2mm_updtsts_tready = '1'
else '0';
-- for queue case used to keep track of number of datamover queued cmnds
UPDT_DONE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_update_done <= '0';
else
desc_update_done <= updt_sts_clr;
end if;
end if;
end process UPDT_DONE_PROCESS;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - NO STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_NO_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 0 generate
begin
stsstrm_fifo_rden <= '0'; -- Not used in the NO sts stream configuration
GEN_NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NO_MICRO_DMA;
GEN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
s2mm_xferd_bytes <= (others => '0');
end generate GEN_MICRO_DMA;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Register Status on status received rising edge
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
end if;
end if;
end process UPDT_DESC_WRD2;
GEN_DESC_UPDT_MCDMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 1 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 20) &
s2mm_desc_info_in (13 downto 10) & "000" &
s2mm_desc_info_in (9 downto 5) & "000" &
s2mm_desc_info_in (4 downto 0);
end generate GEN_DESC_UPDT_MCDMA_NOQUEUE;
GEN_DESC_UPDT_DMA_NOQUEUE : if C_ENABLE_MULTI_CHANNEL = 0 generate
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
end generate GEN_DESC_UPDT_DMA_NOQUEUE;
-- Drive TVALID
updtsts_tvalid <= updt_sts;
-- Drive TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
-- Drive TData
-- updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH - 1 downto 0);
end generate GEN_DESC_UPDT_NO_STSAPP;
--***********************************************************************--
--** Descriptor Update Logic - NO DESCRIPTOR QUEUES - STS APP **--
--***********************************************************************--
---------------------------------------------------------------------------
-- Generate Descriptor Update Signaling for NO Status App Stream
---------------------------------------------------------------------------
GEN_DESC_UPDT_STSAPP : if C_SG_INCLUDE_STSCNTRL_STRM = 1 generate
begin
-- Rx length is identical to command written, therefore store
-- the BTT value from the command written to be used as the xferd bytes.
GEN_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 1 generate
begin
-----------------------------------------------------------------------
-- On S2MM transferred bytes equals buffer length. Capture length
-- on curdesc write.
-----------------------------------------------------------------------
REG_XFERRED_BYTES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_xferd_bytes <= (others => '0');
elsif(s2mm_cmnd_wr = '1')then
s2mm_xferd_bytes <= s2mm_cmnd_data(BUFFER_LENGTH_WIDTH-1 downto 0);
end if;
end if;
end process REG_XFERRED_BYTES;
end generate GEN_USING_STSAPP_LENGTH;
-- Configured as a store and forward channel (i.e. indeterminate BTT mode)
-- Receive length will be reported in datamover status.
GEN_NOT_USING_STSAPP_LENGTH : if C_SG_USE_STSAPP_LENGTH = 0 generate
begin
-- Transferred byte length from status is equal to bytes transferred field
-- in descriptor status
GEN_EQ_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH = 23 generate
begin
s2mm_xferd_bytes <= s2mm_brcvd;
end generate GEN_EQ_23BIT_BYTE_XFERED;
-- Transferred byte length from status is less than bytes transferred field
-- in descriptor status therefore need to pad value.
GEN_LESSTHN_23BIT_BYTE_XFERED : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
s2mm_xferd_bytes <= PAD_VALUE & s2mm_brcvd;
end generate GEN_LESSTHN_23BIT_BYTE_XFERED;
end generate GEN_NOT_USING_STSAPP_LENGTH;
-----------------------------------------------------------------------
-- For EOF Descriptor then need to update APP fields from Status
-- Stream FIFO
-----------------------------------------------------------------------
WRITE_APP_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_app_fields <= '0';
-- If writing app fields and reach LAST then stop writing
-- app fields
elsif(writing_app_fields = '1' -- Writing app fields
and stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) = '1' -- Last app word (tlast=1)
and stsstrm_fifo_rden_i = '1')then -- Fifo read
writing_app_fields <= '0';
-- ON EOF Descriptor, then need to write application fields on desc
-- update
elsif(eof_received = '1'
and s2mm_xferd_bytes /= ZERO_LENGTH) then
writing_app_fields <= '1';
end if;
end if;
end process WRITE_APP_PROCESS;
-- Shift in apps to SG engine if tvalid, tready, and not on last word
sts_shftenbl <= updt_sts and updtsts_tvalid and s_axis_s2mm_updtsts_tready;
-----------------------------------------------------------------------
-- Catpure Status. Status is built from status word from DataMover
-- and from transferred bytes value.
-----------------------------------------------------------------------
UPDT_DESC_WRD2 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_desc_sts <= (others => '0');
-- Status from Prmry Datamover received
elsif(sts_received_re = '1')then
updt_desc_sts <= DESC_NOT_LAST
& s2mm_ioc
& s2mm_complete
& s2mm_decerr
& s2mm_slverr
& s2mm_interr
& sof_received -- If asserted also set SOF
& eof_received -- If asserted also set EOF
& RESERVED_STS
& s2mm_xferd_bytes;
-- Shift on descriptor update
elsif(sts_shftenbl = '1')then
updt_desc_sts <= updt_desc_reg3;
end if;
end if;
end process UPDT_DESC_WRD2;
-----------------------------------------------------------------------
-- If EOF Descriptor (writing_app_fields=1) then pass data from
-- status stream FIFO into descriptor update shift registers
-- Else pass zeros
-----------------------------------------------------------------------
UPDT_REG3_MUX : process(writing_app_fields,
stsstrm_fifo_dout,
updt_zero_reg3,
sts_shftenbl)
begin
if(writing_app_fields = '1')then
updt_desc_reg3 <= stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH) -- Update LAST setting
& '0'
& stsstrm_fifo_dout(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); -- Update Word
stsstrm_fifo_rden_i <= sts_shftenbl;
else
updt_desc_reg3 <= updt_zero_reg3;
stsstrm_fifo_rden_i <= '0';
end if;
end process UPDT_REG3_MUX;
stsstrm_fifo_rden <= stsstrm_fifo_rden_i;
-----------------------------------------------------------------------
-- APP 0 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD3 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg3 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg3 <= updt_zero_reg4;
end if;
end if;
end process UPDT_ZERO_WRD3;
-----------------------------------------------------------------------
-- APP 1 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD4 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg4 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg4 <= updt_zero_reg5;
end if;
end if;
end process UPDT_ZERO_WRD4;
-----------------------------------------------------------------------
-- APP 2 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD5 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg5 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg5 <= updt_zero_reg6;
end if;
end if;
end process UPDT_ZERO_WRD5;
-----------------------------------------------------------------------
-- APP 3 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD6 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or sts_received_re = '1')then
updt_zero_reg6 <= (others => '0');
-- Shift data out on shift enable
elsif(sts_shftenbl = '1')then
updt_zero_reg6 <= updt_zero_reg7;
end if;
end if;
end process UPDT_ZERO_WRD6;
-----------------------------------------------------------------------
-- APP 4 Register (Set to Zero for Non-EOF Descriptor)
-----------------------------------------------------------------------
UPDT_ZERO_WRD7 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_zero_reg7 <= (others => '0');
elsif(sts_received_re = '1')then
updt_zero_reg7 <= DESC_LAST
& '0'
& ZERO_VALUE;
end if;
end if;
end process UPDT_ZERO_WRD7;
-----------------------------------------------------------------------
-- Drive TVALID
-- If writing app then base on stsstrm fifo empty flag
-- If writing datamover status then base simply assert on updt_sts
-----------------------------------------------------------------------
TVALID_MUX : process(writing_app_fields,updt_sts,stsstrm_fifo_empty)
begin
if(updt_sts = '1' and writing_app_fields = '1')then
updtsts_tvalid <= not stsstrm_fifo_empty;
else
updtsts_tvalid <= updt_sts;
end if;
end process TVALID_MUX;
-- Drive TDATA
updtsts_tdata <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0);
-- DRIVE TLAST
updtsts_tlast <= updt_desc_sts(C_S_AXIS_UPDSTS_TDATA_WIDTH);
end generate GEN_DESC_UPDT_STSAPP;
-- Pass out to sg engine
s_axis_s2mm_updtsts_tdata <= updtsts_tdata;
s_axis_s2mm_updtsts_tvalid <= updtsts_tvalid;
s_axis_s2mm_updtsts_tlast <= updtsts_tlast and updtsts_tvalid;
end generate GEN_DESC_UPDT_NO_QUEUE;
end implementation;
| mit | d66355e58b69e418944042ea9a68e317 | 0.438192 | 4.443698 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/builtin/builtin_extdepth_v6.vhd | 19 | 50,137 | `protect begin_protected
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`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect end_protected
| bsd-2-clause | acd8d37ab32e405ba1dfd6325380deff | 0.949758 | 1.822965 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/tagmemcoupled.vhd | 1 | 8,626 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.types_mem.all;
library riverlib;
use riverlib.types_cache.all;
entity tagmemcoupled is generic (
memtech : integer := 0;
async_reset : boolean := false;
abus : integer := 64; -- system bus address bus (32 or 64 bits)
waybits : integer := 2; -- log2 of number of ways bits (=2 for 4 ways)
ibits : integer := 7; -- lines memory addres width (usually 6..8)
lnbits : integer := 5; -- One line bits: log2(bytes_per_line)
flbits : integer := 1 -- Total flags number saved with address tag
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_direct_access : in std_logic;
i_invalidate : in std_logic;
i_re : in std_logic;
i_we : in std_logic;
i_addr : in std_logic_vector(abus-1 downto 0);
i_wdata : in std_logic_vector(8*(2**lnbits)-1 downto 0);
i_wstrb : in std_logic_vector(2**lnbits-1 downto 0);
i_wflags : in std_logic_vector(flbits-1 downto 0);
o_raddr : out std_logic_vector(abus-1 downto 0);
o_rdata : out std_logic_vector(8*(2**lnbits)+15 downto 0);
o_rflags : out std_logic_vector(flbits-1 downto 0);
o_hit : out std_logic;
o_hit_next : out std_logic
);
end;
architecture arch_tagmemcoupled of tagmemcoupled is
constant TAG_START : integer := abus - (ibits + lnbits);
constant EVEN : integer := 0;
constant ODD : integer := 1;
constant MemTotal : integer := 2;
type tagmem_in_type is record
direct_access : std_logic;
invalidate : std_logic;
re : std_logic;
we : std_logic;
addr : std_logic_vector(abus-1 downto 0);
wdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
wstrb : std_logic_vector((2**lnbits)-1 downto 0);
wflags : std_logic_vector(flbits-1 downto 0);
snoop_addr : std_logic_vector(abus-1 downto 0);
end record;
type tagmem_out_type is record
raddr : std_logic_vector(abus-1 downto 0);
rdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
rflags : std_logic_vector(flbits-1 downto 0);
hit : std_logic;
snoop_ready : std_logic;
snoop_flags : std_logic_vector(flbits-1 downto 0);
end record;
type tagmem_in_vector is array (0 to MemTotal-1) of tagmem_in_type;
type tagmem_out_vector is array (0 to MemTotal-1) of tagmem_out_type;
signal r_req_addr : std_logic_vector(abus-1 downto 0);
signal linei : tagmem_in_vector;
signal lineo : tagmem_out_vector;
begin
dx : for i in 0 to MemTotal-1 generate
memx : tagmemnway generic map (
async_reset => async_reset,
memtech => memtech,
abus => abus,
waybits => waybits,
ibits => ibits - 1,
lnbits => lnbits,
flbits => flbits,
snoop => false
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_direct_access => linei(i).direct_access,
i_invalidate => linei(i).invalidate,
i_re => linei(i).re,
i_we => linei(i).we,
i_addr => linei(i).addr,
i_wdata => linei(i).wdata,
i_wstrb => linei(i).wstrb,
i_wflags => linei(i).wflags,
o_raddr => lineo(i).raddr,
o_rdata => lineo(i).rdata,
o_rflags => lineo(i).rflags,
o_hit => lineo(i).hit,
i_snoop_addr => linei(i).snoop_addr,
o_snoop_ready => lineo(i).snoop_ready,
o_snoop_flags => lineo(i).snoop_flags
);
end generate;
comb : process(i_nrst, i_direct_access, i_invalidate, i_re, i_we,
i_addr, i_wstrb, i_wdata, i_wflags,
lineo, r_req_addr)
variable v_addr_sel : std_logic;
variable v_addr_sel_r : std_logic;
variable v_use_overlay : std_logic;
variable v_use_overlay_r : std_logic;
variable vb_index : std_logic_vector(ibits-1 downto 0);
variable vb_index_next : std_logic_vector(ibits-1 downto 0);
variable vb_addr_next : std_logic_vector(abus-1 downto 0);
variable vb_addr_tag_direct : std_logic_vector(abus-1 downto 0);
variable vb_addr_tag_next : std_logic_vector(abus-1 downto 0);
variable vb_raddr_tag : std_logic_vector(abus-1 downto 0);
variable vb_o_raddr : std_logic_vector(abus-1 downto 0);
variable vb_o_rdata : std_logic_vector(8*(2**lnbits)+15 downto 0);
variable v_o_hit : std_logic;
variable v_o_hit_next : std_logic;
variable vb_o_rflags : std_logic_vector(flbits-1 downto 0);
begin
v_addr_sel := i_addr(lnbits);
v_addr_sel_r := r_req_addr(lnbits);
vb_addr_next := i_addr + (2**lnbits);
vb_index := i_addr(ibits+lnbits-1 downto lnbits);
vb_index_next := vb_addr_next(ibits+lnbits-1 downto lnbits);
v_use_overlay := and_reduce(i_addr(lnbits-1 downto 1));
v_use_overlay_r := and_reduce(r_req_addr(lnbits-1 downto 1));
-- Change the bit order in the requested address:
-- [tag][line_idx][odd/evenbit][line_bytes] on
-- [tag][1'b0] [line_idx] [line_bytes]
--
-- Example (abus=32; ibits=7; lnbits=5;):
-- [4:0] byte in line [4:0]
-- [11:5] line index {[1'b0],[11:6]}
-- [31:12] tag [31:12]
vb_addr_tag_direct := i_addr;
vb_addr_tag_direct(ibits + lnbits - 1 downto lnbits) := '0' & vb_index(ibits-1 downto 1);
vb_addr_tag_next := vb_addr_next;
vb_addr_tag_next(ibits + lnbits - 1 downto lnbits) := '0' & vb_index_next(ibits-1 downto 1);
if v_addr_sel = '0' then
linei(EVEN).addr <= vb_addr_tag_direct;
linei(EVEN).wstrb <= i_wstrb;
linei(ODD).addr <= vb_addr_tag_next;
linei(ODD).wstrb <= (others => '0');
else
linei(EVEN).addr <= vb_addr_tag_next;
linei(EVEN).wstrb <= (others => '0');
linei(ODD).addr <= vb_addr_tag_direct;
linei(ODD).wstrb <= i_wstrb;
end if;
linei(EVEN).direct_access <= i_direct_access and ((not v_addr_sel) or v_use_overlay);
linei(ODD).direct_access <= i_direct_access and (v_addr_sel or v_use_overlay);
linei(EVEN).invalidate <= i_invalidate and ((not v_addr_sel) or v_use_overlay);
linei(ODD).invalidate <= i_invalidate and (v_addr_sel or v_use_overlay);
linei(EVEN).re <= i_re and ((not v_addr_sel) or v_use_overlay);
linei(ODD).re <= i_re and (v_addr_sel or v_use_overlay);
linei(EVEN).we <= i_we and ((not v_addr_sel) or v_use_overlay);
linei(ODD).we <= i_we and (v_addr_sel or v_use_overlay);
linei(EVEN).wdata <= i_wdata;
linei(ODD).wdata <= i_wdata;
linei(EVEN).wflags <= i_wflags;
linei(ODD).wflags <= i_wflags;
-- Form output:
if v_addr_sel_r = '0' then
vb_o_rdata := lineo(ODD).rdata(15 downto 0) & lineo(EVEN).rdata;
vb_raddr_tag := lineo(EVEN).raddr;
vb_o_rflags := lineo(EVEN).rflags;
v_o_hit := lineo(EVEN).hit;
if v_use_overlay_r = '0' then
v_o_hit_next := lineo(EVEN).hit;
else
v_o_hit_next := lineo(ODD).hit;
end if;
else
vb_o_rdata := lineo(EVEN).rdata(15 downto 0) & lineo(ODD).rdata;
vb_raddr_tag := lineo(ODD).raddr;
vb_o_rflags := lineo(ODD).rflags;
v_o_hit := lineo(ODD).hit;
if v_use_overlay_r = '0' then
v_o_hit_next := lineo(ODD).hit;
else
v_o_hit_next := lineo(EVEN).hit;
end if;
end if;
vb_o_raddr := vb_raddr_tag;
vb_o_raddr(lnbits) := v_addr_sel_r;
vb_o_raddr(ibits + lnbits - 1 downto lnbits + 1) :=
vb_raddr_tag(ibits + lnbits - 2 downto lnbits);
o_raddr <= vb_o_raddr;
o_rdata <= vb_o_rdata;
o_rflags <= vb_o_rflags;
o_hit <= v_o_hit;
o_hit_next <= v_o_hit_next;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r_req_addr <= (others => '0');
elsif rising_edge(i_clk) then
r_req_addr <= i_addr;
end if;
end process;
end;
| apache-2.0 | c6abb48fea0d8178da331c7932d45260 | 0.601669 | 2.987877 | false | false | false | false |
quicky2000/top_chenillard | chenillard.vhd | 1 | 2,153 | --
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity chenillard is
port(
clk : in std_logic;
reset : in std_logic;
button : in std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic
);
end chenillard;
architecture Behavioral of chenillard is
type state_type is (e1,e2,e3,e4,e5,e6);
signal state,next_state : state_type;
begin
--state register
process(clk,reset)
begin
if reset = '1' then
state <= e1;
elsif rising_edge(clk) then
state <= next_state;
end if;
end process;
--state transition
process(state)
begin
case state is
when e1 => next_state <= e2;
when e2 => next_state <= e3;
when e3 => next_state <= e4;
when e4 => next_state <= e5;
when e5 => next_state <= e6;
when e6 => next_state <= e1;
end case;
end process;
--output function
led1 <= '1' when state = e1 else '0';
led2 <= '1' when state = e2 or state = e6 else '0';
led3 <= '1' when state = e3 or state = e5 else '0';
led4 <= '1' when state = e4 else '0';
end Behavioral;
| gpl-3.0 | f59eead7f81df9e68fa248f2ba08c39a | 0.677659 | 3.218236 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/TEST_CTRL_9P6_50MHZ_SCH/CTRL_9P6_50MHZ.vhd | 2 | 44,032 | -- PROFI_9P6_50MHZ_REC_BYTE
-- PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 17.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_9P6_50MHZ_VHDL is
Port ( InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
-- ERROR_QUIT : in std_logic; --Eingangsvariable, Fehler beenden
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL_COUNT_SWITCH : in std_logic; --Eingangsvariable, Counter wählen
FIRST_BYTE : in std_logic; --Eingangsvariable, Nur immer erstes Byte lesen
CTRL_ERROR : out std_logic; --Ausgangsvariable, Fehler anzeigen
BYTE_OK : out std_logic; --Ausgangsvariable, Byte vollständig
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Vektor >> Normal:(7 downto 0); TEST:(8 downto 0)
PARITY_OK : out std_logic; --Ausgangsvariable, Parität in Ordnung
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_9P6_50MHZ_VHDL;
architecture Behavioral of CTRL_9P6_50MHZ_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
-- ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F, --15
ST_CTRL_10, --16
ST_CTRL_11, --17
ST_CTRL_12, --18
ST_CTRL_13, --19
ST_CTRL_14); --20
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0); -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
signal BIT_VALUE : std_logic; -- Wert aktuelles Bit
signal COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0); --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0); --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0); --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0); --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal LONG_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal LONG_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal InAB_S : std_logic; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal EN_BIT_0 : std_logic; --BIT0
signal EN_BIT_1 : std_logic; --BIT1
signal EN_BIT_2 : std_logic; --BIT2
signal EN_BIT_3 : std_logic; --BIT3
signal EN_BIT_4 : std_logic; --BIT4
signal EN_BIT_5 : std_logic; --BIT5
signal EN_BIT_6 : std_logic; --BIT6
signal EN_BIT_7 : std_logic; --BIT7
signal EN_BIT_8 : std_logic; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0); --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0);
signal CNTT02 : std_logic_vector (15 downto 0);
signal CNTT03 : std_logic_vector (15 downto 0);
signal CNTT04 : std_logic_vector (15 downto 0);
signal CNTT05 : std_logic_vector (15 downto 0);
signal CNTT06 : std_logic_vector (15 downto 0);
signal CNTT07 : std_logic_vector (15 downto 0);
signal CNTT08 : std_logic_vector (15 downto 0);
signal CNTT09 : std_logic_vector (15 downto 0);
signal CNTT10 : std_logic_vector (15 downto 0);
signal CNTT11 : std_logic_vector (15 downto 0);
signal CNTT12 : std_logic_vector (15 downto 0);
signal CNTT13 : std_logic_vector (15 downto 0);
signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
signal TMP01 : std_logic;
signal TMP02 : std_logic;
signal TMP03 : std_logic;
signal TMP10 : std_logic;
signal TMP11 : std_logic;
signal TMP20 : std_logic;
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"EE09";
constant long_CNTT13 : std_logic_vector := x"FA3E";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (InAB, InAB_S, not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, COUNT_L_M, COUNT_S_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, EN_BIT_0, BIT_VALUE) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_VEC(0)<='0';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(0) = 1
BYTE_VEC(0)<='1';
if (EN_BIT_0 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, EN_BIT_1, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_VEC(1)<='0';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(1) = 1
BYTE_VEC(1)<='1';
if (EN_BIT_1 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, EN_BIT_2, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_VEC(2)<='0';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(2) = 1
BYTE_VEC(2)<='1';
if (EN_BIT_2 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, EN_BIT_3, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_VEC(3)<='0';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(3) = 1
BYTE_VEC(3)<='1';
if (EN_BIT_3 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, EN_BIT_4, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_VEC(4)<='0';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(4) = 1
BYTE_VEC(4)<='1';
if (EN_BIT_4 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, EN_BIT_5, BIT_VALUE) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_VEC(5)<='0';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(5) = 1
BYTE_VEC(5)<='1';
if (EN_BIT_5 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, EN_BIT_6, BIT_VALUE) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_VEC(6)<='0';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(6) = 1
BYTE_VEC(6)<='1';
if (EN_BIT_6 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, EN_BIT_7, BIT_VALUE) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_VEC(7)<='0';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(7) = 1
BYTE_VEC(7)<='1';
if (EN_BIT_7 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, EN_BIT_8, BIT_VALUE) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8 = 1 und BIT_VALUE = 1 dann setze BYTE_VEC(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_8 = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, FIRST_BYTE, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13) -- , ERROR_QUIT
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (COUNT_L = CNTS30) --156250
-- if (COUNT >=3)
then
-- VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --n_COUNT < CNTS30
--VAS01
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS01
n_COUNT_L <= COUNT_L+1; -- dieser Zähler wird nicht abgefragt! (Sinnlos?)
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_02; --warte tsyn30 ab
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --n_COUNT < CNTT01
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; --Zaehlschleife
end if;
when ST_CTRL_04 =>
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_00; --Error
end if;
-- when ST_CTRL_05 =>
-- if (ERROR_QUIT = '0') -- Error nicht bestätigt
-- then
-- -- VAS03
-- n_COUNT_L <= x"00000";
-- n_COUNT_S <= COUNT_S+1;
-- EN_BIT_0 <= '0';
-- EN_BIT_1 <= '0';
-- EN_BIT_2 <= '0';
-- EN_BIT_3 <= '0';
-- EN_BIT_4 <= '0';
-- EN_BIT_5 <= '0';
-- EN_BIT_6 <= '0';
-- EN_BIT_7 <= '0';
-- EN_BIT_8 <= '0';
-- BIT_VALUE <= '0';
-- BYTE_OK <= '0';
-- CTRL_ERROR <= '1';
-- n_SV <= ST_CTRL_05; -- Fehlerschleife
-- else --ERROR_QUIT = '1'
-- VAS00
-- n_COUNT_L <= x"00000"; -- Zaehler nullen
-- n_COUNT_S <= x"0000"; -- Zaehler nullen
-- EN_BIT_0 <= '0';
-- EN_BIT_1 <= '0';
-- EN_BIT_2 <= '0';
-- EN_BIT_3 <= '0';
-- EN_BIT_4 <= '0';
-- EN_BIT_5 <= '0';
-- EN_BIT_6 <= '0';
-- EN_BIT_7 <= '0';
-- EN_BIT_8 <= '0';
-- BIT_VALUE <= '0';
-- BYTE_OK <= '0';
-- CTRL_ERROR <= '0';
-- n_SV <= ST_CTRL_00; --Zurueck zum Initialzustand
-- end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if;
when ST_CTRL_0E =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (COUNT_S = CNTT11) --54687
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_10; -- Zustandsuebgergang
else --n_COUNT < CNTT11
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if;
when ST_CTRL_10 =>
if (InAB_S = '0')
then
-- VAS03
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '1';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit; ST_CTRL_05 vorher
else --InAB_S = '1'
-- VAS13
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '1';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_11; --Stoppbit erkannt
end if;
when ST_CTRL_11 =>
if (FIRST_BYTE = '1')
then
-- VAS00
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Stopp nach einem Byte
else --FIRST_BYTE = '0'
-- VAS14
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --kein Stop gesetzt
end if;
when ST_CTRL_12 =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_12; --Zaehlschleife
end if;
when ST_CTRL_13 =>
if (InAB_S = '0') -- Startbit gefunden
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang;
else -- InAB_S = '1'
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_14; --Zaehlschleife Teil 1
end if;
when ST_CTRL_14 =>
if (COUNT_S = CNTT13) --64062
then
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else -- n_COUNT < CNTT13
-- VAS02
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_13; --Zaehlschleife Teil 2
end if;
when others =>
-- VAS00
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_OK <= '0';
CTRL_ERROR <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung
begin
TMP00 <= BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 <= BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 <= BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 <= BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 <= TMP00 xor TMP01;
TMP11 <= TMP02 xor TMP03;
TMP20 <= TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
begin
BYTE_OUT(0) <= BYTE_VEC(0);
BYTE_OUT(1) <= BYTE_VEC(1);
BYTE_OUT(2) <= BYTE_VEC(2);
BYTE_OUT(3) <= BYTE_VEC(3);
BYTE_OUT(4) <= BYTE_VEC(4);
BYTE_OUT(5) <= BYTE_VEC(5);
BYTE_OUT(6) <= BYTE_VEC(6);
BYTE_OUT(7) <= BYTE_VEC(7);
-- BYTE_OUT(8) <= BYTE_VEC(8); --Bit 8 Test, nach Test entfernen
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, DISPL_COUNT_SWITCH, LONG_STATE_SV, LONG_STATE_n_SV, COUNT_L ,COUNT_S) -- Zustandsanzeige
begin
LONG_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
LONG_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= LONG_STATE_SV(0); --Bit0
DISPL1_SV(1) <= LONG_STATE_SV(1); --Bit1
DISPL1_SV(2) <= LONG_STATE_SV(2); --Bit2
DISPL1_SV(3) <= LONG_STATE_SV(3); --Bit3
DISPL2_SV(0) <= LONG_STATE_SV(4); --usw.
DISPL2_SV(1) <= LONG_STATE_SV(5);
DISPL2_SV(2) <= LONG_STATE_SV(6);
DISPL2_SV(3) <= LONG_STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= LONG_STATE_n_SV(0);
DISPL1_n_SV(1) <= LONG_STATE_n_SV(1);
DISPL1_n_SV(2) <= LONG_STATE_n_SV(2);
DISPL1_n_SV(3) <= LONG_STATE_n_SV(3);
DISPL2_n_SV(0) <= LONG_STATE_n_SV(4);
DISPL2_n_SV(1) <= LONG_STATE_n_SV(5);
DISPL2_n_SV(2) <= LONG_STATE_n_SV(6);
DISPL2_n_SV(3) <= LONG_STATE_n_SV(7);
else --Zähler anzeigen
if (DISPL_COUNT_SWITCH ='0')
then --kleinen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_S(0);
DISPL1_n_SV(1) <= COUNT_S(1);
DISPL1_n_SV(2) <= COUNT_S(2);
DISPL1_n_SV(3) <= COUNT_S(3);
DISPL2_n_SV(0) <= COUNT_S(4);
DISPL2_n_SV(1) <= COUNT_S(5);
DISPL2_n_SV(2) <= COUNT_S(6);
DISPL2_n_SV(3) <= COUNT_S(7);
else -- langen Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT_L(0);
DISPL1_n_SV(1) <= COUNT_L(1);
DISPL1_n_SV(2) <= COUNT_L(2);
DISPL1_n_SV(3) <= COUNT_L(3);
DISPL2_n_SV(0) <= COUNT_L(4);
DISPL2_n_SV(1) <= COUNT_L(5);
DISPL2_n_SV(2) <= COUNT_L(6);
DISPL2_n_SV(3) <= COUNT_L(7);
end if;
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral;
| gpl-2.0 | 861cae961fd3815ca88d83266c9a2351 | 0.515511 | 2.526654 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/fmul_d.vhd | 1 | 11,359 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity DoubleMul is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(63 downto 0);
i_b : in std_logic_vector(63 downto 0);
o_res : out std_logic_vector(63 downto 0);
o_illegal_op : out std_logic;
o_overflow : out std_logic;
o_valid : out std_logic;
o_busy : out std_logic
);
end;
architecture arch_DoubleMul of DoubleMul is
component imul53 is generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(52 downto 0);
i_b : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(105 downto 0);
o_shift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic
);
end component;
type RegistersType is record
busy : std_logic;
ena : std_logic_vector(4 downto 0);
a : std_logic_vector(63 downto 0);
b : std_logic_vector(63 downto 0);
result : std_logic_vector(63 downto 0);
zeroA : std_logic;
zeroB : std_logic;
mantA : std_logic_vector(52 downto 0);
mantB : std_logic_vector(52 downto 0);
expAB : std_logic_vector(12 downto 0);
expAlign : std_logic_vector(11 downto 0);
mantAlign : std_logic_vector(104 downto 0);
postShift : std_logic_vector(11 downto 0);
mantPostScale : std_logic_vector(104 downto 0);
nanA : std_logic;
nanB : std_logic;
overflow : std_logic;
illegal_op : std_logic;
end record;
constant R_RESET : RegistersType := (
'0', (others => '0'), -- busy, ena
(others => '0'), (others => '0'), (others => '0'), -- a, b, result
'0', '0', (others => '0'), (others => '0'), -- zeroA, zeroB, mantA, mantB
(others => '0'), (others => '0'), (others => '0'), -- expAB, expAlign, mantAlign
(others => '0'), (others => '0'), -- postShift, mantPostScale
'0', '0', '0', '0' -- nanA, nanB, overflow, illegal_op
);
constant zero11 : std_logic_vector(10 downto 0) := (others => '0');
constant zero63 : std_logic_vector(62 downto 0) := (others => '0');
constant zero105 : std_logic_vector(104 downto 0) := (others => '0');
signal r, rin : RegistersType;
signal w_imul_ena : std_logic;
signal wb_imul_result : std_logic_vector(105 downto 0);
signal wb_imul_shift : std_logic_vector(6 downto 0);
signal w_imul_rdy : std_logic;
signal w_imul_overflow : std_logic;
begin
u_imul53 : imul53 generic map (
async_reset => async_reset
) port map (
i_nrst => i_nrst,
i_clk => i_clk,
i_ena => w_imul_ena,
i_a => r.mantA,
i_b => r.mantB,
o_result => wb_imul_result,
o_shift => wb_imul_shift,
o_rdy => w_imul_rdy,
o_overflow => w_imul_overflow
);
-- registers:
comb : process(i_nrst, i_ena, i_a, i_b, r,
wb_imul_result, wb_imul_shift, w_imul_rdy, w_imul_overflow)
variable v : RegistersType;
variable signA : std_logic;
variable signB : std_logic;
variable mantA : std_logic_vector(52 downto 0);
variable mantB : std_logic_vector(52 downto 0);
variable zeroA : std_logic;
variable zeroB : std_logic;
variable expAB_t : std_logic_vector(11 downto 0);
variable expAB : std_logic_vector(12 downto 0);
variable mantAlign : std_logic_vector(104 downto 0);
variable expAlign_t : std_logic_vector(12 downto 0);
variable expAlign : std_logic_vector(12 downto 0);
variable postShift : std_logic_vector(11 downto 0);
variable mantPostScale : std_logic_vector(104 downto 0);
variable mantShort : std_logic_vector(52 downto 0);
variable tmpMant05 : std_logic_vector(51 downto 0);
variable mantOnes : std_logic;
variable mantEven : std_logic;
variable mant05 : std_logic;
variable rndBit : std_logic;
variable nanA : std_logic;
variable nanB : std_logic;
variable mantZeroA : std_logic;
variable mantZeroB : std_logic;
variable res : std_logic_vector(63 downto 0);
begin
v := r;
v.ena(0) := i_ena and not r.busy;
v.ena(1) := r.ena(0);
v.ena(4 downto 2) := r.ena(3 downto 2) & w_imul_rdy;
if i_ena = '1' then
v.busy := '1';
v.overflow := '0';
v.a := i_a;
v.b := i_b;
end if;
signA := r.a(63);
signB := r.b(63);
zeroA := '0';
if r.a(62 downto 0) = zero63 then
zeroA := '1';
end if;
zeroB := '0';
if r.b(62 downto 0) = zero63 then
zeroB := '1';
end if;
mantA(51 downto 0) := r.a(51 downto 0);
mantA(52) := '0';
if r.a(62 downto 52) /= zero11 then
mantA(52) := '1';
end if;
mantB(51 downto 0) := r.b(51 downto 0);
mantB(52) := '0';
if r.b(62 downto 52) /= zero11 then
mantB(52) := '1';
end if;
-- expA - expB + 1023
expAB_t := ('0' & r.a(62 downto 52)) + ('0' & r.b(62 downto 52));
expAB := ('0' & expAB_t) - 1023;
if r.ena(0) = '1' then
v.expAB := expAB;
v.zeroA := zeroA;
v.zeroB := zeroB;
v.mantA := mantA;
v.mantB := mantB;
end if;
w_imul_ena <= r.ena(1);
-- imul53 module:
mantAlign := (others => '0');
if wb_imul_result(105) = '1' then
mantAlign := wb_imul_result(105 downto 1);
elsif wb_imul_result(104) = '1' then
mantAlign := wb_imul_result(104 downto 0);
else
for i in 1 to 104 loop
if i = conv_integer(wb_imul_shift) then
mantAlign := wb_imul_result(104-i downto 0) & zero105(i-1 downto 0);
end if;
end loop;
end if;
expAlign_t := r.expAB + 1;
if wb_imul_result(105) = '1' then
expAlign := expAlign_t;
elsif r.a(62 downto 52) = zero11 or r.b(62 downto 52) = zero11 then
expAlign := expAlign_t - ("000000" & wb_imul_shift);
else
expAlign := r.expAB - ("000000" & wb_imul_shift);
end if;
-- IMPORTANT exception! new ZERO value
if expAlign(12) = '1' or expAlign = zero63(12 downto 0) then
if wb_imul_shift = "0000000" or wb_imul_result(105) = '1'
or r.a(62 downto 52) = zero11 or r.b(62 downto 52) = zero11 then
postShift := not expAlign(11 downto 0) + 2;
else
postShift := not expAlign(11 downto 0) + 1;
end if;
else
postShift := (others => '0');
end if;
if w_imul_rdy = '1' then
v.expAlign := expAlign(11 downto 0);
v.mantAlign := mantAlign;
v.postShift := postShift;
-- Exceptions:
v.nanA := '0';
if r.a(62 downto 52) = "11111111111" then
v.nanA := '1';
end if;
v.nanB := '0';
if r.b(62 downto 52) = "11111111111" then
v.nanB := '1';
end if;
v.overflow := '0';
if expAlign(12) = '0' and expAlign >= "0011111111111" then
v.overflow := '1';
end if;
end if;
-- Prepare to mantissa post-scale
mantPostScale := (others => '0');
if r.postShift = X"000" then
mantPostScale := r.mantAlign;
elsif r.postShift < conv_std_logic_vector(105, 12) then
for i in 1 to 104 loop
if conv_std_logic_vector(i, 7) = r.postShift(6 downto 0) then
mantPostScale := zero105(i-1 downto 0) & r.mantAlign(104 downto i);
end if;
end loop;
end if;
if r.ena(2) = '1' then
v.mantPostScale := mantPostScale;
end if;
-- Rounding bit
mantShort := r.mantPostScale(104 downto 52);
tmpMant05 := r.mantPostScale(51 downto 0);
mantOnes := '0';
if mantShort(52) = '1' and mantShort(51 downto 0) = X"fffffffffffff" then
mantOnes := '1';
end if;
mantEven := r.mantPostScale(52);
mant05 := '0';
if tmpMant05 = X"8000000000000" then
mant05 := '1';
end if;
rndBit := r.mantPostScale(51) and not(mant05 and not mantEven);
-- Check Borders
nanA := '0';
if r.a(62 downto 52) = "11111111111" then
nanA := '1';
end if;
nanB := '0';
if r.b(62 downto 52) = "11111111111" then
nanB := '1';
end if;
mantZeroA := '0';
if r.a(51 downto 0) = zero63(51 downto 0) then
mantZeroA := '1';
end if;
mantZeroB := '0';
if r.b(51 downto 0) = zero63(51 downto 0) then
mantZeroB := '1';
end if;
-- Result multiplexers:
if (nanA and mantZeroA and r.zeroB) = '1' or (nanB and mantZeroB and r.zeroA) = '1' then
res(63) := '1';
elsif (nanA and not mantZeroA) = '1' then
-- when both values are NaN, value B has higher priority if sign=1
res(63) := signA or (nanA and signB);
elsif (nanB and not mantZeroB) = '1' then
res(63) := signB;
else
res(63) := r.a(63) xor r.b(63);
end if;
if nanA = '1' then
res(62 downto 52) := r.a(62 downto 52);
elsif nanB = '1' then
res(62 downto 52) := r.b(62 downto 52);
elsif (r.expAlign(11) or r.zeroA or r.zeroB) = '1' then
res(62 downto 52) := (others => '0');
elsif r.overflow = '1' then
res(62 downto 52) := (others => '1');
else
res(62 downto 52) := r.expAlign(10 downto 0)
+ (mantOnes and rndBit and not r.overflow);
end if;
if (nanA and mantZeroA and not mantZeroB) = '1'
or (nanB and mantZeroB and not mantZeroA) = '1'
or (not nanA and not nanB and r.overflow) = '1' then
res(51 downto 0) := (others => '0');
elsif (nanA and not (nanB and signB)) = '1' then
-- when both values are NaN, value B has higher priority if sign=1
res(51) := '1';
res(50 downto 0) := r.a(50 downto 0);
elsif nanB = '1' then
res(51) := '1';
res(50 downto 0) := r.b(50 downto 0);
else
res(51 downto 0) := mantShort(51 downto 0) + rndBit;
end if;
if r.ena(3) = '1' then
v.result := res;
v.illegal_op := nanA or nanB;
v.busy := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_res <= r.result;
o_illegal_op <= r.illegal_op;
o_overflow <= r.overflow;
o_valid <= r.ena(4);
o_busy <= r.busy;
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | a2e69fe2791f51459669f94821195146 | 0.559996 | 3.151776 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/tap_uart.vhd | 1 | 9,886 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity uart_tap is
port (
nrst : in std_logic;
clk : in std_logic;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_msti : in axi4_master_in_type;
o_msto : out axi4_master_out_type;
o_mstcfg : out axi4_master_config_type
);
end;
architecture arch_uart_tap of uart_tap is
constant MAGIC_ID : std_logic_vector(7 downto 0) := X"31";
constant SCALER_DEFAULT : std_logic_vector(17 downto 0) := "111111111111111011";
constant BAUD_DEFAULT : std_logic_vector(17 downto 0) := (others => '1');
constant HANDSHAKE_ACK : std_logic_vector(31 downto 0) := X"0a4b4341";
constant xmstconfig : axi4_master_config_type := (
descrsize => PNP_CFG_MASTER_DESCR_BYTES,
descrtype => PNP_CFG_TYPE_MASTER,
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_UART_TAP
);
type uart_state_type is (idle, startbit, data, stopbit);
type dma_req_state_type is (
DMAREQ_IDLE,
DMAREQ_OPERATION,
DMAREQ_ADDR,
DMAREQ_READ,
DMAREQ_WAIT_READ_RESP,
DMAREQ_UART_TX,
DMAREQ_WDATA,
DMAREQ_WRITE
);
type registers is record
dma : dma_bank_type;
tx_data : std_logic_vector(31 downto 0);
tx_byte_cnt : integer range 0 to 4;
dma_req_state : dma_req_state_type;
dma_state_next : dma_req_state_type;
dma_req_write : std_logic;
dma_byte_cnt : integer range 0 to 7;
dma_req_len : integer range 0 to 63;
dma_req_addr : std_logic_vector(63 downto 0);
dma_req_wdata : std_logic_vector(31 downto 0);
rword_valid : std_logic;
rword : std_logic_vector(31 downto 0);
watchdog : integer;
end record;
signal r, rin : registers;
signal dma_response : dma_response_type;
signal w_com_dready : std_logic; -- new byte is avaiable for read
signal w_com_accepted : std_logic; -- new byte can be accepted;
signal wb_com_data : std_logic_vector(7 downto 0);
signal w_com_thempty : std_logic; -- transmitter's hold register is empty
signal w_com_write : std_logic;
component dcom_uart is
port (
rst : in std_ulogic;
clk : in std_ulogic;
i_cfg_frame : in std_logic;
i_cfg_ovf : in std_logic;
i_cfg_break : in std_logic;
i_cfg_tcnt : in std_logic_vector(1 downto 0);
i_cfg_rxen : in std_logic;
i_cfg_brate : in std_logic_vector(17 downto 0);
i_cfg_scaler : in std_logic_vector(17 downto 0);
o_cfg_scaler : out std_logic_vector(31 downto 0);
o_cfg_rxen : out std_logic;
o_cfg_txen : out std_logic;
o_cfg_flow : out std_logic;
i_com_read : in std_ulogic;
i_com_write : in std_ulogic;
i_com_data : in std_logic_vector(7 downto 0);
o_com_dready : out std_ulogic;
o_com_tsempty : out std_ulogic;
o_com_thempty : out std_ulogic;
o_com_lock : out std_ulogic;
o_com_enable : out std_ulogic;
o_com_data : out std_logic_vector(7 downto 0);
ui : in uart_in_type;
uo : out uart_out_type
);
end component;
begin
comblogic : process(nrst, i_msti, i_uart, r, dma_response, w_com_dready,
wb_com_data, w_com_thempty)
variable v : registers;
variable wb_dma_request : dma_request_type;
variable wb_dma_response : dma_response_type;
variable wb_msto : axi4_master_out_type;
variable v_com_write : std_logic;
variable v_com_accepted : std_logic;
begin
v := r;
wb_dma_request.valid := '0';
wb_dma_request.ready := '0';
wb_dma_request.write := '0';
wb_dma_request.addr := (others => '0');
wb_dma_request.size := "010"; -- 4 bytes
wb_dma_request.bytes := (others => '0');
wb_dma_request.wdata := (others => '0');
v_com_accepted := '0';
v_com_write := '0';
--! DMA control
case r.dma_req_state is
when DMAREQ_IDLE =>
v_com_accepted := '1';
if w_com_dready = '1' and wb_com_data = MAGIC_ID then
v.dma_req_state := DMAREQ_OPERATION;
end if;
when DMAREQ_OPERATION =>
v_com_accepted := '1';
if w_com_dready = '1' then
v.dma_req_write := wb_com_data(6);
v.dma_req_len := conv_integer(wb_com_data(5 downto 0));
v.dma_req_state := DMAREQ_ADDR;
v.dma_byte_cnt := 0;
end if;
when DMAREQ_ADDR =>
v_com_accepted := '1';
if w_com_dready = '1' then
v.dma_req_addr := wb_com_data & r.dma_req_addr(63 downto 8);
if r.dma_byte_cnt = 7 then
if (wb_com_data & r.dma_req_addr(63 downto 40)) /= X"00000000" then
v.dma_req_state := DMAREQ_IDLE;
elsif r.dma_req_write = '1' then
v.dma_req_state := DMAREQ_WDATA;
v.dma_byte_cnt := 0;
else
v.dma_req_state := DMAREQ_READ;
end if;
else
v.dma_byte_cnt := r.dma_byte_cnt + 1;
end if;
end if;
when DMAREQ_READ =>
wb_dma_request.valid := '1';
wb_dma_request.write := '0';
wb_dma_request.addr := r.dma_req_addr(CFG_SYSBUS_ADDR_BITS-1 downto 0);
wb_dma_request.bytes := conv_std_logic_vector(4, 11);
wb_dma_request.wdata := (others => '0');
if dma_response.ready = '1' then
v.dma_req_state := DMAREQ_WAIT_READ_RESP;
end if;
when DMAREQ_WAIT_READ_RESP =>
wb_dma_request.ready := '1';
if dma_response.valid = '1' then
v.dma_req_state := DMAREQ_UART_TX;
v.tx_data := dma_response.rdata(31 downto 0);
v.tx_byte_cnt := 4;
if r.dma_req_len = 0 then
v.dma_state_next := DMAREQ_IDLE;
else
v.dma_req_len := r.dma_req_len - 1;
v.dma_req_addr := r.dma_req_addr + 4;
v.dma_state_next := DMAREQ_READ;
end if;
end if;
when DMAREQ_WDATA =>
v_com_accepted := '1';
if w_com_dready = '1' then
v.dma_req_wdata := wb_com_data & r.dma_req_wdata(31 downto 8);
v.dma_byte_cnt := r.dma_byte_cnt + 1;
if r.dma_byte_cnt = 3 then
v.dma_req_state := DMAREQ_WRITE;
end if;
end if;
when DMAREQ_WRITE =>
wb_dma_request.valid := '1';
wb_dma_request.write := '1';
wb_dma_request.addr := r.dma_req_addr(CFG_SYSBUS_ADDR_BITS-1 downto 0);
wb_dma_request.bytes := conv_std_logic_vector(4, 11);
wb_dma_request.wdata := r.dma_req_wdata & r.dma_req_wdata;
if dma_response.ready = '1' then
if r.dma_req_len = 0 then
v.dma_req_state := DMAREQ_UART_TX; -- Handshake ACK
v.tx_data := HANDSHAKE_ACK;
v.tx_byte_cnt := 4;
v.dma_state_next := DMAREQ_IDLE;
else
v.dma_byte_cnt := 0;
v.dma_req_len := r.dma_req_len - 1;
v.dma_req_addr := r.dma_req_addr + 4;
v.dma_req_state := DMAREQ_WDATA;
end if;
end if;
when DMAREQ_UART_TX =>
v_com_write := '1';
if r.tx_byte_cnt = 0 then
v.dma_req_state := r.dma_state_next;
elsif w_com_thempty = '1' then
v.tx_byte_cnt := r.tx_byte_cnt - 1;
v.tx_data := X"00" & r.tx_data(31 downto 8);
end if;
when others =>
end case;
procedureAxi4DMA(
i_request => wb_dma_request,
o_response => wb_dma_response,
i_bank => r.dma,
o_bank => v.dma,
i_msti => i_msti,
o_msto => wb_msto
);
dma_response <= wb_dma_response;
w_com_accepted <= v_com_accepted;
w_com_write <= v_com_write;
if nrst = '0' then
v.tx_byte_cnt := 0;
v.tx_data := (others => '0');
v.dma := DMA_BANK_RESET;
v.dma_req_state := DMAREQ_IDLE;
v.dma_state_next := DMAREQ_IDLE;
v.dma_req_write := '0';
v.dma_byte_cnt := 0;
v.dma_req_len := 0;
v.dma_req_addr := (others => '0');
v.dma_req_wdata := (others => '0');
end if;
rin <= v;
o_msto <= wb_msto;
end process;
o_mstcfg <= xmstconfig;
dcom0 : dcom_uart port map (
rst => nrst,
clk => clk,
i_cfg_frame => '0',
i_cfg_ovf => '0',
i_cfg_break => '0',
i_cfg_tcnt => "00",
i_cfg_rxen => '0',
i_cfg_brate => BAUD_DEFAULT,
i_cfg_scaler => SCALER_DEFAULT,
o_cfg_scaler => open,
o_cfg_rxen => open,
o_cfg_txen => open,
o_cfg_flow => open,
i_com_read => w_com_accepted,
i_com_write => w_com_write,
i_com_data => r.tx_data(7 downto 0),
o_com_dready => w_com_dready,
o_com_tsempty => open,
o_com_thempty => w_com_thempty,
o_com_lock => open,
o_com_enable => open,
o_com_data => wb_com_data,
ui => i_uart,
uo => o_uart
);
-- registers:
regs : process(clk)
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end; | apache-2.0 | 956d703c7773f2b855b14571f0be392d | 0.559175 | 3.130462 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/pll/clkp90_k7.vhd | 3 | 4,258 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Clock phase offset generator (90 deg) for Kintex7 FPGA.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity clkp90_kintex7 is
generic (
freq : integer := 125000
);
port (
--! Active High
i_rst : in std_logic;
i_clk : in std_logic;
o_clk : out std_logic;
o_clkp90 : out std_logic;
o_clk2x : out std_logic;
o_lock : out std_logic
);
end clkp90_kintex7;
architecture rtl of clkp90_kintex7 is
constant clk_mul : integer := 8;
constant clk_div : integer := 8;
constant period : real := 1000000.0/real(freq);
constant clkio_div : integer := freq*clk_mul/200000;
signal CLKFBOUT : std_logic;
signal CLKFBIN : std_logic;
signal clk_nobuf : std_logic;
signal clk90_nobuf : std_logic;
signal clkio_nobuf : std_logic;
begin
CLKFBIN <= CLKFBOUT;
PLLE2_ADV_inst : PLLE2_ADV generic map (
BANDWIDTH => "OPTIMIZED", -- OPTIMIZED, HIGH, LOW
CLKFBOUT_MULT => clk_mul, -- Multiply value for all CLKOUT, (2-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of CLKFB, (-360.000-360.000).
-- CLKIN_PERIOD: Input clock period in nS to ps resolution (i.e. 33.333 is 30 MHz).
CLKIN1_PERIOD => period,
CLKIN2_PERIOD => 0.0,
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT (1-128)
CLKOUT0_DIVIDE => clk_div,
CLKOUT1_DIVIDE => clk_div,
CLKOUT2_DIVIDE => clkio_div,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT outputs (0.001-0.999).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for CLKOUT outputs (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 90.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
COMPENSATION => "ZHOLD", -- ZHOLD, BUF_IN, EXTERNAL, INTERNAL
DIVCLK_DIVIDE => 1, -- Master division value (1-56)
-- REF_JITTER: Reference input jitter in UI (0.000-0.999).
REF_JITTER1 => 0.0,
REF_JITTER2 => 0.0,
STARTUP_WAIT => "TRUE" -- Delay DONE until PLL Locks, ("TRUE"/"FALSE")
) port map (
-- Clock Outputs: 1-bit (each) output: User configurable clock outputs
CLKOUT0 => clk_nobuf,
CLKOUT1 => clk90_nobuf,
CLKOUT2 => clkio_nobuf,
CLKOUT3 => OPEN,
CLKOUT4 => OPEN,
CLKOUT5 => OPEN,
-- DRP Ports: 16-bit (each) output: Dynamic reconfigration ports
DO => OPEN,
DRDY => OPEN,
-- Feedback Clocks: 1-bit (each) output: Clock feedback ports
CLKFBOUT => CLKFBOUT,
-- Status Ports: 1-bit (each) output: PLL status ports
LOCKED => o_lock,
-- Clock Inputs: 1-bit (each) input: Clock inputs
CLKIN1 => i_clk,
CLKIN2 => '0',
-- Con trol Ports: 1-bit (each) input: PLL control ports
CLKINSEL => '1',
PWRDWN => '0',
RST => i_rst,
-- DRP Ports: 7-bit (each) input: Dynamic reconfigration ports
DADDR => "0000000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
-- Feedback Clocks: 1-bit (each) input: Clock feedback ports
CLKFBIN => CLKFBIN
);
bufgclk0 : BUFG port map (I => clk_nobuf, O => o_clk);
bufgclk90 : BUFG port map (I => clk90_nobuf, O => o_clkp90);
bufgclkio : BUFG port map (I => clkio_nobuf, O => o_clk2x);
end;
| apache-2.0 | 405a9678f463d4533be3c92a7382a57f | 0.537576 | 3.645548 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/PROFIBUS_MONITOR/CTRL_BIT_REGISTER.vhd | 4 | 17,316 | -- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 25.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BIT_REGISTER is
Port (EN_BIT_i : in std_logic_vector (8 downto 0); --Eingangsvariable, Einschalten des Bitregisters i
BIT_VALUE : in std_logic; -- Eingangsvariable, Wert des aktuellen Bits
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Byte, 8bit, Vektor
PARITY_OK : out std_logic; --Ausgangsvariable, Parität i.O.
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BIT_REGISTER;
architecture Behavioral of CTRL_BIT_REGISTER is
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0 := ST_BR_EN_BIT0_0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0 := ST_BR_EN_BIT0_0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0 := ST_BR_EN_BIT0_0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1 := ST_BR_EN_BIT1_0; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1 := ST_BR_EN_BIT1_0; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1 := ST_BR_EN_BIT1_0; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2 := ST_BR_EN_BIT2_0; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2 := ST_BR_EN_BIT2_0; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2 := ST_BR_EN_BIT2_0; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3 := ST_BR_EN_BIT3_0; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3 := ST_BR_EN_BIT3_0; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3 := ST_BR_EN_BIT3_0; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4 := ST_BR_EN_BIT4_0; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4 := ST_BR_EN_BIT4_0; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4 := ST_BR_EN_BIT4_0; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5 := ST_BR_EN_BIT5_0; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5 := ST_BR_EN_BIT5_0; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5 := ST_BR_EN_BIT5_0; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6 := ST_BR_EN_BIT6_0; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6 := ST_BR_EN_BIT6_0; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6 := ST_BR_EN_BIT6_0; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7 := ST_BR_EN_BIT7_0; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7 := ST_BR_EN_BIT7_0; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7 := ST_BR_EN_BIT7_0; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8 := ST_BR_EN_BIT8_0; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8 := ST_BR_EN_BIT8_0; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8 := ST_BR_EN_BIT8_0; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0) := b"000000000"; -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
--signal not_CLK : std_logic; --negierte Taktvariable
--signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
--signal TMP01 : std_logic;
--signal TMP02 : std_logic;
--signal TMP03 : std_logic;
--signal TMP10 : std_logic;
--signal TMP11 : std_logic;
--signal TMP20 : std_logic;
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, CLK) --Master
begin
if (RESET ='1')
then SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
else
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, CLK) --Slave
begin
if (RESET = '1')
then SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if falling_edge(CLK)
then
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_OUT(0)<='0';
BYTE_VEC(0)<='0';
if (EN_BIT_i(0) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(0) = 1
BYTE_OUT(0)<='1';
BYTE_VEC(0)<='1';
if (EN_BIT_i(0) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_OUT(1)<='0';
BYTE_VEC(1)<='0';
if (EN_BIT_i(1) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(1) = 1
BYTE_OUT(1)<='1';
BYTE_VEC(1)<='1';
if (EN_BIT_i(1) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_OUT(2)<='0';
BYTE_VEC(2)<='0';
if (EN_BIT_i(2) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(2) = 1
BYTE_OUT(2)<='1';
BYTE_VEC(2)<='1';
if (EN_BIT_i(2) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_OUT(3)<='0';
BYTE_VEC(3)<='0';
if (EN_BIT_i(3) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(3) = 1
BYTE_OUT(3)<='1';
BYTE_VEC(3)<='1';
if (EN_BIT_i(3) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_OUT(4)<='0';
BYTE_VEC(4)<='0';
if (EN_BIT_i(4) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(4) = 1
BYTE_OUT(4)<='1';
BYTE_VEC(4)<='1';
if (EN_BIT_i(4) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_OUT(5)<='0';
BYTE_VEC(5)<='0';
if (EN_BIT_i(5) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(5) = 1
BYTE_OUT(5)<='1';
BYTE_VEC(5)<='1';
if (EN_BIT_i(5) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_OUT(6)<='0';
BYTE_VEC(6)<='0';
if (EN_BIT_i(6) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(6) = 1
BYTE_OUT(6)<='1';
BYTE_VEC(6)<='1';
if (EN_BIT_i(6) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_OUT(7)<='0';
BYTE_VEC(7)<='0';
if (EN_BIT_i(7) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(7) = 1
BYTE_OUT(7)<='1';
BYTE_VEC(7)<='1';
if (EN_BIT_i(7) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_i(8) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_i(8) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung (Mit VARIABLEN := , STATT SIGNALEN <=)
variable TMP00, TMP01, TMP02, TMP03, TMP10, TMP11, TMP20 : std_logic;
begin
TMP00 := BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 := BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 := BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 := BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 := TMP00 xor TMP01;
TMP11 := TMP02 xor TMP03;
TMP20 := TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
--BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
-- begin
-- BYTE_OUT(0) <= BYTE_VEC(0);
-- BYTE_OUT(1) <= BYTE_VEC(1);
-- BYTE_OUT(2) <= BYTE_VEC(2);
-- BYTE_OUT(3) <= BYTE_VEC(3);
-- BYTE_OUT(4) <= BYTE_VEC(4);
-- BYTE_OUT(5) <= BYTE_VEC(5);
-- BYTE_OUT(6) <= BYTE_VEC(6);
-- BYTE_OUT(7) <= BYTE_VEC(7);
--end process;
end Behavioral;
| gpl-2.0 | 553c8239073c39d71c521aa11ea7b83e | 0.578251 | 2.418098 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/ram_tech.vhd | 1 | 1,894 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
entity ram_tech is generic (
memtech : integer := 0;
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_addr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture rtl of ram_tech is
component ram_inferred is
generic (
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_addr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end component;
begin
inf0 : if memtech = inferred or is_fpga(memtech) /= 0 generate
x0 : ram_inferred generic map
(
abits => abits,
dbits => dbits
) port map (
i_clk => i_clk,
i_addr => i_addr,
o_rdata => o_rdata,
i_wena => i_wena,
i_wdata => i_wdata
);
end generate;
end;
| apache-2.0 | 89abb82acb517390dbd7da47876fd97a | 0.631468 | 3.507407 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/iobuf_virtex6.vhd | 3 | 762 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief IO buffer for fpga virtex6.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity iobuf_virtex6 is
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end;
architecture rtl of iobuf_virtex6 is
begin
io_inst : IOBUF generic map
(
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW"
) port map
(
O => o,
IO => io,
I => i,
T => t
);
end;
| apache-2.0 | 8d65bc96080b1c9644c075f7514561af | 0.467192 | 3.96875 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/bufgmux_tech.vhd | 1 | 1,679 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual clock multiplexer with buffered output.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity bufgmux_tech is
generic
(
tech : integer := 0;
rf_frontend_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end;
architecture rtl of bufgmux_tech is
component bufgmux_fpga is
generic (
rf_frontend_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end component;
component bufgmux_micron180 is
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic
);
end component;
begin
inf : if tech = inferred generate
O <= I1 when S = '0' else I2;
end generate;
xlnx : if tech = virtex6 or tech = kintex7 generate
mux_buf : bufgmux_fpga generic map (
rf_frontend_ena => rf_frontend_ena
) port map (
O => O,
I1 => I1,
I2 => I2,
S => S
);
end generate;
mic0 : if tech = mikron180 generate
mux_buf : bufgmux_micron180
port map (
O => O,
I1 => I1,
I2 => I2,
S => S
);
end generate;
end;
| apache-2.0 | f03aa8791d771d0795537ba4c3189c03 | 0.484217 | 3.790068 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_pntr.vhd | 1 | 22,062 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
ch2_eof_detected : in std_logic ; --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
tail_updt : in std_logic;
tail_updt_latch : out std_logic;
ch2_updt_done : in std_logic;
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic ; --
bd_eq : out std_logic
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal first : std_logic;
signal eof_latch : std_logic;
signal ch2_sg_idle_int : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch1_fetch_address <= ch1_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif((ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0'))then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
-- Addresses are always 16 word 32-bit aligned
ch2_fetch_address <= ch2_fetch_address_i (C_M_AXI_SG_ADDR_WIDTH-1 downto 6) & "000000";
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1' or ch2_eof_detected = '1')then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
ch2_sg_idle_int <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
ch2_sg_idle_int <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
-- Needed for multi channel
EOF_LATCH_PROC : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_taildesc_wren = '1' or eof_latch = '1')then -- nned to have some reset condition here
eof_latch <= '0';
elsif (ch2_sg_idle_int = '1' and ch2_updt_done = '1') then
eof_latch <= '1';
end if;
end if;
end process EOF_LATCH_PROC;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or eof_latch = '1')then -- nned to have some reset condition here
tail_updt_latch <= '0';
first <= '0';
elsif (tail_updt = '1') then
tail_updt_latch <= '0';
elsif(ch2_taildesc_wren = '1' and first = '0')then
first <= '1';
elsif(ch2_taildesc_wren = '1' and first = '1')then
tail_updt_latch <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
EQUAL_BD : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
bd_eq <= '0';
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
bd_eq <= '0';
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
bd_eq <= '1';
end if;
end if;
end process EQUAL_BD;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
tail_updt_latch <= '0';
bd_eq <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
| mit | 1653c29e5926f7b342860f52cd666dd9 | 0.41814 | 4.808631 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/CTRL_BIT_REGISTER/CTRL_BIT_REGISTER.vhd | 4 | 17,447 | -- CTRL_BIT_REGISTER
-- Einlesen der einzelnen Werte für bestimmte Bits, Berechung der Parität und Ausgabe als Byte
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 08.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 25.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_BIT_REGISTER is
Port (EN_BIT_i : in std_logic_vector (8 downto 0); --Eingangsvariable, Einschalten des Bitregisters i
BIT_VALUE : in std_logic; -- Eingangsvariable, Wert des aktuellen Bits
BYTE_OUT : out std_logic_vector (7 downto 0); --Ausgangsvariable, Byte, 8bit, Vektor
PARITY_OK : out std_logic; --Ausgangsvariable, Parität i.O.
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_BIT_REGISTER;
architecture Behavioral of CTRL_BIT_REGISTER is
type TYPE_STATE_BR_BIT0 is
(ST_BR_EN_BIT0_0, --Zustaende BIT_REGISTER BIT0
ST_BR_EN_BIT0_1);
type TYPE_STATE_BR_BIT1 is
(ST_BR_EN_BIT1_0, --Zustaende BIT_REGISTER BIT1
ST_BR_EN_BIT1_1);
type TYPE_STATE_BR_BIT2 is
(ST_BR_EN_BIT2_0, --Zustaende BIT_REGISTER BIT2
ST_BR_EN_BIT2_1);
type TYPE_STATE_BR_BIT3 is
(ST_BR_EN_BIT3_0, --Zustaende BIT_REGISTER BIT3
ST_BR_EN_BIT3_1);
type TYPE_STATE_BR_BIT4 is
(ST_BR_EN_BIT4_0, --Zustaende BIT_REGISTER BIT4
ST_BR_EN_BIT4_1);
type TYPE_STATE_BR_BIT5 is
(ST_BR_EN_BIT5_0, --Zustaende BIT_REGISTER BIT5
ST_BR_EN_BIT5_1);
type TYPE_STATE_BR_BIT6 is
(ST_BR_EN_BIT6_0, --Zustaende BIT_REGISTER BIT6
ST_BR_EN_BIT6_1);
type TYPE_STATE_BR_BIT7 is
(ST_BR_EN_BIT7_0, --Zustaende BIT_REGISTER BIT7
ST_BR_EN_BIT7_1);
type TYPE_STATE_BR_BIT8 is
(ST_BR_EN_BIT8_0, --Zustaende BIT_REGISTER BIT8
ST_BR_EN_BIT8_1);
signal SV_BR_BIT0 : TYPE_STATE_BR_BIT0 := ST_BR_EN_BIT0_0; --Zustandsvariable BIT_REGSITER BIT0
signal n_SV_BR_BIT0: TYPE_STATE_BR_BIT0 := ST_BR_EN_BIT0_0; --Zustandsvariable BIT_REGSITER BIT0, neuer Wert
signal SV_BR_BIT0_M: TYPE_STATE_BR_BIT0 := ST_BR_EN_BIT0_0; --Zustandsvariable BIT_REGSITER BIT0, Ausgang Master
signal SV_BR_BIT1 : TYPE_STATE_BR_BIT1 := ST_BR_EN_BIT1_0; --Zustandsvariable BIT_REGSITER BIT1
signal n_SV_BR_BIT1: TYPE_STATE_BR_BIT1 := ST_BR_EN_BIT1_0; --Zustandsvariable BIT_REGSITER BIT1, neuer Wert
signal SV_BR_BIT1_M: TYPE_STATE_BR_BIT1 := ST_BR_EN_BIT1_0; --Zustandsvariable BIT_REGSITER BIT1, Ausgang Master
signal SV_BR_BIT2 : TYPE_STATE_BR_BIT2 := ST_BR_EN_BIT2_0; --Zustandsvariable BIT_REGSITER BIT2
signal n_SV_BR_BIT2: TYPE_STATE_BR_BIT2 := ST_BR_EN_BIT2_0; --Zustandsvariable BIT_REGSITER BIT2, neuer Wert
signal SV_BR_BIT2_M: TYPE_STATE_BR_BIT2 := ST_BR_EN_BIT2_0; --Zustandsvariable BIT_REGSITER BIT2, Ausgang Master
signal SV_BR_BIT3 : TYPE_STATE_BR_BIT3 := ST_BR_EN_BIT3_0; --Zustandsvariable BIT_REGSITER BIT3
signal n_SV_BR_BIT3: TYPE_STATE_BR_BIT3 := ST_BR_EN_BIT3_0; --Zustandsvariable BIT_REGSITER BIT3, neuer Wert
signal SV_BR_BIT3_M: TYPE_STATE_BR_BIT3 := ST_BR_EN_BIT3_0; --Zustandsvariable BIT_REGSITER BIT3, Ausgang Master
signal SV_BR_BIT4 : TYPE_STATE_BR_BIT4 := ST_BR_EN_BIT4_0; --Zustandsvariable BIT_REGSITER BIT4
signal n_SV_BR_BIT4: TYPE_STATE_BR_BIT4 := ST_BR_EN_BIT4_0; --Zustandsvariable BIT_REGSITER BIT4, neuer Wert
signal SV_BR_BIT4_M: TYPE_STATE_BR_BIT4 := ST_BR_EN_BIT4_0; --Zustandsvariable BIT_REGSITER BIT4, Ausgang Master
signal SV_BR_BIT5 : TYPE_STATE_BR_BIT5 := ST_BR_EN_BIT5_0; --Zustandsvariable BIT_REGSITER BIT5
signal n_SV_BR_BIT5: TYPE_STATE_BR_BIT5 := ST_BR_EN_BIT5_0; --Zustandsvariable BIT_REGSITER BIT5, neuer Wert
signal SV_BR_BIT5_M: TYPE_STATE_BR_BIT5 := ST_BR_EN_BIT5_0; --Zustandsvariable BIT_REGSITER BIT5, Ausgang Master
signal SV_BR_BIT6 : TYPE_STATE_BR_BIT6 := ST_BR_EN_BIT6_0; --Zustandsvariable BIT_REGSITER BIT6
signal n_SV_BR_BIT6: TYPE_STATE_BR_BIT6 := ST_BR_EN_BIT6_0; --Zustandsvariable BIT_REGSITER BIT6, neuer Wert
signal SV_BR_BIT6_M: TYPE_STATE_BR_BIT6 := ST_BR_EN_BIT6_0; --Zustandsvariable BIT_REGSITER BIT6, Ausgang Master
signal SV_BR_BIT7 : TYPE_STATE_BR_BIT7 := ST_BR_EN_BIT7_0; --Zustandsvariable BIT_REGSITER BIT7
signal n_SV_BR_BIT7: TYPE_STATE_BR_BIT7 := ST_BR_EN_BIT7_0; --Zustandsvariable BIT_REGSITER BIT7, neuer Wert
signal SV_BR_BIT7_M: TYPE_STATE_BR_BIT7 := ST_BR_EN_BIT7_0; --Zustandsvariable BIT_REGSITER BIT7, Ausgang Master
signal SV_BR_BIT8 : TYPE_STATE_BR_BIT8 := ST_BR_EN_BIT8_0; --Zustandsvariable BIT_REGSITER BIT8
signal n_SV_BR_BIT8: TYPE_STATE_BR_BIT8 := ST_BR_EN_BIT8_0; --Zustandsvariable BIT_REGSITER BIT8, neuer Wert
signal SV_BR_BIT8_M: TYPE_STATE_BR_BIT8 := ST_BR_EN_BIT8_0; --Zustandsvariable BIT_REGSITER BIT8, Ausgang Master
signal BYTE_VEC : std_logic_vector (8 downto 0) := b"000000000"; -- Vektor, BIT_REGSITER, vor Auswertung der Checksume
--signal not_CLK : std_logic; --negierte Taktvariable
--signal TMP00 : std_logic; --temporärer Zwischenwert, Paritätsprüfung
--signal TMP01 : std_logic;
--signal TMP02 : std_logic;
--signal TMP03 : std_logic;
--signal TMP10 : std_logic;
--signal TMP11 : std_logic;
--signal TMP20 : std_logic;
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV_BR_BIT0, n_SV_BR_BIT1, n_SV_BR_BIT2, n_SV_BR_BIT3, n_SV_BR_BIT4, n_SV_BR_BIT5, n_SV_BR_BIT6, n_SV_BR_BIT7, n_SV_BR_BIT8, CLK) --Master
begin
if (RESET ='1')
then SV_BR_BIT0_M <= ST_BR_EN_BIT0_0;
SV_BR_BIT1_M <= ST_BR_EN_BIT1_0;
SV_BR_BIT2_M <= ST_BR_EN_BIT2_0;
SV_BR_BIT3_M <= ST_BR_EN_BIT3_0;
SV_BR_BIT4_M <= ST_BR_EN_BIT4_0;
SV_BR_BIT5_M <= ST_BR_EN_BIT5_0;
SV_BR_BIT6_M <= ST_BR_EN_BIT6_0;
SV_BR_BIT7_M <= ST_BR_EN_BIT7_0;
SV_BR_BIT8_M <= ST_BR_EN_BIT8_0;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_BR_BIT0_M <= n_SV_BR_BIT0;
SV_BR_BIT1_M <= n_SV_BR_BIT1;
SV_BR_BIT2_M <= n_SV_BR_BIT2;
SV_BR_BIT3_M <= n_SV_BR_BIT3;
SV_BR_BIT4_M <= n_SV_BR_BIT4;
SV_BR_BIT5_M <= n_SV_BR_BIT5;
SV_BR_BIT6_M <= n_SV_BR_BIT6;
SV_BR_BIT7_M <= n_SV_BR_BIT7;
SV_BR_BIT8_M <= n_SV_BR_BIT8;
else
SV_BR_BIT0_M <= SV_BR_BIT0_M;
SV_BR_BIT1_M <= SV_BR_BIT1_M;
SV_BR_BIT2_M <= SV_BR_BIT2_M;
SV_BR_BIT3_M <= SV_BR_BIT3_M;
SV_BR_BIT4_M <= SV_BR_BIT4_M;
SV_BR_BIT5_M <= SV_BR_BIT5_M;
SV_BR_BIT6_M <= SV_BR_BIT6_M;
SV_BR_BIT7_M <= SV_BR_BIT7_M;
SV_BR_BIT8_M <= SV_BR_BIT8_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_BR_BIT0_M, SV_BR_BIT1_M, SV_BR_BIT2_M, SV_BR_BIT3_M, SV_BR_BIT4_M, SV_BR_BIT5_M, SV_BR_BIT6_M, SV_BR_BIT7_M, SV_BR_BIT8_M, CLK) --Slave
begin
if (RESET = '1')
then SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
else
if falling_edge(CLK)
then
SV_BR_BIT0 <= SV_BR_BIT0_M;
SV_BR_BIT1 <= SV_BR_BIT1_M;
SV_BR_BIT2 <= SV_BR_BIT2_M;
SV_BR_BIT3 <= SV_BR_BIT3_M;
SV_BR_BIT4 <= SV_BR_BIT4_M;
SV_BR_BIT5 <= SV_BR_BIT5_M;
SV_BR_BIT6 <= SV_BR_BIT6_M;
SV_BR_BIT7 <= SV_BR_BIT7_M;
SV_BR_BIT8 <= SV_BR_BIT8_M;
end if;
end if;
end process;
BIT_REGISTER_EN_BIT_0_PROC:process (SV_BR_BIT0, n_SV_BR_BIT0, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit0
begin
case SV_BR_BIT0 is
when ST_BR_EN_BIT0_0 =>
BYTE_OUT(0)<='0';
BYTE_VEC(0)<='0';
if (EN_BIT_i(0) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_EN_BIT0_1
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
when ST_BR_EN_BIT0_1 =>
-- EN_BIT_0_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(0) = 1
BYTE_OUT(0)<='1';
BYTE_VEC(0)<='1';
if (EN_BIT_i(0) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end if;
else n_SV_BR_BIT0 <= ST_BR_EN_BIT0_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT0 <= ST_BR_EN_BIT0_0;
end case;
end process;
BIT_REGISTER_EN_BIT_1_PROC:process (SV_BR_BIT1, n_SV_BR_BIT1, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT1 is
when ST_BR_EN_BIT1_0 =>
BYTE_OUT(1)<='0';
BYTE_VEC(1)<='0';
if (EN_BIT_i(1) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT1_1
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
when ST_BR_EN_BIT1_1 =>
-- EN_BIT_1_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(1) = 1
BYTE_OUT(1)<='1';
BYTE_VEC(1)<='1';
if (EN_BIT_i(1) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end if;
else n_SV_BR_BIT1 <= ST_BR_EN_BIT1_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT1 <= ST_BR_EN_BIT1_0;
end case;
end process;
BIT_REGISTER_EN_BIT_2_PROC:process (SV_BR_BIT2, n_SV_BR_BIT2, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT2 is
when ST_BR_EN_BIT2_0 =>
BYTE_OUT(2)<='0';
BYTE_VEC(2)<='0';
if (EN_BIT_i(2) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT2_1
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
when ST_BR_EN_BIT2_1 =>
-- EN_BIT_2_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(2) = 1
BYTE_OUT(2)<='1';
BYTE_VEC(2)<='1';
if (EN_BIT_i(2) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end if;
else n_SV_BR_BIT2 <= ST_BR_EN_BIT2_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT2 <= ST_BR_EN_BIT2_0;
end case;
end process;
BIT_REGISTER_EN_BIT_3_PROC:process (SV_BR_BIT3, n_SV_BR_BIT3, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT3 is
when ST_BR_EN_BIT3_0 =>
BYTE_OUT(3)<='0';
BYTE_VEC(3)<='0';
if (EN_BIT_i(3) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT3_1
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
when ST_BR_EN_BIT3_1 =>
-- EN_BIT_3_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(3) = 1
BYTE_OUT(3)<='1';
BYTE_VEC(3)<='1';
if (EN_BIT_i(3) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end if;
else n_SV_BR_BIT3 <= ST_BR_EN_BIT3_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT3 <= ST_BR_EN_BIT3_0;
end case;
end process;
BIT_REGISTER_EN_BIT_4_PROC:process (SV_BR_BIT4, n_SV_BR_BIT4, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT4 is
when ST_BR_EN_BIT4_0 =>
BYTE_OUT(4)<='0';
BYTE_VEC(4)<='0';
if (EN_BIT_i(4) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT4_1
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
when ST_BR_EN_BIT4_1 =>
-- EN_BIT_4 = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(4) = 1
BYTE_OUT(4)<='1';
BYTE_VEC(4)<='1';
if (EN_BIT_i(4) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end if;
else n_SV_BR_BIT4 <= ST_BR_EN_BIT4_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT4 <= ST_BR_EN_BIT4_0;
end case;
end process;
BIT_REGISTER_EN_BIT_5_PROC:process (SV_BR_BIT5, n_SV_BR_BIT5, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit1
begin
case SV_BR_BIT5 is
when ST_BR_EN_BIT5_0 =>
BYTE_OUT(5)<='0';
BYTE_VEC(5)<='0';
if (EN_BIT_i(5) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT5_1
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
when ST_BR_EN_BIT5_1 =>
-- EN_BIT_5_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(5) = 1
BYTE_OUT(5)<='1';
BYTE_VEC(5)<='1';
if (EN_BIT_i(5) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end if;
else n_SV_BR_BIT5 <= ST_BR_EN_BIT5_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT5 <= ST_BR_EN_BIT5_0;
end case;
end process;
BIT_REGISTER_EN_BIT_6_PROC:process (SV_BR_BIT6, n_SV_BR_BIT6, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit6
begin
case SV_BR_BIT6 is
when ST_BR_EN_BIT6_0 =>
BYTE_OUT(6)<='0';
BYTE_VEC(6)<='0';
if (EN_BIT_i(6) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT6_1
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
when ST_BR_EN_BIT6_1 =>
-- EN_BIT_6 = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(6) = 1
BYTE_OUT(6)<='1';
BYTE_VEC(6)<='1';
if (EN_BIT_i(6) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end if;
else n_SV_BR_BIT6 <= ST_BR_EN_BIT6_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT6 <= ST_BR_EN_BIT6_0;
end case;
end process;
BIT_REGISTER_EN_BIT_7_PROC:process (SV_BR_BIT7, n_SV_BR_BIT7, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit7
begin
case SV_BR_BIT7 is
when ST_BR_EN_BIT7_0 =>
BYTE_OUT(7)<='0';
BYTE_VEC(7)<='0';
if (EN_BIT_i(7) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT7_1
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
when ST_BR_EN_BIT7_1 =>
-- EN_BIT_7_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(7) = 1
BYTE_OUT(7)<='1';
BYTE_VEC(7)<='1';
if (EN_BIT_i(7) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end if;
else n_SV_BR_BIT7 <= ST_BR_EN_BIT7_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT7 <= ST_BR_EN_BIT7_0;
end case;
end process;
BIT_REGISTER_EN_BIT_8_PROC:process (SV_BR_BIT8, n_SV_BR_BIT8, BIT_VALUE, EN_BIT_i) --BIT_REGISTER Bit8
begin
case SV_BR_BIT8 is
when ST_BR_EN_BIT8_0 =>
BYTE_VEC(8)<='0';
if (EN_BIT_i(8) = '1')
then
if (BIT_VALUE = '1')--gehe zu ST_BR_BIT8_1
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
when ST_BR_EN_BIT8_1 =>
-- EN_BIT_8_S = 1 und BIT_VALUE = 1 dann setze BYTE_OUT(8) = 1
BYTE_VEC(8)<='1';
if (EN_BIT_i(8) = '1')
then
if (BIT_VALUE = '1')
then n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end if;
else n_SV_BR_BIT8 <= ST_BR_EN_BIT8_1; -- BIT_VALUE = 0
end if;
when others =>
n_SV_BR_BIT8 <= ST_BR_EN_BIT8_0;
end case;
end process;
PARITY_CHECK_PROC: process (BYTE_VEC) --Paritätsprüfung (Mit VARIABLEN := , STATT SIGNALEN <=)
variable TMP00, TMP01, TMP02, TMP03, TMP10, TMP11, TMP20 : std_logic;
begin
TMP00 := BYTE_VEC(0) xor BYTE_VEC(1);
TMP01 := BYTE_VEC(2) xor BYTE_VEC(3);
TMP02 := BYTE_VEC(4) xor BYTE_VEC(5);
TMP03 := BYTE_VEC(6) xor BYTE_VEC(7);
TMP10 := TMP00 xor TMP01;
TMP11 := TMP02 xor TMP03;
TMP20 := TMP10 xor TMP11;
if (TMP20 = BYTE_VEC(8))
then PARITY_OK <= '1'; -- Parität korrekt
else PARITY_OK <= '0'; -- Parität fehlerhaft
end if;
end process;
--BYTE_OUT_PORC: process (BYTE_VEC) --BYTEausgabe
-- begin
-- BYTE_OUT(0) <= BYTE_VEC(0);
-- BYTE_OUT(1) <= BYTE_VEC(1);
-- BYTE_OUT(2) <= BYTE_VEC(2);
-- BYTE_OUT(3) <= BYTE_VEC(3);
-- BYTE_OUT(4) <= BYTE_VEC(4);
-- BYTE_OUT(5) <= BYTE_VEC(5);
-- BYTE_OUT(6) <= BYTE_VEC(6);
-- BYTE_OUT(7) <= BYTE_VEC(7);
--end process;
end Behavioral; | gpl-2.0 | 5d60ef024ae47a2b33d1e7cbb31a9568 | 0.57391 | 2.437753 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/types_mem.vhd | 1 | 7,672 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! Provide common generic log() function
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief Declaration of 'virtual' Memory components.
package types_mem is
--! @brief Declaration of the "virtual" BootROM component.
--! @details BootRom start address must implements address matching to the
--! CPU reset vector (0x200) and all processing after power-on is
--! using this memory block. BootRom size depends of the configuration
--! and size of the generated hex file.
--! Component implements one-clock access to the
--! ROM without wait-staits. Datawidth depends of the AXI4 bus
--! configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] hex_filename Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component Rom_tech is
generic (
memtech : integer := 0;
abits : integer;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
--! @brief Galileo PRN codes ROM storage:
--! @details This ROM is used in FSE Engine to form reference E1 reference
--! signals. HEX-file isn't used for this ROM because 'inferred'
--! module was built using "case when" operators.
component RomPrn_tech is
generic (
generic_tech : integer := 0
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Declaration of the "virtual" SRAM component with unaligned access.
--! @details This module implements internal SRAM and support unaligned access
--! without wait-states. For example it allows to read 4 bytes from
--! address 0x3 for one clock.
--! Component implements one-clock access without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] memtech Generic technology selector.
--! @param[in] abits Generic argument defining SRAM size as 2**abits.
--! @param[in] clk System bus clock.
--! @param[in] raddr Read address.
--! @param[out] rdata Output data value.
--! @param[in] waddr Write address.
--! @param[in] we Write enable.
--! @param[in] wstrb Byte selector to form write only for the specified bytes.
--! @param[in] wdata Write data.
component srambytes_tech is
generic (
memtech : integer := 0;
abits : integer := 16;
init_file : string := ""
);
port (
clk : in std_logic;
raddr : in global_addr_array_type;
rdata : out std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
waddr : in global_addr_array_type;
we : in std_logic;
wstrb : in std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
wdata : in std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 32-bits data width.
--! @details This module doesn't support byte access and always implements
--! 4-bytes alignment.
component Ram32_tech
generic (
generic_tech : integer := 0;
generic_abits : integer := 10
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 64-bits data width.
--! @details This module doesn't support byte access and always implements
--! 4-bytes alignment.
component Ram32x2_tech
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic_vector(1 downto 0);
i_data : in std_logic_vector(63 downto 0);
o_data : out std_logic_vector(63 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 64-bits data width.
--! @details This module doesn't support byte access and always implements
--! 8-bytes alignment.
component Ram64_tech
generic (
generic_tech : integer := 0;
generic_abits : integer := 4
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(63 downto 0);
o_data : out std_logic_vector(63 downto 0)
);
end component;
--! @brief dual-port RAM declaration.
component syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end component;
component dpram_tech is
generic (
memtech : integer := 0;
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end component;
component ram_tech is generic (
memtech : integer := 0;
abits : integer := 12;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_addr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_wena : in std_logic;
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end component;
component otp_tech is generic (
memtech : integer := 0
);
port (
clk : in std_logic; -- only for FPGA
i_we : in std_ulogic;
i_re : in std_ulogic;
i_addr : in std_logic_vector(11 downto 0);
i_wdata : in std_logic_vector(15 downto 0);
o_rdata : out std_logic_vector(15 downto 0);
io_gnd : inout std_logic;
io_vdd : inout std_logic;
io_vdd18 : inout std_logic;
io_upp : inout std_logic
);
end component;
end;
| apache-2.0 | f38482ba540ef2b1458bf4905a8b7992 | 0.622263 | 3.663801 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/icache_lru.vhd | 1 | 15,940 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_cache.all;
entity icache_lru is generic (
memtech : integer;
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
-- Control path:
i_req_valid : in std_logic;
i_req_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_req_ready : out std_logic;
o_resp_valid : out std_logic;
o_resp_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_resp_data : out std_logic_vector(31 downto 0);
o_resp_load_fault : out std_logic;
o_resp_executable : out std_logic;
o_resp_writable : out std_logic;
o_resp_readable : out std_logic;
i_resp_ready : in std_logic;
-- Memory interface:
i_req_mem_ready : in std_logic;
o_req_mem_valid : out std_logic;
o_req_mem_type : out std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
o_req_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
o_req_mem_strob : out std_logic_vector(ICACHE_BYTES_PER_LINE-1 downto 0);
o_req_mem_data : out std_logic_vector(ICACHE_LINE_BITS-1 downto 0);
i_mem_data_valid : in std_logic;
i_mem_data : in std_logic_vector(ICACHE_LINE_BITS-1 downto 0);
i_mem_load_fault : in std_logic;
-- MPU interface:
o_mpu_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
i_mpu_flags : in std_logic_vector(CFG_MPU_FL_TOTAL-1 downto 0);
-- Debug Signals:
i_flush_address : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- clear ICache address from debug interface
i_flush_valid : in std_logic -- address to clear icache is valid
);
end;
architecture arch_icache_lru of icache_lru is
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
constant State_Idle : std_logic_vector(3 downto 0) := "0000";
constant State_CheckHit : std_logic_vector(3 downto 0) := "0001";
constant State_TranslateAddress : std_logic_vector(3 downto 0) := "0010";
constant State_WaitGrant : std_logic_vector(3 downto 0) := "0011";
constant State_WaitResp : std_logic_vector(3 downto 0) := "0100";
constant State_CheckResp : std_logic_vector(3 downto 0) := "0101";
constant State_SetupReadAdr : std_logic_vector(3 downto 0) := "0110";
constant State_FlushAddr : std_logic_vector(3 downto 0) := "0111";
constant State_FlushCheck : std_logic_vector(3 downto 0) := "1000";
constant State_ResetAddr : std_logic_vector(3 downto 0) := "1001";
constant State_ResetWrite : std_logic_vector(3 downto 0) := "1010";
type RegistersType is record
req_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
req_addr_next : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
write_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
state : std_logic_vector(3 downto 0);
req_mem_valid : std_logic;
mem_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
req_mem_type : std_logic_vector(REQ_MEM_TYPE_BITS-1 downto 0);
executable : std_logic;
load_fault : std_logic;
req_flush : std_logic;
req_flush_all : std_logic;
req_flush_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
req_flush_cnt : std_logic_vector(CFG_ILOG2_LINES_PER_WAY+CFG_ILOG2_NWAYS-1 downto 0);
flush_cnt : std_logic_vector(CFG_ILOG2_LINES_PER_WAY+CFG_ILOG2_NWAYS-1 downto 0);
cache_line_i : std_logic_vector(ICACHE_LINE_BITS-1 downto 0);
end record;
constant R_RESET : RegistersType := (
(others => '0'), (others => '0'), -- req_addr, req_addr_next
(others => '0'), -- write_addr
State_ResetAddr, -- state
'0', (others => '0'), -- req_mem_valid, mem_addr,
(others => '0'), -- req_mem_type
'0', -- executable
'0', -- load_fault
'0', -- req_flush
'0', -- req_flush_all
(others => '0'), (others => '0'), -- req_flush_addr, req_flush_cnt
(others => '1'), -- flush_cnt
(others => '0') -- cache_line_i
);
signal r, rin : RegistersType;
signal line_direct_access_i : std_logic;
signal line_invalidate_i : std_logic;
signal line_re_i : std_logic;
signal line_we_i : std_logic;
signal line_addr_i : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal line_wdata_i : std_logic_vector(ICACHE_LINE_BITS-1 downto 0);
signal line_wstrb_i : std_logic_vector(2**CFG_ILOG2_BYTES_PER_LINE-1 downto 0);
signal line_wflags_i : std_logic_vector(ITAG_FL_TOTAL-1 downto 0);
signal line_raddr_o : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
signal line_rdata_o : std_logic_vector(ICACHE_LINE_BITS+15 downto 0);
signal line_rflags_o : std_logic_vector(ITAG_FL_TOTAL-1 downto 0);
signal line_hit_o : std_logic;
signal line_hit_next_o : std_logic;
begin
memcouple : tagmemcoupled generic map (
memtech => memtech,
async_reset => async_reset,
abus => CFG_CPU_ADDR_BITS,
waybits => CFG_ILOG2_NWAYS,
ibits => CFG_ILOG2_LINES_PER_WAY,
lnbits => CFG_ILOG2_BYTES_PER_LINE,
flbits => ITAG_FL_TOTAL
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_direct_access => line_direct_access_i,
i_invalidate => line_invalidate_i,
i_re => line_re_i,
i_we => line_we_i,
i_addr => line_addr_i,
i_wdata => line_wdata_i,
i_wstrb => line_wstrb_i,
i_wflags => line_wflags_i,
o_raddr => line_raddr_o,
o_rdata => line_rdata_o,
o_rflags => line_rflags_o,
o_hit => line_hit_o,
o_hit_next => line_hit_next_o
);
comb : process(i_nrst, i_req_valid, i_req_addr,
i_resp_ready, i_req_mem_ready,
i_mem_data_valid, i_mem_data, i_mem_load_fault,
i_mpu_flags, i_flush_address, i_flush_valid,
line_raddr_o, line_rdata_o, line_rflags_o, line_hit_o, line_hit_next_o, r)
variable v : RegistersType;
variable v_req_ready : std_logic;
variable v_resp_valid : std_logic;
variable vb_cached_data : std_logic_vector(31 downto 0);
variable vb_uncached_data : std_logic_vector(31 downto 0);
variable vb_resp_data : std_logic_vector(31 downto 0);
variable v_resp_er_load_fault : std_logic;
variable v_direct_access : std_logic;
variable v_invalidate : std_logic;
variable v_line_cs_read : std_logic;
variable v_line_cs_write : std_logic;
variable vb_line_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_line_wdata : std_logic_vector(ICACHE_LINE_BITS-1 downto 0);
variable vb_line_wstrb : std_logic_vector(ICACHE_BYTES_PER_LINE-1 downto 0);
variable v_line_wflags : std_logic_vector(ITAG_FL_TOTAL-1 downto 0);
variable sel_cached : integer;
variable sel_uncached : integer;
variable v_ready_next : std_logic;
variable vb_addr_direct_next : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
begin
v := r;
v_ready_next := '0';
v_req_ready := '0';
v_resp_valid := '0';
vb_resp_data := (others => '0');
v_resp_er_load_fault := '0';
v_direct_access := '0';
v_invalidate := '0';
sel_cached := conv_integer(r.req_addr(CFG_ILOG2_BYTES_PER_LINE-1 downto 1));
sel_uncached := conv_integer(r.req_addr(2 downto 1));
vb_cached_data := line_rdata_o(16*sel_cached + 31 downto 16*sel_cached);
vb_uncached_data := r.cache_line_i(16*sel_uncached + 31 downto 16*sel_uncached);
-- flush request via debug interface
if i_flush_valid = '1' then
v.req_flush := '1';
v.req_flush_all := i_flush_address(0);
if i_flush_address(0) = '1' then
v.req_flush_cnt := (others => '1');
v.req_flush_addr := (others => '0');
elsif and_reduce(i_flush_address(CFG_ILOG2_BYTES_PER_LINE-1 downto 1)) = '1' then
v.req_flush_cnt := conv_std_logic_vector(1,
CFG_ILOG2_LINES_PER_WAY+CFG_ILOG2_NWAYS);
v.req_flush_addr := i_flush_address;
else
v.req_flush_cnt := (others => '0');
v.req_flush_addr := i_flush_address;
end if;
end if;
-- Flush counter when direct access
if r.req_addr(CFG_ILOG2_NWAYS-1 downto 0) =
conv_std_logic_vector(ICACHE_WAYS-1, CFG_ILOG2_NWAYS) then
vb_addr_direct_next(CFG_CPU_ADDR_BITS-1 downto CFG_ILOG2_BYTES_PER_LINE) :=
r.req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_ILOG2_BYTES_PER_LINE) + 1;
vb_addr_direct_next(CFG_ILOG2_BYTES_PER_LINE-1 downto 0) := (others => '0');
else
vb_addr_direct_next := r.req_addr + 1;
end if;
v_line_cs_read := '0';
v_line_cs_write := '0';
vb_line_addr := r.req_addr;
vb_line_wdata := r.cache_line_i;
vb_line_wstrb := (others => '0');
v_line_wflags := (others => '0');
case r.state is
when State_Idle =>
v.executable := '1';
v_ready_next := '1';
when State_CheckHit =>
vb_resp_data := vb_cached_data;
if line_hit_o = '1' and line_hit_next_o = '1' then
-- Hit
v_resp_valid := '1';
if i_resp_ready = '1' then
v_ready_next := '1';
v.state := State_Idle;
end if;
else
-- Miss
v.state := State_TranslateAddress;
end if;
when State_TranslateAddress =>
if i_mpu_flags(CFG_MPU_FL_EXEC) = '0' then
v.cache_line_i := (others => '1');
v.state := State_CheckResp;
else
v.req_mem_valid := '1';
v.state := State_WaitGrant;
v.write_addr := r.req_addr;
if i_mpu_flags(CFG_MPU_FL_CACHABLE) = '1' then
if line_hit_o = '0' then
v.mem_addr := r.req_addr(CFG_CPU_ADDR_BITS-1 downto CFG_ILOG2_BYTES_PER_LINE)
& zero64(CFG_ILOG2_BYTES_PER_LINE-1 downto 0);
else
v.write_addr := r.req_addr_next;
v.mem_addr := r.req_addr_next(CFG_CPU_ADDR_BITS-1 downto CFG_ILOG2_BYTES_PER_LINE)
& zero64(CFG_ILOG2_BYTES_PER_LINE-1 downto 0);
end if;
v.req_mem_type := ReadShared;
else
v.mem_addr := r.req_addr(CFG_CPU_ADDR_BITS-1 downto 3) & "000";
v.req_mem_type := ReadNoSnoop;
end if;
end if;
v.load_fault := '0';
v.executable := i_mpu_flags(CFG_MPU_FL_EXEC);
when State_WaitGrant =>
if i_req_mem_ready = '1' then
v.state := State_WaitResp;
v.req_mem_valid := '0';
end if;
when State_WaitResp =>
if i_mem_data_valid = '1' then
v.cache_line_i := i_mem_data;
v.state := State_CheckResp;
v.write_addr := r.req_addr; -- Swap addres for 1 clock to write line
v.req_addr := r.write_addr;
if i_mem_load_fault = '1' then
v.load_fault := '1';
end if;
end if;
when State_CheckResp =>
v.req_addr := r.write_addr; -- Restore req_addr after line write
if r.req_mem_type(REQ_MEM_TYPE_CACHED) = '0' or r.load_fault = '1' then
v_resp_valid := '1';
vb_resp_data := vb_uncached_data;
v_resp_er_load_fault := r.load_fault;
if i_resp_ready = '1' then
v.state := State_Idle;
end if;
else
v.state := State_SetupReadAdr;
v_line_cs_write := '1';
v_line_wflags(TAG_FL_VALID) := '1';
vb_line_wstrb := (others => '1'); -- write full line
end if;
when State_SetupReadAdr =>
v.state := State_CheckHit;
when State_FlushAddr =>
v.state := State_FlushCheck;
v_direct_access := r.req_flush_all; -- 0=only if hit; 1=will be applied ignoring hit
v_invalidate := '1'; -- generate: wstrb='1; wflags='0
v.cache_line_i := (others => '0');
when State_FlushCheck =>
v.state := State_FlushAddr;
v_direct_access := r.req_flush_all;
v_line_cs_write := r.req_flush_all;
if or_reduce(r.flush_cnt) = '1' then
v.flush_cnt := r.flush_cnt - 1;
if r.req_flush_all = '1' then
v.req_addr := vb_addr_direct_next;
else
v.req_addr := r.req_addr + ICACHE_BYTES_PER_LINE;
end if;
else
v.state := State_Idle;
end if;
when State_ResetAddr =>
-- Write clean line
v_direct_access := '1';
v_invalidate := '1'; -- generate: wstrb='1; wflags='0
v.state := State_ResetWrite;
when State_ResetWrite =>
v_direct_access := '1';
v_line_cs_write := '1';
v.state := State_ResetAddr;
if or_reduce(r.flush_cnt) = '1' then
v.flush_cnt := r.flush_cnt - 1;
v.req_addr := vb_addr_direct_next;
else
v.state := State_Idle;
end if;
when others =>
end case;
if v_ready_next = '1' then
if r.req_flush = '1' then
v.state := State_FlushAddr;
v.req_flush := '0';
v.cache_line_i := (others => '0');
v.req_addr := r.req_flush_addr(CFG_CPU_ADDR_BITS-1 downto CFG_ILOG2_BYTES_PER_LINE)
& zero64(CFG_ILOG2_BYTES_PER_LINE-1 downto 0);
v.flush_cnt := r.req_flush_cnt;
else
v_req_ready := '1';
v_line_cs_read := i_req_valid;
vb_line_addr := i_req_addr;
if i_req_valid = '1' then
v.req_addr := i_req_addr;
v.req_addr_next := i_req_addr + ICACHE_BYTES_PER_LINE;
v.state := State_CheckHit;
end if;
end if;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
line_direct_access_i <= v_direct_access;
line_invalidate_i <= v_invalidate;
line_re_i <= v_line_cs_read;
line_we_i <= v_line_cs_write;
line_addr_i <= vb_line_addr;
line_wdata_i <= vb_line_wdata;
line_wstrb_i <= vb_line_wstrb;
line_wflags_i <= v_line_wflags;
o_req_ready <= v_req_ready;
o_req_mem_valid <= r.req_mem_valid;
o_req_mem_addr <= r.mem_addr;
o_req_mem_type <= r.req_mem_type;
o_req_mem_strob <= (others => '0');
o_req_mem_data <= (others => '0');
o_resp_valid <= v_resp_valid;
o_resp_data <= vb_resp_data;
o_resp_addr <= r.req_addr;
o_resp_load_fault <= v_resp_er_load_fault;
o_resp_executable <= r.executable;
o_resp_writable <= '0';
o_resp_readable <= '0';
o_mpu_addr <= r.req_addr;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | e132f8b40fb45dce959db3703455915b | 0.564994 | 3.160817 | false | false | false | false |
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Y8xqN1k5Z4CrikAE44uRlt0QXk4mtxFZQGBLLogmU4AvMxv9agoJlpIkJfpxF93JenK+4YvRxl4o
3KS3i12zl6q/fGDIRmyaHjfYKksBOIS9BuBHkjOCFBHx3fYmHlzrL76d5VkCa0CGWLOvPP7vD7EC
kIaa5pNI3UcbklfkQ4YTI6VAYObMXCjg5/Y7VeWeha284Y3N7V9AFVoDVFWMYJDT4u0pK9vdPJcy
IKORlSuoA1BfmhnC2xY6aB3iksVG7DJGO7AIJE4xgDdtbf9aHEeWkEMEG8HzHNs1ct+fe6ptnHtG
J4auzi51plFi91VVh6UWRdlQcCFUx9xX4zcPwpJqBLl9BNw+DMZu09dVSN1mi6MXkJVhrMgE4lR7
YG1ykbx6jCxe3TYXOoqJcyNSN78gDmznRewlm1c9TXkXZ+KLVk+7bCuKXaV3Ic2kkI0zj/ifFg2k
9SofmMTPqKjbHIZ9B34FYtsrkhvIyGsDHp9wQ+rPPUNy4kgfpUhjBMXuRIax/rsjo+hGDr+Q4+CK
WEGG5qXAcLMhH2JhtF8GtPqpMChWQ1crPnzuo71OeWzK5XVN6Y+bjjcBk/d4b6dhGa4TYf2B55pH
wsOcIggqf5q7ccQ4hud58nrttOCYVfTTG3qE9REOJ3DgGjIge74yCtcfYE/Zs+SwtbBa
`protect end_protected
| bsd-2-clause | 42f34f55c50d801b0d8f060bc82523b6 | 0.931385 | 1.866049 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/cache/tagmemnway.vhd | 1 | 8,248 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.types_mem.all;
library riverlib;
use riverlib.types_cache.all;
entity tagmemnway is generic (
memtech : integer := 0;
async_reset : boolean := false;
abus : integer := 64; -- system bus address bus (32 or 64 bits)
waybits : integer := 2; -- log2 of number of ways bits (=2 for 4 ways)
ibits : integer := 7; -- lines memory addres width (usually 6..8)
lnbits : integer := 5; -- One line bits: log2(bytes_per_line)
flbits : integer := 1; -- Total flags number saved with address tag
snoop : boolean := false -- Snoop port disabled; 1 Enabled (L2 caching)
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_direct_access : in std_logic;
i_invalidate : in std_logic;
i_re : in std_logic;
i_we : in std_logic;
i_addr : in std_logic_vector(abus-1 downto 0);
i_wdata : in std_logic_vector(8*(2**lnbits)-1 downto 0);
i_wstrb : in std_logic_vector(2**lnbits-1 downto 0);
i_wflags : in std_logic_vector(flbits-1 downto 0);
o_raddr : out std_logic_vector(abus-1 downto 0);
o_rdata : out std_logic_vector(8*(2**lnbits)-1 downto 0);
o_rflags : out std_logic_vector(flbits-1 downto 0);
o_hit : out std_logic;
-- L2 snoop port, active when snoop = 1
i_snoop_addr : in std_logic_vector(abus-1 downto 0);
o_snoop_ready : out std_logic;
o_snoop_flags : out std_logic_vector(flbits-1 downto 0)
);
end;
architecture arch_tagmemnway of tagmemnway is
constant FL_VALID : integer := 0;
constant NWAYS : integer := 2**waybits;
type WayInType is record
addr : std_logic_vector(abus-1 downto 0);
wstrb : std_logic_vector((2**lnbits)-1 downto 0);
wdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
wflags : std_logic_vector(flbits-1 downto 0);
snoop_addr : std_logic_vector(abus-1 downto 0);
end record;
type WayOutType is record
raddr : std_logic_vector(abus-1 downto 0);
rdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
rflags : std_logic_vector(flbits-1 downto 0);
hit : std_logic;
snoop_flags : std_logic_vector(flbits-1 downto 0);
end record;
type way_in_vector is array (0 to NWAYS-1) of WayInType;
type way_out_vector is array (0 to NWAYS-1) of WayOutType;
type RegistersType is record
req_addr : std_logic_vector(abus-1 downto 0);
direct_access : std_logic;
invalidate : std_logic;
re : std_logic;
end record;
constant R_RESET : RegistersType := ((others => '0'), '0', '0', '0');
signal way_i : way_in_vector;
signal way_o : way_out_vector;
signal lrui_init : std_logic;
signal lrui_raddr : std_logic_vector(ibits-1 downto 0);
signal lrui_waddr : std_logic_vector(ibits-1 downto 0);
signal lrui_up : std_logic;
signal lrui_down : std_logic;
signal lrui_lru : std_logic_vector(waybits-1 downto 0);
signal lruo_lru : std_logic_vector(waybits-1 downto 0);
signal r, rin : RegistersType;
begin
dx : for i in 0 to NWAYS-1 generate
wayx : tagmem generic map (
async_reset => async_reset,
memtech => memtech,
abus => abus,
ibits => ibits,
lnbits => lnbits,
flbits => flbits,
snoop => snoop
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_addr => way_i(i).addr,
i_wstrb => way_i(i).wstrb,
i_wdata => way_i(i).wdata,
i_wflags => way_i(i).wflags,
o_raddr => way_o(i).raddr,
o_rdata => way_o(i).rdata,
o_rflags => way_o(i).rflags,
o_hit => way_o(i).hit,
i_snoop_addr => way_i(i).snoop_addr,
o_snoop_flags => way_o(i).snoop_flags
);
end generate;
lru0 : lrunway generic map (
abits => ibits,
waybits => waybits
) port map (
i_clk => i_clk,
i_init => lrui_init,
i_raddr => lrui_raddr,
i_waddr => lrui_waddr,
i_up => lrui_up,
i_down => lrui_down,
i_lru => lrui_lru,
o_lru => lruo_lru
);
comb : process(i_nrst, i_direct_access, i_invalidate, i_re, i_we,
i_addr, i_wstrb, i_wdata, i_wflags, i_snoop_addr,
way_o, lruo_lru, r)
variable v : RegistersType;
variable vb_raddr : std_logic_vector(abus-1 downto 0);
variable vb_rdata : std_logic_vector(8*(2**lnbits)-1 downto 0);
variable vb_rflags : std_logic_vector(flbits-1 downto 0);
variable v_hit : std_logic;
variable vb_hit_idx : std_logic_vector(waybits-1 downto 0);
variable v_way_we : std_logic;
variable vb_wstrb : std_logic_vector((2**lnbits)-1 downto 0);
variable vb_wflags : std_logic_vector(flbits-1 downto 0);
variable v_snoop_ready : std_logic;
variable vb_snoop_flags : std_logic_vector(flbits-1 downto 0);
begin
v.direct_access := i_direct_access;
v.invalidate := i_invalidate;
v.re := i_re;
v.req_addr := i_addr;
vb_hit_idx := lruo_lru;
if r.direct_access = '1' then
vb_hit_idx := r.req_addr(waybits-1 downto 0);
else
for i in 0 to NWAYS-1 loop
if way_o(i).hit = '1' then
vb_hit_idx := conv_std_logic_vector(i, waybits);
end if;
end loop;
end if;
vb_raddr := way_o(conv_integer(vb_hit_idx)).raddr;
vb_rdata := way_o(conv_integer(vb_hit_idx)).rdata;
vb_rflags := way_o(conv_integer(vb_hit_idx)).rflags;
v_hit := way_o(conv_integer(vb_hit_idx)).hit;
if r.invalidate = '1' then
vb_wflags := (others => '0');
vb_wstrb := (others => '1');
else
vb_wflags := i_wflags;
vb_wstrb := i_wstrb;
end if;
-- Warning: we can write only into previously read line,
-- if the previuosly read line is hit and contains valid flags
-- HIGH we modify it. Otherwise, we write into displacing line.
--
for i in 0 to NWAYS-1 loop
way_i(i).addr <= i_addr;
way_i(i).wdata <= i_wdata;
way_i(i).wstrb <= (others => '0');
way_i(i).wflags <= vb_wflags;
way_i(i).snoop_addr <= i_snoop_addr;
end loop;
v_way_we := i_we or (r.invalidate and v_hit);
if v_way_we = '1' then
way_i(conv_integer(vb_hit_idx)).wstrb <= vb_wstrb;
end if;
v_snoop_ready := '1';
vb_snoop_flags := (others => '0');
if snoop then
for i in 0 to NWAYS-1 loop
-- tagmem already cleared snoop flags if there's no snoop hit
if way_o(i).snoop_flags(FL_VALID) = '1' then
vb_snoop_flags := way_o(i).snoop_flags;
end if;
end loop;
-- Writing into snoop tag memory, output value won't be valid on next clock
if v_way_we = '1' then
v_snoop_ready := '0';
end if;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
lrui_init <= r.direct_access;
lrui_raddr <= i_addr(ibits+lnbits-1 downto lnbits);
lrui_waddr <= r.req_addr(ibits+lnbits-1 downto lnbits);
lrui_up <= i_we or (v_hit and r.re);
lrui_down <= v_hit and r.invalidate;
lrui_lru <= vb_hit_idx;
rin <= v;
o_raddr <= vb_raddr;
o_rdata <= vb_rdata;
o_rflags <= vb_rflags;
o_hit <= v_hit;
o_snoop_ready <= v_snoop_ready;
o_snoop_flags <= vb_snoop_flags;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 8ffb33d85702d0d0c605832c2f73826a | 0.600509 | 3.131359 | false | false | false | false |
BBN-Q/VHDL-FIR-filters | src/FIR_DirectTranspose.vhd | 1 | 3,458 | ----------------------------------------------------------------------------------
-- Simple FIR filter using transposed direct form.
-- Initial version: Colm Ryan ([email protected])
-- Create Date: 05/05/2015
-- Dependencies:
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library ieee_proposed;
use ieee_proposed.standard_additions.all;
use work.CoeffHelpers.all;
entity FIR_DirectTranspose is
generic(
--Default 1/4 band low-pass filter generated in Python with
-- import scipy.signal
-- br = scipy.signal.remez(16, [0,0.1,0.2,0.5], [1,0])
coeffs : real_vector := (0.01662606, -0.00696415, -0.03403663, -0.04855056, -0.01434685, 0.08048669, 0.20301046, 0.28957738, 0.28957738, 0.20301046, 0.08048669, -0.01434685, -0.04855056, -0.03403663, -0.00696415, 0.01662606);
data_in_width : natural := 16;
data_out_width : natural := 16
);
port (
rst : in std_logic;
clk : in std_logic;
data_in : in std_logic_vector(data_in_width-1 downto 0);
data_in_vld : std_logic;
data_in_last : std_logic;
data_out : out std_logic_vector(data_out_width-1 downto 0));
end FIR_DirectTranspose;
architecture Behavioral of FIR_DirectTranspose is
constant NUM_TAPS : natural := coeffs'length;
type chainedSum_t is array(0 to NUM_TAPS-1) of signed(47 downto 0);
signal chainedSum : chainedSum_t := (others => (others => '0'));
--Vivado does not infer DSP for constant multiplier so force DSP
-- see http://www.xilinx.com/support/answers/60913.html
attribute use_dsp48 : string;
attribute use_dsp48 of chainedSum : signal is "yes";
signal data_in_d : signed(data_in_width-1 downto 0) := (others => '0');
--We resize to 18 bits because the DSP slices offer 18x25 bit multipliers
constant COEFF_SCALE_BITS : integer := optimum_scaling(coeffs);
constant COEFF_SCALE : real := real(2 ** (17 - COEFF_SCALE_BITS));
constant SCALED_COEFFS : integer_vector := scale_coeffs(coeffs, COEFF_SCALE);
--we resize the sum to 48 bits because the DSP slices offer 48 bit adder accumulators
--If we assume the coefficients are normalized then we don't need to worry about overflow in the addition
constant SUM_NUM_BITS : natural := 48;
--The multiplication gives us 18 + data_in_width - 1 bits
--We also need to undo the coefficients' scaling
constant TOP_OUTPUT_BIT : natural := 18 + data_in_width - 2 - COEFF_SCALE_BITS;
constant BOTTOM_OUTPUT_BIT : natural := TOP_OUTPUT_BIT - data_out_width + 1;
begin
main : process(clk)
begin
if rising_edge(clk) then
--register input data and convert to signed for DSP slice
data_in_d <= signed(data_in);
--Multiply by coeffs and chain the sum
chainedSum(0) <= resize(data_in_d * to_signed(SCALED_COEFFS(SCALED_COEFFS'high),18), SUM_NUM_BITS);
sumLooper : for ct in 1 to NUM_TAPS-1 loop
chainedSum(ct) <= resize(data_in_d * to_signed(SCALED_COEFFS(SCALED_COEFFS'high-ct),18), SUM_NUM_BITS) + chainedSum(ct-1);
end loop;
end if;
end process;
--Slice out the appropriate portion of the output - for now just truncate LSB
data_out <= std_logic_vector(chainedSum(chainedSum'high)(TOP_OUTPUT_BIT downto BOTTOM_OUTPUT_BIT));
end Behavioral;
| apache-2.0 | 20f2204965c22955e547d7dca7e09c35 | 0.665703 | 3.380254 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_cmd_split.vhd | 1 | 22,818 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
library lib_cdc_v1_0_2;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
entity axi_dma_cmd_split is
generic (
C_ADDR_WIDTH : integer range 32 to 64 := 32;
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
C_INCLUDE_S2MM : integer range 0 to 1 := 0
);
port (
clock : in std_logic;
sgresetn : in std_logic;
clock_sec : in std_logic;
aresetn : in std_logic;
-- command coming from _MNGR
s_axis_cmd_tvalid : in std_logic;
s_axis_cmd_tready : out std_logic;
s_axis_cmd_tdata : in std_logic_vector ((C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);
-- split command to DM
s_axis_cmd_tvalid_s : out std_logic;
s_axis_cmd_tready_s : in std_logic;
s_axis_cmd_tdata_s : out std_logic_vector ((C_ADDR_WIDTH+CMD_BASE_WIDTH+8)-1 downto 0);
-- Tvalid from Datamover
tvalid_from_datamover : in std_logic;
status_in : in std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
tvalid_unsplit : out std_logic;
status_out : out std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
-- Tlast of stream data from Datamover
tlast_stream_data : in std_logic;
tready_stream_data : in std_logic;
tlast_unsplit : out std_logic;
tlast_unsplit_user : out std_logic
);
end entity axi_dma_cmd_split;
architecture implementation of axi_dma_cmd_split is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
type SPLIT_MM2S_STATE_TYPE is (
IDLE,
SEND,
SPLIT
);
signal mm2s_cs : SPLIT_MM2S_STATE_TYPE;
signal mm2s_ns : SPLIT_MM2S_STATE_TYPE;
signal mm2s_cmd : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46-1 downto 0);
signal command_ns : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal command : std_logic_vector (C_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH-1 downto 0);
signal cache_info : std_logic_vector (31 downto 0);
signal vsize_data : std_logic_vector (22 downto 0);
signal vsize_data_int : std_logic_vector (22 downto 0);
signal vsize : std_logic_vector (22 downto 0);
signal counter : std_logic_vector (22 downto 0);
signal counter_tlast : std_logic_vector (22 downto 0);
signal split_cmd : std_logic_vector (31+(C_ADDR_WIDTH-32) downto 0);
signal stride_data : std_logic_vector (22 downto 0);
signal vsize_over : std_logic;
signal cmd_proc_cdc_from : std_logic;
signal cmd_proc_cdc_to : std_logic;
signal cmd_proc_cdc : std_logic;
signal cmd_proc_ns : std_logic;
ATTRIBUTE async_reg : STRING;
-- ATTRIBUTE async_reg OF cmd_proc_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF cmd_proc_cdc : SIGNAL IS "true";
signal cmd_out : std_logic;
signal cmd_out_ns : std_logic;
signal split_out : std_logic;
signal split_out_ns : std_logic;
signal command_valid : std_logic;
signal command_valid_ns : std_logic;
signal command_ready : std_logic;
signal reset_lock : std_logic;
signal reset_lock_tlast : std_logic;
signal tvalid_unsplit_int : std_logic;
signal tlast_stream_data_int : std_logic;
signal ready_for_next_cmd : std_logic;
signal ready_for_next_cmd_tlast : std_logic;
signal ready_for_next_cmd_tlast_cdc_from : std_logic;
signal ready_for_next_cmd_tlast_cdc_to : std_logic;
signal ready_for_next_cmd_tlast_cdc : std_logic;
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF ready_for_next_cmd_tlast_cdc : SIGNAL IS "true";
signal tmp1, tmp2, tmp3, tmp4 : std_logic;
signal tlast_int : std_logic;
signal eof_bit : std_logic;
signal eof_bit_cdc_from : std_logic;
signal eof_bit_cdc_to : std_logic;
signal eof_bit_cdc : std_logic;
signal eof_set : std_logic;
signal over_ns, over : std_logic;
signal cmd_in : std_logic;
signal status_out_int : std_logic_vector (C_DM_STATUS_WIDTH-1 downto 0);
begin
s_axis_cmd_tvalid_s <= command_valid;
command_ready <= s_axis_cmd_tready_s;
s_axis_cmd_tdata_s <= command (103+(C_ADDR_WIDTH-32) downto 96+(C_ADDR_WIDTH-32)) & command (71+(C_ADDR_WIDTH-32) downto 0);
REGISTER_STATE_MM2S : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cs <= IDLE;
cmd_proc_cdc_from <= '0';
cmd_out <= '0';
command <= (others => '0');
command_valid <= '0';
split_out <= '0';
over <= '0';
else
mm2s_cs <= mm2s_ns;
cmd_proc_cdc_from <= cmd_proc_ns;
cmd_out <= cmd_out_ns;
command <= command_ns;
command_valid <= command_valid_ns;
split_out <= split_out_ns;
over <= over_ns;
end if;
end if;
end process REGISTER_STATE_MM2S;
-- grab the MM2S command coming from MM2S_mngr
REGISTER_MM2S_CMD : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
mm2s_cmd <= (others => '0');
s_axis_cmd_tready <= '0';
cache_info <= (others => '0');
vsize_data <= (others => '0');
vsize_data_int <= (others => '0');
stride_data <= (others => '0');
eof_bit_cdc_from <= '0';
cmd_in <= '0';
elsif (s_axis_cmd_tvalid = '1' and ready_for_next_cmd = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd_tlast_cdc = '1') then -- when there is no processing being done, means it is ready to accept
mm2s_cmd <= s_axis_cmd_tdata;
s_axis_cmd_tready <= '1';
cache_info <= s_axis_cmd_tdata (149+(C_ADDR_WIDTH-32) downto 118+(C_ADDR_WIDTH-32));
vsize_data <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32));
vsize_data_int <= s_axis_cmd_tdata (117+(C_ADDR_WIDTH-32) downto 95+(C_ADDR_WIDTH-32)) - '1';
stride_data <= s_axis_cmd_tdata (94+(C_ADDR_WIDTH-32) downto 72+(C_ADDR_WIDTH-32));
eof_bit_cdc_from <= s_axis_cmd_tdata (30);
cmd_in <= '1';
else
mm2s_cmd <= mm2s_cmd; --split_cmd;
vsize_data <= vsize_data;
vsize_data_int <= vsize_data_int;
stride_data <= stride_data;
cache_info <= cache_info;
s_axis_cmd_tready <= '0';
eof_bit_cdc_from <= eof_bit_cdc_from;
cmd_in <= '0';
end if;
end if;
end process REGISTER_MM2S_CMD;
REGISTER_DECR_VSIZE : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
vsize <= "00000000000000000000000";
elsif (command_valid = '1' and command_ready = '1' and (vsize < vsize_data_int)) then -- sending a cmd out to DM
vsize <= vsize + '1';
elsif (cmd_proc_cdc_from = '0') then -- idle or when all cmd are sent to DM
vsize <= "00000000000000000000000";
else
vsize <= vsize;
end if;
end if;
end process REGISTER_DECR_VSIZE;
vsize_over <= '1' when (vsize = vsize_data_int) else '0';
-- eof_set <= eof_bit when (vsize = vsize_data_int) else '0';
REGISTER_SPLIT : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
split_cmd <= (others => '0');
elsif (s_axis_cmd_tvalid = '1' and cmd_proc_cdc_from = '0' and ready_for_next_cmd = '1' and ready_for_next_cmd_tlast_cdc = '1') then
split_cmd <= s_axis_cmd_tdata (63+(C_ADDR_WIDTH-32) downto 32); -- capture the ba when a new cmd arrives
elsif (split_out = '1') then -- add stride to previous ba
split_cmd <= split_cmd + stride_data;
else
split_cmd <= split_cmd;
end if;
end if;
end process REGISTER_SPLIT;
MM2S_MACHINE : process(mm2s_cs,
s_axis_cmd_tvalid,
cmd_proc_cdc_from,
vsize_over, command_ready,
cache_info, mm2s_cmd,
split_cmd, eof_set,
cmd_in, command
)
begin
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
mm2s_ns <= mm2s_cs;
command_ns <= command;
-- Default signal assignment
case mm2s_cs is
-------------------------------------------------------------------
when IDLE =>
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
if (cmd_in = '1' and cmd_proc_cdc_from = '0') then
cmd_proc_ns <= '1'; -- new command has come in and i need to start processing
mm2s_ns <= SEND;
over_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
else
mm2s_ns <= IDLE;
over_ns <= '0';
cmd_proc_ns <= '0'; -- ready to receive new command
split_out_ns <= '0';
command_valid_ns <= '0';
end if;
-------------------------------------------------------------------
when SEND =>
cmd_out_ns <= '1';
command_ns <= command;
if (vsize_over = '1' and command_ready = '1') then
mm2s_ns <= IDLE;
cmd_proc_ns <= '1';
command_valid_ns <= '0';
split_out_ns <= '0';
over_ns <= '1';
elsif (command_ready = '0') then --(command_valid = '1' and command_ready = '0') then
mm2s_ns <= SEND;
command_valid_ns <= '1';
cmd_proc_ns <= '1';
split_out_ns <= '0';
over_ns <= '0';
else
mm2s_ns <= SPLIT;
command_valid_ns <= '0';
cmd_proc_ns <= '1';
over_ns <= '0';
split_out_ns <= '0';
end if;
-------------------------------------------------------------------
when SPLIT =>
cmd_proc_ns <= '1';
mm2s_ns <= SEND;
command_ns <= cache_info & mm2s_cmd (72+(C_ADDR_WIDTH-32) downto 65+(C_ADDR_WIDTH-32)) & split_cmd & mm2s_cmd (31) & eof_set & mm2s_cmd (29 downto 0); -- buf length remains the same
-- command_ns <= cache_info & mm2s_cmd (72 downto 65) & split_cmd & mm2s_cmd (31 downto 0); -- buf length remains the same
cmd_out_ns <= '0';
split_out_ns <= '1';
command_valid_ns <= '1';
-------------------------------------------------------------------
-- coverage off
when others =>
mm2s_ns <= IDLE;
-- coverage on
end case;
end process MM2S_MACHINE;
SWALLOW_TVALID : process(clock)
begin
if(clock'EVENT and clock = '1')then
if(sgresetn = '0')then
counter <= (others => '0');
-- tvalid_unsplit_int <= '0';
reset_lock <= '1';
ready_for_next_cmd <= '0';
elsif (vsize_data_int = "00000000000000000000000") then
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '1';
reset_lock <= '0';
elsif ((tvalid_from_datamover = '1') and (counter < vsize_data_int)) then
counter <= counter + '1';
-- tvalid_unsplit_int <= '0';
ready_for_next_cmd <= '0';
reset_lock <= '0';
elsif ((counter = vsize_data_int) and (reset_lock = '0') and (tvalid_from_datamover = '1')) then
counter <= (others => '0');
-- tvalid_unsplit_int <= '1';
ready_for_next_cmd <= '1';
else
counter <= counter;
-- tvalid_unsplit_int <= '0';
if (cmd_proc_cdc_from = '1') then
ready_for_next_cmd <= '0';
else
ready_for_next_cmd <= ready_for_next_cmd;
end if;
end if;
end if;
end process SWALLOW_TVALID;
tvalid_unsplit_int <= tvalid_from_datamover when (counter = vsize_data_int) else '0'; --tvalid_unsplit_int;
SWALLOW_TDATA : process(clock)
begin
if(clock'EVENT and clock = '1')then
if (sgresetn = '0' or cmd_in = '1') then
tvalid_unsplit <= '0';
status_out_int <= (others => '0');
else
tvalid_unsplit <= tvalid_unsplit_int;
if (tvalid_from_datamover = '1') then
status_out_int (C_DM_STATUS_WIDTH-2 downto 0) <= status_in (C_DM_STATUS_WIDTH-2 downto 0) or status_out_int (C_DM_STATUS_WIDTH-2 downto 0);
else
status_out_int <= status_out_int;
end if;
if (tvalid_unsplit_int = '1') then
status_out_int (C_DM_STATUS_WIDTH-1) <= status_in (C_DM_STATUS_WIDTH-1);
end if;
end if;
end if;
end process SWALLOW_TDATA;
status_out <= status_out_int;
SWALLOW_TLAST_GEN : if C_INCLUDE_S2MM = 0 generate
begin
eof_set <= '1'; --eof_bit when (vsize = vsize_data_int) else '0';
CDC_CMD_PROC1 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => cmd_proc_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => cmd_proc_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC2 : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => eof_bit_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock_sec,
scndry_resetn => '0',
scndry_out => eof_bit_cdc,
scndry_vect_out => open
);
CDC_CMD_PROC : process (clock_sec)
begin
if (clock_sec'EVENT and clock_sec = '1') then
if (aresetn = '0') then
-- cmd_proc_cdc_to <= '0';
-- cmd_proc_cdc <= '0';
-- eof_bit_cdc_to <= '0';
-- eof_bit_cdc <= '0';
ready_for_next_cmd_tlast_cdc_from <= '0';
else
-- cmd_proc_cdc_to <= cmd_proc_cdc_from;
-- cmd_proc_cdc <= cmd_proc_cdc_to;
-- eof_bit_cdc_to <= eof_bit_cdc_from;
-- eof_bit_cdc <= eof_bit_cdc_to;
ready_for_next_cmd_tlast_cdc_from <= ready_for_next_cmd_tlast;
end if;
end if;
end process CDC_CMD_PROC;
CDC_CMDTLAST_PROC : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => ready_for_next_cmd_tlast_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => clock,
scndry_resetn => '0',
scndry_out => ready_for_next_cmd_tlast_cdc,
scndry_vect_out => open
);
--CDC_CMDTLAST_PROC : process (clock)
-- begin
-- if (clock'EVENT and clock = '1') then
-- if (sgresetn = '0') then
-- ready_for_next_cmd_tlast_cdc_to <= '0';
-- ready_for_next_cmd_tlast_cdc <= '0';
-- else
-- ready_for_next_cmd_tlast_cdc_to <= ready_for_next_cmd_tlast_cdc_from;
-- ready_for_next_cmd_tlast_cdc <= ready_for_next_cmd_tlast_cdc_to;
-- end if;
-- end if;
--end process CDC_CMDTLAST_PROC;
SWALLOW_TLAST : process(clock_sec)
begin
if(clock_sec'EVENT and clock_sec = '1')then
if(aresetn = '0')then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '0';
reset_lock_tlast <= '1';
ready_for_next_cmd_tlast <= '1';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and vsize_data_int = "00000000000000000000000") then
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '1';
reset_lock_tlast <= '0';
elsif ((tlast_stream_data = '1' and tready_stream_data = '1') and (counter_tlast < vsize_data_int)) then
counter_tlast <= counter_tlast + '1';
tlast_stream_data_int <= '0';
ready_for_next_cmd_tlast <= '0';
reset_lock_tlast <= '0';
elsif ((counter_tlast = vsize_data_int) and (reset_lock_tlast = '0') and (tlast_stream_data = '1' and tready_stream_data = '1')) then
counter_tlast <= (others => '0');
tlast_stream_data_int <= '1';
ready_for_next_cmd_tlast <= '1';
else
counter_tlast <= counter_tlast;
tlast_stream_data_int <= '0';
if (cmd_proc_cdc = '1') then
ready_for_next_cmd_tlast <= '0';
else
ready_for_next_cmd_tlast <= ready_for_next_cmd_tlast;
end if;
end if;
end if;
end process SWALLOW_TLAST;
tlast_unsplit <= tlast_stream_data when (counter_tlast = vsize_data_int and eof_bit_cdc = '1') else '0';
tlast_unsplit_user <= tlast_stream_data when (counter_tlast = vsize_data_int) else '0';
-- tlast_unsplit <= tlast_stream_data; -- when (counter_tlast = vsize_data_int) else '0';
end generate SWALLOW_TLAST_GEN;
SWALLOW_TLAST_GEN_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
eof_set <= eof_bit_cdc_from;
ready_for_next_cmd_tlast_cdc <= '1';
end generate SWALLOW_TLAST_GEN_S2MM;
end implementation;
| mit | 8195921bcf14ededaf1054094af9641a | 0.50447 | 3.722956 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/fpu_d/imul53.vhd | 1 | 5,804 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity imul53 is
generic (
async_reset : boolean
);
port (
i_nrst : in std_logic;
i_clk : in std_logic;
i_ena : in std_logic;
i_a : in std_logic_vector(52 downto 0);
i_b : in std_logic_vector(52 downto 0);
o_result : out std_logic_vector(105 downto 0);
o_shift : out std_logic_vector(6 downto 0);
o_rdy : out std_logic;
o_overflow : out std_logic
);
end;
architecture arch_imul53 of imul53 is
type mux_type is array (16 downto 0) of std_logic_vector(56 downto 0);
type RegistersType is record
delay : std_logic_vector(15 downto 0);
shift : std_logic_vector(6 downto 0);
accum_ena : std_logic;
b : std_logic_vector(55 downto 0);
sum : std_logic_vector(105 downto 0);
overflow : std_logic;
end record;
constant R_RESET : RegistersType := (
(others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), '0');
signal r, rin : RegistersType;
begin
-- registers:
comb : process(i_nrst, i_ena, i_a, i_b, r)
variable v : RegistersType;
variable vb_mux : mux_type;
variable vb_sel : std_logic_vector(56 downto 0);
variable vb_shift : std_logic_vector(6 downto 0);
variable vb_sumInv : std_logic_vector(104 downto 0);
variable vb_lshift_p1 : integer range 0 to 104;
variable vb_lshift_p2 : integer range 0 to 104;
begin
v := r;
vb_mux(0) := (others => '0');
vb_mux(1) := "0000" & i_a; -- 1*a
vb_mux(2) := "000" & i_a & '0'; -- 2*a
vb_mux(3) := vb_mux(2) + vb_mux(1); -- 2*a + 1*a
vb_mux(4) := "00" & i_a & "00"; -- 4*a
vb_mux(5) := vb_mux(4) + vb_mux(1); -- 4*a + 1*a
vb_mux(6) := vb_mux(4) + vb_mux(2); -- 4*a + 2*a
vb_mux(8) := '0' & i_a & "000"; -- 8*a
vb_mux(7) := vb_mux(8) - vb_mux(1); -- 8*a - 1*a
vb_mux(9) := vb_mux(8) + vb_mux(1); -- 8*a + 1*a
vb_mux(10) := vb_mux(8) + vb_mux(2); -- 8*a + 2*a
vb_mux(11) := vb_mux(10) + vb_mux(1); -- (8*a + 2*a) + 1*a
vb_mux(12) := vb_mux(8) + vb_mux(4); -- 8*a + 4*a
vb_mux(16) := i_a & "0000"; -- unused
vb_mux(13) := vb_mux(16) - vb_mux(3); -- 16*a - (2*a + 1*a)
vb_mux(14) := vb_mux(16) - vb_mux(2); -- 16*a - 2*a
vb_mux(15) := vb_mux(16) - vb_mux(1); -- 16*a - 1*a
v.delay := r.delay(14 downto 0) & i_ena;
if i_ena = '1' then
v.b := "000" & i_b;
v.overflow := '0';
v.accum_ena := '1';
v.sum := (others => '0');
v.shift := (others => '0');
elsif r.delay(13) = '1' then
v.accum_ena := '0';
end if;
case r.b(55 downto 52) is
when X"1" => vb_sel := vb_mux(1);
when X"2" => vb_sel := vb_mux(2);
when X"3" => vb_sel := vb_mux(3);
when X"4" => vb_sel := vb_mux(4);
when X"5" => vb_sel := vb_mux(5);
when X"6" => vb_sel := vb_mux(6);
when X"7" => vb_sel := vb_mux(7);
when X"8" => vb_sel := vb_mux(8);
when X"9" => vb_sel := vb_mux(9);
when X"A" => vb_sel := vb_mux(10);
when X"B" => vb_sel := vb_mux(11);
when X"C" => vb_sel := vb_mux(12);
when X"D" => vb_sel := vb_mux(13);
when X"E" => vb_sel := vb_mux(14);
when X"F" => vb_sel := vb_mux(15);
when others =>
vb_sel := (others => '0');
end case;
if r.accum_ena = '1' then
v.sum := (r.sum(101 downto 0) & "0000") + vb_sel;
v.b := r.b(51 downto 0) & "0000";
end if;
-- To avoid timing constrains violation occured in Vivado Studio
-- try to implement parallel demuxultiplexer splitted on 2 parts
vb_sumInv(0) := '0';
for i in 0 to 103 loop
vb_sumInv(i + 1) := r.sum(103 - i);
end loop;
vb_lshift_p1 := 0;
for i in 0 to 63 loop
if vb_lshift_p1 = 0 and vb_sumInv(i) = '1' then
vb_lshift_p1 := i;
end if;
end loop;
vb_lshift_p2 := 0;
for i in 0 to 40 loop
if vb_lshift_p2 = 0 and vb_sumInv(64 + i) = '1' then
vb_lshift_p2 := 64 + i;
end if;
end loop;
if r.sum(105) = '1' then
vb_shift := "1111111";
v.overflow := '1';
elsif r.sum(104) = '1' then
vb_shift := (others => '0');
elsif vb_lshift_p1 /= 0 then
vb_shift := conv_std_logic_vector(vb_lshift_p1, 7);
else
vb_shift := conv_std_logic_vector(vb_lshift_p2, 7);
end if;
if r.delay(14) = '1' then
v.shift := vb_shift;
v.overflow := '0';
if vb_shift = "1111111" then
v.overflow := '1';
end if;
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
rin <= v;
end process;
o_result <= r.sum;
o_shift <= r.shift;
o_overflow <= r.overflow;
o_rdy <= r.delay(15);
-- registers:
regs : process(i_nrst, i_clk)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 5eeec5de1b8c3be2875a66698b3ae4b6 | 0.518952 | 2.845098 | false | false | false | false |
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`protect end_protected
| bsd-2-clause | d246d944b520cb95123a446f6d88f6a4 | 0.941419 | 1.85107 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/pll/SysPLL_k7.vhd | 1 | 7,557 | -- file: SysPLL_k7.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____40.000______0.000______50.0______135.255_____89.971
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________200.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_k7 is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_k7;
architecture xilinx of SysPLL_k7 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_k7,clk_wiz_v3_6,{component_name=SysPLL_k7,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 5.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 25.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 5.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_IN,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
| apache-2.0 | fc5d773f33ac1d0e829c2fc0e0dfdf99 | 0.587005 | 4.177446 | false | false | false | false |
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