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ObKo/USBCore | Core/ulpi_port.vhdl | 1 | 11,342 | --
-- USB Full-Speed/Hi-Speed Device Controller core - ulpi_port.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
--! ULPI PHY controller
entity ulpi_port is
generic (
HIGH_SPEED: boolean := true
);
port (
rst : in std_logic; --! Global external asynchronous reset
--! ULPI PHY signals
ulpi_data_in : in std_logic_vector(7 downto 0);
ulpi_data_out : out std_logic_vector(7 downto 0);
ulpi_dir : in std_logic;
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_reset : out std_logic;
ulpi_clk : in std_logic;
--! RX AXI-Stream, first data is PID
axis_rx_tvalid : out std_logic;
axis_rx_tready : in std_logic;
axis_rx_tlast : out std_logic;
axis_rx_tdata : out std_logic_vector(7 downto 0);
--! TX AXI-Stream, first data should be PID (in 4 least significant bits)
axis_tx_tvalid : in std_logic;
axis_tx_tready : out std_logic;
axis_tx_tlast : in std_logic;
axis_tx_tdata : in std_logic_vector(7 downto 0);
usb_vbus_valid : out std_logic; --! VBUS has valid voltage
usb_reset : out std_logic; --! USB bus is in reset state
usb_idle : out std_logic; --! USB bus is in idle state
usb_suspend : out std_logic --! USB bus is in suspend state
);
end ulpi_port;
architecture ulpi_port of ulpi_port is
constant SUSPEND_TIME : integer := 190000; -- = ~3 ms
constant RESET_TIME : integer := 190000; -- = ~3 ms
constant CHIRP_K_TIME : integer := 66000; -- = ~1 ms
constant CHIRP_KJ_TIME: integer := 120; -- = ~2 us
constant SWITCH_TIME : integer := 6000; -- = ~100 us
type MACHINE is (S_Init, S_WriteReg_A, S_WriteReg_D, S_STP, S_Reset, S_Suspend,
S_Idle, S_TX, S_TX_Last, S_ChirpStart, S_ChirpStartK, S_ChirpK,
S_ChirpKJ, S_SwitchFSStart, S_SwitchFS);
signal state : MACHINE;
signal state_after : MACHINE;
signal dir_d : std_logic;
signal tx_pid : std_logic_vector(3 downto 0);
signal reg_data : std_logic_vector(7 downto 0);
signal buf_data : std_logic_vector(7 downto 0);
signal buf_last : std_logic;
signal buf_valid : std_logic;
signal tx_eop : std_logic := '0';
signal bus_tx_ready : std_logic := '0';
signal chirp_kj_counter : std_logic_vector(2 downto 0);
signal hs_enabled : std_logic := '0';
signal usb_line_state : std_logic_vector(1 downto 0);
signal state_counter : std_logic_vector(17 downto 0);
signal packet : std_logic := '0';
signal packet_buf : std_logic_vector(7 downto 0);
begin
OUTER : process(ulpi_clk) is
begin
if rising_edge(ulpi_clk) then
if dir_d = ulpi_dir and ulpi_dir = '1' and ulpi_nxt = '1' then
packet_buf <= ulpi_data_in;
if packet = '0' then
axis_rx_tvalid <= '0';
packet <= '1';
else
axis_rx_tdata <= packet_buf;
axis_rx_tvalid <= '1';
end if;
axis_rx_tlast <= '0';
elsif packet = '1' and dir_d = ulpi_dir and
((ulpi_dir = '1' and ulpi_data_in(4) = '0') or (ulpi_dir = '0')) then
axis_rx_tdata <= packet_buf;
axis_rx_tvalid <= '1';
axis_rx_tlast <= '1';
packet <= '0';
else
axis_rx_tvalid <= '0';
axis_rx_tlast <= '0';
end if;
end if;
end process;
STATE_COUNT: process(ulpi_clk) is
begin
if rising_edge(ulpi_clk) then
if dir_d = ulpi_dir and ulpi_dir = '1' and ulpi_nxt = '0' AND ulpi_data_in(1 downto 0) /= usb_line_state then
if state = S_ChirpKJ then
if ulpi_data_in(1 downto 0) = "01" then
chirp_kj_counter <= chirp_kj_counter + 1;
end if;
else
chirp_kj_counter <= (others => '0');
end if;
usb_line_state <= ulpi_data_in(1 downto 0);
state_counter <= (others => '0');
elsif state = S_ChirpStartK then
state_counter <= (others => '0');
elsif state = S_SwitchFSStart then
state_counter <= (others => '0');
else
state_counter <= state_counter + 1;
end if;
end if;
end process;
FSM : process(ulpi_clk) is
begin
if rising_edge(ulpi_clk) then
dir_d <= ulpi_dir;
if dir_d = ulpi_dir then
if ulpi_dir = '1' and ulpi_nxt = '0' then
if ulpi_data_in(3 downto 2) = "11" then
usb_vbus_valid <= '1';
else
usb_vbus_valid <= '0';
end if;
elsif ulpi_dir = '0' then
case state is
when S_Init =>
ulpi_data_out <= X"8A";
reg_data <= X"00";
state <= S_WriteReg_A;
state_after <= S_SwitchFSStart;
when S_WriteReg_A =>
if ulpi_nxt = '1' then
ulpi_data_out <= reg_data;
state <= S_WriteReg_D;
end if;
when S_WriteReg_D =>
if ulpi_nxt = '1' then
ulpi_data_out <= X"00";
state <= S_STP;
end if;
when S_Reset =>
usb_reset <= '1';
if hs_enabled = '0' and HIGH_SPEED then
state <= S_ChirpStart;
elsif HIGH_SPEED then
state <= S_SwitchFSStart;
else
if usb_line_state /= "00" then
state <= S_Idle;
end if;
end if;
when S_Suspend =>
-- Should be J state for 20 ms, but I'm too lazy
-- FIXME: Need valid resume sequence for HS
if usb_line_state /= "01" then
state <= S_Idle;
end if;
when S_STP =>
state <= state_after;
when S_Idle =>
usb_reset <= '0';
if usb_line_state = "00" and state_counter > RESET_TIME then
state <= S_Reset;
elsif hs_enabled = '0' and usb_line_state = "01" and state_counter > SUSPEND_TIME then
state <= S_Suspend;
elsif bus_tx_ready = '1' and axis_tx_tvalid = '1' then
ulpi_data_out <= "0100" & axis_tx_tdata(3 downto 0);
buf_valid <= '0';
if axis_tx_tlast = '1' then
state <= S_TX_Last;
else
state <= S_TX;
end if;
end if;
when S_TX =>
if ulpi_nxt = '1' then
if axis_tx_tvalid = '1' and buf_valid = '0' then
ulpi_data_out <= axis_tx_tdata;
if axis_tx_tlast = '1' then
state <= S_TX_Last;
end if;
elsif buf_valid = '1' then
ulpi_data_out <= buf_data;
buf_valid <= '0';
if buf_last = '1' then
state <= S_TX_Last;
end if;
else
ulpi_data_out <= X"00";
end if;
else
if axis_tx_tvalid = '1' and buf_valid = '0' then
buf_data <= axis_tx_tdata;
buf_last <= axis_tx_tlast;
buf_valid <= '1';
end if;
end if;
when S_TX_Last =>
if ulpi_nxt = '1' then
ulpi_data_out <= X"00";
state_after <= S_Idle;
state <= S_STP;
end if;
when S_ChirpStart =>
reg_data <= b"0_1_0_10_1_00";
ulpi_data_out <= X"84";
state <= S_WriteReg_A;
state_after <= S_ChirpStartK;
when S_ChirpStartK =>
if ulpi_nxt = '1' then
ulpi_data_out <= X"00";
state <= S_ChirpK;
else
ulpi_data_out <= X"40";
end if;
when S_ChirpK =>
if state_counter > CHIRP_K_TIME then
ulpi_data_out <= X"00";
state <= S_STP;
state_after <= S_ChirpKJ;
end if;
when S_ChirpKJ =>
if chirp_kj_counter > 3 AND state_counter > CHIRP_KJ_TIME then
reg_data <= b"0_1_0_00_0_00";
ulpi_data_out <= X"84";
state <= S_WriteReg_A;
state_after <= S_Idle;
hs_enabled <= '1';
end if;
when S_SwitchFSStart =>
reg_data <= b"0_1_0_00_1_01";
ulpi_data_out <= X"84";
state <= S_WriteReg_A;
hs_enabled <= '0';
state_after <= S_SwitchFS;
when S_SwitchFS =>
if state_counter > SWITCH_TIME then
if usb_line_state = "00" AND HIGH_SPEED then
state <= S_ChirpStart;
else
state <= S_Idle;
end if;
end if;
end case;
end if;
end if;
end if;
end process;
ulpi_stp <= '1' when ulpi_dir = '1' and axis_rx_tready = '0' else
'1' when state = S_STP else
'0';
ulpi_reset <= rst;
bus_tx_ready <= '1' when ulpi_dir = '0' and ulpi_dir = dir_d else
'0';
axis_tx_tready <= '1' when bus_tx_ready = '1' and state = S_Idle else
'1' when bus_tx_ready = '1' and state = S_TX and buf_valid = '0' else
'0';
usb_idle <= '1' when state = S_Idle else
'0';
usb_suspend <= '1' when state = S_Suspend else
'0';
end ulpi_port;
| mit | 0df6a4c36261b6daab50ef6efc8ebcd6 | 0.487392 | 3.769359 | false | false | false | false |
peteut/nvc | test/sem/alias.vhd | 1 | 2,086 | entity e is
end entity;
architecture test of e is
alias my_int is integer; -- OK
signal x : my_int; -- OK
subtype s is my_int range 1 to 5; -- OK
alias my_bad : integer is integer; -- Error
alias ax is x; -- OK
signal y : ax; -- Error
alias as is s; -- OK
signal z : as; -- OK
function foo (x : bit) return integer;
function foo (x : character) return integer;
alias foo_bit is foo [bit return integer]; -- OK
alias foo_char is foo [character return integer]; -- OK
alias foo_int is foo [integer return integer]; -- Error
alias foo_p is foo [bit]; -- Error
alias foo_a is foo(1) [bit return integer]; -- Error
alias foo_b is foo [blah return integer]; -- Error
procedure bar (x : bit);
procedure bar (x : character);
alias bar_bit is bar [bit]; -- OK
alias bar_char is bar [character]; -- OK
alias bar_int is bar [integer]; -- Error
procedure test is
begin
assert foo_bit('1') = 1; -- OK
assert foo_char('1') = 1; -- OK
bar_bit('1'); -- OK
bar_char('1'); -- OK
assert foo('1') = 1; -- Error
assert foo_int(1) = 1; -- Error
bar_bit(character'(1)); -- Error
end procedure;
type bv_ptr is access bit_vector;
procedure test2(variable x : bv_ptr) is
variable v : bit_vector(1 to 10);
alias va is v(x'left); -- Error
begin
end procedure;
procedure maybe_use_last_value(signal x : my_int);
procedure proc is
begin
maybe_use_last_value(ax);
end procedure;
type int_array is array (integer range <>) of integer;
alias int_vector is int_array;
type int_array_2 is array (integer range <>) of integer;
constant c1 : int_array_2(1 to 3) := (1, 2, 3);
constant c2 : int_vector(1 to 3) := int_vector(c1); -- OK
begin
end architecture;
| gpl-3.0 | 28d2034d16fe22205378ad41313f54b0 | 0.526846 | 3.772152 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_rst_processing_system7_0_100M_0/synth/cpu_rst_processing_system7_0_100M_0.vhd | 1 | 6,773 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY cpu_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_rst_processing_system7_0_100M_0;
ARCHITECTURE cpu_rst_processing_system7_0_100M_0_arch OF cpu_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "cpu_rst_processing_system7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "cpu_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END cpu_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | 131dae441701593606b32dc4426f7dd5 | 0.716669 | 3.446819 | false | false | false | false |
UnofficialRepos/OSVVM | RandomPkg.vhd | 1 | 89,151 | --
-- File Name : RandomPkg.vhd
-- Design Unit Name : RandomPkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email: [email protected]
-- Lars Asplund email: [email protected] - RandBool, RandSl, RandBit, DistBool, DistSl, DistBit
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- RandomPType, a protected type, defined to hold randomization RandomSeeds and
-- function methods to facilitate randomization with uniform and weighted
-- distributions
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 06/2021 2021.06 Updated InitSeed, moved shared stuff to RandomBasePkg
-- 08/2020 2020.08 RandBool, RandSl, RandBit, DistBool, DistSl, DistBit (from Lars)
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 No changes. Updated release numbers to make documentation and
-- package have consistent release identifiers.
-- 5/2015 2015.06 Revised Alerts to Alert(OSVVM_ALERTLOG_ID, ...) ;
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 1/2014 2014.01 Added RandTime, RandReal(set), RandIntV, RandRealV, RandTimeV
-- Made sort, revsort from SortListPkg_int visible via aliases
-- 5/2013 2013.05 Big vector randomization added overloading RandUnsigned, RandSlv, and RandSigned
-- Added NULL_RANGE_TYPE to minimize null range warnings
-- 5/2013 - Removed extra variable declaration in functions RandInt and RandReal
-- 04/2013 2013.04 Changed DistInt. Return array indices now match input
-- Better Min, Max error handling in Uniform, FavorBig, FavorSmall, Normal, Poisson
-- 06/2012 2.2 Removed '_' in the name of subprograms FavorBig and FavorSmall
-- 07/2011 2.1 Bug fix to convenience functions for slv, unsigned, and signed.
-- 03/2011 2.0 Major clean-up. Moved RandomParmType and control to here
-- 06/2010 1.2 Added Normal and Poisson distributions
-- 02/2009 : 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- Numerous revisions for SynthWorks' Advanced VHDL Testbenches and Verification
-- 12/2006 : 0.1 Initial revision
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2021 by SynthWorks Design Inc.
-- Copyright (C) 2021 by OSVVM Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
-- comment out following 3 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
-- use ieee_proposed.standard_textio_additions.all ; -- remove with VHDL-2008
package RandomPkg is
-- make things from SortListPkg_int visible
-- alias sort is work.SortListPkg_int.sort [integer_vector return integer_vector] ;
-- alias revsort is work.SortListPkg_int.revsort[integer_vector return integer_vector] ;
-- Supports DistValInt functionality
type DistRecType is record
Value : integer ;
Weight : integer ;
end record ;
type DistType is array (natural range <>) of DistRecType ;
-- Weight vectors not indexed by integers
type NaturalVBoolType is array (boolean range <>) of natural;
type NaturalVSlType is array (std_logic range <>) of natural;
type NaturalVBitType is array (bit range <>) of natural;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
---
--- RandomPType
---
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
type RandomPType is protected
--- ///////////////////////////////////////////////////////////////////////////
---
--- Parameter Settings
---
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
-- Seed Manipulation
------------------------------------------------------------
-- Known ambiguity between InitSeed with string and integer_vector
-- Recommendation, use : RV.InitSeed(RV'instance_path) ;
-- For integer_vector use either : RV.InitSeed(IV => (1,5)) ;
-- or : RV.InitSeed(integer_vector'(1,5)) ;
-- Initialize Seeds
procedure InitSeed ( S : string ; UseNewSeedMethods : boolean := FALSE ) ;
procedure InitSeed ( I : integer ; UseNewSeedMethods : boolean := FALSE ) ;
procedure InitSeed ( T : time ; UseNewSeedMethods : boolean := TRUE ) ;
procedure InitSeed ( IV : integer_vector ; UseNewSeedMethods : boolean := FALSE ) ;
-- Save and restore seed values
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
procedure SeedRandom (RandomSeedIn : RandomSeedType ) ;
impure function SeedRandom return RandomSeedType ;
-- alias SeedRandom is SetSeed [RandomSeedType] ;
-- alias SeedRandom is GetSeed [return RandomSeedType] ;
------------------------------------------------------------
-- Setting Randomization Parameters
------------------------------------------------------------
procedure SetRandomParm (RandomParmIn : RandomParmType) ;
procedure SetRandomParm (
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) ;
impure function GetRandomParm return RandomParmType ;
impure function GetRandomParm return RandomDistType ;
-- For compatibility with previous version - replace with alias
procedure SetRandomMode (RandomDistIn : RandomDistType) ;
-- alias SetRandomMode is SetRandomParm [RandomDistType, Real, Real] ;
--- ///////////////////////////////////////////////////////////////////////////
---
--- Base Randomization Distributions
---
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
--
-- Uniform
-- Generate a random number with a Uniform distribution
--
------------------------------------------------------------
impure function Uniform (Min, Max : in real) return real ;
impure function Uniform (Min, Max : integer) return integer ;
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer ;
------------------------------------------------------------
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
------------------------------------------------------------
impure function FavorSmall (Min, Max : real) return real ;
impure function FavorSmall (Min, Max : integer) return integer ;
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer ;
------------------------------------------------------------
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
------------------------------------------------------------
impure function FavorBig (Min, Max : real) return real ;
impure function FavorBig (Min, Max : integer) return integer ;
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer ;
-----------------------------------------------------------------
--
-- Normal
-- Generate a random number with a normal distribution
-- Uses Box Muller, per Wikipedia
--
------------------------------------------------------------
impure function Normal (Mean, StdDeviation : real) return real ;
impure function Normal (Mean, StdDeviation, Min, Max : real) return real ;
impure function Normal (
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
-- Uses knuth method, per Wikipedia
--
------------------------------------------------------------
impure function Poisson (Mean : real) return real ;
impure function Poisson (Mean, Min, Max : real) return real ;
impure function Poisson (
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomization with range.
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandInt (Min, Max : integer) return integer ;
impure function RandReal (Min, Max : Real) return real ;
impure function RandTime (Min, Max : time ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Size : natural) return Signed ;
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector ;
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomization with range and exclude vector.
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer ;
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time ;
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return Signed ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector ;
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomly select a value within a set of values
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandInt (A : integer_vector ) return integer ;
impure function RandReal (A : real_vector ) return real ;
impure function RandTime (A : time_vector ) return time ;
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A : integer_vector ; Size : natural) return Signed ;
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandInt (A, Exclude : integer_vector ) return integer ;
impure function RandReal (A, Exclude : real_vector ) return real ;
impure function RandTime (A, Exclude : time_vector) return time ;
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned ;
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed ;
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector ;
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector ;
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector ;
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector ;
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Basic Discrete Distributions
-- Randomly select between 0 and N-1 based on the specified weight.
-- where N = number values in weight array
-- Always uses Uniform
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistInt (Weight : integer_vector ) return integer ;
impure function DistSlv (Weight : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned (Weight : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned (Weight : integer_vector ; Size : natural ) return signed ;
impure function DistBool (Weight : NaturalVBoolType ) return boolean ;
impure function DistSl (Weight : NaturalVSlType ) return std_logic ;
impure function DistBit (Weight : NaturalVBitType ) return bit ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistInt (Weight : integer_vector ; Exclude : integer_vector ) return integer ;
impure function DistSlv (Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector ;
impure function DistUnsigned (Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned ;
impure function DistSigned (Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Distribution for sparse values
-- Specify weight and value
-- Always uses Uniform via DistInt
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistValInt (A : DistType ) return integer ;
impure function DistValSlv (A : DistType ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned (A : DistType ; Size : natural) return unsigned ;
impure function DistValSigned (A : DistType ; Size : natural) return signed ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Specify weight and value
-- Always uses Uniform via DistInt
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistValInt (A : DistType ; Exclude : integer_vector ) return integer ;
impure function DistValSlv (A : DistType ; Exclude : integer_vector ; Size : natural) return std_logic_vector ;
impure function DistValUnsigned (A : DistType ; Exclude : integer_vector ; Size : natural) return unsigned ;
impure function DistValSigned (A : DistType ; Exclude : integer_vector ; Size : natural) return signed ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Large vector handling.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandUnsigned (Size : natural) return unsigned ;
impure function RandSlv (Size : natural) return std_logic_vector ;
impure function RandSigned (Size : natural) return signed ;
impure function RandUnsigned (Max : Unsigned) return unsigned ;
impure function RandSlv (Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Max : signed) return signed ;
impure function RandUnsigned (Min, Max : unsigned) return unsigned ;
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector ;
impure function RandSigned (Min, Max : signed) return signed ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Convenience Functions. Resolve into calls into the other functions
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandReal return real ; -- 0.0 to 1.0
impure function RandReal (Max : Real) return real ; -- 0.0 to Max
impure function RandInt (Max : integer) return integer ;
impure function RandSlv (Max, Size : natural) return std_logic_vector ;
impure function RandUnsigned (Max, Size : natural) return Unsigned ;
impure function RandSigned (Max : integer ; Size : natural ) return Signed ;
impure function RandBool return boolean;
impure function RandSl return std_logic;
impure function RandBit return bit;
end protected RandomPType ;
end RandomPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomPkg is
-----------------------------------------------------------------
-- Local Randomization Support
-----------------------------------------------------------------
constant NULL_SLV : std_logic_vector (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_UV : unsigned (NULL_RANGE_TYPE) := (others => '0') ;
constant NULL_SV : signed (NULL_RANGE_TYPE) := (others => '0') ;
--- ///////////////////////////////////////////////////////////////////////////
--- RandomPType Body
--- ///////////////////////////////////////////////////////////////////////////
type RandomPType is protected body
variable RandomSeed : RandomSeedType := OldGenRandSeed(integer_vector'(1,7)) ;
--- ///////////////////////////////////////////////////////////////////////////
---
--- Base Call to Uniform. Use this one rather than RandomBasePkg
---
--- ///////////////////////////////////////////////////////////////////////////
-----------------------------------------------------------------
impure function Uniform return real is
-----------------------------------------------------------------
variable rRandom : real ;
begin
ieee.math_real.Uniform (RandomSeed(RandomSeed'left), RandomSeed(RandomSeed'right), rRandom) ;
return rRandom ;
end function Uniform ;
--- ///////////////////////////////////////////////////////////////////////////
---
--- Seed Manipulation
---
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
procedure InitSeed (S : string ; UseNewSeedMethods : boolean := FALSE ) is
------------------------------------------------------------
variable ChurnSeed : real ;
begin
if UseNewSeedMethods then
RandomSeed := GenRandSeed(S) ;
Uniform(ChurnSeed, RandomSeed) ;
else
RandomSeed := OldGenRandSeed(S) ;
end if ;
end procedure InitSeed ;
------------------------------------------------------------
procedure InitSeed (I : integer ; UseNewSeedMethods : boolean := FALSE ) is
------------------------------------------------------------
variable ChurnSeed : real ;
begin
if UseNewSeedMethods then
RandomSeed := GenRandSeed(I) ;
Uniform(ChurnSeed, RandomSeed) ;
else
RandomSeed := OldGenRandSeed(I) ;
end if ;
end procedure InitSeed ;
------------------------------------------------------------
procedure InitSeed (T : time ; UseNewSeedMethods : boolean := TRUE ) is
------------------------------------------------------------
variable ChurnSeed : real ;
begin
-- Allow specification of UseNewSeedMethods
-- but ignore it as this is a new method and will churn the seed.
-- Let integer values roll over - is well supported, infact,
-- math_real.uniform depends on it being supported.
-- Also considered:
-- RandomSeed := GenRandSeed((T REM (2**30 * std.env.resolution_limit))/std.env.resolution_limit) ;
-- RandomSeed := GenRandSeed( (T - (T/2**30)*2**30) /std.env.resolution_limit) ;
-- However, GHDL does not support REM and the calculation is not warrented.
RandomSeed := GenRandSeed(T /std.env.resolution_limit) ;
Uniform(ChurnSeed, RandomSeed) ;
end procedure InitSeed ;
------------------------------------------------------------
procedure InitSeed (IV : integer_vector ; UseNewSeedMethods : boolean := FALSE ) is
------------------------------------------------------------
variable ChurnSeed : real ;
begin
if UseNewSeedMethods then
RandomSeed := GenRandSeed(IV) ;
Uniform(ChurnSeed, RandomSeed) ;
else
RandomSeed := OldGenRandSeed(IV) ;
end if ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
RandomSeed := RandomSeedIn ;
end procedure SetSeed ;
------------------------------------------------------------
procedure SeedRandom (RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
RandomSeed := RandomSeedIn ;
end procedure SeedRandom ;
------------------------------------------------------------
impure function GetSeed return RandomSeedType is
------------------------------------------------------------
begin
return RandomSeed ;
end function GetSeed ;
------------------------------------------------------------
impure function SeedRandom return RandomSeedType is
------------------------------------------------------------
begin
return RandomSeed ;
end function SeedRandom ;
--- ///////////////////////////////////////////////////////////////////////////
---
--- Setting Randomization Parameters
---
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
variable RandomParm : RandomParmType ; -- left most values ok for init
------------------------------------------------------------
procedure SetRandomParm (RandomParmIn : RandomParmType) is
------------------------------------------------------------
begin
RandomParm := RandomParmIn ;
end procedure SetRandomParm ;
------------------------------------------------------------
procedure SetRandomParm (
------------------------------------------------------------
Distribution : RandomDistType ;
Mean : Real := 0.0 ;
Deviation : Real := 0.0
) is
begin
RandomParm := RandomParmType'(Distribution, Mean, Deviation) ;
end procedure SetRandomParm ;
------------------------------------------------------------
impure function GetRandomParm return RandomParmType is
------------------------------------------------------------
begin
return RandomParm ;
end function GetRandomParm ;
------------------------------------------------------------
impure function GetRandomParm return RandomDistType is
------------------------------------------------------------
begin
return RandomParm.Distribution ;
end function GetRandomParm ;
------------------------------------------------------------
-- Deprecated. For compatibility with previous version
procedure SetRandomMode (RandomDistIn : RandomDistType) is
------------------------------------------------------------
begin
SetRandomParm(RandomDistIn) ;
end procedure SetRandomMode ;
--- ///////////////////////////////////////////////////////////////////////////
---
--- Check ranges for Randomization and Generate FAILURE
---
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
-- PT Local
impure function CheckMinMax(
------------------------------------------------------------
constant Name : in string ;
constant Min : in real ;
constant Max : in real
) return real is
begin
if Min > Max then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg." & Name &
": Min: " & to_string(Min, 2) &
" > Max: " & to_string(Max, 2),
FAILURE ) ;
return Min ;
else
return Max ;
end if;
end function CheckMinMax ;
------------------------------------------------------------
-- PT Local
impure function CheckMinMax(
------------------------------------------------------------
constant Name : in string ;
constant Min : in integer ;
constant Max : in integer
) return integer is
begin
if Min > Max then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg." & Name &
": Min: " & to_string(Min) &
" > Max: " & to_string(Max),
FAILURE ) ;
return Min ;
else
return Max ;
end if;
end function CheckMinMax ;
------------------------------------------------------------
-- PT Local
impure function CheckMinMax(
------------------------------------------------------------
constant Name : in string ;
constant Min : in time ;
constant Max : in time
) return time is
begin
if Min > Max then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg." & Name &
": Min: " & to_string(Min, ns) &
" > Max: " & to_string(Max, ns),
FAILURE ) ;
return Min ;
else
return Max ;
end if;
end function CheckMinMax ;
--- ///////////////////////////////////////////////////////////////////////////
---
--- Base Randomization Distributions
---
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
--
-- Uniform
-- Generate a random number with a Uniform distribution
--
------------------------------------------------------------
impure function LocalUniform (Min, Max : in real) return real is
------------------------------------------------------------
begin
return scale(Uniform, Min, Max) ;
end function LocalUniform ;
------------------------------------------------------------
impure function Uniform (Min, Max : in real) return real is
------------------------------------------------------------
constant CkMax : real := CheckMinMax("Uniform", Min, Max) ;
begin
return LocalUniform(Min, CkMax) ;
end function Uniform ;
------------------------------------------------------------
impure function LocalUniform (Min, Max : integer) return integer is
------------------------------------------------------------
begin
return scale(Uniform, Min, Max) ;
end function LocalUniform ;
------------------------------------------------------------
impure function Uniform (Min, Max : integer) return integer is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("Uniform", Min, Max) ;
begin
return LocalUniform(Min, CkMax) ;
end function Uniform ;
------------------------------------------------------------
impure function LocalUniform (Min, Max : integer ; Exclude : integer_vector) return integer is
------------------------------------------------------------
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
iRandomVal := Uniform(Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function LocalUniform ;
------------------------------------------------------------
impure function Uniform (Min, Max : integer ; Exclude : integer_vector) return integer is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("Uniform", Min, Max) ;
begin
return LocalUniform (Min, Max, Exclude) ;
end function Uniform ;
------------------------------------------------------------
--
-- FavorSmall
-- Generate random numbers with a greater number of small
-- values than large values
--
------------------------------------------------------------
impure function FavorSmall (Min, Max : real) return real is
------------------------------------------------------------
constant CkMax : real := CheckMinMax("FavorSmall", Min, Max) ;
begin
return scale(FavorSmall(Uniform), Min, CkMax) ; -- real
end function FavorSmall ;
------------------------------------------------------------
impure function FavorSmall (Min, Max : integer) return integer is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("FavorSmall", Min, Max) ;
begin
return scale(FavorSmall(Uniform), Min, CkMax) ; -- integer
end function FavorSmall ;
------------------------------------------------------------
impure function FavorSmall (Min, Max : integer ; Exclude : integer_vector) return integer is
------------------------------------------------------------
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
constant CkMax : integer := CheckMinMax("FavorSmall", Min, Max) ;
begin
ExcludeList.add(Exclude, Min, CkMax) ;
count := ExcludeList.count ;
iRandomVal := FavorSmall(Min, CkMax - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorSmall ;
------------------------------------------------------------
--
-- FavorBig
-- Generate random numbers with a greater number of large
-- values than small values
--
------------------------------------------------------------
impure function FavorBig (Min, Max : real) return real is
------------------------------------------------------------
constant CkMax : real := CheckMinMax("FavorBig", Min, Max) ;
begin
return scale(FavorBig(Uniform), Min, CkMax) ; -- real
end function FavorBig ;
------------------------------------------------------------
impure function FavorBig (Min, Max : integer) return integer is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("FavorBig", Min, Max) ;
begin
return scale(FavorBig(Uniform), Min, CkMax) ; -- integer
end function FavorBig ;
------------------------------------------------------------
impure function FavorBig (Min, Max : integer ; Exclude : integer_vector) return integer is
------------------------------------------------------------
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
constant CkMax : integer := CheckMinMax("FavorBig", Min, Max) ;
begin
ExcludeList.add(Exclude, Min, CkMax) ;
count := ExcludeList.count ;
iRandomVal := FavorBig(Min, CkMax - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
return iRandomVal ;
end function FavorBig ;
-----------------------------------------------------------------
--
-- Normal
-- Generate a random number with a normal distribution
--
-- Use Box Muller, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Box%E2%80%93Muller_transform
--
------------------------------------------------------------
impure function Normal (Mean, StdDeviation : real) return real is
------------------------------------------------------------
variable x01, y01 : real ;
variable StdNormalDist : real ; -- mean 0, variance 1
begin
-- add this check to set parameters?
if StdDeviation < 0.0 then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.Normal: Standard deviation must be >= 0.0", FAILURE) ;
return -1.0 ;
end if ;
-- Box Muller
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
x01 := Uniform ;
y01 := Uniform ;
StdNormalDist := sqrt(-2.0 * log(x01)) * cos(math_2_pi*y01) ;
-- Polar form rejected due to mean 50.0, std deviation = 5 resulted
-- in a median of 49
-- -- find two Uniform distributed values with range -1 to 1
-- -- that satisify S = X **2 + Y**2 < 1.0
-- loop
-- Uniform (x01, RandomSeed) ;
-- Uniform (y01, RandomSeed) ;
-- x := 2.0 * x01 - 1.0 ; -- scale to -1 to 1
-- y := 2.0 * y01 - 1.0 ;
-- s := x*x + y*y ;
-- exit when s < 1.0 and s > 0.0 ;
-- end loop ;
-- -- Calculate Standard Normal Distribution
-- StdNormalDist := x * sqrt((-2.0 * log(s)) / s) ;
-- Convert to have Mean and StdDeviation
return StdDeviation * StdNormalDist + Mean ;
end function Normal ;
------------------------------------------------------------
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (Mean, StdDeviation, Min, Max : real) return real is
------------------------------------------------------------
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg.Normal: Min: " & to_string(Min, 2) &
" > Max: " & to_string(Max, 2),
FAILURE) ;
return Mean ;
else
loop
rRandomVal := Normal (Mean, StdDeviation) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Normal ;
------------------------------------------------------------
-- Normal + RandomVal >= Min and RandomVal <= Max
impure function Normal (
------------------------------------------------------------
Mean : real ;
StdDeviation : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg.Normal: Min: " & to_string(Min) &
" > Max: " & to_string(Max),
FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Normal(Mean, StdDeviation) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Normal ;
-----------------------------------------------------------------
-- Poisson
-- Generate a random number with a poisson distribution
-- Discrete distribution = only generates integral values
--
-- Use knuth method, per Wikipedia :
-- http ://en.wikipedia.org/wiki/Poisson_distribution
--
------------------------------------------------------------
impure function Poisson (Mean : real) return real is
------------------------------------------------------------
variable Product : Real := 1.0 ;
variable Bound : Real := 0.0 ;
variable UniformRand : Real := 0.0 ;
variable PoissonRand : Real := 0.0 ;
begin
Bound := exp(-1.0 * Mean) ;
Product := 1.0 ;
-- add this check to set parameters?
if Mean <= 0.0 or Bound <= 0.0 then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.Poisson: Mean < 0 or too large. Mean = " & real'image(Mean), FAILURE) ;
return Mean ;
end if ;
while (Product >= Bound) loop
PoissonRand := PoissonRand + 1.0 ;
UniformRand := Uniform ;
Product := Product * UniformRand ;
end loop ;
return PoissonRand ;
end function Poisson ; -- no range
------------------------------------------------------------
-- Poisson + RandomVal >= Min and RandomVal < Max
impure function Poisson (Mean, Min, Max : real) return real is
------------------------------------------------------------
variable rRandomVal : real ;
begin
if Max < Min then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg.Poisson: Min: " & to_string(Min, 2) &
" > Max: " & to_string(Max, 2),
FAILURE) ;
return Mean ;
else
loop
rRandomVal := Poisson (Mean) ;
exit when rRandomVal >= Min and rRandomVal <= Max ;
end loop ;
end if ;
return rRandomVal ;
end function Poisson ;
------------------------------------------------------------
impure function Poisson (
------------------------------------------------------------
Mean : real ;
Min : integer ;
Max : integer ;
Exclude : integer_vector := NULL_INTV
) return integer is
variable iRandomVal : integer ;
begin
if Max < Min then
Alert(OSVVM_RANDOM_ALERTLOG_ID,
"RandomPkg.Poisson: Min: " & to_string(Min) &
" > Max: " & to_string(Max),
FAILURE) ;
return integer(round(Mean)) ;
else
loop
iRandomVal := integer(round( Poisson (Mean) )) ;
exit when iRandomVal >= Min and iRandomVal <= Max and
not inside(iRandomVal, Exclude) ;
end loop ;
end if ;
return iRandomVal ;
end function Poisson ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomization with range.
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function LocalRandInt (Min, Max : integer) return integer is
------------------------------------------------------------
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return LocalUniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandInt: RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function LocalRandInt ;
------------------------------------------------------------
impure function RandInt (Min, Max : integer) return integer is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandInt", Min, Max) ;
begin
return LocalRandInt(Min, CkMax) ;
end function RandInt ;
------------------------------------------------------------
impure function RandSlv (Min, Max, Size : natural) return std_logic_vector is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandSlv", Min, Max) ;
begin
return std_logic_vector(to_unsigned(LocalRandInt(Min, CkMax), Size)) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandUnsigned (Min, Max, Size : natural) return Unsigned is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandUnsigned", Min, Max) ;
begin
return to_unsigned(LocalRandInt(Min, CkMax), Size) ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSigned (Min, Max : integer ; Size : natural ) return Signed is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandSigned", Min, Max) ;
begin
return to_signed(LocalRandInt(Min, CkMax), Size) ;
end function RandSigned ;
------------------------------------------------------------
impure function RandIntV (Min, Max : integer ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
constant CkMax : integer := CheckMinMax("RandIntV", Min, Max) ;
begin
for i in result'range loop
result(i) := LocalRandInt(Min, CkMax) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function RandIntV (Min, Max : integer ; Unique : natural ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
iUnique := Unique ;
if Max-Min+1 < Unique then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.(RandIntV | RandRealV | RandTimeV): Unique > number of values available", FAILURE) ;
iUnique := Max-Min+1 ;
end if ;
for i in result'range loop
result(i) := RandInt(Min, Max, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function LocalRandReal(Min, Max : Real) return real is
------------------------------------------------------------
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return LocalUniform(Min, Max) ;
when FAVOR_SMALL => return FavorSmall(Min, Max) ;
when FAVOR_BIG => return FavorBig (Min, Max) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max) ;
when others =>
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandReal: Specified RandomParm.Distribution not implemented", FAILURE) ;
return real(integer'low) ;
end case ;
end function LocalRandReal ;
------------------------------------------------------------
impure function RandReal(Min, Max : Real) return real is
------------------------------------------------------------
constant CkMax : real := CheckMinMax("RandReal", Min, Max) ;
begin
return LocalRandReal(Min, CkMax) ;
end function RandReal ;
------------------------------------------------------------
impure function RandRealV (Min, Max : real ; Size : natural) return real_vector is
------------------------------------------------------------
variable result : real_vector(1 to Size) ;
constant CkMax : real := CheckMinMax("RandRealV", Min, Max) ;
begin
for i in result'range loop
result(i) := LocalRandReal(Min, CkMax) ;
end loop ;
return result ;
end function RandRealV ;
------------------------------------------------------------
impure function LocalRandTime (Min, Max : time ; Unit :time := ns) return time is
------------------------------------------------------------
variable IntVal : integer ;
begin
-- if Max - Min > 2**31 result will be out of range
IntVal := LocalRandInt(0, (Max - Min)/Unit) ;
return Min + Unit*IntVal ;
end function LocalRandTime ;
------------------------------------------------------------
impure function RandTime (Min, Max : time ; Unit :time := ns) return time is
------------------------------------------------------------
constant CkMax : time := CheckMinMax("RandTime", Min, Max) ;
begin
return LocalRandTime (Min, CkMax, Unit) ;
end function RandTime ;
------------------------------------------------------------
impure function RandTimeV (Min, Max : time ; Size : natural ; Unit : time := ns) return time_vector is
------------------------------------------------------------
variable result : time_vector(1 to Size) ;
constant CkMax : time := CheckMinMax("RandTimeV", Min, Max) ;
begin
for i in result'range loop
result(i) := LocalRandTime(Min, CkMax, Unit) ;
end loop ;
return result ;
end function RandTimeV ;
------------------------------------------------------------
impure function RandTimeV (Min, Max : time ; Unique : natural ; Size : natural ; Unit : time := ns) return time_vector is
------------------------------------------------------------
constant CkMax : time := CheckMinMax("RandTimeV", Min, Max) ;
begin
-- if Unique = 0, it is more efficient to call RandTimeV(Min, Max, Size)
return to_time_vector(RandIntV(Min/Unit, CkMax/Unit, Unique, Size), Unit) ;
end function RandTimeV ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomization with range and exclude vector.
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function LocalRandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
------------------------------------------------------------
begin
case RandomParm.Distribution is
when NONE | UNIFORM => return LocalUniform(Min, Max, Exclude) ;
when FAVOR_SMALL => return FavorSmall(Min, Max, Exclude) ;
when FAVOR_BIG => return FavorBig (Min, Max, Exclude) ;
when NORMAL => return Normal(RandomParm.Mean, RandomParm.StdDeviation, Min, Max, Exclude) ;
when POISSON => return Poisson(RandomParm.Mean, Min, Max, Exclude) ;
when others =>
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandInt: Specified RandomParm.Distribution not implemented", FAILURE) ;
return integer'low ;
end case ;
end function LocalRandInt ;
------------------------------------------------------------
impure function RandInt (Min, Max : integer ; Exclude : integer_vector ) return integer is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandInt", Min, Max) ;
begin
return LocalRandInt(Min, CkMax, Exclude) ;
end function RandInt ;
------------------------------------------------------------
impure function RandSlv (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandSlv", Min, Max) ;
begin
return std_logic_vector(to_unsigned(RandInt(Min, CkMax, Exclude), Size)) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandUnsigned (Min, Max : natural ; Exclude : integer_vector ; Size : natural ) return Unsigned is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandUnsigned", Min, Max) ;
begin
return to_unsigned(RandInt(Min, CkMax, Exclude), Size) ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSigned (Min, Max : integer ; Exclude : integer_vector ; Size : natural ) return Signed is
------------------------------------------------------------
constant CkMax : integer := CheckMinMax("RandSigned", Min, Max) ;
begin
return to_signed(RandInt(Min, CkMax, Exclude), Size) ;
end function RandSigned ;
------------------------------------------------------------
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
constant CkMax : integer := CheckMinMax("RandIntV", Min, Max) ;
begin
for i in result'range loop
result(i) := RandInt(Min, CkMax, Exclude) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function RandIntV (Min, Max : integer ; Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
------------------------------------------------------------
variable ResultPlus : integer_vector(1 to Size + Exclude'length) ;
constant CkMax : integer := CheckMinMax("RandIntV", Min, Max) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
ResultPlus(Size+1 to ResultPlus'right) := Exclude ;
for i in 1 to Size loop
ResultPlus(i) := RandInt(Min, CkMax, ResultPlus(maximum(1, 1 + i - Unique) to ResultPlus'right)) ;
end loop ;
return ResultPlus(1 to Size) ;
end function RandIntV ;
------------------------------------------------------------
impure function RandTime (Min, Max : time ; Exclude : time_vector ; Unit : time := ns) return time is
------------------------------------------------------------
variable IntVal : integer ;
constant CkMax : time := CheckMinMax("RandTime", Min, Max) ;
begin
-- if Min or Max > 2**31 value will be out of range
return RandInt(Min/Unit, Max/Unit, to_integer_vector(Exclude, Unit)) * Unit ;
end function RandTime ;
------------------------------------------------------------
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Size : natural ; Unit : in time := ns) return time_vector is
------------------------------------------------------------
constant CkMax : time := CheckMinMax("RandTimeV", Min, Max) ;
begin
return to_time_vector( RandIntV(Min/Unit, CkMax/Unit, to_integer_vector(Exclude, Unit), Size), Unit ) ;
end function RandTimeV ;
------------------------------------------------------------
impure function RandTimeV (Min, Max : time ; Exclude : time_vector ; Unique : natural ; Size : natural ; Unit : in time := ns) return time_vector is
------------------------------------------------------------
constant CkMax : time := CheckMinMax("RandTimeV", Min, Max) ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
return to_time_vector( RandIntV(Min/Unit, CkMax/Unit, to_integer_vector(Exclude, Unit), Unique, Size), Unit ) ;
end function RandTimeV ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomly select a value within a set of values
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandInt ( A : integer_vector ) return integer is
------------------------------------------------------------
alias A_norm : integer_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandInt ;
------------------------------------------------------------
impure function RandReal ( A : real_vector ) return real is
------------------------------------------------------------
alias A_norm : real_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandReal ;
------------------------------------------------------------
impure function RandTime ( A : time_vector ) return time is
------------------------------------------------------------
alias A_norm : time_vector(1 to A'length) is A ;
begin
return A_norm( RandInt(1, A'length) ) ;
end function RandTime ;
------------------------------------------------------------
impure function RandSlv (A : integer_vector ; Size : natural) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(RandInt(A), Size)) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandUnsigned (A : integer_vector ; Size : natural) return Unsigned is
------------------------------------------------------------
begin
return to_unsigned(RandInt(A), Size) ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSigned (A : integer_vector ; Size : natural ) return Signed is
------------------------------------------------------------
begin
return to_signed(RandInt(A), Size) ;
end function RandSigned ;
------------------------------------------------------------
impure function RandIntV (A : integer_vector ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandInt(A) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function RandIntV (A : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
variable iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(A, Size)
-- require A'length >= Unique
iUnique := Unique ;
if A'length < Unique then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > length of set of values", FAILURE) ;
iUnique := A'length ;
end if ;
for i in result'range loop
result(i) := RandInt(A, result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function RandRealV (A : real_vector ; Size : natural) return real_vector is
------------------------------------------------------------
variable result : real_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandReal(A) ;
end loop ;
return result ;
end function RandRealV ;
------------------------------------------------------------
impure function RandRealV (A : real_vector ; Unique : natural ; Size : natural) return real_vector is
------------------------------------------------------------
alias A_norm : real_vector(1 to A'length) is A ;
variable result : real_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandRealV ;
------------------------------------------------------------
impure function RandTimeV (A : time_vector ; Size : natural) return time_vector is
------------------------------------------------------------
variable result : time_vector(1 to Size) ;
begin
for i in result'range loop
result(i) := RandTime(A) ;
end loop ;
return result ;
end function RandTimeV ;
------------------------------------------------------------
impure function RandTimeV (A : time_vector ; Unique : natural ; Size : natural) return time_vector is
------------------------------------------------------------
alias A_norm : time_vector(1 to A'length) is A ;
variable result : time_vector(1 to Size) ;
variable IntResult : integer_vector(result'range) ;
begin
-- randomly generate indices
IntResult := RandIntV(1, A'length, Unique, Size) ;
-- translate indicies into result values
for i in result'range loop
result(i) := A_norm(IntResult(i)) ;
end loop ;
return result ;
end function RandTimeV ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Randomly select a value within a set of values with exclude values (so can skip last or last n)
-- Uses internal settings of RandomParm to deterimine distribution.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandInt ( A, Exclude : integer_vector ) return integer is
------------------------------------------------------------
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandInt ;
------------------------------------------------------------
impure function RandReal ( A, Exclude : real_vector ) return real is
------------------------------------------------------------
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandReal ;
------------------------------------------------------------
impure function RandTime ( A, Exclude : time_vector ) return time is
------------------------------------------------------------
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
return NewA(RandInt(1, NewALength)) ;
end function RandTime ;
------------------------------------------------------------
impure function RandSlv (A, Exclude : integer_vector ; Size : natural) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(RandInt(A, Exclude), Size)) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandUnsigned (A, Exclude : integer_vector ; Size : natural) return Unsigned is
------------------------------------------------------------
begin
return to_unsigned(RandInt(A, Exclude), Size) ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSigned (A, Exclude : integer_vector ; Size : natural ) return Signed is
------------------------------------------------------------
begin
return to_signed(RandInt(A, Exclude), Size) ;
end function RandSigned ;
------------------------------------------------------------
impure function RandIntV (A, Exclude : integer_vector ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function RandIntV (A, Exclude : integer_vector ; Unique : natural ; Size : natural) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(1 to Size) ;
variable NewA : integer_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandIntV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandIntV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandInt(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandIntV ;
------------------------------------------------------------
impure function RandRealV (A, Exclude : real_vector ; Size : natural) return real_vector is
------------------------------------------------------------
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandRealV ;
------------------------------------------------------------
impure function RandRealV (A, Exclude : real_vector ; Unique : natural ; Size : natural) return real_vector is
------------------------------------------------------------
variable result : real_vector(1 to Size) ;
variable NewA : real_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandRealV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandReal(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandRealV ;
------------------------------------------------------------
impure function RandTimeV (A, Exclude : time_vector ; Size : natural) return time_vector is
------------------------------------------------------------
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength : natural ;
begin
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Randomize Index
for i in result'range loop
result(i) := NewA(RandInt(1, NewALength)) ;
end loop ;
return result ;
end function RandTimeV ;
------------------------------------------------------------
impure function RandTimeV (A, Exclude : time_vector ; Unique : natural ; Size : natural) return time_vector is
------------------------------------------------------------
variable result : time_vector(1 to Size) ;
variable NewA : time_vector(1 to A'length) ;
variable NewALength, iUnique : natural ;
begin
-- if Unique = 0, it is more efficient to call RandRealV(Min, Max, Size)
-- Remove Exclude from A
RemoveExclude(A, Exclude, NewA, NewALength) ;
-- Require NewALength >= Unique
iUnique := Unique ;
if NewALength < Unique then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandTimeV: Unique > Length of Set A - Exclude", FAILURE) ;
iUnique := NewALength ;
end if ;
-- Randomize using exclude list of Unique # of newly generated values
for i in result'range loop
result(i) := RandTime(NewA(1 to NewALength), result(maximum(1, 1 + i - iUnique) to Size)) ;
end loop ;
return result ;
end function RandTimeV ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistInt ( Weight : integer_vector ) return integer is
------------------------------------------------------------
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
iRandomVal := Uniform(1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
return i ;
end if ;
end loop ;
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
return DistArray'low ; -- allows debugging vs integer'left, out of range
end function DistInt ;
------------------------------------------------------------
impure function DistSlv ( Weight : integer_vector ; Size : natural ) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(DistInt(Weight), Size)) ;
end function DistSlv ;
------------------------------------------------------------
impure function DistUnsigned ( Weight : integer_vector ; Size : natural ) return unsigned is
------------------------------------------------------------
begin
return to_unsigned(DistInt(Weight), Size) ;
end function DistUnsigned ;
------------------------------------------------------------
impure function DistSigned ( Weight : integer_vector ; Size : natural ) return signed is
------------------------------------------------------------
begin
return to_signed(DistInt(Weight), Size) ;
end function DistSigned ;
------------------------------------------------------------
impure function DistBool ( Weight : NaturalVBoolType ) return boolean is
------------------------------------------------------------
variable FullWeight : integer_vector(0 to 1) := (others => 0);
begin
for i in Weight'range loop
FullWeight(boolean'pos(i)) := Weight(i) ;
end loop ;
return boolean'val(DistInt(FullWeight)) ;
end function DistBool ;
------------------------------------------------------------
impure function DistSl ( Weight : NaturalVSlType ) return std_logic is
------------------------------------------------------------
variable FullWeight : integer_vector(0 to 8) := (others => 0);
begin
for i in Weight'range loop
FullWeight(std_logic'pos(i)) := Weight(i) ;
end loop ;
return std_logic'val(DistInt(FullWeight)) ;
end function DistSl ;
------------------------------------------------------------
impure function DistBit ( Weight : NaturalVBitType ) return bit is
------------------------------------------------------------
variable FullWeight : integer_vector(0 to 1) := (others => 0);
begin
for i in Weight'range loop
FullWeight(bit'pos(i)) := Weight(i) ;
end loop ;
return bit'val(DistInt(FullWeight)) ;
end function DistBit ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Basic Distributions with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistInt ( Weight : integer_vector ; Exclude : integer_vector ) return integer is
------------------------------------------------------------
variable DistArray : integer_vector(weight'range) ;
variable ExcludeTemp : integer ;
begin
DistArray := Weight ;
for i in Exclude'range loop
ExcludeTemp := Exclude(i) ;
if ExcludeTemp >= DistArray'low and ExcludeTemp <= DistArray'high then
DistArray(ExcludeTemp) := 0 ;
end if ;
end loop ;
return DistInt(DistArray) ;
end function DistInt ;
------------------------------------------------------------
impure function DistSlv ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(DistInt(Weight, Exclude), Size)) ;
end function DistSlv ;
------------------------------------------------------------
impure function DistUnsigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return unsigned is
------------------------------------------------------------
begin
return to_unsigned(DistInt(Weight, Exclude), Size) ;
end function DistUnsigned ;
------------------------------------------------------------
impure function DistSigned ( Weight : integer_vector ; Exclude : integer_vector ; Size : natural ) return signed is
------------------------------------------------------------
begin
return to_signed(DistInt(Weight, Exclude), Size) ;
end function DistSigned ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Distribution for sparse values
-- Always uses Uniform via DistInt
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistValInt ( A : DistType ) return integer is
------------------------------------------------------------
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistArray'range loop
DistArray(i) := DistRecArray(i).Weight ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
------------------------------------------------------------
impure function DistValSlv ( A : DistType ; Size : natural ) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(DistValInt(A), Size)) ;
end function DistValSlv ;
------------------------------------------------------------
impure function DistValUnsigned ( A : DistType ; Size : natural ) return unsigned is
------------------------------------------------------------
begin
return to_unsigned(DistValInt(A), Size) ;
end function DistValUnsigned ;
------------------------------------------------------------
impure function DistValSigned ( A : DistType ; Size : natural ) return signed is
------------------------------------------------------------
begin
return to_signed(DistValInt(A), Size) ;
end function DistValSigned ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Distribution for sparse values with exclude values (so can skip last or last n)
-- Always uses Uniform via DistInt
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function DistValInt ( A : DistType ; Exclude : integer_vector ) return integer is
------------------------------------------------------------
variable DistArray : integer_vector(0 to A'length -1) ;
alias DistRecArray : DistType(DistArray'range) is A ;
begin
for i in DistRecArray'range loop
if inside(DistRecArray(i).Value, exclude) then
DistArray(i) := 0 ; -- exclude
else
DistArray(i) := DistRecArray(i).Weight ;
end if ;
end loop ;
return DistRecArray(DistInt(DistArray)).Value ;
end function DistValInt ;
------------------------------------------------------------
impure function DistValSlv ( A : DistType ; Exclude : integer_vector ; Size : natural ) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(DistValInt(A, Exclude), Size)) ;
end function DistValSlv ;
------------------------------------------------------------
impure function DistValUnsigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return unsigned is
------------------------------------------------------------
begin
return to_unsigned(DistValInt(A, Exclude), Size) ;
end function DistValUnsigned ;
------------------------------------------------------------
impure function DistValSigned ( A : DistType ; Exclude : integer_vector ; Size : natural ) return signed is
------------------------------------------------------------
begin
return to_signed(DistValInt(A, Exclude), Size) ;
end function DistValSigned ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Large vector handling.
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandUnsigned (Size : natural) return unsigned is
------------------------------------------------------------
constant NumLoops : integer := integer(ceil(real(Size)/30.0)) ;
constant Remain : integer := (Size - 1) mod 30 + 1 ; -- range 1 to 30
variable RandVal : unsigned(1 to Size) ;
begin
if size = 0 then
return NULL_UV ; -- Null array
end if ;
for i in 0 to NumLoops-2 loop
RandVal(1 + 30*i to 30 + 30*i) := to_unsigned(RandInt(0, 2**30-1), 30) ;
end loop ;
RandVal(1+30*(NumLoops-1) to Remain + 30*(NumLoops-1)) := to_unsigned(RandInt(0, 2**Remain-1), Remain) ;
return RandVal ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSlv (Size : natural) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(RandUnsigned(Size)) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandSigned (Size : natural) return signed is
------------------------------------------------------------
begin
return signed(RandUnsigned(Size)) ;
end function RandSigned ;
------------------------------------------------------------
impure function SizeByLeftMostBit (A : unsigned) return integer is
------------------------------------------------------------
alias normA : unsigned (A'length downto 1) is A ;
begin
for i in normA'range loop
if normA(i) = '1' then
return i ;
end if ;
end loop ;
return -1 ;
end function SizeByLeftMostBit ;
------------------------------------------------------------
impure function RandUnsigned (Max : unsigned) return unsigned is
------------------------------------------------------------
alias normMax : unsigned (Max'length downto 1) is Max ;
variable Result : unsigned(Max'range) := (others => '0') ;
alias normResult : unsigned(normMax'range) is Result ;
variable Size : integer ;
begin
-- Size = -1 if not found or Max'length = 0
Size := SizeByLeftMostBit(Max) ;
if Size > 0 then
loop
normResult(Size downto 1) := RandUnsigned(Size) ;
exit when normResult <= Max ;
end loop ;
return Result ; -- = normResult with range same as Max
else
return resize("0", Max'length) ;
end if ;
end function RandUnsigned ;
-- Working version that scales the value
-- impure function RandUnsigned (Max : unsigned) return unsigned is
-- constant MaxVal : unsigned(Max'length+3 downto 1) := (others => '1') ;
-- begin
-- if max'length > 0 then
-- -- "Max'length+3" creates 3 guard bits
-- return resize( RandUnsigned(Max'length+3) * ('0'&Max+1) / ('0'&MaxVal+1), Max'length) ;
-- else
-- return NULL_UV ; -- Null Array
-- end if ;
-- end function RandUnsigned ;
------------------------------------------------------------
impure function RandSlv (Max : std_logic_vector) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(RandUnsigned( unsigned(Max))) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandSigned (Max : signed) return signed is
------------------------------------------------------------
begin
if max'length > 0 then
AlertIf (OSVVM_RANDOM_ALERTLOG_ID, Max < 0, "RandomPkg.RandSigned: Max < 0", FAILURE) ;
return signed(RandUnsigned( unsigned(Max))) ;
else
return NULL_SV ; -- Null Array
end if ;
end function RandSigned ;
------------------------------------------------------------
impure function RandUnsigned (Min, Max : unsigned) return unsigned is
------------------------------------------------------------
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandUnsigned(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandUnsigned: Max < Min", FAILURE) ;
end if ;
return NULL_UV ;
end if ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSlv (Min, Max : std_logic_vector) return std_logic_vector is
------------------------------------------------------------
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return RandSlv(Max-Min) + Min ;
else
if Len > 0 then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandSlv: Max < Min", FAILURE) ;
end if ;
return NULL_SlV ;
end if ;
end function RandSlv ;
------------------------------------------------------------
impure function RandSigned (Min, Max : signed) return signed is
------------------------------------------------------------
constant LEN : integer := maximum(Max'length, Min'length) ;
begin
if LEN > 0 and Min <= Max then
return resize(RandSigned(resize(Max,LEN+1) - resize(Min,LEN+1)) + Min, LEN) ;
else
if Len > 0 then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.RandSigned: Max < Min", FAILURE) ;
end if ;
return NULL_SV ;
end if ;
end function RandSigned ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Convenience Functions. Resolve into calls into the other functions
--
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
impure function RandReal return real is
------------------------------------------------------------
begin
return RandReal(0.0, 1.0) ;
end function RandReal ;
------------------------------------------------------------
impure function RandReal(Max : Real) return real is -- 0.0 to Max
------------------------------------------------------------
begin
return RandReal(0.0, Max) ;
end function RandReal ;
------------------------------------------------------------
impure function RandInt (Max : integer) return integer is
------------------------------------------------------------
begin
return RandInt(0, Max) ;
end function RandInt ;
------------------------------------------------------------
impure function RandSlv (Max, Size : natural) return std_logic_vector is
------------------------------------------------------------
begin
return std_logic_vector(to_unsigned(RandInt(0, Max), Size)) ;
end function RandSlv ;
------------------------------------------------------------
impure function RandUnsigned (Max, Size : natural) return Unsigned is
------------------------------------------------------------
begin
return to_unsigned(RandInt(0, Max), Size) ;
end function RandUnsigned ;
------------------------------------------------------------
impure function RandSigned (Max : integer ; Size : natural ) return Signed is
------------------------------------------------------------
begin
-- chose 0 to Max rather than -Max to +Max to be same as RandUnsigned, either seems logical
return to_signed(RandInt(0, Max), Size) ;
end function RandSigned ;
------------------------------------------------------------
impure function RandBool return boolean is
------------------------------------------------------------
begin
return RandInt(1) = 1;
end function RandBool ;
------------------------------------------------------------
impure function RandSl return std_logic is
------------------------------------------------------------
begin
return std_logic'val(RandInt(8));
end function RandSl ;
------------------------------------------------------------
impure function RandBit return bit is
------------------------------------------------------------
begin
return bit'val(RandInt(1));
end function RandBit ;
end protected body RandomPType ;
end RandomPkg ;
| artistic-2.0 | ee2691f5a514e47a90147c24f0fe71dc | 0.471077 | 5.124799 | false | false | false | false |
ObKo/USBCore | Examples/EP1_Loopback/ep1_loopback.vhdl | 1 | 10,221 | --
-- USB Full-Speed/Hi-Speed Device Controller core - ep1_loopback.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity ep1_loopback is
port (
led : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
ulpi_dir : in std_logic;
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_reset : out std_logic;
ulpi_clk60 : in std_logic;
main_clk : in std_logic
);
end ep1_loopback;
architecture ep1_loopback of ep1_loopback is
constant USE_HIGH_SPEED: boolean := true;
constant CONFIG_DESC : BYTE_ARRAY(0 to 8) := (
X"09", -- bLength = 9
X"02", -- bDescriptionType = Configuration Descriptor
X"20", X"00", -- wTotalLength = 32
X"01", -- bNumInterfaces = 1
X"01", -- bConfigurationValue
X"00", -- iConfiguration
X"C0", -- bmAttributes = Self-powered
X"32" -- bMaxPower = 100 mA
);
constant INTERFACE_DESC : BYTE_ARRAY(0 to 8) := (
X"09", -- bLength = 9
X"04", -- bDescriptorType = Interface Descriptor
X"00", -- bInterfaceNumber = 0
X"00", -- bAlternateSetting
X"02", -- bNumEndpoints = 2
X"00", -- bInterfaceClass
X"00", -- bInterfaceSubClass
X"00", -- bInterfaceProtocol
X"00" -- iInterface
);
constant EP1_IN_DESC : BYTE_ARRAY(0 to 6) := (
X"07", -- bLength = 7
X"05", -- bDescriptorType = Endpoint Descriptor
X"81", -- bEndpointAddress = IN1
B"00_00_00_10", -- bmAttributes = Bulk
X"00", X"02", -- wMaxPacketSize = 512 bytes
X"00" -- bInterval
);
constant EP1_OUT_DESC : BYTE_ARRAY(0 to 6) := (
X"07", -- bLength = 7
X"05", -- bDescriptorType = Endpoint Descriptor
X"01", -- bEndpointAddress = OUT1
B"00_00_00_10", -- bmAttributes = Bulk
X"00", X"02", -- wMaxPacketSize = 512 bytes
X"00" -- bInterval
);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal usb_clk : std_logic;
signal usb_reset : std_logic;
signal usb_idle : std_logic;
signal usb_suspend : std_logic;
signal usb_configured : std_logic;
signal usb_crc_error : std_logic;
signal usb_sof : std_logic;
signal ctl_xfer_endpoint : std_logic_vector(3 downto 0);
signal ctl_xfer_type : std_logic_vector(7 downto 0);
signal ctl_xfer_request : std_logic_vector(7 downto 0);
signal ctl_xfer_value : std_logic_vector(15 downto 0);
signal ctl_xfer_index : std_logic_vector(15 downto 0);
signal ctl_xfer_length : std_logic_vector(15 downto 0);
signal ctl_xfer_accept : std_logic;
signal ctl_xfer : std_logic;
signal ctl_xfer_done : std_logic;
signal ctl_xfer_data_out : std_logic_vector(7 downto 0);
signal ctl_xfer_data_out_valid: std_logic;
signal ctl_xfer_data_in : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid : std_logic;
signal ctl_xfer_data_in_last : std_logic;
signal ctl_xfer_data_in_ready : std_logic;
signal blk_xfer_endpoint : std_logic_vector(3 downto 0);
signal blk_in_xfer : std_logic;
signal blk_out_xfer : std_logic;
signal blk_xfer_in_has_data : std_logic;
signal blk_xfer_in_data : std_logic_vector(7 downto 0);
signal blk_xfer_in_data_valid : std_logic;
signal blk_xfer_in_data_ready : std_logic;
signal blk_xfer_in_data_last : std_logic;
signal blk_xfer_out_ready_read: std_logic;
signal blk_xfer_out_data : std_logic_vector(7 downto 0);
signal blk_xfer_out_data_valid: std_logic;
signal ep1_in_axis_tdata : std_logic_vector(7 downto 0);
signal ep1_in_axis_tvalid : std_logic;
signal ep1_in_axis_tready : std_logic;
signal ep1_in_axis_tlast : std_logic;
signal ep1_out_axis_tdata : std_logic_vector(7 downto 0);
signal ep1_out_axis_tvalid : std_logic;
signal ep1_out_axis_tready : std_logic;
signal ep1_out_axis_tlast : std_logic;
signal led_counter : std_logic_vector(25 downto 0);
signal ulpi_stp_int : std_logic;
begin
ULPI_IO: for i in 7 downto 0 generate
begin
ULPI_IOBUF : IOBUF
port map (
O => ulpi_data_in(i),
IO => ulpi_data(i),
I => ulpi_data_out(i),
T => ulpi_dir
);
end generate;
USB_CONTROLLER: usb_tlp
generic map (
VENDOR_ID => X"DEAD",
PRODUCT_ID => X"BEEF",
MANUFACTURER => "USBCore",
PRODUCT => "Endpoint 1 Loopback Device",
SERIAL => "",
CONFIG_DESC => CONFIG_DESC & INTERFACE_DESC &
EP1_IN_DESC & EP1_OUT_DESC,
HIGH_SPEED => USE_HIGH_SPEED
)
port map (
ulpi_data_in => ulpi_data_in,
ulpi_data_out => ulpi_data_out,
ulpi_dir => ulpi_dir,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_reset => ulpi_reset,
ulpi_clk60 => ulpi_clk60,
usb_clk => usb_clk,
usb_reset => usb_reset,
usb_idle => usb_idle,
usb_suspend => usb_suspend,
usb_configured => usb_configured,
usb_crc_error => usb_crc_error,
usb_sof => usb_sof,
ctl_xfer_endpoint => ctl_xfer_endpoint,
ctl_xfer_type => ctl_xfer_type,
ctl_xfer_request => ctl_xfer_request,
ctl_xfer_value => ctl_xfer_value,
ctl_xfer_index => ctl_xfer_index,
ctl_xfer_length => ctl_xfer_length,
ctl_xfer_accept => ctl_xfer_accept,
ctl_xfer => ctl_xfer,
ctl_xfer_done => ctl_xfer_done,
ctl_xfer_data_out => ctl_xfer_data_out,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid,
ctl_xfer_data_in => ctl_xfer_data_in,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid,
ctl_xfer_data_in_last => ctl_xfer_data_in_last,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready,
blk_xfer_endpoint => blk_xfer_endpoint,
blk_in_xfer => blk_in_xfer,
blk_out_xfer => blk_out_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid
);
EP1_IN_CTL: blk_ep_in_ctl
generic map (
USE_ASYNC_FIFO => true
)
port map (
rst => usb_reset,
usb_clk => usb_clk,
axis_clk => main_clk,
blk_in_xfer => blk_in_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
axis_tdata => ep1_in_axis_tdata,
axis_tvalid => ep1_in_axis_tvalid,
axis_tready => ep1_in_axis_tready,
axis_tlast => ep1_in_axis_tlast
);
EP1_OUT_CTL: blk_ep_out_ctl
generic map (
USE_ASYNC_FIFO => true
)
port map (
rst => usb_reset,
usb_clk => usb_clk,
axis_clk => main_clk,
blk_out_xfer => blk_out_xfer,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid,
axis_tdata => ep1_out_axis_tdata,
axis_tvalid => ep1_out_axis_tvalid,
axis_tready => ep1_out_axis_tready,
axis_tlast => ep1_out_axis_tlast
);
ep1_in_axis_tdata <= ep1_out_axis_tdata;
ep1_in_axis_tvalid <= ep1_out_axis_tvalid;
ep1_out_axis_tready <= ep1_in_axis_tready;
ep1_in_axis_tlast <= ep1_out_axis_tlast;
COUNT: process(usb_clk) is
begin
if rising_edge(usb_clk) then
led_counter <= led_counter + 1;
end if;
end process;
led <= '1' when usb_idle = '1' AND usb_configured = '1' else
led_counter(led_counter'left) when usb_idle = '1' else
'1' when led_counter(led_counter'left downto led_counter'left - 2) = "000" else
'0';
end ep1_loopback;
| mit | 3a0b647cd20a6cb6e6965ad8f973c956 | 0.574014 | 3.377726 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/test_image/example_design/test_image_prod.vhd | 1 | 10,078 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: test_image_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : test_image.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 230
-- C_READ_DEPTH_A : 230
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 230
-- C_READ_DEPTH_B : 230
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY test_image_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END test_image_prod;
ARCHITECTURE xilinx OF test_image_prod IS
COMPONENT test_image_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : test_image_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| bsd-2-clause | 863fd2f2953b3c90d82820defb90256c | 0.492558 | 3.824668 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/address_gen.vhd | 1 | 20,718 | -------------------------------------------------------------------------------
-- address_gen.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : address_gen.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI bus address generation
-- logic
-- Structure : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.conv_integer;
library axi_epc_v2_0;
use axi_epc_v2_0.ld_arith_reg;
-------------------------------------------------------------------------------
-- Definition of Generics --
-------------------------------------------------------------------------------
-- C_PRH_MAX_AWIDTH - Maximum of address bus width of all peripherals
-- NO_PRH_DWIDTH_MATCH - Indication that no device is employing data width
-- matching
-- NO_PRH_SYNC - Indicates all devices are configured for
-- asynchronous interface
-- NO_PRH_ASYNC - Indicates all devices are configured for
-- synchronous interface
-- ADDRCNT_WIDTH - Width of counter generating address suffix in case
-- of data width matching
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Rst - IPIC reset
-- Local_Clk - Operational clock for peripheral interface
-- Local_Rst - Rest for peripheral interface
-- Bus2IP_Addr - Address bus from IPIC interface
-- Dev_fifo_access - Indicates if the current access is to a FIFO like
-- - structure within the external peripheral device
-- Dev_sync - Indicates if the current device being accessed
-- is synchronous device
-- Dev_dwidth_match - Indicates if the current device employs data
-- width matching
-- Dev_dbus_width - Indicates decoded value for the data bus width
-- Async_addr_cnt_ld - Load signal for the address suffix counter for
-- asynchronous interface
-- Async_addr_cnt_ce - Enable for address suffix counter for asynchronous
-- interface
-- Sync_addr_cnt_ld - Load signal for the address suffix counter for
-- synchronous interface
-- Sync_addr_cnt_ce - Enable for address suffix counter for synchronous
-- interface
-- Addr_Int - Internal address bus for peripheral interface
-- Addr_suffix - Address suffix (lower bits of address bus) generated
-- within this module when data width matching is
-- enabled
-------------------------------------------------------------------------------
entity address_gen is
generic (
C_PRH_MAX_AWIDTH : integer;
NO_PRH_DWIDTH_MATCH : integer;
NO_PRH_SYNC : integer;
NO_PRH_ASYNC : integer;
ADDRCNT_WIDTH : integer
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
Local_Clk : in std_logic;
Local_Rst : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
Dev_fifo_access : in std_logic;
Dev_sync : in std_logic;
Dev_dwidth_match : in std_logic;
Dev_dbus_width : in std_logic_vector(0 to 2);
Async_addr_cnt_ld : in std_logic;
Async_addr_cnt_ce : in std_logic;
Sync_addr_cnt_ld : in std_logic;
Sync_addr_cnt_ce : in std_logic;
Addr_Int : out std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
Addr_suffix : out std_logic_vector(0 to ADDRCNT_WIDTH-1)
);
end entity address_gen;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of address_gen is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ADDRCNT_RST : std_logic_vector(0 to ADDRCNT_WIDTH-1)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal async_addr_cnt_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal async_addr_ld_cnt_val : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal sync_addr_cnt_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal sync_addr_ld_cnt_val : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal async_addr_suffix : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal sync_addr_suffix : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal addr_suffix_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- NAME: NO_DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: If no device employs data width matching, then generate
-- default values
-------------------------------------------------------------------------------
NO_DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 1 generate
Addr_suffix <= (others => '0');
Addr_Int <= Bus2IP_Addr;
end generate NO_DEV_DWIDTH_MATCH_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: If any device employs data width matching, then generate
-- address suffix, peripheral address bus, async and sync cycle
-- indications
-------------------------------------------------------------------------------
DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 0 generate
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as synchronous devices
-----------------------------------------------------------------------------
SOME_DEV_SYNC_GEN: if NO_PRH_SYNC = 0 generate
---------------------------------------------------------------------------
-- Counter for address suffix generation for synchronous peripheral
-- interface
---------------------------------------------------------------------------
I_SYNC_ADDRCNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => true,
C_REG_WIDTH => ADDRCNT_WIDTH,
C_RESET_VALUE => ADDRCNT_RST,
C_LD_WIDTH => ADDRCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Local_Clk,
RST => Local_Rst,
Q => sync_addr_cnt_i,
LD => sync_addr_ld_cnt_val,
AD => "1",
LOAD => Sync_addr_cnt_ld,
OP => Sync_addr_cnt_ce
);
---------------------------------------------------------------------------
-- NAME : SYNC_ADDR_LD_VAL_PROCESS
---------------------------------------------------------------------------
-- Description: Initial load value for the address suffix counter
---------------------------------------------------------------------------
SYNC_ADDR_LD_VAL_PROCESS: process(Dev_dbus_width, Bus2IP_Addr)
begin
sync_addr_ld_cnt_val <= (others => '0');
case Dev_dbus_width is
when "001" =>
sync_addr_ld_cnt_val <=
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 1);
when "010" =>
sync_addr_ld_cnt_val <= '0' &
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 2);
when "100" =>
sync_addr_ld_cnt_val <= (others => '0');
when others =>
sync_addr_ld_cnt_val <= (others => '0');
end case;
end process SYNC_ADDR_LD_VAL_PROCESS;
---------------------------------------------------------------------------
-- NAME : SYNC_ADDR_SUFFIX_PROCESS
---------------------------------------------------------------------------
-- Description: Address suffix generation for synchronous interface
---------------------------------------------------------------------------
SYNC_ADDR_SUFFIX_PROCESS: process(Dev_dbus_width, sync_addr_cnt_i)
begin
sync_addr_suffix <= (others => '0');
case Dev_dbus_width is
when "001" =>
sync_addr_suffix <= sync_addr_cnt_i;
when "010" =>
sync_addr_suffix <= sync_addr_cnt_i(1 to ADDRCNT_WIDTH-1) & '0';
when "100" =>
sync_addr_suffix <= (others => '0');
when others =>
sync_addr_suffix <= (others => '0');
end case;
end process SYNC_ADDR_SUFFIX_PROCESS;
end generate SOME_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as asynchronous devices
-----------------------------------------------------------------------------
SOME_DEV_ASYNC_GEN: if NO_PRH_ASYNC = 0 generate
---------------------------------------------------------------------------
-- Counter for address suffix generation for asynchronous peripheral
-- interface
---------------------------------------------------------------------------
I_ASYNC_ADDRCNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => true,
C_REG_WIDTH => ADDRCNT_WIDTH,
C_RESET_VALUE => ADDRCNT_RST,
C_LD_WIDTH => ADDRCNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Bus2IP_Clk,
RST => Bus2IP_Rst,
Q => async_addr_cnt_i,
LD => async_addr_ld_cnt_val,
AD => "1",
LOAD => Async_addr_cnt_ld,
OP => Async_addr_cnt_ce
);
---------------------------------------------------------------------------
-- NAME : ASYNC_ADDR_LD_VAL_PROCESS
---------------------------------------------------------------------------
-- Description: Initial load value for the address suffix counter
---------------------------------------------------------------------------
ASYNC_ADDR_LD_VAL_PROCESS: process(Dev_dbus_width, Bus2IP_Addr)
begin
async_addr_ld_cnt_val <= (others => '0');
case Dev_dbus_width is
when "001" =>
async_addr_ld_cnt_val <=
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 1);
when "010" =>
async_addr_ld_cnt_val <= '0' &
Bus2IP_Addr(C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH to C_PRH_MAX_AWIDTH - 2);
when "100" =>
async_addr_ld_cnt_val <= (others => '0');
when others =>
async_addr_ld_cnt_val <= (others => '0');
end case;
end process ASYNC_ADDR_LD_VAL_PROCESS;
---------------------------------------------------------------------------
-- NAME : ASYNC_ADDR_SUFFIX_PROCESS
---------------------------------------------------------------------------
-- Description: Address suffix generation for asynchronous interface
---------------------------------------------------------------------------
ASYNC_ADDR_SUFFIX_PROCESS: process(Dev_dbus_width, async_addr_cnt_i)
begin
async_addr_suffix <= (others => '0');
case Dev_dbus_width is
when "001" =>
async_addr_suffix <= async_addr_cnt_i;
when "010" =>
async_addr_suffix <= async_addr_cnt_i(1 to ADDRCNT_WIDTH-1) & '0';
when "100" =>
async_addr_suffix <= (others => '0');
when others =>
async_addr_suffix <= (others => '0');
end case;
end process ASYNC_ADDR_SUFFIX_PROCESS;
end generate SOME_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as synchronous devices
-----------------------------------------------------------------------------
ALL_DEV_SYNC_GEN: if NO_PRH_ASYNC = 1 generate
addr_suffix_i <= sync_addr_suffix;
end generate ALL_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as asynchronous devices
-----------------------------------------------------------------------------
ALL_DEV_ASYNC_GEN: if NO_PRH_SYNC = 1 generate
addr_suffix_i <= async_addr_suffix;
end generate ALL_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: DEV_SYNC_AND_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some devices are configured as synchronous and some
-- asynchronous
-----------------------------------------------------------------------------
DEV_SYNC_AND_ASYNC_GEN: if NO_PRH_SYNC = 0 and NO_PRH_ASYNC = 0 generate
addr_suffix_i <= async_addr_suffix when dev_sync = '0'
else sync_addr_suffix;
end generate DEV_SYNC_AND_ASYNC_GEN;
Addr_suffix <= addr_suffix_i;
Addr_Int <= Bus2IP_Addr when (Dev_dwidth_match = '0' or Dev_fifo_access = '1')
else Bus2IP_Addr(0 to C_PRH_MAX_AWIDTH-ADDRCNT_WIDTH-1)
& addr_suffix_i;
end generate DEV_DWIDTH_MATCH_GEN;
end architecture imp;
--------------------------------end of file------------------------------------
| gpl-3.0 | 08f25a97f6b6d420e5e4b16e1d2f1449 | 0.39748 | 5.124413 | false | false | false | false |
peteut/nvc | test/simp/cfold.vhd | 1 | 3,444 | entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
variable b : boolean;
begin
b := a1'length = 5;
b := a1'low(1) = 1;
b := a1'high(1) = 5;
b := a1'left = 1;
b := a1'right = 5;
b := int2_vec'length = 2;
b := int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
r := 2.0 ** 4;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
-- Billowitch tc3170
tc3170: process is
constant L : REAL := -10.0;
constant R : REAL := 10.0;
type RT1 is range L to R;
begin
assert ( RT1'right = RT1(R) ); -- Should be removed
end process;
bitvec: process is
constant x : bit_vector(1 to 3) := "101";
constant y : bit_vector(1 to 3) := "110";
constant z : bit_vector(3 downto 1) := "011";
variable b : boolean;
begin
b := (x and y) = "100";
b := (y and z) = "010";
b := (x or y) = "111";
b := not x = "010";
b := (x xor y) = "011";
b := (x xnor y) = "100";
b := (x nand y) = "011";
b := (x nor y) = "000";
end process;
end architecture;
| gpl-3.0 | 66184b89c713ad7e3a6fed7cf5b7e33c | 0.421893 | 3.330754 | false | false | false | false |
peteut/nvc | lib/std/standard.vhd | 1 | 3,018 | -- -*- coding: latin-1; -*-
--
-- STANDARD package as defined by IEEE 1076-1993
--
package STANDARD is
type INTEGER;
type STRING;
type REAL;
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134, C135,
C136, C137, C138, C139, C140, C141, C142, C143,
C144, C145, C146, C147, C148, C149, C150, C151,
C152, C153, C154, C155, C156, C157, C158, C159,
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '¶', '¹',
C184, C185, C186, C187, C188, C189, C190, C191,
C192, C193, C194, C195, C196, C197, C198, C199,
C200, C201, C202, C203, C204, C205, C206, C207,
C208, C209, C210, C211, C212, C213, C214, C215,
C216, C217, C218, C219, C220, C221, C222, C223,
C224, C225, C226, C227, C228, C229, C230, C231,
C232, C233, C234, C235, C236, C237, C238, C239,
C240, C241, C242, C243, C244, C245, C246, C247,
C248, C249, C250, C251, C252, C253, C254, C255
);
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
type INTEGER is range -2147483648 to 2147483647;
type REAL is range -1.7976931348623157e308 to 1.7976931348623157e308;
type TIME is range -9223372036854775808 to 9223372036854775807
units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
impure function NOW return DELAY_LENGTH;
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
type STRING is array (POSITIVE range <>) of CHARACTER;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR,
MODE_ERROR);
attribute FOREIGN : STRING;
attribute FOREIGN of NOW : function is "_std_standard_now";
end package;
| gpl-3.0 | 19b7d1448a28cade5f38f78361a40fad | 0.463883 | 2.871551 | false | false | false | false |
UnofficialRepos/OSVVM | TbUtilPkg.vhd | 1 | 40,522 | --
-- File Name: TbUtilPkg.vhd
-- Design Unit Name: TbUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Added EdgeRose, EdgeFell, FindRisingEdge, FindFallingEdge.
-- 01/2022 2022.01 Added MetaTo01. Added WaitForTransaction without clock for RdyType/AckType and bit.
-- 02/2021 2021.02 Added AckType, RdyType, RequestTransaction, WaitForTransaction for AckType/RdyType
-- 12/2020 2020.12 Added IfElse functions for string and integer.
-- Added Increment function for integer
-- 01/2020 2020.01 Updated Licenses to Apache
-- 08/2018 2018.08 Updated WaitForTransaction to allow 0 time transactions
-- 04/2018 2018.04 Added RequestTransaction, WaitForTransaction, Toggle, WaitForToggle for bit.
-- Added Increment and WaitForToggle for integer.
-- 11/2016 2016.11 First Public Release Version
-- Updated naming for consistency.
-- 10/2013 2013.10 Split out Text Utilities
-- 11/1999: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 1999 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use work.AlertLogPkg.all ;
use work.TranscriptPkg.all ;
use work.ResolutionPkg.all ;
use work.OsvvmGlobalPkg.all ;
package TbUtilPkg is
constant CLK_ACTIVE : std_logic := '1' ;
constant t_sim_resolution : time := std.env.resolution_limit ; -- VHDL-2008
-- constant t_sim_resolution : time := 1 ns ; -- for non VHDL-2008 simulators
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean ;
------------------------------------------------------------
-- EdgeRose, EdgeFell, FindRisingEdge, FindFallingEdge
------------------------------------------------------------
function EdgeRose ( signal C : in std_logic ) return boolean ;
function EdgeFell ( signal C : in std_logic ) return boolean ;
function EdgeActive ( signal C : in std_logic; A : std_logic ) return boolean ;
procedure FindRisingEdge ( signal C : in std_logic) ;
procedure FindFallingEdge ( signal C : in std_logic ) ;
procedure FindActiveEdge ( signal C : in std_logic; A : std_logic ) ;
------------------------------------------------------------
-- MetaTo01
-- Convert Meta values to 0
------------------------------------------------------------
function MetaTo01 ( constant A : in std_ulogic ) return std_ulogic ;
function MetaTo01 ( constant A : in std_ulogic_vector ) return std_ulogic_vector ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector ;
function IfElse(Expr : boolean ; A, B : integer) return integer ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
subtype RdyType is resolved_max integer range 0 to integer'high ;
subtype AckType is resolved_max integer range -1 to integer'high ;
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) ;
-- Set Ack to Model starting value
procedure StartTransaction ( signal Ack : Out std_logic ) ;
-- Set Ack to Model finishing value
procedure FinishTransaction ( signal Ack : Out std_logic ) ;
-- If a transaction is pending, return true
function TransactionPending ( signal Rdy : In std_logic ) return boolean ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In RdyType ;
signal Ack : InOut AckType
);
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : in bit ;
signal Ack : out bit
) ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) ;
procedure Toggle ( signal Sig : InOut std_logic ) ;
procedure ToggleHS ( signal Sig : InOut std_logic ) ;
function IsToggle ( signal Sig : In std_logic ) return boolean ;
procedure WaitForToggle ( signal Sig : In std_logic ) ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) ;
procedure Toggle ( signal Sig : InOut bit ) ;
procedure ToggleHS ( signal Sig : InOut bit ) ;
function IsToggle ( signal Sig : In bit ) return boolean ;
procedure WaitForToggle ( signal Sig : In bit ) ;
-- Integer type versions
procedure Increment ( signal Sig : InOut integer ; constant RollOverValue : in integer := 0) ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer ;
procedure WaitForToggle ( signal Sig : In integer ) ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) ;
-- resolved_barrier : summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer ;
subtype integer_barrier is resolved_barrier integer ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time := 0 ns
) ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) ;
------------------------------------------------------------
-- Deprecated subprogram names
-- Maintaining backward compatibility using aliases
------------------------------------------------------------
-- History of RequestTransaction / WaitForTransaction
alias RequestAction is RequestTransaction [std_logic, std_logic] ;
alias WaitForRequest is WaitForTransaction [std_logic, std_logic, std_logic] ;
-- History of WaitForToggle
alias WaitOnToggle is WaitForToggle [std_logic] ;
-- History of WaitForBarrier
alias WayPointBlock is WaitForBarrier [std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic] ;
alias SyncTo is WaitForBarrier2[std_logic, std_logic_vector] ;
-- Backward compatible name
alias SyncToClk is WaitForClock [std_logic, time] ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) ;
procedure StrobeAck ( signal Ack : Out std_logic ) ;
end TbUtilPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body TbUtilPkg is
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
------------------------------------------------------------
-- ZeroOneHot, OneHot
-- OneHot: return true if exactly one value is 1
-- ZeroOneHot: return false when more than one value is a 1
------------------------------------------------------------
function OneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return found_one ; -- found a one
end function OneHot ;
function ZeroOneHot ( constant A : in std_logic_vector ) return boolean is
variable found_one : boolean := FALSE ;
begin
for i in A'range loop
if A(i) = '1' or A(i) = 'H' then
if found_one then
return FALSE ;
end if ;
found_one := TRUE ;
end if ;
end loop ;
return TRUE ; -- all zero or found a one
end function ZeroOneHot ;
------------------------------------------------------------
-- EdgeRose, EdgeFell, FindRisingEdge, FindFallingEdge
------------------------------------------------------------
function EdgeRose ( signal C : in std_logic ) return boolean is
begin
return to_x01(C)='1' and to_x01(C'last_value)='0' and C'last_event= 0 sec ;
end function EdgeRose ;
function EdgeFell ( signal C : in std_logic ) return boolean is
begin
return to_x01(C)='0' and to_x01(C'last_value)='1' and C'last_event= 0 sec ;
end function EdgeFell ;
function EdgeActive ( signal C : in std_logic; A : std_logic ) return boolean is
begin
return to_x01(C)=A and to_x01(C'last_value)=not A and C'last_event= 0 sec ;
end function EdgeActive ;
procedure FindRisingEdge ( signal C : in std_logic) is
begin
if not EdgeRose(C) then
wait until rising_edge(C) ;
end if ;
end procedure FindRisingEdge ;
--!! Rejected as the semantic is confusing
--!! procedure FindRisingEdge ( signal C : in std_logic; Count : integer) is
--!! variable Start : integer := 1 ;
--!! begin
--!! if EdgeRose(C) then
--!! Start := 2 ;
--!! end if
--!! for i in Start to Count loop
--!! wait until rising_edge(C) ;
--!! end loop ;
--!! end procedure FindRisingEdge ;
procedure FindFallingEdge ( signal C : in std_logic ) is
begin
if not EdgeFell(C) then
wait until falling_edge(C) ;
end if ;
end procedure FindFallingEdge ;
procedure FindActiveEdge ( signal C : in std_logic; A : std_logic ) is
begin
if A = '1' then
FindRisingEdge(C) ;
else
FindFallingEdge(C) ;
end if ;
end procedure FindActiveEdge ;
------------------------------------------------------------
-- MetaTo01
-- Convert Meta values to 0
------------------------------------------------------------
constant MetaTo01Table : stdulogic_indexby_stdulogic := (
'1' => '1',
'H' => '1',
others => '0'
);
function MetaTo01 ( constant A : in std_ulogic ) return std_ulogic is
begin
return MetaTo01Table(A) ;
end function MetaTo01 ;
function MetaTo01 ( constant A : in std_ulogic_vector ) return std_ulogic_vector is
variable result : std_logic_vector(A'range) ;
begin
for i in A'range loop
result(i) := MetaTo01Table(A(i)) ;
end loop ;
return result ;
end function MetaTo01 ;
------------------------------------------------------------
-- IfElse
-- Crutch until VHDL-2019 conditional initialization
-- If condition is true return first parameter otherwise return second
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : std_logic_vector) return std_logic_vector is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
function IfElse(Expr : boolean ; A, B : integer) return integer is
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- RequestTransaction - Transaction initiation in transaction procedure
-- WaitForTransaction - Transaction execution control in VC
------------------------------------------------------------
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- std_logic
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out std_logic ;
signal Ack : In std_logic
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- bit
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : Out bit ;
signal Ack : In bit
) is
begin
-- Record contains new transaction
Rdy <= '1' ;
-- Find Ack low = '0'
wait until Ack = '0' ;
-- Prepare for Next Transaction
Rdy <= '0' ;
-- Transaction Done
wait until Ack = '1' ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In bit ;
signal Ack : Out bit
) is
variable AckTime : time ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if needed (not back-to-back transactions)
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end procedure WaitForTransaction ;
------------------------------------------------------------
-- RequestTransaction - WaitForTransaction
-- integer
------------------------------------------------------------
procedure RequestTransaction (
signal Rdy : InOut RdyType ;
signal Ack : In AckType
) is
begin
-- Initiate Transaction Request
Rdy <= Increment(Rdy) ;
wait for 0 ns ;
-- Wait for Transaction Completion
wait until Rdy = Ack ;
end procedure RequestTransaction ;
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) is
begin
-- End of Previous Cycle. Signal Done
Ack <= Increment(Ack) ;
-- Find Start of Transaction
wait until Ack /= Rdy ;
-- Align to clock if needed (not back-to-back transactions)
if not EdgeActive(Clk, CLK_ACTIVE) then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure WaitForTransaction ;
procedure WaitForTransaction (
signal Rdy : In RdyType ;
signal Ack : InOut AckType
) is
begin
-- End of Previous Cycle. Signal Done
Ack <= Increment(Ack) ;
-- Find Start of Transaction
wait until Ack /= Rdy ;
end procedure WaitForTransaction ;
------------------------------------------------------------
-- WaitForTransaction
-- Specializations for interrupt handling
-- Currently only std_logic based
------------------------------------------------------------
procedure WaitForTransaction (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal Ack : Out std_logic ;
signal TimeOut : In std_logic ;
constant Polarity : In std_logic := '1'
) is
variable AckTime : time ;
variable FoundRdy : boolean ;
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if (Rdy /= '1' and TimeOut /= Polarity) then
wait until Rdy = '1' or TimeOut = Polarity ;
end if ;
FoundRdy := Rdy = '1' ;
-- align to clock if Rdy or TimeOut does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
if FoundRdy then
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- Allow transactions without time passing
end if ;
end procedure WaitForTransaction ;
-- Variation for model that stops waiting when IntReq is asserted
-- Intended for models that need to switch between instruction streams
-- such as a CPU when interrupt is pending
procedure WaitForTransactionOrIrq (
signal Clk : In std_logic ;
signal Rdy : In std_logic ;
signal IntReq : In std_logic
) is
variable AckTime : time ;
constant POLARITY : std_logic := '1' ;
begin
AckTime := NOW ;
-- Find Ready or Time out
wait for 0 ns ; -- allow Rdy from previous cycle to clear
if (Rdy /= '1' and IntReq /= POLARITY) then
wait until Rdy = '1' or IntReq = POLARITY ;
else
wait for 0 ns ; -- allow Ack to update
end if ;
-- align to clock if Rdy or IntReq does not happen within delta cycles from Ack
if NOW /= AckTime then
wait until Clk = CLK_ACTIVE ;
end if ;
end procedure ;
-- Set Ack to Model starting value
-- Pairs with WaitForTransactionOrIrq above
procedure StartTransaction ( signal Ack : Out std_logic ) is
begin
Ack <= '0' ;
wait for 0 ns ; -- Allow transactions without time passing
end procedure StartTransaction ;
-- Set Ack to Model finishing value
-- Pairs with WaitForTransactionOrIrq above
procedure FinishTransaction ( signal Ack : Out std_logic ) is
begin
-- End of Cycle
Ack <= '1' ;
wait for 0 ns ; -- Allow Ack to update
end procedure FinishTransaction ;
-- If a transaction is pending, return true
-- Used to detect presence of transaction stream,
-- such as an interrupt handler
function TransactionPending (
signal Rdy : In std_logic
) return boolean is
begin
return Rdy = '1' ;
end function TransactionPending ;
-- Variation for clockless models
procedure WaitForTransaction (
signal Rdy : In std_logic ;
signal Ack : Out std_logic
) is
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- allow 0 time transactions
end procedure WaitForTransaction ;
procedure WaitForTransaction (
signal Rdy : in bit ;
signal Ack : out bit
) is
begin
-- End of Previous Cycle. Signal Done
Ack <= '1' ; -- #6
-- Find Start of Transaction
wait for 0 ns ; -- Allow Rdy from previous cycle to clear
if Rdy /= '1' then -- #2
wait until Rdy = '1' ;
end if ;
-- Model active and owns the record
Ack <= '0' ; -- #3
wait for 0 ns ; -- allow 0 time transactions
end procedure WaitForTransaction ;
------------------------------------------------------------
-- Toggle, WaitForToggle
-- Used for communicating between processes
------------------------------------------------------------
constant toggle_sl_table : stdulogic_indexby_stdulogic := (
'0' => '1',
'L' => '1',
others => '0'
);
procedure Toggle (
signal Sig : InOut std_logic ;
constant DelayVal : time
) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec, "osvvm.TbUtilPkg.Toggle: Delay value < 0 ns") ;
end if ;
Sig <= toggle_sl_table(Sig) after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut std_logic ) is
begin
Sig <= toggle_sl_table(Sig) ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In std_logic ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In std_logic ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Bit type versions
procedure Toggle ( signal Sig : InOut bit ; constant DelayVal : time ) is
variable iDelayVal : time ;
begin
if DelayVal > t_sim_resolution then
iDelayVal := DelayVal - t_sim_resolution ;
else
iDelayVal := 0 sec ;
AlertIf(OSVVM_ALERTLOG_ID, DelayVal < 0 sec,
"osvvm.TbUtilPkg.Toggle: Delay value < 0 ns", WARNING) ;
end if ;
Sig <= not Sig after iDelayVal ;
end procedure Toggle ;
procedure Toggle ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
end procedure Toggle ;
procedure ToggleHS ( signal Sig : InOut bit ) is
begin
Sig <= not Sig ;
wait for 0 ns ; -- Sig toggles
wait for 0 ns ; -- new values updated into record
end procedure ToggleHS ;
function IsToggle ( signal Sig : In bit ) return boolean is
begin
return Sig'event ;
end function IsToggle ;
procedure WaitForToggle ( signal Sig : In bit ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
-- Integer type versions
procedure Increment (signal Sig : InOut integer ; constant RollOverValue : in integer := 0) is
begin
--!! if Sig = integer'high then
if Sig = 2**30-1 then -- for consistency with function increment
Sig <= RollOverValue ;
else
Sig <= Sig + 1 ;
end if ;
end procedure Increment ;
function Increment (constant Sig : in integer ; constant Amount : in integer := 1) return integer is
begin
--! Sig = integer'high - Amount + 1 ;
return (Sig + Amount) mod 2**30 ;
end function Increment ;
procedure WaitForToggle ( signal Sig : In integer ) is
begin
wait on Sig ;
end procedure WaitForToggle ;
------------------------------------------------------------
-- WaitForBarrier
-- Barrier Synchronization
-- Multiple processes call it, it finishes when all have called it
------------------------------------------------------------
procedure WaitForBarrier ( signal Sig : InOut std_logic ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut std_logic ; constant TimeOut : time ) is
begin
Sig <= 'H' ;
-- Wait until all processes set Sig to H
-- Level check not necessary since last value /= H yet
wait until Sig = 'H' for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= '0' ;
wait for 0 ns ;
end procedure WaitForBarrier ;
------------------------------------------------------------
-- resolved_barrier
-- summing resolution used in conjunction with integer based barriers
function resolved_barrier ( s : integer_vector ) return integer is
variable result : integer := 0 ;
begin
for i in s'RANGE loop
-- if s(i) /= integer'left then
-- result := result + s(i);
-- else
if s(i) /= 0 then
result := result + 1; -- removes the initialization requirement
end if ;
end loop ;
return result ;
end function resolved_barrier ;
-- Usage of integer barriers requires resolved_barrier. Initialization to 1 recommended, but not required
-- signal barrier1 : resolved_barrier integer := 1 ; -- using the resolution function
-- signal barrier2 : integer_barrier := 1 ; -- using the subtype that already applies the resolution function
procedure WaitForBarrier ( signal Sig : InOut integer ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; signal TimeOut : std_logic ; constant Polarity : in std_logic := '1') is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 or TimeOut = Polarity ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
procedure WaitForBarrier ( signal Sig : InOut integer ; constant TimeOut : time ) is
begin
Sig <= 0 ;
-- Wait until all processes set Sig to 0
-- Level check not necessary since last value /= 0 yet
wait until Sig = 0 for TimeOut ;
-- Deactivate and propagate to allow back to back calls
Sig <= 1 ;
wait for 0 ns ;
end procedure WaitForBarrier ;
-- Using separate signals
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncIn : in std_logic ) is
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until other process' Rdy is at level 1
if SyncIn /= '1' then
wait until SyncIn = '1' ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
procedure WaitForBarrier2 ( signal SyncOut : out std_logic ; signal SyncInV : in std_logic_vector ) is
constant ALL_ONE : std_logic_vector(SyncInV'Range) := (others => '1');
begin
-- Activate Rdy
SyncOut <= '1' ;
-- Make sure our Rdy is seen
wait for 0 ns ;
-- Wait until all other process' Rdy is at level 1
if SyncInV /= ALL_ONE then
wait until SyncInV = ALL_ONE ;
end if ;
-- Deactivate Rdy
SyncOut <= '0' ;
end procedure WaitForBarrier2 ;
------------------------------------------------------------
-- WaitForClock
-- Sync to Clock - after a delay, after a number of clocks
------------------------------------------------------------
procedure WaitForClock ( signal Clk : in std_logic ; constant Delay : in time ) is
begin
if delay > t_sim_resolution then
wait for delay - t_sim_resolution ;
end if ;
wait until Clk = CLK_ACTIVE ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; constant NumberOfClocks : in integer := 1) is
begin
for i in 1 to NumberOfClocks loop
wait until Clk = CLK_ACTIVE ;
end loop ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in boolean ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable ;
end procedure WaitForClock ;
procedure WaitForClock ( signal Clk : in std_logic ; signal Enable : in std_logic ; constant Polarity : std_logic := '1' ) is
begin
wait on Clk until Clk = CLK_ACTIVE and Enable = Polarity ;
end procedure WaitForClock ;
------------------------------------------------------------
-- WaitForLevel
-- Find a signal at a level
------------------------------------------------------------
procedure WaitForLevel ( signal A : in boolean ) is
begin
if not A then
wait until A ;
end if ;
end procedure WaitForLevel ;
procedure WaitForLevel ( signal A : in std_logic ; Polarity : std_logic := '1' ) is
begin
if A /= Polarity then
-- wait on A until A = Polarity ;
if Polarity = '1' then
wait until A = '1' ;
else
wait until A = '0' ;
end if ;
end if ;
end procedure WaitForLevel ;
------------------------------------------------------------
-- CreateClock, CreateReset
-- Note these do not exit
------------------------------------------------------------
procedure CreateClock (
signal Clk : inout std_logic ;
constant Period : time ;
constant DutyCycle : real := 0.5
) is
constant HIGH_TIME : time := Period * DutyCycle ;
constant LOW_TIME : time := Period - HIGH_TIME ;
begin
if HIGH_TIME = LOW_TIME then
loop
Clk <= toggle_sl_table(Clk) after HIGH_TIME ;
wait on Clk ;
end loop ;
else
-- Schedule s.t. all assignments after the first occur on delta cycle 0
Clk <= '0', '1' after LOW_TIME ;
wait for period - t_sim_resolution ; -- allows after on future Clk <= '0'
loop
Clk <= '0' after t_sim_resolution, '1' after LOW_TIME + t_sim_resolution ;
wait for period ;
end loop ;
end if ;
end procedure CreateClock ;
procedure CheckClockPeriod (
constant AlertLogID : AlertLogIDType ;
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
variable LastLogTime, ObservedPeriod : time ;
begin
wait until Clk = CLK_ACTIVE ;
LastLogTime := now ;
-- Check First HowMany clocks
for i in 1 to HowMany loop
wait until Clk = CLK_ACTIVE ;
ObservedPeriod := now - LastLogTime ;
AffirmIf(AlertLogID, ObservedPeriod = Period,
"CheckClockPeriod: " & ClkName & " Period: " & to_string(ObservedPeriod, GetOsvvmDefaultTimeUnits) &
" = Expected " & to_string(Period, GetOsvvmDefaultTimeUnits)) ;
LastLogTime := now ;
end loop ;
wait ;
end procedure CheckClockPeriod ;
procedure CheckClockPeriod (
signal Clk : in std_logic ;
constant Period : time ;
constant ClkName : string := "Clock" ;
constant HowMany : integer := 5
) is
begin
CheckClockPeriod (
AlertLogID => ALERTLOG_DEFAULT_ID,
Clk => Clk,
Period => Period,
ClkName => ClkName,
HowMany => HowMany
) ;
end procedure CheckClockPeriod ;
procedure CreateReset (
signal Reset : out std_logic ;
constant ResetActive : in std_logic ;
signal Clk : in std_logic ;
constant Period : time ;
constant tpd : time := 0 ns
) is
begin
wait until Clk = CLK_ACTIVE ;
Reset <= ResetActive after tpd ;
wait for Period - t_sim_resolution ;
wait until Clk = CLK_ACTIVE ;
Reset <= not ResetActive after tpd ;
wait ;
end procedure CreateReset ;
procedure LogReset (
constant AlertLogID : AlertLogIDType ;
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
-- Does not log the value of Reset at time 0.
for_ever : loop
wait on Reset ;
if Reset = ResetActive then
LOG(AlertLogID, ResetName & " now active", INFO) ;
print("") ;
elsif Reset = not ResetActive then
LOG(AlertLogID, ResetName & " now inactive", INFO) ;
print("") ;
else
LOG(AlertLogID, ResetName & " = " & to_string(Reset), INFO) ;
print("") ;
end if ;
end loop for_ever ;
end procedure LogReset ;
procedure LogReset (
signal Reset : in std_logic ;
constant ResetActive : in std_logic ;
constant ResetName : in string := "Reset" ;
constant LogLevel : in LogType := ALWAYS
) is
begin
LogReset (
AlertLogID => ALERTLOG_DEFAULT_ID,
Reset => Reset,
ResetActive => ResetActive,
ResetName => ResetName,
LogLevel => LogLevel
) ;
end procedure LogReset ;
------------------------------------------------------------
-- Deprecated
-- WaitForAck, StrobeAck
-- Replaced by WaitForToggle and Toggle
------------------------------------------------------------
procedure WaitForAck ( signal Ack : In std_logic ) is
begin
-- Wait for Model to be done
wait until Ack = '1' ;
wait for 0 ns ;
end procedure ;
procedure StrobeAck ( signal Ack : Out std_logic ) is
begin
-- Model done, drive rising edge on Ack
Ack <= '0' ;
wait for 0 ns ;
Ack <= '1' ;
wait for 0 ns ;
end procedure ;
end TbUtilPkg ;
| artistic-2.0 | 3f6ef2a88dc389fbdad16f08d0c55722 | 0.571097 | 4.411758 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_10/lab10_1_1/lpm_rom0.vhd | 1 | 6,284 | -- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "lab10_1.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
widthad_a => 5,
width_a => 4,
width_byteena_a => 1
)
PORT MAP (
clock0 => clock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "lab10_1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
-- Retrieval info: PRIVATE: WidthData NUMERIC "4"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "lab10_1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q_a 0 0 4 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 705112b374dd2953cf53e083eb7fca35 | 0.669955 | 3.508654 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/example_design/ram_16x8k_dp_exdes.vhd | 1 | 5,654 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x8k_dp_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x8k_dp_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END ram_16x8k_dp_exdes;
ARCHITECTURE xilinx OF ram_16x8k_dp_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ram_16x8k_dp IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : ram_16x8k_dp
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| bsd-3-clause | 00549532756df2e6ee6589207d9502cf | 0.545278 | 4.431034 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/blk_mem_gen_v7_3.vhd | 1 | 5,667 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file blk_mem_gen_v7_3.vhd when simulating
-- the core, blk_mem_gen_v7_3. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY blk_mem_gen_v7_3 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END blk_mem_gen_v7_3;
ARCHITECTURE blk_mem_gen_v7_3_a OF blk_mem_gen_v7_3 IS
-- synthesis translate_off
COMPONENT wrapped_blk_mem_gen_v7_3
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_blk_mem_gen_v7_3 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 4,
c_addrb_width => 4,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "00",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "artix7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "blk_mem_gen_v7_3.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 16,
c_read_depth_b => 16,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 16,
c_write_depth_b => 16,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_blk_mem_gen_v7_3
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END blk_mem_gen_v7_3_a;
| bsd-2-clause | 28527d66c7cf461cb1dafb6838ffe293 | 0.530969 | 3.785571 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/cpu_xadc_wiz_0_0_xadc_core_drp.vhd | 1 | 45,152 | -------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_xadc_core_drp.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010, 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : cpu_xadc_wiz_0_0_xadc_core_drp.vhd
-- Version : v1.00.a
-- Description : XADC for AXI bus on new FPGA devices.
-- This file containts actual interface between the core
-- and XADC hard macro.
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_xadc.vhd
-- -cpu_xadc_wiz_0_0_xadc_core_drp.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.or_reduce;
use IEEE.numeric_std.all;
library work;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- un-comment below line if testing locally with BLH or UNISIM model
--use unisim.XADC;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- AXI4 Slave Single block generics
-------------------------------------------------------------------------------
-- C_S_AXI_ADDR_WIDTH -- AXI4 address bus width
-- C_S_AXI_DATA_WIDTH -- AXI4 Slave bus width
--
-------------------------------------------------------------------------------
-- XADC Specific Generics
-------------------------------------------------------------------------------
-- C_SIM_MONITOR_FILE -- stimuli file
-- CE_NUMBERS -- read/write chip enble no.
-- IP_INTR_NUM -- interrupt signals no.
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- AXI Slave Interface -- INPUT/OUTPUT Signals
-------------------------------------------------------------------------------
-- Bus2IP_Clk -- bus clock
-- Bus2IP_Rst -- bus reset
-- -- Bus 2 IP IPIC interface
-- Bus2IP_RdCE -- bus read chip enable signals
-- Bus2IP_WrCE -- bus write chip enable signals
-- Bus2IP_Addr -- bus address bits
-- Bus2IP_Data -- bus to ip data
-- -- IP 2 Bus IPIC interface
-- Sysmon_IP2Bus_Data -- data from sysmon
-- Sysmon_IP2Bus_WrAck -- write ack from sysmon
-- Sysmon_IP2Bus_RdAck -- read ack from sysmon
-------------------------------------------------------------------------------
-- XADC EXTERNAL INTERFACE -- INPUT Signals
-------------------------------------------------------------------------------
-- VAUXN -- user selectable differential inputs
-- VAUXP -- user selectable differential inputs
-- CONVST -- Conversion start signal for event-driven
-- sampling mode
-------------------------------------------------------------------------------
-- XADC Interrupt -- OUTPUT Signal to Interrupt Module
-------------------------------------------------------------------------------
-- Interrupt_status -- interrupt from the sysmon core
-- ALARM -- XADC alarm output signals of the hard macro
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_xadc_core_drp is
generic
(
----------------
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_DATA_WIDTH : integer;
C_FAMILY : string;
----------------
CE_NUMBERS : integer;
IP_INTR_NUM : integer;
C_SIM_MONITOR_FILE : string ;
----------------
MUX_ADDR_NO : integer
);
port
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- Bus 2 IP IPIC interface
Bus2IP_RdCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_WrCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_Addr : in std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- IP 2 Bus IPIC interface
Sysmon_IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Sysmon_IP2Bus_WrAck : out std_logic;
Sysmon_IP2Bus_RdAck : out std_logic;
---------------- interrupt interface with the system -----------
Interrupt_status : out std_logic_vector(0 to IP_INTR_NUM-1);
---------------- sysmon macro interface -------------------
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
ot_out : out STD_LOGIC;
alarm_out : out STD_LOGIC_VECTOR (7 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end entity cpu_xadc_wiz_0_0_xadc_core_drp;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of cpu_xadc_wiz_0_0_xadc_core_drp is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant DATA_SIZE_DRP : integer := 16;
constant ADDR_SIZE_DRP : integer := 7;
constant CHANNEL_NO : integer := 5;
constant ALARM_NO : integer := 8; -- updated from 3 to 8 for XADC
constant ALARM_REG_LENGTH : integer := 9;-- internal constant-- updated from 4 to 9 for XADC
constant STATUS_REG_LENGTH : integer := 11;--internal constant
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal daddr_i : std_logic_vector(ADDR_SIZE_DRP-1 downto 0);
signal alm_i : std_logic_vector(ALARM_NO-1 downto 0);
signal channel_i : std_logic_vector(CHANNEL_NO-1 downto 0);
signal mux_addr_no_i : std_logic_vector(MUX_ADDR_NO-1 downto 0);-- added for XADC
signal do_i : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal di_i : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal den_i : std_logic;
signal dwe_i : std_logic;
signal busy_i : std_logic;
signal drdy_i : std_logic;
signal eoc_i : std_logic;
signal eos_i : std_logic;
signal ot_i : std_logic;
signal daddr_C : std_logic_vector(7 downto 0);
signal den_C : std_logic;
signal di_C : std_logic_vector(15 downto 0);
signal dwe_C : std_logic;
signal do_C : std_logic_vector(15 downto 0);
signal drdy_C : std_logic;
signal bgrant_B : std_logic;
signal daddr_i_int : std_logic_vector(ADDR_SIZE_DRP downto 0);
signal temp_bus_update: std_logic := '0';
signal temp_rd_wait_cycle_reg : std_logic_vector(15 downto 0) := X"03E8";
-- JTAG related signals
signal jtaglocked_i : std_logic;
signal jtagbusy_i : std_logic;
signal jtagmodified_i : std_logic;
signal jtagmodified_d1 : std_logic;
signal jtag_modified_info: std_logic;
-------------------------------------------------------------------------------
-- Following signals are used as internal signals
signal do_reg : std_logic_vector(DATA_SIZE_DRP-1 downto 0);
signal alarm_reg : std_logic_vector(ALARM_REG_LENGTH-1 downto 0);
signal status_reg : std_logic_vector(STATUS_REG_LENGTH-1 downto 0);
-------------------------------------------------------------------------------
signal convst_rst_wrce_or_reduce : std_logic;
signal local_rdce_or_reduce : std_logic;
signal register_rdce_select : std_logic_vector(0 to 2);
signal convst_reset_wrce_select : std_logic_vector(0 to 1);
-------------------------------------------------------------------------------
signal eoc_d1 : std_logic;
signal eos_d1 : std_logic;
signal eoc_info : std_logic;
signal eos_info : std_logic;
-------------------------------------------------------------------------------
signal convst_reg : std_logic := '0';
signal hard_macro_rst_reg : std_logic;
signal sysmon_hard_block_reset : std_logic;
-------------------------------------------------------------------------------
signal local_reg_rdack_final : std_logic;
signal status_reg_rdack : std_logic;
signal status_reg_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
signal local_reg_wrack : std_logic;
signal local_reg_wrack_d1 : std_logic;
signal local_reg_rdack : std_logic;
signal local_reg_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
signal sysmon_IP2Bus_Data_i : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
signal drdy_rd_ack_i : std_logic;
signal drdy_wr_ack_i : std_logic;
signal drdy_rd_ack_i_d1 : std_logic;
signal drdy_rd_ack_i_d2 : std_logic;
signal drdy_wr_ack_i_d1 : std_logic;
signal drdy_wr_ack_i_d2 : std_logic;
signal convst_d1 : std_logic;
-------------------------------------------------------------------------------
signal convst_reg_input : std_logic;
signal den_d1 : std_logic;
signal den_actual : std_logic;
-------------------------------------------------------------------------------
-- The following signals are locally declared signals and will not be connected
-- to any where from XADC hard macro. EDK has dedicated VN/VP ports and these
-- are connected to the board like power supply pins, so it is not required
-- that these ports to be listed in the port list of the core.
-- in simulation these signals will show as un-initialised.
-------------------------------------------------------------------------------
--following signals are added for providing the falling edge interrupt detection
signal ot_d1 : std_logic;
signal ot_falling_edge : std_logic;
--
signal alarm_0_d1 : std_logic;
signal alarm_0_falling_edge : std_logic;
--
signal alarm_3_d1 : std_logic;
signal vbram_alarm_3_falling_edge : std_logic;
--
signal alarm_4_d1 : std_logic;
signal vccpint_alarm_4_falling_edge : std_logic;
--
signal aux_channel_p : std_logic_vector (15 downto 0);
signal aux_channel_n : std_logic_vector (15 downto 0);
signal daddr_A : std_logic_vector(7 downto 0);
signal den_A : std_logic;
signal di_A : std_logic_vector(15 downto 0);
signal dwe_A : std_logic;
signal do_A : std_logic_vector(15 downto 0);
signal drdy_A : std_logic;
signal bbusy_A : std_logic;
signal drp_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Assign temporary internal signal to separate out Addr bit 23 to Addr bit 29
-- from PLB address lines
-- As the addresses for XADC are word aligned, it is required to trim the
-- address bit 30 and 31. The incoming address from PLB is word aligned.
-- The internal register file interface are at sequential address like
-- 0x00h, 0x01h...etc
-------------------------------------------------------------------------------
-- daddr_i <= Bus2IP_Addr(23 to 29);
daddr_i <= Bus2IP_Addr(2 to 8);
-------------------------------------------------------------------------------
-- Data from PLB will be assigned to the DI port of DRP
-- Assign the last half word (bit 16 to 31)data from PLB DATA Bus to the
-- internal signal
-------------------------------------------------------------------------------
di_i <= Bus2IP_Data((C_S_AXI_DATA_WIDTH/2) to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
-- If jtaglocked_i output from XADC goes high, it prevents read/write access
-- to DRP port
-------------------------------------------------------------------------------
-- JTAGLOCKED_RD_PROCESS
------------------------
-- generate enable signal for DRP. the enable signal is logical AND of
-- chip enable for the address range of REG_FILE_BASEADDR
-------------------------------------------------------------------------------
JTAGLOCKED_RD_PROCESS: process(jtaglocked_i,
Bus2IP_RdCE(CE_NUMBERS-1),
Bus2IP_WrCE(CE_NUMBERS-1)
) is
begin
if (jtaglocked_i ='1') then
den_i <= '0';
else
den_i <= (
Bus2IP_RdCE(CE_NUMBERS-1)
or
Bus2IP_WrCE(CE_NUMBERS-1)
);
end if;
end process JTAGLOCKED_RD_PROCESS;
-------------------------------------------------------------------------------
-- DEN_REG_PROCESS
------------------------
-- generate enable signal for DRP for "Single Clock Cycle" only.
-------------------------------------------------------------------------------
DEN_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
den_d1 <= den_i;
end if;
end process DEN_REG_PROCESS;
den_actual <= den_i and (not den_d1);
-------------------------------------------------------------------------------
-- JTAGLOCKED_WR_PROCESS
------------------------
-- This signal will be interfaced with DWE port of XADC
-------------------------------------------------------------------------------
JTAGLOCKED_WR_PROCESS: process(jtaglocked_i,
Bus2IP_WrCE(CE_NUMBERS-1)
) is
begin
if (jtaglocked_i ='1') then
dwe_i <= '0';
else
dwe_i <= Bus2IP_WrCE(CE_NUMBERS-1);
end if;
end process JTAGLOCKED_WR_PROCESS;
-------------------------------------------------------------------------------
-- JTAGLOCKED_WR_ACK_PROCESS
----------------------------
-- Generate the internal register write_ack, when the DRDY from XADC is high
-- as well as the WrCE(5) signal from PLB is high.
-- This Write Ack is only when PLB accesses DRP port.
-- _____|--------|____ WrCE
-- ___________|--|__ DRDY is active for 1 clock cycle = one clock width ack
-- DRDY will go high after the 4th clock cycle when the data, address, control
-- signals are present on the interface.
-- Delayed the ACK generated when jtaglock='1'.
-------------------------------------------------------------------------------
JTAGLOCKED_WR_ACK_PROCESS:process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if(Bus2IP_Rst = RESET_ACTIVE) then
drdy_wr_ack_i <= '0';
drdy_wr_ack_i_d1 <= '0';
drdy_wr_ack_i_d2 <= '0';
elsif (jtaglocked_i ='1') then
drdy_wr_ack_i_d1 <= Bus2IP_WrCE(CE_NUMBERS-1);
drdy_wr_ack_i_d2 <= drdy_wr_ack_i_d1;
drdy_wr_ack_i <= drdy_wr_ack_i_d1 and (not drdy_wr_ack_i_d2);
else
drdy_wr_ack_i <= drdy_i and Bus2IP_WrCE(CE_NUMBERS-1);
end if;
end if;
end process JTAGLOCKED_WR_ACK_PROCESS;
-------------------------------------------------------------------------------
-- JTAGLOCKED_RD_ACK_PROCESS
----------------------------
-- Generate the internal read_ack, when the DRDY from XADC is high as well as
-- the RdCE(5) signal from PLB is high
-- This Read Ack is only when PLB accesses DRP port.
-- Delayed the ACK generated when jtaglock='1'.
-------------------------------------------------------------------------------
JTAGLOCKED_RD_ACK_PROCESS:process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk='1' then
if(Bus2IP_Rst = RESET_ACTIVE) then
drdy_rd_ack_i <= '0';
drdy_rd_ack_i_d1 <= '0';
drdy_rd_ack_i_d2 <= '0';
elsif (jtaglocked_i ='1') then
drdy_rd_ack_i_d1 <= Bus2IP_RdCE(CE_NUMBERS-1);
drdy_rd_ack_i_d2 <= drdy_rd_ack_i_d1;
drdy_rd_ack_i <= drdy_rd_ack_i_d1 and (not drdy_rd_ack_i_d2);
else
drdy_rd_ack_i <= drdy_i and Bus2IP_RdCE(CE_NUMBERS-1);
end if;
end if;
end process JTAGLOCKED_RD_ACK_PROCESS;
-------------------------------------------------------------------------------
-- It is required to register the DRDY as well as DO ports of the XADC .
-- This will delay the ACK generation by one clock cycle.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- DO_REG_PROCESS
-----------------
-- This process is used to register the DO port of DRP in the
-- local register. If JTAG access is going on, then core need to wait till the
-- JTAG access ends. Once the JTAG access is over the Bus2IP_Addr, DEN are
-- presented to the DRP, then DO of DRP put the data as per the DADDR by making
-- the DRDY high for 1 clock cycle.
-------------------------------------------------------------------------------
DO_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if(Bus2IP_Rst = RESET_ACTIVE) then
do_reg <= (others => '0');
elsif (jtaglocked_i ='1') then
do_reg <= (others => '0');
else
do_reg <= do_i;
end if;
end if;
end process DO_REG_PROCESS;
-------------------------------------------------------------------------------
-- combine for CONVST and reset macro write chip enable signals
-------------------------------------------------------------------------------
convst_reset_wrce_select <= Bus2IP_WrCE(3) & Bus2IP_WrCE(4);
-------------------------------------------------------------------------------
-- CONVST_RST_PROCESS:
----------------------
-- This process is used to register the CONVST and XADC RST signals
-- The bit 31st Bus2IP_Data is used along with the Bus2IP_WrCE(3 to 4)
-- to start the conversion or to reset the sysmon through software.
-------------------------------------------------------------------------------
CONVST_RST_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
convst_reg_input <= '0';
hard_macro_rst_reg <= '0';
else
case convst_reset_wrce_select is
when "10" => convst_reg_input <= Bus2IP_Data(31);
when "01" => hard_macro_rst_reg <= Bus2IP_Data(31);
-- coverage off
when others => null;
-- coverage on
end case;
end if;
end if;
end process CONVST_RST_PROCESS;
daddr_C <= '0' & daddr_i;
di_C <= di_i;
dwe_C <= dwe_i;
den_C <= den_actual;
do_i <= do_C;
drdy_i <= drdy_C;
-- Generate the WRITE ACK back to PLB
Sysmon_IP2Bus_WrAck <= (drdy_wr_ack_i or local_reg_wrack) ;
-- Generate the READ ACK back to PLB
Sysmon_IP2Bus_RdAck <= (drdy_rd_ack_i or local_reg_rdack_final);
-------------------------------------------------------------------------------
-- Bus reset as well as the hard macro register reset
-------------------------------------------------------------------------------
-- XADC Reset Register (SYSMONRR)
-------------------------------------------------------------------------------
sysmon_hard_block_reset<= Bus2IP_Rst or hard_macro_rst_reg;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- EOC_REG_EXTEND_PROCESS
-------------------------
-- Extend the EOC signal which is active high for 1 clock cycle till the
-- PLB reads the status register.
-- _____|--|__________ one clock width EOC
-- _____|--------|____ extended EOC
-------------------------------------------------------------------------------
EOC_REG_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
eoc_d1 <= '0';
elsif(eoc_i = '1') then
eoc_d1 <= '1';
elsif(status_reg_rdack = '1')then
eoc_d1 <= '0';
end if;
end if;
end process EOC_REG_EXTEND_PROCESS;
eoc_info <= eoc_d1 or eoc_i;
-------------------------------------------------------------------------------
-- EOS_REG_EXTEND_PROCESS
-------------------------
-- Extend the EOS signal which is active high for 1 clock cycle till the
-- PLB reads the status register.
-- _____|--|__________ one clock width EOS
-- _____|--------|____ extended EOS
-------------------------------------------------------------------------------
EOS_REG_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
eos_d1 <= '0';
elsif(eos_i = '1') then
eos_d1 <= '1';
elsif(status_reg_rdack = '1')then
eos_d1 <= '0';
end if;
end if;
end process EOS_REG_EXTEND_PROCESS;
eos_info <= eos_d1 or eos_i;
-------------------------------------------------------------------------------
-- JTAGMODIFIED_EXTEND_PROCESS
-------------------------
-- Extend the JTAGMODIFIED signal which is active high till the DRP read is
-- performed
-- __________|------ RDCE to DRP
-- _____|----|_____ JTAGMODIFIED
-- _______|------|____ extended JTAGMODIFIED
-- _____|--------|____ jtag_modified_info
-------------------------------------------------------------------------------
JTAGMODIFIED_EXTEND_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE or drdy_rd_ack_i = '1') then
jtagmodified_d1 <= '0';
elsif(jtagmodified_i = '1') then
jtagmodified_d1 <= '1';
end if;
end if;
end process JTAGMODIFIED_EXTEND_PROCESS;
jtag_modified_info <= jtagmodified_i or jtagmodified_d1;
-------------------------------------------------------------------------------
-- STATUS_REG_PROCESS
---------------------
-- This process is used to register the JTAG, BUSY, EOC, EOS,
-- & Channel bits in internal register
-------------------------------------------------------------------------------
STATUS_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
status_reg <= (others => '0');
else
status_reg(10) <= jtagbusy_i;
status_reg(9) <= jtag_modified_info;
status_reg(8) <= jtaglocked_i;
status_reg(7) <= busy_i;
status_reg(6) <= eos_info;
status_reg(5) <= eoc_info;
status_reg(4) <= channel_i(4);
status_reg(3) <= channel_i(3);
status_reg(2) <= channel_i(2);
status_reg(1) <= channel_i(1);
status_reg(0) <= channel_i(0);
end if;
end if;
end process STATUS_REG_PROCESS;
busy_out <= busy_i;
channel_out <= channel_i;
eoc_out <= eoc_i;
eos_out <= eos_i;
-------------------------------------------------------------------------------
-- ALARM_REG_PROCESS (ALARM OUTPUT STATUS REGISTER - AOSR)
-----------------------------------------------------------
-- This process is used to register the ALARM, OT bits in internal register
-------------------------------------------------------------------------------
ALARM_REG_PROCESS: process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
alarm_reg <= (others => '0');
else
alarm_reg(8) <= alm_i(7);-- added for XADC
alarm_reg(7) <= alm_i(6);
alarm_reg(6) <= alm_i(5);
alarm_reg(5) <= alm_i(4);
alarm_reg(4) <= alm_i(3);-- added for XADC
alarm_reg(3) <= alm_i(2);
alarm_reg(2) <= alm_i(1);
alarm_reg(1) <= alm_i(0);
alarm_reg(0) <= ot_i;
end if;
end if;
end process ALARM_REG_PROCESS;
-- OT out to top level port
ot_out <= ot_i;
--------------------------
-- OT_FALLING_EDGE_DETECT: this process is used to register the OT.
--------------------------
-- ____|-------|________ ot_i
-- ______|-------|______ ot_d1
-- ____________|-|______ ot_falling_edge
----------------------------------------
OT_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
ot_d1 <= ot_i;
end if;
end process OT_FALLING_EDGE_DETECT;
ot_falling_edge <= ot_d1 and (not ot_i);
------------------------------
-- ALARM_0_FALLING_EDGE_DETECT: User temperature settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(0)
-- ______|-------|______ alm_i(0)_d1
-- ____________|-|______ alarm_0_falling_edge
---------------------------------------------
ALARM_0_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
alarm_0_d1 <= alm_i(0);
end if;
end process ALARM_0_FALLING_EDGE_DETECT;
alarm_0_falling_edge <= alarm_0_d1 and (not alm_i(0));
------------------------------
-- ALARM_3_FALLING_EDGE_DETECT: VBRM settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(3)
-- ______|-------|______ alm_i(3)_d1
-- ____________|-|______ vbram_alarm_3_falling_edge
---------------------------------------------
--ALARM_3_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
--begin
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- alarm_3_d1 <= alm_i(3);
-- end if;
--end process ALARM_3_FALLING_EDGE_DETECT;
--vbram_alarm_3_falling_edge <= alarm_3_d1 and (not alm_i(3));
------------------------------
-- ALARM_4_FALLING_EDGE_DETECT: VCCPINT settings interrupt falling edge
------------------------------ detection logic
-- ____|-------|________ alm_i(4)
-- ______|-------|______ alm_i(4)_d1
-- ____________|-|______ vccpint_alarm_4_falling_edge
---------------------------------------------
--ALARM_4_FALLING_EDGE_DETECT: process (Bus2IP_Clk) is
--begin
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- alarm_4_d1 <= alm_i(4);
-- end if;
--end process ALARM_4_FALLING_EDGE_DETECT;
--vccpint_alarm_4_falling_edge <= alarm_4_d1 and (not alm_i(4));
-------------------------------------------------------------------------------
-- dont register any interrupt signal and just pass
-- it on to the interrupt controller
-------------------------------------------------------------------------------
Interrupt_status(0) <= ot_i;
Interrupt_status(1) <= alm_i(0);
Interrupt_status(2) <= alm_i(1);
Interrupt_status(3) <= alm_i(2);
Interrupt_status(4) <= eos_i;
Interrupt_status(5) <= eoc_i;
Interrupt_status(6) <= jtaglocked_i;
Interrupt_status(7) <= jtagmodified_i;
Interrupt_status(8) <= ot_falling_edge;
Interrupt_status(9) <= alarm_0_falling_edge;
Interrupt_status(10) <= alm_i(3);-- Added for XADC VccBram sensor o/p
Interrupt_status(11) <= alm_i(4); -- XADC VCCPint sensor o/p for Zynq
Interrupt_status(12) <= alm_i(5); -- XADC VCCPaux sensor o/p for Zynq
Interrupt_status(13) <= alm_i(6); -- XADC VCCddro sensor o/p for Zynq
Interrupt_status(14) <= '0';
Interrupt_status(15) <= '0';
Interrupt_status(16) <= '0';
-------------------------------------------------------------------------------
-- Status Register, Alarm Reg and DRP Register File Interface (RFI) can be READ
-------------------------------------------------------------------------------
register_rdce_select <= Bus2IP_RdCE(1) & -- Status Register
Bus2IP_RdCE(2) & -- AOSR
Bus2IP_RdCE(CE_NUMBERS-1);-- DPR
-------------------------------------------------------------------------------
-- The upper bits are always '0'.
-------------------------------------------------------------------------------
sysmon_IP2Bus_Data_i(0 to 13)<=(others => '0');
-------------------------------------------------------------------------------
-- LOCAL_REG_READ_PROCESS
-------------------------
LOCAL_REG_READ_PROCESS: process (register_rdce_select,
status_reg,
alarm_reg,
do_reg,
jtag_modified_info,
jtaglocked_i) is
begin
case register_rdce_select is
-- bus2ip_rdce(1,2,8)
when "100" =>
sysmon_IP2Bus_Data_i(14 to 31) <= "0000000" & status_reg;
when "010" =>
sysmon_IP2Bus_Data_i(14 to 31) <= "000000000" & alarm_reg;
when "001" =>
sysmon_IP2Bus_Data_i(14 to 31) <= jtag_modified_info &
jtaglocked_i &
do_reg;
-- coverage off
when others =>
sysmon_IP2Bus_Data_i(14 to 31) <= (others => '0');
-- coverage on
end case;
end process LOCAL_REG_READ_PROCESS;
-------------------------------------------------------------------------------
-- STATUS_REG_READ_ACK_GEN_PROCESS
----------------------------------
-- To generate the RdAck for status registers, use RdCE
-------------------------------------------------------------------------------
-- _____|-----|_______ rdce
-- ________|--|__________ rd_ack from local registers i.e. status register
-------------------------------------------------------------------------------
STATUS_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
status_reg_rdack_d1 <= '0';
status_reg_rdack <= '0';
else
status_reg_rdack_d1 <= Bus2IP_RdCE(1);
status_reg_rdack <= Bus2IP_RdCE(1) and (not status_reg_rdack_d1);
end if;
end if;
end process STATUS_REG_READ_ACK_GEN_PROCESS;
-------------------------------------------------------------------------------
-- For register which are just write-only a read ack is required for completing
-- the transaction.
-------------------------------------------------------------------------------
local_rdce_or_reduce <= or_reduce(Bus2IP_RdCE(2 to 4));
-------------------------------------------------------------------------------
-- LOCAL_REG_READ_ACK_GEN_PROCESS
---------------------------------
-- To generate the RdAck for alarm,CONVST,XADC Hard Macro registers,
-- use RdCE
-------------------------------------------------------------------------------
-- _____|-----|_______ rdce
-- ________|--|__________ rd_ack from local registers
-------------------------------------------------------------------------------
LOCAL_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
local_reg_rdack_d1 <= '0';
local_reg_rdack <= '0';
else
local_reg_rdack_d1 <= local_rdce_or_reduce;
local_reg_rdack <= local_rdce_or_reduce and (not local_reg_rdack_d1);
end if;
end if;
end process LOCAL_REG_READ_ACK_GEN_PROCESS;
local_reg_rdack_final <= status_reg_rdack or local_reg_rdack;
-------------------------------------------------------------------------------
-- For register which are just read-only a write ack is required for completing
-- the transaction.
-------------------------------------------------------------------------------
convst_rst_wrce_or_reduce <= or_reduce(Bus2IP_WrCE(1 to 4));
-------------------------------------------------------------------------------
-- LOCAL_REG_WRITE_ACK_GEN_PROCESS
----------------------------------
-- To generate the WrAck for local registers, use WrCE
-------------------------------------------------------------------------------
-- _____|-----|_______ wrce
-- ________|--|__________ wr_ack from local registers
-- i.e. convst,reset register
-------------------------------------------------------------------------------
LOCAL_REG_WRITE_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Bus2IP_Rst = RESET_ACTIVE) then
local_reg_wrack_d1 <= '0';
local_reg_wrack <= '0';
else
local_reg_wrack_d1 <= convst_rst_wrce_or_reduce;
local_reg_wrack <= convst_rst_wrce_or_reduce and
(not local_reg_wrack_d1);
end if;
end if;
end process LOCAL_REG_WRITE_ACK_GEN_PROCESS;
-------------------------------------------------------------------------------
-- All the signals listed here are FROM IP to PLB IPIF INTERFACE
-------------------------------------------------------------------------------
-- Present the DRP data to Sysmon_IP2Bus_Data
Sysmon_IP2Bus_Data <= sysmon_IP2Bus_Data_i;
-------------------------------------------------------------------------------
-- Added interface to ALARM signals from the XADC macro to core ports.
------------------------------------------------------------------------
alarm_out <= alarm_reg(8 downto 1);-- updated from 2 downto 1 to 8 downto 1 for XADC
------------------------------------------------------------------------
-- Added interface to MUX ADDRESS for external address multiplexer from the
-- XADC macro to core ports.
-------------------------------------------------------------------------------
-- == XADC INTERFACE -- OUTPUT Signals ==
-------------------------------------------------------------------------------
-- BUSY -- ADC busy signal
-- DRDY -- Data ready signal for Dynamic Reconfigurable Port
-- EOC -- End of conversion for ADC
-- EOS -- End of sequence used in auto sequence mode
-- JTAGBUSY -- Used to indicate that the JTAG DRP is doing transaction
-- JTAGLOCKED -- Used to indicate the DRP port lock is requested
-- JTAGMODIFIED -- Used to indicate that the JTAG write to JTAG is happened
-- OT -- Signal for Over Temperature alarm
-- ALM -- Sysmon Alarm outputs
-- CHANNEL -- Channel selection outputs
-- DO -- Output data bus for Dynamic Reconfigurable Port
-------------------------------------------------------------------------------
-- == XADC INTERFACE -- INPUT Signals ==
-------------------------------------------------------------------------------
-- VN -- High Bandwidth Dedicated analog input pair
-- VP which provides differential analog input. These pins are
-- just like dedicated suply pins and user dont have control
-- over these pins.
-- CONVST -- Conversion start input used in event driven sampling
-- CONVSTCLK -- Conversion start clock input
-- DCLK -- Clock input for Dynamic Reconfigurable Port
-- DEN -- Enable signal for Dynamic Reconfigurable Port
-- DWE -- Write Enable signal for Dynamic Reconfigurable Port
-- RESET -- External hard Reset input
-- DADDR -- Address bus for Dynamic Reconfigurable Port
-- DI -- Input data bus for Dynamic Reconfigurable Port
-- VAUXN -- Low Bandwidth, Sixteen auxiliary analog input pairs
-- VAUXP which provides differential analog inputs
-- MUXADDR -- External address multiplexer driven by Channel selection
-- Registers
aux_channel_p(0) <= '0';
aux_channel_n(0) <= '0';
aux_channel_p(1) <= '0';
aux_channel_n(1) <= '0';
aux_channel_p(2) <= '0';
aux_channel_n(2) <= '0';
aux_channel_p(3) <= '0';
aux_channel_n(3) <= '0';
aux_channel_p(4) <= '0';
aux_channel_n(4) <= '0';
aux_channel_p(5) <= '0';
aux_channel_n(5) <= '0';
aux_channel_p(6) <= '0';
aux_channel_n(6) <= '0';
aux_channel_p(7) <= '0';
aux_channel_n(7) <= '0';
aux_channel_p(8) <= '0';
aux_channel_n(8) <= '0';
aux_channel_p(9) <= '0';
aux_channel_n(9) <= '0';
aux_channel_p(10) <= '0';
aux_channel_n(10) <= '0';
aux_channel_p(11) <= '0';
aux_channel_n(11) <= '0';
aux_channel_p(12) <= '0';
aux_channel_n(12) <= '0';
aux_channel_p(13) <= '0';
aux_channel_n(13) <= '0';
aux_channel_p(14) <= '0';
aux_channel_n(14) <= '0';
aux_channel_p(15) <= '0';
aux_channel_n(15) <= '0';
XADC_INST : XADC
generic map(
INIT_40 => X"0000", -- config reg 0
INIT_41 => X"3100", -- config reg 1
INIT_42 => X"0400", -- config reg 2
INIT_48 => X"0100", -- Sequencer channel selection
INIT_49 => X"0000", -- Sequencer channel selection
INIT_4A => X"0000", -- Sequencer Average selection
INIT_4B => X"0000", -- Sequencer Average selection
INIT_4C => X"0000", -- Sequencer Bipolar selection
INIT_4D => X"0000", -- Sequencer Bipolar selection
INIT_4E => X"0000", -- Sequencer Acq time selection
INIT_4F => X"0000", -- Sequencer Acq time selection
INIT_50 => X"B5ED", -- Temp alarm trigger
INIT_51 => X"57E4", -- Vccint upper alarm limit
INIT_52 => X"A147", -- Vccaux upper alarm limit
INIT_53 => X"CA33", -- Temp alarm OT upper
INIT_54 => X"A93A", -- Temp alarm reset
INIT_55 => X"52C6", -- Vccint lower alarm limit
INIT_56 => X"9555", -- Vccaux lower alarm limit
INIT_57 => X"AE4E", -- Temp alarm OT reset
INIT_58 => X"5999", -- Vccbram upper alarm limit
INIT_5C => X"5111", -- Vccbram lower alarm limit
INIT_59 => X"5555", -- Vccpint upper alarm limit
INIT_5D => X"5111", -- Vccpint lower alarm limit
INIT_5A => X"9999", -- Vccpaux upper alarm limit
INIT_5E => X"91EB", -- Vccpaux lower alarm limit
INIT_5B => X"6AAA", -- Vccddro upper alarm limit
INIT_5F => X"6666", -- Vccddro lower alarm limit
SIM_DEVICE => "ZYNQ",
SIM_MONITOR_FILE => "/home/guest/cae/fpga/ntpserver/cpu/ip/cpu_xadc_wiz_0_0/cpu_xadc_wiz_0_0/simulation/functional/design.txt"
)
port map (
CONVST => '0',
CONVSTCLK => '0',
DADDR => daddr_C(6 downto 0), --: in (6 downto 0)
DCLK => Bus2IP_Clk, --: in
DEN => den_C, --: in
DI => di_C, --: in (15 downto 0)
DWE => dwe_C, --: in
RESET => sysmon_hard_block_reset, --: in
VAUXN(15 downto 0) => aux_channel_n(15 downto 0),
VAUXP(15 downto 0) => aux_channel_p(15 downto 0),
ALM => alm_i,
BUSY => busy_i, --: out
CHANNEL => channel_i, --: out (4 downto 0)
DO => do_C, --: out (15 downto 0)
DRDY => drdy_C, --: out
EOC => eoc_i, --: out
EOS => eos_i, --: out
JTAGLOCKED => jtaglocked_i, --: out
JTAGBUSY => jtagbusy_i, --: out
JTAGMODIFIED => jtagmodified_i, --: out
OT => ot_i, --: out
VN => vn_in,
VP => vp_in
);
end architecture imp;
--------------------------------------------------------------------------------
| gpl-3.0 | dd641af594b37b519c32c38eff4689a7 | 0.442107 | 4.367998 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/sim/cpu_axi_epc_0_0.vhd | 1 | 16,776 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_epc:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_epc_v2_0;
USE axi_epc_v2_0.axi_epc;
ENTITY cpu_axi_epc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END cpu_axi_epc_0_0;
ARCHITECTURE cpu_axi_epc_0_0_arch OF cpu_axi_epc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_epc IS
GENERIC (
C_S_AXI_CLK_PERIOD_PS : INTEGER;
C_PRH_CLK_PERIOD_PS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_PERIPHERALS : INTEGER;
C_PRH_MAX_AWIDTH : INTEGER;
C_PRH_MAX_DWIDTH : INTEGER;
C_PRH_MAX_ADWIDTH : INTEGER;
C_PRH_CLK_SUPPORT : INTEGER;
C_PRH0_BASEADDR : STD_LOGIC_VECTOR;
C_PRH0_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH0_FIFO_ACCESS : INTEGER;
C_PRH0_FIFO_OFFSET : INTEGER;
C_PRH0_AWIDTH : INTEGER;
C_PRH0_DWIDTH : INTEGER;
C_PRH0_DWIDTH_MATCH : INTEGER;
C_PRH0_SYNC : INTEGER;
C_PRH0_BUS_MULTIPLEX : INTEGER;
C_PRH0_ADDR_TSU : INTEGER;
C_PRH0_ADDR_TH : INTEGER;
C_PRH0_ADS_WIDTH : INTEGER;
C_PRH0_CSN_TSU : INTEGER;
C_PRH0_CSN_TH : INTEGER;
C_PRH0_WRN_WIDTH : INTEGER;
C_PRH0_WR_CYCLE : INTEGER;
C_PRH0_DATA_TSU : INTEGER;
C_PRH0_DATA_TH : INTEGER;
C_PRH0_RDN_WIDTH : INTEGER;
C_PRH0_RD_CYCLE : INTEGER;
C_PRH0_DATA_TOUT : INTEGER;
C_PRH0_DATA_TINV : INTEGER;
C_PRH0_RDY_TOUT : INTEGER;
C_PRH0_RDY_WIDTH : INTEGER;
C_PRH1_BASEADDR : STD_LOGIC_VECTOR;
C_PRH1_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH1_FIFO_ACCESS : INTEGER;
C_PRH1_FIFO_OFFSET : INTEGER;
C_PRH1_AWIDTH : INTEGER;
C_PRH1_DWIDTH : INTEGER;
C_PRH1_DWIDTH_MATCH : INTEGER;
C_PRH1_SYNC : INTEGER;
C_PRH1_BUS_MULTIPLEX : INTEGER;
C_PRH1_ADDR_TSU : INTEGER;
C_PRH1_ADDR_TH : INTEGER;
C_PRH1_ADS_WIDTH : INTEGER;
C_PRH1_CSN_TSU : INTEGER;
C_PRH1_CSN_TH : INTEGER;
C_PRH1_WRN_WIDTH : INTEGER;
C_PRH1_WR_CYCLE : INTEGER;
C_PRH1_DATA_TSU : INTEGER;
C_PRH1_DATA_TH : INTEGER;
C_PRH1_RDN_WIDTH : INTEGER;
C_PRH1_RD_CYCLE : INTEGER;
C_PRH1_DATA_TOUT : INTEGER;
C_PRH1_DATA_TINV : INTEGER;
C_PRH1_RDY_TOUT : INTEGER;
C_PRH1_RDY_WIDTH : INTEGER;
C_PRH2_BASEADDR : STD_LOGIC_VECTOR;
C_PRH2_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH2_FIFO_ACCESS : INTEGER;
C_PRH2_FIFO_OFFSET : INTEGER;
C_PRH2_AWIDTH : INTEGER;
C_PRH2_DWIDTH : INTEGER;
C_PRH2_DWIDTH_MATCH : INTEGER;
C_PRH2_SYNC : INTEGER;
C_PRH2_BUS_MULTIPLEX : INTEGER;
C_PRH2_ADDR_TSU : INTEGER;
C_PRH2_ADDR_TH : INTEGER;
C_PRH2_ADS_WIDTH : INTEGER;
C_PRH2_CSN_TSU : INTEGER;
C_PRH2_CSN_TH : INTEGER;
C_PRH2_WRN_WIDTH : INTEGER;
C_PRH2_WR_CYCLE : INTEGER;
C_PRH2_DATA_TSU : INTEGER;
C_PRH2_DATA_TH : INTEGER;
C_PRH2_RDN_WIDTH : INTEGER;
C_PRH2_RD_CYCLE : INTEGER;
C_PRH2_DATA_TOUT : INTEGER;
C_PRH2_DATA_TINV : INTEGER;
C_PRH2_RDY_TOUT : INTEGER;
C_PRH2_RDY_WIDTH : INTEGER;
C_PRH3_BASEADDR : STD_LOGIC_VECTOR;
C_PRH3_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH3_FIFO_ACCESS : INTEGER;
C_PRH3_FIFO_OFFSET : INTEGER;
C_PRH3_AWIDTH : INTEGER;
C_PRH3_DWIDTH : INTEGER;
C_PRH3_DWIDTH_MATCH : INTEGER;
C_PRH3_SYNC : INTEGER;
C_PRH3_BUS_MULTIPLEX : INTEGER;
C_PRH3_ADDR_TSU : INTEGER;
C_PRH3_ADDR_TH : INTEGER;
C_PRH3_ADS_WIDTH : INTEGER;
C_PRH3_CSN_TSU : INTEGER;
C_PRH3_CSN_TH : INTEGER;
C_PRH3_WRN_WIDTH : INTEGER;
C_PRH3_WR_CYCLE : INTEGER;
C_PRH3_DATA_TSU : INTEGER;
C_PRH3_DATA_TH : INTEGER;
C_PRH3_RDN_WIDTH : INTEGER;
C_PRH3_RD_CYCLE : INTEGER;
C_PRH3_DATA_TOUT : INTEGER;
C_PRH3_DATA_TINV : INTEGER;
C_PRH3_RDY_TOUT : INTEGER;
C_PRH3_RDY_WIDTH : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END COMPONENT axi_epc;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF prh_clk: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CLK";
ATTRIBUTE X_INTERFACE_INFO OF prh_rst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RST";
ATTRIBUTE X_INTERFACE_INFO OF prh_cs_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CS_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_addr: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF prh_ads: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADS";
ATTRIBUTE X_INTERFACE_INFO OF prh_be: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BE";
ATTRIBUTE X_INTERFACE_INFO OF prh_rnw: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF prh_rd_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RD_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_wr_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF WR_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_burst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BURST";
ATTRIBUTE X_INTERFACE_INFO OF prh_rdy: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RDY";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_i: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_I";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_o: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_O";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_t: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_T";
BEGIN
U0 : axi_epc
GENERIC MAP (
C_S_AXI_CLK_PERIOD_PS => 10000,
C_PRH_CLK_PERIOD_PS => 10000,
C_FAMILY => "zynq",
C_INSTANCE => "axi_epc_inst",
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_PERIPHERALS => 1,
C_PRH_MAX_AWIDTH => 32,
C_PRH_MAX_DWIDTH => 32,
C_PRH_MAX_ADWIDTH => 32,
C_PRH_CLK_SUPPORT => 0,
C_PRH0_BASEADDR => X"80600000",
C_PRH0_HIGHADDR => X"8060FFFF",
C_PRH0_FIFO_ACCESS => 0,
C_PRH0_FIFO_OFFSET => 0,
C_PRH0_AWIDTH => 32,
C_PRH0_DWIDTH => 32,
C_PRH0_DWIDTH_MATCH => 0,
C_PRH0_SYNC => 1,
C_PRH0_BUS_MULTIPLEX => 0,
C_PRH0_ADDR_TSU => 0,
C_PRH0_ADDR_TH => 0,
C_PRH0_ADS_WIDTH => 0,
C_PRH0_CSN_TSU => 0,
C_PRH0_CSN_TH => 0,
C_PRH0_WRN_WIDTH => 0,
C_PRH0_WR_CYCLE => 0,
C_PRH0_DATA_TSU => 0,
C_PRH0_DATA_TH => 0,
C_PRH0_RDN_WIDTH => 0,
C_PRH0_RD_CYCLE => 0,
C_PRH0_DATA_TOUT => 0,
C_PRH0_DATA_TINV => 0,
C_PRH0_RDY_TOUT => 0,
C_PRH0_RDY_WIDTH => 100000,
C_PRH1_BASEADDR => X"B000FFFF",
C_PRH1_HIGHADDR => X"BFFFFFFF",
C_PRH1_FIFO_ACCESS => 0,
C_PRH1_FIFO_OFFSET => 0,
C_PRH1_AWIDTH => 32,
C_PRH1_DWIDTH => 32,
C_PRH1_DWIDTH_MATCH => 0,
C_PRH1_SYNC => 0,
C_PRH1_BUS_MULTIPLEX => 0,
C_PRH1_ADDR_TSU => 0,
C_PRH1_ADDR_TH => 0,
C_PRH1_ADS_WIDTH => 0,
C_PRH1_CSN_TSU => 0,
C_PRH1_CSN_TH => 0,
C_PRH1_WRN_WIDTH => 0,
C_PRH1_WR_CYCLE => 0,
C_PRH1_DATA_TSU => 0,
C_PRH1_DATA_TH => 0,
C_PRH1_RDN_WIDTH => 0,
C_PRH1_RD_CYCLE => 0,
C_PRH1_DATA_TOUT => 0,
C_PRH1_DATA_TINV => 0,
C_PRH1_RDY_TOUT => 0,
C_PRH1_RDY_WIDTH => 0,
C_PRH2_BASEADDR => X"C000FFFF",
C_PRH2_HIGHADDR => X"CFFFFFFF",
C_PRH2_FIFO_ACCESS => 0,
C_PRH2_FIFO_OFFSET => 0,
C_PRH2_AWIDTH => 32,
C_PRH2_DWIDTH => 32,
C_PRH2_DWIDTH_MATCH => 0,
C_PRH2_SYNC => 0,
C_PRH2_BUS_MULTIPLEX => 0,
C_PRH2_ADDR_TSU => 0,
C_PRH2_ADDR_TH => 0,
C_PRH2_ADS_WIDTH => 0,
C_PRH2_CSN_TSU => 0,
C_PRH2_CSN_TH => 0,
C_PRH2_WRN_WIDTH => 0,
C_PRH2_WR_CYCLE => 0,
C_PRH2_DATA_TSU => 0,
C_PRH2_DATA_TH => 0,
C_PRH2_RDN_WIDTH => 0,
C_PRH2_RD_CYCLE => 0,
C_PRH2_DATA_TOUT => 0,
C_PRH2_DATA_TINV => 0,
C_PRH2_RDY_TOUT => 0,
C_PRH2_RDY_WIDTH => 0,
C_PRH3_BASEADDR => X"D000FFFF",
C_PRH3_HIGHADDR => X"DFFFFFFF",
C_PRH3_FIFO_ACCESS => 0,
C_PRH3_FIFO_OFFSET => 0,
C_PRH3_AWIDTH => 32,
C_PRH3_DWIDTH => 32,
C_PRH3_DWIDTH_MATCH => 0,
C_PRH3_SYNC => 0,
C_PRH3_BUS_MULTIPLEX => 0,
C_PRH3_ADDR_TSU => 0,
C_PRH3_ADDR_TH => 0,
C_PRH3_ADS_WIDTH => 0,
C_PRH3_CSN_TSU => 0,
C_PRH3_CSN_TH => 0,
C_PRH3_WRN_WIDTH => 0,
C_PRH3_WR_CYCLE => 0,
C_PRH3_DATA_TSU => 0,
C_PRH3_DATA_TH => 0,
C_PRH3_RDN_WIDTH => 0,
C_PRH3_RD_CYCLE => 0,
C_PRH3_DATA_TOUT => 0,
C_PRH3_DATA_TINV => 0,
C_PRH3_RDY_TOUT => 0,
C_PRH3_RDY_WIDTH => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
prh_clk => prh_clk,
prh_rst => prh_rst,
prh_cs_n => prh_cs_n,
prh_addr => prh_addr,
prh_ads => prh_ads,
prh_be => prh_be,
prh_rnw => prh_rnw,
prh_rd_n => prh_rd_n,
prh_wr_n => prh_wr_n,
prh_burst => prh_burst,
prh_rdy => prh_rdy,
prh_data_i => prh_data_i,
prh_data_o => prh_data_o,
prh_data_t => prh_data_t
);
END cpu_axi_epc_0_0_arch;
| gpl-3.0 | e4e3f22a1059e30da835a8b24412115e | 0.628398 | 2.816655 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_14/Lab_14_1_1/sync_RS.vhd | 1 | 672 | library ieee;
use ieee. std_logic_1164.all;
entity sync_RS is
PORT(S: in std_logic;
R: in std_logic;
CLOCK: in std_logic;
CLR: in std_logic;
PRESET: in std_logic;
Q: out std_logic;
QN: out std_logic);
end sync_RS;
Architecture Arch_sync_RS of sync_RS is
begin
FF: process (CLOCK, CLR, PRESET)
variable x: std_logic;
begin
if (CLR='0') then
x:='0';
elsif (PRESET='0') then
x:='1';
elsif (CLOCK='1' and CLOCK'EVENT) then
if (S='0' and R='0') then
x:=x;
elsif (S='1' and R='1')then
x:='Z';
elsif (S='0' and R='1')then
x:='0';
else
x:='1';
end if;
end if;
Q <= x;
QN <= not x;
end process FF;
end Arch_sync_RS; | gpl-2.0 | 8d82e36d40cbf4c10c94974a2cee293e | 0.581845 | 2.4 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_pkg.vhd | 1 | 11,862 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_eb_fifo_counted_resized_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_eb_fifo_counted_resized_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_eb_fifo_counted_resized_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
VALID : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_eb_fifo_counted_resized_pkg;
PACKAGE BODY k7_eb_fifo_counted_resized_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_eb_fifo_counted_resized_pkg;
| gpl-2.0 | b91ac550a71280f58b27d3a29f171c23 | 0.508262 | 3.90969 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_pctrl.vhd | 1 | 18,589 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
ENTITY rd_fifo_256to64_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF rd_fifo_256to64_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 100 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | 4b9dc1c986ec9f6f2d7ce071f2188c61 | 0.509441 | 3.23512 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_gpio_0_0/sim/cpu_axi_gpio_0_0.vhd | 1 | 9,086 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY cpu_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END cpu_axi_gpio_0_0;
ARCHITECTURE cpu_axi_gpio_0_0_arch OF cpu_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 16,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000013",
C_TRI_DEFAULT => X"FFFFFF2C",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END cpu_axi_gpio_0_0_arch;
| gpl-3.0 | 0a8a9dc932af698793f4b3f96ccf91a9 | 0.678847 | 3.223129 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/netgen/synthesis/controller_synthesis.vhd | 1 | 471,899 | --------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: P.20131013
-- \ \ Application: netgen
-- / / Filename: controller_synthesis.vhd
-- /___/ /\ Timestamp: Sat Jul 04 18:44:17 2015
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm controller -w -dir netgen/synthesis -ofmt vhdl -sim controller.ngc controller_synthesis.vhd
-- Device : xc7a100t-1-csg324
-- Input file : controller.ngc
-- Output file : C:\Users\saidwivedi\OneDrive\Project\NIT\ANN_proto_final\netgen\synthesis\controller_synthesis.vhd
-- # of Entities : 1
-- Design Name : controller
-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Command Line Tools User Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
-- synthesis translate_off
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity controller is
port (
clk : in STD_LOGIC := 'X';
reset : in STD_LOGIC := 'X'
);
end controller;
architecture Structure of controller is
component test_image
port (
clka : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 0 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
dina : in STD_LOGIC_VECTOR ( 7 downto 0 );
douta : out STD_LOGIC_VECTOR ( 7 downto 0 )
);
end component;
component weight_hid
port (
clka : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 0 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
dina : in STD_LOGIC_VECTOR ( 23 downto 0 );
douta : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component;
component weight_out
port (
clka : in STD_LOGIC := 'X';
wea : in STD_LOGIC_VECTOR ( 0 downto 0 );
addra : in STD_LOGIC_VECTOR ( 2 downto 0 );
dina : in STD_LOGIC_VECTOR ( 23 downto 0 );
douta : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component;
component mul_hid
port (
clk : in STD_LOGIC := 'X';
ce : in STD_LOGIC := 'X';
sclr : in STD_LOGIC := 'X';
bypass : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 7 downto 0 );
b : in STD_LOGIC_VECTOR ( 7 downto 0 );
s : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component;
component acticv_mul
port (
clk : in STD_LOGIC := 'X';
ce : in STD_LOGIC := 'X';
a : in STD_LOGIC_VECTOR ( 15 downto 0 );
b : in STD_LOGIC_VECTOR ( 15 downto 0 );
d : in STD_LOGIC_VECTOR ( 15 downto 0 );
p : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end component;
signal clk_BUFGP_0 : STD_LOGIC;
signal reset_IBUF_1 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shift_over_flag_34 : STD_LOGIC;
signal curr_state_FSM_FFd1_150 : STD_LOGIC;
signal \Q_n0319_3)\ : STD_LOGIC;
signal \Q_n0319_1)\ : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_7_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_6_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_5_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_4_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_3_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_2_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_1_Q : STD_LOGIC;
signal transition_num_1_output_3_7_wide_mux_4_OUT_0_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_31_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_30_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_29_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_28_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_27_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_26_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_25_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_24_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_23_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_22_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_21_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_20_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_19_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_18_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_17_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_16_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_15_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_14_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_13_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_12_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_11_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_10_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_9_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_8_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_7_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_6_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_5_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_4_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_3_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_2_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_1_Q : STD_LOGIC;
signal transition_num_31_GND_7_o_add_6_OUT_0_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_31_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_30_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_29_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_28_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_27_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_26_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_25_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_24_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_23_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_22_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_21_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_20_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_19_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_18_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_17_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_16_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_15_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_14_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_13_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_12_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_11_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_10_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_9_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_8_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_7_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_6_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_5_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_4_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_3_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_2_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_1_Q : STD_LOGIC;
signal GND_7_o_transition_num_31_mux_7_OUT_0_Q : STD_LOGIC;
signal N0 : STD_LOGIC;
signal Q_n0240_inv : STD_LOGIC;
signal curr_state_FSM_FFd3_In : STD_LOGIC;
signal curr_state_FSM_FFd2_In : STD_LOGIC;
signal curr_state_FSM_FFd1_In : STD_LOGIC;
signal curr_state_FSM_FFd3_266 : STD_LOGIC;
signal curr_state_FSM_FFd2_267 : STD_LOGIC;
signal Mcount_addra_image : STD_LOGIC;
signal Mcount_addra_image1 : STD_LOGIC;
signal Mcount_addra_image2 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q_305 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi_306 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q_307 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q_308 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1_309 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q_310 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q_311 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2_312 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q_313 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q_314 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3_315 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q_316 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q_317 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4_318 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q_319 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q_320 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5_321 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q_322 : STD_LOGIC;
signal Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323 : STD_LOGIC;
signal Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324 : STD_LOGIC;
signal layer_map_count_en_inv : STD_LOGIC;
signal layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv : STD_LOGIC;
signal layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o : STD_LOGIC;
signal layer_map_ce : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_401 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_433 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_434 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_435 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_436 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_437 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_438 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_439 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_440 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_441 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_442 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_443 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_444 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_445 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_447 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_448 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_449 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_450 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_451 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_452 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_453 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_454 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_455 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_456 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_457 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_458 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_459 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_460 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_31_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_30_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_29_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_28_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_27_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_26_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_25_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_24_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_23_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_22_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_21_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_20_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_19_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_18_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_17_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_16_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Result_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_n0056_inv : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_enable_inv : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_GND_14_o_MUX_60_o : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifted_output_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_acticv_mul_en_562 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_input_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_595 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_627 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_628 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_629 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_630 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_631 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_632 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_633 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_634 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_635 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_636 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_637 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_638 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_639 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_641 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_642 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_643 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_644 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_645 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_646 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_647 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_648 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_649 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_650 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_651 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_652 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_653 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_654 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_31_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_30_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_29_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_28_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_27_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_26_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_25_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_24_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_23_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_22_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_21_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_20_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_19_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_18_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_17_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_16_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Result_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_n0056_inv : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_GND_14_o_MUX_60_o : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_INV_16_o : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifted_output_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_acticv_mul_en_755 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_input_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_788 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_820 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_821 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_822 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_823 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_824 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_825 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_826 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_827 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_828 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_829 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_830 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_831 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_832 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_834 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_835 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_836 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_837 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_838 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_839 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_840 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_841 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_842 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_843 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_844 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_845 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_846 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_847 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_31_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_30_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_29_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_28_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_27_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_26_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_25_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_24_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_23_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_22_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_21_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_20_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_19_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_18_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_17_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_16_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Result_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_n0056_inv : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_GND_14_o_MUX_60_o : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_INV_16_o : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifted_output_temp_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_acticv_mul_en_948 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_0_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_1_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_2_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_3_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_4_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_5_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_6_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_7_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_8_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_9_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_10_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_11_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_12_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_13_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_14_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_input_temp_15_Q : STD_LOGIC;
signal N01 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_983 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_984 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_985 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_986 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_989 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_990 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_991 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_992 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_995 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_996 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_997 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_998 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127 : STD_LOGIC;
signal Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt_1128 : STD_LOGIC;
signal layer_map_activation_hid_count_map_Mcount_count_xor_7_rt_1129 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1130 : STD_LOGIC;
signal layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1131 : STD_LOGIC;
signal layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1132 : STD_LOGIC;
signal layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot_1133 : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_31_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_30_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_29_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_28_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_27_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_26_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_17_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_16_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_15_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_14_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_13_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_12_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_11_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_10_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_9_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_8_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_7_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_6_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_5_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_4_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_3_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_2_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_1_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_0_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_31_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_30_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_29_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_28_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_27_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_26_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_17_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_16_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_15_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_14_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_13_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_12_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_11_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_10_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_9_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_8_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_7_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_6_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_5_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_4_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_3_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_2_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_1_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_0_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_31_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_30_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_29_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_28_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_27_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_26_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_17_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_16_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_15_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_14_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_13_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_12_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_11_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_10_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_9_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_8_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_7_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_6_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_5_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_4_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_3_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_2_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_1_UNCONNECTED : STD_LOGIC;
signal NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_0_UNCONNECTED : STD_LOGIC;
signal image : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_hid : STD_LOGIC_VECTOR2 ( 2 downto 0 , 7 downto 0 );
signal out_weight_hid : STD_LOGIC_VECTOR ( 23 downto 0 );
signal out_weight_out : STD_LOGIC_VECTOR ( 23 downto 0 );
signal addra_image : STD_LOGIC_VECTOR ( 2 downto 0 );
signal output_3 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_2 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_1 : STD_LOGIC_VECTOR ( 7 downto 0 );
signal output_temp : STD_LOGIC_VECTOR ( 7 downto 0 );
signal transition_num : STD_LOGIC_VECTOR ( 31 downto 0 );
signal GND_7_o_GND_7_o_mux_14_OUT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal input : STD_LOGIC_VECTOR ( 7 downto 0 );
signal weight : STD_LOGIC_VECTOR2 ( 2 downto 0 , 7 downto 0 );
signal dina_image : STD_LOGIC_VECTOR ( 0 downto 0 );
signal addr_weight_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal layer_map_activation_hid_count_map_Mcount_count_cy : STD_LOGIC_VECTOR ( 6 downto 0 );
signal layer_map_activation_hid_count_map_Mcount_count_lut : STD_LOGIC_VECTOR ( 0 downto 0 );
signal layer_map_Result : STD_LOGIC_VECTOR ( 7 downto 0 );
signal layer_map_activation_hid_count_map_count : STD_LOGIC_VECTOR ( 7 downto 0 );
signal layer_map_weighted_sum : STD_LOGIC_VECTOR2 ( 2 downto 0 , 15 downto 0 );
begin
XST_VCC : VCC
port map (
P => N0
);
XST_GND : GND
port map (
G => dina_image(0)
);
output_3_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 0),
Q => output_3(0)
);
output_3_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 1),
Q => output_3(1)
);
output_3_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 2),
Q => output_3(2)
);
output_3_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 3),
Q => output_3(3)
);
output_3_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 4),
Q => output_3(4)
);
output_3_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 5),
Q => output_3(5)
);
output_3_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 6),
Q => output_3(6)
);
output_3_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(2, 7),
Q => output_3(7)
);
output_2_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 0),
Q => output_2(0)
);
output_2_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 1),
Q => output_2(1)
);
output_2_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 2),
Q => output_2(2)
);
output_2_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 3),
Q => output_2(3)
);
output_2_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 4),
Q => output_2(4)
);
output_2_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 5),
Q => output_2(5)
);
output_2_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 6),
Q => output_2(6)
);
output_2_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(1, 7),
Q => output_2(7)
);
output_1_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 0),
Q => output_1(0)
);
output_1_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 1),
Q => output_1(1)
);
output_1_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 2),
Q => output_1(2)
);
output_1_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 3),
Q => output_1(3)
);
output_1_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 4),
Q => output_1(4)
);
output_1_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 5),
Q => output_1(5)
);
output_1_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 6),
Q => output_1(6)
);
output_1_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Q_n0240_inv,
CLR => reset_IBUF_1,
D => output_hid(0, 7),
Q => output_1(7)
);
transition_num_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_0_Q,
Q => transition_num(0)
);
transition_num_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_1_Q,
Q => transition_num(1)
);
transition_num_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_2_Q,
Q => transition_num(2)
);
transition_num_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_3_Q,
Q => transition_num(3)
);
transition_num_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_4_Q,
Q => transition_num(4)
);
transition_num_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_5_Q,
Q => transition_num(5)
);
transition_num_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_6_Q,
Q => transition_num(6)
);
transition_num_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_7_Q,
Q => transition_num(7)
);
transition_num_8 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_8_Q,
Q => transition_num(8)
);
transition_num_9 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_9_Q,
Q => transition_num(9)
);
transition_num_10 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_10_Q,
Q => transition_num(10)
);
transition_num_11 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_11_Q,
Q => transition_num(11)
);
transition_num_12 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_12_Q,
Q => transition_num(12)
);
transition_num_13 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_13_Q,
Q => transition_num(13)
);
transition_num_14 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_14_Q,
Q => transition_num(14)
);
transition_num_15 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_15_Q,
Q => transition_num(15)
);
transition_num_16 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_16_Q,
Q => transition_num(16)
);
transition_num_17 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_17_Q,
Q => transition_num(17)
);
transition_num_18 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_18_Q,
Q => transition_num(18)
);
transition_num_19 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_19_Q,
Q => transition_num(19)
);
transition_num_20 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_20_Q,
Q => transition_num(20)
);
transition_num_21 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_21_Q,
Q => transition_num(21)
);
transition_num_22 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_22_Q,
Q => transition_num(22)
);
transition_num_23 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_23_Q,
Q => transition_num(23)
);
transition_num_24 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_24_Q,
Q => transition_num(24)
);
transition_num_25 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_25_Q,
Q => transition_num(25)
);
transition_num_26 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_26_Q,
Q => transition_num(26)
);
transition_num_27 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_27_Q,
Q => transition_num(27)
);
transition_num_28 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_28_Q,
Q => transition_num(28)
);
transition_num_29 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_29_Q,
Q => transition_num(29)
);
transition_num_30 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_30_Q,
Q => transition_num(30)
);
transition_num_31 : FDCE
generic map(
INIT => '1'
)
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => GND_7_o_transition_num_31_mux_7_OUT_31_Q,
Q => transition_num(31)
);
addr_weight_out_0 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => GND_7_o_GND_7_o_mux_14_OUT(0),
Q => addr_weight_out(0)
);
addr_weight_out_1 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => GND_7_o_GND_7_o_mux_14_OUT(1),
Q => addr_weight_out(1)
);
addr_weight_out_2 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => GND_7_o_GND_7_o_mux_14_OUT(2),
Q => addr_weight_out(2)
);
output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_0_Q,
Q => output_temp(0)
);
output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_1_Q,
Q => output_temp(1)
);
output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_2_Q,
Q => output_temp(2)
);
output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_3_Q,
Q => output_temp(3)
);
output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_4_Q,
Q => output_temp(4)
);
output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_5_Q,
Q => output_temp(5)
);
output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_6_Q,
Q => output_temp(6)
);
output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324,
CLR => reset_IBUF_1,
D => transition_num_1_output_3_7_wide_mux_4_OUT_7_Q,
Q => output_temp(7)
);
curr_state_FSM_FFd3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => curr_state_FSM_FFd3_In,
Q => curr_state_FSM_FFd3_266
);
curr_state_FSM_FFd2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => curr_state_FSM_FFd2_In,
Q => curr_state_FSM_FFd2_267
);
curr_state_FSM_FFd1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => curr_state_FSM_FFd1_In,
Q => curr_state_FSM_FFd1_150
);
addra_image_0 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => Mcount_addra_image,
Q => addra_image(0)
);
addra_image_1 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => Mcount_addra_image1,
Q => addra_image(1)
);
addra_image_2 : FDC
port map (
C => clk_BUFGP_0,
CLR => reset_IBUF_1,
D => Mcount_addra_image2,
Q => addra_image(2)
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q,
O => transition_num_31_GND_7_o_add_6_OUT_0_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_1_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_0_Q_275,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002,
O => transition_num_31_GND_7_o_add_6_OUT_1_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_2_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_Q_276,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003,
O => transition_num_31_GND_7_o_add_6_OUT_2_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_3_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_Q_277,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004,
O => transition_num_31_GND_7_o_add_6_OUT_3_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_4_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_Q_278,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005,
O => transition_num_31_GND_7_o_add_6_OUT_4_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_5_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_Q_279,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006,
O => transition_num_31_GND_7_o_add_6_OUT_5_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_6_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_Q_280,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007,
O => transition_num_31_GND_7_o_add_6_OUT_6_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_7_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_Q_281,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008,
O => transition_num_31_GND_7_o_add_6_OUT_7_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_8_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_Q_282,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009,
O => transition_num_31_GND_7_o_add_6_OUT_8_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_9_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_Q_283,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010,
O => transition_num_31_GND_7_o_add_6_OUT_9_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_10_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_Q_284,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011,
O => transition_num_31_GND_7_o_add_6_OUT_10_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_11_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_Q_285,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012,
O => transition_num_31_GND_7_o_add_6_OUT_11_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_12_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_Q_286,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013,
O => transition_num_31_GND_7_o_add_6_OUT_12_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_13_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_Q_287,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014,
O => transition_num_31_GND_7_o_add_6_OUT_13_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_14_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_Q_288,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015,
O => transition_num_31_GND_7_o_add_6_OUT_14_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_15_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_Q_289,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016,
O => transition_num_31_GND_7_o_add_6_OUT_15_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_16_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_Q_290,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017,
O => transition_num_31_GND_7_o_add_6_OUT_16_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_17_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_Q_291,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018,
O => transition_num_31_GND_7_o_add_6_OUT_17_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_18_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_Q_292,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019,
O => transition_num_31_GND_7_o_add_6_OUT_18_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_19_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_Q_293,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020,
O => transition_num_31_GND_7_o_add_6_OUT_19_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_20_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_Q_294,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021,
O => transition_num_31_GND_7_o_add_6_OUT_20_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_21_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_Q_295,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022,
O => transition_num_31_GND_7_o_add_6_OUT_21_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_22_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_Q_296,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023,
O => transition_num_31_GND_7_o_add_6_OUT_22_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_23_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_Q_297,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024,
O => transition_num_31_GND_7_o_add_6_OUT_23_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_24_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_Q_298,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025,
O => transition_num_31_GND_7_o_add_6_OUT_24_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_25_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_Q_299,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026,
O => transition_num_31_GND_7_o_add_6_OUT_25_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_26_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_Q_300,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027,
O => transition_num_31_GND_7_o_add_6_OUT_26_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_27_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_Q_301,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028,
O => transition_num_31_GND_7_o_add_6_OUT_27_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_28_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_Q_302,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029,
O => transition_num_31_GND_7_o_add_6_OUT_28_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_29_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_Q_303,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030,
O => transition_num_31_GND_7_o_add_6_OUT_29_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q : MUXCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304,
DI => dina_image(0),
S => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031,
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q_305
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_30_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_Q_304,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031,
O => transition_num_31_GND_7_o_add_6_OUT_30_Q
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_Q : XORCY
port map (
CI => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_Q_305,
LI => Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt_1128,
O => transition_num_31_GND_7_o_add_6_OUT_31_Q
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi : LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => transition_num(4),
I1 => transition_num(3),
I2 => transition_num(2),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi_306
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q : LUT5
generic map(
INIT => X"01000000"
)
port map (
I0 => transition_num(2),
I1 => transition_num(3),
I2 => transition_num(4),
I3 => transition_num(1),
I4 => transition_num(0),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q_307
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi_306,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_0_Q_307,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q_308
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(9),
I1 => transition_num(8),
I2 => transition_num(7),
I3 => transition_num(6),
I4 => transition_num(5),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1_309
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(5),
I1 => transition_num(6),
I2 => transition_num(7),
I3 => transition_num(8),
I4 => transition_num(9),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q_310
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_0_Q_308,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi1_309,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_1_Q_310,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q_311
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(14),
I1 => transition_num(13),
I2 => transition_num(12),
I3 => transition_num(11),
I4 => transition_num(10),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2_312
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(10),
I1 => transition_num(11),
I2 => transition_num(12),
I3 => transition_num(13),
I4 => transition_num(14),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q_313
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_1_Q_311,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi2_312,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_2_Q_313,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q_314
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(19),
I1 => transition_num(18),
I2 => transition_num(17),
I3 => transition_num(16),
I4 => transition_num(15),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3_315
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(15),
I1 => transition_num(16),
I2 => transition_num(17),
I3 => transition_num(18),
I4 => transition_num(19),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q_316
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_2_Q_314,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi3_315,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_3_Q_316,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q_317
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(24),
I1 => transition_num(23),
I2 => transition_num(22),
I3 => transition_num(21),
I4 => transition_num(20),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4_318
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(20),
I1 => transition_num(21),
I2 => transition_num(22),
I3 => transition_num(23),
I4 => transition_num(24),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q_319
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_3_Q_317,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi4_318,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_4_Q_319,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q_320
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => transition_num(29),
I1 => transition_num(28),
I2 => transition_num(27),
I3 => transition_num(26),
I4 => transition_num(25),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5_321
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => transition_num(25),
I1 => transition_num(26),
I2 => transition_num(27),
I3 => transition_num(28),
I4 => transition_num(29),
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q_322
);
Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q : MUXCY
port map (
CI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_4_Q_320,
DI => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lutdi5_321,
S => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_lut_5_Q_322,
O => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323
);
layer_map_activation_hid_count_map_Mcount_count_xor_7_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(6),
LI => layer_map_activation_hid_count_map_Mcount_count_xor_7_rt_1129,
O => layer_map_Result(7)
);
layer_map_activation_hid_count_map_Mcount_count_xor_6_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(5),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032,
O => layer_map_Result(6)
);
layer_map_activation_hid_count_map_Mcount_count_cy_6_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(5),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032,
O => layer_map_activation_hid_count_map_Mcount_count_cy(6)
);
layer_map_activation_hid_count_map_Mcount_count_xor_5_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(4),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033,
O => layer_map_Result(5)
);
layer_map_activation_hid_count_map_Mcount_count_cy_5_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(4),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033,
O => layer_map_activation_hid_count_map_Mcount_count_cy(5)
);
layer_map_activation_hid_count_map_Mcount_count_xor_4_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(3),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034,
O => layer_map_Result(4)
);
layer_map_activation_hid_count_map_Mcount_count_cy_4_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(3),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034,
O => layer_map_activation_hid_count_map_Mcount_count_cy(4)
);
layer_map_activation_hid_count_map_Mcount_count_xor_3_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(2),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035,
O => layer_map_Result(3)
);
layer_map_activation_hid_count_map_Mcount_count_cy_3_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(2),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035,
O => layer_map_activation_hid_count_map_Mcount_count_cy(3)
);
layer_map_activation_hid_count_map_Mcount_count_xor_2_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(1),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036,
O => layer_map_Result(2)
);
layer_map_activation_hid_count_map_Mcount_count_cy_2_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(1),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036,
O => layer_map_activation_hid_count_map_Mcount_count_cy(2)
);
layer_map_activation_hid_count_map_Mcount_count_xor_1_Q : XORCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(0),
LI => layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037,
O => layer_map_Result(1)
);
layer_map_activation_hid_count_map_Mcount_count_cy_1_Q : MUXCY
port map (
CI => layer_map_activation_hid_count_map_Mcount_count_cy(0),
DI => dina_image(0),
S => layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037,
O => layer_map_activation_hid_count_map_Mcount_count_cy(1)
);
layer_map_activation_hid_count_map_Mcount_count_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_activation_hid_count_map_Mcount_count_lut(0),
O => layer_map_Result(0)
);
layer_map_activation_hid_count_map_Mcount_count_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_activation_hid_count_map_Mcount_count_lut(0),
O => layer_map_activation_hid_count_map_Mcount_count_cy(0)
);
layer_map_activation_hid_count_map_count_7 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(7),
Q => layer_map_activation_hid_count_map_count(7)
);
layer_map_activation_hid_count_map_count_6 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(6),
Q => layer_map_activation_hid_count_map_count(6)
);
layer_map_activation_hid_count_map_count_5 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(5),
Q => layer_map_activation_hid_count_map_count(5)
);
layer_map_activation_hid_count_map_count_4 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(4),
Q => layer_map_activation_hid_count_map_count(4)
);
layer_map_activation_hid_count_map_count_3 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(3),
Q => layer_map_activation_hid_count_map_count(3)
);
layer_map_activation_hid_count_map_count_2 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(2),
Q => layer_map_activation_hid_count_map_count(2)
);
layer_map_activation_hid_count_map_count_1 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(1),
Q => layer_map_activation_hid_count_map_count(1)
);
layer_map_activation_hid_count_map_count_0 : FDCE
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CE => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv,
CLR => layer_map_count_en_inv,
D => layer_map_Result(0),
Q => layer_map_activation_hid_count_map_count(0)
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_401,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1130,
O => layer_map_shift_map_0_shifter_map_Result_31_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_30_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038,
O => layer_map_shift_map_0_shifter_map_Result_30_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_401
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_29_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039,
O => layer_map_shift_map_0_shifter_map_Result_29_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_402
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_28_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040,
O => layer_map_shift_map_0_shifter_map_Result_28_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_403
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_27_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041,
O => layer_map_shift_map_0_shifter_map_Result_27_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_404
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_26_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042,
O => layer_map_shift_map_0_shifter_map_Result_26_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_405
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_25_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043,
O => layer_map_shift_map_0_shifter_map_Result_25_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_406
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_24_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044,
O => layer_map_shift_map_0_shifter_map_Result_24_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_407
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_23_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045,
O => layer_map_shift_map_0_shifter_map_Result_23_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_408
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_22_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046,
O => layer_map_shift_map_0_shifter_map_Result_22_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_409
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_21_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047,
O => layer_map_shift_map_0_shifter_map_Result_21_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_410
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_20_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048,
O => layer_map_shift_map_0_shifter_map_Result_20_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_411
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_19_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049,
O => layer_map_shift_map_0_shifter_map_Result_19_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_412
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_18_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050,
O => layer_map_shift_map_0_shifter_map_Result_18_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_413
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_17_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051,
O => layer_map_shift_map_0_shifter_map_Result_17_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_414
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_16_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052,
O => layer_map_shift_map_0_shifter_map_Result_16_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_415
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_15_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053,
O => layer_map_shift_map_0_shifter_map_Result_15_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_416
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_14_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054,
O => layer_map_shift_map_0_shifter_map_Result_14_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_417
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_13_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055,
O => layer_map_shift_map_0_shifter_map_Result_13_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_418
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_12_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056,
O => layer_map_shift_map_0_shifter_map_Result_12_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_419
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_11_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057,
O => layer_map_shift_map_0_shifter_map_Result_11_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_420
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_10_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058,
O => layer_map_shift_map_0_shifter_map_Result_10_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_421
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_9_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059,
O => layer_map_shift_map_0_shifter_map_Result_9_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_422
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_8_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060,
O => layer_map_shift_map_0_shifter_map_Result_8_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_423
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_7_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061,
O => layer_map_shift_map_0_shifter_map_Result_7_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_424
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_6_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062,
O => layer_map_shift_map_0_shifter_map_Result_6_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_425
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_5_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063,
O => layer_map_shift_map_0_shifter_map_Result_5_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_426
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_4_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064,
O => layer_map_shift_map_0_shifter_map_Result_4_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_427
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_3_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065,
O => layer_map_shift_map_0_shifter_map_Result_3_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_428
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_2_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066,
O => layer_map_shift_map_0_shifter_map_Result_2_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_429
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_1_Q : XORCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431,
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067,
O => layer_map_shift_map_0_shifter_map_Result_1_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_430
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_0_shifter_map_Result_0_Q
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_431
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_433,
DI => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987,
O => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_435,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_434,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_433
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_434
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_437,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_436,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_435
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_436
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_439,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_438,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_437
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_438
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_441,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_440,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_439
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_440
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_443,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_442,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_441
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_442
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_445,
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_444,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_443
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_444
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_445
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_448,
DI => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_447,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_447
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_450,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_449,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_448
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_449
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_452,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_451,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_450
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_451
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_454,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_453,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_452
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_453
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_456,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_455,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_454
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_455
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_458,
DI => dina_image(0),
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_457,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_456
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_457
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_460,
S => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_459,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_458
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_459
);
layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_460
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_31 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_31_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_30 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_30_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_29 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_29_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_28 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_28_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_27 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_27_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_26 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_26_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_25 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_25_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_24 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_24_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_23 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_23_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_22 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_22_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_21 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_21_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_20 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_20_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_19 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_19_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_18 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_18_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_17 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_17_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_16 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_16_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_15_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_14_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_13_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_12_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_11_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_10_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_9_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_8_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_7_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_6_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_5_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_4_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_3_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_2_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_1_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q
);
layer_map_shift_map_0_shifter_map_shifter_shift_counter_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_Result_0_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q
);
layer_map_shift_map_0_shifter_map_acticv_mul_en : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_GND_14_o_GND_14_o_MUX_60_o,
Q => layer_map_shift_map_0_shifter_map_acticv_mul_en_562
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_15_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_14_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_13_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_12_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_11_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_10_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_9_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_8_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_7_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_6_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_5_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_4_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_3_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_2_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_1_Q
);
layer_map_shift_map_0_shifter_map_shifted_output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_0_Q,
Q => layer_map_shift_map_0_shifter_map_shifted_output_temp_0_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q
);
layer_map_shift_map_0_shifter_map_shifter_temp_reg_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q,
Q => layer_map_shift_map_0_shifter_map_shifter_temp_reg_0_Q
);
layer_map_shift_map_0_shifter_map_input_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 15),
Q => layer_map_shift_map_0_shifter_map_input_temp_15_Q
);
layer_map_shift_map_0_shifter_map_input_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 14),
Q => layer_map_shift_map_0_shifter_map_input_temp_14_Q
);
layer_map_shift_map_0_shifter_map_input_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 13),
Q => layer_map_shift_map_0_shifter_map_input_temp_13_Q
);
layer_map_shift_map_0_shifter_map_input_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 12),
Q => layer_map_shift_map_0_shifter_map_input_temp_12_Q
);
layer_map_shift_map_0_shifter_map_input_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 11),
Q => layer_map_shift_map_0_shifter_map_input_temp_11_Q
);
layer_map_shift_map_0_shifter_map_input_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 10),
Q => layer_map_shift_map_0_shifter_map_input_temp_10_Q
);
layer_map_shift_map_0_shifter_map_input_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 9),
Q => layer_map_shift_map_0_shifter_map_input_temp_9_Q
);
layer_map_shift_map_0_shifter_map_input_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 8),
Q => layer_map_shift_map_0_shifter_map_input_temp_8_Q
);
layer_map_shift_map_0_shifter_map_input_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 7),
Q => layer_map_shift_map_0_shifter_map_input_temp_7_Q
);
layer_map_shift_map_0_shifter_map_input_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 6),
Q => layer_map_shift_map_0_shifter_map_input_temp_6_Q
);
layer_map_shift_map_0_shifter_map_input_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 5),
Q => layer_map_shift_map_0_shifter_map_input_temp_5_Q
);
layer_map_shift_map_0_shifter_map_input_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 4),
Q => layer_map_shift_map_0_shifter_map_input_temp_4_Q
);
layer_map_shift_map_0_shifter_map_input_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 3),
Q => layer_map_shift_map_0_shifter_map_input_temp_3_Q
);
layer_map_shift_map_0_shifter_map_input_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 2),
Q => layer_map_shift_map_0_shifter_map_input_temp_2_Q
);
layer_map_shift_map_0_shifter_map_input_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 1),
Q => layer_map_shift_map_0_shifter_map_input_temp_1_Q
);
layer_map_shift_map_0_shifter_map_input_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(0, 0),
Q => layer_map_shift_map_0_shifter_map_input_temp_0_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_595,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1131,
O => layer_map_shift_map_1_shifter_map_Result_31_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_30_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068,
O => layer_map_shift_map_1_shifter_map_Result_30_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_595
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_29_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069,
O => layer_map_shift_map_1_shifter_map_Result_29_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_596
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_28_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070,
O => layer_map_shift_map_1_shifter_map_Result_28_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_597
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_27_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071,
O => layer_map_shift_map_1_shifter_map_Result_27_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_598
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_26_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072,
O => layer_map_shift_map_1_shifter_map_Result_26_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_599
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_25_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073,
O => layer_map_shift_map_1_shifter_map_Result_25_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_600
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_24_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074,
O => layer_map_shift_map_1_shifter_map_Result_24_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_601
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_23_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075,
O => layer_map_shift_map_1_shifter_map_Result_23_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_602
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_22_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076,
O => layer_map_shift_map_1_shifter_map_Result_22_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_603
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_21_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077,
O => layer_map_shift_map_1_shifter_map_Result_21_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_604
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_20_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078,
O => layer_map_shift_map_1_shifter_map_Result_20_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_605
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_19_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079,
O => layer_map_shift_map_1_shifter_map_Result_19_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_606
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_18_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080,
O => layer_map_shift_map_1_shifter_map_Result_18_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_607
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_17_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081,
O => layer_map_shift_map_1_shifter_map_Result_17_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_608
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_16_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082,
O => layer_map_shift_map_1_shifter_map_Result_16_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_609
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_15_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083,
O => layer_map_shift_map_1_shifter_map_Result_15_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_610
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_14_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084,
O => layer_map_shift_map_1_shifter_map_Result_14_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_611
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_13_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085,
O => layer_map_shift_map_1_shifter_map_Result_13_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_612
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_12_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086,
O => layer_map_shift_map_1_shifter_map_Result_12_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_613
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_11_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087,
O => layer_map_shift_map_1_shifter_map_Result_11_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_614
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_10_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088,
O => layer_map_shift_map_1_shifter_map_Result_10_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_615
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_9_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089,
O => layer_map_shift_map_1_shifter_map_Result_9_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_616
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_8_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090,
O => layer_map_shift_map_1_shifter_map_Result_8_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_617
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_7_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091,
O => layer_map_shift_map_1_shifter_map_Result_7_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_618
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_6_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092,
O => layer_map_shift_map_1_shifter_map_Result_6_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_619
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_5_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093,
O => layer_map_shift_map_1_shifter_map_Result_5_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_620
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_4_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094,
O => layer_map_shift_map_1_shifter_map_Result_4_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_621
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_3_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095,
O => layer_map_shift_map_1_shifter_map_Result_3_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_622
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_2_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096,
O => layer_map_shift_map_1_shifter_map_Result_2_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_623
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_1_Q : XORCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625,
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097,
O => layer_map_shift_map_1_shifter_map_Result_1_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_624
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_1_shifter_map_Result_0_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_625
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_627,
DI => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993,
O => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_INV_16_o
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_629,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_628,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_627
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_628
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_631,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_630,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_629
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_630
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_633,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_632,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_631
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_632
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_635,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_634,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_633
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_634
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_637,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_636,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_635
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_636
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_639,
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_638,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_637
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_638
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_639
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_642,
DI => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_641,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_641
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_644,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_643,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_642
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_643
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_646,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_645,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_644
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_645
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_648,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_647,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_646
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_647
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_650,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_649,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_648
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_649
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_652,
DI => dina_image(0),
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_651,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_650
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_651
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_654,
S => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_653,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_652
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_653
);
layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_654
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_31 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_31_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_30 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_30_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_29 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_29_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_28 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_28_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_27 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_27_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_26 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_26_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_25 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_25_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_24 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_24_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_23 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_23_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_22 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_22_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_21 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_21_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_20 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_20_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_19 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_19_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_18 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_18_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_17 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_17_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_16 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_16_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_15_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_14_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_13_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_12_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_11_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_10_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_9_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_8_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_7_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_6_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_5_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_4_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_3_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_2_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_1_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q
);
layer_map_shift_map_1_shifter_map_shifter_shift_counter_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_Result_0_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q
);
layer_map_shift_map_1_shifter_map_acticv_mul_en : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_GND_14_o_GND_14_o_MUX_60_o,
Q => layer_map_shift_map_1_shifter_map_acticv_mul_en_755
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_15_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_14_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_13_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_12_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_11_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_10_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_9_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_8_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_7_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_6_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_5_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_4_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_3_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_2_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_1_Q
);
layer_map_shift_map_1_shifter_map_shifted_output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_0_Q,
Q => layer_map_shift_map_1_shifter_map_shifted_output_temp_0_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q
);
layer_map_shift_map_1_shifter_map_shifter_temp_reg_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q,
Q => layer_map_shift_map_1_shifter_map_shifter_temp_reg_0_Q
);
layer_map_shift_map_1_shifter_map_input_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 15),
Q => layer_map_shift_map_1_shifter_map_input_temp_15_Q
);
layer_map_shift_map_1_shifter_map_input_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 14),
Q => layer_map_shift_map_1_shifter_map_input_temp_14_Q
);
layer_map_shift_map_1_shifter_map_input_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 13),
Q => layer_map_shift_map_1_shifter_map_input_temp_13_Q
);
layer_map_shift_map_1_shifter_map_input_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 12),
Q => layer_map_shift_map_1_shifter_map_input_temp_12_Q
);
layer_map_shift_map_1_shifter_map_input_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 11),
Q => layer_map_shift_map_1_shifter_map_input_temp_11_Q
);
layer_map_shift_map_1_shifter_map_input_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 10),
Q => layer_map_shift_map_1_shifter_map_input_temp_10_Q
);
layer_map_shift_map_1_shifter_map_input_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 9),
Q => layer_map_shift_map_1_shifter_map_input_temp_9_Q
);
layer_map_shift_map_1_shifter_map_input_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 8),
Q => layer_map_shift_map_1_shifter_map_input_temp_8_Q
);
layer_map_shift_map_1_shifter_map_input_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 7),
Q => layer_map_shift_map_1_shifter_map_input_temp_7_Q
);
layer_map_shift_map_1_shifter_map_input_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 6),
Q => layer_map_shift_map_1_shifter_map_input_temp_6_Q
);
layer_map_shift_map_1_shifter_map_input_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 5),
Q => layer_map_shift_map_1_shifter_map_input_temp_5_Q
);
layer_map_shift_map_1_shifter_map_input_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 4),
Q => layer_map_shift_map_1_shifter_map_input_temp_4_Q
);
layer_map_shift_map_1_shifter_map_input_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 3),
Q => layer_map_shift_map_1_shifter_map_input_temp_3_Q
);
layer_map_shift_map_1_shifter_map_input_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 2),
Q => layer_map_shift_map_1_shifter_map_input_temp_2_Q
);
layer_map_shift_map_1_shifter_map_input_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 1),
Q => layer_map_shift_map_1_shifter_map_input_temp_1_Q
);
layer_map_shift_map_1_shifter_map_input_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(1, 0),
Q => layer_map_shift_map_1_shifter_map_input_temp_0_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_788,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1132,
O => layer_map_shift_map_2_shifter_map_Result_31_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_30_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098,
O => layer_map_shift_map_2_shifter_map_Result_30_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_Q_788
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_29_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099,
O => layer_map_shift_map_2_shifter_map_Result_29_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_Q_789
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_28_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100,
O => layer_map_shift_map_2_shifter_map_Result_28_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_Q_790
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_27_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101,
O => layer_map_shift_map_2_shifter_map_Result_27_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_Q_791
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_26_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102,
O => layer_map_shift_map_2_shifter_map_Result_26_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_Q_792
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_25_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103,
O => layer_map_shift_map_2_shifter_map_Result_25_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_Q_793
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_24_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104,
O => layer_map_shift_map_2_shifter_map_Result_24_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_Q_794
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_23_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105,
O => layer_map_shift_map_2_shifter_map_Result_23_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_Q_795
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_22_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106,
O => layer_map_shift_map_2_shifter_map_Result_22_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_Q_796
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_21_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107,
O => layer_map_shift_map_2_shifter_map_Result_21_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_Q_797
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_20_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108,
O => layer_map_shift_map_2_shifter_map_Result_20_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_Q_798
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_19_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109,
O => layer_map_shift_map_2_shifter_map_Result_19_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_Q_799
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_18_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110,
O => layer_map_shift_map_2_shifter_map_Result_18_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_Q_800
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_17_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111,
O => layer_map_shift_map_2_shifter_map_Result_17_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_Q_801
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_16_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112,
O => layer_map_shift_map_2_shifter_map_Result_16_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_Q_802
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_15_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113,
O => layer_map_shift_map_2_shifter_map_Result_15_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_Q_803
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_14_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114,
O => layer_map_shift_map_2_shifter_map_Result_14_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_Q_804
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_13_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115,
O => layer_map_shift_map_2_shifter_map_Result_13_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_Q_805
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_12_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116,
O => layer_map_shift_map_2_shifter_map_Result_12_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_Q_806
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_11_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117,
O => layer_map_shift_map_2_shifter_map_Result_11_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_Q_807
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_10_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118,
O => layer_map_shift_map_2_shifter_map_Result_10_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_Q_808
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_9_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119,
O => layer_map_shift_map_2_shifter_map_Result_9_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_Q_809
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_8_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120,
O => layer_map_shift_map_2_shifter_map_Result_8_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_Q_810
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_7_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121,
O => layer_map_shift_map_2_shifter_map_Result_7_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_Q_811
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_6_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122,
O => layer_map_shift_map_2_shifter_map_Result_6_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_Q_812
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_5_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123,
O => layer_map_shift_map_2_shifter_map_Result_5_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_Q_813
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_4_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124,
O => layer_map_shift_map_2_shifter_map_Result_4_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_Q_814
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_3_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125,
O => layer_map_shift_map_2_shifter_map_Result_3_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_Q_815
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_2_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126,
O => layer_map_shift_map_2_shifter_map_Result_2_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_Q_816
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_1_Q : XORCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818,
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127,
O => layer_map_shift_map_2_shifter_map_Result_1_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_Q_817
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_0_Q : XORCY
port map (
CI => dina_image(0),
LI => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_2_shifter_map_Result_0_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q : MUXCY
port map (
CI => dina_image(0),
DI => N0,
S => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_0_Q_818
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_820,
DI => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999,
O => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_INV_16_o
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_822,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_821,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_5_Q_820
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_5_Q_821
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_824,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_823,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_4_Q_822
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_4_Q_823
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_826,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_825,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_3_Q_824
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_3_Q_825
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_828,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_827,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_2_Q_826
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_2_Q_827
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_830,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_829,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_1_Q_828
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_1_Q_829
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_832,
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_831,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_cy_0_Q_830
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lut_0_Q_831
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi : LUT3
generic map(
INIT => X"01"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_INV_16_o_lutdi_832
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_835,
DI => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_834,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_6_Q_834
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_837,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_836,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_5_Q_835
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_5_Q_836
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_839,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_838,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_4_Q_837
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_4_Q_838
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_841,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_840,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_3_Q_839
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_3_Q_840
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_843,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_842,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_2_Q_841
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_2_Q_842
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q : MUXCY
port map (
CI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_845,
DI => dina_image(0),
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_844,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_1_Q_843
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q : LUT5
generic map(
INIT => X"00000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_1_Q_844
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q : MUXCY
port map (
CI => N0,
DI => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_847,
S => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_846,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_0_Q_845
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q : LUT5
generic map(
INIT => X"00010000"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lut_0_Q_846
);
layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi : LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_lutdi_847
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_31 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_31_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_30 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_30_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_29 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_29_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_28 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_28_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_27 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_27_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_26 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_26_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_25 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_25_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_24 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_24_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_23 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_23_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_22 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_22_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_21 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_21_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_20 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_20_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_19 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_19_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_18 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_18_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_17 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_17_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_16 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_16_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_15_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_14_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_13_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_12_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_11_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_10_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_9_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_8_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_7_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_6_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_5_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_4_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_3_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_2_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_1_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q
);
layer_map_shift_map_2_shifter_map_shifter_shift_counter_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_Result_0_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q
);
layer_map_shift_map_2_shifter_map_acticv_mul_en : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_GND_14_o_GND_14_o_MUX_60_o,
Q => layer_map_shift_map_2_shifter_map_acticv_mul_en_948
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_15_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_14_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_13_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_12_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_11_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_10_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_9_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_8_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_7_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_6_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_5_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_4_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_3_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_2_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_1_Q
);
layer_map_shift_map_2_shifter_map_shifted_output_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_n0056_inv,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_0_Q,
Q => layer_map_shift_map_2_shifter_map_shifted_output_temp_0_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_15 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_14 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_13 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_12 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_11 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_10 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_9 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_8 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_7 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_6 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_5 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_4 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_3 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_2 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_1 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q
);
layer_map_shift_map_2_shifter_map_shifter_temp_reg_0 : FDC
generic map(
INIT => '0'
)
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q,
Q => layer_map_shift_map_2_shifter_map_shifter_temp_reg_0_Q
);
layer_map_shift_map_2_shifter_map_input_temp_15 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 15),
Q => layer_map_shift_map_2_shifter_map_input_temp_15_Q
);
layer_map_shift_map_2_shifter_map_input_temp_14 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 14),
Q => layer_map_shift_map_2_shifter_map_input_temp_14_Q
);
layer_map_shift_map_2_shifter_map_input_temp_13 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 13),
Q => layer_map_shift_map_2_shifter_map_input_temp_13_Q
);
layer_map_shift_map_2_shifter_map_input_temp_12 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 12),
Q => layer_map_shift_map_2_shifter_map_input_temp_12_Q
);
layer_map_shift_map_2_shifter_map_input_temp_11 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 11),
Q => layer_map_shift_map_2_shifter_map_input_temp_11_Q
);
layer_map_shift_map_2_shifter_map_input_temp_10 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 10),
Q => layer_map_shift_map_2_shifter_map_input_temp_10_Q
);
layer_map_shift_map_2_shifter_map_input_temp_9 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 9),
Q => layer_map_shift_map_2_shifter_map_input_temp_9_Q
);
layer_map_shift_map_2_shifter_map_input_temp_8 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 8),
Q => layer_map_shift_map_2_shifter_map_input_temp_8_Q
);
layer_map_shift_map_2_shifter_map_input_temp_7 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 7),
Q => layer_map_shift_map_2_shifter_map_input_temp_7_Q
);
layer_map_shift_map_2_shifter_map_input_temp_6 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 6),
Q => layer_map_shift_map_2_shifter_map_input_temp_6_Q
);
layer_map_shift_map_2_shifter_map_input_temp_5 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 5),
Q => layer_map_shift_map_2_shifter_map_input_temp_5_Q
);
layer_map_shift_map_2_shifter_map_input_temp_4 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 4),
Q => layer_map_shift_map_2_shifter_map_input_temp_4_Q
);
layer_map_shift_map_2_shifter_map_input_temp_3 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 3),
Q => layer_map_shift_map_2_shifter_map_input_temp_3_Q
);
layer_map_shift_map_2_shifter_map_input_temp_2 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 2),
Q => layer_map_shift_map_2_shifter_map_input_temp_2_Q
);
layer_map_shift_map_2_shifter_map_input_temp_1 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 1),
Q => layer_map_shift_map_2_shifter_map_input_temp_1_Q
);
layer_map_shift_map_2_shifter_map_input_temp_0 : FDCE
port map (
C => clk_BUFGP_0,
CE => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_weighted_sum(2, 0),
Q => layer_map_shift_map_2_shifter_map_input_temp_0_Q
);
Q_n0319_3_1 : LUT2
generic map(
INIT => X"4"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
O => \Q_n0319_3)\
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT211 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
O => Mmux_GND_7_o_GND_7_o_mux_14_OUT21_324
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT81 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(7),
I3 => output_3(7),
I4 => output_2(7),
O => transition_num_1_output_3_7_wide_mux_4_OUT_7_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT71 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(6),
I3 => output_3(6),
I4 => output_2(6),
O => transition_num_1_output_3_7_wide_mux_4_OUT_6_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT61 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(5),
I3 => output_3(5),
I4 => output_2(5),
O => transition_num_1_output_3_7_wide_mux_4_OUT_5_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT51 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(4),
I3 => output_3(4),
I4 => output_2(4),
O => transition_num_1_output_3_7_wide_mux_4_OUT_4_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT41 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(3),
I3 => output_3(3),
I4 => output_2(3),
O => transition_num_1_output_3_7_wide_mux_4_OUT_3_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT31 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(2),
I3 => output_3(2),
I4 => output_2(2),
O => transition_num_1_output_3_7_wide_mux_4_OUT_2_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT21 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(1),
I3 => output_3(1),
I4 => output_2(1),
O => transition_num_1_output_3_7_wide_mux_4_OUT_1_Q
);
Mmux_transition_num_1_output_3_7_wide_mux_4_OUT11 : LUT5
generic map(
INIT => X"EC64A820"
)
port map (
I0 => transition_num(0),
I1 => transition_num(1),
I2 => output_1(0),
I3 => output_3(0),
I4 => output_2(0),
O => transition_num_1_output_3_7_wide_mux_4_OUT_0_Q
);
Q_n0240_inv1 : LUT3
generic map(
INIT => X"28"
)
port map (
I0 => curr_state_FSM_FFd2_267,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
O => Q_n0240_inv
);
Q_n0319_1_1 : LUT3
generic map(
INIT => X"54"
)
port map (
I0 => curr_state_FSM_FFd3_266,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd2_267,
O => \Q_n0319_1)\
);
input_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(7),
I4 => image(7),
O => input(7)
);
input_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(6),
I4 => image(6),
O => input(6)
);
input_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(5),
I4 => image(5),
O => input(5)
);
input_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(4),
I4 => image(4),
O => input(4)
);
input_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(3),
I4 => image(3),
O => input(3)
);
input_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(2),
I4 => image(2),
O => input(2)
);
input_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(1),
I4 => image(1),
O => input(1)
);
input_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => output_temp(0),
I4 => image(0),
O => input(0)
);
weight_2_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(23),
I4 => out_weight_hid(23),
O => weight(2, 7)
);
weight_2_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(22),
I4 => out_weight_hid(22),
O => weight(2, 6)
);
weight_2_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(21),
I4 => out_weight_hid(21),
O => weight(2, 5)
);
weight_2_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(20),
I4 => out_weight_hid(20),
O => weight(2, 4)
);
weight_2_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(19),
I4 => out_weight_hid(19),
O => weight(2, 3)
);
weight_2_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(18),
I4 => out_weight_hid(18),
O => weight(2, 2)
);
weight_2_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(17),
I4 => out_weight_hid(17),
O => weight(2, 1)
);
weight_2_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(16),
I4 => out_weight_hid(16),
O => weight(2, 0)
);
weight_1_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(15),
I4 => out_weight_hid(15),
O => weight(1, 7)
);
weight_1_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(14),
I4 => out_weight_hid(14),
O => weight(1, 6)
);
weight_1_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(13),
I4 => out_weight_hid(13),
O => weight(1, 5)
);
weight_1_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(12),
I4 => out_weight_hid(12),
O => weight(1, 4)
);
weight_1_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(11),
I4 => out_weight_hid(11),
O => weight(1, 3)
);
weight_1_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(10),
I4 => out_weight_hid(10),
O => weight(1, 2)
);
weight_1_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(9),
I4 => out_weight_hid(9),
O => weight(1, 1)
);
weight_1_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(8),
I4 => out_weight_hid(8),
O => weight(1, 0)
);
weight_0_7_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(7),
I4 => out_weight_hid(7),
O => weight(0, 7)
);
weight_0_6_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(6),
I4 => out_weight_hid(6),
O => weight(0, 6)
);
weight_0_5_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(5),
I4 => out_weight_hid(5),
O => weight(0, 5)
);
weight_0_4_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(4),
I4 => out_weight_hid(4),
O => weight(0, 4)
);
weight_0_3_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(3),
I4 => out_weight_hid(3),
O => weight(0, 3)
);
weight_0_2_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(2),
I4 => out_weight_hid(2),
O => weight(0, 2)
);
weight_0_1_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(1),
I4 => out_weight_hid(1),
O => weight(0, 1)
);
weight_0_0_1 : LUT5
generic map(
INIT => X"14041000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => out_weight_out(0),
I4 => out_weight_hid(0),
O => weight(0, 0)
);
Mcount_addra_image_xor_0_11 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addra_image(0),
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
I3 => curr_state_FSM_FFd2_267,
O => Mcount_addra_image
);
Mcount_addra_image_xor_1_11 : LUT5
generic map(
INIT => X"00101000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd3_266,
I3 => addra_image(0),
I4 => addra_image(1),
O => Mcount_addra_image1
);
Mcount_addra_image_xor_2_11 : LUT6
generic map(
INIT => X"0010100010001000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd3_266,
I3 => addra_image(2),
I4 => addra_image(0),
I5 => addra_image(1),
O => Mcount_addra_image2
);
layer_map_shift_map_0_shifter_map_Mmux_GND_14_o_GND_14_o_MUX_60_o11 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o,
O => layer_map_shift_map_0_shifter_map_GND_14_o_GND_14_o_MUX_60_o
);
layer_map_shift_map_0_shifter_map_n0056_inv1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
O => layer_map_shift_map_0_shifter_map_n0056_inv
);
layer_map_shift_map_1_shifter_map_Mmux_GND_14_o_GND_14_o_MUX_60_o11 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_INV_16_o,
O => layer_map_shift_map_1_shifter_map_GND_14_o_GND_14_o_MUX_60_o
);
layer_map_shift_map_1_shifter_map_n0056_inv1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
O => layer_map_shift_map_1_shifter_map_n0056_inv
);
layer_map_shift_map_2_shifter_map_Mmux_GND_14_o_GND_14_o_MUX_60_o11 : LUT3
generic map(
INIT => X"10"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_INV_16_o,
O => layer_map_shift_map_2_shifter_map_GND_14_o_GND_14_o_MUX_60_o
);
layer_map_shift_map_2_shifter_map_n0056_inv1 : LUT2
generic map(
INIT => X"1"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
O => layer_map_shift_map_2_shifter_map_n0056_inv
);
layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o8_SW0 : LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => layer_map_activation_hid_count_map_count(7),
I1 => layer_map_activation_hid_count_map_count(6),
I2 => layer_map_activation_hid_count_map_count(5),
I3 => layer_map_activation_hid_count_map_count(4),
I4 => layer_map_activation_hid_count_map_count(3),
O => N01
);
layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o8 : LUT6
generic map(
INIT => X"4001000000004001"
)
port map (
I0 => N01,
I1 => layer_map_activation_hid_count_map_count(1),
I2 => layer_map_activation_hid_count_map_count(0),
I3 => \Q_n0319_1)\,
I4 => \Q_n0319_3)\,
I5 => layer_map_activation_hid_count_map_count(2),
O => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_983
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_984
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_985
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
I3 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
I4 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
I5 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_986
);
layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_7 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q,
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_983,
I2 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_984,
I3 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_985,
I4 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_986,
I5 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_987,
O => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_989
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_990
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_991
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
I2 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
I3 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
I4 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
I5 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_992
);
layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_7 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q,
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_989,
I2 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_990,
I3 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_991,
I4 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_992,
I5 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_993,
O => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_995
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_996
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_997
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5 : LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
I1 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
I2 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
I3 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
I4 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
I5 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_998
);
layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_7 : LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_Q,
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_1_995,
I2 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_2_996,
I3 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_3_997,
I4 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_4_998,
I5 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o_31_5_999,
O => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o
);
reset_IBUF : IBUF
port map (
I => reset,
O => reset_IBUF_1
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(1),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_1_rt_1002
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(2),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_2_rt_1003
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(3),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_3_rt_1004
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(4),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_4_rt_1005
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(5),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_5_rt_1006
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(6),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_6_rt_1007
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(7),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_7_rt_1008
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(8),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_8_rt_1009
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(9),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_9_rt_1010
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(10),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_10_rt_1011
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(11),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_11_rt_1012
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(12),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_12_rt_1013
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(13),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_13_rt_1014
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(14),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_14_rt_1015
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(15),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_15_rt_1016
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(16),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_16_rt_1017
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(17),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_17_rt_1018
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(18),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_18_rt_1019
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(19),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_19_rt_1020
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(20),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_20_rt_1021
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(21),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_21_rt_1022
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(22),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_22_rt_1023
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(23),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_23_rt_1024
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(24),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_24_rt_1025
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(25),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_25_rt_1026
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(26),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_26_rt_1027
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(27),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_27_rt_1028
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(28),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_28_rt_1029
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(29),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_29_rt_1030
);
Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(30),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_cy_30_rt_1031
);
layer_map_activation_hid_count_map_Mcount_count_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(6),
O => layer_map_activation_hid_count_map_Mcount_count_cy_6_rt_1032
);
layer_map_activation_hid_count_map_Mcount_count_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(5),
O => layer_map_activation_hid_count_map_Mcount_count_cy_5_rt_1033
);
layer_map_activation_hid_count_map_Mcount_count_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(4),
O => layer_map_activation_hid_count_map_Mcount_count_cy_4_rt_1034
);
layer_map_activation_hid_count_map_Mcount_count_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(3),
O => layer_map_activation_hid_count_map_Mcount_count_cy_3_rt_1035
);
layer_map_activation_hid_count_map_Mcount_count_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(2),
O => layer_map_activation_hid_count_map_Mcount_count_cy_2_rt_1036
);
layer_map_activation_hid_count_map_Mcount_count_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(1),
O => layer_map_activation_hid_count_map_Mcount_count_cy_1_rt_1037
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_30_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1038
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1039
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_28_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1040
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_27_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1041
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_26_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1042
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_25_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1043
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1044
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1045
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_22_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1046
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_21_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1047
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_20_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1048
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1049
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_18_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1050
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1051
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_16_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1052
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_15_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1053
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1054
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_13_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1055
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_12_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1056
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1057
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_10_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1058
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1059
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_8_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1060
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_7_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1061
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_6_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1062
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1063
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1064
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_3_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1065
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1066
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1067
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_30_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1068
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1069
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_28_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1070
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_27_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1071
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_26_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1072
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_25_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1073
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1074
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1075
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_22_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1076
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_21_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1077
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_20_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1078
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1079
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_18_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1080
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1081
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_16_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1082
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_15_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1083
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1084
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_13_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1085
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_12_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1086
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1087
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_10_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1088
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1089
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_8_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1090
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_7_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1091
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_6_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1092
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1093
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1094
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_3_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1095
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1096
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1097
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_30_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_30_rt_1098
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_29_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_29_rt_1099
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_28_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_28_rt_1100
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_27_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_27_rt_1101
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_26_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_26_rt_1102
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_25_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_25_rt_1103
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_24_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_24_rt_1104
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_23_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_23_rt_1105
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_22_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_22_rt_1106
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_21_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_21_rt_1107
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_20_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_20_rt_1108
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_19_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_19_rt_1109
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_18_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_18_rt_1110
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_17_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_17_rt_1111
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_16_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_16_rt_1112
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_15_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_15_rt_1113
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_14_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_14_rt_1114
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_13_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_13_rt_1115
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_12_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_12_rt_1116
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_11_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_11_rt_1117
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_10_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_10_rt_1118
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_9_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_9_rt_1119
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_8_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_8_rt_1120
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_7_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_7_rt_1121
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_6_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_6_rt_1122
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_5_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_5_rt_1123
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_4_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_4_rt_1124
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_3_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_3_rt_1125
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_2_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_2_rt_1126
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_1_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_cy_1_rt_1127
);
Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => transition_num(31),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_xor_31_rt_1128
);
layer_map_activation_hid_count_map_Mcount_count_xor_7_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_activation_hid_count_map_count(7),
O => layer_map_activation_hid_count_map_Mcount_count_xor_7_rt_1129
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1130
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_1_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1131
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt : LUT1
generic map(
INIT => X"2"
)
port map (
I0 => layer_map_shift_map_2_shifter_map_shifter_shift_counter_31_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_xor_31_rt_1132
);
layer_map_shift_map_0_shifter_map_shift_over_flag : FDC
port map (
C => clk_BUFGP_0,
CLR => layer_map_shift_map_0_shifter_map_enable_inv,
D => layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot_1133,
Q => layer_map_shift_map_0_shifter_map_shift_over_flag_34
);
layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot : LUT4
generic map(
INIT => X"FF01"
)
port map (
I0 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I1 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I2 => layer_map_shift_map_0_shifter_map_shifter_shift_counter_31_INV_16_o,
I3 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
O => layer_map_shift_map_0_shifter_map_shift_over_flag_rstpot_1133
);
layer_map_count_en_inv1 : LUT3
generic map(
INIT => X"EB"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
O => layer_map_count_en_inv
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT18 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 0),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_1_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT21 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 10),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_11_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT31 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 11),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_12_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT41 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 12),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_13_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT51 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 13),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_14_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT71 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 15),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT81 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 1),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_2_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT91 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 2),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_3_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT101 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 3),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_4_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT111 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 4),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_5_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT121 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 5),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_6_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT131 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 6),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_7_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT141 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 7),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_8_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT151 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 8),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_9_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT161 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(0, 9),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
I3 => layer_map_shift_map_0_shifter_map_shifter_temp_reg_10_Q,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT18 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 0),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_1_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT21 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 10),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_11_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT31 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 11),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_12_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT41 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 12),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_13_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT51 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 13),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_14_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT71 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 15),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT81 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 1),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_2_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT91 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 2),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_3_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT101 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 3),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_4_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT111 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 4),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_5_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT121 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 5),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_6_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT131 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 6),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_7_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT141 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 7),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_8_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT151 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 8),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_9_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT161 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(1, 9),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
I3 => layer_map_shift_map_1_shifter_map_shifter_temp_reg_10_Q,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT18 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 0),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_1_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_0_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT21 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 10),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_11_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_10_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT31 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 11),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_12_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_11_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT41 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 12),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_13_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_12_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT51 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 13),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_14_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_13_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT71 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 15),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_15_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT81 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 1),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_2_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_1_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT91 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 2),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_3_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_2_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT101 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 3),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_4_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_3_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT111 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 4),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_5_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_4_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT121 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 5),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_6_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_5_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT131 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 6),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_7_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_6_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT141 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 7),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_8_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_7_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT151 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 8),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_9_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_8_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT161 : LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => layer_map_weighted_sum(2, 9),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
I3 => layer_map_shift_map_2_shifter_map_shifter_temp_reg_10_Q,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_9_Q
);
layer_map_shift_map_0_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT61 : LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => layer_map_weighted_sum(0, 14),
I1 => layer_map_shift_map_0_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_0_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_446,
O => layer_map_shift_map_0_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q
);
layer_map_shift_map_1_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT61 : LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => layer_map_weighted_sum(1, 14),
I1 => layer_map_shift_map_1_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_1_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_640,
O => layer_map_shift_map_1_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q
);
layer_map_shift_map_2_shifter_map_Mmux_shifter_temp_reg_15_input_15_mux_4_OUT61 : LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => layer_map_weighted_sum(2, 14),
I1 => layer_map_shift_map_2_shifter_map_GND_14_o_shifter_shift_counter_31_equal_1_o,
I2 => layer_map_shift_map_2_shifter_map_Mcompar_shifter_shift_counter_31_GND_14_o_LessThan_2_o_cy_6_Q_833,
O => layer_map_shift_map_2_shifter_map_shifter_temp_reg_15_input_15_mux_4_OUT_14_Q
);
layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv1 : LUT6
generic map(
INIT => X"FFFFFFFF7FF7EFFE"
)
port map (
I0 => layer_map_activation_hid_count_map_count(1),
I1 => layer_map_activation_hid_count_map_count(0),
I2 => \Q_n0319_3)\,
I3 => layer_map_activation_hid_count_map_count(2),
I4 => \Q_n0319_1)\,
I5 => N01,
O => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o_inv
);
layer_map_ce1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => curr_state_FSM_FFd3_266,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd1_150,
O => layer_map_ce
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT11 : LUT4
generic map(
INIT => X"0010"
)
port map (
I0 => addr_weight_out(0),
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd2_267,
I3 => curr_state_FSM_FFd3_266,
O => GND_7_o_GND_7_o_mux_14_OUT(0)
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT31 : LUT6
generic map(
INIT => X"0010100010001000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => addr_weight_out(2),
I4 => addr_weight_out(0),
I5 => addr_weight_out(1),
O => GND_7_o_GND_7_o_mux_14_OUT(2)
);
Mmux_GND_7_o_GND_7_o_mux_14_OUT21 : LUT5
generic map(
INIT => X"00101000"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => addr_weight_out(0),
I4 => addr_weight_out(1),
O => GND_7_o_GND_7_o_mux_14_OUT(1)
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT321 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_9_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_9_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT311 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_8_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_8_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT301 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_7_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_7_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT291 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_6_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_6_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT281 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_5_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_5_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT271 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_4_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_4_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT261 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_3_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_3_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT231 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_2_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_2_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT121 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_1_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_1_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT11 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_0_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_0_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT21 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_10_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_10_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT31 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_11_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_11_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT41 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_12_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_12_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT51 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_13_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_13_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT61 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_14_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_14_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT71 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_15_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_15_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT81 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_16_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_16_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT91 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_17_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_17_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT101 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_18_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_18_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT111 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_19_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_19_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT131 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_20_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_20_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT251 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_31_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_31_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT241 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_30_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_30_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT221 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_29_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_29_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT211 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_28_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_28_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT201 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_27_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_27_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT191 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_26_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_26_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT181 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_25_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_25_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT171 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_24_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_24_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT161 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_23_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_23_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT151 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_22_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_22_Q
);
Mmux_GND_7_o_transition_num_31_mux_7_OUT141 : LUT4
generic map(
INIT => X"AA02"
)
port map (
I0 => transition_num_31_GND_7_o_add_6_OUT_21_Q,
I1 => transition_num(30),
I2 => Mcompar_GND_7_o_transition_num_31_LessThan_6_o_cy_5_Q_323,
I3 => transition_num(31),
O => GND_7_o_transition_num_31_mux_7_OUT_21_Q
);
curr_state_FSM_FFd3_In1 : LUT4
generic map(
INIT => X"7D75"
)
port map (
I0 => curr_state_FSM_FFd2_267,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
I3 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
O => curr_state_FSM_FFd3_In
);
layer_map_shift_map_0_shifter_map_enable_inv1 : LUT4
generic map(
INIT => X"F137"
)
port map (
I0 => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o,
I1 => curr_state_FSM_FFd2_267,
I2 => curr_state_FSM_FFd1_150,
I3 => curr_state_FSM_FFd3_266,
O => layer_map_shift_map_0_shifter_map_enable_inv
);
curr_state_FSM_FFd2_In1 : LUT5
generic map(
INIT => X"B2BEA2AE"
)
port map (
I0 => curr_state_FSM_FFd2_267,
I1 => curr_state_FSM_FFd1_150,
I2 => curr_state_FSM_FFd3_266,
I3 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
I4 => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o,
O => curr_state_FSM_FFd2_In
);
curr_state_FSM_FFd1_In1 : LUT5
generic map(
INIT => X"7A6A3A2A"
)
port map (
I0 => curr_state_FSM_FFd1_150,
I1 => curr_state_FSM_FFd3_266,
I2 => curr_state_FSM_FFd2_267,
I3 => layer_map_activation_hid_count_map_count_7_num_neurons_7_equal_1_o,
I4 => layer_map_shift_map_0_shifter_map_shift_over_flag_34,
O => curr_state_FSM_FFd1_In
);
clk_BUFGP : BUFGP
port map (
I => clk,
O => clk_BUFGP_0
);
Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_INV_0 : INV
port map (
I => transition_num(0),
O => Madd_transition_num_31_GND_7_o_add_6_OUT_lut_0_Q
);
layer_map_activation_hid_count_map_Mcount_count_lut_0_INV_0 : INV
port map (
I => layer_map_activation_hid_count_map_count(0),
O => layer_map_activation_hid_count_map_Mcount_count_lut(0)
);
layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_INV_0 : INV
port map (
I => layer_map_shift_map_0_shifter_map_shifter_shift_counter_0_Q,
O => layer_map_shift_map_0_shifter_map_Mcount_shifter_shift_counter_lut_0_Q
);
layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_INV_0 : INV
port map (
I => layer_map_shift_map_1_shifter_map_shifter_shift_counter_0_Q,
O => layer_map_shift_map_1_shifter_map_Mcount_shifter_shift_counter_lut_0_Q
);
layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_INV_0 : INV
port map (
I => layer_map_shift_map_2_shifter_map_shifter_shift_counter_0_Q,
O => layer_map_shift_map_2_shifter_map_Mcount_shifter_shift_counter_lut_0_Q
);
test_image_map : test_image
port map (
clka => clk_BUFGP_0,
wea(0) => dina_image(0),
addra(2) => addra_image(2),
addra(1) => addra_image(1),
addra(0) => addra_image(0),
dina(7) => dina_image(0),
dina(6) => dina_image(0),
dina(5) => dina_image(0),
dina(4) => dina_image(0),
dina(3) => dina_image(0),
dina(2) => dina_image(0),
dina(1) => dina_image(0),
dina(0) => dina_image(0),
douta(7) => image(7),
douta(6) => image(6),
douta(5) => image(5),
douta(4) => image(4),
douta(3) => image(3),
douta(2) => image(2),
douta(1) => image(1),
douta(0) => image(0)
);
weight_hid_map : weight_hid
port map (
clka => clk_BUFGP_0,
wea(0) => dina_image(0),
addra(2) => addra_image(2),
addra(1) => addra_image(1),
addra(0) => addra_image(0),
dina(23) => dina_image(0),
dina(22) => dina_image(0),
dina(21) => dina_image(0),
dina(20) => dina_image(0),
dina(19) => dina_image(0),
dina(18) => dina_image(0),
dina(17) => dina_image(0),
dina(16) => dina_image(0),
dina(15) => dina_image(0),
dina(14) => dina_image(0),
dina(13) => dina_image(0),
dina(12) => dina_image(0),
dina(11) => dina_image(0),
dina(10) => dina_image(0),
dina(9) => dina_image(0),
dina(8) => dina_image(0),
dina(7) => dina_image(0),
dina(6) => dina_image(0),
dina(5) => dina_image(0),
dina(4) => dina_image(0),
dina(3) => dina_image(0),
dina(2) => dina_image(0),
dina(1) => dina_image(0),
dina(0) => dina_image(0),
douta(23) => out_weight_hid(23),
douta(22) => out_weight_hid(22),
douta(21) => out_weight_hid(21),
douta(20) => out_weight_hid(20),
douta(19) => out_weight_hid(19),
douta(18) => out_weight_hid(18),
douta(17) => out_weight_hid(17),
douta(16) => out_weight_hid(16),
douta(15) => out_weight_hid(15),
douta(14) => out_weight_hid(14),
douta(13) => out_weight_hid(13),
douta(12) => out_weight_hid(12),
douta(11) => out_weight_hid(11),
douta(10) => out_weight_hid(10),
douta(9) => out_weight_hid(9),
douta(8) => out_weight_hid(8),
douta(7) => out_weight_hid(7),
douta(6) => out_weight_hid(6),
douta(5) => out_weight_hid(5),
douta(4) => out_weight_hid(4),
douta(3) => out_weight_hid(3),
douta(2) => out_weight_hid(2),
douta(1) => out_weight_hid(1),
douta(0) => out_weight_hid(0)
);
weight_out_map : weight_out
port map (
clka => clk_BUFGP_0,
wea(0) => dina_image(0),
addra(2) => addr_weight_out(2),
addra(1) => addr_weight_out(1),
addra(0) => addr_weight_out(0),
dina(23) => dina_image(0),
dina(22) => dina_image(0),
dina(21) => dina_image(0),
dina(20) => dina_image(0),
dina(19) => dina_image(0),
dina(18) => dina_image(0),
dina(17) => dina_image(0),
dina(16) => dina_image(0),
dina(15) => dina_image(0),
dina(14) => dina_image(0),
dina(13) => dina_image(0),
dina(12) => dina_image(0),
dina(11) => dina_image(0),
dina(10) => dina_image(0),
dina(9) => dina_image(0),
dina(8) => dina_image(0),
dina(7) => dina_image(0),
dina(6) => dina_image(0),
dina(5) => dina_image(0),
dina(4) => dina_image(0),
dina(3) => dina_image(0),
dina(2) => dina_image(0),
dina(1) => dina_image(0),
dina(0) => dina_image(0),
douta(23) => out_weight_out(23),
douta(22) => out_weight_out(22),
douta(21) => out_weight_out(21),
douta(20) => out_weight_out(20),
douta(19) => out_weight_out(19),
douta(18) => out_weight_out(18),
douta(17) => out_weight_out(17),
douta(16) => out_weight_out(16),
douta(15) => out_weight_out(15),
douta(14) => out_weight_out(14),
douta(13) => out_weight_out(13),
douta(12) => out_weight_out(12),
douta(11) => out_weight_out(11),
douta(10) => out_weight_out(10),
douta(9) => out_weight_out(9),
douta(8) => out_weight_out(8),
douta(7) => out_weight_out(7),
douta(6) => out_weight_out(6),
douta(5) => out_weight_out(5),
douta(4) => out_weight_out(4),
douta(3) => out_weight_out(3),
douta(2) => out_weight_out(2),
douta(1) => out_weight_out(1),
douta(0) => out_weight_out(0)
);
layer_map_neuron_map_2_neurons_mul_hid_map : mul_hid
port map (
clk => clk_BUFGP_0,
ce => layer_map_ce,
sclr => dina_image(0),
bypass => dina_image(0),
a(7) => input(7),
a(6) => input(6),
a(5) => input(5),
a(4) => input(4),
a(3) => input(3),
a(2) => input(2),
a(1) => input(1),
a(0) => input(0),
b(7) => weight(2, 7),
b(6) => weight(2, 6),
b(5) => weight(2, 5),
b(4) => weight(2, 4),
b(3) => weight(2, 3),
b(2) => weight(2, 2),
b(1) => weight(2, 1),
b(0) => weight(2, 0),
s(15) => layer_map_weighted_sum(2, 15),
s(14) => layer_map_weighted_sum(2, 14),
s(13) => layer_map_weighted_sum(2, 13),
s(12) => layer_map_weighted_sum(2, 12),
s(11) => layer_map_weighted_sum(2, 11),
s(10) => layer_map_weighted_sum(2, 10),
s(9) => layer_map_weighted_sum(2, 9),
s(8) => layer_map_weighted_sum(2, 8),
s(7) => layer_map_weighted_sum(2, 7),
s(6) => layer_map_weighted_sum(2, 6),
s(5) => layer_map_weighted_sum(2, 5),
s(4) => layer_map_weighted_sum(2, 4),
s(3) => layer_map_weighted_sum(2, 3),
s(2) => layer_map_weighted_sum(2, 2),
s(1) => layer_map_weighted_sum(2, 1),
s(0) => layer_map_weighted_sum(2, 0)
);
layer_map_neuron_map_1_neurons_mul_hid_map : mul_hid
port map (
clk => clk_BUFGP_0,
ce => layer_map_ce,
sclr => dina_image(0),
bypass => dina_image(0),
a(7) => input(7),
a(6) => input(6),
a(5) => input(5),
a(4) => input(4),
a(3) => input(3),
a(2) => input(2),
a(1) => input(1),
a(0) => input(0),
b(7) => weight(1, 7),
b(6) => weight(1, 6),
b(5) => weight(1, 5),
b(4) => weight(1, 4),
b(3) => weight(1, 3),
b(2) => weight(1, 2),
b(1) => weight(1, 1),
b(0) => weight(1, 0),
s(15) => layer_map_weighted_sum(1, 15),
s(14) => layer_map_weighted_sum(1, 14),
s(13) => layer_map_weighted_sum(1, 13),
s(12) => layer_map_weighted_sum(1, 12),
s(11) => layer_map_weighted_sum(1, 11),
s(10) => layer_map_weighted_sum(1, 10),
s(9) => layer_map_weighted_sum(1, 9),
s(8) => layer_map_weighted_sum(1, 8),
s(7) => layer_map_weighted_sum(1, 7),
s(6) => layer_map_weighted_sum(1, 6),
s(5) => layer_map_weighted_sum(1, 5),
s(4) => layer_map_weighted_sum(1, 4),
s(3) => layer_map_weighted_sum(1, 3),
s(2) => layer_map_weighted_sum(1, 2),
s(1) => layer_map_weighted_sum(1, 1),
s(0) => layer_map_weighted_sum(1, 0)
);
layer_map_neuron_map_0_neurons_mul_hid_map : mul_hid
port map (
clk => clk_BUFGP_0,
ce => layer_map_ce,
sclr => dina_image(0),
bypass => dina_image(0),
a(7) => input(7),
a(6) => input(6),
a(5) => input(5),
a(4) => input(4),
a(3) => input(3),
a(2) => input(2),
a(1) => input(1),
a(0) => input(0),
b(7) => weight(0, 7),
b(6) => weight(0, 6),
b(5) => weight(0, 5),
b(4) => weight(0, 4),
b(3) => weight(0, 3),
b(2) => weight(0, 2),
b(1) => weight(0, 1),
b(0) => weight(0, 0),
s(15) => layer_map_weighted_sum(0, 15),
s(14) => layer_map_weighted_sum(0, 14),
s(13) => layer_map_weighted_sum(0, 13),
s(12) => layer_map_weighted_sum(0, 12),
s(11) => layer_map_weighted_sum(0, 11),
s(10) => layer_map_weighted_sum(0, 10),
s(9) => layer_map_weighted_sum(0, 9),
s(8) => layer_map_weighted_sum(0, 8),
s(7) => layer_map_weighted_sum(0, 7),
s(6) => layer_map_weighted_sum(0, 6),
s(5) => layer_map_weighted_sum(0, 5),
s(4) => layer_map_weighted_sum(0, 4),
s(3) => layer_map_weighted_sum(0, 3),
s(2) => layer_map_weighted_sum(0, 2),
s(1) => layer_map_weighted_sum(0, 1),
s(0) => layer_map_weighted_sum(0, 0)
);
layer_map_shift_map_2_shifter_map_acticv_mul_map : acticv_mul
port map (
clk => clk_BUFGP_0,
ce => layer_map_shift_map_2_shifter_map_acticv_mul_en_948,
a(15) => layer_map_shift_map_2_shifter_map_shifted_output_temp_15_Q,
a(14) => layer_map_shift_map_2_shifter_map_shifted_output_temp_14_Q,
a(13) => layer_map_shift_map_2_shifter_map_shifted_output_temp_13_Q,
a(12) => layer_map_shift_map_2_shifter_map_shifted_output_temp_12_Q,
a(11) => layer_map_shift_map_2_shifter_map_shifted_output_temp_11_Q,
a(10) => layer_map_shift_map_2_shifter_map_shifted_output_temp_10_Q,
a(9) => layer_map_shift_map_2_shifter_map_shifted_output_temp_9_Q,
a(8) => layer_map_shift_map_2_shifter_map_shifted_output_temp_8_Q,
a(7) => layer_map_shift_map_2_shifter_map_shifted_output_temp_7_Q,
a(6) => layer_map_shift_map_2_shifter_map_shifted_output_temp_6_Q,
a(5) => layer_map_shift_map_2_shifter_map_shifted_output_temp_5_Q,
a(4) => layer_map_shift_map_2_shifter_map_shifted_output_temp_4_Q,
a(3) => layer_map_shift_map_2_shifter_map_shifted_output_temp_3_Q,
a(2) => layer_map_shift_map_2_shifter_map_shifted_output_temp_2_Q,
a(1) => layer_map_shift_map_2_shifter_map_shifted_output_temp_1_Q,
a(0) => layer_map_shift_map_2_shifter_map_shifted_output_temp_0_Q,
b(15) => layer_map_shift_map_2_shifter_map_input_temp_15_Q,
b(14) => layer_map_shift_map_2_shifter_map_input_temp_14_Q,
b(13) => layer_map_shift_map_2_shifter_map_input_temp_13_Q,
b(12) => layer_map_shift_map_2_shifter_map_input_temp_12_Q,
b(11) => layer_map_shift_map_2_shifter_map_input_temp_11_Q,
b(10) => layer_map_shift_map_2_shifter_map_input_temp_10_Q,
b(9) => layer_map_shift_map_2_shifter_map_input_temp_9_Q,
b(8) => layer_map_shift_map_2_shifter_map_input_temp_8_Q,
b(7) => layer_map_shift_map_2_shifter_map_input_temp_7_Q,
b(6) => layer_map_shift_map_2_shifter_map_input_temp_6_Q,
b(5) => layer_map_shift_map_2_shifter_map_input_temp_5_Q,
b(4) => layer_map_shift_map_2_shifter_map_input_temp_4_Q,
b(3) => layer_map_shift_map_2_shifter_map_input_temp_3_Q,
b(2) => layer_map_shift_map_2_shifter_map_input_temp_2_Q,
b(1) => layer_map_shift_map_2_shifter_map_input_temp_1_Q,
b(0) => layer_map_shift_map_2_shifter_map_input_temp_0_Q,
d(15) => dina_image(0),
d(14) => dina_image(0),
d(13) => dina_image(0),
d(12) => N0,
d(11) => dina_image(0),
d(10) => dina_image(0),
d(9) => dina_image(0),
d(8) => dina_image(0),
d(7) => dina_image(0),
d(6) => dina_image(0),
d(5) => dina_image(0),
d(4) => dina_image(0),
d(3) => dina_image(0),
d(2) => dina_image(0),
d(1) => dina_image(0),
d(0) => dina_image(0),
p(31) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_31_UNCONNECTED,
p(30) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_30_UNCONNECTED,
p(29) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_29_UNCONNECTED,
p(28) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_28_UNCONNECTED,
p(27) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_27_UNCONNECTED,
p(26) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_26_UNCONNECTED,
p(25) => output_hid(2, 7),
p(24) => output_hid(2, 6),
p(23) => output_hid(2, 5),
p(22) => output_hid(2, 4),
p(21) => output_hid(2, 3),
p(20) => output_hid(2, 2),
p(19) => output_hid(2, 1),
p(18) => output_hid(2, 0),
p(17) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_17_UNCONNECTED,
p(16) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_16_UNCONNECTED,
p(15) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_15_UNCONNECTED,
p(14) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_14_UNCONNECTED,
p(13) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_13_UNCONNECTED,
p(12) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_12_UNCONNECTED,
p(11) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_11_UNCONNECTED,
p(10) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_10_UNCONNECTED,
p(9) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_9_UNCONNECTED,
p(8) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_8_UNCONNECTED,
p(7) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_7_UNCONNECTED,
p(6) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_6_UNCONNECTED,
p(5) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_5_UNCONNECTED,
p(4) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_4_UNCONNECTED,
p(3) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_3_UNCONNECTED,
p(2) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_2_UNCONNECTED,
p(1) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_1_UNCONNECTED,
p(0) => NLW_layer_map_shift_map_2_shifter_map_acticv_mul_map_p_0_UNCONNECTED
);
layer_map_shift_map_1_shifter_map_acticv_mul_map : acticv_mul
port map (
clk => clk_BUFGP_0,
ce => layer_map_shift_map_1_shifter_map_acticv_mul_en_755,
a(15) => layer_map_shift_map_1_shifter_map_shifted_output_temp_15_Q,
a(14) => layer_map_shift_map_1_shifter_map_shifted_output_temp_14_Q,
a(13) => layer_map_shift_map_1_shifter_map_shifted_output_temp_13_Q,
a(12) => layer_map_shift_map_1_shifter_map_shifted_output_temp_12_Q,
a(11) => layer_map_shift_map_1_shifter_map_shifted_output_temp_11_Q,
a(10) => layer_map_shift_map_1_shifter_map_shifted_output_temp_10_Q,
a(9) => layer_map_shift_map_1_shifter_map_shifted_output_temp_9_Q,
a(8) => layer_map_shift_map_1_shifter_map_shifted_output_temp_8_Q,
a(7) => layer_map_shift_map_1_shifter_map_shifted_output_temp_7_Q,
a(6) => layer_map_shift_map_1_shifter_map_shifted_output_temp_6_Q,
a(5) => layer_map_shift_map_1_shifter_map_shifted_output_temp_5_Q,
a(4) => layer_map_shift_map_1_shifter_map_shifted_output_temp_4_Q,
a(3) => layer_map_shift_map_1_shifter_map_shifted_output_temp_3_Q,
a(2) => layer_map_shift_map_1_shifter_map_shifted_output_temp_2_Q,
a(1) => layer_map_shift_map_1_shifter_map_shifted_output_temp_1_Q,
a(0) => layer_map_shift_map_1_shifter_map_shifted_output_temp_0_Q,
b(15) => layer_map_shift_map_1_shifter_map_input_temp_15_Q,
b(14) => layer_map_shift_map_1_shifter_map_input_temp_14_Q,
b(13) => layer_map_shift_map_1_shifter_map_input_temp_13_Q,
b(12) => layer_map_shift_map_1_shifter_map_input_temp_12_Q,
b(11) => layer_map_shift_map_1_shifter_map_input_temp_11_Q,
b(10) => layer_map_shift_map_1_shifter_map_input_temp_10_Q,
b(9) => layer_map_shift_map_1_shifter_map_input_temp_9_Q,
b(8) => layer_map_shift_map_1_shifter_map_input_temp_8_Q,
b(7) => layer_map_shift_map_1_shifter_map_input_temp_7_Q,
b(6) => layer_map_shift_map_1_shifter_map_input_temp_6_Q,
b(5) => layer_map_shift_map_1_shifter_map_input_temp_5_Q,
b(4) => layer_map_shift_map_1_shifter_map_input_temp_4_Q,
b(3) => layer_map_shift_map_1_shifter_map_input_temp_3_Q,
b(2) => layer_map_shift_map_1_shifter_map_input_temp_2_Q,
b(1) => layer_map_shift_map_1_shifter_map_input_temp_1_Q,
b(0) => layer_map_shift_map_1_shifter_map_input_temp_0_Q,
d(15) => dina_image(0),
d(14) => dina_image(0),
d(13) => dina_image(0),
d(12) => N0,
d(11) => dina_image(0),
d(10) => dina_image(0),
d(9) => dina_image(0),
d(8) => dina_image(0),
d(7) => dina_image(0),
d(6) => dina_image(0),
d(5) => dina_image(0),
d(4) => dina_image(0),
d(3) => dina_image(0),
d(2) => dina_image(0),
d(1) => dina_image(0),
d(0) => dina_image(0),
p(31) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_31_UNCONNECTED,
p(30) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_30_UNCONNECTED,
p(29) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_29_UNCONNECTED,
p(28) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_28_UNCONNECTED,
p(27) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_27_UNCONNECTED,
p(26) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_26_UNCONNECTED,
p(25) => output_hid(1, 7),
p(24) => output_hid(1, 6),
p(23) => output_hid(1, 5),
p(22) => output_hid(1, 4),
p(21) => output_hid(1, 3),
p(20) => output_hid(1, 2),
p(19) => output_hid(1, 1),
p(18) => output_hid(1, 0),
p(17) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_17_UNCONNECTED,
p(16) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_16_UNCONNECTED,
p(15) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_15_UNCONNECTED,
p(14) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_14_UNCONNECTED,
p(13) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_13_UNCONNECTED,
p(12) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_12_UNCONNECTED,
p(11) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_11_UNCONNECTED,
p(10) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_10_UNCONNECTED,
p(9) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_9_UNCONNECTED,
p(8) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_8_UNCONNECTED,
p(7) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_7_UNCONNECTED,
p(6) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_6_UNCONNECTED,
p(5) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_5_UNCONNECTED,
p(4) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_4_UNCONNECTED,
p(3) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_3_UNCONNECTED,
p(2) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_2_UNCONNECTED,
p(1) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_1_UNCONNECTED,
p(0) => NLW_layer_map_shift_map_1_shifter_map_acticv_mul_map_p_0_UNCONNECTED
);
layer_map_shift_map_0_shifter_map_acticv_mul_map : acticv_mul
port map (
clk => clk_BUFGP_0,
ce => layer_map_shift_map_0_shifter_map_acticv_mul_en_562,
a(15) => layer_map_shift_map_0_shifter_map_shifted_output_temp_15_Q,
a(14) => layer_map_shift_map_0_shifter_map_shifted_output_temp_14_Q,
a(13) => layer_map_shift_map_0_shifter_map_shifted_output_temp_13_Q,
a(12) => layer_map_shift_map_0_shifter_map_shifted_output_temp_12_Q,
a(11) => layer_map_shift_map_0_shifter_map_shifted_output_temp_11_Q,
a(10) => layer_map_shift_map_0_shifter_map_shifted_output_temp_10_Q,
a(9) => layer_map_shift_map_0_shifter_map_shifted_output_temp_9_Q,
a(8) => layer_map_shift_map_0_shifter_map_shifted_output_temp_8_Q,
a(7) => layer_map_shift_map_0_shifter_map_shifted_output_temp_7_Q,
a(6) => layer_map_shift_map_0_shifter_map_shifted_output_temp_6_Q,
a(5) => layer_map_shift_map_0_shifter_map_shifted_output_temp_5_Q,
a(4) => layer_map_shift_map_0_shifter_map_shifted_output_temp_4_Q,
a(3) => layer_map_shift_map_0_shifter_map_shifted_output_temp_3_Q,
a(2) => layer_map_shift_map_0_shifter_map_shifted_output_temp_2_Q,
a(1) => layer_map_shift_map_0_shifter_map_shifted_output_temp_1_Q,
a(0) => layer_map_shift_map_0_shifter_map_shifted_output_temp_0_Q,
b(15) => layer_map_shift_map_0_shifter_map_input_temp_15_Q,
b(14) => layer_map_shift_map_0_shifter_map_input_temp_14_Q,
b(13) => layer_map_shift_map_0_shifter_map_input_temp_13_Q,
b(12) => layer_map_shift_map_0_shifter_map_input_temp_12_Q,
b(11) => layer_map_shift_map_0_shifter_map_input_temp_11_Q,
b(10) => layer_map_shift_map_0_shifter_map_input_temp_10_Q,
b(9) => layer_map_shift_map_0_shifter_map_input_temp_9_Q,
b(8) => layer_map_shift_map_0_shifter_map_input_temp_8_Q,
b(7) => layer_map_shift_map_0_shifter_map_input_temp_7_Q,
b(6) => layer_map_shift_map_0_shifter_map_input_temp_6_Q,
b(5) => layer_map_shift_map_0_shifter_map_input_temp_5_Q,
b(4) => layer_map_shift_map_0_shifter_map_input_temp_4_Q,
b(3) => layer_map_shift_map_0_shifter_map_input_temp_3_Q,
b(2) => layer_map_shift_map_0_shifter_map_input_temp_2_Q,
b(1) => layer_map_shift_map_0_shifter_map_input_temp_1_Q,
b(0) => layer_map_shift_map_0_shifter_map_input_temp_0_Q,
d(15) => dina_image(0),
d(14) => dina_image(0),
d(13) => dina_image(0),
d(12) => N0,
d(11) => dina_image(0),
d(10) => dina_image(0),
d(9) => dina_image(0),
d(8) => dina_image(0),
d(7) => dina_image(0),
d(6) => dina_image(0),
d(5) => dina_image(0),
d(4) => dina_image(0),
d(3) => dina_image(0),
d(2) => dina_image(0),
d(1) => dina_image(0),
d(0) => dina_image(0),
p(31) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_31_UNCONNECTED,
p(30) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_30_UNCONNECTED,
p(29) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_29_UNCONNECTED,
p(28) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_28_UNCONNECTED,
p(27) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_27_UNCONNECTED,
p(26) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_26_UNCONNECTED,
p(25) => output_hid(0, 7),
p(24) => output_hid(0, 6),
p(23) => output_hid(0, 5),
p(22) => output_hid(0, 4),
p(21) => output_hid(0, 3),
p(20) => output_hid(0, 2),
p(19) => output_hid(0, 1),
p(18) => output_hid(0, 0),
p(17) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_17_UNCONNECTED,
p(16) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_16_UNCONNECTED,
p(15) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_15_UNCONNECTED,
p(14) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_14_UNCONNECTED,
p(13) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_13_UNCONNECTED,
p(12) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_12_UNCONNECTED,
p(11) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_11_UNCONNECTED,
p(10) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_10_UNCONNECTED,
p(9) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_9_UNCONNECTED,
p(8) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_8_UNCONNECTED,
p(7) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_7_UNCONNECTED,
p(6) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_6_UNCONNECTED,
p(5) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_5_UNCONNECTED,
p(4) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_4_UNCONNECTED,
p(3) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_3_UNCONNECTED,
p(2) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_2_UNCONNECTED,
p(1) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_1_UNCONNECTED,
p(0) => NLW_layer_map_shift_map_0_shifter_map_acticv_mul_map_p_0_UNCONNECTED
);
end Structure;
-- synthesis translate_on
| bsd-2-clause | c264cd63409017dd686b45d90bd3346c | 0.646291 | 2.615645 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_prod.vhd | 1 | 10,695 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_dp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_dp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x1k_dp_prod;
ARCHITECTURE xilinx OF ram_16x1k_dp_prod IS
COMPONENT ram_16x1k_dp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x1k_dp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| bsd-3-clause | 727fd4fe1a8ab9604b3af82caa87ba40 | 0.48892 | 3.80605 | false | false | false | false |
olgirard/openmsp430 | core/synthesis/xilinx/src/coregen/spartan3adsp_pmem.vhd | 1 | 5,206 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file spartan3adsp_pmem.vhd when simulating
-- the core, spartan3adsp_pmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY spartan3adsp_pmem IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END spartan3adsp_pmem;
ARCHITECTURE spartan3adsp_pmem_a OF spartan3adsp_pmem IS
-- synthesis translate_off
component wrapped_spartan3adsp_pmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_spartan3adsp_pmem use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3adsp",
c_write_depth_b => 4096,
c_write_depth_a => 4096,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 12,
c_addrb_width => 12,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 4096,
c_read_depth_a => 4096,
c_byte_size => 8,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 2,
c_has_enb => 0,
c_web_width => 2,
c_has_ena => 1,
c_use_byte_web => 1,
c_use_byte_wea => 1,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_spartan3adsp_pmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END spartan3adsp_pmem_a;
| bsd-3-clause | 0006b04e169b327c275c60a027fefe95 | 0.564157 | 3.694819 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/tx_Transact.vhd | 1 | 58,569 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tx_Transact is
port (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction
trn_tsof_n : OUT std_logic;
trn_teof_n : OUT std_logic;
trn_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_trem_n : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_terrfwd_n : OUT std_logic;
trn_tsrc_rdy_n : OUT std_logic;
trn_tdst_rdy_n : IN std_logic;
trn_tsrc_dsc_n : OUT std_logic;
trn_tdst_dsc_n : IN std_logic;
trn_tbuf_av : IN std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : OUT std_logic;
us_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Event Buffer FIFO read port
eb_FIFO_re : OUT std_logic;
eb_FIFO_empty : IN std_logic;
eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Read interface for Tx port
Regs_RdAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Irpt Channel
Irpt_Req : IN std_logic;
Irpt_RE : OUT std_logic;
Irpt_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- PIO MRd Channel
pioCplD_Req : IN std_logic;
pioCplD_RE : OUT std_logic;
pioCplD_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
pio_FC_stop : OUT std_logic;
-- downstream MRd Channel
dsMRd_Req : IN std_logic;
dsMRd_RE : OUT std_logic;
dsMRd_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- upstream MWr/MRd Channel
usTlp_Req : IN std_logic;
usTlp_RE : OUT std_logic;
usTlp_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : OUT std_logic;
us_Last_sof : OUT std_logic;
us_Last_eof : OUT std_logic;
-- Message routing method
Msg_Routing : IN std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- DDR read port
DDR_rdc_sof : OUT std_logic;
DDR_rdc_eof : OUT std_logic;
DDR_rdc_v : OUT std_logic;
DDR_rdc_FA : OUT std_logic;
DDR_rdc_Shift : OUT std_logic;
DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : OUT std_logic;
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR_rdD_sof : IN std_logic;
-- DDR_rdD_eof : IN std_logic;
-- DDR_rdDout_V : IN std_logic;
-- DDR_rdDout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut : OUT std_logic;
Tx_eb_TimeOut : OUT std_logic;
Format_Shower : OUT std_logic;
mbuf_UserFull : IN std_logic;
Tx_Reset : IN std_logic;
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end tx_Transact;
architecture Behavioral of tx_Transact is
type TxTrnStates is ( St_TxIdle -- Idle
, St_d_CmdReq -- Issue the read command to MemReader
, St_d_CmdAck -- Wait for the read command ACK from MemReader
, St_d_Header0 -- 1st Header for TLP with payload
, St_d_Header2 -- 2nd Header for TLP with payload
-- , St_d_HeaderPlus -- Extra Header for TLP4 with payload
, St_d_1st_Data -- Last Header for TLP3/4 with payload
, St_d_Payload -- Data for TLP with payload
, St_d_Payload_used -- Data flow from memory buffer discontinued
, St_d_Tail -- Last data for TLP with payload
, St_d_Tail_chk -- Last data extended for TLP with payload
, St_nd_Prepare -- Prepare for 1st Header of TLP without payload
-- , St_nd_Header1 -- 1st Header for TLP without payload
, St_nd_Header2 -- 2nd Header for TLP without payload
-- , St_nd_HeaderPlus -- Extra Header for TLP4 without payload
, St_nd_HeaderLast -- Tail processing for the last dword of TLP w/o payload
, St_nd_Arbitration -- One extra cycle for arbitration
);
-- State variables
signal TxTrn_State : TxTrnStates;
-- Signals with the arbitrator
signal take_an_Arbitration : std_logic;
signal Req_Bundle : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Read_a_Buffer : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Ack_Indice : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Tx_Indicator : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal b1_Tx_Indicator : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal vec_ChQout_Valid : std_logic_vector (C_CHANNEL_NUMBER-1 downto 0);
signal Tx_Busy : std_logic;
-- Channel buffer output token bits
signal usTLP_is_MWr : std_logic;
signal TLP_is_CplD : std_logic;
-- Bit information, telling whether the outgoing TLP has payload
signal ChBuf_has_Payload : std_logic;
signal ChBuf_No_Payload : std_logic;
-- Channel buffers output OR'ed and registered
signal Trn_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal Trn_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Addresses from different channel buffer
signal mAddr_pioCplD : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
signal mAddr_usTlp : std_logic_vector(C_PRAM_AWIDTH-1+2 downto 0);
signal DDRAddr_usTlp : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
signal Regs_Addr_pioCplD : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal DDRAddr_pioCplD : std_logic_vector(C_DDR_IAWIDTH-1 downto 0);
-- BAR number
signal BAR_pioCplD : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
signal BAR_usTlp : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Misc. info.
signal AInc_usTlp : std_logic;
signal pioCplD_is_0Leng : std_logic;
-- Delay for requests from Channel Buffers
signal Irpt_Req_r1 : std_logic;
signal pioCplD_Req_r1 : std_logic;
signal dsMRd_Req_r1 : std_logic;
signal usTlp_Req_r1 : std_logic;
-- Registered channel buffer outputs
signal Irpt_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal dsMRd_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_to_TLP : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Req_Min_Leng : std_logic;
signal pioCplD_Req_2DW_Leng : std_logic;
signal usTlp_Req_Min_Leng : std_logic;
signal usTlp_Req_2DW_Leng : std_logic;
-- Channel buffer read enables
signal Irpt_RE_i : std_logic;
signal pioCplD_RE_i : std_logic;
signal dsMRd_RE_i : std_logic;
signal usTlp_RE_i : std_logic;
-- Flow controls
signal pio_FC_stop_i : std_logic;
signal us_FC_stop_i : std_logic;
-- Local reset for tx
signal trn_tx_Reset_n : std_logic;
-- Alias for transaction interface signals
signal trn_td_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_tsof_n_i : std_logic;
signal trn_trem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_teof_n_i : std_logic;
signal Format_Shower_i : std_logic;
signal trn_tsrc_rdy_n_i : std_logic;
signal trn_tsrc_dsc_n_i : std_logic;
signal trn_terrfwd_n_i : std_logic;
signal trn_tdst_rdy_n_i : std_logic;
signal trn_tdst_dsc_n_i : std_logic;
signal trn_tbuf_av_i : std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Upstream DMA transferred bytes count up
signal us_DMA_Bytes_Add_i : std_logic;
signal us_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
--------------------- Memory Reader -----------------------------
---
--- Memory reader is the interface to access all sorts of memories
--- BRAM, FIFO, Registers, as well as possible DDR SDRAM
---
-------------------------------------------------------------------
COMPONENT
tx_Mem_Reader
PORT(
DDR_rdc_sof : OUT std_logic;
DDR_rdc_eof : OUT std_logic;
DDR_rdc_v : OUT std_logic;
DDR_rdc_FA : OUT std_logic;
DDR_rdc_Shift : OUT std_logic;
DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : IN std_logic;
-- DDR_rdD_sof : IN std_logic;
-- DDR_rdD_eof : IN std_logic;
-- DDR_rdDout_V : IN std_logic;
-- DDR_rdDout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_FIFO_RdEn : OUT std_logic;
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_re : OUT std_logic;
eb_FIFO_empty : IN std_logic;
eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One : IN std_logic;
RdNumber_eq_Two : IN std_logic;
StartAddr : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord : IN std_logic;
FixedAddr : IN std_logic;
is_CplD : IN std_logic;
BAR_value : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req : IN std_logic;
RdCmd_Ack : OUT std_logic;
mbuf_WE : OUT std_logic;
mbuf_Din : OUT std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
mbuf_Full : IN std_logic;
mbuf_aFull : IN std_logic;
mbuf_UserFull : IN std_logic;
Tx_TimeOut : OUT std_logic;
Tx_eb_TimeOut : OUT std_logic;
mReader_Rst_n : IN std_logic;
trn_clk : IN std_logic
);
END COMPONENT;
signal RdNumber : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal RdNumber_eq_One : std_logic;
signal RdNumber_eq_Two : std_logic;
signal StartAddr : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Shift_1st_QWord : std_logic;
signal FixedAddr : std_logic;
signal is_CplD : std_logic;
signal BAR_value : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
signal RdCmd_Req : std_logic;
signal RdCmd_Ack : std_logic;
--------------------- Memory Buffer -----------------------------
---
--- A unified memory buffer holding the payload for the next tx TLP
--- 34 bits wide, wherein 2 additional framing bits
--- temporarily 64 data depth, possibly deepened.
---
-------------------------------------------------------------------
component
k7_mBuf_128x72
port (
clk : IN std_logic;
rst : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
empty : OUT std_logic
);
end component;
signal mbuf_reset : std_logic;
signal mbuf_WE : std_logic;
signal mbuf_Din : std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_Full : std_logic;
signal mbuf_aFull : std_logic;
signal mbuf_RE : std_logic;
signal mbuf_Qout : std_logic_VECTOR(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_Empty : std_logic;
-- Calculated infomation
signal mbuf_RE_ok : std_logic;
signal mbuf_Qvalid : std_logic;
--------------------- Output arbitration ------------------------
---
--- For sake of fairness, the priorities are cycled every time
--- a service is done, after which the priority of the request
--- just serviced is set to the lowest and other lower priorities
--- increased and higher stay.
---
-------------------------------------------------------------------
COMPONENT
Tx_Output_Arbitor
PORT(
rst_n : IN std_logic;
clk : IN std_logic;
arbtake : IN std_logic;
Req : IN std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
bufread : OUT std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
Ack : OUT std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0)
);
END COMPONENT;
begin
-- Connect outputs
trn_td <= trn_td_i;
trn_tsof_n <= trn_tsof_n_i;
trn_trem_n <= trn_trem_n_i;
trn_teof_n <= trn_teof_n_i;
trn_tsrc_rdy_n <= trn_tsrc_rdy_n_i;
trn_tsrc_dsc_n <= trn_tsrc_dsc_n_i;
trn_terrfwd_n <= trn_terrfwd_n_i;
Format_Shower <= Format_Shower_i;
us_Last_sof <= usTLP_is_MWr and not trn_tsof_n_i;
us_Last_eof <= usTLP_is_MWr and not trn_teof_n_i;
-- Connect inputs
trn_tdst_rdy_n_i <= trn_tdst_rdy_n;
trn_tdst_dsc_n_i <= trn_tdst_dsc_n;
trn_tbuf_av_i <= trn_tbuf_av;
-- Always deasserted
trn_tsrc_dsc_n_i <= '1';
trn_terrfwd_n_i <= '1';
-- trn_trem_n_i <= (OTHERS=>'0');
-- Upstream DMA transferred bytes counting up
us_DMA_Bytes_Add <= us_DMA_Bytes_Add_i;
us_DMA_Bytes <= us_DMA_Bytes_i ;
-- Flow controls
pio_FC_stop <= pio_FC_stop_i;
us_FC_stop <= us_FC_stop_i;
---------------------------------------------------------------------------------
-- Synchronous Calculation: us_FC_stop, pio_FC_stop
--
Synch_Calc_FC_stop:
process ( trn_clk, Tx_Reset)
begin
if Tx_Reset = '1' then
us_FC_stop_i <= '1';
pio_FC_stop_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
if trn_tbuf_av_i(C_TBUF_AWIDTH-1 downto 1) /=C_ALL_ZEROS(C_TBUF_AWIDTH-1 downto 1) then
us_FC_stop_i <= '0';
pio_FC_stop_i <= '0';
else
us_FC_stop_i <= '1';
pio_FC_stop_i <= '1';
end if;
end if;
end process;
-- Channel buffer read enable
Irpt_RE <= Irpt_RE_i;
pioCplD_RE <= pioCplD_RE_i;
dsMRd_RE <= dsMRd_RE_i;
usTlp_RE <= usTlp_RE_i;
-- -----------------------------------
-- Synchronized Local reset
--
Syn_Local_Reset:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
trn_tx_Reset_n <= '0';
elsif trn_clk'event and trn_clk = '1' then
trn_tx_Reset_n <= trn_tdst_dsc_n_i and not Tx_Reset;
end if;
end process;
-- -----------------------------------
-- Format detector
--
Syn_Format_Shower:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
Format_Shower_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Format_Shower_i = '0' then
if trn_tsof_n_i='0' and trn_tsrc_rdy_n_i='0' and trn_tdst_rdy_n_i='0' then
Format_Shower_i <= '1';
else
Format_Shower_i <= '0';
end if;
else
if trn_teof_n_i='0' and trn_tsrc_rdy_n_i='0' and trn_tdst_rdy_n_i='0' then
Format_Shower_i <= '0';
else
Format_Shower_i <= '1';
end if;
end if;
end if;
end process;
------------------------------------------------------------
--- Memory reader
------------------------------------------------------------
ABB_Tx_MReader:
tx_Mem_Reader
PORT MAP(
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_FA => DDR_rdc_FA , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR_rdD_sof => DDR_rdD_sof , -- IN std_logic;
-- DDR_rdD_eof => DDR_rdD_eof , -- IN std_logic;
-- DDR_rdDout_V => DDR_rdDout_V , -- IN std_logic;
-- DDR_rdDout => DDR_rdDout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_re => eb_FIFO_re , -- OUT std_logic;
eb_FIFO_empty => eb_FIFO_empty , -- IN std_logic;
eb_FIFO_qout => eb_FIFO_qout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr => Regs_RdAddr , -- OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout => Regs_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber => RdNumber , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
RdNumber_eq_One => RdNumber_eq_One , -- IN std_logic;
RdNumber_eq_Two => RdNumber_eq_Two , -- IN std_logic;
StartAddr => StartAddr , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord => Shift_1st_QWord , -- IN std_logic;
FixedAddr => '0', -- FixedAddr , -- IN std_logic;
is_CplD => is_CplD , -- IN std_logic;
BAR_value => BAR_value , -- IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req => RdCmd_Req , -- IN std_logic;
RdCmd_Ack => RdCmd_Ack , -- OUT std_logic;
mbuf_WE => mbuf_WE , -- OUT std_logic;
mbuf_Din => mbuf_Din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
mbuf_Full => mbuf_Full , -- IN std_logic;
mbuf_aFull => mbuf_aFull , -- IN std_logic;
mbuf_UserFull => mbuf_UserFull , -- IN std_logic;
Tx_TimeOut => Tx_TimeOut , -- OUT std_logic;
Tx_eb_TimeOut => Tx_eb_TimeOut , -- OUT std_logic;
mReader_Rst_n => trn_tx_Reset_n , -- IN std_logic;
trn_clk => trn_clk -- IN std_logic
);
------------------------------------------------------------
--- Memory buffer
------------------------------------------------------------
ABB_Tx_MBuffer:
k7_mBuf_128x72
PORT MAP(
wr_en => mbuf_WE , -- IN std_logic;
din => mbuf_Din , -- IN std_logic_VECTOR(C_DBUS_WIDTH+1 downto 0);
prog_full => mbuf_aFull , -- OUT std_logic;
full => mbuf_Full , -- OUT std_logic;
rd_en => mbuf_RE , -- IN std_logic;
dout => mbuf_Qout , -- OUT std_logic_VECTOR(C_DBUS_WIDTH+1 downto 0);
empty => mbuf_Empty , -- OUT std_logic
rst => mbuf_reset, --Tx_Reset , -- IN std_logic;
clk => trn_clk -- IN std_logic;
);
mbuf_RE <= mbuf_RE_ok and (not trn_tdst_rdy_n_i or trn_tsrc_rdy_n_i);
---------------------------------------------------------------------------------
-- Synchronous Delay: mbuf_Qout Valid
--
Synchron_Delay_mbuf_Qvalid:
process ( trn_clk, Tx_Reset)
begin
if Tx_Reset = '1' then
mbuf_Qvalid <= '0';
elsif trn_clk'event and trn_clk = '1' then
if mbuf_Qvalid='0' and mbuf_RE='1' and mbuf_Empty='0' then -- a valid data is going out
mbuf_Qvalid <= '1';
elsif mbuf_Qvalid='1' and mbuf_RE='1' and mbuf_Empty='1' then -- an invalid data is going out
mbuf_Qvalid <= '0';
else -- state stays
mbuf_Qvalid <= mbuf_Qvalid;
end if;
end if;
end process;
------------------------------------------------------------
--- Output arbitration
------------------------------------------------------------
O_Arbitration:
Tx_Output_Arbitor
PORT MAP(
rst_n => trn_tx_Reset_n,
clk => trn_clk,
arbtake => take_an_Arbitration,
Req => Req_Bundle,
bufread => Read_a_Buffer,
Ack => Ack_Indice
);
-----------------------------------------------------
-- Synchronous Delay: Channel Requests
--
Synchron_Delay_ChRequests:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Irpt_Req_r1 <= Irpt_Req;
pioCplD_Req_r1 <= pioCplD_Req;
dsMRd_Req_r1 <= dsMRd_Req;
usTlp_Req_r1 <= usTlp_Req;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: Tx_Busy
--
Synchron_Delay_Tx_Busy:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Tx_Indicator <= b1_Tx_Indicator;
Tx_Busy <= (b1_Tx_Indicator(C_CHAN_INDEX_IRPT) and vec_ChQout_Valid(C_CHAN_INDEX_IRPT) )
or (b1_Tx_Indicator(C_CHAN_INDEX_MRD) and vec_ChQout_Valid(C_CHAN_INDEX_MRD) )
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS))
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US))
;
end if;
end process;
-- ---------------------------------------------
-- Reg : Channel Buffer Qout has Payload
--
Reg_ChBuf_with_Payload:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
ChBuf_has_Payload <= (b1_Tx_Indicator(C_CHAN_INDEX_MRD) and TLP_is_CplD and vec_ChQout_Valid(C_CHAN_INDEX_MRD) )
or (b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) and usTLP_is_MWr and vec_ChQout_Valid(C_CHAN_INDEX_DMA_US))
;
end if;
end process;
-- ---------------------------------------------
-- Channel Buffer Qout has no Payload
-- (! subordinate to ChBuf_has_Payload ! )
--
ChBuf_No_Payload <= Tx_Busy;
-- Arbitrator inputs
Req_Bundle(C_CHAN_INDEX_IRPT) <= Irpt_Req_r1;
Req_Bundle(C_CHAN_INDEX_MRD) <= pioCplD_Req_r1;
Req_Bundle(C_CHAN_INDEX_DMA_DS) <= dsMRd_Req_r1;
Req_Bundle(C_CHAN_INDEX_DMA_US) <= usTlp_Req_r1;
-- Arbitrator outputs
b1_Tx_Indicator(C_CHAN_INDEX_IRPT) <= Ack_Indice(C_CHAN_INDEX_IRPT);
b1_Tx_Indicator(C_CHAN_INDEX_MRD) <= Ack_Indice(C_CHAN_INDEX_MRD);
b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS) <= Ack_Indice(C_CHAN_INDEX_DMA_DS);
b1_Tx_Indicator(C_CHAN_INDEX_DMA_US) <= Ack_Indice(C_CHAN_INDEX_DMA_US);
-- Arbitrator reads channel buffers
Irpt_RE_i <= Read_a_Buffer(C_CHAN_INDEX_IRPT);
pioCplD_RE_i <= Read_a_Buffer(C_CHAN_INDEX_MRD);
dsMRd_RE_i <= Read_a_Buffer(C_CHAN_INDEX_DMA_DS);
usTlp_RE_i <= Read_a_Buffer(C_CHAN_INDEX_DMA_US);
-- determine whether the upstream TLP is an MWr or an MRd.
usTLP_is_MWr <= usTlp_Qout (C_CHBUF_FMT_BIT_TOP);
TLP_is_CplD <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP);
-- check if the Channel buffer output is valid
vec_ChQout_Valid(C_CHAN_INDEX_IRPT) <= Irpt_Qout (C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_MRD) <= pioCplD_Qout(C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_DMA_DS) <= dsMRd_Qout (C_CHBUF_QVALID_BIT);
vec_ChQout_Valid(C_CHAN_INDEX_DMA_US) <= usTlp_Qout (C_CHBUF_QVALID_BIT);
-- -----------------------------------
-- Delay : Channel_Buffer_Qout
-- Bit-mapping is done
--
Delay_Channel_Buffer_Qout:
process ( trn_clk, trn_tx_Reset_n)
begin
if trn_tx_Reset_n = '0' then
Irpt_Qout_to_TLP <= (Others=>'0');
pioCplD_Qout_to_TLP <= (Others=>'0');
dsMRd_Qout_to_TLP <= (Others=>'0');
usTlp_Qout_to_TLP <= (Others=>'0');
pioCplD_Req_Min_Leng <= '0';
pioCplD_Req_2DW_Leng <= '0';
usTlp_Req_Min_Leng <= '0';
usTlp_Req_2DW_Leng <= '0';
Regs_Addr_pioCplD <= (Others=>'1');
mAddr_pioCplD <= (Others=>'1');
mAddr_usTlp <= (Others=>'1');
AInc_usTlp <= '1';
BAR_pioCplD <= (Others=>'1');
BAR_usTlp <= (Others=>'1');
pioCplD_is_0Leng <= '0';
elsif trn_clk'event and trn_clk = '1' then
if b1_Tx_Indicator(C_CHAN_INDEX_IRPT)='1' then
Irpt_Qout_to_TLP <= (Others=>'0'); -- must be 1st argument
-- 1st header Hi
Irpt_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= Irpt_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
-- Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_OF_MSG; --Irpt_Qout(C_CHBUF_MSGTYPE_BIT_TOP downto C_CHBUF_MSGTYPE_BIT_BOT);
Irpt_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_TOP
downto C_TLP_TYPE_BIT_BOT+1+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT)
& Msg_Routing;
Irpt_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= Irpt_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
Irpt_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= Irpt_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header Lo
Irpt_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
Irpt_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= Irpt_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
Irpt_Qout_to_TLP(C_MSG_CODE_BIT_TOP downto C_MSG_CODE_BIT_BOT) <= Irpt_Qout(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT);
-- 2nd headers all zero
-- ...
else
Irpt_Qout_to_TLP <= (Others=>'0');
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_MRD)='1' then
pioCplD_Qout_to_TLP <= (Others=>'0'); -- must be 1st argument
-- 1st header Hi
pioCplD_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= pioCplD_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_TYPE_COMPLETION; --pioCplD_Qout(C_CHBUF_TYPE_BIT_TOP downto C_CHBUF_TYPE_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= pioCplD_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= pioCplD_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
pioCplD_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header Lo
pioCplD_Qout_to_TLP(C_CPLD_CPLT_ID_BIT_TOP downto C_CPLD_CPLT_ID_BIT_BOT) <= localID;
pioCplD_Qout_to_TLP(C_CPLD_CS_BIT_TOP downto C_CPLD_CS_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT);
pioCplD_Qout_to_TLP(C_CPLD_BC_BIT_TOP downto C_CPLD_BC_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT);
-- 2nd header Hi
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_REQID_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_REQID_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT);
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_TAG_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_TAG_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT);
pioCplD_Qout_to_TLP(C_DBUS_WIDTH+C_CPLD_LA_BIT_TOP downto C_DBUS_WIDTH+C_CPLD_LA_BIT_BOT) <= pioCplD_Qout(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT);
-- no 2nd header Lo
if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
then
pioCplD_Req_Min_Leng <= '1';
else
pioCplD_Req_Min_Leng <= '0';
end if;
if pioCplD_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
then
pioCplD_Req_2DW_Leng <= '1';
else
pioCplD_Req_2DW_Leng <= '0';
end if;
-- Misc
Regs_Addr_pioCplD <= pioCplD_Qout(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
mAddr_pioCplD <= pioCplD_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- !! C_CHBUF_MA_BIT_BOT);
DDRAddr_pioCplD <= pioCplD_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
BAR_pioCplD <= pioCplD_Qout(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT);
pioCplD_is_0Leng <= pioCplD_Qout(C_CHBUF_0LENG_BIT);
else
pioCplD_Req_Min_Leng <= '0';
pioCplD_Req_2DW_Leng <= '0';
pioCplD_Qout_to_TLP <= (Others=>'0');
Regs_Addr_pioCplD <= (Others=>'1');
mAddr_pioCplD <= (Others=>'1');
DDRAddr_pioCplD <= (Others=>'1');
BAR_pioCplD <= (Others=>'1');
pioCplD_is_0Leng <= '0';
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_DMA_US)='1' then
usTlp_Qout_to_TLP <= (Others=>'0'); -- must be 1st argument
-- 1st header HI
usTlp_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= usTlp_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= usTlp_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= usTlp_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header LO
usTlp_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
usTlp_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= usTlp_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
usTlp_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT);
-- 2nd header HI (Address)
-- usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
if usTlp_Qout(C_CHBUF_FMT_BIT_BOT)='1' then -- 4DW MWr
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT+32);
else
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH+32) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
end if;
-- 2nd header LO (Address)
usTlp_Qout_to_TLP(2*C_DBUS_WIDTH-1-32 downto C_DBUS_WIDTH) <= usTlp_Qout(C_CHBUF_HA_BIT_TOP-32 downto C_CHBUF_HA_BIT_BOT);
--
if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
then
usTlp_Req_Min_Leng <= '1';
else
usTlp_Req_Min_Leng <= '0';
end if;
if usTlp_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
then
usTlp_Req_2DW_Leng <= '1';
else
usTlp_Req_2DW_Leng <= '0';
end if;
-- Misc
DDRAddr_usTlp <= usTlp_Qout(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT);
mAddr_usTlp <= usTlp_Qout(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- !! C_CHBUF_MA_BIT_BOT);
AInc_usTlp <= usTlp_Qout(C_CHBUF_AINC_BIT);
BAR_usTlp <= usTlp_Qout(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT);
else
usTlp_Req_Min_Leng <= '0';
usTlp_Req_2DW_Leng <= '0';
usTlp_Qout_to_TLP <= (Others=>'0');
DDRAddr_usTlp <= (Others=>'1');
mAddr_usTlp <= (Others=>'1');
AInc_usTlp <= '1';
BAR_usTlp <= (Others=>'1');
end if;
if b1_Tx_Indicator(C_CHAN_INDEX_DMA_DS)='1' then
dsMRd_Qout_to_TLP <= (Others=>'0'); -- must be 1st argument
-- 1st header HI
dsMRd_Qout_to_TLP(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) <= dsMRd_Qout(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) <= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT) <= dsMRd_Qout(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT) <= dsMRd_Qout(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT) <= dsMRd_Qout(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- 1st header LO
dsMRd_Qout_to_TLP(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT) <= localID;
dsMRd_Qout_to_TLP(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT) <= dsMRd_Qout(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_LAST_BE_BIT_TOP downto C_TLP_LAST_BE_BIT_BOT);
dsMRd_Qout_to_TLP(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT) <= C_ALL_ONES(C_TLP_1ST_BE_BIT_TOP downto C_TLP_1ST_BE_BIT_BOT);
-- 2nd header (Address)
dsMRd_Qout_to_TLP(2*C_DBUS_WIDTH-1 downto C_DBUS_WIDTH) <= dsMRd_Qout(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT);
else
dsMRd_Qout_to_TLP <= (Others=>'0');
end if;
end if;
end process;
-- OR-wired channel buffer outputs
Trn_Qout_wire <= Irpt_Qout_to_TLP
or pioCplD_Qout_to_TLP
or dsMRd_Qout_to_TLP
or usTlp_Qout_to_TLP
;
-- ---------------------------------------------------
-- State Machine: Tx output control
--
TxFSM_OutputControl:
process ( trn_clk, trn_tx_Reset_n)
begin
if trn_tx_Reset_n = '0' then
take_an_Arbitration <= '0';
RdNumber <= (Others=>'0');
RdNumber_eq_One <= '0';
RdNumber_eq_Two <= '0';
StartAddr <= (Others=>'0');
Shift_1st_QWord <= '0';
-- FixedAddr <= '0';
is_CplD <= '0';
BAR_value <= (Others=>'0');
RdCmd_Req <= '0';
mbuf_reset <= '1';
mbuf_RE_ok <= '0';
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= (Others=>'0');
trn_trem_n_i <= (Others=>'0');
TxTrn_State <= St_TxIdle;
Trn_Qout_reg <= (Others=>'0');
elsif trn_clk'event and trn_clk = '1' then
case TxTrn_State is
when St_TxIdle =>
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= (Others=>'0');
trn_trem_n_i <= (Others=>'0');
mbuf_RE_ok <= '0';
take_an_Arbitration <= '0';
Trn_Qout_reg <= Trn_Qout_wire;
RdNumber <= Trn_Qout_wire (C_TLP_FLD_WIDTH_OF_LENG-1+32 downto 32);
RdNumber_eq_One <= pioCplD_Req_Min_Leng or usTlp_Req_Min_Leng;
RdNumber_eq_Two <= pioCplD_Req_2DW_Leng or usTlp_Req_2DW_Leng;
-- FixedAddr <= not AInc_usTlp;
-- BAR_value <= BAR_pioCplD and BAR_usTlp;
RdCmd_Req <= ChBuf_has_Payload;
if pioCplD_is_0Leng='1' then
BAR_value <= '0' & CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1);
StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto 0) ;
Shift_1st_QWord <= '1';
is_CplD <= '0';
elsif BAR_pioCplD=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_pioCplD);
Shift_1st_QWord <= '1';
is_CplD <= '1';
elsif BAR_pioCplD=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_pioCplD);
Shift_1st_QWord <= '1';
is_CplD <= '1';
-- elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
-- BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
-- StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+4) & mAddr_usTlp & "00";
elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
Shift_1st_QWord <= not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
is_CplD <= '0';
elsif BAR_usTlp=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
BAR_value <= '0' & BAR_usTlp(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= C_ALL_ONES(C_DBUS_WIDTH-1 downto C_DDR_IAWIDTH) & DDRAddr_usTlp;
Shift_1st_QWord <= not usTlp_Qout_to_TLP(C_TLP_FMT_BIT_BOT);
is_CplD <= '0';
else
BAR_value <= '0' & BAR_pioCplD(C_ENCODE_BAR_NUMBER-2 downto 0);
StartAddr <= (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_EP_AWIDTH) & Regs_Addr_pioCplD)
-- and (C_ALL_ONES(C_DBUS_WIDTH-1 downto C_PRAM_AWIDTH+2) & mAddr_usTlp)
;
Shift_1st_QWord <= '1';
is_CplD <= '0';
end if;
if ChBuf_has_Payload = '1' then
TxTrn_State <= St_d_CmdReq;
mbuf_reset <= '0';
elsif ChBuf_No_Payload = '1' then
TxTrn_State <= St_nd_Prepare;
mbuf_reset <= '0';
else
TxTrn_State <= St_TxIdle;
mbuf_reset <= not mbuf_Empty; -- '1';
end if;
--- --- --- --- --- --- --- --- --- --- --- --- ---
--- --- --- --- --- --- --- --- --- --- --- --- ---
when St_nd_Prepare =>
trn_teof_n_i <= '1';
if trn_tdst_rdy_n_i = '0' then
TxTrn_State <= St_nd_Header2; -- St_nd_Header1
trn_tsrc_rdy_n_i <= '0';
trn_tsof_n_i <= '0';
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
else
TxTrn_State <= St_nd_Prepare;
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_td_i <= (Others=>'0');
end if;
when St_nd_Header2 =>
trn_tsrc_rdy_n_i <= '0';
if trn_tdst_rdy_n_i = '1' then
TxTrn_State <= St_nd_Header2;
take_an_Arbitration <= '0';
trn_tsof_n_i <= trn_tsof_n_i;
trn_teof_n_i <= '1';
trn_td_i <= trn_td_i; -- Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
else -- 3DW header
TxTrn_State <= St_nd_HeaderLast;
take_an_Arbitration <= '1';
trn_tsof_n_i <= '1';
trn_teof_n_i <= '0';
if Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then -- 4DW header
trn_trem_n_i <= X"00";
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
else
trn_trem_n_i <= X"0F";
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto C_DBUS_WIDTH) & X"00000000";
end if;
end if;
when St_nd_HeaderLast =>
trn_tsof_n_i <= '1';
take_an_Arbitration <= '0';
if trn_tdst_rdy_n_i = '1' then
TxTrn_State <= St_nd_HeaderLast;
trn_tsrc_rdy_n_i <= '0';
trn_teof_n_i <= '0';
trn_td_i <= trn_td_i;
trn_trem_n_i <= trn_trem_n_i;
else
TxTrn_State <= St_nd_Arbitration; -- St_TxIdle;
trn_tsrc_rdy_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= trn_td_i;
trn_trem_n_i <= trn_trem_n_i;
end if;
when St_nd_Arbitration =>
trn_tsof_n_i <= '1';
TxTrn_State <= St_TxIdle;
trn_tsrc_rdy_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= trn_td_i;
trn_trem_n_i <= (OTHERS=>'0');
--- --- --- --- --- --- --- --- --- --- --- --- ---
--- --- --- --- --- --- --- --- --- --- --- --- ---
when St_d_CmdReq =>
if RdCmd_Ack = '1' then
RdCmd_Req <= '0';
TxTrn_State <= St_d_CmdAck;
else
RdCmd_Req <= '1';
TxTrn_State <= St_d_CmdReq;
end if;
when St_d_CmdAck =>
trn_teof_n_i <= '1';
if mbuf_Empty = '0' and trn_tdst_rdy_n_i = '0' then
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_td_i <= (Others=>'0');
mbuf_RE_ok <= '1';
TxTrn_State <= St_d_Header0; -- St_d_Header1
else
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_td_i <= (Others=>'0');
mbuf_RE_ok <= '0';
TxTrn_State <= St_d_CmdAck;
end if;
when St_d_Header0 =>
if trn_tdst_rdy_n_i = '0' then
take_an_Arbitration <= '1';
trn_tsrc_rdy_n_i <= '0';
trn_tsof_n_i <= '0';
trn_teof_n_i <= '1';
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
mbuf_RE_ok <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT); -- '1'; -- 4DW
TxTrn_State <= St_d_Header2;
else
take_an_Arbitration <= '0';
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= trn_td_i;
mbuf_RE_ok <= '0';
TxTrn_State <= St_d_Header0;
end if;
when St_d_Header2 =>
trn_tsrc_rdy_n_i <= '0';
trn_trem_n_i <= (OTHERS=>'0');
take_an_Arbitration <= '0';
if trn_tdst_rdy_n_i = '1' then
TxTrn_State <= St_d_Header2;
-- trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1+32 downto 32);
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1 downto 0);
trn_tsof_n_i <= '0';
trn_teof_n_i <= '1';
mbuf_RE_ok <= not Trn_Qout_reg (C_TLP_FMT_BIT_BOT);
elsif Trn_Qout_reg (C_TLP_FMT_BIT_BOT) = '1' then -- 4DW header
TxTrn_State <= St_d_1st_Data; -- St_d_HeaderPlus;
-- trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1+96 downto 96);
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH);
trn_tsof_n_i <= '1';
trn_teof_n_i <= '1';
mbuf_RE_ok <= '1';
else -- 3DW header
-- trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH-1+64 downto 64);
trn_td_i <= Trn_Qout_reg (C_DBUS_WIDTH*2-1 downto C_DBUS_WIDTH+32)
& mbuf_Qout(C_DBUS_WIDTH-1-32 downto 0);
trn_tsof_n_i <= '1';
trn_teof_n_i <= mbuf_Qout(C_DBUS_WIDTH);
mbuf_RE_ok <= not trn_tsrc_rdy_n_i and mbuf_Qout(C_DBUS_WIDTH);
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
else
TxTrn_State <= St_d_1st_Data;
end if;
end if;
when St_d_1st_Data =>
mbuf_RE_ok <= not trn_tsrc_rdy_n_i and mbuf_Qout(C_DBUS_WIDTH);
-- trn_tsof_n_i <= '1';
take_an_Arbitration <= '0';
if trn_tdst_rdy_n_i = '1' then
TxTrn_State <= St_d_1st_Data;
trn_teof_n_i <= '1';
trn_td_i <= trn_td_i;
trn_tsrc_rdy_n_i <= '0';
elsif mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
trn_teof_n_i <= '0';
trn_trem_n_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
trn_tsrc_rdy_n_i <= not mbuf_Qvalid; -- '0';
elsif mbuf_Qvalid = '0' then
TxTrn_State <= St_d_Payload_used;
trn_teof_n_i <= '1';
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
trn_tsrc_rdy_n_i <= '1';
else
TxTrn_State <= St_d_Payload;
trn_teof_n_i <= '1';
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
trn_tsrc_rdy_n_i <= '0';
end if;
when St_d_Payload =>
mbuf_RE_ok <= '1';
-- trn_tsof_n_i <= '1';
take_an_Arbitration <= '0';
if trn_tdst_rdy_n_i='1' then
trn_td_i <= trn_td_i;
trn_teof_n_i <= trn_teof_n_i;
trn_trem_n_i <= trn_trem_n_i;
trn_tsrc_rdy_n_i <= '0';
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail;
elsif mbuf_Qvalid='1' then
TxTrn_State <= St_d_Payload;
else
TxTrn_State <= St_d_Payload_used;
end if;
else
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
trn_teof_n_i <= mbuf_Qout(C_DBUS_WIDTH);
trn_tsrc_rdy_n_i <= mbuf_Qout(C_DBUS_WIDTH) and not mbuf_Qvalid;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
trn_trem_n_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
elsif mbuf_Qvalid='1' then
trn_trem_n_i <= (OTHERS=>'0');
TxTrn_State <= St_d_Payload;
else
trn_trem_n_i <= (OTHERS=>'0');
TxTrn_State <= St_d_Payload_used;
end if;
end if;
when St_d_Payload_used =>
mbuf_RE_ok <= '1';
take_an_Arbitration <= '0';
-- trn_tsof_n_i <= '1';
if trn_tsrc_rdy_n_i='0' then
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
trn_tsrc_rdy_n_i <= not mbuf_Qvalid and not trn_tdst_rdy_n_i;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
trn_teof_n_i <= '0';
trn_trem_n_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
else
trn_teof_n_i <= '1';
trn_trem_n_i <= (OTHERS=>'0');
end if;
if mbuf_Qvalid='1' then
TxTrn_State <= St_d_Payload;
else
TxTrn_State <= St_d_Payload_used;
end if;
elsif mbuf_Qvalid='1' then
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
trn_tsrc_rdy_n_i <= '0';
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
trn_teof_n_i <= '0';
trn_trem_n_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
else
trn_teof_n_i <= '1';
trn_trem_n_i <= (OTHERS=>'0');
end if;
if mbuf_Qout(C_DBUS_WIDTH) = '0' then
TxTrn_State <= St_d_Tail_chk;
else
TxTrn_State <= St_d_Payload;
end if;
else
TxTrn_State <= St_d_Payload_used;
trn_td_i <= trn_td_i;
trn_teof_n_i <= trn_teof_n_i;
trn_trem_n_i <= trn_trem_n_i;
trn_tsrc_rdy_n_i <= '1';
end if;
when St_d_Tail =>
take_an_Arbitration <= '0';
mbuf_RE_ok <= '0';
-- trn_tsof_n_i <= '1';
trn_tsrc_rdy_n_i <= '0';
if trn_tdst_rdy_n_i = '1' then
TxTrn_State <= St_d_Tail;
trn_teof_n_i <= trn_teof_n_i;
trn_trem_n_i <= trn_trem_n_i;
trn_td_i <= trn_td_i;
else
TxTrn_State <= St_d_Tail_chk;
trn_teof_n_i <= '0';
trn_trem_n_i <= X"0" & mbuf_Qout(70) & mbuf_Qout(70)
& mbuf_Qout(70) & mbuf_Qout(70);
trn_td_i <= mbuf_Qout(C_DBUS_WIDTH-1 downto 0);
end if;
when St_d_Tail_chk =>
take_an_Arbitration <= '0';
mbuf_RE_ok <= '0';
-- trn_tsof_n_i <= '1';
if trn_tdst_rdy_n_i = '1' then
trn_tsrc_rdy_n_i <= '0';
trn_teof_n_i <= '0';
trn_trem_n_i <= trn_trem_n_i;
trn_td_i <= trn_td_i;
TxTrn_State <= St_d_Tail_chk;
else
trn_tsrc_rdy_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= (Others=>'0');
trn_trem_n_i <= (Others=>'0');
TxTrn_State <= St_TxIdle;
end if;
when Others =>
take_an_Arbitration <= '0';
RdNumber <= (Others=>'0');
RdNumber_eq_One <= '0';
RdNumber_eq_Two <= '0';
StartAddr <= (Others=>'0');
-- FixedAddr <= '0';
BAR_value <= (Others=>'0');
RdCmd_Req <= '0';
mbuf_reset <= '0';
mbuf_RE_ok <= '0';
trn_tsrc_rdy_n_i <= '1';
trn_tsof_n_i <= '1';
trn_teof_n_i <= '1';
trn_td_i <= (Others=>'0');
trn_trem_n_i <= (Others=>'0');
TxTrn_State <= St_TxIdle;
end case;
end if;
end process;
---------------------------------------------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Synch_Acc_us_DMA_Bytes:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
us_DMA_Bytes_i <= '0' & trn_td_i(32+C_TLP_FLD_WIDTH_OF_LENG-1 downto 32) & "00";
if trn_td_i(C_TLP_FMT_BIT_TOP) = '1'
and trn_td_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
= C_ALL_ZEROS(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) then
us_DMA_Bytes_Add_i <= not trn_tsof_n_i
and not trn_tsrc_rdy_n_i
and not trn_tdst_rdy_n_i
;
else
us_DMA_Bytes_Add_i <= '0';
end if;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | f20fa668d79168b743797abdfe5a9e87 | 0.457341 | 3.397865 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/shifter_tb.vhd | 1 | 1,505 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY shifter_tb IS
END shifter_tb;
ARCHITECTURE behavior OF shifter_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shifter
PORT(
clk : IN std_logic;
input : IN std_logic_vector(15 downto 0);
enable : IN std_logic;
active_output : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal input : std_logic_vector(15 downto 0) := (others => '0');
signal enable : std_logic := '0';
--Outputs
signal active_output : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shifter PORT MAP (
clk => clk,
input => input,
enable => enable,
active_output => active_output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
enable <= '0';
wait for clk_period;
enable <= '1';
input <= "0000000001111000";
-- wait for clk_period*3;
--
-- input <= "0000000000000111";
wait for clk_period;
input <= "0000000000000000";
wait;
end process;
END;
| bsd-2-clause | b155977355e7516bf9473099721e394f | 0.583389 | 3.697789 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_address_decoder.vhd | 1 | 23,175 | -------------------------------------------------------------------------------
-- Address Decoder - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v1.01.a
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
use work.cpu_xadc_wiz_0_0_pselect_f;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
use work.cpu_xadc_wiz_0_0_family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity cpu_xadc_wiz_0_0_address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of cpu_xadc_wiz_0_0_address_decoder is
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity work.cpu_xadc_wiz_0_0_pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity work.cpu_xadc_wiz_0_0_pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
| gpl-3.0 | f8c7bed4a2f5803ca32df3bc419bfcc1 | 0.42753 | 4.686552 | false | false | false | false |
peteut/nvc | test/regress/stack1.vhd | 2 | 432 | entity stack1 is
end entity;
architecture arch of stack1 is
signal clk : bit;
begin
process
variable cnt : natural;
begin
if(clk='0') then
clk <= '1';
else
clk <= '0';
end if;
if now < 50 ns then
wait for 2 ns;
end if;
cnt := cnt + 1;
if cnt = 1000000 then
wait;
end if;
end process;
end arch;
| gpl-3.0 | 8bea37f3af98f42befc584b56a6a7fe8 | 0.462963 | 4.037383 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_exdes.vhd | 1 | 4,750 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_sp_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_sp_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END ram_16x1k_sp_exdes;
ARCHITECTURE xilinx OF ram_16x1k_sp_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ram_16x1k_sp IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : ram_16x1k_sp
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| bsd-3-clause | c5572105039954183bb759e5ab47f569 | 0.563789 | 4.580521 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_pselect_f.vhd | 1 | 12,520 | -------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_pselect_f.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2008-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_pselect_f.vhd
--
-- Description:
-- (Note: At least as early as I.31, XST implements a carry-
-- chain structure for most decoders when these are coded in
-- inferrable VHLD. An example of such code can be seen
-- below in the "INFERRED_GEN" Generate Statement.
--
-- -> New code should not need to instantiate pselect-type
-- components.
--
-- -> Existing code can be ported to Virtex5 and later by
-- replacing pselect instances by pselect_f instances.
-- As long as the C_FAMILY parameter is not included
-- in the Generic Map, an inferred implementation
-- will result.
--
-- -> If the designer wishes to force an explicit carry-
-- chain implementation, pselect_f can be used with
-- the C_FAMILY parameter set to the target
-- Xilinx FPGA family.
-- )
--
-- Parameterizeable peripheral select (address decode).
-- AValid qualifier comes in on Carry In at bottom
-- of carry chain.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: cpu_xadc_wiz_0_0_pselect_f.vhd
-- cpu_xadc_wiz_0_0_family_support.vhd
--
-------------------------------------------------------------------------------
-- History:
-- Vaibhav & FLO 05/26/06 First Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
library work;
use work.cpu_xadc_wiz_0_0_family_support.all;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_AB -- number of address bits to decode
-- C_AW -- width of address bus
-- C_BAR -- base address of peripheral (peripheral select
-- is asserted when the C_AB most significant
-- address bits match the C_AB most significant
-- C_BAR bits
-- Definition of Ports:
-- A -- address input
-- AValid -- address qualifier
-- CS -- peripheral select
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_pselect_f is
generic (
C_AB : integer := 9;
C_AW : integer := 32;
C_BAR : std_logic_vector;
C_FAMILY : string := "nofamily"
);
port (
A : in std_logic_vector(0 to C_AW-1);
AValid : in std_logic;
CS : out std_logic
);
end entity cpu_xadc_wiz_0_0_pselect_f;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of cpu_xadc_wiz_0_0_pselect_f is
component MUXCY is
port (
O : out std_logic;
CI : in std_logic;
DI : in std_logic;
S : in std_logic
);
end component MUXCY;
constant NLS : natural := native_lut_size(C_FAMILY);
constant USE_INFERRED : boolean := not supported(C_FAMILY, u_MUXCY)
or NLS=0 -- LUT not supported.
or C_AB <= NLS; -- Just one LUT
-- needed.
-----------------------------------------------------------------------------
-- C_BAR may not be indexed from 0 and may not be ascending;
-- BAR recasts C_BAR to have these properties.
-----------------------------------------------------------------------------
constant BAR : std_logic_vector(0 to C_BAR'length-1) := C_BAR;
type bo2sl_type is array (boolean) of std_logic;
constant bo2sl : bo2sl_type := (false => '0', true => '1');
function min(i, j: integer) return integer is
begin
if i<j then return i; else return j; end if;
end;
begin
------------------------------------------------------------------------------
-- Check that the generics are valid.
------------------------------------------------------------------------------
-- synthesis translate_off
assert (C_AB <= C_BAR'length) and (C_AB <= C_AW)
report "cpu_xadc_wiz_0_0_pselect_f generic error: " &
"(C_AB <= C_BAR'length) and (C_AB <= C_AW)" &
" does not hold."
severity failure;
-- synthesis translate_on
------------------------------------------------------------------------------
-- Build a behavioral decoder
------------------------------------------------------------------------------
INFERRED_GEN : if (USE_INFERRED = TRUE ) generate
begin
XST_WA:if C_AB > 0 generate
CS <= AValid when A(0 to C_AB-1) = BAR (0 to C_AB-1) else
'0' ;
end generate XST_WA;
PASS_ON_GEN:if C_AB = 0 generate
CS <= AValid ;
end generate PASS_ON_GEN;
end generate INFERRED_GEN;
------------------------------------------------------------------------------
-- Build a structural decoder using the fast carry chain
------------------------------------------------------------------------------
GEN_STRUCTURAL_A : if (USE_INFERRED = FALSE ) generate
constant NUM_LUTS : integer := (C_AB+(NLS-1))/NLS;
signal lut_out : std_logic_vector(0 to NUM_LUTS); -- XST workaround
signal carry_chain : std_logic_vector(0 to NUM_LUTS);
begin
carry_chain(NUM_LUTS) <= AValid; -- Initialize start of carry chain.
CS <= carry_chain(0); -- Assign end of carry chain to output.
XST_WA: if NUM_LUTS > 0 generate -- workaround for XST
begin
GEN_DECODE: for i in 0 to NUM_LUTS-1 generate
constant NI : natural := i;
constant BTL : positive := min(NLS, C_AB-NI*NLS);-- num Bits This LUT
begin
lut_out(i) <= bo2sl(A(NI*NLS to NI*NLS+BTL-1) = -- LUT
BAR(NI*NLS to NI*NLS+BTL-1));
MUXCY_I: component MUXCY -- MUXCY
port map (
O => carry_chain(i),
CI => carry_chain(i+1),
DI => '0',
S => lut_out(i)
);
end generate GEN_DECODE;
end generate XST_WA;
end generate GEN_STRUCTURAL_A;
end imp;
| gpl-3.0 | cc6aa889cf327c1f072878b9b642647b | 0.411901 | 5.276022 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/example_design/k7_bram4096x64_prod.vhd | 1 | 10,568 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: k7_bram4096x64_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 8
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 64
-- C_READ_WIDTH_A : 64
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 8
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 64
-- C_READ_WIDTH_B : 64
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 1
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_bram4096x64_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END k7_bram4096x64_prod;
ARCHITECTURE xilinx OF k7_bram4096x64_prod IS
COMPONENT k7_bram4096x64_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : k7_bram4096x64_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| gpl-2.0 | bf53769594dceb4d038476fa81171b0e | 0.491957 | 3.817919 | false | false | false | false |
esar/hdmilight-v1 | fpga/test_ambilight.vhd | 2 | 5,251 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_ambilight IS
END test_ambilight;
ARCHITECTURE behavior OF test_ambilight IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ambilight
PORT(
vidclk : IN std_logic;
viddata_r : IN std_logic_vector(7 downto 0);
viddata_g : IN std_logic_vector(7 downto 0);
viddata_b : IN std_logic_vector(7 downto 0);
hblank : IN std_logic;
vblank : IN std_logic;
cfgclk : IN std_logic;
cfgwe : IN std_logic;
cfglight : IN std_logic_vector(7 downto 0);
cfgcomponent : IN std_logic_vector(3 downto 0);
cfgdatain : IN std_logic_vector(7 downto 0);
cfgdataout : OUT std_logic_vector(7 downto 0);
output : OUT std_logic
);
END COMPONENT;
--Inputs
signal vidclk : std_logic := '0';
signal viddata_r : std_logic_vector(7 downto 0) := (others => '0');
signal viddata_g : std_logic_vector(7 downto 0) := (others => '0');
signal viddata_b : std_logic_vector(7 downto 0) := (others => '0');
signal hblank : std_logic := '0';
signal vblank : std_logic := '0';
signal cfgclk : std_logic := '0';
signal cfgwe : std_logic := '0';
signal cfglight : std_logic_vector(7 downto 0) := (others => '0');
signal cfgcomponent : std_logic_vector(3 downto 0) := (others => '0');
signal cfgdatain : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal cfgdataout : std_logic_vector(7 downto 0);
signal output : std_logic;
-- Clock period definitions
constant vidclk_period : time := 10 ns;
constant cfgclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ambilight PORT MAP (
vidclk => vidclk,
viddata_r => viddata_r,
viddata_g => viddata_g,
viddata_b => viddata_b,
hblank => hblank,
vblank => vblank,
cfgclk => cfgclk,
cfgwe => cfgwe,
cfglight => cfglight,
cfgcomponent => cfgcomponent,
cfgdatain => cfgdatain,
cfgdataout => cfgdataout,
output => output
);
-- Clock process definitions
vidclk_process :process
begin
vidclk <= '0';
wait for vidclk_period/2;
vidclk <= '1';
wait for vidclk_period/2;
end process;
cfgclk_process :process
begin
cfgclk <= '0';
wait for cfgclk_period/2;
cfgclk <= '1';
wait for cfgclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for vidclk_period*10;
cfglight <= (others => '0');
cfgcomponent <= x"0";
wait for cfgclk_period*2;
cfgdatain <= x"00";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgcomponent <= x"1";
wait for cfgclk_period*2;
cfgdatain <= x"07";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgcomponent <= x"2";
wait for cfgclk_period*2;
cfgdatain <= x"00";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgcomponent <= x"3";
wait for cfgclk_period*2;
cfgdatain <= x"07";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgcomponent <= x"4";
wait for cfgclk_period*2;
cfgdatain <= x"06";
cfgwe <= '1';
wait for cfgclk_period*2;
cfgwe <= '0';
wait for cfgclk_period;
for field in 0 to 10 loop
-- vblank = hBlank = 1
hblank <= '1';
vblank <= '1';
for y in 0 to 20 loop
for x in 0 to 820 loop
viddata_r <= x"00";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
end loop;
for y in 0 to 288 loop
-- vBlank = hBlank = 0
hblank <= '0';
vblank <= '0';
-- line of video, 720 pixels in total
for x in 0 to 720 loop
viddata_r <= x"aa";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
-- hBlank = 1
hblank <= '1';
-- blank data
for x in 0 to 100 loop
viddata_r <= x"00";
viddata_g <= x"00";
viddata_b <= x"00";
wait for vidclk_period;
end loop;
end loop;
end loop;
wait;
end process;
END;
| gpl-2.0 | e60b45aba49e8321245e8a1057f583fc | 0.580842 | 3.550372 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/fan.vhd | 1 | 5,462 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : fan.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-04-28
-- Last update: 2016-08-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Pulse width/density modulator
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-28 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity fan is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
fan_pct : in std_logic_vector(7 downto 0);
fan_tach : in std_logic;
fan_pwm : out std_logic;
fan_uspr : out std_logic_vector(19 downto 0)
);
end fan;
architecture rtl of fan is
signal pwm_div : std_logic_vector(3 downto 0);
signal pwm_ce : std_logic;
signal pwm_cnt : std_logic_vector(7 downto 0);
signal pwm_term : std_logic;
signal pwm_out : std_logic;
signal tach_dly : std_logic_vector(2 downto 0);
signal tach_pulse : std_logic;
signal tach_meas : std_logic_vector(19 downto 0);
signal tach_msout : std_logic_vector(19 downto 0);
begin
-- First divider to generate clock enable for the PWM
-- Divide by 16
fan_pwmdiv:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pwm_div <= (others => '0');
pwm_ce <= '0';
elsif (clk'event and clk = '1') then
if (pwm_ce = '1') then
pwm_div <= (others => '0');
else
pwm_div <= pwm_div + 1;
end if;
if (pwm_div = x"E") then
pwm_ce <= '1';
else
pwm_ce <= '0';
end if;
end if;
end process;
-- Pulse width modulator counter
fan_pwmcnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pwm_cnt <= (others => '0');
pwm_term <= '0';
elsif (clk'event and clk = '1') then
if (pwm_ce = '1') then
pwm_cnt <= pwm_cnt + 1;
if (pwm_cnt = x"FE") then
pwm_term <= '1';
else
pwm_term <= '0';
end if;
end if;
end if;
end process;
-- Pulse width modulator output
fan_pwmout:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pwm_out <= '0';
elsif (clk'event and clk = '1') then
if (pwm_ce = '1') then
if (pwm_term = '1') then
pwm_out <= '1';
elsif (pwm_cnt = fan_pct) then
pwm_out <= '0';
end if;
end if;
end if;
end process;
-- Final output register
fan_oreg: delay_sig generic map (1) port map (rst_n, clk, pwm_out, fan_pwm);
-- ----------------------------------------------------------------------
-- Tach measurement reference is 1 us
-- Tach input buffer and rising edge detector
fan_ireg:
process (rst_n, clk) is
begin
if (rst_n = '0') then
tach_dly <= (others => '0');
tach_pulse <= '0';
elsif (clk'event and clk = '1') then
tach_dly(0) <= fan_tach; -- input register
if (tsc_1ppus = '1') then
tach_dly(1) <= tach_dly(0);
tach_dly(2) <= tach_dly(1);
tach_pulse <= not tach_dly(2) and tach_dly(1);
end if;
end if;
end process;
-- Measure time between tach pulses
fan_meas:
process (rst_n, clk) is
variable tach_add : std_logic_vector(fan_uspr'left + 1 downto 0);
begin
if (rst_n = '0') then
tach_meas <= (others => '0');
tach_msout <= (others => '0');
elsif (clk'event and clk = '1') then
if (tsc_1ppus = '1') then
if (tach_pulse = '1') then
tach_meas <= (others => '0');
tach_meas(0) <= '1'; -- Start measurement at one
else
-- saturating up counter
tach_add := ('0' & tach_meas) + 1;
if (tach_add(tach_add'left) = '0') then
tach_meas <= tach_add(tach_meas'range);
end if;
end if;
-- Output at next pulse or overflow
if (tach_pulse = '1' or tach_add(tach_add'left) = '1') then
tach_msout <= tach_meas;
end if;
end if;
end if;
end process;
fan_uspr <= tach_msout;
end rtl;
| gpl-3.0 | aa251c5bd1ba329530b903680f537b64 | 0.413036 | 3.83837 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/simulation/k7_bram4096x64_tb.vhd | 1 | 4,553 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: k7_bram4096x64_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY k7_bram4096x64_tb IS
END ENTITY;
ARCHITECTURE k7_bram4096x64_tb_ARCH OF k7_bram4096x64_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
k7_bram4096x64_synth_inst:ENTITY work.k7_bram4096x64_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 | f6d61c4f2e373513ccff817a4204862a | 0.618274 | 4.507921 | false | false | false | false |
peteut/nvc | test/elab/issue19.vhd | 2 | 1,939 | entity comp6_bot is
generic (num : integer := 2 );
port (
x : in bit_vector(7 downto 0);
y : out bit_vector(7 downto 0) );
end entity;
architecture rtl of comp6_bot is
function cfunc (constant val : integer) return integer is
variable tmp : integer;
begin tmp := 0;
for i in 0 to 3 loop
tmp := tmp + val;
end loop;
return tmp;
end function cfunc;
function cfunc2 (constant k : integer) return integer is
variable tmp : integer;
begin
tmp := 1;
for i in 0 to k loop
if tmp > k then
return i;
end if;
tmp := tmp + tmp;
end loop;
end cfunc2;
function my_cfunc2 (constant k: integer) return integer is
begin
if k > 1 then
return cfunc(k);
end if;
return 1;
end my_cfunc2;
constant cnum : integer := cfunc(num);
type m_a_t is array (cnum-1 downto 0) of bit_vector(num-1 downto 0);
signal ma : m_a_t;
signal tmp : integer := cnum;
constant cnum2 : integer := cfunc2(num);
type m_a_t2 is array (cnum2-1 downto 0) of bit_vector(num-1 downto 0);
signal ma2 : m_a_t2;
signal tmp2 : integer := cnum2;
constant cnum3 : integer := my_cfunc2(num);
type m_a_t3 is array (cnum3-1 downto 0) of bit_vector(num-1 downto 0);
signal ma3 : m_a_t3;
signal tmp3 : integer := cnum3;
begin
y <= x;
g1: if cnum /= 32 generate
assert false;
end generate;
g2: if cnum3 /= 32 generate
assert false;
end generate;
end architecture;
-------------------------------------------------------------------------------
entity comp6 is
end entity;
architecture rtl of comp6 is
signal b: bit_vector(7 downto 0);
component comp6_bot is
generic (num : integer := 2 );
port (
y : out bit_vector(7 downto 0);
x : in bit_vector(7 downto 0) );
end component;
begin
c1: component comp6_bot
generic map (num => 8)
port map ( x=>x"aa", y=>b );
end architecture;
| gpl-3.0 | f15ce4f746c82e3e2b5a85f87325784e | 0.587932 | 3.303237 | false | false | false | false |
peteut/nvc | test/bounds/issue356.vhd | 2 | 621 | entity nvc_bug is
end nvc_bug;
architecture behav of nvc_bug is
type std_logic_vector is array (integer range <>) of integer;
function to_bitvector(x : std_logic_vector) return bit_vector;
signal mode : std_logic_vector(1 downto 0);
begin
process
subtype modetype is bit_vector(mode'range);
begin
case modetype'(to_bitvector(mode)) is
when "00" =>
when "01" =>
when "10" =>
when "11" =>
when others =>
end case;
assert false report "end of test" severity note;
wait;
end process;
end behav;
| gpl-3.0 | 1aed18483e77b8808ea797d33ed9f04b | 0.5781 | 3.955414 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/axi_ipif_ssp1.vhd | 2 | 22,534 | -------------------------------------------------------------------------------
-- axi_ipif_ssp1.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_ipif_ssp1.vhd
-- Version: v1.01.b
--
-- Description: AXI IPIF Slave Services Package 1
-- This block provides the following services:
-- - wraps the axi_lite_ipif interface to IPIC block and
-- sets up its address decoding.
-- - Provides the Software Reset register
-- - Provides interrupt servicing
-- - IPIC multiplexing service between the external IIC
-- register block IP2Bus data path and the internal
-- Interrupt controller's IP2Bus data path.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
-- NLR 01/07/11
-- ^^^^^^
-- - Updated the version to v1_01_b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
library axi_iic_v2_0;
library axi_lite_ipif_v3_0;
-- axi_lite_ipif refered from axi_lite_ipif_v2_0
use axi_lite_ipif_v3_0.axi_lite_ipif;
use axi_lite_ipif_v3_0.ipif_pkg.all;
library interrupt_control_v3_1;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_IIC_REGS -- Number of IIC registers
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- Target FPGA architecture
-------------------------------------------------------------------------------
-- Definition of Ports:
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IP interconnect port signals
-- Bus2IP_Clk -- Bus to IIC clock
-- Bus2IP_Reset -- Bus to IIC reset
-- Bus2IIC_Addr -- Bus to IIC address
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_RNW -- Bus to IIC read not write
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_ipif_ssp1 is
generic
(
C_NUM_IIC_REGS : integer := 10;
-- Number of IIC Registers
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7"
-- Select the target architecture type
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2Bus_IntrEvent : in std_logic_vector (0 to 7);
-- IIC Interrupt events
IIC2INTC_Irpt : out std_logic; -- IP-2-interrupt controller
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IP Interconnect (IPIC) port signals used by the IIC registers.
Bus2IIC_Clk : out std_logic;
Bus2IIC_Reset : out std_logic;
Bus2IIC_Addr : out std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
Bus2IIC_Data : out std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_RNW : out std_logic;
Bus2IIC_RdCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
Bus2IIC_WrCE : out std_logic_vector(0 to C_NUM_IIC_REGS-1);
IIC2Bus_Data : in std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1)
);
end entity axi_ipif_ssp1;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_ipif_ssp1 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ZEROES : std_logic_vector(0 to 31) := X"00000000";
constant INTR_BASEADDR : std_logic_vector := X"00000000";
constant INTR_HIGHADDR : std_logic_vector
:= X"0000003F";
constant RST_BASEADDR : std_logic_vector
:= X"00000040";
constant RST_HIGHADDR : std_logic_vector
:= X"00000043";
constant IIC_REG_BASEADDR : std_logic_vector
:= X"00000100";
constant IIC_REG_HIGHADDR : std_logic_vector
:= X"000001FF";
constant C_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZEROES & INTR_BASEADDR, -- Interrupt controller
ZEROES & INTR_HIGHADDR,
ZEROES & RST_BASEADDR, -- Software reset register
ZEROES & RST_HIGHADDR,
ZEROES & IIC_REG_BASEADDR, -- IIC registers
ZEROES & IIC_REG_HIGHADDR
);
constant C_ARD_IDX_INTERRUPT : integer := 0;
constant C_ARD_IDX_RESET : integer := 1;
constant C_ARD_IDX_IIC_REGS : integer := 2;
-- The C_IP_INTR_MODE_ARRAY must have the same width as the IP2Bus_IntrEvent
-- entity port.
constant C_IP_INTR_MODE_ARRAY : integer_array_type
:= (3, 3, 3, 3, 3, 3, 3, 3);
constant C_INCLUDE_DEV_PENCODER : boolean := FALSE;
constant C_INCLUDE_DEV_ISC : boolean := FALSE;
constant C_NUM_INTERRUPT_REGS : integer := 16;
constant C_NUM_RESET_REGS : integer := 1;
constant C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
C_ARD_IDX_INTERRUPT => C_NUM_INTERRUPT_REGS,
C_ARD_IDX_RESET => C_NUM_RESET_REGS,
C_ARD_IDX_IIC_REGS => C_NUM_IIC_REGS
);
constant C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0)
:= X"000001FF";
constant C_USE_WSTRB : integer := 0;
constant C_DPHASE_TIMEOUT : integer := 8;
SUBTYPE INTERRUPT_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 0)+C_ARD_NUM_CE_ARRAY(0)-1;
SUBTYPE RESET_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 1)+C_ARD_NUM_CE_ARRAY(1)-1;
SUBTYPE IIC_CE_RNG is integer
range calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)
to calc_start_ce_index(C_ARD_NUM_CE_ARRAY, 2)+C_ARD_NUM_CE_ARRAY(2)-1;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
-- IPIC Signals
signal AXI_Bus2IP_Clk : std_logic;
signal AXI_Bus2IP_Resetn: std_logic;
signal AXI_Bus2IP_Reset : std_logic;
signal AXI_IP2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_IP2Bus_WrAck : std_logic;
signal AXI_IP2Bus_RdAck : std_logic;
signal AXI_IP2Bus_WrAck1 : std_logic;
signal AXI_IP2Bus_RdAck1 : std_logic;
signal AXI_IP2Bus_WrAck2 : std_logic;
signal AXI_IP2Bus_RdAck2 : std_logic;
signal Intr2Bus_WrAck : std_logic;
signal Intr2Bus_RdAck : std_logic;
signal AXI_IP2Bus_Error : std_logic;
signal AXI_Bus2IP_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal AXI_Bus2IP_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal AXI_Bus2IP_RNW : std_logic;
signal AXI_Bus2IP_CS : std_logic_vector(0 to
((C_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal AXI_Bus2IP_RdCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
signal AXI_Bus2IP_WrCE : std_logic_vector(0 to
calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
-- Derived IPIC signals for use with the reset register functionality
signal reset2Bus_Error : std_logic;
signal reset2IP_Reset : std_logic;
-- Derived IPIC signals for use with the interrupt controller
signal Intr2Bus_DevIntr : std_logic;
signal Intr2Bus_DBus : std_logic_vector(0 to C_S_AXI_DATA_WIDTH-1);
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
--------------------------------------------------------------------------
-- RESET signal assignment - IPIC RESET is active low
--------------------------------------------------------------------------
AXI_Bus2IP_Reset <= not AXI_Bus2IP_Resetn;
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_FAMILY => C_FAMILY,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY
)
port map
(
-- System signals
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
-- AXI Interface signals
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Resetn => AXI_Bus2IP_Resetn,
IP2Bus_Data => AXI_IP2Bus_Data,
IP2Bus_WrAck => AXI_IP2Bus_WrAck,
IP2Bus_RdAck => AXI_IP2Bus_RdAck,
IP2Bus_Error => AXI_IP2Bus_Error,
Bus2IP_Addr => AXI_Bus2IP_Addr,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_RNW => AXI_Bus2IP_RNW,
Bus2IP_BE => open,
Bus2IP_CS => AXI_Bus2IP_CS,
Bus2IP_RdCE => AXI_Bus2IP_RdCE,
Bus2IP_WrCE => AXI_Bus2IP_WrCE
);
-------------------------------------------------------------------------------
-- INTERRUPT DEVICE
-------------------------------------------------------------------------------
X_INTERRUPT_CONTROL : entity interrupt_control_v3_1.interrupt_control
generic map (
C_NUM_CE => C_NUM_INTERRUPT_REGS, -- [integer range 4 to 16]
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC => 1, -- [integer range 1 to 29]
C_IP_INTR_MODE_ARRAY => C_IP_INTR_MODE_ARRAY, -- [INTEGER_ARRAY_TYPE]
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER => C_INCLUDE_DEV_PENCODER, -- [boolean]
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC => C_INCLUDE_DEV_ISC, -- [boolean]
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH -- [integer range 32 to 128]
)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_Reset => reset2IP_Reset,
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
Interrupt_RdCE => AXI_Bus2IP_RdCE(INTERRUPT_CE_RNG),
Interrupt_WrCE => AXI_Bus2IP_WrCE(INTERRUPT_CE_RNG),
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts => "00",
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts => "0",
-- Inputs from the IP Interface
IP2Bus_IntrEvent => IIC2Bus_IntrEvent,
-- Final Device Interrupt Output
Intr2Bus_DevIntr => IIC2INTC_Irpt,
-- Status Reply Outputs to the Bus
Intr2Bus_DBus => Intr2Bus_DBus,
Intr2Bus_WrAck => open,
Intr2Bus_RdAck => open,
Intr2Bus_Error => open,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-------------------------------------------------------------------------------
-- SOFT RESET REGISTER
-------------------------------------------------------------------------------
X_SOFT_RESET : entity axi_iic_v2_0.soft_reset
generic map (
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH, -- [integer]
-- Width of the write data bus
C_RESET_WIDTH => 4)
port map (
-- Inputs From the IPIF Bus
Bus2IP_Reset => AXI_Bus2IP_Reset,
Bus2IP_Clk => AXI_Bus2IP_Clk,
Bus2IP_WrCE => AXI_Bus2IP_WrCE(RESET_CE_RNG'LEFT),
Bus2IP_Data => AXI_Bus2IP_Data,
Bus2IP_BE => "1111",
-- Final Device Reset Output
reset2IP_Reset => reset2IP_Reset,
-- Status Reply Outputs to the Bus
reset2Bus_WrAck => open,
reset2Bus_Error => reset2Bus_Error,
Reset2Bus_ToutSup => open);
-------------------------------------------------------------------------------
-- IIC Register (External) Connections
-------------------------------------------------------------------------------
Bus2IIC_Clk <= AXI_Bus2IP_Clk;
Bus2IIC_Reset <= reset2IP_Reset;
Bus2IIC_Addr <= AXI_Bus2IP_Addr;
Bus2IIC_Data <= AXI_Bus2IP_Data;
Bus2IIC_RNW <= AXI_Bus2IP_RNW;
Bus2IIC_RdCE <= AXI_Bus2IP_RdCE(IIC_CE_RNG);
Bus2IIC_WrCE <= AXI_Bus2IP_WrCE(IIC_CE_RNG);
-------------------------------------------------------------------------------
-- Read Ack/Write Ack generation
-------------------------------------------------------------------------------
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_RdAck2 <= or_reduce(AXI_Bus2IP_CS) and AXI_Bus2IP_RNW;
AXI_IP2Bus_RdAck1 <= AXI_IP2Bus_RdAck2;
end if;
end process;
AXI_IP2Bus_RdAck <= (not (AXI_IP2Bus_RdAck1)) and AXI_IP2Bus_RdAck2;
process(AXI_Bus2IP_Clk)
begin
if(AXI_Bus2IP_Clk'event and AXI_Bus2IP_Clk = '1') then
AXI_IP2Bus_WrAck2 <= (or_reduce(AXI_Bus2IP_CS) and not AXI_Bus2IP_RNW);
AXI_IP2Bus_WrAck1 <= AXI_IP2Bus_WrAck2;
end if;
end process;
AXI_IP2Bus_WrAck <= (not AXI_IP2Bus_WrAck1) and AXI_IP2Bus_WrAck2;
-------------------------------------------------------------------------------
-- Data and Error generation
-------------------------------------------------------------------------------
AXI_IP2Bus_Data <= Intr2Bus_DBus or IIC2Bus_Data;
AXI_IP2Bus_Error <= reset2Bus_Error;
end architecture RTL;
| gpl-3.0 | c6574877e7cdb8b354ebf8d03bee12d0 | 0.468093 | 4.025366 | false | false | false | false |
ErikAndren/VGA3BitTestPattern | VGA3BitTestPattern.vhd | 1 | 2,184 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
entity VGA3BitTestPattern is
port (
RstN : in bit1;
Clk : in bit1;
--
Button : in word(3-1 downto 0);
--
HSync : out bit1;
VSync : out bit1;
VgaRed : out word(3-1 downto 0);
VgaGreen : out word(3-1 downto 0);
VgaBlue : out word(3-1 downto 0)
);
end entity;
architecture rtl of VGA3BitTestPattern is
signal ButtonDB, Button_N, Button_D : word(Button'length-1 downto 0);
signal Blue_D, Red_D, Green_D : word(3-1 downto 0);
signal Blue_N, Red_N, Green_N : word(3-1 downto 0);
signal InView : bit1;
begin
Db0 : entity work.Debounce
port map (
Clk => Clk,
x => Button(0),
DBx => ButtonDB(0)
);
Db1 : entity work.Debounce
port map (
Clk => Clk,
x => Button(1),
DBx => ButtonDB(1)
);
Db2 : entity work.Debounce
port map (
Clk => Clk,
x => Button(2),
DBx => ButtonDB(2)
);
Sync : process (RstN, Clk)
begin
if RstN = '0' then
Button_D <= (others => '1');
Red_D <= (others => '0');
Blue_D <= (others => '0');
Green_D <= (others => '0');
elsif rising_edge(Clk) then
Button_D <= Button_N;
Red_D <= Red_N;
Green_D <= Green_N;
Blue_D <= Blue_N;
end if;
end process;
AsyncProc : process (Green_D, Blue_D, Red_D, Button_D, ButtonDB)
begin
Red_N <= Red_D;
Green_N <= Green_D;
Blue_N <= Blue_D;
Button_N <= ButtonDB;
if (ButtonDB(0) = '0' and Button_D(0) = '1') then
Red_N <= Red_D + 1;
end if;
if (ButtonDB(1) = '0' and Button_D(1) = '1') then
Blue_N <= Blue_D + 1;
end if;
if (ButtonDB(2) = '0' and Button_D(2) = '1') then
Green_N <= Green_D + 1;
end if;
end process;
VgaRed <= Red_D when inView = '1' else (others => '0');
VgaBlue <= Blue_D when inView = '1' else (others => '0');
VgaGreen <= Green_D when inView = '1' else (others => '0');
VgaGen : entity work.VGAGen
generic map (
ClkDiv => true
)
port map (
RstN => RstN,
Clk => Clk,
--
HSync => HSync,
VSync => VSync,
RedOut => open,
GreenOut => open,
BlueOut => open,
--
InView => InView
);
end architecture rtl;
| gpl-2.0 | eae7b7d5879047b4bb1da6283652e5d6 | 0.576923 | 2.490308 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_synth.vhd | 1 | 11,718 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_eb_fifo_counted_resized_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_eb_fifo_counted_resized_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF k7_eb_fifo_counted_resized_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(15-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(15-1 DOWNTO 0);
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: k7_eb_fifo_counted_resized_dgen
GENERIC MAP (
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: k7_eb_fifo_counted_resized_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: k7_eb_fifo_counted_resized_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 64,
C_WR_PNTR_WIDTH => 15,
C_RD_PNTR_WIDTH => 15,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
k7_eb_fifo_counted_resized_inst : k7_eb_fifo_counted_resized_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
VALID => valid,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | dbbbef4a8ec6a5f144e677c8f5786826 | 0.460147 | 3.960122 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_dverif.vhd | 1 | 5,853 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
ENTITY k7_sfifo_15x128_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF k7_sfifo_15x128_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:k7_sfifo_15x128_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 92fed792a00a87b98a14c6aa78dec5b2 | 0.56911 | 3.965447 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/bmg_stim_gen.vhd | 1 | 16,101 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENB : OUT STD_LOGIC :='0';
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(16,16);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEB_VCC: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEB_GND: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(9 DOWNTO 0) <= WRITE_ADDR_A(9 DOWNTO 0);
READ_ADDR_INT_A(9 DOWNTO 0) <= READ_ADDR_A(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(9 DOWNTO 0) <= WRITE_ADDR_B(9 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(9 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(9 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH => 16,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH =>16 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
ENA <= DO_READ_A OR DO_WRITE_A ;
ENB <= DO_READ_B OR DO_WRITE_B ;
WEA <= IF_THEN_ELSE(DO_WRITE_A='1', WEA_VCC,WEA_GND) ;
WEB <= IF_THEN_ELSE(DO_WRITE_B='1', WEB_VCC,WEB_GND) ;
END ARCHITECTURE;
| bsd-3-clause | a8af4cd190914fb4edcef680d25765fc | 0.575741 | 3.201631 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/superip_internal.vhd | 1 | 8,647 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity superip_internal is
port(
-- Outputs
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
slv_reg26 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : in STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
--register 26 is output, flags go there
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end entity superip_internal;
architecture RTL of superip_internal is
-- Internals
signal Mux3_BalanceORMux2_Left : std_logic_vector(23 downto 0);
signal Mux3_BalanceORMux2_Right : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Left : std_logic_vector(23 downto 0);
signal Mux2_FilterORMux1_Right : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Left_out : std_logic_vector(23 downto 0);
signal Mux1_VolCtrlORAudio_Right_out : std_logic_vector(23 downto 0);
signal Filter_Left_out : std_logic_vector(23 downto 0);
signal Filter_Right_out : std_logic_vector(23 downto 0);
signal OUT_VOLCTRL_L : signed(23 downto 0);
signal OUT_VOLCTRL_R : signed(23 downto 0);
signal Balance_L_OUT : signed(23 downto 0);
signal Balance_R_OUT : signed(23 downto 0);
-- Outputs Register 26
ALIAS VolCtrl_RDY_L : STD_LOGIC is slv_reg26(0);
ALIAS VolCtrl_RDY_R : STD_LOGIC is slv_reg26(1);
ALIAS Filter_ready_out : STD_LOGIC is slv_reg26(2);
ALIAS READY_BAL : STD_LOGIC is slv_reg26(3);
-- Inputs Register 27
ALIAS HP_SW : STD_LOGIC is slv_reg27(0); --1 will enable it
ALIAS BP_SW : STD_LOGIC is slv_reg27(4); --1 will enable it
ALIAS LP_SW : STD_LOGIC is slv_reg27(8); --1 will enable it
ALIAS Reset_in : STD_LOGIC is slv_reg27(16);--1 will reset everything
ALIAS sample_trigger_en : STD_LOGIC is slv_reg27(20);--1 will set filter to wait for SAMPLE_TRIG from audioIP, otherwise, its constantly calculating
ALIAS bus_frames_en : std_logic is slv_reg27(31);--1 will
-- inputs register 25
signal Mux_Select_in : std_logic_vector(2 downto 0);
--slv_reg25(0) -> Mux1:= Volctrl or rawAudio; 0 for Volctrl pass
--slv_reg25(4) -> Mux2:= Filter or Mux1; 0 for Filter pass
--slv_reg25(8) -> mux3:= Balance or Mux2 0 for Balance pass
-- inputs register 24
ALIAS Reset_Filter : STD_LOGIC is slv_reg24(0); --1 will reset filter only, we use this because its unstable
begin
Mux_Select_in <= slv_reg25(8) & slv_reg25(4) & slv_reg25(0);
slv_reg28 <= x"00" & Mux3_BalanceORMux2_Left; --this goes out, and should arrive in mixerboard
slv_reg29 <= x"00" & Mux3_BalanceORMux2_Right; --this goes out, and should arrive in mixerboard
Mux_Frames_or_internal : process(Mux3_BalanceORMux2_Left, Mux3_BalanceORMux2_Right, slv_reg27(31), slv_reg30(23 downto 0), slv_reg31(23 downto 0))
begin
if bus_frames_en = '0' then
Mux3_BalanceORMux2_Left_out <= Mux3_BalanceORMux2_Left;
Mux3_BalanceORMux2_Right_out <= Mux3_BalanceORMux2_Right;
else
Mux3_BalanceORMux2_Left_out <= slv_reg30(23 downto 0); --this is input from mixerIP,
Mux3_BalanceORMux2_Right_out <= slv_reg31(23 downto 0);
end if;
end process;
Tester_inst : entity work.Tester
port map(
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
VolCtrl_Left_out_in => std_logic_vector(OUT_VOLCTRL_L),
VolCtrl_Right_out_in => std_logic_vector(OUT_VOLCTRL_R),
Mux1_VolCtrlORAudio_Left_out => Mux1_VolCtrlORAudio_Left_out,
Mux1_VolCtrlORAudio_Right_out => Mux1_VolCtrlORAudio_Right_out,
Filter_Left_out_in => Filter_Left_out,
Filter_Right_out_in => Filter_Right_out,
Mux2_FilterORMux1_Left_out => Mux2_FilterORMux1_Left,
Mux2_FilterORMux1_Right_out => Mux2_FilterORMux1_Right,
Balance_Left_out_in => std_logic_vector(Balance_L_OUT),
Balance_Right_out_in => std_logic_vector(Balance_R_OUT),
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right,
Mux_Select_in => Mux_Select_in
);
VolCtrl_inst : entity work.VolCtrl
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8
)
port map(
OUT_VOLCTRL_L => OUT_VOLCTRL_L,
OUT_VOLCTRL_R => OUT_VOLCTRL_R,
OUT_RDY_L => VolCtrl_RDY_L,
OUT_RDY_R => VolCtrl_RDY_R,
IN_SIG_L => signed(Audio_Left_in),
IN_SIG_R => signed(Audio_Right_in),
IN_COEF_L => signed(slv_reg15),
IN_COEF_R => signed(slv_reg16),
RESET => Reset_in,
CLK_48 => CLK_48_in,
CLK_100M => CLK_100M_in
);
filter_Comp : entity work.Filter_Top_Level
port map(
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14,
CLK_48 => CLK_48_in,
RST => Reset_Filter,
SAMPLE_TRIG => SAMPLE_TRIG,
sample_trigger_en => sample_trigger_en,
HP_SW => HP_SW,
BP_SW => BP_SW,
LP_SW => LP_SW,
AUDIO_IN_L => Mux1_VolCtrlORAudio_Left_out,
AUDIO_IN_R => Mux1_VolCtrlORAudio_Right_out,
AUDIO_OUT_L => Filter_Left_out,
AUDIO_OUT_R => Filter_Right_out,
FILTER_DONE => Filter_ready_out
);
Balance_inst : entity work.Balance
generic map(
INTBIT_WIDTH => 24,
FRACBIT_WIDTH => 8,
N => 32,
Attenuation_Const => 11
)
port map(
CLK_BAL => CLK_48_in,
RESET_BAL => Reset_in,
POINTER => to_integer(signed(slv_reg17)),
CH_L_IN => signed(Mux2_FilterORMux1_Left),
CH_R_IN => signed(Mux2_FilterORMux1_Right),
CH_L_OUT => Balance_L_OUT,
CH_R_OUT => Balance_R_OUT,
READY_BAL => READY_BAL
);
end architecture RTL;
| mit | ace34135d199a165cf9f12836198c442 | 0.576501 | 3.061969 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_13/lab13_1/lab13_1.vhd | 1 | 760 | library ieee;
use ieee.std_logic_1164.all;
entity RS_FF is
PORT ( S: in std_logic;
R: in std_logic;
CLOCK: in std_logic;
CLR: in std_logic;
PRESET: in std_logic;
Q: out std_logic;
QN: out std_logic);
end RS_FF;
Architecture Arch_RS_FF of RS_FF is
begin
FF:process(CLOCK,CLR,PRESET)
begin
if (CLR='0') then
x:='0';
elsif(PRESET='0') then
x:='1';
elsif(CLOCK='1' and CLOCK'EVENT) then
if (S='0' and R='0') then
x:=x;
elsif(S='1' and R='1') then
x:='Z';
elsif(S='0' and R='1') then
x:='0';
else
x:='1';
end if;
end if;
Q<=x;
QN<=not x;
end process FF;
end Arch_RS_FF;
| gpl-2.0 | 63580e8681d18882cbda90f18341ea67 | 0.478947 | 2.900763 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/bcdtime.vhd | 1 | 8,290 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : bcdtime.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-04
-- Last update: 2016-08-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: BCD Time counters ms resolution
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-04 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
entity bcdtime is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
set : in std_logic;
set_time : in time_ty;
cur_time : out time_ty
);
end bcdtime;
architecture rtl of bcdtime is
SIGNAL dig_1ms : std_logic_vector(3 downto 0);
SIGNAL dig_10ms : std_logic_vector(3 downto 0);
SIGNAL dig_100ms : std_logic_vector(3 downto 0);
SIGNAL dig_1s : std_logic_vector(3 downto 0);
SIGNAL dig_10s : std_logic_vector(3 downto 0);
SIGNAL dig_1m : std_logic_vector(3 downto 0);
SIGNAL dig_10m : std_logic_vector(3 downto 0);
SIGNAL dig_1h : std_logic_vector(3 downto 0);
SIGNAL dig_10h : std_logic_vector(3 downto 0);
signal ms_carry : std_logic;
signal s_carry : std_logic;
signal m_carry : std_logic;
signal h_carry : std_logic;
signal sync_time : std_logic;
begin
-- Set latch
time_set:
process (rst_n, clk) is
begin
if (rst_n = '0') then
sync_time <= '0';
elsif (clk'event and clk = '1') then
if (set = '1') then
sync_time <= '1';
elsif (tsc_1pps = '1') then
sync_time <= '0';
end if;
end if;
end process;
-- Clock ms counters 0-999
time_ms:
process (rst_n, clk) is
begin
if (rst_n = '0') then
dig_1ms <= (others => '0');
dig_10ms <= (others => '0');
dig_100ms <= (others => '0');
ms_carry <= '0';
elsif (clk'event and clk = '1') then
if (sync_time = '1' and tsc_1pps = '1') then
dig_1ms <= (others => '0');
dig_1ms(1) <= '1'; -- Set 2ms ahead for display pipe delay
dig_10ms <= (others => '0');
dig_100ms <= (others => '0');
ms_carry <= '0';
elsif (tsc_1ppms = '1') then
if (dig_1ms = 9) then
dig_1ms <= (others => '0');
else
dig_1ms <= dig_1ms + 1;
end if;
if (dig_1ms = 9) then
if (dig_10ms = 9) then
dig_10ms <= (others => '0');
else
dig_10ms <= dig_10ms + 1;
end if;
end if;
if (dig_1ms = 9 and dig_10ms = 9) then
if (dig_100ms = 9) then
dig_100ms <= (others => '0');
else
dig_100ms <= dig_100ms + 1;
end if;
end if;
if (dig_1ms = 8 and dig_10ms = 9 and dig_100ms = 9) then
ms_carry <= '1';
else
ms_carry <= '0';
end if;
end if;
end if;
end process;
-- Clock second counters 0 - 59
time_s:
process (rst_n, clk) is
begin
if (rst_n = '0') then
dig_1s <= (others => '0');
dig_10s <= (others => '0');
s_carry <= '0';
elsif (clk'event and clk = '1') then
if (sync_time = '1' and tsc_1pps = '1') then
dig_1s <= set_time.t_1s;
dig_10s <= set_time.t_10s;
s_carry <= '0';
elsif (tsc_1ppms = '1' and ms_carry = '1') then
if (dig_1s = 9) then
dig_1s <= (others => '0');
else
dig_1s <= dig_1s + 1;
end if;
if (dig_1s = 9) then
if (dig_10s = 5) then
dig_10s <= (others => '0');
else
dig_10s <= dig_10s + 1;
end if;
end if;
if (dig_1s = 8 and dig_10s = 5) then
s_carry <= '1';
else
s_carry <= '0';
end if;
end if;
end if;
end process;
-- Clock minute counters 0 - 59
time_m:
process (rst_n, clk) is
begin
if (rst_n = '0') then
dig_1m <= (others => '0');
dig_10m <= (others => '0');
m_carry <= '0';
elsif (clk'event and clk = '1') then
if (sync_time = '1' and tsc_1pps = '1') then
dig_1m <= set_time.t_1m;
dig_10m <= set_time.t_10m;
m_carry <= '0';
elsif (tsc_1ppms = '1' and s_carry = '1' and ms_carry ='1') then
if (dig_1m = 9) then
dig_1m <= (others => '0');
else
dig_1m <= dig_1m + 1;
end if;
if (dig_1m = 9) then
if (dig_10m = 5) then
dig_10m <= (others => '0');
else
dig_10m <= dig_10m + 1;
end if;
end if;
if (dig_1m = 8 and dig_10m = 5) then
m_carry <= '1';
else
m_carry <= '0';
end if;
end if;
end if;
end process;
-- Clock hour counters 0 - 23
time_h:
process (rst_n, clk) is
begin
if (rst_n = '0') then
dig_1h <= (others => '0');
dig_10h <= (others => '0');
h_carry <= '0';
elsif (clk'event and clk = '1') then
if (sync_time = '1' and tsc_1pps = '1') then
dig_1h <= set_time.t_1h;
dig_10h <= set_time.t_10h;
h_carry <= '0';
elsif (tsc_1ppms = '1' and m_carry = '1' and s_carry = '1' and ms_carry = '1') then
if (dig_1h = 9 or (dig_1h = 3 and dig_10h = 2)) then
dig_1h <= (others => '0');
else
dig_1h <= dig_1h + 1;
end if;
if (dig_1h = 9 or (dig_1h = 3 and dig_10h = 2)) then
if (dig_1h = 3 and dig_10h = 2) then
dig_10h <= (others => '0');
else
dig_10h <= dig_10h + 1;
end if;
end if;
if (dig_1h = 2 and dig_10h = 2) then
h_carry <= '1';
else
h_carry <= '0';
end if;
end if;
end if;
end process;
cur_time.t_1ms <= dig_1ms;
cur_time.t_10ms <= dig_10ms;
cur_time.t_100ms <= dig_100ms;
cur_time.t_1s <= dig_1s;
cur_time.t_10s <= dig_10s;
cur_time.t_1m <= dig_1m;
cur_time.t_10m <= dig_10m;
cur_time.t_1h <= dig_1h;
cur_time.t_10h <= dig_10h;
end rtl;
| gpl-3.0 | 5d4d6c90cbac98f6417e77ff2e32df67 | 0.362002 | 3.709172 | false | false | false | false |
peteut/nvc | test/sem/static.vhd | 1 | 2,317 | entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
sub2_i: entity work.sub
generic map ( N => N )
port map (
x(N downto 0) => x ); -- Error
process is
type rec is record
f1, f2 : integer;
end record;
subtype rs is rec; -- OK
constant rc : rs := (0, 0); -- OK
constant i : integer := rc.f1; -- OK
begin
end process;
end architecture;
| gpl-3.0 | b97bf373b0816c2516916e33ad1daa64 | 0.425982 | 4.388258 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_8/Lab_8_3/lpm_divide0.vhd | 1 | 4,511 | -- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_divide
-- ============================================================
-- File Name: lpm_divide0.vhd
-- Megafunction Name(s):
-- lpm_divide
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_divide0 IS
PORT
(
denom : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_divide0;
ARCHITECTURE SYN OF lpm_divide0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_divide
GENERIC (
lpm_drepresentation : STRING;
lpm_hint : STRING;
lpm_nrepresentation : STRING;
lpm_type : STRING;
lpm_widthd : NATURAL;
lpm_widthn : NATURAL
);
PORT (
denom : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
quotient : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
remain : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
numer : IN STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
quotient <= sub_wire0(3 DOWNTO 0);
remain <= sub_wire1(3 DOWNTO 0);
lpm_divide_component : lpm_divide
GENERIC MAP (
lpm_drepresentation => "UNSIGNED",
lpm_hint => "LPM_REMAINDERPOSITIVE=TRUE",
lpm_nrepresentation => "UNSIGNED",
lpm_type => "LPM_DIVIDE",
lpm_widthd => 4,
lpm_widthn => 4
)
PORT MAP (
denom => denom,
numer => numer,
quotient => sub_wire0,
remain => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
-- Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "0"
-- Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
-- Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
-- Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
-- Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "4"
-- Retrieval info: USED_PORT: denom 0 0 4 0 INPUT NODEFVAL denom[3..0]
-- Retrieval info: USED_PORT: numer 0 0 4 0 INPUT NODEFVAL numer[3..0]
-- Retrieval info: USED_PORT: quotient 0 0 4 0 OUTPUT NODEFVAL quotient[3..0]
-- Retrieval info: USED_PORT: remain 0 0 4 0 OUTPUT NODEFVAL remain[3..0]
-- Retrieval info: CONNECT: @numer 0 0 4 0 numer 0 0 4 0
-- Retrieval info: CONNECT: @denom 0 0 4 0 denom 0 0 4 0
-- Retrieval info: CONNECT: quotient 0 0 4 0 @quotient 0 0 4 0
-- Retrieval info: CONNECT: remain 0 0 4 0 @remain 0 0 4 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_divide0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 | f67cb500f3b8e3b4cb55ea2832803e6b | 0.657061 | 3.634972 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_12/Lab_12_1/lab_12_1.vhd | 1 | 637 | Library IEEE;
use IEEE.std_logic_1164.all;
entity lab_12_1 is
port( A: in std_logic_vector (2 downto 0);
Q: out std_logic_vector (7 downto 0));
end entity lab_12_1;
architecture Behave of lab_12_1 is
begin
process (A)
begin
case A is
when "000" => Q <= "00000001";
when "001" => Q <= "00000010";
when "010" => Q <= "00000100";
when "011" => Q <= "00001000";
when "100" => Q <= "00010000";
when "101" => Q <= "00100000";
when "110" => Q <= "01000000";
when "111" => Q <= "10000000";
when others => Q <= "00000000";
end case;
end process;
end Behave; | gpl-2.0 | b33f367a76cab4d05409e12a22529c1e | 0.538462 | 2.895455 | false | false | false | false |
peteut/nvc | test/sem/attr.vhd | 1 | 4,629 | entity e is
end entity;
architecture a1 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of x : signal is 6; -- OK
attribute bar of y : signal is "hello"; -- OK
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
signal i : int_vec(1 to 3);
attribute foo of i : signal is 6; -- OK
begin
process is
variable v : integer;
begin
v := x'foo; -- OK
report y'bar; -- OK
end process;
process is
begin
report z'foo; -- Error
end process;
process is
variable v : int_vec_ptr;
begin
assert v'length = 5;
assert v.all'length = 62;
end process;
process is
begin
report e'path_name; -- OK
report e'instance_name; -- OK
report a1'path_name; -- OK
report a1'instance_name; -- OK
end process;
process is
begin
assert i'event; -- OK
assert i(1)'event; -- OK
assert i(x)'event; -- OK
assert i'foo = 1; -- OK
assert i(1)'foo = 2; -- Error
end process;
end architecture;
architecture a2 of e is
attribute foo : integer;
attribute bar : string;
signal x, y, z : integer;
attribute foo of z : signal is string'("boo"); -- Error
attribute bar of x : signal is 73; -- Error
attribute foo of q : signal is 71; -- Error
attribute foo of yah : label is 12; -- Ignored
begin
end architecture;
architecture a3 of e is
type int10_vec is array (integer range 1 to 10) of integer;
begin
process is
variable x : integer;
begin
assert int10_vec'low = 1; -- OK
assert int10_vec'high = 10; -- OK
assert int10_vec'left = 1; -- OK
assert int10_vec'right = 10; -- OK
assert int10_vec'low(1) = 1; -- OK
assert int10_vec'left(x) = 2; -- Error
end process;
end architecture;
package p is
function func(x : in integer) return integer;
end package;
package body p is
function func(x : in integer) return integer is
begin
report func'instance_name;
return x + 1;
end function;
end package body;
entity issue39 is
generic (
g : bit := '0'
);
begin
assert (g = '0' or g = '1')
report issue39'instance_name & "oops!"
severity failure;
end entity issue39;
architecture a4 of e is
begin
process is
begin
assert integer'image(0)(0) = '0'; -- OK
end process;
process is
variable i : integer;
attribute a : bit_vector;
attribute a of i : variable is "101";
attribute b : integer;
attribute b of i : variable is 4;
begin
assert i'a(1) = '0'; -- OK
assert i'b(1) = 1; -- Error
end process;
process is
variable i : integer;
attribute a : boolean;
attribute a of i : signal is true; -- Error
begin
end process;
process is
variable x : integer;
begin
assert x'last_event = 0 ns; -- Error
end process;
process is
type bv_ptr is access bit_vector;
variable a : bv_ptr;
type r is record
x : integer;
end record;
variable b : r;
begin
a(a'range) := "110101"; -- OK
a(bit_vector'range) := "110101"; -- Error
a(b'range) := "101010"; -- Error
a(e'range) := "110101"; -- Error
end process;
process is
function func(x : integer) return bit_vector;
variable a : bit_vector(1 to 10);
begin
a(func(4)'range) := (others => '1'); -- OK
end process;
process is
type bvptr is access bit_vector;
variable b : bvptr;
begin
for i in b.all'range loop -- OK
end loop;
for i in b'range loop -- OK
end loop;
end process;
b1: block is
function fie return string is
begin
return "11010011";
end function;
function fie2(x : integer := 4) return string is
begin
-- report fie2'instance_name; ???
return "101";
end function;
begin
process
begin
assert fie'RIGHT = 1; -- OK
assert fie2'RIGHT = 1; -- OK
end process;
end block;
end architecture;
| gpl-3.0 | 98be36c63f70cf17b78ffa456bf89474 | 0.518471 | 3.916244 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_encoder.vhd | 3 | 20,871 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_udaten: in std_logic_vector(1 downto 0); -- user data control
conf_chsten: in std_logic_vector(1 downto 0); -- ch. status control
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
user_data_a: in std_logic_vector(191 downto 0); -- ch. a user data
user_data_b: in std_logic_vector(191 downto 0); -- ch. b user data
ch_stat_a: in std_logic_vector(191 downto 0); -- ch. a status
ch_stat_b: in std_logic_vector(191 downto 0); -- ch. b status
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
mem_rd: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio, imem_rd : std_logic;
signal tick_counter : std_logic;
signal tick_counter_d1 : std_logic;
signal tick_counter_d2 : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
tick_counter <= not tick_counter;
end if;
end process DCLK;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
tick_counter_d1 <= '0';
tick_counter_d2 <= '0';
spdif_clk_en <= '0';
else
tick_counter_d1 <= tick_counter;
tick_counter_d2 <= tick_counter_d1;
spdif_clk_en <= '0';
if (tick_counter_d1 xor tick_counter_d2) = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
-- Sample memory read process. Enabled by the conf_txdata bit.
-- Buffer address is reset when disabled. Also generates events for
-- lower and upper buffer empty conditions
mem_rd <= imem_rd;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
imem_rd <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
imem_rd <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
imem_rd <='1';
end if;
when READ_CHA =>
channel <= '0';
imem_rd <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
imem_rd <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
imem_rd <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
imem_rd <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
if resetn = '0' then
spdif_tx_o <= '0';
else
spdif_tx_o <= spdif_out;
end if;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= ch_stat_a when conf_chsten = "01" else
ch_stat_a when conf_chsten = "10" and framest = CHANNEL_A else
ch_stat_b when conf_chsten = "10" and framest = CHANNEL_B else
def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= user_data_a when conf_udaten = "01" else
user_data_a when conf_udaten = "10" and framest = CHANNEL_A else
user_data_b when conf_udaten = "10" and framest = CHANNEL_B else
def_user_data;
end rtl;
| mit | 4cb6e7691fb88dd31cfa1c71e05f6735 | 0.449907 | 4.309519 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_dgen.vhd | 1 | 4,560 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
ENTITY rd_fifo_256to64_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF rd_fifo_256to64_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 63e6ff2fcc93544cc99d95974a60f4b1 | 0.601535 | 4.179652 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_pkg.vhd | 1 | 11,457 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_sfifo_15x128_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_sfifo_15x128_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_sfifo_15x128_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_sfifo_15x128_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_sfifo_15x128_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_sfifo_15x128_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_sfifo_15x128_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_sfifo_15x128_pkg;
PACKAGE BODY k7_sfifo_15x128_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_sfifo_15x128_pkg;
| gpl-2.0 | 5ac13464d35d67058d6cd178eff6c2af | 0.506764 | 3.908905 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/v6eb_pcie.vhd | 1 | 94,257 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:12:51 01 Feb 2010
-- Design Name:
-- Module Name: v6pcieDMA - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
--
-- Revision 1.00 - File Released
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity v6pcieDMA is
generic (
constant pcieLanes : integer := 4--C_NUM_PCIE_LANES
);
Port (
userclk_50MHz : IN std_logic; --50 MHz USER Socket SingleEnded
userclk_200MHz_n : IN std_logic; --200 MHz USER Socket LVDS N
userclk_200MHz_p : IN std_logic; --200 MHz USER Socket LVDS P
-- DPR blinker
LEDs_IO_pin : OUT std_logic_vector(3 downto 0);
-- PCIe transceivers
pci_exp_rxp : IN std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_rxn : IN std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txp : OUT std_logic_vector(pcieLanes - 1 downto 0);
pci_exp_txn : OUT std_logic_vector(pcieLanes - 1 downto 0);
-- Necessity signals
sys_clk_p : IN std_logic; --125 MHz PCIe Clock
sys_clk_n : IN std_logic; --125 MHz PCIe Clock
sys_reset_n : IN std_logic --Reset
);
end entity v6pcieDMA;
architecture Behavioral of v6pcieDMA is
component PCIe_UserLogic_00
port (
bram_rd_dout: in std_logic_vector(63 downto 0);
debug_in_1i: in std_logic_vector(31 downto 0);
debug_in_2i: in std_logic_vector(31 downto 0);
debug_in_3i: in std_logic_vector(31 downto 0);
debug_in_4i: in std_logic_vector(31 downto 0);
dma_host2board_busy: in std_logic;
dma_host2board_done: in std_logic;
fifo_rd_count: in std_logic_vector(14 downto 0);
fifo_wr_count: in std_logic_vector(14 downto 0);
fifo_rd_dout: in std_logic_vector(71 downto 0);
fifo_rd_empty: in std_logic;
fifo_rd_pempty: in std_logic;
fifo_wr_full: in std_logic;
fifo_wr_pfull: in std_logic;
fifo_rd_valid: in std_logic;
inout_logic_cw_ce: in std_logic := '1';
inout_logic_cw_clk: in std_logic;
reg01_td: in std_logic_vector(31 downto 0);
reg01_tv: in std_logic;
reg02_td: in std_logic_vector(31 downto 0);
reg02_tv: in std_logic;
reg03_td: in std_logic_vector(31 downto 0);
reg03_tv: in std_logic;
reg04_td: in std_logic_vector(31 downto 0);
reg04_tv: in std_logic;
reg05_td: in std_logic_vector(31 downto 0);
reg05_tv: in std_logic;
reg06_td: in std_logic_vector(31 downto 0);
reg06_tv: in std_logic;
reg07_td: in std_logic_vector(31 downto 0);
reg07_tv: in std_logic;
reg08_td: in std_logic_vector(31 downto 0);
reg08_tv: in std_logic;
reg09_td: in std_logic_vector(31 downto 0);
reg09_tv: in std_logic;
reg10_td: in std_logic_vector(31 downto 0);
reg10_tv: in std_logic;
reg11_td: in std_logic_vector(31 downto 0);
reg11_tv: in std_logic;
reg12_td: in std_logic_vector(31 downto 0);
reg12_tv: in std_logic;
reg13_td: in std_logic_vector(31 downto 0);
reg13_tv: in std_logic;
reg14_td: in std_logic_vector(31 downto 0);
reg14_tv: in std_logic;
rst_i: in std_logic;
user_logic_cw_ce: in std_logic := '1';
user_logic_cw_clk: in std_logic;
bram_rd_addr: out std_logic_vector(11 downto 0);
bram_wr_addr: out std_logic_vector(11 downto 0);
bram_wr_din: out std_logic_vector(63 downto 0);
bram_wr_en: out std_logic_vector(7 downto 0);
fifo_rd_en: out std_logic;
fifo_wr_din: out std_logic_vector(71 downto 0);
fifo_wr_en: out std_logic;
reg01_rd: out std_logic_vector(31 downto 0);
reg01_rv: out std_logic;
reg02_rd: out std_logic_vector(31 downto 0);
reg02_rv: out std_logic;
reg03_rd: out std_logic_vector(31 downto 0);
reg03_rv: out std_logic;
reg04_rd: out std_logic_vector(31 downto 0);
reg04_rv: out std_logic;
reg05_rd: out std_logic_vector(31 downto 0);
reg05_rv: out std_logic;
reg06_rd: out std_logic_vector(31 downto 0);
reg06_rv: out std_logic;
reg07_rd: out std_logic_vector(31 downto 0);
reg07_rv: out std_logic;
reg08_rd: out std_logic_vector(31 downto 0);
reg08_rv: out std_logic;
reg09_rd: out std_logic_vector(31 downto 0);
reg09_rv: out std_logic;
reg10_rd: out std_logic_vector(31 downto 0);
reg10_rv: out std_logic;
reg11_rd: out std_logic_vector(31 downto 0);
reg11_rv: out std_logic;
reg12_rd: out std_logic_vector(31 downto 0);
reg12_rv: out std_logic;
reg13_rd: out std_logic_vector(31 downto 0);
reg13_rv: out std_logic;
reg14_rd: out std_logic_vector(31 downto 0);
reg14_rv: out std_logic;
rst_o: out std_logic;
user_int_1o: out std_logic;
user_int_2o: out std_logic;
user_int_3o: out std_logic
);
end component;
-- -----------------------------------------------------------------------
--- COMPONENT Declaration: v6_pcie_v1_6 x4 ---
--- OSS: Ricordarsi di matchare POWER_SAVE - VENDOR_ID e DEVICE_ID ---
--- OSS: For POWER_SAVE error correct bit[4] and install ISE12 Patch!! ---
-- -----------------------------------------------------------------------
--S component v6_pcie_v1_7_x1
-- component v6_pcie_v1_7_x4
component pcieCore
generic (
PL_FAST_TRAIN : string := "FALSE"
);
port (
-------------------------------------------------------------------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface --
-------------------------------------------------------------------------------------------------------------------
pci_exp_txp : out std_logic_vector(3 downto 0);
pci_exp_txn : out std_logic_vector(3 downto 0);
pci_exp_rxp : in std_logic_vector(3 downto 0);
pci_exp_rxn : in std_logic_vector(3 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 2. Clocking Interface --
-------------------------------------------------------------------------------------------------------------------
PIPE_PCLK_IN : in std_logic;
PIPE_RXUSRCLK_IN : in std_logic;
PIPE_RXOUTCLK_IN : in std_logic_vector(3 downto 0);
PIPE_DCLK_IN : in std_logic;
PIPE_USERCLK1_IN : in std_logic;
PIPE_USERCLK2_IN : in std_logic;
PIPE_OOBCLK_IN : in std_logic;
PIPE_MMCM_LOCK_IN : in std_logic;
PIPE_TXOUTCLK_OUT : out std_logic;
PIPE_RXOUTCLK_OUT : out std_logic_vector(3 downto 0);
PIPE_PCLK_SEL_OUT : out std_logic_vector(3 downto 0);
PIPE_GEN3_OUT : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 3. AXI-S Interface --
-------------------------------------------------------------------------------------------------------------------
-- Common
user_clk_out : out std_logic;
user_reset_out : out std_logic;
user_lnk_up : out std_logic;
-- TX
tx_buf_av : out std_logic_vector(5 downto 0);
tx_cfg_req : out std_logic;
tx_err_drop : out std_logic;
s_axis_tx_tready : out std_logic;
s_axis_tx_tdata : in std_logic_vector((C_DATA_WIDTH - 1) downto 0);
s_axis_tx_tkeep : in std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
s_axis_tx_tlast : in std_logic;
s_axis_tx_tvalid : in std_logic;
s_axis_tx_tuser : in std_logic_vector(3 downto 0);
tx_cfg_gnt : in std_logic;
-- RX
m_axis_rx_tdata : out std_logic_vector((C_DATA_WIDTH - 1) downto 0);
m_axis_rx_tkeep : out std_logic_vector((C_DATA_WIDTH / 8 - 1) downto 0);
m_axis_rx_tlast : out std_logic;
m_axis_rx_tvalid : out std_logic;
m_axis_rx_tready : in std_logic;
m_axis_rx_tuser : out std_logic_vector(21 downto 0);
rx_np_ok : in std_logic;
rx_np_req : in std_logic;
-- Flow Control
fc_cpld : out std_logic_vector(11 downto 0);
fc_cplh : out std_logic_vector(7 downto 0);
fc_npd : out std_logic_vector(11 downto 0);
fc_nph : out std_logic_vector(7 downto 0);
fc_pd : out std_logic_vector(11 downto 0);
fc_ph : out std_logic_vector(7 downto 0);
fc_sel : in std_logic_vector(2 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 4. Configuration (CFG) Interface --
-------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EP and RP --
---------------------------------------------------------------------
cfg_mgmt_do : out std_logic_vector (31 downto 0);
cfg_mgmt_rd_wr_done : out std_logic;
cfg_status : out std_logic_vector(15 downto 0);
cfg_command : out std_logic_vector(15 downto 0);
cfg_dstatus : out std_logic_vector(15 downto 0);
cfg_dcommand : out std_logic_vector(15 downto 0);
cfg_lstatus : out std_logic_vector(15 downto 0);
cfg_lcommand : out std_logic_vector(15 downto 0);
cfg_dcommand2 : out std_logic_vector(15 downto 0);
cfg_pcie_link_state : out std_logic_vector(2 downto 0);
cfg_pmcsr_pme_en : out std_logic;
cfg_pmcsr_powerstate : out std_logic_vector(1 downto 0);
cfg_pmcsr_pme_status : out std_logic;
cfg_received_func_lvl_rst : out std_logic;
-- Management Interface
cfg_mgmt_di : in std_logic_vector (31 downto 0);
cfg_mgmt_byte_en : in std_logic_vector (3 downto 0);
cfg_mgmt_dwaddr : in std_logic_vector (9 downto 0);
cfg_mgmt_wr_en : in std_logic;
cfg_mgmt_rd_en : in std_logic;
cfg_mgmt_wr_readonly : in std_logic;
-- Error Reporting Interface
cfg_err_ecrc : in std_logic;
cfg_err_ur : in std_logic;
cfg_err_cpl_timeout : in std_logic;
cfg_err_cpl_unexpect : in std_logic;
cfg_err_cpl_abort : in std_logic;
cfg_err_posted : in std_logic;
cfg_err_cor : in std_logic;
cfg_err_atomic_egress_blocked : in std_logic;
cfg_err_internal_cor : in std_logic;
cfg_err_malformed : in std_logic;
cfg_err_mc_blocked : in std_logic;
cfg_err_poisoned : in std_logic;
cfg_err_norecovery : in std_logic;
cfg_err_tlp_cpl_header : in std_logic_vector(47 downto 0);
cfg_err_cpl_rdy : out std_logic;
cfg_err_locked : in std_logic;
cfg_err_acs : in std_logic;
cfg_err_internal_uncor : in std_logic;
cfg_trn_pending : in std_logic;
cfg_pm_halt_aspm_l0s : in std_logic;
cfg_pm_halt_aspm_l1 : in std_logic;
cfg_pm_force_state_en : in std_logic;
cfg_pm_force_state : std_logic_vector(1 downto 0);
cfg_dsn : std_logic_vector(63 downto 0);
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
cfg_interrupt : in std_logic;
cfg_interrupt_rdy : out std_logic;
cfg_interrupt_assert : in std_logic;
cfg_interrupt_di : in std_logic_vector(7 downto 0);
cfg_interrupt_do : out std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : out std_logic_vector(2 downto 0);
cfg_interrupt_msienable : out std_logic;
cfg_interrupt_msixenable : out std_logic;
cfg_interrupt_msixfm : out std_logic;
cfg_interrupt_stat : in std_logic;
cfg_pciecap_interrupt_msgnum : in std_logic_vector(4 downto 0);
cfg_to_turnoff : out std_logic;
cfg_turnoff_ok : in std_logic;
cfg_bus_number : out std_logic_vector(7 downto 0);
cfg_device_number : out std_logic_vector(4 downto 0);
cfg_function_number : out std_logic_vector(2 downto 0);
cfg_pm_wake : in std_logic;
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
cfg_pm_send_pme_to : in std_logic;
cfg_ds_bus_number : in std_logic_vector(7 downto 0);
cfg_ds_device_number : in std_logic_vector(4 downto 0);
cfg_ds_function_number : in std_logic_vector(2 downto 0);
cfg_mgmt_wr_rw1c_as_rw : in std_logic;
cfg_msg_received : out std_logic;
cfg_msg_data : out std_logic_vector(15 downto 0);
cfg_bridge_serr_en : out std_logic;
cfg_slot_control_electromech_il_ctl_pulse : out std_logic;
cfg_root_control_syserr_corr_err_en : out std_logic;
cfg_root_control_syserr_non_fatal_err_en : out std_logic;
cfg_root_control_syserr_fatal_err_en : out std_logic;
cfg_root_control_pme_int_en : out std_logic;
cfg_aer_rooterr_corr_err_reporting_en : out std_logic;
cfg_aer_rooterr_non_fatal_err_reporting_en : out std_logic;
cfg_aer_rooterr_fatal_err_reporting_en : out std_logic;
cfg_aer_rooterr_corr_err_received : out std_logic;
cfg_aer_rooterr_non_fatal_err_received : out std_logic;
cfg_aer_rooterr_fatal_err_received : out std_logic;
cfg_msg_received_err_cor : out std_logic;
cfg_msg_received_err_non_fatal : out std_logic;
cfg_msg_received_err_fatal : out std_logic;
cfg_msg_received_pm_as_nak : out std_logic;
cfg_msg_received_pm_pme : out std_logic;
cfg_msg_received_pme_to_ack : out std_logic;
cfg_msg_received_assert_int_a : out std_logic;
cfg_msg_received_assert_int_b : out std_logic;
cfg_msg_received_assert_int_c : out std_logic;
cfg_msg_received_assert_int_d : out std_logic;
cfg_msg_received_deassert_int_a : out std_logic;
cfg_msg_received_deassert_int_b : out std_logic;
cfg_msg_received_deassert_int_c : out std_logic;
cfg_msg_received_deassert_int_d : out std_logic;
cfg_msg_received_setslotpowerlimit : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 5. Physical Layer Control and Status (PL) Interface --
-------------------------------------------------------------------------------------------------------------------
pl_directed_link_change : in std_logic_vector(1 downto 0);
pl_directed_link_width : in std_logic_vector(1 downto 0);
pl_directed_link_speed : in std_logic;
pl_directed_link_auton : in std_logic;
pl_upstream_prefer_deemph : in std_logic;
pl_sel_lnk_rate : out std_logic;
pl_sel_lnk_width : out std_logic_vector(1 downto 0);
pl_ltssm_state : out std_logic_vector(5 downto 0);
pl_lane_reversal_mode : out std_logic_vector(1 downto 0);
pl_phy_lnk_up : out std_logic;
pl_tx_pm_state : out std_logic_vector(2 downto 0);
pl_rx_pm_state : out std_logic_vector(1 downto 0);
pl_link_upcfg_cap : out std_logic;
pl_link_gen2_cap : out std_logic;
pl_link_partner_gen2_supported : out std_logic;
pl_initial_link_width : out std_logic_vector(2 downto 0);
pl_directed_change_done : out std_logic;
---------------------------------------------------------------------
-- EP Only --
---------------------------------------------------------------------
pl_received_hot_rst : out std_logic;
---------------------------------------------------------------------
-- RP Only --
---------------------------------------------------------------------
pl_transmit_hot_rst : in std_logic;
pl_downstream_deemph_source : in std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 6. AER interface --
-------------------------------------------------------------------------------------------------------------------
cfg_err_aer_headerlog : in std_logic_vector(127 downto 0);
cfg_aer_interrupt_msgnum : in std_logic_vector(4 downto 0);
cfg_err_aer_headerlog_set : out std_logic;
cfg_aer_ecrc_check_en : out std_logic;
cfg_aer_ecrc_gen_en : out std_logic;
-------------------------------------------------------------------------------------------------------------------
-- 7. VC interface --
-------------------------------------------------------------------------------------------------------------------
cfg_vc_tcvc_map : out std_logic_vector(6 downto 0);
-------------------------------------------------------------------------------------------------------------------
-- 8. System(SYS) Interface --
-------------------------------------------------------------------------------------------------------------------
PIPE_MMCM_RST_N : in std_logic; -- // Async | Async
sys_clk : in std_logic;
sys_rst_n : in std_logic
);
end component;
signal fifo_reset_done : std_logic;
signal pio_reading_status : std_logic;
-- -----------------------------------------------------------------------
-- DDR SDRAM control module
-- -----------------------------------------------------------------------
COMPONENT bram_DDRs_Control_loopback
GENERIC (
C_ASYNFIFO_WIDTH : integer ;
P_SIMULATION : boolean
);
PORT (
DDR_wr_sof : IN std_logic;
DDR_wr_eof : IN std_logic;
DDR_wr_v : IN std_logic;
DDR_wr_FA : IN std_logic;
DDR_wr_Shift : IN std_logic;
DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : OUT std_logic;
DDR_rdc_sof : IN std_logic;
DDR_rdc_eof : IN std_logic;
DDR_rdc_v : IN std_logic;
DDR_rdc_FA : IN std_logic;
DDR_rdc_Shift : IN std_logic;
DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : IN std_logic;
DDR_FIFO_Empty : OUT std_logic;
DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : OUT std_logic;
DDR_Blinker : OUT std_logic;
mem_clk : IN std_logic;
trn_clk : IN std_logic;
Sim_Zeichen : OUT std_logic;
trn_reset_n : IN std_logic
);
END COMPONENT;
COMPONENT bram_DDRs_Control
GENERIC (
C_ASYNFIFO_WIDTH : integer ;
P_SIMULATION : boolean
);
PORT (
--USER Logic Interface
user_wr_weA : IN std_logic_vector(7 downto 0);
user_wr_addrA : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
user_wr_dinA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
user_rd_addrB : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
user_rd_doutB : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
user_rd_clk : IN std_logic;
user_wr_clk : IN std_logic;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof : IN std_logic;
DDR_wr_eof : IN std_logic;
DDR_wr_v : IN std_logic;
DDR_wr_FA : IN std_logic;
DDR_wr_Shift : IN std_logic;
DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : OUT std_logic;
DDR_rdc_sof : IN std_logic;
DDR_rdc_eof : IN std_logic;
DDR_rdc_v : IN std_logic;
DDR_rdc_FA : IN std_logic;
DDR_rdc_Shift : IN std_logic;
DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : IN std_logic;
DDR_FIFO_Empty : OUT std_logic;
DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : OUT std_logic;
DDR_Blinker : OUT std_logic;
mem_clk : IN std_logic;
trn_clk : IN std_logic;
Sim_Zeichen : OUT std_logic;
trn_reset_n : IN std_logic
);
END COMPONENT;
signal DDR_wr_sof : std_logic;
signal DDR_wr_eof : std_logic;
signal DDR_wr_v : std_logic;
signal DDR_wr_FA : std_logic;
signal DDR_wr_Shift : std_logic;
signal DDR_wr_Mask : std_logic_vector(2-1 downto 0);
signal DDR_wr_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full : std_logic;
signal DDR_rdc_sof : std_logic;
signal DDR_rdc_eof : std_logic;
signal DDR_rdc_v : std_logic;
signal DDR_rdc_FA : std_logic;
signal DDR_rdc_Shift : std_logic;
signal DDR_rdc_din : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_rdc_full : std_logic;
signal DDR_FIFO_RdEn : std_logic;
signal DDR_FIFO_Empty : std_logic;
signal DDR_FIFO_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Ready : std_logic;
signal DDR_Blinker : std_logic;
signal user_wr_weA : std_logic_vector(7 downto 0) := (Others =>'0');
signal user_wr_addrA : std_logic_vector(C_PRAM_AWIDTH-1 downto 0) := (Others =>'0');
signal user_wr_dinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0) := (Others =>'0');
signal user_rd_addrB : std_logic_vector(C_PRAM_AWIDTH-1 downto 0) := (Others =>'0');
signal user_rd_doutB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- -----------------------------------------------------------------------
-- FIFO module
-- -----------------------------------------------------------------------
component eb_wrapper_loopback
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(72-1 downto 0);
pfull : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(72-1 downto 0);
pempty : OUT std_logic;
empty : OUT std_logic;
data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : IN std_logic
);
end component;
component eb_wrapper
port (
--FIFO PCIe-->USER
H2B_wr_clk : IN std_logic;
H2B_wr_en : IN std_logic;
H2B_wr_din : IN std_logic_VECTOR(72-1 downto 0);
H2B_wr_pfull : OUT std_logic;
H2B_wr_full : OUT std_logic;
H2B_wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
H2B_rd_clk : IN std_logic;
H2B_rd_en : IN std_logic;
H2B_rd_dout : OUT std_logic_VECTOR(72-1 downto 0);
H2B_rd_pempty : OUT std_logic;
H2B_rd_empty : OUT std_logic;
H2B_rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
H2B_rd_valid : OUT std_logic;
--FIFO USER-->PCIe
B2H_wr_clk : IN std_logic;
B2H_wr_en : IN std_logic;
B2H_wr_din : IN std_logic_VECTOR(72-1 downto 0);
B2H_wr_pfull : OUT std_logic;
B2H_wr_full : OUT std_logic;
B2H_wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
B2H_rd_clk : IN std_logic;
B2H_rd_en : IN std_logic;
B2H_rd_dout : OUT std_logic_VECTOR(72-1 downto 0);
B2H_rd_pempty : OUT std_logic;
B2H_rd_empty : OUT std_logic;
B2H_rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
B2H_rd_valid : OUT std_logic;
--RESET from PCIe
rst : IN std_logic
);
end component;
signal eb_wclk : std_logic;
signal eb_we : std_logic;
signal eb_wsof : std_logic;
signal eb_weof : std_logic;
signal eb_din : std_logic_VECTOR(72-1 downto 0);
signal eb_pfull : std_logic;
signal eb_full : std_logic;
signal eb_rclk : std_logic;
signal eb_re : std_logic;
signal eb_dout : std_logic_VECTOR(72-1 downto 0);
signal eb_pempty : std_logic;
signal eb_empty : std_logic;
signal eb_valid : std_logic;
signal eb_rst : std_logic;
signal eb_data_count : std_logic_vector(C_FIFO_DC_WIDTH downto 0);
signal H2B_wr_data_count : std_logic_vector(C_FIFO_DC_WIDTH downto 0);
signal B2H_rd_data_count : std_logic_vector(C_FIFO_DC_WIDTH downto 0);
signal pio_read_status : std_logic;
signal eb_FIFO_ow : std_logic;
signal eb_FIFO_Status : std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
signal H2B_FIFO_Status : std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
signal B2H_FIFO_Status : std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
signal eb_we_up : std_logic;
signal eb_din_up : std_logic_VECTOR(72-1 downto 0);
signal tab_sel : STD_LOGIC;
signal user_rd_en : std_logic := '0';
signal user_rd_dout : std_logic_VECTOR(72-1 downto 0);
signal user_rd_pempty : std_logic;
signal user_rd_empty : std_logic;
signal user_rd_data_count : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal user_wr_data_count : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal user_wr_en : std_logic := '0';
signal user_wr_din : std_logic_VECTOR(72-1 downto 0) := (Others =>'0');
signal user_wr_pfull : std_logic;
signal user_wr_full : std_logic;
signal user_rd_valid : std_logic;
------------- COMPONENT Declaration: tlpControl ------
--
component tlpControl
port (
-- Test pin, emulating DDR data flow discontinuity
mbuf_UserFull : IN std_logic;
trn_Blinker : OUT std_logic;
--S SIMONE: Wanxau UserLogic Signals, not Used
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_rv : OUT std_logic;
dlm_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_tv : IN std_logic;
dlm_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
Link_Buf_full : IN std_logic;
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Data generator control
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
--S SIMONE: Wanxau UserLogic Signals, not Used
-- Interrupter triggers
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
-- SIMONE Register: PC-->FPGA
reg01_tv : OUT std_logic;
reg01_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_tv : OUT std_logic;
reg02_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_tv : OUT std_logic;
reg03_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_tv : OUT std_logic;
reg04_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_tv : OUT std_logic;
reg05_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_tv : OUT std_logic;
reg06_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_tv : OUT std_logic;
reg07_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_tv : OUT std_logic;
reg08_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_tv : OUT std_logic;
reg09_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_tv : OUT std_logic;
reg10_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_tv : OUT std_logic;
reg11_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_tv : OUT std_logic;
reg12_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_tv : OUT std_logic;
reg13_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_tv : OUT std_logic;
reg14_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: FPGA-->PC
reg01_rv : IN std_logic;
reg01_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_rv : IN std_logic;
reg02_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_rv : IN std_logic;
reg03_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_rv : IN std_logic;
reg04_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_rv : IN std_logic;
reg05_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_rv : IN std_logic;
reg06_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_rv : IN std_logic;
reg07_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_rv : IN std_logic;
reg08_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_rv : IN std_logic;
reg09_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_rv : IN std_logic;
reg10_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_rv : IN std_logic;
reg11_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_rv : IN std_logic;
reg12_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_rv : IN std_logic;
reg13_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_rv : IN std_logic;
reg14_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--SIMONE debug signals
debug_in_1i : OUT std_logic_vector(31 downto 0);
debug_in_2i : OUT std_logic_vector(31 downto 0);
debug_in_3i : OUT std_logic_vector(31 downto 0);
debug_in_4i : OUT std_logic_vector(31 downto 0);
-- Event Buffer FIFO interface
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_re : OUT std_logic;
eb_FIFO_empty : IN std_logic;
eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_data_count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
eb_FIFO_ow : IN std_logic;
pio_reading_status : OUT std_logic;
eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst : OUT std_logic;
H2B_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
B2H_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
-- Debugging signals
DMA_us_Done : OUT std_logic;
DMA_us_Busy : OUT std_logic;
DMA_us_Busy_LED : OUT std_logic;
DMA_ds_Done : OUT std_logic;
DMA_ds_Busy : OUT std_logic;
DMA_ds_Busy_LED : OUT std_logic;
-- DDR control interface
DDR_Ready : IN std_logic;
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
DDR_rdc_sof : OUT std_logic;
DDR_rdc_eof : OUT std_logic;
DDR_rdc_v : OUT std_logic;
DDR_rdc_FA : OUT std_logic;
DDR_rdc_Shift : OUT std_logic;
DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : OUT std_logic;
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Transaction layer interface
trn_lnk_up_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rnp_ok_n : OUT std_logic;
trn_tsrc_dsc_n : OUT std_logic;
trn_tdst_dsc_n : IN std_logic;
trn_tbuf_av : IN std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
trn_terrfwd_n : OUT std_logic;
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_tdst_rdy_n : IN std_logic;
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rerrfwd_n : IN std_logic;
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
cfg_dcommand : IN std_logic_vector(15 downto 0);
pcie_link_width : IN std_logic_vector( 5 downto 0);
localId : IN std_logic_vector(15 downto 0);
cfg_interrupt_n : OUT std_logic;
cfg_interrupt_rdy_n : IN std_logic;
cfg_interrupt_mmenable : IN std_logic_vector(2 downto 0);
cfg_interrupt_msienable : IN std_logic;
cfg_interrupt_di : OUT std_logic_vector(7 downto 0);
cfg_interrupt_do : IN std_logic_vector(7 downto 0);
cfg_interrupt_assert_n : OUT std_logic;
Format_Shower : OUT std_logic;
trn_rbar_hit_n : IN std_logic_vector(6 downto 0);
trn_tsrc_rdy_n : OUT std_logic;
trn_rdst_rdy_n : OUT std_logic;
trn_tsof_n : OUT std_logic;
trn_teof_n : OUT std_logic;
trn_trem_n : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
signal Format_Shower : std_logic;
-- TRN Layer signals
signal trn_terr_drop_n : std_logic;
signal trn_tcfg_gnt_n : std_logic;
signal trn_tstr_n : std_logic;
signal trn_fc_cpld : STD_LOGIC_vector (12-1 downto 0);
signal trn_fc_cplh : STD_LOGIC_vector (8-1 downto 0);
signal trn_fc_npd : STD_LOGIC_vector (12-1 downto 0);
signal trn_fc_nph : STD_LOGIC_vector (8-1 downto 0);
signal trn_fc_pd : STD_LOGIC_vector (12-1 downto 0);
signal trn_fc_ph : STD_LOGIC_vector (8-1 downto 0);
signal trn_fc_sel : STD_LOGIC_vector (3-1 downto 0);
signal cfg_interrupt_msixenable : std_logic;
signal cfg_interrupt_msixfm : std_logic;
signal cfg_dcommand2 : std_logic_vector (16-1 downto 0);
signal trn_tcfg_req_n : std_logic;
signal pl_initial_link_width : STD_LOGIC_vector (3-1 downto 0);
signal pl_lane_reversal_mode : STD_LOGIC_vector (2-1 downto 0);
signal pl_link_gen2_capable : STD_LOGIC;
signal pl_link_partner_gen2_supported : STD_LOGIC;
signal pl_link_upcfg_capable : STD_LOGIC;
signal pl_ltssm_state : STD_LOGIC_vector (6-1 downto 0);
signal pl_received_hot_rst : STD_LOGIC;
signal pl_sel_link_rate : STD_LOGIC;
signal pl_sel_link_width : STD_LOGIC_vector (2-1 downto 0);
signal pl_directed_link_auton : STD_LOGIC;
signal pl_directed_link_change : STD_LOGIC_vector (2-1 downto 0);
signal pl_directed_link_speed : STD_LOGIC;
signal pl_directed_link_width : STD_LOGIC_vector (2-1 downto 0);
signal pl_upstream_prefer_deemph : STD_LOGIC;
signal trn_reset_n_int1 : STD_LOGIC;
signal trn_lnk_up_n_int1 : STD_LOGIC;
signal trn_clk : std_logic;
signal trn_reset_n : std_logic;
signal trn_lnk_up_n : std_logic;
signal trn_td : std_logic_vector(63 downto 0);
signal trn_trem_n : std_logic_vector(7 downto 0);
signal trn_tsof_n : std_logic;
signal trn_teof_n : std_logic;
signal trn_tsrc_rdy_n : std_logic;
signal trn_tdst_rdy_n : std_logic;
signal trn_tdst_dsc_n : std_logic;
signal trn_tsrc_dsc_n : std_logic;
signal trn_terrfwd_n : std_logic;
signal trn_tbuf_av : std_logic_vector(5 downto 0);
signal trn_rd : std_logic_vector(63 downto 0);
signal trn_rrem_n : std_logic_vector(7 downto 0);
signal trn_rsof_n : std_logic;
signal trn_reof_n : std_logic;
signal trn_rsrc_rdy_n : std_logic;
signal trn_rsrc_dsc_n : std_logic;
signal trn_rdst_rdy_n : std_logic;
signal trn_rerrfwd_n : std_logic;
signal trn_rnp_ok_n : std_logic;
signal trn_rbar_hit_n : std_logic_vector(6 downto 0);
signal trn_rfc_nph_av : std_logic_vector(7 downto 0);
signal trn_rfc_npd_av : std_logic_vector(11 downto 0);
signal trn_rfc_ph_av : std_logic_vector(7 downto 0);
signal trn_rfc_pd_av : std_logic_vector(11 downto 0);
signal trn_rfc_cplh_av : std_logic_vector(7 downto 0);
signal trn_rfc_cpld_av : std_logic_vector(11 downto 0);
signal trn_rcpl_streaming_n : std_logic;
signal cfg_do : std_logic_vector(31 downto 0);
signal cfg_rd_wr_done_n : std_logic;
signal cfg_di : std_logic_vector(31 downto 0);
signal cfg_byte_en_n : std_logic_vector(3 downto 0);
signal cfg_dwaddr : std_logic_vector(9 downto 0);
signal cfg_wr_en_n : std_logic;
signal cfg_rd_en_n : std_logic;
signal cfg_err_cor_n : std_logic;
signal cfg_err_ur_n : std_logic;
signal cfg_err_cpl_rdy_n : std_logic;
signal cfg_err_ecrc_n : std_logic;
signal cfg_err_cpl_timeout_n : std_logic;
signal cfg_err_cpl_abort_n : std_logic;
signal cfg_err_cpl_unexpect_n : std_logic;
signal cfg_err_posted_n : std_logic;
signal cfg_err_locked_n : std_logic;
signal cfg_err_tlp_cpl_header : std_logic_vector(47 downto 0);
signal cfg_interrupt_n : std_logic;
signal cfg_interrupt_rdy_n : std_logic;
signal cfg_interrupt_mmenable : std_logic_vector(2 downto 0);
signal cfg_interrupt_msienable : std_logic;
signal cfg_interrupt_di : std_logic_vector(7 downto 0);
signal cfg_interrupt_do : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert_n : std_logic;
signal cfg_turnoff_ok_n : std_logic;
signal cfg_to_turnoff_n : std_logic;
signal cfg_pm_wake_n : std_logic;
signal cfg_pcie_link_state_n : std_logic_vector(2 downto 0);
signal cfg_trn_pending_n : std_logic;
signal cfg_bus_number : std_logic_vector(7 downto 0);
signal cfg_device_number : std_logic_vector(4 downto 0);
signal cfg_function_number : std_logic_vector(2 downto 0);
signal cfg_dsn : std_logic_vector(63 downto 0);
signal cfg_status : std_logic_vector(15 downto 0);
signal cfg_command : std_logic_vector(15 downto 0);
signal cfg_dstatus : std_logic_vector(15 downto 0);
signal cfg_dcommand : std_logic_vector(15 downto 0);
signal cfg_lstatus : std_logic_vector(15 downto 0);
signal cfg_lcommand : std_logic_vector(15 downto 0);
signal fast_train_simulation_only : std_logic;
signal two_plm_auto_config : std_logic_vector(1 downto 0);
signal sys_clk_c : std_logic;
signal sys_reset_n_c : std_logic;
signal reset_n : std_logic;
signal localId : std_logic_vector(15 downto 0);
signal pcie_link_width : std_logic_vector( 5 downto 0);
signal synclk2out : std_logic;
signal Sim_Zeichen : std_logic;
--
signal trn_Blinker : std_logic;
signal DAQ_irq : std_logic := '0';
signal CTL_irq : std_logic := '0';
signal DLM_irq : std_logic := '0';
--S SIMONE: Wanxau UserLogic Signals, not Used
signal protocol_link_act : std_logic_vector(2-1 downto 0) := (OTHERS=>'0');
signal protocol_rst : std_logic;
signal daq_rstop : std_logic;
signal ctl_rv : std_logic;
signal ctl_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal ctl_ttake : std_logic;
signal ctl_tv : std_logic := '0';
signal ctl_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal ctl_tstop : std_logic;
signal ctl_reset : std_logic;
signal ctl_status : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal dlm_tv : std_logic;
signal dlm_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal dlm_rv : std_logic := '0';
signal dlm_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal tab_we : std_logic_vector(2-1 downto 0);
signal tab_wa : std_logic_vector(12-1 downto 0);
signal tab_wd : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dg_running : std_logic := '0';
signal dg_rst : STD_LOGIC;
signal DG_Mask : STD_LOGIC;
--S SIMONE: Wanxau UserLogic Signals, not Used
-- SIMONE Register: PC-->FPGA
signal reg01_tv : std_logic;
signal reg01_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg02_tv : std_logic;
signal reg02_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg03_tv : std_logic;
signal reg03_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg04_tv : std_logic;
signal reg04_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg05_tv : std_logic;
signal reg05_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg06_tv : std_logic;
signal reg06_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg07_tv : std_logic;
signal reg07_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg08_tv : std_logic;
signal reg08_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg09_tv : std_logic;
signal reg09_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg10_tv : std_logic;
signal reg10_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg11_tv : std_logic;
signal reg11_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg12_tv : std_logic;
signal reg12_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg13_tv : std_logic;
signal reg13_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg14_tv : std_logic;
signal reg14_td : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: FPGA-->PC
signal reg01_rv : std_logic := '0';
signal reg01_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg02_rv : std_logic := '0';
signal reg02_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg03_rv : std_logic := '0';
signal reg03_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg04_rv : std_logic := '0';
signal reg04_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg05_rv : std_logic := '0';
signal reg05_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg06_rv : std_logic := '0';
signal reg06_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg07_rv : std_logic := '0';
signal reg07_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg08_rv : std_logic := '0';
signal reg08_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg09_rv : std_logic := '0';
signal reg09_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg10_rv : std_logic := '0';
signal reg10_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg11_rv : std_logic := '0';
signal reg11_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg12_rv : std_logic := '0';
signal reg12_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg13_rv : std_logic := '0';
signal reg13_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal reg14_rv : std_logic := '0';
signal reg14_rd : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0) := (OTHERS=>'0');
signal debug_in_1i : std_logic_vector(31 downto 0);
signal debug_in_2i : std_logic_vector(31 downto 0);
signal debug_in_3i : std_logic_vector(31 downto 0);
signal debug_in_4i : std_logic_vector(31 downto 0);
signal user_rst_o : std_logic;
signal clk_200MHz : std_logic;
signal DMA_Host2Board_Busy : std_logic;
signal DMA_Host2Board_Done : std_logic;
signal DMA_us_Busy : std_logic;
signal DMA_us_Done : std_logic;
signal DMA_ds_Done : std_logic;
signal DMA_ds_Busy : std_logic;
begin
LoopBack_Off_UserLogic: if not USE_LOOPBACK_TEST generate
--S SIMONE: My Custom User Logic!!
pcie_userlogic_00_x0: PCIe_UserLogic_00
port map (
inout_logic_cw_ce => '1',
inout_logic_cw_clk => trn_clk,
user_logic_cw_ce => '1',
user_logic_cw_clk => clk_200MHz,
fifo_rd_count => user_rd_data_count,
fifo_rd_dout => user_rd_dout ,
fifo_rd_empty => user_rd_empty ,
fifo_rd_pempty => user_rd_pempty ,
fifo_wr_full => user_wr_full ,
fifo_wr_pfull => user_wr_pfull ,
fifo_rd_en => user_rd_en ,
fifo_wr_din => user_wr_din ,
fifo_wr_en => user_wr_en ,
fifo_rd_valid => user_rd_valid ,
fifo_wr_count => user_wr_data_count,
bram_rd_addr => user_rd_addrB ,
bram_wr_addr => user_wr_addrA ,
bram_wr_din => user_wr_dinA ,
bram_wr_en => user_wr_weA ,
bram_rd_dout => user_rd_doutB ,
DMA_Host2Board_Busy => DMA_Host2Board_Busy,
DMA_Host2Board_Done => DMA_Host2Board_Done,
reg01_td => reg01_td,
reg01_tv => reg01_tv,
reg02_td => reg02_td,
reg02_tv => reg02_tv,
reg03_td => reg03_td,
reg03_tv => reg03_tv,
reg04_td => reg04_td,
reg04_tv => reg04_tv,
reg05_td => reg05_td,
reg05_tv => reg05_tv,
reg06_td => reg06_td,
reg06_tv => reg06_tv,
reg07_td => reg07_td,
reg07_tv => reg07_tv,
reg08_td => reg08_td,
reg08_tv => reg08_tv,
reg09_td => reg09_td,
reg09_tv => reg09_tv,
reg10_td => reg10_td,
reg10_tv => reg10_tv,
reg11_td => reg11_td,
reg11_tv => reg11_tv,
reg12_td => reg12_td,
reg12_tv => reg12_tv,
reg13_td => reg13_td,
reg13_tv => reg13_tv,
reg14_td => reg14_td,
reg14_tv => reg14_tv,
reg01_rd => reg01_rd,
reg01_rv => reg01_rv,
reg02_rd => reg02_rd,
reg02_rv => reg02_rv,
reg03_rd => reg03_rd,
reg03_rv => reg03_rv,
reg04_rd => reg04_rd,
reg04_rv => reg04_rv,
reg05_rd => reg05_rd,
reg05_rv => reg05_rv,
reg06_rd => reg06_rd,
reg06_rv => reg06_rv,
reg07_rd => reg07_rd,
reg07_rv => reg07_rv,
reg08_rd => reg08_rd,
reg08_rv => reg08_rv,
reg09_rd => reg09_rd,
reg09_rv => reg09_rv,
reg10_rd => reg10_rd,
reg10_rv => reg10_rv,
reg11_rd => reg11_rd,
reg11_rv => reg11_rv,
reg12_rd => reg12_rd,
reg12_rv => reg12_rv,
reg13_rd => reg13_rd,
reg13_rv => reg13_rv,
reg14_rd => reg14_rd,
reg14_rv => reg14_rv,
user_int_1o => CTL_irq,
user_int_2o => DAQ_irq,
user_int_3o => DLM_irq,
debug_in_1i => debug_in_1i,
debug_in_2i => debug_in_2i,
debug_in_3i => debug_in_3i,
debug_in_4i => debug_in_4i,
rst_i => trn_reset_n,
rst_o => user_rst_o
);
end generate;
DMA_Host2Board_Busy <= '0'; --DMA_ds_Busy;
DMA_Host2Board_Done <= DMA_ds_Done;
-- LEDs_IO_pin(5) <= DMA_ds_Done;
-- LEDs_IO_pin(7) <= DMA_us_Done;
sys_reset_n_ibuf : IBUF
port map (
O => sys_reset_n_c,
I => sys_reset_n
);
refclk_ibuf : IBUFDS_GTXE1
port map (
O => sys_clk_c,
ODIV2 => open,
I => sys_clk_p,
IB => sys_clk_n,
CEB => '0'
);
userclk_ibuf : IBUFDS
port map (
O => clk_200MHz,
I => userclk_200MHz_p,
IB => userclk_200MHz_n
);
cfg_err_cor_n <= '1';
cfg_err_ur_n <= '1';
cfg_err_ecrc_n <= '1';
cfg_err_cpl_timeout_n <= '1';
cfg_err_cpl_abort_n <= '1';
cfg_err_cpl_unexpect_n <= '1';
cfg_err_posted_n <= '0';
cfg_err_locked_n <= '0';
cfg_err_tlp_cpl_header <= (OTHERS=>'0');
cfg_trn_pending_n <= '1';
cfg_pm_wake_n <= '1';
--
trn_fc_sel <= (OTHERS=>'0');
pl_directed_link_auton <= '0';
pl_directed_link_change <= (OTHERS=>'0');
pl_directed_link_speed <= '0';
pl_directed_link_width <= (OTHERS=>'0');
pl_upstream_prefer_deemph <= '0';
trn_tcfg_gnt_n <= '0';
trn_tstr_n <= '0'; -- '1';
--
trn_tdst_dsc_n <= '1';
--
cfg_di <= (OTHERS=>'0');
cfg_dwaddr <= (OTHERS=>'1');
cfg_byte_en_n <= (OTHERS=>'1');
cfg_wr_en_n <= '1';
cfg_rd_en_n <= '1';
cfg_dsn <= X"00000001" & X"01" & X"000A35"; -- //this is taken from GUI -
cfg_turnoff_ok_n <= '0';
localId <= cfg_bus_number & cfg_device_number & cfg_function_number;
pcie_link_width <= cfg_lstatus(9 downto 4);
trn_lnk_up_n_int_i: FDCP
generic map (
INIT => '1'
)
port map (
Q => trn_lnk_up_n,
D => trn_lnk_up_n_int1,
C => trn_clk,
CLR => '0',
PRE => '0'
);
trn_reset_n_i: FDCP
generic map (
INIT => '1'
)
port map (
Q => trn_reset_n,
D => trn_reset_n_int1,
C => trn_clk,
CLR => '0',
PRE => '0'
);
-- --------------------------------------------------------------
-- --------------------------------------------------------------
make4Lanes: if pcieLanes = 4 generate
--S pcieCore : v6_pcie_v1_7_x1
-- pcieCore : v6_pcie_v1_7_x4
pcieCore_i : pcieCore
generic map (
PL_FAST_TRAIN => "FALSE"
)
port map (
---------------------------------------------------------
-- 1. PCI Express (pci_exp) Interface
---------------------------------------------------------
-- Tx
pci_exp_txp => pci_exp_txp ,
pci_exp_txn => pci_exp_txn ,
-- Rx
pci_exp_rxp => pci_exp_rxp ,
pci_exp_rxn => pci_exp_rxn ,
---------------------------------------------------------
-- 2. Transaction (TRN) Interface
---------------------------------------------------------
-- Common
user_clk_out => trn_clk ,
user_reset_out => trn_reset_n_int1 ,
user_lnk_up => trn_lnk_up_n_int1 ,
--Polarity Need to change
-- Tx
trn_buf_av => trn_tbuf_av ,
trn_cfg_req => trn_tcfg_req_n ,
trn_err_drop => trn_terr_drop_n ,
s_axis_tx_tready => trn_tdst_rdy_n ,
s_axis_tx_tdata => trn_td ,
s_axis_tx_tkeep => trn_trem_n(0) ,
-- trn_tsof_n => trn_tsof_n ,
s_axis_tx_tlast => trn_teof_n ,
s_axis_tx_tvalid => trn_tsrc_rdy_n ,
s_axis_tx_tuser(3) => trn_tsrc_dsc_n ,
s_axis_tx_tuser(1) => trn_terrfwd_n ,
trn_cfg_gnt => trn_tcfg_gnt_n ,
s_axis_tx_tuser(2) => trn_tstr_n ,
-- Rx
trn_rd => trn_rd ,
trn_rrem_n => trn_rrem_n(0) ,
trn_rsof_n => trn_rsof_n ,
trn_reof_n => trn_reof_n ,
trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
trn_rerrfwd_n => trn_rerrfwd_n ,
trn_rbar_hit_n => trn_rbar_hit_n ,
trn_rdst_rdy_n => trn_rdst_rdy_n ,
trn_rnp_ok_n => trn_rnp_ok_n ,
-- Flow Control
fc_cpld => trn_fc_cpld ,
fc_cplh => trn_fc_cplh ,
fc_npd => trn_fc_npd ,
fc_nph => trn_fc_nph ,
fc_pd => trn_fc_pd ,
fc_ph => trn_fc_ph ,
fc_sel => trn_fc_sel ,
---------------------------------------------------------
-- 3. Configuration (CFG) Interface
---------------------------------------------------------
cfg_do => cfg_do ,
cfg_rd_wr_done_n => cfg_rd_wr_done_n ,
cfg_di => cfg_di ,
cfg_byte_en_n => cfg_byte_en_n ,
cfg_dwaddr => cfg_dwaddr ,
cfg_wr_en_n => cfg_wr_en_n ,
cfg_rd_en_n => cfg_rd_en_n ,
cfg_err_cor_n => cfg_err_cor_n ,
cfg_err_ur_n => cfg_err_ur_n ,
cfg_err_ecrc_n => cfg_err_ecrc_n ,
cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n ,
cfg_err_cpl_abort_n => cfg_err_cpl_abort_n ,
cfg_err_cpl_unexpect_n => cfg_err_cpl_unexpect_n ,
cfg_err_posted_n => cfg_err_posted_n ,
cfg_err_locked_n => cfg_err_locked_n ,
cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header ,
cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n ,
cfg_interrupt_n => cfg_interrupt_n ,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
cfg_interrupt_assert_n => cfg_interrupt_assert_n ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_msixenable => cfg_interrupt_msixenable ,
cfg_interrupt_msixfm => cfg_interrupt_msixfm ,
cfg_turnoff_ok_n => cfg_turnoff_ok_n ,
cfg_to_turnoff_n => cfg_to_turnoff_n ,
cfg_trn_pending_n => cfg_trn_pending_n ,
cfg_pm_wake_n => cfg_pm_wake_n ,
cfg_bus_number => cfg_bus_number ,
cfg_device_number => cfg_device_number ,
cfg_function_number => cfg_function_number ,
cfg_status => cfg_status ,
cfg_command => cfg_command ,
cfg_dstatus => cfg_dstatus ,
cfg_dcommand => cfg_dcommand ,
cfg_lstatus => cfg_lstatus ,
cfg_lcommand => cfg_lcommand ,
cfg_dcommand2 => cfg_dcommand2 ,
cfg_pcie_link_state_n => cfg_pcie_link_state_n ,
cfg_dsn => cfg_dsn ,
---------------------------------------------------------
-- 4. Physical Layer Control and Status (PL) Interface
---------------------------------------------------------
pl_initial_link_width => pl_initial_link_width ,
pl_lane_reversal_mode => pl_lane_reversal_mode ,
pl_link_gen2_capable => pl_link_gen2_capable ,
pl_link_partner_gen2_supported => pl_link_partner_gen2_supported ,
pl_link_upcfg_capable => pl_link_upcfg_capable ,
pl_ltssm_state => pl_ltssm_state ,
pl_received_hot_rst => pl_received_hot_rst ,
pl_sel_link_rate => pl_sel_link_rate ,
pl_sel_link_width => pl_sel_link_width ,
pl_directed_link_auton => pl_directed_link_auton ,
pl_directed_link_change => pl_directed_link_change ,
pl_directed_link_speed => pl_directed_link_speed ,
pl_directed_link_width => pl_directed_link_width ,
pl_upstream_prefer_deemph => pl_upstream_prefer_deemph ,
---------------------------------------------------------
-- 5. System (SYS) Interface
---------------------------------------------------------
sys_clk => sys_clk_c ,
sys_rst_n => sys_reset_n_c
);
end generate;
-- ---------------------------------------------------------------
-- tlp control module
-- ---------------------------------------------------------------
trn_rrem_n(7 downto 1) <= X"0" & trn_rrem_n(0) & trn_rrem_n(0) & trn_rrem_n(0);
theTlpControl:
tlpControl
port map (
mbuf_UserFull => '0' ,
trn_Blinker => trn_Blinker ,
-- Interrupter triggers
DAQ_irq => DAQ_irq , -- IN std_logic;
CTL_irq => CTL_irq , -- IN std_logic;
DLM_irq => DLM_irq , -- IN std_logic;
--S SIMONE: Wanxau UserLogic Signals, not Used
-- DCB protocol interface
protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
protocol_rst => protocol_rst , -- OUT std_logic;
Link_Buf_Full => daq_rstop , -- IN std_logic;
-- Fabric side: CTL Rx
ctl_rv => ctl_rv , -- OUT std_logic;
ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: CTL Tx
ctl_ttake => ctl_ttake , -- OUT std_logic;
ctl_tv => ctl_tv , -- IN std_logic;
ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop => ctl_tstop , -- OUT std_logic;
ctl_reset => ctl_reset , -- OUT std_logic;
ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_rv => dlm_rv , -- OUT std_logic;
dlm_rd => dlm_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_tv => dlm_tv , -- IN std_logic;
dlm_td => dlm_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DG_is_Running => dg_running , -- IN std_logic;
DG_Reset => dg_rst , -- OUT STD_LOGIC;
DG_Mask => dg_mask , -- OUT STD_LOGIC
--S SIMONE: Wanxau UserLogic Signals, not Used
-- SIMONE Register: PC-->FPGA
reg01_tv => reg01_tv,
reg01_td => reg01_td,
reg02_tv => reg02_tv,
reg02_td => reg02_td,
reg03_tv => reg03_tv,
reg03_td => reg03_td,
reg04_tv => reg04_tv,
reg04_td => reg04_td,
reg05_tv => reg05_tv,
reg05_td => reg05_td,
reg06_tv => reg06_tv,
reg06_td => reg06_td,
reg07_tv => reg07_tv,
reg07_td => reg07_td,
reg08_tv => reg08_tv,
reg08_td => reg08_td,
reg09_tv => reg09_tv,
reg09_td => reg09_td,
reg10_tv => reg10_tv,
reg10_td => reg10_td,
reg11_tv => reg11_tv,
reg11_td => reg11_td,
reg12_tv => reg12_tv,
reg12_td => reg12_td,
reg13_tv => reg13_tv,
reg13_td => reg13_td,
reg14_tv => reg14_tv,
reg14_td => reg14_td,
-- SIMONE Register: FPGA-->PC
reg01_rv => reg01_rv,
reg01_rd => reg01_rd,
reg02_rv => reg02_rv,
reg02_rd => reg02_rd,
reg03_rv => reg03_rv,
reg03_rd => reg03_rd,
reg04_rv => reg04_rv,
reg04_rd => reg04_rd,
reg05_rv => reg05_rv,
reg05_rd => reg05_rd,
reg06_rv => reg06_rv,
reg06_rd => reg06_rd,
reg07_rv => reg07_rv,
reg07_rd => reg07_rd,
reg08_rv => reg08_rv,
reg08_rd => reg08_rd,
reg09_rv => reg09_rv,
reg09_rd => reg09_rd,
reg10_rv => reg10_rv,
reg10_rd => reg10_rd,
reg11_rv => reg11_rv,
reg11_rd => reg11_rd,
reg12_rv => reg12_rv,
reg12_rd => reg12_rd,
reg13_rv => reg13_rv,
reg13_rd => reg13_rd,
reg14_rv => reg14_rv,
reg14_rd => reg14_rd,
-- SIMONE debug signals
debug_in_1i => debug_in_1i,
debug_in_2i => debug_in_2i,
debug_in_3i => debug_in_3i,
debug_in_4i => debug_in_4i,
-- Event Buffer FIFO interface
eb_FIFO_we => eb_we , -- OUT std_logic;
eb_FIFO_wsof => eb_wsof , -- OUT std_logic;
eb_FIFO_weof => eb_weof , -- OUT std_logic;
eb_FIFO_din => eb_din(C_DBUS_WIDTH-1 downto 0) , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_re => eb_re , -- OUT std_logic;
eb_FIFO_empty => eb_empty , -- IN std_logic;
eb_FIFO_qout => eb_dout(C_DBUS_WIDTH-1 downto 0) , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_data_count => eb_data_count , -- IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
eb_FIFO_ow => eb_FIFO_ow , -- IN std_logic;
pio_reading_status => pio_reading_status , -- OUT std_logic;
eb_FIFO_Status => eb_FIFO_Status , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst => eb_rst , -- OUT std_logic;
H2B_FIFO_Status => H2B_FIFO_Status ,
B2H_FIFO_Status => B2H_FIFO_Status ,
-- Debugging signals
DMA_us_Done => DMA_us_Done , -- OUT std_logic;
DMA_us_Busy => DMA_us_Busy , -- OUT std_logic;
-- DMA_us_Busy_LED => LEDs_IO_pin(6) , -- OUT std_logic;
DMA_ds_Done => DMA_ds_Done , -- OUT std_logic;
DMA_ds_Busy => DMA_ds_Busy , -- OUT std_logic;
-- DMA_ds_Busy_LED => LEDs_IO_pin(4) , -- OUT std_logic;
-------------------
-- DDR Interface
DDR_Ready => DDR_Ready , -- IN std_logic;
DDR_wr_sof => DDR_wr_sof , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof , -- OUT std_logic;
DDR_wr_v => DDR_wr_v , -- OUT std_logic;
DDR_wr_FA => DDR_wr_FA , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_FA => DDR_rdc_FA , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-------------------
-- Transaction Interface
trn_lnk_up_n => trn_lnk_up_n ,
trn_rsrc_dsc_n => trn_rsrc_dsc_n ,
trn_rnp_ok_n => trn_rnp_ok_n ,
trn_tsrc_dsc_n => trn_tsrc_dsc_n ,
trn_tdst_dsc_n => trn_tdst_dsc_n ,
trn_tbuf_av => trn_tbuf_av ,
trn_terrfwd_n => trn_terrfwd_n ,
trn_clk => trn_clk ,
trn_reset_n => trn_reset_n ,
trn_rsrc_rdy_n => trn_rsrc_rdy_n ,
trn_tdst_rdy_n => trn_tdst_rdy_n ,
trn_rsof_n => trn_rsof_n ,
trn_reof_n => trn_reof_n ,
trn_rerrfwd_n => trn_rerrfwd_n ,
trn_rrem_n => trn_rrem_n ,
trn_rd => trn_rd ,
cfg_interrupt_n => cfg_interrupt_n ,
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n ,
cfg_interrupt_mmenable => cfg_interrupt_mmenable ,
cfg_interrupt_msienable => cfg_interrupt_msienable ,
cfg_interrupt_di => cfg_interrupt_di ,
cfg_interrupt_do => cfg_interrupt_do ,
cfg_interrupt_assert_n => cfg_interrupt_assert_n ,
trn_rbar_hit_n => trn_rbar_hit_n ,
trn_tsrc_rdy_n => trn_tsrc_rdy_n ,
trn_rdst_rdy_n => trn_rdst_rdy_n ,
trn_tsof_n => trn_tsof_n ,
trn_teof_n => trn_teof_n ,
trn_trem_n => trn_trem_n ,
trn_td => trn_td ,
Format_Shower => Format_Shower ,
cfg_dcommand => cfg_dcommand ,
pcie_link_width => pcie_link_width ,
localId => localId
);
-- -----------------------------------------------------------------------
-- DDR SDRAM: control module USER LOGIC (2 BRAM Module:
-- -----------------------------------------------------------------------
LoopBack_BRAM_Off: if not USE_LOOPBACK_TEST generate
DDRs_ctrl_module:
bram_DDRs_Control
GENERIC MAP (
C_ASYNFIFO_WIDTH => 72 ,
P_SIMULATION => FALSE
)
PORT MAP(
user_wr_weA => user_wr_weA ,
user_wr_addrA => user_wr_addrA ,
user_wr_dinA => user_wr_dinA ,
user_rd_addrB => user_rd_addrB ,
user_rd_doutB => user_rd_doutB ,
user_rd_clk => clk_200MHz ,
user_wr_clk => clk_200MHz ,
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_FA => DDR_wr_FA , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_FA => DDR_rdc_FA , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready , -- OUT std_logic;
DDR_Blinker => DDR_Blinker , -- OUT std_logic;
mem_clk => trn_clk , -- IN
trn_clk => trn_clk , -- IN std_logic;
Sim_Zeichen => Sim_Zeichen , -- OUT std_logic;
trn_reset_n => trn_reset_n -- IN std_logic
);
end generate;
LoopBack_BRAM_On: if USE_LOOPBACK_TEST generate
DDRs_ctrl_module:
bram_DDRs_Control_loopback
GENERIC MAP (
C_ASYNFIFO_WIDTH => 72 ,
P_SIMULATION => FALSE
)
PORT MAP(
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
DDR_wr_sof => DDR_wr_sof , -- IN std_logic;
DDR_wr_eof => DDR_wr_eof , -- IN std_logic;
DDR_wr_v => DDR_wr_v , -- IN std_logic;
DDR_wr_FA => DDR_wr_FA , -- IN std_logic;
DDR_wr_Shift => DDR_wr_Shift , -- IN std_logic;
DDR_wr_Mask => DDR_wr_Mask , -- IN std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- OUT std_logic;
DDR_rdc_sof => DDR_rdc_sof , -- IN std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- IN std_logic;
DDR_rdc_v => DDR_rdc_v , -- IN std_logic;
DDR_rdc_FA => DDR_rdc_FA , -- IN std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- IN std_logic;
DDR_rdc_din => DDR_rdc_din , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- OUT std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- IN std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- OUT std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready => DDR_Ready , -- OUT std_logic;
DDR_Blinker => DDR_Blinker , -- OUT std_logic;
mem_clk => trn_clk , -- IN
trn_clk => trn_clk , -- IN std_logic;
Sim_Zeichen => Sim_Zeichen , -- OUT std_logic;
trn_reset_n => trn_reset_n -- IN std_logic
);
end generate;
LEDs_IO_pin(0) <= trn_reset_n xor Format_Shower;
LEDs_IO_pin(1) <= trn_lnk_up_n ;
LEDs_IO_pin(2) <= Format_Shower ;
LEDs_IO_pin(3) <= trn_Blinker ;
------------------------ -----------------------
-- Event Buffer wrapper (FIFO Module: H2B & B2H)
------------------------ -----------------------
LoopBack_FIFO_Off: if not USE_LOOPBACK_TEST generate
queue_buffer0:
eb_wrapper
port map (
H2B_wr_clk => trn_clk ,
H2B_wr_en => eb_we ,
H2B_wr_din => eb_din ,
H2B_wr_pfull => eb_pfull ,
H2B_wr_full => eb_full ,
H2B_wr_data_count => H2B_wr_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
H2B_rd_clk => clk_200MHz ,
H2B_rd_en => user_rd_en ,
H2B_rd_dout => user_rd_dout ,
H2B_rd_pempty => user_rd_pempty ,
H2B_rd_empty => user_rd_empty ,
H2B_rd_valid => user_rd_valid ,
H2B_rd_data_count => user_rd_data_count ,
B2H_wr_clk => clk_200MHz ,
B2H_wr_en => user_wr_en ,
B2H_wr_din => user_wr_din ,
B2H_wr_pfull => user_wr_pfull ,
B2H_wr_full => user_wr_full ,
B2H_wr_data_count => user_wr_data_count ,
B2H_rd_clk => trn_clk ,
B2H_rd_en => eb_re ,
B2H_rd_dout => eb_dout ,
B2H_rd_pempty => eb_pempty ,
B2H_rd_empty => eb_empty ,
B2H_rd_valid => eb_valid ,
B2H_rd_data_count => B2H_rd_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
rst => eb_rst
);
--- 64 bits to 32 bits transformation ( --> Count * 2)---
B2H_rd_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
<= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
B2H_rd_data_count(0) <= '0';
H2B_wr_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
<= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
H2B_wr_data_count(0) <= '0';
--- Hybrid FIFO Signal used by PCIe interface and Linux Driver
eb_FIFO_ow <= eb_we_up and eb_full;
fifo_reset_done <= not eb_rst;
eb_din(72-1 downto C_DBUS_WIDTH) <= (OTHERS=>'0');
eb_data_count <= B2H_rd_data_count;
--- Hybrid FIFO Status used by PCIe interface and Linux Driver ---
--- read: status ; write: reset H2B and B2H FIFO
eb_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
<= (OTHERS=>'0');
eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
<= B2H_rd_data_count(C_FIFO_DC_WIDTH downto 1);
eb_FIFO_Status(2) <= '0';
eb_FIFO_Status(1) <= eb_pfull;
eb_FIFO_Status(0) <= eb_empty and fifo_reset_done;
--- Host2Board FIFO status used by user ---
--- read: H2B status ; write: nothing
H2B_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
<= (OTHERS=>'0');
H2B_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
<= H2B_wr_data_count(C_FIFO_DC_WIDTH downto 1);
H2B_FIFO_Status(2) <= '0';
H2B_FIFO_Status(1) <= eb_pfull;
H2B_FIFO_Status(0) <= eb_full and fifo_reset_done;
--- Board2Host FIFO status used by user ---
--- read: B2H status ; write: nothing
B2H_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
<= (OTHERS=>'0');
B2H_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
<= B2H_rd_data_count(C_FIFO_DC_WIDTH downto 1);
B2H_FIFO_Status(2) <= eb_valid;
B2H_FIFO_Status(1) <= eb_pempty;
B2H_FIFO_Status(0) <= eb_empty and fifo_reset_done;
end generate;
LoopBack_FIFO_On: if USE_LOOPBACK_TEST generate
queue_buffer0:
eb_wrapper_loopback
port map (
wr_clk => trn_clk , -- eb_wclk ,
wr_en => eb_we ,
din => eb_din ,
pfull => eb_pfull ,
full => eb_full ,
rd_clk => trn_clk , -- eb_rclk ,
rd_en => eb_re ,
dout => eb_dout ,
pempty => eb_pempty ,
empty => eb_empty ,
data_count => eb_data_count(C_EMU_FIFO_DC_WIDTH-1+1 downto 1) ,
rst => eb_rst
);
eb_data_count(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1)
<= C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_EMU_FIFO_DC_WIDTH+1);
eb_data_count(0)<= '0';
fifo_reset_done <= not eb_rst;
eb_FIFO_ow <= eb_we_up and eb_full;
eb_din(72-1 downto C_DBUS_WIDTH) <= (OTHERS=>'0');
eb_FIFO_Status(C_DBUS_WIDTH-1 downto C_FIFO_DC_WIDTH+3)
<= (OTHERS=>'0');
eb_FIFO_Status(C_FIFO_DC_WIDTH+2 downto 3)
<= eb_data_count(C_FIFO_DC_WIDTH downto 1);
eb_FIFO_Status(2) <= '0';
eb_FIFO_Status(1) <= eb_pfull;
eb_FIFO_Status(0) <= eb_empty and fifo_reset_done;
H2B_FIFO_Status <= (OTHERS=>'0');
H2B_FIFO_Status <= (OTHERS=>'0');
end generate;
end Behavioral;
| gpl-2.0 | b3d5112becc7d147f305aa7c224763e6 | 0.417136 | 3.732507 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Filter_Top_Level.vhd | 1 | 8,396 | ---------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:51:05 05/05/2015
-- Design Name:
-- Module Name: Filter_Top_Level - RTL
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Filter_Top_Level is
Port(slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
CLK_48 : in std_logic;
RST : in std_logic;
SAMPLE_TRIG : in std_logic;
sample_trigger_en : in std_logic;
HP_SW : in std_logic;
BP_SW : in std_logic;
LP_SW : in std_logic;
AUDIO_IN_L : in std_logic_vector(23 downto 0);
AUDIO_IN_R : in std_logic_vector(23 downto 0);
AUDIO_OUT_L : out std_logic_vector(23 downto 0);
AUDIO_OUT_R : out std_logic_vector(23 downto 0);
FILTER_DONE : out std_logic
-- clk : in STD_LOGIC;
-- rst : in STD_LOGIC;
-- sample_trig : in STD_LOGIC;
-- Audio_in : in STD_LOGIC_VECTOR (23 downto 0);
-- filter_done : in STD_LOGIC;
-- Audio_out : in STD_LOGIC_VECTOR (23 downto 0)
);
end Filter_Top_Level;
architecture RTL of Filter_Top_Level is
Component IIR_Biquad_II_v3 is
Port(
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR(23 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR(23 downto 0)
);
end Component;
signal IIR_LP_Done_R, IIR_LP_Done_L, IIR_BP_Done_R, IIR_BP_Done_L, IIR_HP_Done_R, IIR_HP_Done_L : std_logic;
signal AUDIO_OUT_TRUNC_L, AUDIO_OUT_TRUNC_R, IIR_LP_Y_Out_R, IIR_LP_Y_Out_L, IIR_BP_Y_Out_R, IIR_BP_Y_Out_L, IIR_HP_Y_Out_R, IIR_HP_Y_Out_L : std_logic_vector(23 downto 0);
signal sample_trigger_safe : STD_LOGIC := '0';
signal val : std_logic_vector(2 downto 0);
begin
sample_trigger_safe <= SAMPLE_TRIG or (not sample_trigger_en);
val <= HP_SW & BP_SW & LP_SW;
--USER logic implementation added here
---- connect all the "filter done" with an AND gate to the user_logic top level entity.
FILTER_DONE <= IIR_LP_Done_R and IIR_LP_Done_L and IIR_BP_Done_R and IIR_BP_Done_L and IIR_HP_Done_R and IIR_HP_Done_L;
AUDIO_OUT_L <= AUDIO_OUT_TRUNC_L; -- & X"00";
AUDIO_OUT_R <= AUDIO_OUT_TRUNC_R; -- & X"00";
---this process controls each individual filter and the final output of the filter.
MUX_filters: process(IIR_BP_Y_Out_L, IIR_BP_Y_Out_R, IIR_HP_Y_Out_L, IIR_HP_Y_Out_R, IIR_LP_Y_Out_L, IIR_LP_Y_Out_R, val, RST)
begin
if rst = '1' then
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
else
case VAL is
when "000" =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when "001" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R;
when "010" =>
AUDIO_OUT_TRUNC_L <= IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_BP_Y_Out_R;
when "011" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R;
when "100" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R;
when "101" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_HP_Y_Out_R;
when "110" =>
AUDIO_OUT_TRUNC_L <= IIR_HP_Y_Out_L + IIR_BP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_HP_Y_Out_R + IIR_BP_Y_Out_R;
when "111" =>
AUDIO_OUT_TRUNC_L <= IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
when others =>
AUDIO_OUT_TRUNC_L <= (others => '0'); --IIR_LP_Y_Out_L + IIR_BP_Y_Out_L + IIR_HP_Y_Out_L;
AUDIO_OUT_TRUNC_R <= (others => '0'); --IIR_LP_Y_Out_R + IIR_BP_Y_Out_R + IIR_HP_Y_Out_R;
end case;
end if;
end process;
IIR_LP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0),
filter_done => IIR_LP_Done_R,
Y_out => IIR_LP_Y_Out_R
);
IIR_LP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg0,
Coef_b1 => slv_reg1,
Coef_b2 => slv_reg2,
Coef_a1 => slv_reg3,
Coef_a2 => slv_reg4,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_LP_Done_L,
Y_out => IIR_LP_Y_Out_L
);
IIR_BP_R : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_BP_Done_R,
Y_out => IIR_BP_Y_Out_R
);
IIR_BP_L : IIR_Biquad_II_v3 --(20 - 20000)
Port map(
Coef_b0 => slv_reg5,
Coef_b1 => slv_reg6,
Coef_b2 => slv_reg7,
Coef_a1 => slv_reg8,
Coef_a2 => slv_reg9,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_BP_Done_L,
Y_out => IIR_BP_Y_Out_L
);
IIR_HP_R : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_R(23 downto 0), --X_in_truncated_R,
filter_done => IIR_HP_Done_R,
Y_out => IIR_HP_Y_Out_R
);
IIR_HP_L : IIR_Biquad_II_v3
Port map(
Coef_b0 => slv_reg10,
Coef_b1 => slv_reg11,
Coef_b2 => slv_reg12,
Coef_a1 => slv_reg13,
Coef_a2 => slv_reg14,
clk => CLK_48,
rst => rst,
sample_trig => sample_trigger_safe, --Sample_IIR,
X_in => AUDIO_IN_L(23 downto 0), --X_in_truncated_L,
filter_done => IIR_HP_Done_L,
Y_out => IIR_HP_Y_Out_L
);
end RTL;
| mit | 5d621f022aaade23b4a5d4a98059b485 | 0.544664 | 2.586568 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/abandoned_code/Rueckfallposition_19_12_2012/TEST2_SRAM_25MHZ_255_BYTE/SRAM_25MHZ_255_BYTE_alt.vhd | 4 | 14,494 | -- SRAM_25MHZ_255_BYTE
-- beschreibt/liest den SRAM des Spartan 3
-- Ersteller: Martin Harndt
-- Erstellt: 30.11.2012
-- Bearbeiter: mharndt
-- Geaendert: 12.12.2012
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SRAM_25MHZ_255_BYTE is
Port ( GO : in std_logic;
COUNT_ADR_OUT : out std_logic_vector(18 downto 0); --Ausgabe Adresse, 19 Byte
COUNT_DAT_OUT : inout std_logic_vector(15 downto 0); --Ausgabe gespeicherte Daten, 16 Byte
DISPL_ADR : in std_logic; -- umschalten zwischen aktuellen Zustand und Adresse
DISPL_DAT : in std_logic; -- umschalten zwischen Folgeszustand und Daten
WE : out std_logic; -- Write Enable
OE : out std_logic; -- Output Enable
CE1 : out std_logic; -- Chip Enable
UB1 : out std_logic; -- Upper Byte Enable
LB1 : out std_logic; -- Lower Byte Enable
STOP : out std_logic; -- zum Anzeigen von STOP
PLUS : in std_logic; -- Adresszähler +1
MINUS : in std_logic; -- Adresszähler -1
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE : in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end SRAM_25MHZ_255_BYTE;
architecture Behavioral of SRAM_25MHZ_255_BYTE is
type TYPE_STATE is
(ST_RAM_00, --Zustaende
ST_RAM_01,
ST_RAM_02,
ST_RAM_03,
ST_RAM_04,
ST_RAM_05,
ST_RAM_06,
ST_RAM_07,
ST_RAM_08,
ST_RAM_09);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal GO_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal PLUS_S : std_logic; --Eingangsvariable, Zwischengespeichert im Eingangsregister
signal MINUS_S : std_logic; --Eingangsvariable, --Zwischengespeichert im Eingangsregister
signal COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, Vektor, 19 bit
signal n_COUNT_ADR : std_logic_vector(18 downto 0); --Adresszaehler, neuer Wert, Vektor, 19 bit
signal COUNT_ADR_M : std_logic_vector(18 downto 0); --Adresszaehler, Ausgang Master, Vektor, 19 bit
signal COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, Vektor, 15 bit
signal n_COUNT_DAT : std_logic_vector(15 downto 0); --Datenzaehler, neuer Wert, Vektor, 15 bit
signal COUNT_DAT_M : std_logic_vector(15 downto 0); --Datenzaehler, Ausgang Master, Vektor, 15 bit
signal DISPL_STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal DISPL_STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal WRITE :std_logic; -- Schreib-Anzeiger (Write=1)
signal WRITE_REG : std_logic; --Schreibanzeiger (1=schreiben)
signal WRITE_BUF : std_logic; --Schreibanzeiger_Slave
signal COUNT_DAT_OUT_INPUT : std_logic_vector(15 downto 0); --Eingangsvariable, Zwischengespeichert Eingangsregister, 16 bit
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraiable, Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (GO, GO_S, not_CLK_IO, PLUS, PLUS_S, MINUS, MINUS_S, COUNT_DAT_OUT) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then GO_S <= GO;
PLUS_S <= PLUS;
MINUS_S <= MINUS;
if (WRITE = '0') then
COUNT_DAT_OUT_INPUT <= COUNT_DAT_OUT;
end if;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_RAM_00;
WRITE_REG <= '0';
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_ADR_M <= n_COUNT_ADR;
COUNT_DAT_M <= n_COUNT_DAT;
WRITE_REG <= WRITE_BUF;
else SV_M <= SV_M;
COUNT_ADR_M <= COUNT_ADR_M;
COUNT_DAT_M <= COUNT_DAT_M;
WRITE_REG <= WRITE_REG;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_RAM_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT_ADR <= COUNT_ADR_M;
COUNT_DAT <= COUNT_DAT_M;
end if;
end if;
end process;
IL_OL_PROC: process (GO_S, SV, COUNT_ADR, COUNT_DAT, PLUS_S, MINUS_S)
begin
UB1 <= '0'; --Upper Byte Ein (0=Ein 1=Aus)
LB1 <= '0'; --Lower Byte Ein (0=Ein 1=Aus)
case SV is
when ST_RAM_00 =>
if (GO_S = '1')
then
-- RAM01
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus (0=Ein 1=Aus) 0
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '1'; --Aus (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_01; -- Zustandsuebgergang
else
--RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus 0
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_00; -- GO = '0'
end if;
when ST_RAM_01 =>
-- RAM02
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '0'; --Ein
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '1'; -- Schreiben
n_SV <= ST_RAM_02; -- Zustandsuebgergang
when ST_RAM_02 =>
if (COUNT_ADR = b"1111111111111111111" AND COUNT_DAT = b"0000000000000000")
then
-- RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_03; -- COUNT_ADR < FF
else
--RAM03
n_COUNT_ADR <= COUNT_ADR+1; -- Adress Zaehler inkrementieren
n_COUNT_DAT <= COUNT_DAT-1; -- Daten Zaehler dekrementieren
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_04; -- COUNT_ADR = FF
end if;
when ST_RAM_03 =>
if (GO_S = '0')
then
-- RAM06
n_COUNT_ADR <= b"0000000000000000000"; -- Wert wird null
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_05; -- GO_S ='0'
else
--RAM05
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_03; -- GO_S ='1'
end if;
when ST_RAM_04 =>
-- RAM04
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '1'; --Aus (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_01; -- Zustandsübergang
when ST_RAM_05 =>
if (GO_S = '0')
then
-- RAM08
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_06; -- GO_S ='0'
else
--RAM07
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_00; -- GO_S ='1'
end if;
when ST_RAM_06 =>
if (PLUS_S = '1')
then
-- RAM09
n_COUNT_ADR <= COUNT_ADR+1; -- Wert wird erhöht
n_COUNT_DAT <= COUNT_DAT;
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '0'; -- Aus(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_07; -- PLUS_S ='1'
else
--RAM11
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '1'; --Ein
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_08; -- PLUS_S ='0'
end if;
when ST_RAM_07 =>
if (PLUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM10
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_07; -- PLUS_S ='1'
end if;
when ST_RAM_08 =>
if (MINUS_S = '1')
then
--RAM12
n_COUNT_ADR <= COUNT_ADR-1; -- Wert wird verringert
n_COUNT_DAT <= COUNT_DAT;
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_09; -- MINUS_S ='1'
else
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_05; -- PLUS_S ='0'
end if;
when ST_RAM_09 =>
if (MINUS_S = '0')
then
-- RAM14
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus (0=Ein 1=Aus)
OE <= '0'; --Ein (0=Ein 1=Aus)
CE1 <= '0'; --Ein (0=Ein 1=Aus)
STOP <= '1'; -- Ein(0=Aus 1=Ein)
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_05; -- PLUS_S ='0'
else
--RAM13
n_COUNT_ADR <= COUNT_ADR; -- Wert bleibt gleich
n_COUNT_DAT <= COUNT_DAT; -- Wert bleibt gleich
WE <= '1'; --Aus
OE <= '0'; --Ein
CE1 <= '0'; --Ein
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_09; -- MINUS_S ='1'
end if;
when others =>
-- RAM00
n_COUNT_ADR <= b"0000000000000000000"; -- Adress Zaehler Neustart
n_COUNT_DAT <= b"1111111111111111"; -- Daten Zaehler Neustart
WE <= '1'; --Aus
OE <= '1'; --Aus
CE1 <= '1'; --Aus
STOP <= '0'; --Aus
WRITE <= '0'; -- Lesen
n_SV <= ST_RAM_00;
end case;
end process;
OREG_CHG_PROC: process (CLK, n_COUNT_ADR) --Ausgangsregister
begin
-- Adressen
COUNT_ADR_OUT <= n_COUNT_ADR;
if (CLK'event and CLK = '1')
then
-- Daten
if (WRITE = '1')
then
COUNT_DAT_OUT <= n_COUNT_DAT;
else
COUNT_DAT_OUT <= COUNT_DAT_OUT_INPUT;
end if;
end if;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_STATE_SV, DISPL_STATE_n_SV, DISPL_ADR, DISPL_DAT, COUNT_ADR, COUNT_DAT_OUT_INPUT) -- Zustandsanzeige
begin
DISPL_STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
DISPL_STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
if (DISPL_ADR = '0')
then
-- Aktuellen Zustand anzeigen
DISPL1_SV(0) <= DISPL_STATE_SV(0); --Bit0
DISPL1_SV(1) <= DISPL_STATE_SV(1); --Bit1
DISPL1_SV(2) <= DISPL_STATE_SV(2); --Bit2
DISPL1_SV(3) <= DISPL_STATE_SV(3); --Bit3
DISPL2_SV(0) <= DISPL_STATE_SV(4); --usw.
DISPL2_SV(1) <= DISPL_STATE_SV(5);
DISPL2_SV(2) <= DISPL_STATE_SV(6);
DISPL2_SV(3) <= DISPL_STATE_SV(7);
else
-- Adresse anzeigen (erste 8 Bit)
DISPL1_SV(0) <= COUNT_ADR(0); --Bit0
DISPL1_SV(1) <= COUNT_ADR(1); --Bit1
DISPL1_SV(2) <= COUNT_ADR(2); --Bit2
DISPL1_SV(3) <= COUNT_ADR(3); --Bit3
DISPL2_SV(0) <= COUNT_ADR(4); --usw.
DISPL2_SV(1) <= COUNT_ADR(5);
DISPL2_SV(2) <= COUNT_ADR(6);
DISPL2_SV(3) <= COUNT_ADR(7);
end if;
if (DISPL_DAT = '0')
then
-- Folgezustand anzeigen
DISPL1_n_SV(0) <= DISPL_STATE_n_SV(0);
DISPL1_n_SV(1) <= DISPL_STATE_n_SV(1);
DISPL1_n_SV(2) <= DISPL_STATE_n_SV(2);
DISPL1_n_SV(3) <= DISPL_STATE_n_SV(3);
DISPL2_n_SV(0) <= DISPL_STATE_n_SV(4);
DISPL2_n_SV(1) <= DISPL_STATE_n_SV(5);
DISPL2_n_SV(2) <= DISPL_STATE_n_SV(6);
DISPL2_n_SV(3) <= DISPL_STATE_n_SV(7);
else
--Daten anzeigen (erste 8 Bit)
DISPL1_n_SV(0) <= COUNT_DAT_OUT_INPUT(0);
DISPL1_n_SV(1) <= COUNT_DAT_OUT_INPUT(1);
DISPL1_n_SV(2) <= COUNT_DAT_OUT_INPUT(2);
DISPL1_n_SV(3) <= COUNT_DAT_OUT_INPUT(3);
DISPL2_n_SV(0) <= COUNT_DAT_OUT_INPUT(4);
DISPL2_n_SV(1) <= COUNT_DAT_OUT_INPUT(5);
DISPL2_n_SV(2) <= COUNT_DAT_OUT_INPUT(6);
DISPL2_n_SV(3) <= COUNT_DAT_OUT_INPUT(7);
end if;
end process;
end Behavioral;
| gpl-2.0 | c4dc383a47980dd1a642a8f7dcf24b25 | 0.542086 | 2.918059 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_sm.vhd | 1 | 50,954 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_sm.vhd
-- Description: This entity contains the S2MM DMA Controller State Machine
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_sm is
generic (
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Width of Buffer Length, Transferred Bytes, and BTT fields
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1
-- Depth of DataMover command FIFO
);
port (
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
s2mm_stop : in std_logic ; --
--
-- S2MM Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_desc_flush : in std_logic ; --
s2mm_cmnd_idle : out std_logic ; --
s2mm_sts_idle : out std_logic ; --
s2mm_eof_set : out std_logic ; --
s2mm_eof_micro : in std_logic ; --
s2mm_sof_micro : in std_logic ; --
--
-- S2MM Descriptor Fetch Request --
desc_fetch_req : out std_logic ; --
desc_fetch_done : in std_logic ; --
desc_update_done : in std_logic ; --
updt_pending : in std_logic ;
desc_available : in std_logic ; --
--
-- S2MM Status Stream RX Length --
s2mm_rxlength_valid : in std_logic ; --
s2mm_rxlength_clr : out std_logic ; --
s2mm_rxlength : in std_logic_vector --
(C_SG_LENGTH_WIDTH - 1 downto 0) ; --
--
-- DataMover Command --
s2mm_cmnd_wr : out std_logic ; --
s2mm_cmnd_data : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
s2mm_cmnd_pending : in std_logic ; --
--
-- Descriptor Fields --
s2mm_desc_info : in std_logic_vector --
(31 downto 0); --
s2mm_desc_baddress : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_desc_blength : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_v : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0); --
s2mm_desc_blength_s : in std_logic_vector --
(BUFFER_LENGTH_WIDTH-1 downto 0) --
);
end axi_dma_s2mm_sm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_sm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- DataMover Commmand TAG
constant S2MM_CMD_TAG : std_logic_vector(2 downto 0) := (others => '0');
-- DataMover Command Destination Stream Offset
constant S2MM_CMD_DSA : std_logic_vector(5 downto 0) := (others => '0');
-- DataMover Cmnd Reserved Bits
constant S2MM_CMD_RSVD : std_logic_vector(
DATAMOVER_CMD_RSVMSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH downto
DATAMOVER_CMD_RSVLSB_BOFST + C_M_AXI_S2MM_ADDR_WIDTH)
:= (others => '0');
-- Queued commands counter width
constant COUNTER_WIDTH : integer := clog2(C_PRMY_CMDFIFO_DEPTH+1);
-- Queued commands zero count
constant ZERO_COUNT : std_logic_vector(COUNTER_WIDTH - 1 downto 0)
:= (others => '0');
-- Zero buffer length error - compare value
constant ZERO_LENGTH : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
constant ZERO_BUFFER : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- State Machine Signals
signal desc_fetch_req_cmb : std_logic := '0';
signal write_cmnd_cmb : std_logic := '0';
signal s2mm_rxlength_clr_cmb : std_logic := '0';
signal rxlength : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_rxlength_set : std_logic := '0';
signal blength_grtr_rxlength : std_logic := '0';
signal rxlength_fetched : std_logic := '0';
signal cmnds_queued : std_logic_vector(COUNTER_WIDTH - 1 downto 0) := (others => '0');
signal cmnds_queued_shift : std_logic_vector(C_PRMY_CMDFIFO_DEPTH - 1 downto 0) := (others => '0');
signal count_incr : std_logic := '0';
signal count_decr : std_logic := '0';
signal desc_fetch_done_d1 : std_logic := '0';
signal zero_length_error : std_logic := '0';
signal s2mm_eof_set_i : std_logic := '0';
signal queue_more : std_logic := '0';
signal burst_type : std_logic;
signal eof_micro : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
EN_MICRO_DMA : if C_MICRO_DMA = 1 generate
begin
eof_micro <= s2mm_eof_micro;
end generate EN_MICRO_DMA;
NO_MICRO_DMA : if C_MICRO_DMA = 0 generate
begin
eof_micro <= '0';
end generate NO_MICRO_DMA;
s2mm_eof_set <= s2mm_eof_set_i;
burst_type <= '1' and (not s2mm_keyhole);
-- A 0 s2mm_keyhole means incremental burst
-- a 1 s2mm_keyhole means fixed burst
-------------------------------------------------------------------------------
-- Not using rx length from status stream - (indeterminate length mode)
-------------------------------------------------------------------------------
GEN_SM_FOR_NO_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
-- EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-- For no status stream or not using length in status app field then eof set is
-- generated from datamover status (see axi_dma_s2mm_cmdsts_if.vhd)
s2mm_eof_set_i <= '0';
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_fetch_done,
desc_update_done,
s2mm_cmnd_pending,
s2mm_stop,
s2mm_desc_flush,
updt_pending
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
-- fetch descriptor if desc available, not stopped and running
-- if (updt_pending = '1') then
-- s2mm_ns <= WAIT_STATUS;
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 1) then
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
else
s2mm_ns <= WAIT_STATUS;
write_cmnd_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- wait until fetch complete then execute
-- elsif(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
-- s2mm_ns <= EXECUTE_XFER;
elsif (s2mm_cmnd_pending = '0')then
desc_fetch_req_cmb <= '0';
if (updt_pending = '0') then
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
write_cmnd_cmb <= '1';
else
-- coverage off
s2mm_ns <= WAIT_STATUS;
-- coverage on
end if;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
-- when EXECUTE_XFER =>
-- -- if error exit
-- if(s2mm_stop = '1')then
-- s2mm_ns <= IDLE;
-- -- Write another command if there is not one already pending
-- elsif(s2mm_cmnd_pending = '0')then
-- if (updt_pending = '0') then
-- write_cmnd_cmb <= '1';
-- end if;
-- if(C_SG_INCLUDE_DESC_QUEUE = 1)then
-- s2mm_ns <= IDLE;
-- else
-- s2mm_ns <= WAIT_STATUS;
-- end if;
-- else
-- s2mm_ns <= EXECUTE_XFER;
-- end if;
-------------------------------------------------------------------
when WAIT_STATUS =>
-- for no Q wait until desc updated
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register State Machine Statues
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register State Machine Signalse
-------------------------------------------------------------------------------
-- SM_SIG_REGISTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- desc_fetch_req <= '0' ;
-- else
-- if (C_SG_INCLUDE_DESC_QUEUE = 0) then
-- desc_fetch_req <= '1';
-- else
-- desc_fetch_req <= desc_fetch_req_cmb ;
-- end if;
-- end if;
-- end if;
-- end process SM_SIG_REGISTER;
desc_fetch_req <= '1' when (C_SG_INCLUDE_DESC_QUEUE = 0) else
desc_fetch_req_cmb ;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For Indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & PAD_VALUE
-- & s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro --00" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro --'0' -- For Indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
-- s2mm_cmnd_data <= (others => '0');
-- Fetch SM issued a command write
elsif(write_cmnd_cmb = '1')then
s2mm_cmnd_wr <= '1';
-- s2mm_cmnd_data <= s2mm_desc_info
-- & s2mm_desc_blength_v
-- & s2mm_desc_blength_s
-- & S2MM_CMD_RSVD
-- & "0000" -- Cat IOC to CMD TAG
-- & s2mm_desc_baddress
-- & '1' -- Always reset DRE
-- & '0' -- For indeterminate BTT mode do not set EOF
-- & S2MM_CMD_DSA
-- & burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
-- & s2mm_desc_blength;
else
s2mm_cmnd_wr <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s2mm_cmnd_data <= s2mm_desc_info
& s2mm_desc_blength_v
& s2mm_desc_blength_s
& S2MM_CMD_RSVD
& "00" & eof_micro & eof_micro -- "0000" -- Cat IOC to CMD TAG
& s2mm_desc_baddress
& '1' -- Always reset DRE
& eof_micro -- For indeterminate BTT mode do not set EOF
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
end generate GEN_CMD_BTT_EQL_23;
-- Drive unused output to zero
s2mm_rxlength_clr <= '0';
end generate GEN_SM_FOR_NO_LENGTH;
-------------------------------------------------------------------------------
-- Generate state machine and support logic for Using RX Length from Status
-- Stream
-------------------------------------------------------------------------------
-- this would not hold good for MCDMA
GEN_SM_FOR_LENGTH : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
type SG_S2MM_STATE_TYPE is (
IDLE,
FETCH_DESCRIPTOR,
GET_RXLENGTH,
CMPR_LENGTH,
EXECUTE_XFER,
WAIT_STATUS
);
signal s2mm_cs : SG_S2MM_STATE_TYPE;
signal s2mm_ns : SG_S2MM_STATE_TYPE;
begin
-------------------------------------------------------------------------------
-- S2MM Transfer State Machine
-------------------------------------------------------------------------------
S2MM_MACHINE : process(s2mm_cs,
s2mm_run_stop,
desc_available,
desc_update_done,
-- desc_fetch_done,
updt_pending,
s2mm_rxlength_valid,
rxlength_fetched,
s2mm_cmnd_pending,
zero_length_error,
s2mm_stop,
s2mm_desc_flush
-- queue_more
)
begin
-- Default signal assignment
desc_fetch_req_cmb <= '0';
s2mm_rxlength_clr_cmb <= '0';
write_cmnd_cmb <= '0';
s2mm_cmnd_idle <= '0';
s2mm_rxlength_set <= '0';
--rxlength_fetched_clr <= '0';
s2mm_ns <= s2mm_cs;
case s2mm_cs is
-------------------------------------------------------------------
when IDLE =>
if(s2mm_run_stop = '1' and desc_available = '1'
-- and s2mm_stop = '0' and queue_more = '1' and updt_pending = '0')then
and s2mm_stop = '0' and updt_pending = '0')then
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
else
s2mm_ns <= FETCH_DESCRIPTOR;
desc_fetch_req_cmb <= '1';
end if;
else
s2mm_cmnd_idle <= '1';
s2mm_ns <= IDLE; --FETCH_DESCRIPTOR;
end if;
-------------------------------------------------------------------
when FETCH_DESCRIPTOR =>
desc_fetch_req_cmb <= '0';
-- exit if error or descriptor flushed
if(s2mm_desc_flush = '1')then
s2mm_ns <= IDLE;
-- Descriptor fetch complete
else --if(desc_fetch_done = '1')then
-- desc_fetch_req_cmb <= '0';
if(rxlength_fetched = '0')then
s2mm_ns <= GET_RXLENGTH;
else
s2mm_ns <= CMPR_LENGTH;
end if;
-- else
-- desc_fetch_req_cmb <= '1';
end if;
-------------------------------------------------------------------
WHEN GET_RXLENGTH =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- Buffer length zero, do not compare lengths, execute
-- command to force datamover to issue interror
elsif(zero_length_error = '1')then
s2mm_ns <= EXECUTE_XFER;
elsif(s2mm_rxlength_valid = '1')then
s2mm_rxlength_set <= '1';
s2mm_rxlength_clr_cmb <= '1';
s2mm_ns <= CMPR_LENGTH;
else
s2mm_ns <= GET_RXLENGTH;
end if;
-------------------------------------------------------------------
WHEN CMPR_LENGTH =>
s2mm_ns <= EXECUTE_XFER;
-------------------------------------------------------------------
when EXECUTE_XFER =>
if(s2mm_stop = '1')then
s2mm_ns <= IDLE;
-- write new command if one is not already pending
elsif(s2mm_cmnd_pending = '0')then
write_cmnd_cmb <= '1';
-- If descriptor queuing enabled then
-- do NOT need to wait for status
if(C_SG_INCLUDE_DESC_QUEUE = 1)then
s2mm_ns <= IDLE;
-- No queuing therefore must wait for
-- status before issuing next command
else
s2mm_ns <= WAIT_STATUS;
end if;
else
s2mm_ns <= EXECUTE_XFER;
end if;
-------------------------------------------------------------------
-- coverage off
when WAIT_STATUS =>
if(desc_update_done = '1' or s2mm_stop = '1')then
s2mm_ns <= IDLE;
else
s2mm_ns <= WAIT_STATUS;
end if;
-- coverage on
-------------------------------------------------------------------
-- coverage off
when others =>
s2mm_ns <= IDLE;
-- coverage on
end case;
end process S2MM_MACHINE;
-------------------------------------------------------------------------------
-- Register state machine states
-------------------------------------------------------------------------------
REGISTER_STATE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cs <= IDLE;
else
s2mm_cs <= s2mm_ns;
end if;
end if;
end process REGISTER_STATE;
-------------------------------------------------------------------------------
-- Register state machine signals
-------------------------------------------------------------------------------
SM_SIG_REGISTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_req <= '0' ;
s2mm_rxlength_clr <= '0' ;
else
if (C_SG_INCLUDE_DESC_QUEUE = 0) then
desc_fetch_req <= '1';
else
desc_fetch_req <= desc_fetch_req_cmb ;
end if;
s2mm_rxlength_clr <= s2mm_rxlength_clr_cmb;
end if;
end if;
end process SM_SIG_REGISTER;
-------------------------------------------------------------------------------
-- Check for a ZERO value in descriptor buffer length. If there is
-- then flag an error and skip waiting for valid rxlength. cmnd will
-- get written to datamover with BTT=0 and datamover will flag dmaint error
-- which will be logged in desc, reset required to clear error
-------------------------------------------------------------------------------
REG_ALIGN_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
desc_fetch_done_d1 <= '0';
else
desc_fetch_done_d1 <= desc_fetch_done;
end if;
end if;
end process REG_ALIGN_DONE;
-------------------------------------------------------------------------------
-- Zero length error detection - for determinate mode, detect early to prevent
-- rxlength calcuation from first taking place. This will force a 0 BTT
-- command to be issued to the datamover causing an internal error.
-------------------------------------------------------------------------------
REG_ZERO_LNGTH_ERR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
zero_length_error <= '0';
elsif(desc_fetch_done_d1 = '1'
and s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) = ZERO_LENGTH)then
zero_length_error <= '1';
end if;
end if;
end process REG_ZERO_LNGTH_ERR;
-------------------------------------------------------------------------------
-- Capture/Hold receive length from status stream. Also decrement length
-- based on if received length is greater than descriptor buffer size. (i.e. is
-- the case where multiple descriptors/buffers are used to describe one packet)
-------------------------------------------------------------------------------
REG_RXLENGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
rxlength <= (others => '0');
-- If command register rxlength from status stream fifo
elsif(s2mm_rxlength_set = '1')then
rxlength <= s2mm_rxlength;
-- On command write if current desc buffer size not greater
-- than current rxlength then decrement rxlength in preperations
-- for subsequent commands
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
rxlength <= std_logic_vector(unsigned(rxlength(C_SG_LENGTH_WIDTH-1 downto 0))
- unsigned(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0)));
end if;
end if;
end process REG_RXLENGTH;
-------------------------------------------------------------------------------
-- Calculate if Descriptor Buffer Length is 'Greater Than' or 'Equal To'
-- Received Length value
-------------------------------------------------------------------------------
REG_BLENGTH_GRTR_RXLNGTH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
blength_grtr_rxlength <= '0';
elsif(s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0) >= rxlength)then
blength_grtr_rxlength <= '1';
else
blength_grtr_rxlength <= '0';
end if;
end if;
end process REG_BLENGTH_GRTR_RXLNGTH;
-------------------------------------------------------------------------------
-- On command assert rxlength fetched flag indicating length grabbed from
-- status stream fifo
-------------------------------------------------------------------------------
RXLENGTH_FTCHED_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_eof_set_i = '1')then
rxlength_fetched <= '0';
elsif(s2mm_rxlength_set = '1')then
rxlength_fetched <= '1';
end if;
end if;
end process RXLENGTH_FTCHED_PROCESS;
-------------------------------------------------------------------------------
-- Build DataMover command
-------------------------------------------------------------------------------
-- If Bytes To Transfer (BTT) width less than 23, need to add pad
GEN_CMD_BTT_LESS_23 : if C_SG_LENGTH_WIDTH < 23 generate
constant PAD_VALUE : std_logic_vector(22 - C_SG_LENGTH_WIDTH downto 0)
:= (others => '0');
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF=0 to CMD Tag
& '0' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& s2mm_desc_blength(C_SG_LENGTH_WIDTH-1 downto 0);
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF=1 to CMD Tag
& '1' -- Cat. IOC to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- Set EOF=1
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& PAD_VALUE
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_LESS_23;
-- If Bytes To Transfer (BTT) width equal 23, no required pad
GEN_CMD_BTT_EQL_23 : if C_SG_LENGTH_WIDTH = 23 generate
begin
-- When command by sm, drive command to s2mm_cmdsts_if
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_cmnd_wr <= '0';
s2mm_cmnd_data <= (others => '0');
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will NOT hold entire rxlength of data therefore
-- set EOF = based on Desc.EOF and pass buffer length for BTT
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '0')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '0' -- Cat. EOF='0' to CMD Tag
& '0' -- Cat. IOC='0' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '0' -- Not End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& s2mm_desc_blength;
s2mm_eof_set_i <= '0';
-- Current Desc Buffer will hold entire rxlength of data therefore
-- set EOF = 1 and pass rxlength for BTT
--
-- Note: change to mode where EOF generates IOC interrupt as
-- opposed to a IOC bit in the descriptor negated need for an
-- EOF and IOC tag. Given time, these two bits could be combined
-- into 1. Associated logic in SG engine would also need to be
-- modified as well as in s2mm_sg_if.
elsif(write_cmnd_cmb = '1' and blength_grtr_rxlength = '1')then
s2mm_cmnd_wr <= '1';
s2mm_cmnd_data <= s2mm_desc_info
& ZERO_BUFFER
& ZERO_BUFFER
& S2MM_CMD_RSVD
--& S2MM_CMD_TAG & s2mm_desc_ioc -- Cat IOC to CMD TAG
-- Command Tag
& '0'
& '0'
& '1' -- Cat. EOF='1' to CMD Tag
& '1' -- Cat. IOC='1' to CMD TAG
-- Command
& s2mm_desc_baddress
& '1' -- Always reset DRE
& '1' -- End of Frame
& S2MM_CMD_DSA
& burst_type -- Key Hole '1' -- s2mm_desc_type -- IR# 545697
& rxlength;
s2mm_eof_set_i <= '1';
else
-- s2mm_cmnd_data <= (others => '0');
s2mm_cmnd_wr <= '0';
s2mm_eof_set_i <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
end generate GEN_CMD_BTT_EQL_23;
end generate GEN_SM_FOR_LENGTH;
-------------------------------------------------------------------------------
-- Counter for keepting track of pending commands/status in primary datamover
-- Use this to determine if primary datamover for s2mm is Idle.
-------------------------------------------------------------------------------
-- Increment queue count for each command written if not occuring at
-- same time a status from DM being updated to SG engine
count_incr <= '1' when write_cmnd_cmb = '1' and desc_update_done = '0'
else '0';
-- Decrement queue count for each status update to SG engine if not occuring
-- at same time as command being written to DM
count_decr <= '1' when write_cmnd_cmb = '0' and desc_update_done = '1'
else '0';
-- keep track of number queue commands
--CMD2STS_COUNTER : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
-- cmnds_queued <= (others => '0');
-- elsif(count_incr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) + 1);
-- elsif(count_decr = '1')then
-- cmnds_queued <= std_logic_vector(unsigned(cmnds_queued(COUNTER_WIDTH - 1 downto 0)) - 1);
-- end if;
-- end if;
-- end process CMD2STS_COUNTER;
QUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 1 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift <= (others => '0');
elsif(count_incr = '1')then
cmnds_queued_shift <= cmnds_queued_shift (2 downto 0) & '1';
elsif(count_decr = '1')then
cmnds_queued_shift <= '0' & cmnds_queued_shift (3 downto 1);
end if;
end if;
end process CMD2STS_COUNTER1;
end generate QUEUE_COUNT;
NOQUEUE_COUNT : if C_SG_INCLUDE_DESC_QUEUE = 0 generate
begin
CMD2STS_COUNTER1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or s2mm_stop = '1')then
cmnds_queued_shift (0) <= '0';
elsif(count_incr = '1')then
cmnds_queued_shift (0) <= '1';
elsif(count_decr = '1')then
cmnds_queued_shift (0) <= '0';
end if;
end if;
end process CMD2STS_COUNTER1;
end generate NOQUEUE_COUNT;
-- indicate idle when no more queued commands
--s2mm_sts_idle <= '1' when cmnds_queued_shift = "0000"
-- else '0';
s2mm_sts_idle <= not cmnds_queued_shift(0);
-------------------------------------------------------------------------------
-- Queue only the amount of commands that can be queued on descriptor update
-- else lock up can occur. Note datamover command fifo depth is set to number
-- of descriptors to queue.
-------------------------------------------------------------------------------
--QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- if(m_axi_sg_aresetn = '0')then
-- queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
-- else
-- queue_more <= '0';
-- end if;
-- end if;
-- end process QUEUE_MORE_PROCESS;
QUEUE_MORE_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
queue_more <= '0';
-- elsif(cmnds_queued < std_logic_vector(to_unsigned(C_PRMY_CMDFIFO_DEPTH,COUNTER_WIDTH)))then
-- queue_more <= '1';
else
queue_more <= not (cmnds_queued_shift (C_PRMY_CMDFIFO_DEPTH-1)); --'0';
end if;
end if;
end process QUEUE_MORE_PROCESS;
end implementation;
| mit | b68853f9e0005bf3083c489da15a793d | 0.375927 | 4.904139 | false | false | false | false |
szanni/aeshw | zybo-base/aeshw_1.0/hdl/aeshw_v1_0.vhd | 1 | 3,581 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity aeshw_v1_0 is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Parameters of Axi Slave Bus Interface S_AXI
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Ports of Axi Slave Bus Interface S_AXI
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end aeshw_v1_0;
architecture arch_imp of aeshw_v1_0 is
-- component declaration
component aeshw_v1_0_S_AXI is
generic (
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 6
);
port (
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
);
end component aeshw_v1_0_S_AXI;
begin
-- Instantiation of Axi Bus Interface S_AXI
aeshw_v1_0_S_AXI_inst : aeshw_v1_0_S_AXI
generic map (
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH
)
port map (
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWPROT => s_axi_awprot,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARPROT => s_axi_arprot,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready
);
-- Add user logic here
-- User logic ends
end arch_imp;
| bsd-2-clause | cfc12f525cee74fe9b0c1172aa8179ed | 0.662385 | 2.36058 | false | false | false | false |
codepainters/vhdl-utils | clock_prescaler.vhd | 1 | 2,526 | ----------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <[email protected]>
-- This file is distributed under the Modified BSD License.
--
-- This is an implementation of an efficient clock prescaler for Xilinx FPGAs,
-- based on SRL16 shift register primitive.
--
-- It divides the input clock by n * (10 ^ exp), where n is in range 2..16 and
-- exp is in range 0..10. Output goes 1 for one cycle of the input clock,
-- every n * (10 ^ exp) cycles of the input clock.
--
-- It uses only exp + 1 LUTs, which is a significant improvement over a prescaler
-- based on a simple counter.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity clock_prescaler is
generic (n : integer range 2 to 16;
exp : integer range 0 to 10);
port(clk : in std_logic;
q : out std_logic);
end clock_prescaler;
architecture rtl of clock_prescaler is
-- first stage length
constant first_stage_tap : std_logic_vector(3 downto 0) := std_logic_vector(to_signed(n - 1, 4));
-- feedback signal inside each stage
signal sreg_fb : std_logic_vector(0 to exp);
-- those signals go between stages
signal stage_q : std_logic_vector(0 to exp);
begin
-- first stage divides by n
first_reg : SRLC16E
generic map(INIT => X"0001")
port map (Q => sreg_fb(0), Q15 => open,
A0 => first_stage_tap(0), A1 => first_stage_tap(1),
A2 => first_stage_tap(2), A3 => first_stage_tap(3),
CE => '1', D => sreg_fb(0), CLK => clk );
stage_q(0) <= sreg_fb(0);
-- subsequent exp stages each divides by 10
exp_divides : for i in 1 to exp generate
begin
sreg : SRLC16E
generic map(INIT => X"0001")
port map (Q => sreg_fb(i), Q15 => open,
A0 => '1', A1 => '0', A2 => '0', A3 => '1',
CE => stage_q(i - 1), D => sreg_fb(i),
CLK => clk );
-- shift reg output must be AND-ed with previous stage output,
-- so the pulse is only 1 clk period long
q_and : AND2 port map (I0 => sreg_fb(i), I1 => stage_q(i - 1), O => stage_q(i));
end generate;
-- output of the last stage is prescaler's output
q <= stage_q(exp);
end rtl;
| bsd-2-clause | cd4fd17c035d3c93fbf6d1cfdf93ac56 | 0.543547 | 3.736686 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/rocketlib/rocket_l1only.vhd | 1 | 13,124 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief RockeTile top level.
--! @details RISC-V "RocketTile" without Uncore subsystem.
------------------------------------------------------------------------------
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! Rocket-chip specific library
library rocketlib;
--! TileLink interface description.
use rocketlib.types_rocket.all;
library work;
use work.all;
--! @brief RocketTile entity declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
entity rocket_l1only is
generic (
hartid : integer := 0;
reset_vector : integer := 16#1000#
);
port (
nrst : in std_logic;
clk_sys : in std_logic;
msti1 : in nasti_master_in_type;
msto1 : out nasti_master_out_type;
mstcfg1 : out nasti_master_config_type;
msti2 : in nasti_master_in_type;
msto2 : out nasti_master_out_type;
mstcfg2 : out nasti_master_config_type;
interrupts : in std_logic_vector(CFG_CORE_IRQ_TOTAL-1 downto 0)
);
--! @}
end;
--! @brief SOC top-level architecture declaration.
architecture arch_rocket_l1only of rocket_l1only is
constant CFG_HARTID : std_logic_vector(63 downto 0) := conv_std_logic_vector(hartid, 64);
constant CFG_RESET_VECTOR : std_logic_vector(63 downto 0) := conv_std_logic_vector(reset_vector, 64);
constant xmstconfig1 : nasti_master_config_type := (
descrsize => PNP_CFG_MASTER_DESCR_BYTES,
descrtype => PNP_CFG_TYPE_MASTER,
vid => VENDOR_GNSSSENSOR,
did => RISCV_CACHED_TILELINK
);
constant xmstconfig2 : nasti_master_config_type := (
descrsize => PNP_CFG_MASTER_DESCR_BYTES,
descrtype => PNP_CFG_TYPE_MASTER,
vid => VENDOR_GNSSSENSOR,
did => RISCV_UNCACHED_TILELINK
);
signal cpu_rst : std_logic;
signal cto : tile_out_type;
signal cti : tile_in_type;
signal uto : tile_out_type;
signal uti : tile_in_type;
component AxiBridge is port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_in_type
);
end component;
component Tile2Axi is port (
clk : in std_logic;
nrst : in std_logic;
--! Tile-to-AXI direction
tloi : in tile_out_type;
msto : out nasti_master_out_type;
--! AXI-to-Tile direction
msti : in nasti_master_in_type;
tlio : out tile_in_type
);
end component;
COMPONENT RocketTile
PORT(
clock : IN std_logic;
reset : IN std_logic;
io_cached_0_a_ready : IN std_logic;
io_cached_0_a_valid : OUT std_logic;
io_cached_0_a_bits_opcode : OUT std_logic_vector(2 downto 0);
io_cached_0_a_bits_param : OUT std_logic_vector(2 downto 0);
io_cached_0_a_bits_size : OUT std_logic_vector(3 downto 0);
io_cached_0_a_bits_source : OUT std_logic_vector(1 downto 0);
io_cached_0_a_bits_address : OUT std_logic_vector(31 downto 0);
io_cached_0_a_bits_mask : OUT std_logic_vector(7 downto 0);
io_cached_0_a_bits_data : OUT std_logic_vector(63 downto 0);
io_cached_0_b_ready : OUT std_logic;
io_cached_0_b_valid : IN std_logic;
io_cached_0_b_bits_opcode : IN std_logic_vector(2 downto 0);
io_cached_0_b_bits_param : IN std_logic_vector(1 downto 0);
io_cached_0_b_bits_size : IN std_logic_vector(3 downto 0);
io_cached_0_b_bits_source : IN std_logic_vector(1 downto 0);
io_cached_0_b_bits_address : IN std_logic_vector(31 downto 0);
io_cached_0_b_bits_mask : IN std_logic_vector(7 downto 0);
io_cached_0_b_bits_data : IN std_logic_vector(63 downto 0);
io_cached_0_c_ready : IN std_logic;
io_cached_0_c_valid : OUT std_logic;
io_cached_0_c_bits_opcode : OUT std_logic_vector(2 downto 0);
io_cached_0_c_bits_param : OUT std_logic_vector(2 downto 0);
io_cached_0_c_bits_size : OUT std_logic_vector(3 downto 0);
io_cached_0_c_bits_source : OUT std_logic_vector(1 downto 0);
io_cached_0_c_bits_address : OUT std_logic_vector(31 downto 0);
io_cached_0_c_bits_data : OUT std_logic_vector(63 downto 0);
io_cached_0_c_bits_error : OUT std_logic;
io_cached_0_d_ready : OUT std_logic;
io_cached_0_d_valid : IN std_logic;
io_cached_0_d_bits_opcode : IN std_logic_vector(2 downto 0);
io_cached_0_d_bits_param : IN std_logic_vector(1 downto 0);
io_cached_0_d_bits_size : IN std_logic_vector(3 downto 0);
io_cached_0_d_bits_source : IN std_logic_vector(1 downto 0);
io_cached_0_d_bits_sink : IN std_logic_vector(3 downto 0);
io_cached_0_d_bits_addr_lo : IN std_logic_vector(2 downto 0);
io_cached_0_d_bits_data : IN std_logic_vector(63 downto 0);
io_cached_0_d_bits_error : IN std_logic;
io_cached_0_e_ready : IN std_logic;
io_cached_0_e_valid : OUT std_logic;
io_cached_0_e_bits_sink : OUT std_logic_vector(3 downto 0);
io_uncached_0_a_ready : IN std_logic;
io_uncached_0_a_valid : OUT std_logic;
io_uncached_0_a_bits_opcode : OUT std_logic_vector(2 downto 0);
io_uncached_0_a_bits_param : OUT std_logic_vector(2 downto 0);
io_uncached_0_a_bits_size : OUT std_logic_vector(3 downto 0);
io_uncached_0_a_bits_source : OUT std_logic_vector(2 downto 0);
io_uncached_0_a_bits_address : OUT std_logic_vector(31 downto 0);
io_uncached_0_a_bits_mask : OUT std_logic_vector(7 downto 0);
io_uncached_0_a_bits_data : OUT std_logic_vector(63 downto 0);
io_uncached_0_b_ready : OUT std_logic;
io_uncached_0_b_valid : IN std_logic;
io_uncached_0_b_bits_opcode : IN std_logic_vector(2 downto 0);
io_uncached_0_b_bits_param : IN std_logic_vector(1 downto 0);
io_uncached_0_b_bits_size : IN std_logic_vector(3 downto 0);
io_uncached_0_b_bits_source : IN std_logic_vector(2 downto 0);
io_uncached_0_b_bits_address : IN std_logic_vector(31 downto 0);
io_uncached_0_b_bits_mask : IN std_logic_vector(7 downto 0);
io_uncached_0_b_bits_data : IN std_logic_vector(63 downto 0);
io_uncached_0_c_ready : IN std_logic;
io_uncached_0_c_valid : OUT std_logic;
io_uncached_0_c_bits_opcode : OUT std_logic_vector(2 downto 0);
io_uncached_0_c_bits_param : OUT std_logic_vector(2 downto 0);
io_uncached_0_c_bits_size : OUT std_logic_vector(3 downto 0);
io_uncached_0_c_bits_source : OUT std_logic_vector(2 downto 0);
io_uncached_0_c_bits_address : OUT std_logic_vector(31 downto 0);
io_uncached_0_c_bits_data : OUT std_logic_vector(63 downto 0);
io_uncached_0_c_bits_error : OUT std_logic;
io_uncached_0_d_ready : OUT std_logic;
io_uncached_0_d_valid : IN std_logic;
io_uncached_0_d_bits_opcode : IN std_logic_vector(2 downto 0);
io_uncached_0_d_bits_param : IN std_logic_vector(1 downto 0);
io_uncached_0_d_bits_size : IN std_logic_vector(3 downto 0);
io_uncached_0_d_bits_source : IN std_logic_vector(2 downto 0);
io_uncached_0_d_bits_sink : IN std_logic_vector(3 downto 0);
io_uncached_0_d_bits_addr_lo : IN std_logic_vector(2 downto 0);
io_uncached_0_d_bits_data : IN std_logic_vector(63 downto 0);
io_uncached_0_d_bits_error : IN std_logic;
io_uncached_0_e_ready : IN std_logic;
io_uncached_0_e_valid : OUT std_logic;
io_uncached_0_e_bits_sink : OUT std_logic_vector(3 downto 0);
io_hartid : IN std_logic_vector(63 downto 0);
io_interrupts_debug : IN std_logic;
io_interrupts_mtip : IN std_logic;
io_interrupts_msip : IN std_logic;
io_interrupts_meip : IN std_logic;
io_interrupts_seip : IN std_logic;
io_resetVector : IN std_logic_vector(63 downto 0)
);
END COMPONENT;
begin
mstcfg1 <= xmstconfig1;
mstcfg2 <= xmstconfig2;
cpu_rst <= not nrst;
cto.a_source(2) <= '0';
cti.b_source(2) <= '0';
cto.c_source(2) <= '0';
cti.d_source(2) <= '0';
inst_tile: RocketTile PORT MAP(
clock => clk_sys,
reset => cpu_rst,
io_cached_0_a_ready => cti.a_ready,
io_cached_0_a_valid => cto.a_valid,
io_cached_0_a_bits_opcode => cto.a_opcode,
io_cached_0_a_bits_param => cto.a_param,
io_cached_0_a_bits_size => cto.a_size,
io_cached_0_a_bits_source => cto.a_source(1 downto 0),
io_cached_0_a_bits_address => cto.a_address,
io_cached_0_a_bits_mask => cto.a_mask,
io_cached_0_a_bits_data => cto.a_data,
io_cached_0_b_ready => cto.b_ready,
io_cached_0_b_valid => cti.b_valid,
io_cached_0_b_bits_opcode => cti.b_opcode,
io_cached_0_b_bits_param => cti.b_param,
io_cached_0_b_bits_size => cti.b_size,
io_cached_0_b_bits_source => cti.b_source(1 downto 0),
io_cached_0_b_bits_address => cti.b_address,
io_cached_0_b_bits_mask => cti.b_mask,
io_cached_0_b_bits_data => cti.b_data,
io_cached_0_c_ready => cti.c_ready,
io_cached_0_c_valid => cto.c_valid,
io_cached_0_c_bits_opcode => cto.c_opcode,
io_cached_0_c_bits_param => cto.c_param,
io_cached_0_c_bits_size => cto.c_size,
io_cached_0_c_bits_source => cto.c_source(1 downto 0),
io_cached_0_c_bits_address => cto.c_address,
io_cached_0_c_bits_data => cto.c_data,
io_cached_0_c_bits_error => cto.c_error,
io_cached_0_d_ready => cto.d_ready,
io_cached_0_d_valid => cti.d_valid,
io_cached_0_d_bits_opcode => cti.d_opcode,
io_cached_0_d_bits_param => cti.d_param,
io_cached_0_d_bits_size => cti.d_size,
io_cached_0_d_bits_source => cti.d_source(1 downto 0),
io_cached_0_d_bits_sink => cti.d_sink,
io_cached_0_d_bits_addr_lo => cti.d_addr_lo,
io_cached_0_d_bits_data => cti.d_data,
io_cached_0_d_bits_error => cti.d_error,
io_cached_0_e_ready => cti.e_ready,
io_cached_0_e_valid => cto.e_valid,
io_cached_0_e_bits_sink => cto.e_sink,
io_uncached_0_a_ready => uti.a_ready,
io_uncached_0_a_valid => uto.a_valid,
io_uncached_0_a_bits_opcode => uto.a_opcode,
io_uncached_0_a_bits_param => uto.a_param,
io_uncached_0_a_bits_size => uto.a_size,
io_uncached_0_a_bits_source => uto.a_source,
io_uncached_0_a_bits_address => uto.a_address,
io_uncached_0_a_bits_mask => uto.a_mask,
io_uncached_0_a_bits_data => uto.a_data,
io_uncached_0_b_ready => uto.b_ready,
io_uncached_0_b_valid => uti.b_valid,
io_uncached_0_b_bits_opcode => uti.b_opcode,
io_uncached_0_b_bits_param => uti.b_param,
io_uncached_0_b_bits_size => uti.b_size,
io_uncached_0_b_bits_source => uti.b_source,
io_uncached_0_b_bits_address => uti.b_address,
io_uncached_0_b_bits_mask => uti.b_mask,
io_uncached_0_b_bits_data => uti.b_data,
io_uncached_0_c_ready => uti.c_ready,
io_uncached_0_c_valid => uto.c_valid,
io_uncached_0_c_bits_opcode => uto.c_opcode,
io_uncached_0_c_bits_param => uto.c_param,
io_uncached_0_c_bits_size => uto.c_size,
io_uncached_0_c_bits_source => uto.c_source,
io_uncached_0_c_bits_address => uto.c_address,
io_uncached_0_c_bits_data => uto.c_data,
io_uncached_0_c_bits_error => uto.c_error,
io_uncached_0_d_ready => uto.d_ready,
io_uncached_0_d_valid => uti.d_valid,
io_uncached_0_d_bits_opcode => uti.d_opcode,
io_uncached_0_d_bits_param => uti.d_param,
io_uncached_0_d_bits_size => uti.d_size,
io_uncached_0_d_bits_source => uti.d_source,
io_uncached_0_d_bits_sink => uti.d_sink,
io_uncached_0_d_bits_addr_lo => uti.d_addr_lo,
io_uncached_0_d_bits_data => uti.d_data,
io_uncached_0_d_bits_error => uti.d_error,
io_uncached_0_e_ready => uti.e_ready,
io_uncached_0_e_valid => uto.e_valid,
io_uncached_0_e_bits_sink => uto.e_sink,
io_hartid => CFG_HARTID,
io_interrupts_debug => interrupts(CFG_CORE_IRQ_DEBUG),
io_interrupts_mtip => interrupts(CFG_CORE_IRQ_MTIP),
io_interrupts_msip => interrupts(CFG_CORE_IRQ_MSIP),
io_interrupts_meip => interrupts(CFG_CORE_IRQ_MEIP),
io_interrupts_seip => interrupts(CFG_CORE_IRQ_SEIP),
io_resetVector => CFG_RESET_VECTOR
);
cbridge0 : Tile2Axi port map (
clk => clk_sys,
nrst => nrst,
--! Tile-to-AXI direction
tloi => cto,
msto => msto1,
--! AXI-to-Tile direction
msti => msti1,
tlio => cti
);
ubridge0 : Tile2Axi port map (
clk => clk_sys,
nrst => nrst,
--! Tile-to-AXI direction
tloi => uto,
msto => msto2,
--! AXI-to-Tile direction
msti => msti2,
tlio => uti
);
end arch_rocket_l1only;
| apache-2.0 | 50f3142a8bbad5d0711f8ba6f5fdc632 | 0.634563 | 2.862377 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ip/dma_loopback_axi_dma_0_0/sim/dma_loopback_axi_dma_0_0.vhd | 1 | 30,385 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_dma:7.1
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_dma_v7_1_10;
USE axi_dma_v7_1_10.axi_dma;
ENTITY dma_loopback_axi_dma_0_0 IS
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dma_loopback_axi_dma_0_0;
ARCHITECTURE dma_loopback_axi_dma_0_0_arch OF dma_loopback_axi_dma_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dma_loopback_axi_dma_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_dma IS
GENERIC (
C_S_AXI_LITE_ADDR_WIDTH : INTEGER;
C_S_AXI_LITE_DATA_WIDTH : INTEGER;
C_DLYTMR_RESOLUTION : INTEGER;
C_PRMRY_IS_ACLK_ASYNC : INTEGER;
C_ENABLE_MULTI_CHANNEL : INTEGER;
C_NUM_MM2S_CHANNELS : INTEGER;
C_NUM_S2MM_CHANNELS : INTEGER;
C_INCLUDE_SG : INTEGER;
C_SG_INCLUDE_STSCNTRL_STRM : INTEGER;
C_SG_USE_STSAPP_LENGTH : INTEGER;
C_SG_LENGTH_WIDTH : INTEGER;
C_M_AXI_SG_ADDR_WIDTH : INTEGER;
C_M_AXI_SG_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_STS_TDATA_WIDTH : INTEGER;
C_MICRO_DMA : INTEGER;
C_INCLUDE_MM2S : INTEGER;
C_INCLUDE_MM2S_SF : INTEGER;
C_MM2S_BURST_SIZE : INTEGER;
C_M_AXI_MM2S_ADDR_WIDTH : INTEGER;
C_M_AXI_MM2S_DATA_WIDTH : INTEGER;
C_M_AXIS_MM2S_TDATA_WIDTH : INTEGER;
C_INCLUDE_MM2S_DRE : INTEGER;
C_INCLUDE_S2MM : INTEGER;
C_INCLUDE_S2MM_SF : INTEGER;
C_S2MM_BURST_SIZE : INTEGER;
C_M_AXI_S2MM_ADDR_WIDTH : INTEGER;
C_M_AXI_S2MM_DATA_WIDTH : INTEGER;
C_S_AXIS_S2MM_TDATA_WIDTH : INTEGER;
C_INCLUDE_S2MM_DRE : INTEGER;
C_FAMILY : STRING
);
PORT (
s_axi_lite_aclk : IN STD_LOGIC;
m_axi_sg_aclk : IN STD_LOGIC;
m_axi_mm2s_aclk : IN STD_LOGIC;
m_axi_s2mm_aclk : IN STD_LOGIC;
axi_resetn : IN STD_LOGIC;
s_axi_lite_awvalid : IN STD_LOGIC;
s_axi_lite_awready : OUT STD_LOGIC;
s_axi_lite_awaddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_wvalid : IN STD_LOGIC;
s_axi_lite_wready : OUT STD_LOGIC;
s_axi_lite_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_lite_bvalid : OUT STD_LOGIC;
s_axi_lite_bready : IN STD_LOGIC;
s_axi_lite_arvalid : IN STD_LOGIC;
s_axi_lite_arready : OUT STD_LOGIC;
s_axi_lite_araddr : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_lite_rvalid : OUT STD_LOGIC;
s_axi_lite_rready : IN STD_LOGIC;
s_axi_lite_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_lite_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_awvalid : OUT STD_LOGIC;
m_axi_sg_awready : IN STD_LOGIC;
m_axi_sg_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_wlast : OUT STD_LOGIC;
m_axi_sg_wvalid : OUT STD_LOGIC;
m_axi_sg_wready : IN STD_LOGIC;
m_axi_sg_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_bvalid : IN STD_LOGIC;
m_axi_sg_bready : OUT STD_LOGIC;
m_axi_sg_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_sg_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_sg_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_sg_arvalid : OUT STD_LOGIC;
m_axi_sg_arready : IN STD_LOGIC;
m_axi_sg_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_sg_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_sg_rlast : IN STD_LOGIC;
m_axi_sg_rvalid : IN STD_LOGIC;
m_axi_sg_rready : OUT STD_LOGIC;
m_axi_mm2s_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_mm2s_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_mm2s_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_aruser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_mm2s_arvalid : OUT STD_LOGIC;
m_axi_mm2s_arready : IN STD_LOGIC;
m_axi_mm2s_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_mm2s_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_mm2s_rlast : IN STD_LOGIC;
m_axi_mm2s_rvalid : IN STD_LOGIC;
m_axi_mm2s_rready : OUT STD_LOGIC;
mm2s_prmry_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tvalid : OUT STD_LOGIC;
m_axis_mm2s_tready : IN STD_LOGIC;
m_axis_mm2s_tlast : OUT STD_LOGIC;
m_axis_mm2s_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_tid : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
m_axis_mm2s_tdest : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
mm2s_cntrl_reset_out_n : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_mm2s_cntrl_tkeep : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axis_mm2s_cntrl_tvalid : OUT STD_LOGIC;
m_axis_mm2s_cntrl_tready : IN STD_LOGIC;
m_axis_mm2s_cntrl_tlast : OUT STD_LOGIC;
m_axi_s2mm_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
m_axi_s2mm_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
m_axi_s2mm_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_awvalid : OUT STD_LOGIC;
m_axi_s2mm_awready : IN STD_LOGIC;
m_axi_s2mm_wdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axi_s2mm_wstrb : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
m_axi_s2mm_wlast : OUT STD_LOGIC;
m_axi_s2mm_wvalid : OUT STD_LOGIC;
m_axi_s2mm_wready : IN STD_LOGIC;
m_axi_s2mm_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
m_axi_s2mm_bvalid : IN STD_LOGIC;
m_axi_s2mm_bready : OUT STD_LOGIC;
s2mm_prmry_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tvalid : IN STD_LOGIC;
s_axis_s2mm_tready : OUT STD_LOGIC;
s_axis_s2mm_tlast : IN STD_LOGIC;
s_axis_s2mm_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_tid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s_axis_s2mm_tdest : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s2mm_sts_reset_out_n : OUT STD_LOGIC;
s_axis_s2mm_sts_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_s2mm_sts_tkeep : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axis_s2mm_sts_tvalid : IN STD_LOGIC;
s_axis_s2mm_sts_tready : OUT STD_LOGIC;
s_axis_s2mm_sts_tlast : IN STD_LOGIC;
mm2s_introut : OUT STD_LOGIC;
s2mm_introut : OUT STD_LOGIC;
axi_dma_tstvec : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_dma;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_LITE_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_SG_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_MM2S_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 M_AXI_S2MM_CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF axi_resetn: SIGNAL IS "xilinx.com:signal:reset:1.0 AXI_RESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_lite_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG BREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_sg_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_SG RREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_mm2s_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_MM2S RREADY";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 MM2S_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_mm2s_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_MM2S TLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awlen: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awsize: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awburst: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awcache: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wlast: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WLAST";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM WREADY";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BRESP";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axi_s2mm_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_S2MM BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_prmry_reset_out_n: SIGNAL IS "xilinx.com:signal:reset:1.0 S2MM_PRMRY_RESET_OUT_N RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tkeep: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TKEEP";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_s2mm_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_S2MM TLAST";
ATTRIBUTE X_INTERFACE_INFO OF mm2s_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 MM2S_INTROUT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s2mm_introut: SIGNAL IS "xilinx.com:signal:interrupt:1.0 S2MM_INTROUT INTERRUPT";
BEGIN
U0 : axi_dma
GENERIC MAP (
C_S_AXI_LITE_ADDR_WIDTH => 10,
C_S_AXI_LITE_DATA_WIDTH => 32,
C_DLYTMR_RESOLUTION => 125,
C_PRMRY_IS_ACLK_ASYNC => 0,
C_ENABLE_MULTI_CHANNEL => 0,
C_NUM_MM2S_CHANNELS => 1,
C_NUM_S2MM_CHANNELS => 1,
C_INCLUDE_SG => 1,
C_SG_INCLUDE_STSCNTRL_STRM => 0,
C_SG_USE_STSAPP_LENGTH => 0,
C_SG_LENGTH_WIDTH => 23,
C_M_AXI_SG_ADDR_WIDTH => 32,
C_M_AXI_SG_DATA_WIDTH => 32,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => 32,
C_S_AXIS_S2MM_STS_TDATA_WIDTH => 32,
C_MICRO_DMA => 0,
C_INCLUDE_MM2S => 1,
C_INCLUDE_MM2S_SF => 1,
C_MM2S_BURST_SIZE => 16,
C_M_AXI_MM2S_ADDR_WIDTH => 32,
C_M_AXI_MM2S_DATA_WIDTH => 32,
C_M_AXIS_MM2S_TDATA_WIDTH => 32,
C_INCLUDE_MM2S_DRE => 0,
C_INCLUDE_S2MM => 1,
C_INCLUDE_S2MM_SF => 1,
C_S2MM_BURST_SIZE => 16,
C_M_AXI_S2MM_ADDR_WIDTH => 32,
C_M_AXI_S2MM_DATA_WIDTH => 32,
C_S_AXIS_S2MM_TDATA_WIDTH => 32,
C_INCLUDE_S2MM_DRE => 0,
C_FAMILY => "zynq"
)
PORT MAP (
s_axi_lite_aclk => s_axi_lite_aclk,
m_axi_sg_aclk => m_axi_sg_aclk,
m_axi_mm2s_aclk => m_axi_mm2s_aclk,
m_axi_s2mm_aclk => m_axi_s2mm_aclk,
axi_resetn => axi_resetn,
s_axi_lite_awvalid => s_axi_lite_awvalid,
s_axi_lite_awready => s_axi_lite_awready,
s_axi_lite_awaddr => s_axi_lite_awaddr,
s_axi_lite_wvalid => s_axi_lite_wvalid,
s_axi_lite_wready => s_axi_lite_wready,
s_axi_lite_wdata => s_axi_lite_wdata,
s_axi_lite_bresp => s_axi_lite_bresp,
s_axi_lite_bvalid => s_axi_lite_bvalid,
s_axi_lite_bready => s_axi_lite_bready,
s_axi_lite_arvalid => s_axi_lite_arvalid,
s_axi_lite_arready => s_axi_lite_arready,
s_axi_lite_araddr => s_axi_lite_araddr,
s_axi_lite_rvalid => s_axi_lite_rvalid,
s_axi_lite_rready => s_axi_lite_rready,
s_axi_lite_rdata => s_axi_lite_rdata,
s_axi_lite_rresp => s_axi_lite_rresp,
m_axi_sg_awaddr => m_axi_sg_awaddr,
m_axi_sg_awlen => m_axi_sg_awlen,
m_axi_sg_awsize => m_axi_sg_awsize,
m_axi_sg_awburst => m_axi_sg_awburst,
m_axi_sg_awprot => m_axi_sg_awprot,
m_axi_sg_awcache => m_axi_sg_awcache,
m_axi_sg_awvalid => m_axi_sg_awvalid,
m_axi_sg_awready => m_axi_sg_awready,
m_axi_sg_wdata => m_axi_sg_wdata,
m_axi_sg_wstrb => m_axi_sg_wstrb,
m_axi_sg_wlast => m_axi_sg_wlast,
m_axi_sg_wvalid => m_axi_sg_wvalid,
m_axi_sg_wready => m_axi_sg_wready,
m_axi_sg_bresp => m_axi_sg_bresp,
m_axi_sg_bvalid => m_axi_sg_bvalid,
m_axi_sg_bready => m_axi_sg_bready,
m_axi_sg_araddr => m_axi_sg_araddr,
m_axi_sg_arlen => m_axi_sg_arlen,
m_axi_sg_arsize => m_axi_sg_arsize,
m_axi_sg_arburst => m_axi_sg_arburst,
m_axi_sg_arprot => m_axi_sg_arprot,
m_axi_sg_arcache => m_axi_sg_arcache,
m_axi_sg_arvalid => m_axi_sg_arvalid,
m_axi_sg_arready => m_axi_sg_arready,
m_axi_sg_rdata => m_axi_sg_rdata,
m_axi_sg_rresp => m_axi_sg_rresp,
m_axi_sg_rlast => m_axi_sg_rlast,
m_axi_sg_rvalid => m_axi_sg_rvalid,
m_axi_sg_rready => m_axi_sg_rready,
m_axi_mm2s_araddr => m_axi_mm2s_araddr,
m_axi_mm2s_arlen => m_axi_mm2s_arlen,
m_axi_mm2s_arsize => m_axi_mm2s_arsize,
m_axi_mm2s_arburst => m_axi_mm2s_arburst,
m_axi_mm2s_arprot => m_axi_mm2s_arprot,
m_axi_mm2s_arcache => m_axi_mm2s_arcache,
m_axi_mm2s_arvalid => m_axi_mm2s_arvalid,
m_axi_mm2s_arready => m_axi_mm2s_arready,
m_axi_mm2s_rdata => m_axi_mm2s_rdata,
m_axi_mm2s_rresp => m_axi_mm2s_rresp,
m_axi_mm2s_rlast => m_axi_mm2s_rlast,
m_axi_mm2s_rvalid => m_axi_mm2s_rvalid,
m_axi_mm2s_rready => m_axi_mm2s_rready,
mm2s_prmry_reset_out_n => mm2s_prmry_reset_out_n,
m_axis_mm2s_tdata => m_axis_mm2s_tdata,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid,
m_axis_mm2s_tready => m_axis_mm2s_tready,
m_axis_mm2s_tlast => m_axis_mm2s_tlast,
m_axis_mm2s_cntrl_tready => '0',
m_axi_s2mm_awaddr => m_axi_s2mm_awaddr,
m_axi_s2mm_awlen => m_axi_s2mm_awlen,
m_axi_s2mm_awsize => m_axi_s2mm_awsize,
m_axi_s2mm_awburst => m_axi_s2mm_awburst,
m_axi_s2mm_awprot => m_axi_s2mm_awprot,
m_axi_s2mm_awcache => m_axi_s2mm_awcache,
m_axi_s2mm_awvalid => m_axi_s2mm_awvalid,
m_axi_s2mm_awready => m_axi_s2mm_awready,
m_axi_s2mm_wdata => m_axi_s2mm_wdata,
m_axi_s2mm_wstrb => m_axi_s2mm_wstrb,
m_axi_s2mm_wlast => m_axi_s2mm_wlast,
m_axi_s2mm_wvalid => m_axi_s2mm_wvalid,
m_axi_s2mm_wready => m_axi_s2mm_wready,
m_axi_s2mm_bresp => m_axi_s2mm_bresp,
m_axi_s2mm_bvalid => m_axi_s2mm_bvalid,
m_axi_s2mm_bready => m_axi_s2mm_bready,
s2mm_prmry_reset_out_n => s2mm_prmry_reset_out_n,
s_axis_s2mm_tdata => s_axis_s2mm_tdata,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid,
s_axis_s2mm_tready => s_axis_s2mm_tready,
s_axis_s2mm_tlast => s_axis_s2mm_tlast,
s_axis_s2mm_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axis_s2mm_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 5)),
s_axis_s2mm_sts_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_s2mm_sts_tkeep => X"F",
s_axis_s2mm_sts_tvalid => '0',
s_axis_s2mm_sts_tlast => '0',
mm2s_introut => mm2s_introut,
s2mm_introut => s2mm_introut,
axi_dma_tstvec => axi_dma_tstvec
);
END dma_loopback_axi_dma_0_0_arch;
| mit | 0c849638a60590896c9a2e0bbf041788 | 0.678888 | 2.784039 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_ftch_q_mngr.vhd | 1 | 49,985 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
ch2_sg_idle : in std_logic ;
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic ;
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
signal m_axis_ch2_ftch_tvalid_1 : std_logic := '0';
-- KAPIL
signal ch_desc_flush : std_logic := '0';
signal m_axis_ch_ftch_tready : std_logic := '0';
signal ch_ftch_queue_empty : std_logic := '0';
signal ch_ftch_queue_full : std_logic := '0';
signal ch_ftch_pause : std_logic := '0';
signal ch_writing_curdesc : std_logic := '0';
signal ch_ftch_tready : std_logic := '0';
signal m_axis_ch_ftch_tdata : std_logic_vector (C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_ch_ftch_tvalid : std_logic := '0';
signal m_axis_ch_ftch_tlast : std_logic := '0';
signal data_concat : std_logic_vector (95 downto 0) := (others => '0');
signal data_concat_64 : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_64_cdma : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_mcdma : std_logic_vector (63 downto 0) := (others => '0');
signal next_bd : std_logic_vector (31 downto 0) := (others => '0');
signal data_concat_valid, tvalid_new : std_logic;
signal data_concat_tlast, tlast_new : std_logic;
signal counter : std_logic_vector (C_SG_CH1_WORDS_TO_FETCH-1 downto 0);
signal sof_ftch_desc : std_logic;
signal nxtdesc_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal cyclic_enable : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
cyclic_enable <= ch1_cyclic when ch1_ftch_active = '1' else
ch2_cyclic;
nxtdesc <= nxtdesc_int;
TLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH = 13) generate
-- TLAST is generated when 8th beat is received
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
SOF_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tlast = '1'))then
sof_ftch_desc <= '0';
elsif(counter (6) = '1'
and m_axis_mm2s_tready_i = '1' and m_axis_mm2s_tvalid = '1'
and m_axis_mm2s_tdata(27) = '1' )then
sof_ftch_desc <= '1';
end if;
end if;
end process SOF_CHECK;
end generate TLAST_GEN;
NOTLAST_GEN : if (C_SG_CH1_WORDS_TO_FETCH /= 13) generate
sof_ftch_desc <= '0';
CDMA : if C_ENABLE_CDMA = 1 generate
-- For CDMA TLAST is generated when 7th beat is received
-- because last one is not needed
tlast_new <= counter (6) and m_axis_mm2s_tvalid;
tvalid_new <=counter (6) and m_axis_mm2s_tvalid;
end generate CDMA;
NOCDMA : if C_ENABLE_CDMA = 0 generate
-- For DMA tlast is generated with 8th beat
tlast_new <= counter (7) and m_axis_mm2s_tvalid;
tvalid_new <= counter (7) and m_axis_mm2s_tvalid;
end generate NOCDMA;
end generate NOTLAST_GEN;
-- Following shift register keeps track of number of data beats
-- of BD that is being read
DATA_BEAT_REG : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0' or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1')) then
counter (0) <= '1';
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= (others => '0');
Elsif (m_axis_mm2s_tvalid = '1') then
counter (C_SG_CH1_WORDS_TO_FETCH-1 downto 1) <= counter (C_SG_CH1_WORDS_TO_FETCH-2 downto 0);
counter (0) <= '0';
end if;
end if;
end process DATA_BEAT_REG;
-- Registering the Buffer address from BD, 3rd beat
-- Common for DMA, CDMA
DATA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (31 downto 0) <= (others => '0');
Elsif (counter (2) = '1') then
data_concat (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1;
ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (31 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG1_64;
end generate ADDR_64BIT;
ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG1_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (3) = '1') then
data_concat_64 (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG1_64;
data_concat_64 (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate ADDR_64BIT2;
DMA_REG2 : if C_ENABLE_CDMA = 0 generate
begin
-- For DMA, the 7th beat has the control information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (6) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
end generate DMA_REG2;
CDMA_REG2 : if C_ENABLE_CDMA = 1 generate
begin
-- For CDMA, the 5th beat has the DA information
DATA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (63 downto 32) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2;
CDMA_ADDR_64BIT : if C_ACTUAL_ADDR = 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (31 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_REG2_64;
end generate CDMA_ADDR_64BIT;
CDMA_ADDR_64BIT2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
DATA_REG2_64 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_64_cdma (C_ACTUAL_ADDR-32-1 downto 0) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
end if;
end if;
end process DATA_REG2_64;
data_concat_64_cdma (31 downto C_ACTUAL_ADDR-32) <= (others => '0');
end generate CDMA_ADDR_64BIT2;
end generate CDMA_REG2;
NOFLOP_FOR_QUEUE : if C_SG_CH1_WORDS_TO_FETCH = 8 generate
begin
-- Last beat is directly concatenated and passed to FIFO
-- Masking the CMPLT bit with cyclic_enable
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end generate NOFLOP_FOR_QUEUE;
-- In absence of queuing option the last beat needs to be floped
FLOP_FOR_NOQUEUE : if C_SG_CH1_WORDS_TO_FETCH = 13 generate
begin
NO_FETCH_Q : if C_SG_FTCH_DESC2QUEUE = 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95 downto 64) <= (others => '0');
Elsif (counter (7) = '1') then
data_concat (95 downto 64) <= (m_axis_mm2s_tdata(31) and (not cyclic_enable)) & m_axis_mm2s_tdata (30 downto 0);
end if;
end if;
end process DATA_REG3;
end generate NO_FETCH_Q;
FETCH_Q : if C_SG_FTCH_DESC2QUEUE /= 0 generate
DATA_REG3 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat (95) <= '0';
Elsif (counter (7) = '1') then
data_concat (95) <= m_axis_mm2s_tdata (31) and (not cyclic_enable);
end if;
end if;
end process DATA_REG3;
data_concat (94 downto 64) <= (others => '0');
end generate FETCH_Q;
DATA_CNTRL : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_valid <= '0';
data_concat_tlast <= '0';
Else
data_concat_valid <= tvalid_new;
data_concat_tlast <= tlast_new;
end if;
end if;
end process DATA_CNTRL;
end generate FLOP_FOR_NOQUEUE;
-- Since the McDMA BD has two more fields to be captured
-- following procedures are needed
NOMCDMA_FTECH : if C_ENABLE_MULTI_CHANNEL = 0 generate
begin
data_concat_mcdma <= (others => '0');
end generate NOMCDMA_FTECH;
MCDMA_BD_FETCH : if C_ENABLE_MULTI_CHANNEL = 1 generate
begin
DATA_MCDMA_REG1 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (31 downto 0) <= (others => '0');
Elsif (counter (4) = '1') then
data_concat_mcdma (31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG1;
DATA_MCDMA_REG2 : process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
data_concat_mcdma (63 downto 32) <= (others => '0');
Elsif (counter (5) = '1') then
data_concat_mcdma (63 downto 32) <= m_axis_mm2s_tdata;
end if;
end if;
end process DATA_MCDMA_REG2;
end generate MCDMA_BD_FETCH;
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (0) = '1')then
nxtdesc_int(31 downto 6) <= m_axis_mm2s_tdata (31 downto 6);
-- BD addresses are always 16 word 32-bit aligned
nxtdesc_int(5 downto 0) <= (others => '0');
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (0) = '1' --etch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_ACTUAL_ADDR = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
GEN_UPPER_MSB_NXTDESC2 : if C_ACTUAL_ADDR > 32 and C_ACTUAL_ADDR < 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then -- etch_word_count = WORD_ONE)then
nxtdesc_int(C_ACTUAL_ADDR-1 downto 32) <= m_axis_mm2s_tdata (C_ACTUAL_ADDR-32-1 downto 0);
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
nxtdesc_int (63 downto C_ACTUAL_ADDR) <= (others => '0');
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC2;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and counter (1) = '1') then --fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and counter (1) = '1' --fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and counter (7) = '1' --fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1' and (not cyclic_enable);
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_sg_v4_1_3.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_INCLUDE_MM2S => C_INCLUDE_CH1,
C_INCLUDE_S2MM => C_INCLUDE_CH2,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => '0' ,
-- Channel Control
desc1_flush => ch1_desc_flush ,
desc2_flush => ch2_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch1_active => ch1_ftch_active ,
ftch2_active => ch2_ftch_active ,
ftch1_queue_empty => ch1_ftch_queue_empty ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch1_queue_full => ch1_ftch_queue_full ,
ftch2_queue_full => ch2_ftch_queue_full ,
ftch1_pause => ch1_ftch_pause ,
ftch2_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing1_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat_64_cdma => data_concat_64_cdma,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
m_axis1_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axi_sg_aclk, --m_axis_ch_ftch_aclk ,
m_axis_ftch1_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch1_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch1_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch1_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch1_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch1_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch1_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
m_axis_ftch2_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ftch2_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ftch2_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
m_axis_ftch2_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch2_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch2_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch2_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
m_axis_ch2_ftch_tdata_mcdma_nxt <= (others => '0');
end generate GEN_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_sg_v4_1_3.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_FAMILY => C_FAMILY ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ENABLE_CH1 => C_INCLUDE_CH1
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_primary_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
desc2_flush => ch2_desc_flush ,
ftch2_active => ch2_ftch_active ,
ftch2_queue_empty => ch2_ftch_queue_empty ,
ftch2_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
writing2_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
m_axis2_mm2s_tready => ch2_ftch_tready ,
sof_ftch_desc => sof_ftch_desc ,
next_bd => nxtdesc_int ,
data_concat_64 => data_concat_64,
data_concat => data_concat,
data_concat_mcdma => data_concat_mcdma,
data_concat_valid => data_concat_valid,
data_concat_tlast => data_concat_tlast,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch_desc_available => m_axis_ftch1_desc_available ,
m_axis2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis2_ftch_desc_available => m_axis_ftch2_desc_available ,
m_axis2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
ch1_ftch_pause <= '0';
ch2_ftch_pause <= '0';
end generate GEN_NO_QUEUE;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
counter(0),
counter(1),
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(counter(0) = '1' or counter(1)='1')then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
| mit | 3d245017328c560d06874528c0b8b979 | 0.436951 | 4.164029 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/gencomp/gencomp.vhd | 1 | 5,247 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Definition of the gencomp package.
--! @details This file defines constants that are used to enable/disable
--! target dependable modules.
--! This file inherits values from the \e grlib library that
--! that are published under GPL license. All unused values may
--! freely removed or reassigned on others values.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! @brief Technologies names definition
--! @details This package must be built first in a case of manual compilation
--! order (\e ModelSim).
package gencomp is
--! @brief Total number of the known technologies.
--! @details These values was inherited from the \e grlib library.
constant NTECH : integer := 53;
--! Prototype of the data type for mapping name on certain index.
type tech_ability_type is array (0 to NTECH) of integer;
--! @name Techologies names.
--! @brief Set of the predefined technology names.
--! @{
constant inferred : integer := 0; --! Behaviour simulation target.
constant virtex : integer := 1; --! Not implemented.
constant virtex2 : integer := 2; --! Not implemented.
constant memvirage : integer := 3; --! Not implemented.
constant axcel : integer := 4; --! Not implemented.
constant proasic : integer := 5; --! Not implemented.
constant atc18s : integer := 6; --! Not implemented.
constant altera : integer := 7; --! Not implemented.
constant umc : integer := 8; --! Not implemented.
constant rhumc : integer := 9; --! Not implemented.
constant apa3 : integer := 10; --! Not implemented.
constant spartan3 : integer := 11; --! Not implemented.
constant ihp25 : integer := 12; --! Not implemented.
constant rhlib18t : integer := 13; --! Not implemented.
constant virtex4 : integer := 14; --! Not implemented.
constant lattice : integer := 15; --! Not implemented.
constant ut25 : integer := 16; --! Not implemented.
constant spartan3e : integer := 17; --! Not implemented.
constant peregrine : integer := 18; --! Not implemented.
constant memartisan : integer := 19; --! Not implemented.
constant virtex5 : integer := 20; --! Not implemented.
constant custom1 : integer := 21; --! Not implemented.
constant ihp25rh : integer := 22; --! Not implemented.
constant stratix1 : integer := 23; --! Not implemented.
constant stratix2 : integer := 24; --! Not implemented.
constant eclipse : integer := 25; --! Not implemented.
constant stratix3 : integer := 26; --! Not implemented.
constant cyclone3 : integer := 27; --! Not implemented.
constant memvirage90 : integer := 28; --! Not implemented.
constant tsmc90 : integer := 29; --! Not implemented.
constant easic90 : integer := 30; --! Not implemented.
constant atc18rha : integer := 31; --! Not implemented.
constant smic013 : integer := 32; --! Not implemented.
constant tm65gpl : integer := 33; --! Not implemented.
constant axdsp : integer := 34; --! Not implemented.
constant spartan6 : integer := 35; --! Supported. Use files with the '_s6' suffix.
constant virtex6 : integer := 36; --! Supported. Use files with the '_v6' suffix.
constant actfus : integer := 37; --! Not implemented.
constant stratix4 : integer := 38; --! Not implemented.
constant st65lp : integer := 39; --! Not implemented.
constant st65gp : integer := 40; --! Not implemented.
constant easic45 : integer := 41; --! Not implemented.
constant cmos9sf : integer := 42; --! Not implemented.
constant apa3e : integer := 43; --! Not implemented.
constant apa3l : integer := 44; --! Not implemented.
constant ut130 : integer := 45; --! Not implemented.
constant ut90 : integer := 46; --! Not implemented.
constant gf65 : integer := 47; --! Not implemented.
constant virtex7 : integer := 48; --! Not implemented.
constant kintex7 : integer := 49; --! Supported. Use files with the '_k7' suffix.
constant artix7 : integer := 50; --! Not implemented.
constant zynq7000 : integer := 51; --! Not implemented.
constant rhlib13t : integer := 52; --! Not implemented.
constant mikron180 : integer := 53; --! Mikron 180nm. Use files with the '_micron180' suffix.
--! @}
--! @name FPGAs technologies group.
--! @details It is convinient sometimes to implement one module for a group of
--! technologies, this array specifies FPGA group.
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
end;
| apache-2.0 | 013f520dec736caaf8289f45235d4f22 | 0.625119 | 4.099219 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/grethc64.vhd | 1 | 77,538 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grethc
-- File: grethc.vhd
-- Author: Marko Isomaki
-- Description: Ethernet Media Access Controller with Ethernet Debug
-- Communication Link
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library techmap;
use techmap.gencomp.all;
use techmap.types_mem.all;
library ethlib;
use ethlib.types_eth.all;
entity grethc64 is
generic(
memtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 512 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
edclsepahbg : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ctrli : in eth_control_type;
cmdi : in eth_command_type;
statuso : out eth_mac_status_type;
--! Debug value read from internal buffers suing external bus interface
rdbgdatao : out std_logic_vector(31 downto 0);
--irq
irq : out std_logic;
--ethernet input signals
rmii_clk : in std_ulogic;
tx_clk : in std_ulogic;
rx_clk : in std_ulogic;
tx_dv : in std_ulogic;
rxd : in std_logic_vector(3 downto 0);
rx_dv : in std_ulogic;
rx_er : in std_ulogic;
rx_col : in std_ulogic;
rx_en : in std_ulogic;
rx_crs : in std_ulogic;
mdio_i : in std_ulogic;
phyrstaddr : in std_logic_vector(4 downto 0);
mdint : in std_ulogic;
--ethernet output signals
reset : out std_ulogic;
txd : out std_logic_vector(3 downto 0);
tx_en : out std_ulogic;
tx_er : out std_ulogic;
mdc : out std_ulogic;
mdio_o : out std_ulogic;
mdio_oe : out std_ulogic;
--scantest
testrst : in std_ulogic;
testen : in std_ulogic;
testoen : in std_ulogic;
edcladdr : in std_logic_vector(3 downto 0) := "0000";
edclsepahb : in std_ulogic;
edcldisable : in std_ulogic;
speed : out std_ulogic;
tmsto : out eth_tx_ahb_in_type;
tmsti : in eth_tx_ahb_out_type;
tmsto2 : out eth_tx_ahb_in_type;
tmsti2 : in eth_tx_ahb_out_type;
rmsto : out eth_rx_ahb_in_type;
rmsti : in eth_rx_ahb_out_type
);
end entity;
architecture rtl of grethc64 is
procedure sel_op_mode(
capbil : in std_logic_vector(4 downto 0);
speed : out std_ulogic;
duplex : out std_ulogic) is
variable vspeed : std_ulogic;
variable vduplex : std_ulogic;
begin
vspeed := '0'; vduplex := '0';
vspeed := capbil(4) or capbil(3) or capbil(2);
vduplex := (vspeed and capbil(3)) or ((not vspeed) and capbil(1));
speed := vspeed;
duplex := vduplex;
end procedure;
--host constants
constant fabits : integer := log2(fifosize);
constant burstlength : integer := setburstlength(fifosize);
constant burstbits : integer := log2(burstlength);
constant ctrlopcode : std_logic_vector(15 downto 0) := X"8808";
constant broadcast : std_logic_vector(47 downto 0) := X"FFFFFFFFFFFF";
-- constant maxsizetx : integer := 1514;
constant index : integer := log2(edclbufsz);
constant receiveOK : std_logic_vector(3 downto 0) := "0000";
constant frameCheckError : std_logic_vector(3 downto 0) := "0100";
constant alignmentError : std_logic_vector(3 downto 0) := "0001";
constant frameTooLong : std_logic_vector(3 downto 0) := "0010";
constant overrun : std_logic_vector(3 downto 0) := "1000";
constant minpload : std_logic_vector(10 downto 0) :=
conv_std_logic_vector(60, 11);
--mdio constants
constant divisor : std_logic_vector(7 downto 0) :=
conv_std_logic_vector(mdcscaler, 8);
--receiver constants
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--tranceiver constants
constant maxsizetx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18 - 4, 16);
--edcl constants
type szvct is array (0 to 6) of integer;
constant ebuf : szvct := (64, 128, 128, 256, 256, 256, 256);
constant blbits : szvct := (6, 7, 7, 8, 8, 8, 8);
constant winsz : szvct := (4, 4, 8, 8, 16, 32, 64);
constant macaddrt : std_logic_vector(47 downto 0) :=
conv_std_logic_vector(macaddrh, 24) & conv_std_logic_vector(macaddrl, 24);
constant bpbits : integer := blbits(log2(edclbufsz));
constant wsz : integer := winsz(log2(edclbufsz));
constant bselbits : integer := log2(wsz);
constant eabits: integer := log2(edclbufsz) + 8;
constant ebufmax : std_logic_vector(bpbits-1 downto 0) := (others => '1');
constant bufsize : std_logic_vector(2 downto 0) :=
conv_std_logic_vector(log2(edclbufsz), 3);
constant ebufsize : integer := ebuf(log2(edclbufsz));
constant txfifosize : integer := getfifosize(edcl, fifosize, ebufsize);
constant txfabits : integer := log2(txfifosize);
constant txfifosizev : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(txfifosize, txfabits+1);
constant rxburstlen : std_logic_vector(fabits downto 0) :=
conv_std_logic_vector(burstlength, fabits+1);
constant txburstlen : std_logic_vector(txfabits downto 0) :=
conv_std_logic_vector(burstlength, txfabits+1);
type edclrstate_type is (idle, wrda, wrdsa, wrsa, wrtype, ip, ipdata,
oplength, arp, iplength, ipcrc, arpop, udp, spill);
type duplexstate_type is (start, waitop, nextop, selmode, done);
--host types
type txd_state_type is (idle, read_desc, check_desc, req, fill_fifo,
check_result, write_result, readhdr, start, wrbus1,
etdone, getlen, ahberror, fill_fifo2, wrbus2);
type rxd_state_type is (idle, read_desc, check_desc, read_req, read_fifo,
discard, write_status, write_status2);
--mdio types
type mdio_state_type is (idle, preamble, startst, op, op2, phyadr, regadr,
ta, ta2, ta3, data, dataend);
type fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(fabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(fabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(txfabits-1 downto 0);
write : std_ulogic;
waddress : std_logic_vector(txfabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type tx_fifo_access_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type edcl_ram_in_type is record
renable : std_ulogic;
raddress : std_logic_vector(eabits-1 downto 0);
writem : std_ulogic;
writel : std_ulogic;
waddressm : std_logic_vector(eabits-1 downto 0);
waddressl : std_logic_vector(eabits-1 downto 0);
datain : std_logic_vector(31 downto 0);
end record;
type edcl_ram_out_type is record
data : std_logic_vector(31 downto 0);
end record;
type reg_type is record
--user registers
status : eth_mac_status_type;
--master tx interface
tmsto : eth_tx_ahb_in_type;
tmsto2 : eth_tx_ahb_in_type;
txdstate : txd_state_type;
txwrap : std_ulogic;
txden : std_ulogic;
txirq : std_ulogic;
txaddr : std_logic_vector(31 downto 2);
txlength : std_logic_vector(10 downto 0);
txburstcnt : std_logic_vector(burstbits downto 0);
tfwpnt : std_logic_vector(txfabits-1 downto 0);
tfrpnt : std_logic_vector(txfabits-1 downto 0);
tfcnt : std_logic_vector(txfabits downto 0);
txcnt : std_logic_vector(10 downto 0);
txstart : std_ulogic;
txirqgen : std_ulogic;
txstatus : std_logic_vector(1 downto 0);
txvalid : std_ulogic;
txdata : std_logic_vector(31 downto 0);
writeok : std_ulogic;
txread : std_logic_vector(nsync-1 downto 0);
txrestart : std_logic_vector(nsync downto 0);
txdone : std_logic_vector(nsync downto 0);
txstart_sync : std_ulogic;
txreadack : std_ulogic;
txdataav : std_ulogic;
txburstav : std_ulogic;
--master rx interface
rxrenable : std_ulogic;
rmsto : eth_rx_ahb_in_type;
rxdstate : rxd_state_type;
rxstatus : std_logic_vector(4 downto 0);
rxaddr : std_logic_vector(31 downto 2);
rxlength : std_logic_vector(10 downto 0);
rxbytecount : std_logic_vector(10 downto 0);
rxwrap : std_ulogic;
rxirq : std_ulogic;
rfwpnt : std_logic_vector(fabits-1 downto 0);
rfrpnt : std_logic_vector(fabits-1 downto 0);
rfcnt : std_logic_vector(fabits downto 0);
rxcnt : std_logic_vector(10 downto 0);
rxdoneold : std_ulogic;
rxdoneack : std_ulogic;
rxdone : std_logic_vector(nsync-1 downto 0);
rxstart : std_logic_vector(nsync downto 0);
rxwrite : std_logic_vector(nsync-1 downto 0);
rxwriteack : std_ulogic;
rxburstcnt : std_logic_vector(burstbits downto 0);
addrok : std_ulogic;
addrdone : std_ulogic;
ctrlpkt : std_ulogic;
check : std_ulogic;
checkdata : std_logic_vector(31 downto 0);
usesizefield : std_ulogic;
rxden : std_ulogic;
gotframe : std_ulogic;
bcast : std_ulogic;
msbgood : std_ulogic;
rxburstav : std_ulogic;
hashlookup : std_ulogic;
mcast : std_ulogic;
mcastacc : std_ulogic;
--mdio
mdccnt : std_logic_vector(7 downto 0);
mdioclk : std_ulogic;
mdioclkold : std_logic_vector(mdiohold-1 downto 0);
mdio_state : mdio_state_type;
mdioo : std_ulogic;
mdioi : std_ulogic;
mdioen : std_ulogic;
cnt : std_logic_vector(4 downto 0);
duplexstate : duplexstate_type;
init_busy : std_ulogic;
ext : std_ulogic;
extcap : std_ulogic;
regaddr : std_logic_vector(4 downto 0);
phywr : std_ulogic;
rstphy : std_ulogic;
capbil : std_logic_vector(4 downto 0);
rstaneg : std_ulogic;
mdint_sync : std_logic_vector(2 downto 0);
--edcl
erenable : std_ulogic;
edclrstate : edclrstate_type;
edclactive : std_ulogic;
nak : std_ulogic;
ewr : std_ulogic;
write : std_logic_vector(wsz-1 downto 0);
seq : std_logic_vector(13 downto 0);
abufs : std_logic_vector(bselbits downto 0);
tpnt : std_logic_vector(bselbits-1 downto 0);
rpnt : std_logic_vector(bselbits-1 downto 0);
tcnt : std_logic_vector(bpbits-1 downto 0);
rcntm : std_logic_vector(bpbits-1 downto 0);
rcntl : std_logic_vector(bpbits-1 downto 0);
ipcrc : std_logic_vector(17 downto 0);
applength : std_logic_vector(15 downto 0);
oplen : std_logic_vector(9 downto 0);
udpsrc : std_logic_vector(15 downto 0);
ecnt : std_logic_vector(3 downto 0);
tarp : std_ulogic;
tnak : std_ulogic;
tedcl : std_ulogic;
edclbcast : std_ulogic;
edclsepahb : std_ulogic;
end record;
--host signals
signal arst : std_ulogic;
signal irst : std_ulogic;
signal vcc : std_ulogic;
signal txi : host_tx_type;
signal txo : tx_host_type;
signal rxi : host_rx_type;
signal rxo : rx_host_type;
--rx ahb fifo
signal rxrenable : std_ulogic;
signal rxraddress : std_logic_vector(10 downto 0);
signal rxwrite : std_ulogic;
signal rxwdata : std_logic_vector(31 downto 0);
signal rxwaddress : std_logic_vector(10 downto 0);
signal rxrdata : std_logic_vector(31 downto 0);
--tx ahb fifo
signal txrenable : std_ulogic;
signal txraddress : std_logic_vector(10 downto 0);
signal txwrite : std_ulogic;
signal txwdata : std_logic_vector(31 downto 0);
signal txwaddress : std_logic_vector(10 downto 0);
signal txrdata : std_logic_vector(31 downto 0);
--edcl buf
signal erenable : std_ulogic;
signal eraddress : std_logic_vector(15 downto 0);
signal ewritem : std_ulogic;
signal ewritel : std_ulogic;
signal ewaddressm : std_logic_vector(15 downto 0);
signal ewaddressl : std_logic_vector(15 downto 0);
signal ewdata : std_logic_vector(31 downto 0);
signal erdata : std_logic_vector(31 downto 0);
signal r, rin : reg_type;
begin
--reset generators for transmitter and receiver
vcc <= '1';
arst <= testrst when (scanen = 1) and (testen = '1')
else rst and not r.status.reset;
irst <= rst and not r.status.reset;
comb : process(rst, irst, ctrli, cmdi, r, rmsti, tmsti, txo, rxo,
erdata, rxrdata, txrdata, mdio_i, phyrstaddr,
testen, testrst, edcladdr, mdint, tmsti2, edcldisable,
edclsepahb) is
variable v : reg_type;
variable vpirq : std_ulogic;
variable vrdbgdata : std_logic_vector(31 downto 0);
variable txvalid : std_ulogic;
variable vtxfi : tx_fifo_access_in_type;
variable vrxfi : fifo_access_in_type;
variable lengthav : std_ulogic;
variable txdone : std_ulogic;
variable txread : std_ulogic;
variable txrestart : std_ulogic;
variable rxstart : std_ulogic;
variable rxdone : std_ulogic;
variable vrxwrite : std_ulogic;
variable ovrunstop : std_ulogic;
--mdio
variable mdioindex : integer range 0 to 31;
variable mclk : std_ulogic; --rising mdio clk edge
variable nmclk : std_ulogic; --falling mdio clk edge
variable mclkvec : std_logic_vector(mdiohold downto 0);
--edcl
variable veri : edcl_ram_in_type;
variable swap : std_ulogic;
variable setmz : std_ulogic;
variable ipcrctmp : std_logic_vector(15 downto 0);
variable ipcrctmp2 : std_logic_vector(17 downto 0);
variable vrxenable : std_ulogic;
variable crctmp : std_ulogic;
variable vecnt : integer;
begin
v := r; vrdbgdata := (others => '0'); vpirq := '0';
v.check := '0'; lengthav := r.rxdoneold;-- or r.usesizefield;
ovrunstop := '0'; vrxfi.raddress := v.rfrpnt;
if edcl /= 0 then
veri.renable := r.erenable;
veri.datain := rxo.dataout;
veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
end if;
vtxfi.renable := '0';
vtxfi.datain := tmsti.data;
vtxfi.raddress := r.tfrpnt; vtxfi.write := '0';
vtxfi.waddress := r.tfwpnt;
vrxfi.datain := rxo.dataout;
vrxfi.write := '0'; vrxfi.waddress := r.rfwpnt;
vrxfi.renable := r.rxrenable; vrxenable := r.status.rxen;
--synchronization
v.txdone(0) := txo.done;
v.txread(0) := txo.read;
v.txrestart(0) := txo.restart;
v.rxstart(0) := rxo.start;
v.rxdone(0) := rxo.done;
v.rxwrite(0) := rxo.write;
if nsync = 2 then
v.txdone(1) := r.txdone(0);
v.txread(1) := r.txread(0);
v.txrestart(1) := r.txrestart(0);
v.rxstart(1) := r.rxstart(0);
v.rxdone(1) := r.rxdone(0);
v.rxwrite(1) := r.rxwrite(0);
end if;
if enable_mdint = 1 then
v.mdint_sync(0) := mdint;
v.mdint_sync(1) := r.mdint_sync(0);
v.mdint_sync(2) := r.mdint_sync(1);
end if;
txdone := r.txdone(nsync) xor r.txdone(nsync-1);
txread := r.txreadack xor r.txread(nsync-1);
txrestart := r.txrestart(nsync) xor r.txrestart(nsync-1);
rxstart := r.rxstart(nsync) xor r.rxstart(nsync-1);
rxdone := r.rxdoneack xor r.rxdone(nsync-1);
vrxwrite := r.rxwriteack xor r.rxwrite(nsync-1);
if txdone = '1' then
v.txstatus := txo.status;
end if;
-------------------------------------------------------------------------------
-- HOST INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--SLAVE INTERFACE
if cmdi.set_speed = '1' then v.status.speed := '1';
elsif cmdi.clr_speed = '1' then v.status.speed := '0';
end if;
if cmdi.set_reset = '1' then v.status.reset := '1';
elsif cmdi.clr_reset = '1' then v.status.reset := '0';
end if;
if cmdi.set_full_duplex = '1' then v.status.full_duplex := '1';
elsif cmdi.clr_full_duplex = '1' then v.status.full_duplex := '0';
end if;
if cmdi.set_rxena = '1' then v.status.rxen := '1';
elsif cmdi.clr_rxena = '1' then v.status.rxen := '0';
end if;
if cmdi.set_txena = '1' then v.status.txen := '1';
elsif cmdi.clr_txena = '1' then v.status.txen := '0';
end if;
if cmdi.clr_status_phystat = '1' then v.status.phystat := '0'; end if;
if cmdi.clr_status_invaddr = '1' then v.status.invaddr := '0'; end if;
if cmdi.clr_status_toosmall = '1' then v.status.toosmall := '0'; end if;
if cmdi.clr_status_txahberr = '1' then v.status.txahberr := '0'; end if;
if cmdi.clr_status_rxahberr = '1' then v.status.rxahberr := '0'; end if;
if cmdi.clr_status_tx_int = '1' then v.status.tx_int := '0'; end if;
if cmdi.clr_status_rx_int = '1' then v.status.rx_int := '0'; end if;
if cmdi.clr_status_tx_err = '1' then v.status.tx_err := '0'; end if;
if cmdi.clr_status_rx_err = '1' then v.status.rx_err := '0'; end if;
if cmdi.mdio_cmd.valid = '1' then
v.status.mdio.cmd.data := cmdi.mdio_cmd.data;
v.status.mdio.cmd.regadr := cmdi.mdio_cmd.regadr;
v.status.mdio.cmd.read := cmdi.mdio_cmd.read;
v.status.mdio.cmd.write := cmdi.mdio_cmd.write;
v.status.mdio.busy := cmdi.mdio_cmd.read or cmdi.mdio_cmd.write;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_TX_BUFFER then
vtxfi.write := cmdi.dbg_wr_ena;
vtxfi.waddress := cmdi.dbg_addr(txfabits+1 downto 2);
vtxfi.datain := cmdi.dbg_wdata;
vtxfi.raddress := cmdi.dbg_addr(txfabits+1 downto 2);
vtxfi.renable := cmdi.dbg_rd_ena;
vrdbgdata := txrdata;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_RX_BUFFER then
vrxfi.write := cmdi.dbg_wr_ena;
vrxfi.waddress := cmdi.dbg_addr(fabits+1 downto 2);
vrxfi.datain := cmdi.dbg_wdata;
vrxfi.raddress := cmdi.dbg_addr(fabits+1 downto 2);
vrxfi.renable := cmdi.dbg_rd_ena;
vrdbgdata := rxrdata;
end if;
if cmdi.dbg_access_id = DBG_ACCESS_EDCL_BUFFER then
veri.writem := cmdi.dbg_wr_ena;
veri.writel := cmdi.dbg_wr_ena;
veri.waddressm := cmdi.dbg_addr(eabits+1 downto 2);
veri.waddressl := cmdi.dbg_addr(eabits+1 downto 2);
veri.datain := cmdi.dbg_wdata;
veri.raddress := cmdi.dbg_addr(eabits+1 downto 2);
veri.renable := cmdi.dbg_rd_ena;
vrdbgdata := erdata;
end if;
--PHY STATUS DETECTION
if enable_mdint = 1 then
if mdint_pol = 0 then
if (r.mdint_sync(2) and not r.mdint_sync(1)) = '1' then
v.status.phystat := '1';
if ctrli.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
else
if (r.mdint_sync(1) and not r.mdint_sync(2)) = '1' then
v.status.phystat := '1';
if ctrli.pstatirqen = '1' then
vpirq := '1';
end if;
end if;
end if;
end if;
--MASTER INTERFACE
v.txburstav := '0';
if (txfifosizev - r.tfcnt) >= txburstlen then
v.txburstav := '1';
end if;
if (conv_integer(r.abufs) /= 0) then
v.status.edcltx_idle := '0';
else
v.status.edcltx_idle := '1';
end if;
--tx dma fsm
case r.txdstate is
when idle =>
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
if (edcl /= 0) then
v.tedcl := '0'; v.erenable := '0';
end if;
if (edcl /= 0) and (conv_integer(r.abufs) /= 0) and
(ctrli.edcldis = '0') then
v.erenable := '1'; v.status.edcltx_idle := '0';
if r.erenable = '1' then
v.txdstate := getlen;
end if;
v.tcnt := conv_std_logic_vector(10, bpbits);
elsif r.status.txen = '1' then
v.txdstate := read_desc;
v.tmsto.write := '0';
v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.req := '1';
--! AXI_ENABLE: burst transaction size in bytes
v.tmsto.burst_bytes := conv_std_logic_vector(8, 11);
end if;
if r.txirqgen = '1' then
vpirq := '1'; v.txirqgen := '0';
end if;
if txrestart = '1' then
v.txrestart(nsync) := r.txrestart(nsync-1);
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
end if;
when read_desc =>
v.tmsto.write := '0'; v.txstatus := (others => '0');
v.tfwpnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfcnt := (others => '0');
if tmsti.grant = '1' then
v.txburstcnt := r.txburstcnt + 1; v.tmsto.addr := r.tmsto.addr + 4;
if r.txburstcnt(0) = '1' then
v.tmsto.req := '0';
end if;
end if;
if tmsti.ready = '1' then
v.txcnt := r.txcnt + 1;
case r.txcnt(1 downto 0) is
when "00" =>
v.txlength := tmsti.data(10 downto 0);
v.txden := tmsti.data(11);
v.txwrap := tmsti.data(12);
v.txirq := tmsti.data(13);
v.status.txen := tmsti.data(11);
when "01" =>
v.txaddr := tmsti.data(31 downto 2);
v.txdstate := check_desc;
when others => null;
end case;
end if;
when check_desc =>
v.txstart := '0';
v.txburstcnt := (others => '0');
if r.txden = '1' then
if (unsigned(r.txlength) > unsigned(maxsizetx)) or
(conv_integer(r.txlength) = 0) then
v.txdstate := write_result;
v.tmsto.req := '1';
v.tmsto.write := '1';
v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.data := (others => '0');
--! AXI_ENABLE: length of transaction not defined so use simple DMA access
v.tmsto.burst_bytes := conv_std_logic_vector(4,11);
else
v.txdstate := req;
v.tmsto.addr := r.txaddr & "00";
v.txcnt(10 downto 0) := r.txlength;
--! AXI_ENABLE: length of transaction defined
v.tmsto.burst_bytes := r.txlength;
end if;
else
v.txdstate := idle;
end if;
when req =>
if txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := idle;
end if;
elsif txdone = '1' then
v.txdstate := check_result;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone;
end if;
elsif conv_integer(r.txcnt) = 0 then
v.txdstate := check_result;
if (edcl /= 0) and (r.tedcl = '1') then
v.txdstate := etdone; v.txstart_sync := not r.txstart_sync;
end if;
elsif (r.txburstav = '1') or (r.tedcl = '1') then
if (edclsepahbg = 0) or (edcl = 0) or
(r.edclsepahb = '0') or (r.tedcl = '0') then
v.tmsto.req := '1'; v.txdstate := fill_fifo;
else
v.tmsto2.req := '1'; v.txdstate := fill_fifo2;
end if;
end if;
v.txburstcnt := (others => '0');
when fill_fifo =>
v.txburstav := '0';
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) then
v.tmsto.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
when fill_fifo2 =>
if edclsepahbg = 1 then
v.txburstav := '0';
vtxfi.datain := tmsti2.data;
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) or
((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) then
v.tmsto2.req := '0';
end if;
v.txburstcnt := r.txburstcnt + 1;
if (conv_integer(r.txburstcnt) = burstlength-1) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready = '1') or ((edcl /= 0) and (r.tedcl and tmsti2.error) = '1') then
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := r.tfcnt + 1; vtxfi.write := '1';
if r.tmsto2.req = '0' then
v.txdstate := req;
if (r.txstart = '0') and not ((edcl /= 0) and (r.tedcl = '1')) then
v.txstart := '1'; v.txstart_sync := not r.txstart_sync;
end if;
end if;
if conv_integer(r.txcnt) > 3 then
v.txcnt := r.txcnt - 4;
else
v.txcnt := (others => '0');
end if;
end if;
end if;
when check_result =>
if txdone = '1' then
v.txdstate := write_result; v.tmsto.req := '1'; v.txstart := '0';
v.tmsto.write := '1'; v.tmsto.addr := ctrli.txdesc & r.status.txdsel & "000";
v.tmsto.data(31 downto 16) := (others => '0');
v.tmsto.data(15 downto 14) := v.txstatus;
v.tmsto.data(13 downto 0) := (others => '0');
v.txdone(nsync) := r.txdone(nsync-1);
elsif txrestart = '1' then
v.txdstate := idle; v.txstart := '0';
end if;
when write_result =>
if tmsti.grant = '1' then
v.tmsto.req := '0'; v.tmsto.addr := r.tmsto.addr + 4;
end if;
if tmsti.ready = '1' then
v.txdstate := idle;
v.txirqgen := ctrli.tx_irqen and r.txirq;
if r.txwrap = '0' then v.status.txdsel := r.status.txdsel + 1;
else v.status.txdsel := (others => '0'); end if;
if conv_integer(r.txstatus) = 0 then v.status.tx_int := '1';
else v.status.tx_err := '1'; end if;
end if;
when ahberror =>
v.tfcnt := (others => '0'); v.tfwpnt := (others => '0');
v.tfrpnt := (others => '0');
v.status.txahberr := '1'; v.status.txen := '0';
if not ((edcl /= 0) and (r.tedcl = '1')) then
if r.txstart = '1' then
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
end if;
else
v.txdstate := idle;
end if;
else
v.txdstate := idle;
v.abufs := r.abufs - 1; v.tpnt := r.tpnt + 1;
end if;
when others =>
null;
end case;
--tx fifo read
v.txdataav := '0';
if conv_integer(r.tfcnt) /= 0 then
v.txdataav := '1';
end if;
if txread = '1' then
v.txreadack := not r.txreadack;
if r.txdataav = '1' then
if conv_integer(r.tfcnt) < 2 then
v.txdataav := '0';
end if;
v.txvalid := '1';
v.tfcnt := v.tfcnt - 1; v.tfrpnt := r.tfrpnt + 1;
else
v.txvalid := '0';
end if;
v.txdata := txrdata;
end if;
v.rxburstav := '0';
if r.rfcnt >= rxburstlen then
v.rxburstav := '1';
end if;
if ramdebug = 0 then
vtxfi.renable := v.txdataav;
else
vtxfi.renable := vtxfi.renable or v.txdataav;
end if;
--rx dma fsm
case r.rxdstate is
when idle =>
v.rmsto.req := '0'; v.rmsto.write := '0'; v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
if r.status.rxen = '1' then
v.rxdstate := read_desc;
v.rmsto.req := '1';
v.rmsto.addr := ctrli.rxdesc & r.status.rxdsel & "000";
--! AXI_ENABLE: burst transaction descriptor header size in bytes
v.rmsto.burst_bytes := conv_std_logic_vector(8, 11);
elsif rxstart = '1' then
v.rxstart(nsync) := r.rxstart(nsync-1);
v.rxdstate := discard;
end if;
when read_desc =>
v.rxstatus := (others => '0');
if rmsti.grant = '1' then
v.rxburstcnt := r.rxburstcnt + 1; v.rmsto.addr := r.rmsto.addr + 4;
if r.rxburstcnt(0) = '1' then
v.rmsto.req := '0';
--! AXI_ENABLE: don't use burst operation:
v.rmsto.burst_bytes := conv_std_logic_vector(4,11);
end if;
end if;
if rmsti.ready = '1' then
v.rxcnt := r.rxcnt + 1;
case r.rxcnt(1 downto 0) is
when "00" =>
v.status.rxen := rmsti.data(11);
v.rxden := rmsti.data(11);
v.rxwrap := rmsti.data(12);
v.rxirq := rmsti.data(13);
when "01" =>
v.rxaddr := rmsti.data(31 downto 2);
v.rxdstate := check_desc;
v.rxrenable := '1';
when others =>
null;
end case;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when check_desc =>
v.rxcnt := (others => '0'); v.usesizefield := '0'; v.rmsto.write := '1';
if r.rxden = '1' then
if rxstart = '1' then
v.rxdstate := read_req; v.rxstart(nsync) := r.rxstart(nsync-1);
end if;
else
v.rxdstate := idle;
end if;
v.rmsto.addr := r.rxaddr & "00";
when read_req =>
if r.edclactive = '1' then
v.rxdstate := discard;
elsif (r.rxdoneold and r.rxstatus(3)) = '1' then
v.rxdstate := write_status;
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
elsif ((r.addrdone and not r.addrok) or r.ctrlpkt) = '1' then
v.rxdstate := discard; v.status.invaddr := '1';
elsif ((r.rxdoneold = '1') and r.rxcnt >= r.rxlength) then
if r.gotframe = '1' then
v.rxdstate := write_status;
else
v.rxdstate := discard; v.status.toosmall := '1';
end if;
elsif (r.rxburstav or r.rxdoneold) = '1' then
v.rmsto.req := '1'; v.rxdstate := read_fifo;
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
end if;
v.rxburstcnt := (others => '0'); v.rmsto.data := rxrdata;
when read_fifo =>
v.rxburstav := '0';
if rmsti.grant = '1' then
v.rmsto.addr := r.rmsto.addr + 4;
if (lengthav = '1') then
if ((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 8)) and (rmsti.ready = '1')) or
((conv_integer(r.rxcnt) >=
(conv_integer(r.rxlength) - 4)) and (rmsti.ready = '0')) then
v.rmsto.req := '0';
end if;
end if;
v.rxburstcnt := r.rxburstcnt + 1;
if (conv_integer(r.rxburstcnt) = burstlength-1) then
v.rmsto.req := '0';
end if;
end if;
if rmsti.ready = '1' then
v.rmsto.data := rxrdata;
v.rxcnt := r.rxcnt + 4;
if r.rmsto.req = '0' then
v.rxdstate := read_req;
else
v.rfcnt := r.rfcnt - 1; v.rfrpnt := r.rfrpnt + 1;
end if;
v.check := '1'; v.checkdata := r.rmsto.data;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := discard;
v.rxcnt := r.rxcnt + 4;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when write_status =>
v.rmsto.req := '1'; v.rmsto.addr := ctrli.rxdesc & r.status.rxdsel & "000";
v.rxdstate := write_status2;
if multicast = 1 then
v.rmsto.data := "00000" & r.mcastacc & "0000000" &
r.rxstatus & "000" & r.rxlength;
else
v.rmsto.data := "0000000000000" &
r.rxstatus & "000" & r.rxlength;
end if;
when write_status2 =>
if rmsti.grant = '1' then
v.rmsto.req := '0'; v.rmsto.addr := r.rmsto.addr + 4;
end if;
if rmsti.ready = '1' then
if (r.rxstatus(4) or not r.rxstatus(3)) = '1' then
v.rxdstate := discard;
else
v.rxdstate := idle;
end if;
if (ctrli.rx_irqen and r.rxirq) = '1' then
vpirq := '1';
end if;
if conv_integer(r.rxstatus) = 0 then v.status.rx_int := '1';
else v.status.rx_err := '1'; end if;
if r.rxwrap = '1' then
v.status.rxdsel := (others => '0');
else
v.status.rxdsel := r.status.rxdsel + 1;
end if;
end if;
if rmsti.error = '1' then
v.rmsto.req := '0'; v.rxdstate := idle;
v.status.rxahberr := '1'; v.status.rxen := '0';
end if;
when discard =>
if (r.rxdoneold = '0') then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
if r.rxstatus(3) = '1' then
v.rfcnt := (others => '0'); v.rfwpnt := (others => '0');
v.rfrpnt := (others => '0'); v.writeok := '1';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.rxdstate := idle;
elsif (conv_integer(r.rxcnt) < conv_integer(r.rxbytecount)) then
if conv_integer(r.rfcnt) /= 0 then
v.rfrpnt := r.rfrpnt + 1; v.rfcnt := r.rfcnt - 1;
v.rxcnt := r.rxcnt + 4;
end if;
else
v.rxdstate := idle; v.ctrlpkt := '0';
end if;
end if;
when others =>
null;
end case;
--rx address/type check
if r.check = '1' and r.rxcnt(10 downto 5) = "000000" then
case r.rxcnt(4 downto 2) is
when "001" =>
if ctrli.prom = '1' then
v.addrok := '1';
end if;
v.mcast := r.checkdata(24);
if r.checkdata = broadcast(47 downto 16) then
v.bcast := '1';
end if;
if r.checkdata = ctrli.mac_addr(47 downto 16) then
v.msbgood := '1';
end if;
when "010" =>
if r.checkdata(31 downto 16) = broadcast(15 downto 0) then
if r.bcast = '1' then
v.addrok := '1';
end if;
else
v.bcast := '0';
end if;
if r.checkdata(31 downto 16) = ctrli.mac_addr(15 downto 0) then
if r.msbgood = '1' then
v.addrok := '1';
end if;
end if;
if multicast = 1 then
v.hashlookup := ctrli.hash(conv_integer(rxo.mcasthash));
end if;
when "011" =>
if multicast = 1 then
if (r.hashlookup and ctrli.mcasten and r.mcast) = '1' then
v.addrok := '1';
if r.bcast = '0' then
v.mcastacc := '1';
end if;
end if;
end if;
when "100" =>
if r.checkdata(31 downto 16) = ctrlopcode then v.ctrlpkt := '1'; end if;
v.addrdone := '1';
when others =>
null;
end case;
end if;
--rx packet done
if (rxdone and not rxstart) = '1' then
v.gotframe := rxo.gotframe; v.rxbytecount := rxo.byte_count;
v.rxstatus(3 downto 0) := rxo.status;
if (unsigned(rxo.lentype) > maxsizerx) or (rxo.status /= "0000") then
v.rxlength := rxo.byte_count;
else
v.rxlength := rxo.lentype(10 downto 0);
if (rxo.lentype(10 downto 0) > minpload) and
(rxo.lentype(10 downto 0) /= rxo.byte_count) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
elsif (rxo.lentype(10 downto 0) <= minpload) and
(rxo.byte_count /= minpload) then
if rxo.status(2 downto 0) = "000" then
v.rxstatus(4) := '1'; v.rxlength := rxo.byte_count;
v.usesizefield := '0';
end if;
end if;
end if;
v.rxdoneold := '1';
v.rxdoneack := not r.rxdoneack;
end if;
--rx fifo write
if vrxwrite = '1' then
v.rxwriteack := not r.rxwriteack;
if (not r.rfcnt(fabits)) = '1' then
v.rfwpnt := r.rfwpnt + 1; v.rfcnt := v.rfcnt + 1; v.writeok := '1';
vrxfi.write := '1';
else
v.writeok := '0';
end if;
end if;
--must be placed here because it uses variable
if (ramdebug = 0) or (ctrli.ramdebugen = '0') then
vrxfi.raddress := v.rfrpnt;
end if;
-------------------------------------------------------------------------------
-- MDIO INTERFACE -------------------------------------------------------------
-------------------------------------------------------------------------------
--mdio commands
if enable_mdio = 1 then
mclkvec := r.mdioclkold & r.mdioclk;
mclk := mclkvec(mdiohold-1) and not mclkvec(mdiohold);
nmclk := mclkvec(1) and not mclkvec(0);
v.mdioclkold := mclkvec(mdiohold-1 downto 0);
if r.mdccnt = "00000000" then
v.mdccnt := divisor;
v.mdioclk := not r.mdioclk;
else
v.mdccnt := r.mdccnt - 1;
end if;
mdioindex := conv_integer(r.cnt); v.mdioi := mdio_i;
case r.mdio_state is
when idle =>
if (enable_mdio = 1) and (edcl = 0) and (r.status.reset = '1') then
v.mdio_state := idle; v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.write := '0'; v.status.mdio.busy := '0';
v.status.mdio.cmd.data := (others => '0');
v.status.mdio.cmd.regadr := (others => '0');
v.status.reset := '0';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
if mclk = '1' then
v.cnt := (others => '0');
if r.status.mdio.busy = '1' then
v.status.mdio.linkfail := '0';
if r.status.mdio.cmd.read = '1' then
v.status.mdio.cmd.write := '0';
end if;
v.mdio_state := preamble; v.mdioo := '1';
if OEPOL = 0 then v.mdioen := '0'; else v.mdioen := '1'; end if;
end if;
end if;
when preamble =>
if mclk = '1' then
v.cnt := r.cnt + 1;
if r.cnt = "11111" then
v.mdioo := '0'; v.mdio_state := startst;
end if;
end if;
when startst =>
if mclk = '1' then
v.mdioo := '1'; v.mdio_state := op; v.cnt := (others => '0');
end if;
when op =>
if mclk = '1' then
v.mdio_state := op2;
if r.status.mdio.cmd.read = '1' then v.mdioo := '1';
else v.mdioo := '0'; end if;
end if;
when op2 =>
if mclk = '1' then
v.mdioo := not r.mdioo; v.mdio_state := phyadr;
v.cnt := (others => '0');
end if;
when phyadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := ctrli.mdio_phyadr(4);
when 1 => v.mdioo := ctrli.mdio_phyadr(3);
when 2 => v.mdioo := ctrli.mdio_phyadr(2);
when 3 => v.mdioo := ctrli.mdio_phyadr(1);
when 4 => v.mdioo := ctrli.mdio_phyadr(0);
v.mdio_state := regadr; v.cnt := (others => '0');
when others => null;
end case;
end if;
when regadr =>
if mclk = '1' then
v.cnt := r.cnt + 1;
case mdioindex is
when 0 => v.mdioo := r.status.mdio.cmd.regadr(4);
when 1 => v.mdioo := r.status.mdio.cmd.regadr(3);
when 2 => v.mdioo := r.status.mdio.cmd.regadr(2);
when 3 => v.mdioo := r.status.mdio.cmd.regadr(1);
when 4 => v.mdioo := r.status.mdio.cmd.regadr(0);
v.mdio_state := ta; v.cnt := (others => '0');
when others => null;
end case;
end if;
when ta =>
if mclk = '1' then
v.mdio_state := ta2;
if r.status.mdio.cmd.read = '1' then
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
else v.mdioo := '1'; end if;
end if;
when ta2 =>
if mclk = '1' then
v.cnt := "01111"; v.mdio_state := ta3;
if r.status.mdio.cmd.write = '1' then v.mdioo := '0'; v.mdio_state := data; end if;
end if;
when ta3 =>
if mclk = '1' then
v.mdio_state := data;
end if;
if nmclk = '1' then
if r.mdioi /= '0' then
v.status.mdio.linkfail := '1';
end if;
end if;
when data =>
if mclk = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "00000" then
v.mdio_state := dataend;
end if;
if r.status.mdio.cmd.read = '0' then
v.mdioo := r.status.mdio.cmd.data(mdioindex);
end if;
end if;
if nmclk = '1' then
if r.status.mdio.cmd.read = '1' then
v.status.mdio.cmd.data(mdioindex) := r.mdioi;
end if;
end if;
when dataend =>
if mclk = '1' then
if (rmii = 1) or (edcl /= 0) then
v.init_busy := '0';
if (r.duplexstate = done or ctrli.edcldis = '1' or ctrli.disableduplex = '1') then
v.status.mdio.busy := '0';
end if;
else
v.status.mdio.busy := '0';
end if;
v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.write := '0'; v.mdio_state := idle;
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
end if;
when others =>
null;
end case;
end if;
-------------------------------------------------------------------------------
-- EDCL -----------------------------------------------------------------------
-------------------------------------------------------------------------------
if (edcl /= 0) then
if (ramdebug /= 2) or (ctrli.ramdebugen = '0') then
veri.renable := r.erenable; veri.writem := '0'; veri.writel := '0';
veri.waddressm := r.rpnt & r.rcntm; veri.waddressl := r.rpnt & r.rcntl;
vrxenable := '1';
end if;
swap := '0'; vecnt := conv_integer(r.ecnt); setmz := '0';
if vrxwrite = '1' then
if ctrli.edcldis = '0' then
v.rxwriteack := not r.rxwriteack;
end if;
end if;
--edcl receiver
case r.edclrstate is
when idle =>
v.edclbcast := '0'; v.status.edclrx_idle := '1';
if (ramdebug /= 2) or (ctrli.ramdebugen = '0') then
if (rxstart and not ctrli.edcldis) = '1' then
v.edclrstate := wrda; v.edclactive := '0'; v.status.edclrx_idle := '0';
v.rcntm := conv_std_logic_vector(2, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
end if;
end if;
when wrda =>
if vrxwrite = '1' then
v.edclrstate := wrdsa;
veri.writem := '1'; veri.writel := '1';
swap := '1';
v.rcntm := r.rcntm - 2; v.rcntl := r.rcntl + 1;
if (ctrli.emacaddr(47 downto 16) /= rxo.dataout) and
(X"FFFFFFFF" /= rxo.dataout) then
v.edclrstate := spill;
elsif (X"FFFFFFFF" = rxo.dataout) then
v.edclbcast := '1';
end if;
if conv_integer(r.abufs) = wsz then
v.edclrstate := spill;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrdsa =>
if vrxwrite = '1' then
v.edclrstate := wrsa; swap := '1';
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl - 2;
if (ctrli.emacaddr(15 downto 0) /= rxo.dataout(31 downto 16)) and
(X"FFFF" /= rxo.dataout(31 downto 16)) then
v.edclrstate := spill;
elsif (X"FFFF" = rxo.dataout(31 downto 16)) then
v.edclbcast := r.edclbcast;
end if;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrsa =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.edclrstate := wrtype; swap := '1';
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 3;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when wrtype =>
if vrxwrite = '1' then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if X"0800" = rxo.dataout(31 downto 16) and (r.edclbcast = '0') then
v.edclrstate := ip;
elsif X"0806" = rxo.dataout(31 downto 16) and (r.edclbcast = '1') then
v.edclrstate := arp;
else
v.edclrstate := spill;
end if;
end if;
v.ecnt := (others => '0'); v.ipcrc := (others => '0');
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ip =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 1 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 2;
when 2 =>
v.ipcrc :=
crcadder(not rxo.dataout(31 downto 16), r.ipcrc);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl - 1;
when 3 =>
v.rcntm := r.rcntm - 1; v.rcntl := r.rcntl + 2;
when 4 =>
v.udpsrc := rxo.dataout(15 downto 0);
v.rcntm := r.rcntm + 2; v.rcntl := r.rcntl + 1;
when 5 =>
setmz := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 6 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 7 =>
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
if (rxo.dataout(31 downto 18) = r.seq) then
v.nak := '0';
else
v.nak := '1';
veri.datain(31 downto 18) := r.seq;
end if;
veri.datain(17) := v.nak; v.ewr := rxo.dataout(17);
if (rxo.dataout(17) or v.nak) = '1' then
veri.datain(16 downto 7) := (others => '0');
end if;
v.oplen := rxo.dataout(16 downto 7);
v.applength := "000000" & veri.datain(16 downto 7);
v.ipcrc :=
crcadder(v.applength + 38, r.ipcrc);
v.write(conv_integer(r.rpnt)) := rxo.dataout(17);
when 8 =>
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc :=
crcadder(ipcrctmp, ipcrctmp2);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
v.edclrstate := ipdata;
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when ipdata =>
if (vrxwrite and r.ewr and not r.nak) = '1' and
(r.rcntm /= ebufmax) then
veri.writem := '1'; veri.writel := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
end if;
if rxdone = '1' then
v.edclrstate := ipcrc; v.rcntm := conv_std_logic_vector(6, bpbits);
ipcrctmp := (others => '0');
ipcrctmp(1 downto 0) := r.ipcrc(17 downto 16);
ipcrctmp2 := "00" & r.ipcrc(15 downto 0);
v.ipcrc := crcadder(ipcrctmp, ipcrctmp2);
if conv_integer(v.rxstatus(3 downto 0)) /= 0 then
v.edclrstate := idle;
end if;
end if;
when ipcrc =>
veri.writem := '1'; veri.datain(31 downto 16) := not r.ipcrc(15 downto 0);
v.edclrstate := udp; v.rcntm := conv_std_logic_vector(9, bpbits);
v.rcntl := conv_std_logic_vector(9, bpbits);
when udp =>
veri.writem := '1'; veri.writel := '1';
v.edclrstate := iplength;
veri.datain(31 downto 16) := r.udpsrc;
veri.datain(15 downto 0) := r.applength + 18;
v.rcntm := conv_std_logic_vector(4, bpbits);
when iplength =>
veri.writem := '1';
veri.datain(31 downto 16) := r.applength + 38;
v.edclrstate := oplength;
v.rcntm := conv_std_logic_vector(10, bpbits);
v.rcntl := conv_std_logic_vector(10, bpbits);
when oplength =>
if rxstart = '0' then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
veri.writel := '1'; veri.writem := '1';
end if;
if r.nak = '0' then
v.seq := r.seq + 1;
end if;
v.edclrstate := idle;
veri.datain(31 downto 0) := (others => '0');
veri.datain(15 downto 0) := "00000" & r.nak & r.oplen;
when arp =>
if vrxwrite = '1' then
v.ecnt := r.ecnt + 1;
veri.writem := '1'; veri.writel := '1';
case vecnt is
when 0 =>
v.rcntm := r.rcntm + 4;
when 1 =>
swap := '1'; veri.writel := '0';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 4;
when 2 =>
swap := '1';
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 3 =>
swap := '1';
v.rcntm := r.rcntm - 4; v.rcntl := r.rcntl - 4;
when 4 =>
veri.datain := ctrli.emacaddr(31 downto 16) & ctrli.emacaddr(47 downto 32);
v.rcntm := r.rcntm + 1; v.rcntl := r.rcntl + 1;
when 5 =>
v.rcntl := r.rcntl + 1;
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := ctrli.emacaddr(15 downto 0);
if rxo.dataout(15 downto 0) /= ctrli.edclip(31 downto 16) then
v.edclrstate := spill;
end if;
when 6 =>
swap := '1'; veri.writem := '0';
v.rcntm := conv_std_logic_vector(5, bpbits);
v.rcntl := conv_std_logic_vector(1, bpbits);
if rxo.dataout(31 downto 16) /= ctrli.edclip(15 downto 0) then
v.edclrstate := spill;
else
v.edclactive := '1';
end if;
when 7 =>
veri.writem := '0';
veri.datain(15 downto 0) := ctrli.emacaddr(47 downto 32);
v.rcntl := r.rcntl + 1;
v.rcntm := conv_std_logic_vector(2, bpbits);
when 8 =>
v.edclrstate := arpop;
veri.datain := ctrli.emacaddr(31 downto 0);
v.rcntm := conv_std_logic_vector(5, bpbits);
when others =>
null;
end case;
end if;
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
when arpop =>
veri.writem := '1'; veri.datain(31 downto 16) := X"0002";
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
if conv_integer(v.rxstatus) = 0 and (rxo.gotframe = '1') then
v.abufs := r.abufs + 1; v.rpnt := r.rpnt + 1;
end if;
end if;
when spill =>
if (rxdone and not rxstart) = '1' then
v.edclrstate := idle;
end if;
end case;
--edcl transmitter
case r.txdstate is
when getlen =>
v.tcnt := r.tcnt + 1;
if conv_integer(r.tcnt) = 10 then
v.txlength := '0' & erdata(9 downto 0);
v.tnak := erdata(10);
v.txcnt := v.txlength;
if (r.write(conv_integer(r.tpnt)) or v.tnak) = '1' then
v.txlength := (others => '0');
end if;
end if;
if conv_integer(r.tcnt) = 11 then
v.txdstate := readhdr;
v.tcnt := (others => '0');
end if;
when readhdr =>
v.tcnt := r.tcnt + 1; vtxfi.write := '1';
v.tfwpnt := r.tfwpnt + 1; v.tfcnt := v.tfcnt + 1;
vtxfi.datain := erdata;
if conv_integer(r.tcnt) = 12 then
v.txaddr := erdata(31 downto 2);
end if;
if conv_integer(r.tcnt) = 3 then
if erdata(31 downto 16) = X"0806" then
v.tarp := '1'; v.txlength := conv_std_logic_vector(42, 11);
else
v.tarp := '0'; v.txlength := r.txlength + 52;
end if;
end if;
if r.tarp = '0' then
if conv_integer(r.tcnt) = 12 then
v.txdstate := start;
end if;
else
if conv_integer(r.tcnt) = 10 then
v.txdstate := start;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when start =>
v.tmsto.addr := r.txaddr & "00";
v.tmsto.write := r.write(conv_integer(r.tpnt));
-- AXI_ENABLE: EDCL burst length decoded from payload
v.tmsto.burst_bytes := r.txcnt;
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.addr := r.txaddr & "00";
v.tmsto2.write := r.write(conv_integer(r.tpnt));
-- AXI_ENABLE: EDCL burst length decoded from payload
v.tmsto2.burst_bytes := r.txcnt;
end if;
if (conv_integer(r.txcnt) = 0) or (r.tarp or r.tnak) = '1' then
v.txdstate := etdone;
v.txstart_sync := not r.txstart_sync;
v.tmsto.req := '0';
if (edclsepahbg /= 0) and (edcl /= 0) then
v.tmsto2.req := '0';
end if;
elsif r.write(conv_integer(r.tpnt)) = '0' then
v.txdstate := req; v.tedcl := '1';
else
v.txstart_sync := not r.txstart_sync;
v.tedcl := '1';
v.tcnt := r.tcnt + 1;
if (edclsepahbg = 0) or (edcl = 0) or (r.edclsepahb = '0') then
v.tmsto.req := '1'; v.tmsto.data := erdata;
v.txdstate := wrbus1;
else
v.tmsto2.req := '1'; v.tmsto2.data := erdata;
v.txdstate := wrbus2;
end if;
end if;
if (txrestart or txdone) = '1' then
v.txdstate := etdone;
end if;
when wrbus1 =>
if tmsti.grant = '1' then
v.tmsto.addr := r.tmsto.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti.ready = '1')) then
v.tmsto.req := '0';
end if;
end if;
if (tmsti.ready or tmsti.error) = '1' then
v.tmsto.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti.retry = '1' then
v.tmsto.addr := r.tmsto.addr - 4; v.tmsto.req := '1';
end if;
when wrbus2 =>
if tmsti2.grant = '1' then
v.tmsto2.addr := r.tmsto2.addr + 4;
if ((conv_integer(r.txcnt) <= 4) and (tmsti2.ready = '0')) or
((conv_integer(r.txcnt) <= 8) and (tmsti2.ready = '1')) then
v.tmsto2.req := '0';
end if;
end if;
if (tmsti2.ready or tmsti2.error) = '1' then
v.tmsto2.data := erdata; v.tcnt := r.tcnt + 1;
v.txcnt := r.txcnt - 4;
if r.tmsto2.req = '0' then
v.txdstate := etdone;
end if;
end if;
if tmsti2.retry = '1' then
v.tmsto2.addr := r.tmsto2.addr - 4; v.tmsto2.req := '1';
end if;
when etdone =>
if txdone = '1' then
v.txdstate := idle; v.txdone(nsync) := r.txdone(nsync-1);
v.abufs := v.abufs - 1; v.tpnt := r.tpnt + 1;
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0');
elsif txrestart = '1' then
v.txdstate := idle;
end if;
when others =>
null;
end case;
if swap = '1' then
veri.datain(31 downto 16) := rxo.dataout(15 downto 0);
veri.datain(15 downto 0) := rxo.dataout(31 downto 16);
end if;
if setmz = '1' then
veri.datain(31 downto 16) := (others => '0');
end if;
if (ramdebug /= 2) or (edcl = 0) or (cmdi.dbg_rd_ena = '0') then
veri.raddress := r.tpnt & v.tcnt;
end if;
end if;
--edcl duplex mode read
if (rmii = 1) or (edcl /= 0) then
--edcl, gbit link mode check
case r.duplexstate is
when start =>
if (ctrli.edcldis = '0' and ctrli.disableduplex = '0') then
v.status.mdio.cmd.regadr := r.regaddr; v.init_busy := '1';
v.status.mdio.busy := '1'; v.duplexstate := waitop;
if (r.phywr or r.rstphy) = '1' then
v.status.mdio.cmd.write := '1';
else
v.status.mdio.cmd.read := '1';
end if;
if r.rstphy = '1' then
v.status.mdio.cmd.data := X"9000";
end if;
end if;
when waitop =>
if r.init_busy = '0' then
if r.status.mdio.linkfail = '1' then
v.duplexstate := start;
elsif r.rstphy = '1' then
v.duplexstate := start; v.rstphy := '0';
else
v.duplexstate := nextop;
end if;
end if;
when nextop =>
case r.regaddr is
when "00000" =>
if r.status.mdio.cmd.data(15) = '1' then --rst not finished
v.duplexstate := start;
elsif (r.phywr and not r.rstaneg) = '1' then --forced to 10 Mbit HD
v.duplexstate := selmode;
elsif r.status.mdio.cmd.data(12) = '0' then --no auto neg
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := (others => '0');
else
v.duplexstate := start; v.regaddr := "00001";
end if;
if r.rstaneg = '1' then
v.phywr := '0';
end if;
if ctrli.disableduplex = '1' then
v.duplexstate := done; v.status.mdio.busy := '0';
end if;
when "00001" =>
v.ext := r.status.mdio.cmd.data(8); --extended status register
v.extcap := r.status.mdio.cmd.data(1); --extended register capabilities
v.duplexstate := start;
if r.status.mdio.cmd.data(0) = '0' then
--no extended register capabilites, unable to read aneg config
--forcing 10 Mbit
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := (others => '0');
v.regaddr := (others => '0');
elsif (r.status.mdio.cmd.data(8) and not r.rstaneg) = '1' then
--phy gbit capable, disable gbit
v.regaddr := "01001";
elsif r.status.mdio.cmd.data(5) = '1' then --auto neg completed
v.regaddr := "00100";
end if;
if ctrli.disableduplex = '1' then
v.duplexstate := done; v.status.mdio.busy := '0';
end if;
when "00100" =>
v.duplexstate := start; v.regaddr := "00101";
v.capbil(4 downto 0) := r.status.mdio.cmd.data(9 downto 5);
when "00101" =>
v.duplexstate := selmode;
v.capbil(4 downto 0) :=
r.capbil(4 downto 0) and r.status.mdio.cmd.data(9 downto 5);
when "01001" =>
if r.phywr = '0' then
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data(9 downto 8) := (others => '0');
else
v.regaddr := "00000";
v.duplexstate := start; v.phywr := '1';
v.status.mdio.cmd.data := X"3300"; v.rstaneg := '1';
end if;
when others =>
null;
end case;
when selmode =>
v.duplexstate := done; v.status.mdio.busy := '0';
if r.phywr = '1' then
v.status.full_duplex := '0'; v.status.speed := '0';
else
sel_op_mode(r.capbil, v.status.speed, v.status.full_duplex);
end if;
when done =>
null;
end case;
-- MDIO Disable
if ctrli.edcldis = '1' or ctrli.disableduplex = '1' then
if v.duplexstate /= start then
v.duplexstate := start;
v.status.mdio.cmd.regadr := (others => '0');
v.status.mdio.busy := '0';
v.init_busy := '0';
v.status.mdio.cmd.write := '0';
v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.data := X"0000";
end if;
end if;
end if;
--transmitter retry
if tmsti.retry = '1' then
v.tmsto.req := '1'; v.tmsto.addr := r.tmsto.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto.req := '0'; v.txdstate := ahberror;
end if;
if (edclsepahbg /= 0) and (edcl /= 0) then
--transmitter retry
if tmsti2.retry = '1' then
v.tmsto2.req := '1'; v.tmsto2.addr := r.tmsto2.addr - 4;
v.txburstcnt := r.txburstcnt - 1;
end if;
--transmitter AHB error
if tmsti2.error = '1' and (not ((edcl /= 0) and (r.tedcl = '1'))) then
v.tmsto2.req := '0'; v.txdstate := ahberror;
end if;
end if;
--receiver retry
if rmsti.retry = '1' then
v.rmsto.req := '1'; v.rmsto.addr := r.rmsto.addr - 4;
v.rxburstcnt := r.rxburstcnt - 1;
end if;
------------------------------------------------------------------------------
-- RESET ----------------------------------------------------------------------
-------------------------------------------------------------------------------
if irst = '0' then
v.txdstate := idle; v.rxdstate := idle; v.rfrpnt := (others => '0');
v.rfwpnt := (others => '0');
v.rfcnt := (others => '0');
v.status.txen := '0';
v.status.tx_int := '0';
v.status.rx_int := '0';
v.status.tx_err := '0';
v.status.rx_err := '0';
v.status.txahberr := '0';
v.status.rxahberr := '0';
v.txirqgen := '0'; v.status.rxen := '0';
v.status.txdsel := (others => '0'); v.txstart_sync := '0';
v.txread := (others => '0'); v.txrestart := (others => '0');
v.txdone := (others => '0'); v.txreadack := '0';
v.status.rxdsel := (others => '0'); v.rxdone := (others => '0');
v.rxdoneold := '0'; v.rxdoneack := '0'; v.rxwriteack := '0';
v.rxstart := (others => '0'); v.rxwrite := (others => '0');
v.status.invaddr := '0'; v.status.toosmall := '0';
v.status.full_duplex := '0'; v.writeok := '1';
if (enable_mdio = 0) or (edcl /= 0) then
v.status.reset := '0';
end if;
if enable_mdint = 1 then
v.status.phystat := '0';
end if;
if (edcl /= 0) then
v.tpnt := (others => '0'); v.rpnt := (others => '0');
v.tcnt := (others => '0'); v.edclactive := '0';
v.tarp := '0'; v.abufs := (others => '0');
v.edclrstate := idle;
end if;
if (rmii = 1) then
v.status.speed := '1';
else
v.status.speed := '1';
end if;
end if;
if edcl = 0 then
v.edclrstate := idle; v.edclactive := '0'; v.nak := '0'; v.ewr := '0';
v.write := (others => '0'); v.seq := (others => '0'); v.abufs := (others => '0');
v.tpnt := (others => '0'); v.rpnt := (others => '0'); v.tcnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0'); v.ipcrc := (others => '0');
v.applength := (others => '0'); v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0'); v.tarp := '0';
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
end if;
--some parts of edcl are only affected by hw reset
if rst = '0' then
v.duplexstate := start; v.regaddr := (others => '0');
v.phywr := '0'; v.rstphy := '1'; v.rstaneg := '0';
v.seq := (others => '0');
v.mdioo := '0';
if (enable_mdio = 1) then
v.mdccnt := divisor; v.mdioclk := '0';
end if;
v.status.reset := '0';
if (enable_mdio = 1) then
v.mdio_state := idle; v.status.mdio.cmd.read := '0';
v.status.mdio.cmd.valid := '0';
v.status.mdio.cmd.write := '0'; v.status.mdio.busy := '0';
v.status.mdio.cmd.data := (others => '0');
v.status.mdio.cmd.regadr := (others => '0');
v.status.reset := '0'; v.status.mdio.linkfail := '1';
if OEPOL = 0 then v.mdioen := '1'; else v.mdioen := '0'; end if;
v.cnt := (others => '0');
end if;
if edclsepahbg /= 0 then
v.edclsepahb := edclsepahb;
end if;
v.txcnt := (others => '0'); v.txburstcnt := (others => '0');
v.tedcl := '0'; v.erenable := '0';
v.addrok := '0';
v.rxburstcnt := (others => '0'); v.addrdone := '0';
v.rxcnt := (others => '0'); v.rxdoneold := '0';
v.ctrlpkt := '0'; v.bcast := '0'; v.edclactive := '0';
v.msbgood := '0'; v.rxrenable := '0';
if multicast = 1 then
v.mcast := '0'; v.mcastacc := '0';
end if;
v.tnak := '0'; v.tedcl := '0'; v.edclbcast := '0';
v.gotframe := '0';
v.rxbytecount := (others => '0'); v.rxlength := (others => '0');
v.txburstav := '0'; v.txdataav := '0';
v.txstatus := (others => '0'); v.txstart := '0';
v.tfcnt := (others => '0'); v.tfrpnt := (others => '0');
v.tfwpnt := (others => '0'); v.txaddr := (others => '0');
v.txdata := (others => '0');
v.txvalid := '0';
v.txlength := (others => '0');
v.cnt := (others => '0');
v.rxaddr := (others => '0');
v.rxstatus := (others => '0');
v.rxwrap := '0'; v.rxden := '0';
v.rmsto.req := '0';
v.rmsto.write := '0';
v.rmsto.addr := (others => '0');
v.rmsto.data := (others => '0');
v.tmsto.req := '0';
v.tmsto.write := '0';
v.tmsto.addr := (others => '0');
v.tmsto.data := (others => '0');
v.tmsto2.req := '0';
v.tmsto2.write := '0';
v.tmsto2.addr := (others => '0');
v.tmsto2.data := (others => '0');
v.nak := '0'; v.ewr := '0';
v.write := (others => '0');
v.applength := (others => '0');
v.oplen := (others => '0');
v.udpsrc := (others => '0'); v.ecnt := (others => '0');
v.rcntm := (others => '0'); v.rcntl := (others => '0');
v.txwrap := '0';
v.txden := '0';
v.txirq := '0';
v.rxirq := '0';
end if;
-------------------------------------------------------------------------------
-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
-------------------------------------------------------------------------------
rin <= v;
rdbgdatao <= vrdbgdata;
irq <= vpirq;
--rx ahb fifo
rxrenable <= vrxfi.renable;
rxraddress(10 downto fabits) <= (others => '0');
rxraddress(fabits-1 downto 0) <= vrxfi.raddress;
rxwrite <= vrxfi.write;
rxwdata <= vrxfi.datain;
rxwaddress(10 downto fabits) <= (others => '0');
rxwaddress(fabits-1 downto 0) <= vrxfi.waddress;
--tx ahb fifo
txrenable <= vtxfi.renable;
txraddress(10 downto txfabits) <= (others => '0');
txraddress(txfabits-1 downto 0) <= vtxfi.raddress;
txwrite <= vtxfi.write;
txwdata <= vtxfi.datain;
txwaddress(10 downto txfabits) <= (others => '0');
txwaddress(txfabits-1 downto 0) <= vtxfi.waddress;
--edcl buf
erenable <= veri.renable;
eraddress(15 downto eabits) <= (others => '0');
eraddress(eabits-1 downto 0) <= veri.raddress;
ewritem <= veri.writem;
ewritel <= veri.writel;
ewaddressm(15 downto eabits) <= (others => '0');
ewaddressm(eabits-1 downto 0) <= veri.waddressm(eabits-1 downto 0);
ewaddressl(15 downto eabits) <= (others => '0');
ewaddressl(eabits-1 downto 0) <= veri.waddressl(eabits-1 downto 0);
ewdata <= veri.datain;
rxi.enable <= vrxenable;
end process;
statuso <= r.status;
rxi.writeack <= r.rxwriteack;
rxi.doneack <= r.rxdoneack;
rxi.speed <= r.status.speed;
rxi.writeok <= r.writeok;
rxi.rxd <= rxd;
rxi.rx_dv <= rx_dv;
rxi.rx_crs <= rx_crs;
rxi.rx_er <= rx_er;
rxi.rx_en <= rx_en;
txi.rx_col <= rx_col;
txi.rx_crs <= rx_crs;
txi.full_duplex <= r.status.full_duplex;
txi.start <= r.txstart_sync;
txi.readack <= r.txreadack;
txi.speed <= r.status.speed;
txi.data <= r.txdata;
txi.valid <= r.txvalid;
txi.len <= r.txlength;
txi.datavalid <= tx_dv;
mdc <= r.mdioclk;
mdio_o <= r.mdioo;
mdio_oe <= testoen when (scanen/=0 and testen/='0') else r.mdioen;
tmsto <= r.tmsto;
rmsto <= r.rmsto;
tmsto2 <= r.tmsto2;
txd <= txo.txd;
tx_en <= txo.tx_en;
tx_er <= txo.tx_er;
speed <= r.status.speed;
reset <= irst;
regs : process(clk) is
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-------------------------------------------------------------------------------
-- TRANSMITTER-----------------------------------------------------------------
-------------------------------------------------------------------------------
tx_rmii0 : if rmii = 0 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => tx_clk,
txi => txi,
txo => txo);
end generate;
tx_rmii1 : if rmii = 1 generate
tx0: greth_tx
generic map(
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
nsync => nsync,
rmii => rmii,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rmii_clk,
txi => txi,
txo => txo);
end generate;
-------------------------------------------------------------------------------
-- RECEIVER -------------------------------------------------------------------
-------------------------------------------------------------------------------
rx_rmii0 : if rmii = 0 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode
)
port map(
rst => arst,
clk => rx_clk,
rxi => rxi,
rxo => rxo);
end generate;
rx_rmii1 : if rmii = 1 generate
rx0 : greth_rx
generic map(
nsync => nsync,
rmii => rmii,
multicast => multicast,
maxsize => maxsize,
gmiimode => gmiimode)
port map(
rst => arst,
clk => rmii_clk,
rxi => rxi,
rxo => rxo);
end generate;
--! Tx FIFO
tx_fifo0 : syncram_2p_tech generic map (
tech => memtech,
abits => txfabits,
dbits => 32,
sepclk => 0
) port map (
clk,
txrenable,
txraddress(txfabits-1 downto 0),
txrdata,
clk,
txwrite,
txwaddress(txfabits-1 downto 0),
txwdata
);
--! Rx FIFO
rx_fifo0 : syncram_2p_tech generic map (
tech => memtech,
abits => fabits,
dbits => 32,
sepclk => 0
) port map (
clk,
rxrenable,
rxraddress(fabits-1 downto 0),
rxrdata,
clk,
rxwrite,
rxwaddress(fabits-1 downto 0),
rxwdata
);
--! EDCL buffer ram
edclramnft : if (edcl /= 0) generate
r0 : syncram_2p_tech generic map (
memtech,
eabits,
16
) port map (
clk,
erenable,
eraddress(eabits-1 downto 0),
erdata(31 downto 16),
clk,
ewritem,
ewaddressm(eabits-1 downto 0),
ewdata(31 downto 16)
);
r1 : syncram_2p_tech generic map (
memtech,
eabits,
16
) port map(
clk,
erenable,
eraddress(eabits-1 downto 0),
erdata(15 downto 0),
clk,
ewritel,
ewaddressl(eabits-1 downto 0),
ewdata(15 downto 0)
);
end generate;
end architecture;
| apache-2.0 | 4d7fb1991e87abacb671ef72066a8232 | 0.492597 | 3.550275 | false | false | false | false |
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`protect end_protected
| bsd-2-clause | 98f8c15676ed6c0e305dbd665768bfc4 | 0.941906 | 1.837624 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_status_flags_sshft.vhd | 19 | 19,232 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12496)
`protect data_block
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| bsd-2-clause | 3d99a79275fe3b41f9d1c95f51109242 | 0.93984 | 1.856191 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/axi4_uart.vhd | 1 | 14,931 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_uart is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#;
xirq : integer := 0;
fifosz : integer := 16
);
port (
clk : in std_logic;
nrst : in std_logic;
cfg : out axi4_slave_config_type;
i_uart : in uart_in_type;
o_uart : out uart_out_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq : out std_logic
);
end;
architecture arch_axi4_uart of axi4_uart is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(xirq, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_UART
);
constant zero32 : std_logic_vector(31 downto 0) := (others => '0');
type fifo_mem is array (0 to fifosz-1) of std_logic_vector(7 downto 0);
type state_type is (idle, startbit, data, parity, stopbit);
type fifo_in_type is record
raddr : integer range 0 to fifosz-1;
waddr : integer range 0 to fifosz-1;
we : std_logic;
wdata : std_logic_vector(7 downto 0);
end record;
constant fifo_in_none : fifo_in_type := (0, 0, '0', X"00");
signal rfifoi : fifo_in_type;
signal rx_fifo_rdata : std_logic_vector(7 downto 0);
signal rx_fifo : fifo_mem;
signal tfifoi : fifo_in_type;
signal tx_fifo_rdata : std_logic_vector(7 downto 0);
signal tx_fifo : fifo_mem;
type registers is record
tx_state : state_type;
tx_wr_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
tx_rd_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
tx_byte_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
tx_shift : std_logic_vector(10 downto 0); --! stopbit=1,parity=xor,data[7:0],startbit=0
tx_data_cnt : integer range 0 to 11;
tx_scaler_cnt : std_logic_vector(31 downto 0);
tx_level : std_logic;
tx_irq_thresh : std_logic_vector(log2(fifosz)-1 downto 0);
tx_more_thresh : std_logic_vector(1 downto 0);
rx_state : state_type;
rx_wr_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
rx_rd_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
rx_byte_cnt : std_logic_vector(log2(fifosz)-1 downto 0);
rx_shift : std_logic_vector(7 downto 0);
rx_data_cnt : integer range 0 to 7;
rx_scaler_cnt : std_logic_vector(31 downto 0);
rx_level : std_logic;
rx_irq_thresh : std_logic_vector(log2(fifosz)-1 downto 0);
rx_more_thresh : std_logic_vector(1 downto 0);
rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
scaler : std_logic_vector(31 downto 0);
err_parity : std_logic;
err_stopbit : std_logic;
parity_bit : std_logic;
tx_irq_ena : std_logic;
rx_irq_ena : std_logic;
fwcpuid : std_logic_vector(31 downto 0);
end record;
constant R_RESET : registers := (
idle, -- tx_state
(others => '0'), (others => '0'), -- tx_wr_cnt, tx_rd_cnt
(others => '0'), -- tx_byte_cnt
(others => '0'), -- tx_shift
0, -- tx_data_cnt
(others => '0'), -- tx_scaler_cnt
'0', -- tx_level
(others => '0'), -- tx_irq_thresh
(others => '0'), -- tx_more_thresh
idle, -- rx_state
(others => '0'), (others => '0'), -- rx_wr_cnt , rx_rd_cnt
(others => '0'), -- rx_byte_cnt
(others => '0'), -- rx_shift
0, -- rx_data_cnt
(others => '0'), -- rx_scaler_cnt
'1', -- rx_level
(others => '0'), -- rx_irq_thresh
(others => '0'), -- rx_more_thresh
(others => '0'), -- rdata
(others => '0'), -- scaler
'0', -- err_parity
'0', -- err_stopbit
'0', -- parity_bit
'0', -- tx_irq_ena
'0', -- rx_irq_ena
(others => '0')); -- fwcpuid
signal r, rin : registers;
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => '1',
i_rdata => r.rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_uart, r, tx_fifo_rdata, rx_fifo_rdata,
w_bus_re, wb_bus_raddr, wb_bus_waddr, w_bus_we,
wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable tmp : std_logic_vector(31 downto 0);
variable v_rfifoi : fifo_in_type;
variable v_tfifoi : fifo_in_type;
variable posedge_flag : std_logic;
variable negedge_flag : std_logic;
variable tx_fifo_empty : std_logic;
variable tx_fifo_full : std_logic;
variable rx_fifo_empty : std_logic;
variable rx_fifo_full : std_logic;
variable t_tx, t_rx : std_logic_vector(7 downto 0);
variable par : std_logic;
variable irq_ena : std_logic;
begin
v := r;
v_rfifoi := fifo_in_none;
v_rfifoi.raddr := conv_integer(r.rx_rd_cnt);
v_rfifoi.waddr := conv_integer(r.rx_wr_cnt);
v_rfifoi.wdata := r.rx_shift;
v_tfifoi := fifo_in_none;
v_tfifoi.raddr := conv_integer(r.tx_rd_cnt);
v_tfifoi.waddr := conv_integer(r.tx_wr_cnt);
-- Check FIFOs counters with thresholds:
v.tx_more_thresh := r.tx_more_thresh(0) & '0';
if r.tx_byte_cnt > r.tx_irq_thresh then
v.tx_more_thresh(0) := '1';
end if;
v.rx_more_thresh := r.rx_more_thresh(0) & '0';
if r.rx_byte_cnt > r.rx_irq_thresh then
v.rx_more_thresh(0) := '1';
end if;
irq_ena := '0';
if (r.tx_more_thresh(1) and not r.tx_more_thresh(0)) = '1' then
irq_ena := r.tx_irq_ena;
end if;
if (not r.rx_more_thresh(1) and r.rx_more_thresh(0)) = '1' then
irq_ena := irq_ena or r.rx_irq_ena;
end if;
-- system bus clock scaler to baudrate:
posedge_flag := '0';
negedge_flag := '0';
if r.scaler /= zero32 then
if r.tx_scaler_cnt = (r.scaler-1) then
v.tx_scaler_cnt := zero32;
v.tx_level := not r.tx_level;
posedge_flag := not r.tx_level;
else
v.tx_scaler_cnt := r.tx_scaler_cnt + 1;
end if;
if r.rx_state = idle and i_uart.rd = '1' then
v.rx_scaler_cnt := zero32;
v.rx_level := '1';
elsif r.rx_scaler_cnt = (r.scaler-1) then
v.rx_scaler_cnt := zero32;
v.rx_level := not r.rx_level;
negedge_flag := r.rx_level;
else
v.rx_scaler_cnt := r.rx_scaler_cnt + 1;
end if;
end if;
-- Transmitter's FIFO:
tx_fifo_full := '0';
if (r.tx_wr_cnt + 1) = r.tx_rd_cnt then
tx_fifo_full := '1';
end if;
tx_fifo_empty := '0';
if r.tx_rd_cnt = r.tx_wr_cnt then
tx_fifo_empty := '1';
v.tx_byte_cnt := (others => '0');
end if;
-- Receiver's FIFO:
rx_fifo_full := '0';
if (r.rx_wr_cnt + 1) = r.rx_rd_cnt then
rx_fifo_full := '1';
end if;
rx_fifo_empty := '0';
if r.rx_rd_cnt = r.rx_wr_cnt then
rx_fifo_empty := '1';
v.rx_byte_cnt := (others => '0');
end if;
-- Transmitter's state machine:
if i_uart.cts = '1' and posedge_flag = '1' then
case r.tx_state is
when idle =>
if tx_fifo_empty = '0' then
-- stopbit=1,parity=xor,data[7:0],startbit=0
t_tx := tx_fifo_rdata; --r.tx_fifo(conv_integer(r.tx_rd_cnt));
if r.parity_bit = '1' then
par := t_tx(7) xor t_tx(6) xor t_tx(5) xor t_tx(4)
xor t_tx(3) xor t_tx(2) xor t_tx(1) xor t_tx(0);
v.tx_shift := '1' & par & t_tx & '0';
else
v.tx_shift := "11" & t_tx & '0';
end if;
v.tx_state := startbit;
v.tx_rd_cnt := r.tx_rd_cnt + 1;
v.tx_byte_cnt := r.tx_byte_cnt - 1;
v.tx_data_cnt := 0;
end if;
when startbit =>
v.tx_state := data;
when data =>
if r.tx_data_cnt = 8 then
if r.parity_bit = '1' then
v.tx_state := parity;
else
v.tx_state := stopbit;
end if;
end if;
when parity =>
v.tx_state := stopbit;
when stopbit =>
v.tx_state := idle;
when others =>
end case;
if r.tx_state /= idle then
v.tx_data_cnt := r.tx_data_cnt + 1;
v.tx_shift := '1' & r.tx_shift(10 downto 1);
end if;
end if;
--! Receiver's state machine:
if negedge_flag = '1' then
case r.rx_state is
when idle =>
if i_uart.rd = '0' then
v.rx_state := data;
v.rx_shift := (others => '0');
v.rx_data_cnt := 0;
end if;
when data =>
v.rx_shift := i_uart.rd & r.rx_shift(7 downto 1);
if r.rx_data_cnt = 7 then
if r.parity_bit = '1' then
v.rx_state := parity;
else
v.rx_state := stopbit;
end if;
else
v.rx_data_cnt := r.rx_data_cnt + 1;
end if;
when parity =>
t_rx := r.rx_shift;
par := t_rx(7) xor t_rx(6) xor t_rx(5) xor t_rx(4)
xor t_rx(3) xor t_rx(2) xor t_rx(1) xor t_rx(0);
if par = i_uart.rd then
v.err_parity := '0';
else
v.err_parity := '1';
end if;
v.rx_state := stopbit;
when stopbit =>
if i_uart.rd = '0' then
v.err_stopbit := '1';
else
v.err_stopbit := '0';
end if;
if rx_fifo_full = '0' then
v_rfifoi.we := '1';
--v.rx_fifo(conv_integer(r.rx_wr_cnt)) := r.rx_shift;
v.rx_wr_cnt := r.rx_wr_cnt + 1;
v.rx_byte_cnt := r.rx_byte_cnt + 1;
end if;
v.rx_state := idle;
when others =>
end case;
end if;
o_uart.rts <= '1';
if r.tx_state = idle then
o_uart.td <= '1';
else
o_uart.td <= r.tx_shift(0);
end if;
for n in 0 to CFG_WORDS_ON_BUS-1 loop
tmp := (others => '0');
case conv_integer(wb_bus_raddr(n)(11 downto 2)) is
when 0 =>
tmp(1 downto 0) := tx_fifo_empty & tx_fifo_full;
tmp(5 downto 4) := rx_fifo_empty & rx_fifo_full;
tmp(9 downto 8) := r.err_stopbit & r.err_parity;
tmp(13) := r.rx_irq_ena;
tmp(14) := r.tx_irq_ena;
tmp(15) := r.parity_bit;
when 1 =>
tmp := r.scaler;
when 2 =>
tmp := r.fwcpuid;
when 4 =>
if rx_fifo_empty = '0' and w_bus_re = '1' then
tmp(7 downto 0) := rx_fifo_rdata;
v.rx_rd_cnt := r.rx_rd_cnt + 1;
v.rx_byte_cnt := r.rx_byte_cnt - 1;
end if;
when others =>
end case;
v.rdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if w_bus_we = '1' then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wb_bus_wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
tmp := wb_bus_wdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n);
case conv_integer(wb_bus_waddr(n)(11 downto 2)) is
when 0 =>
v.parity_bit := tmp(15);
v.tx_irq_ena := tmp(14);
v.rx_irq_ena := tmp(13);
when 1 =>
v.scaler := tmp;
v.rx_scaler_cnt := zero32;
v.tx_scaler_cnt := zero32;
when 2 =>
if r.fwcpuid = X"00000000" or tmp = X"00000000" then
v.fwcpuid := tmp;
end if;
when 4 =>
if tx_fifo_full = '0' then
v_tfifoi.we := '1';
v_tfifoi.wdata := tmp(7 downto 0);
v.tx_wr_cnt := r.tx_wr_cnt + 1;
v.tx_byte_cnt := r.tx_byte_cnt + 1;
end if;
when others =>
end case;
end if;
end loop;
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
rfifoi <= v_rfifoi;
tfifoi <= v_tfifoi;
o_irq <= irq_ena;
end process;
cfg <= xconfig;
-- fifo pseudo memory:
tfifo0 : process(clk, tfifoi, tx_fifo)
begin
if rising_edge(clk) then
if tfifoi.we = '1' then
tx_fifo(tfifoi.waddr) <= tfifoi.wdata;
end if;
end if;
tx_fifo_rdata <= tx_fifo(tfifoi.raddr);
end process;
rfifo0 : process(clk, rfifoi, rx_fifo)
begin
if rising_edge(clk) then
if rfifoi.we = '1' then
rx_fifo(rfifoi.waddr) <= rfifoi.wdata;
end if;
end if;
rx_fifo_rdata <= rx_fifo(rfifoi.raddr);
end process;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end; | apache-2.0 | 69018654a62b957f716994a4f2b40388 | 0.510883 | 3.176809 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/stacktrbuf.vhd | 1 | 1,347 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2017 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Stack trace buffer on hardware level.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity StackTraceBuffer is
generic (
abits : integer := 5;
dbits : integer := 64
);
port (
i_clk : in std_logic;
i_raddr : in std_logic_vector(abits-1 downto 0);
o_rdata : out std_logic_vector(dbits-1 downto 0);
i_we : in std_logic;
i_waddr : in std_logic_vector(abits-1 downto 0);
i_wdata : in std_logic_vector(dbits-1 downto 0)
);
end;
architecture arch_StackTraceBuffer of StackTraceBuffer is
type ram_type is array ((2**abits)-1 downto 0) of std_logic_vector (dbits-1 downto 0);
signal stackbuf : ram_type;
signal raddr : std_logic_vector(abits-1 downto 0);
begin
-- registers:
regs : process(i_clk) begin
if rising_edge(i_clk) then
if i_we = '1' then
stackbuf(conv_integer(i_waddr)) <= i_wdata;
end if;
raddr <= i_raddr;
end if;
end process;
o_rdata <= stackbuf(conv_integer(raddr));
end;
| apache-2.0 | 726dfaf1bde3f26fb982b25a69c2dc7a | 0.570156 | 3.680328 | false | false | false | false |
quicky2000/top_chenillard | top_chenillard.vhd | 1 | 2,233 | --
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_chenillard is
port(
clk : in std_logic;
w1a : inout std_logic_vector(15 downto 0);
w1b : inout std_logic_vector(15 downto 0);
w2c : inout std_logic_vector(15 downto 0);
rx : in std_logic;
tx : inout std_logic
);
end top_chenillard;
architecture Behavioral of top_chenillard is
component chenillard
port(
clk : in std_logic;
reset : in std_logic;
button : in std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic
);
end component;
signal reset : std_logic;
signal pre_Q : std_logic_vector(23 downto 0);
signal clock_slow : std_logic;
begin
process(clk,reset)
begin
if reset = '1' then
pre_Q <= (others => '0');
elsif rising_edge(clk) then
pre_Q <= pre_Q + 1;
end if;
end process;
clock_slow <= pre_q(23);
chenillard_inst : chenillard
port map(
clk => clock_slow,
reset =>reset,
button => w1a(7),
led1 => w1a(6),
led2 => w1a(4),
led3 => w1a(2),
led4 => w1a(0)
);
reset <= '0';
end Behavioral;
| gpl-3.0 | f4ab2c7fd1913f13b8ad47dad70270f4 | 0.682938 | 3.153955 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/arith/shift.vhd | 1 | 20,960 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2016 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Left/Right shifter arithmetic/logic 32/64 bits.
--!
--! @details Vivado synthesizer (2016.2) doesn't support shift
--! from dynamic value, so implement this mux.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity Shifter is
port (
i_a1 : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Operand 1
i_a2 : in std_logic_vector(5 downto 0); -- Shift bits number
o_sll : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift left 64-bits operand
o_sllw : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift left 32-bits operand
o_srl : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift 64 bits
o_sra : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Arith. shift 64 bits
o_srlw : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Logical shift 32 bits
o_sraw : out std_logic_vector(RISCV_ARCH-1 downto 0) -- Arith. shift 32 bits
);
end;
architecture arch_Shifter of Shifter is
begin
comb : process(i_a1, i_a2)
variable wb_sll : std_logic_vector(63 downto 0);
variable wb_srl : std_logic_vector(63 downto 0);
variable wb_sra : std_logic_vector(63 downto 0);
variable wb_sllw : std_logic_vector(63 downto 0);
variable wb_srlw : std_logic_vector(63 downto 0);
variable wb_sraw : std_logic_vector(63 downto 0);
variable v64 : std_logic_vector(63 downto 0);
variable v32 : std_logic_vector(31 downto 0);
variable msk64 : std_logic_vector(63 downto 0);
variable msk32 : std_logic_vector(63 downto 0);
variable shift64 : integer range 0 to 63;
variable shift32 : integer range 0 to 31;
begin
v64 := i_a1;
v32 := i_a1(31 downto 0);
msk64 := (others => i_a1(63));
msk32 := (others => i_a1(31));
shift64 := conv_integer(i_a2);
shift32 := conv_integer(i_a2(4 downto 0));
case shift64 is
when 0 =>
wb_sll := v64;
wb_srl := v64;
wb_sra := v64;
when 1 =>
wb_sll := v64(62 downto 0) & "0";
wb_srl := "0" & v64(63 downto 1);
wb_sra := (msk64(63 downto 63) & v64(63 downto 1));
when 2 =>
wb_sll := v64(61 downto 0) & "00";
wb_srl := "00" & v64(63 downto 2);
wb_sra := (msk64(63 downto 62) & v64(63 downto 2));
when 3 =>
wb_sll := v64(60 downto 0) & "000";
wb_srl := "000" & v64(63 downto 3);
wb_sra := (msk64(63 downto 61) & v64(63 downto 3));
when 4 =>
wb_sll := v64(59 downto 0) & X"0";
wb_srl := X"0" & v64(63 downto 4);
wb_sra := (msk64(63 downto 60) & v64(63 downto 4));
when 5 =>
wb_sll := v64(58 downto 0) & X"0" & "0";
wb_srl := X"0" & "0" & v64(63 downto 5);
wb_sra := (msk64(63 downto 59) & v64(63 downto 5));
when 6 =>
wb_sll := v64(57 downto 0) & X"0" & "00";
wb_srl := X"0" & "00" & v64(63 downto 6);
wb_sra := (msk64(63 downto 58) & v64(63 downto 6));
when 7 =>
wb_sll := v64(56 downto 0) & X"0" & "000";
wb_srl := X"0" & "000" & v64(63 downto 7);
wb_sra := (msk64(63 downto 57) & v64(63 downto 7));
when 8 =>
wb_sll := v64(55 downto 0) & X"00";
wb_srl := X"00" & v64(63 downto 8);
wb_sra := (msk64(63 downto 56) & v64(63 downto 8));
when 9 =>
wb_sll := v64(54 downto 0) & X"00" & "0";
wb_srl := X"00" & "0" & v64(63 downto 9);
wb_sra := (msk64(63 downto 55) & v64(63 downto 9));
when 10 =>
wb_sll := v64(53 downto 0) & X"00" & "00";
wb_srl := X"00" & "00" & v64(63 downto 10);
wb_sra := (msk64(63 downto 54) & v64(63 downto 10));
when 11 =>
wb_sll := v64(52 downto 0) & X"00" & "000";
wb_srl := X"00" & "000" & v64(63 downto 11);
wb_sra := (msk64(63 downto 53) & v64(63 downto 11));
when 12 =>
wb_sll := v64(51 downto 0) & X"000";
wb_srl := X"000" & v64(63 downto 12);
wb_sra := (msk64(63 downto 52) & v64(63 downto 12));
when 13 =>
wb_sll := v64(50 downto 0) & X"000" & "0";
wb_srl := X"000" & "0" & v64(63 downto 13);
wb_sra := (msk64(63 downto 51) & v64(63 downto 13));
when 14 =>
wb_sll := v64(49 downto 0) & X"000" & "00";
wb_srl := X"000" & "00" & v64(63 downto 14);
wb_sra := (msk64(63 downto 50) & v64(63 downto 14));
when 15 =>
wb_sll := v64(48 downto 0) & X"000" & "000";
wb_srl := X"000" & "000" & v64(63 downto 15);
wb_sra := (msk64(63 downto 49) & v64(63 downto 15));
when 16 =>
wb_sll := v64(47 downto 0) & X"0000";
wb_srl := X"0000" & v64(63 downto 16);
wb_sra := (msk64(63 downto 48) & v64(63 downto 16));
when 17 =>
wb_sll := v64(46 downto 0) & X"0000" & "0";
wb_srl := X"0000" & "0" & v64(63 downto 17);
wb_sra := (msk64(63 downto 47) & v64(63 downto 17));
when 18 =>
wb_sll := v64(45 downto 0) & X"0000" & "00";
wb_srl := X"0000" & "00" & v64(63 downto 18);
wb_sra := (msk64(63 downto 46) & v64(63 downto 18));
when 19 =>
wb_sll := v64(44 downto 0) & X"0000" & "000";
wb_srl := X"0000" & "000" & v64(63 downto 19);
wb_sra := (msk64(63 downto 45) & v64(63 downto 19));
when 20 =>
wb_sll := v64(43 downto 0) & X"00000";
wb_srl := X"00000" & v64(63 downto 20);
wb_sra := (msk64(63 downto 44) & v64(63 downto 20));
when 21 =>
wb_sll := v64(42 downto 0) & X"00000" & "0";
wb_srl := X"00000" & "0" & v64(63 downto 21);
wb_sra := (msk64(63 downto 43) & v64(63 downto 21));
when 22 =>
wb_sll := v64(41 downto 0) & X"00000" & "00";
wb_srl := X"00000" & "00" & v64(63 downto 22);
wb_sra := (msk64(63 downto 42) & v64(63 downto 22));
when 23 =>
wb_sll := v64(40 downto 0) & X"00000" & "000";
wb_srl := X"00000" & "000" & v64(63 downto 23);
wb_sra := (msk64(63 downto 41) & v64(63 downto 23));
when 24 =>
wb_sll := v64(39 downto 0) & X"000000";
wb_srl := X"000000" & v64(63 downto 24);
wb_sra := (msk64(63 downto 40) & v64(63 downto 24));
when 25 =>
wb_sll := v64(38 downto 0) & X"000000" & "0";
wb_srl := X"000000" & "0" & v64(63 downto 25);
wb_sra := (msk64(63 downto 39) & v64(63 downto 25));
when 26 =>
wb_sll := v64(37 downto 0) & X"000000" & "00";
wb_srl := X"000000" & "00" & v64(63 downto 26);
wb_sra := (msk64(63 downto 38) & v64(63 downto 26));
when 27 =>
wb_sll := v64(36 downto 0) & X"000000" & "000";
wb_srl := X"000000" & "000" & v64(63 downto 27);
wb_sra := (msk64(63 downto 37) & v64(63 downto 27));
when 28 =>
wb_sll := v64(35 downto 0) & X"0000000";
wb_srl := X"0000000" & v64(63 downto 28);
wb_sra := (msk64(63 downto 36) & v64(63 downto 28));
when 29 =>
wb_sll := v64(34 downto 0) & X"0000000" & "0";
wb_srl := X"0000000" & "0" & v64(63 downto 29);
wb_sra := (msk64(63 downto 35) & v64(63 downto 29));
when 30 =>
wb_sll := v64(33 downto 0) & X"0000000" & "00";
wb_srl := X"0000000" & "00" & v64(63 downto 30);
wb_sra := (msk64(63 downto 34) & v64(63 downto 30));
when 31 =>
wb_sll := v64(32 downto 0) & X"0000000" & "000";
wb_srl := X"0000000" & "000" & v64(63 downto 31);
wb_sra := (msk64(63 downto 33) & v64(63 downto 31));
when 32 =>
wb_sll := v64(31 downto 0) & X"00000000";
wb_srl := X"00000000" & v64(63 downto 32);
wb_sra := (msk64(63 downto 32) & v64(63 downto 32));
when 33 =>
wb_sll := v64(30 downto 0) & X"00000000" & "0";
wb_srl := X"00000000" & "0" & v64(63 downto 33);
wb_sra := (msk64(63 downto 31) & v64(63 downto 33));
when 34 =>
wb_sll := v64(29 downto 0) & X"00000000" & "00";
wb_srl := X"00000000" & "00" & v64(63 downto 34);
wb_sra := (msk64(63 downto 30) & v64(63 downto 34));
when 35 =>
wb_sll := v64(28 downto 0) & X"00000000" & "000";
wb_srl := X"00000000" & "000" & v64(63 downto 35);
wb_sra := (msk64(63 downto 29) & v64(63 downto 35));
when 36 =>
wb_sll := v64(27 downto 0) & X"000000000";
wb_srl := X"000000000" & v64(63 downto 36);
wb_sra := (msk64(63 downto 28) & v64(63 downto 36));
when 37 =>
wb_sll := v64(26 downto 0) & X"000000000" & "0";
wb_srl := X"000000000" & "0" & v64(63 downto 37);
wb_sra := (msk64(63 downto 27) & v64(63 downto 37));
when 38 =>
wb_sll := v64(25 downto 0) & X"000000000" & "00";
wb_srl := X"000000000" & "00" & v64(63 downto 38);
wb_sra := (msk64(63 downto 26) & v64(63 downto 38));
when 39 =>
wb_sll := v64(24 downto 0) & X"000000000" & "000";
wb_srl := X"000000000" & "000" & v64(63 downto 39);
wb_sra := (msk64(63 downto 25) & v64(63 downto 39));
when 40 =>
wb_sll := v64(23 downto 0) & X"0000000000";
wb_srl := X"0000000000" & v64(63 downto 40);
wb_sra := (msk64(63 downto 24) & v64(63 downto 40));
when 41 =>
wb_sll := v64(22 downto 0) & X"0000000000" & "0";
wb_srl := X"0000000000" & "0" & v64(63 downto 41);
wb_sra := (msk64(63 downto 23) & v64(63 downto 41));
when 42 =>
wb_sll := v64(21 downto 0) & X"0000000000" & "00";
wb_srl := X"0000000000" & "00" & v64(63 downto 42);
wb_sra := (msk64(63 downto 22) & v64(63 downto 42));
when 43 =>
wb_sll := v64(20 downto 0) & X"0000000000" & "000";
wb_srl := X"0000000000" & "000" & v64(63 downto 43);
wb_sra := (msk64(63 downto 21) & v64(63 downto 43));
when 44 =>
wb_sll := v64(19 downto 0) & X"00000000000";
wb_srl := X"00000000000" & v64(63 downto 44);
wb_sra := (msk64(63 downto 20) & v64(63 downto 44));
when 45 =>
wb_sll := v64(18 downto 0) & X"00000000000" & "0";
wb_srl := X"00000000000" & "0" & v64(63 downto 45);
wb_sra := (msk64(63 downto 19) & v64(63 downto 45));
when 46 =>
wb_sll := v64(17 downto 0) & X"00000000000" & "00";
wb_srl := X"00000000000" & "00" & v64(63 downto 46);
wb_sra := (msk64(63 downto 18) & v64(63 downto 46));
when 47 =>
wb_sll := v64(16 downto 0) & X"00000000000" & "000";
wb_srl := X"00000000000" & "000" & v64(63 downto 47);
wb_sra := (msk64(63 downto 17) & v64(63 downto 47));
when 48 =>
wb_sll := v64(15 downto 0) & X"000000000000";
wb_srl := X"000000000000" & v64(63 downto 48);
wb_sra := (msk64(63 downto 16) & v64(63 downto 48));
when 49 =>
wb_sll := v64(14 downto 0) & X"000000000000" & "0";
wb_srl := X"000000000000" & "0" & v64(63 downto 49);
wb_sra := (msk64(63 downto 15) & v64(63 downto 49));
when 50 =>
wb_sll := v64(13 downto 0) & X"000000000000" & "00";
wb_srl := X"000000000000" & "00" & v64(63 downto 50);
wb_sra := (msk64(63 downto 14) & v64(63 downto 50));
when 51 =>
wb_sll := v64(12 downto 0) & X"000000000000" & "000";
wb_srl := X"000000000000" & "000" & v64(63 downto 51);
wb_sra := (msk64(63 downto 13) & v64(63 downto 51));
when 52 =>
wb_sll := v64(11 downto 0) & X"0000000000000";
wb_srl := X"0000000000000" & v64(63 downto 52);
wb_sra := (msk64(63 downto 12) & v64(63 downto 52));
when 53 =>
wb_sll := v64(10 downto 0) & X"0000000000000" & "0";
wb_srl := X"0000000000000" & "0" & v64(63 downto 53);
wb_sra := (msk64(63 downto 11) & v64(63 downto 53));
when 54 =>
wb_sll := v64(9 downto 0) & X"0000000000000" & "00";
wb_srl := X"0000000000000" & "00" & v64(63 downto 54);
wb_sra := (msk64(63 downto 10) & v64(63 downto 54));
when 55 =>
wb_sll := v64(8 downto 0) & X"0000000000000" & "000";
wb_srl := X"0000000000000" & "000" & v64(63 downto 55);
wb_sra := (msk64(63 downto 9) & v64(63 downto 55));
when 56 =>
wb_sll := v64(7 downto 0) & X"00000000000000";
wb_srl := X"00000000000000" & v64(63 downto 56);
wb_sra := (msk64(63 downto 8) & v64(63 downto 56));
when 57 =>
wb_sll := v64(6 downto 0) & X"00000000000000" & "0";
wb_srl := X"00000000000000" & "0" & v64(63 downto 57);
wb_sra := (msk64(63 downto 7) & v64(63 downto 57));
when 58 =>
wb_sll := v64(5 downto 0) & X"00000000000000" & "00";
wb_srl := X"00000000000000" & "00" & v64(63 downto 58);
wb_sra := (msk64(63 downto 6) & v64(63 downto 58));
when 59 =>
wb_sll := v64(4 downto 0) & X"00000000000000" & "000";
wb_srl := X"00000000000000" & "000" & v64(63 downto 59);
wb_sra := (msk64(63 downto 5) & v64(63 downto 59));
when 60 =>
wb_sll := v64(3 downto 0) & X"000000000000000";
wb_srl := X"000000000000000" & v64(63 downto 60);
wb_sra := (msk64(63 downto 4) & v64(63 downto 60));
when 61 =>
wb_sll := v64(2 downto 0) & X"000000000000000" & "0";
wb_srl := X"000000000000000" & "0" & v64(63 downto 61);
wb_sra := (msk64(63 downto 3) & v64(63 downto 61));
when 62 =>
wb_sll := v64(1 downto 0) & X"000000000000000" & "00";
wb_srl := X"000000000000000" & "00" & v64(63 downto 62);
wb_sra := (msk64(63 downto 2) & v64(63 downto 62));
when 63 =>
wb_sll := v64(0) & X"000000000000000" & "000";
wb_srl := X"000000000000000" & "000" & v64(63);
wb_sra := (msk64(63 downto 1) & v64(63));
end case;
case shift32 is
when 0 =>
wb_sllw(31 downto 0) := v32;
wb_srlw(31 downto 0) := v32;
wb_sraw := (msk32(63 downto 32) & v32);
when 1 =>
wb_sllw(31 downto 0) := v32(30 downto 0) & "0";
wb_srlw(31 downto 0) := "0" & v32(31 downto 1);
wb_sraw := (msk32(63 downto 31) & v32(31 downto 1));
when 2 =>
wb_sllw(31 downto 0) := v32(29 downto 0) & "00";
wb_srlw(31 downto 0) := "00" & v32(31 downto 2);
wb_sraw := (msk32(63 downto 30) & v32(31 downto 2));
when 3 =>
wb_sllw(31 downto 0) := v32(28 downto 0) & "000";
wb_srlw(31 downto 0) := "000" & v32(31 downto 3);
wb_sraw := (msk32(63 downto 29) & v32(31 downto 3));
when 4 =>
wb_sllw(31 downto 0) := v32(27 downto 0) & X"0";
wb_srlw(31 downto 0) := X"0" & v32(31 downto 4);
wb_sraw := (msk32(63 downto 28) & v32(31 downto 4));
when 5 =>
wb_sllw(31 downto 0) := v32(26 downto 0) & X"0" & "0";
wb_srlw(31 downto 0) := X"0" & "0" & v32(31 downto 5);
wb_sraw := (msk32(63 downto 27) & v32(31 downto 5));
when 6 =>
wb_sllw(31 downto 0) := v32(25 downto 0) & X"0" & "00";
wb_srlw(31 downto 0) := X"0" & "00" & v32(31 downto 6);
wb_sraw := (msk32(63 downto 26) & v32(31 downto 6));
when 7 =>
wb_sllw(31 downto 0) := v32(24 downto 0) & X"0" & "000";
wb_srlw(31 downto 0) := X"0" & "000" & v32(31 downto 7);
wb_sraw := (msk32(63 downto 25) & v32(31 downto 7));
when 8 =>
wb_sllw(31 downto 0) := v32(23 downto 0) & X"00";
wb_srlw(31 downto 0) := X"00" & v32(31 downto 8);
wb_sraw := (msk32(63 downto 24) & v32(31 downto 8));
when 9 =>
wb_sllw(31 downto 0) := v32(22 downto 0) & X"00" & "0";
wb_srlw(31 downto 0) := X"00" & "0" & v32(31 downto 9);
wb_sraw := (msk32(63 downto 23) & v32(31 downto 9));
when 10 =>
wb_sllw(31 downto 0) := v32(21 downto 0) & X"00" & "00";
wb_srlw(31 downto 0) := X"00" & "00" & v32(31 downto 10);
wb_sraw := (msk32(63 downto 22) & v32(31 downto 10));
when 11 =>
wb_sllw(31 downto 0) := v32(20 downto 0) & X"00" & "000";
wb_srlw(31 downto 0) := X"00" & "000" & v32(31 downto 11);
wb_sraw := (msk32(63 downto 21) & v32(31 downto 11));
when 12 =>
wb_sllw(31 downto 0) := v32(19 downto 0) & X"000";
wb_srlw(31 downto 0) := X"000" & v32(31 downto 12);
wb_sraw := (msk32(63 downto 20) & v32(31 downto 12));
when 13 =>
wb_sllw(31 downto 0) := v32(18 downto 0) & X"000" & "0";
wb_srlw(31 downto 0) := X"000" & "0" & v32(31 downto 13);
wb_sraw := (msk32(63 downto 19) & v32(31 downto 13));
when 14 =>
wb_sllw(31 downto 0) := v32(17 downto 0) & X"000" & "00";
wb_srlw(31 downto 0) := X"000" & "00" & v32(31 downto 14);
wb_sraw := (msk32(63 downto 18) & v32(31 downto 14));
when 15 =>
wb_sllw(31 downto 0) := v32(16 downto 0) & X"000" & "000";
wb_srlw(31 downto 0) := X"000" & "000" & v32(31 downto 15);
wb_sraw := (msk32(63 downto 17) & v32(31 downto 15));
when 16 =>
wb_sllw(31 downto 0) := v32(15 downto 0) & X"0000";
wb_srlw(31 downto 0) := X"0000" & v32(31 downto 16);
wb_sraw := (msk32(63 downto 16) & v32(31 downto 16));
when 17 =>
wb_sllw(31 downto 0) := v32(14 downto 0) & X"0000" & "0";
wb_srlw(31 downto 0) := X"0000" & "0" & v32(31 downto 17);
wb_sraw := (msk32(63 downto 15) & v32(31 downto 17));
when 18 =>
wb_sllw(31 downto 0) := v32(13 downto 0) & X"0000" & "00";
wb_srlw(31 downto 0) := X"0000" & "00" & v32(31 downto 18);
wb_sraw := (msk32(63 downto 14) & v32(31 downto 18));
when 19 =>
wb_sllw(31 downto 0) := v32(12 downto 0) & X"0000" & "000";
wb_srlw(31 downto 0) := X"0000" & "000" & v32(31 downto 19);
wb_sraw := (msk32(63 downto 13) & v32(31 downto 19));
when 20 =>
wb_sllw(31 downto 0) := v32(11 downto 0) & X"00000";
wb_srlw(31 downto 0) := X"00000" & v32(31 downto 20);
wb_sraw := (msk32(63 downto 12) & v32(31 downto 20));
when 21 =>
wb_sllw(31 downto 0) := v32(10 downto 0) & X"00000" & "0";
wb_srlw(31 downto 0) := X"00000" & "0" & v32(31 downto 21);
wb_sraw := (msk32(63 downto 11) & v32(31 downto 21));
when 22 =>
wb_sllw(31 downto 0) := v32(9 downto 0) & X"00000" & "00";
wb_srlw(31 downto 0) := X"00000" & "00" & v32(31 downto 22);
wb_sraw := (msk32(63 downto 10) & v32(31 downto 22));
when 23 =>
wb_sllw(31 downto 0) := v32(8 downto 0) & X"00000" & "000";
wb_srlw(31 downto 0) := X"00000" & "000" & v32(31 downto 23);
wb_sraw := (msk32(63 downto 9) & v32(31 downto 23));
when 24 =>
wb_sllw(31 downto 0) := v32(7 downto 0) & X"000000";
wb_srlw(31 downto 0) := X"000000" & v32(31 downto 24);
wb_sraw := (msk32(63 downto 8) & v32(31 downto 24));
when 25 =>
wb_sllw(31 downto 0) := v32(6 downto 0) & X"000000" & "0";
wb_srlw(31 downto 0) := X"000000" & "0" & v32(31 downto 25);
wb_sraw := (msk32(63 downto 7) & v32(31 downto 25));
when 26 =>
wb_sllw(31 downto 0) := v32(5 downto 0) & X"000000" & "00";
wb_srlw(31 downto 0) := X"000000" & "00" & v32(31 downto 26);
wb_sraw := (msk32(63 downto 6) & v32(31 downto 26));
when 27 =>
wb_sllw(31 downto 0) := v32(4 downto 0) & X"000000" & "000";
wb_srlw(31 downto 0) := X"000000" & "000" & v32(31 downto 27);
wb_sraw := (msk32(63 downto 5) & v32(31 downto 27));
when 28 =>
wb_sllw(31 downto 0) := v32(3 downto 0) & X"0000000";
wb_srlw(31 downto 0) := X"0000000" & v32(31 downto 28);
wb_sraw := (msk32(63 downto 4) & v32(31 downto 28));
when 29 =>
wb_sllw(31 downto 0) := v32(2 downto 0) & X"0000000" & "0";
wb_srlw(31 downto 0) := X"0000000" & "0" & v32(31 downto 29);
wb_sraw := (msk32(63 downto 3) & v32(31 downto 29));
when 30 =>
wb_sllw(31 downto 0) := v32(1 downto 0) & X"0000000" & "00";
wb_srlw(31 downto 0) := X"0000000" & "00" & v32(31 downto 30);
wb_sraw := (msk32(63 downto 2) & v32(31 downto 30));
when 31 =>
wb_sllw(31 downto 0) := v32(0) & X"0000000" & "000";
wb_srlw(31 downto 0) := X"0000000" & "000" & v32(31 downto 31);
wb_sraw := (msk32(63 downto 1) & v32(31 downto 31));
end case;
-- Take into account case when shift = 0 and input value a[31]=1
wb_srlw(63 downto 32) := (others => wb_srlw(31));
wb_sllw(63 downto 32) := (others => wb_sllw(31));
o_sll <= wb_sll;
o_srl <= wb_srl;
o_sra <= wb_sra;
o_sllw <= wb_sllw;
o_srlw <= wb_srlw;
o_sraw <= wb_sraw;
end process;
end;
| apache-2.0 | 8b7f77665ba40ef12edf85829d454aa3 | 0.519132 | 2.881496 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/rocketlib/types_rocket.vhd | 1 | 16,150 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief System Top level modules and interconnect declarations.
-----------------------------------------------------------------------------
--! Standard library.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
use techmap.gencomp.all;
--! CPU, System Bus and common peripheries library.
library ambalib;
use ambalib.types_amba4.all;
--! @brief Declaration of components visible on SoC top level.
package types_rocket is
--! @name Scala inherited constants.
--! @brief The following constants were define in Rocket-chip generator.
--! @{
--! @brief Bits allocated for the memory tag value.
--! @details This value is defined \i Config.scala and depends of others
--! configuration paramters, like number of master, clients, channels
--! and so on. It is not used in VHDL implemenation.
constant MEM_TAG_BITS : integer := 6;
--! @brief SCALA generated value. Not used in VHDL.
constant MEM_ADDR_BITS : integer := 26;
--! @}
--! @name Rocket Chip interrupt pins
--!
--! Interrupts types:
--! 1. Local (inside tile) Software interrupts
--! 2. Local (inside tile) interrupts from timer
--! 3. External (global) interrupts from PLIC (Platorm-Level Interrupt Controller).
--! @}
constant CFG_CORE_IRQ_DEBUG : integer := 0;
--! Local Timer's interrupt (machine mode)
constant CFG_CORE_IRQ_MTIP : integer := CFG_CORE_IRQ_DEBUG + 1;
--! Local sofware interrupt (machine mode)
constant CFG_CORE_IRQ_MSIP : integer := CFG_CORE_IRQ_MTIP + 1;
--! External PLIC's interrupt (machine mode)
constant CFG_CORE_IRQ_MEIP : integer := CFG_CORE_IRQ_MSIP + 1;
--! External PLIC's interrupt (superuser mode)
constant CFG_CORE_IRQ_SEIP : integer := CFG_CORE_IRQ_MEIP + 1;
-- Total number of implemented interrupts
constant CFG_CORE_IRQ_TOTAL : integer := CFG_CORE_IRQ_SEIP + 1;
--! @}
--! @name Memory Transaction types.
--! @details TileLinkIO interface uses these constant to identify the payload
--! size of the transaction.
--! @{
constant MT_B : integer := 0; --! int8_t Memory Transaction.
constant MT_H : integer := 1; --! int16_t Memory Transaction.
constant MT_W : integer := 2; --! int32_t Memory Transaction.
constant MT_D : integer := 3; --! int64_t Memory Transaction.
constant MT_BU : integer := 4; --! uint8_t Memory Transaction.
constant MT_HU : integer := 5; --! uint16_t Memory Transaction.
constant MT_WU : integer := 6; --! uint32_t Memory Transaction.
constant MT_Q : integer := 7; --! AXI data-width Memory Transaction (default 128-bits).
--! @}
--! @brief Memory operation types
--! @details The union bits [5:1] contains information about current transaction
constant M_XRD : std_logic_vector(4 downto 0) := "00000"; --! int load
constant M_XWR : std_logic_vector(4 downto 0) := "00001"; --! int store
constant M_PFR : std_logic_vector(4 downto 0) := "00010"; --! prefetch with intent to read
constant M_PFW : std_logic_vector(4 downto 0) := "00011"; --! prefetch with intent to write
constant M_XA_SWAP : std_logic_vector(4 downto 0) := "00100";
constant M_NOP : std_logic_vector(4 downto 0) := "00101";
constant M_XLR : std_logic_vector(4 downto 0) := "00110";
constant M_XSC : std_logic_vector(4 downto 0) := "00111";
constant M_XA_ADD : std_logic_vector(4 downto 0) := "01000";
constant M_XA_XOR : std_logic_vector(4 downto 0) := "01001";
constant M_XA_OR : std_logic_vector(4 downto 0) := "01010";
constant M_XA_AND : std_logic_vector(4 downto 0) := "01011";
constant M_XA_MIN : std_logic_vector(4 downto 0) := "01100";
constant M_XA_MAX : std_logic_vector(4 downto 0) := "01101";
constant M_XA_MINU : std_logic_vector(4 downto 0) := "01110";
constant M_XA_MAXU : std_logic_vector(4 downto 0) := "01111";
constant M_FLUSH : std_logic_vector(4 downto 0) := "10000"; --! write back dirty data and cede R/W permissions
constant M_PRODUCE : std_logic_vector(4 downto 0) := "10001"; --! write back dirty data and cede W permissions
constant M_CLEAN : std_logic_vector(4 downto 0) := "10011"; --! write back dirty data and retain R/W permissions
function isAMO(cmd : std_logic_vector(4 downto 0)) return std_logic;
--def isPrefetch(cmd: UInt) = cmd === M_PFR || cmd === M_PFW
--def isRead(cmd: UInt) = cmd === M_XRD || cmd === M_XLR || cmd === M_XSC || isAMO(cmd)
function isWrite(cmd : std_logic_vector(4 downto 0)) return std_logic;
--def isWriteIntent(cmd: UInt) = isWrite(cmd) || cmd === M_PFW || cmd === M_XLR
--! <Definitions.scala> Object Acquire {}
constant ACQUIRE_GET_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "000"; -- Get a single beat of data
constant ACQUIRE_GET_BLOCK_DATA : std_logic_vector(2 downto 0) := "001"; -- Get a whole block of data
constant ACQUIRE_PUT_SINGLE_DATA_BEAT : std_logic_vector(2 downto 0) := "010"; -- Put a single beat of data.
constant ACQUIRE_PUT_BLOCK_DATA : std_logic_vector(2 downto 0) := "011"; -- Put a whole block of data.
constant ACQUIRE_PUT_ATOMIC_DATA : std_logic_vector(2 downto 0) := "100"; -- Performe an atomic memory op
constant ACQUIRE_GET_PREFETCH_BLOCK : std_logic_vector(2 downto 0) := "101"; -- Prefetch a whole block of data
constant ACQUIRE_PUT_PREFETCH_BLOCK : std_logic_vector(2 downto 0) := "110"; -- Prefetch a whole block of data, with intent to write
--! <tilelink.scala> Object Grant {}
constant GRANT_ACK_RELEASE : std_logic_vector(3 downto 0) := "0000"; -- For acking Releases
constant GRANT_ACK_PREFETCH : std_logic_vector(3 downto 0) := "0001"; -- For acking any kind of Prefetch
constant GRANT_ACK_NON_PREFETCH_PUT : std_logic_vector(3 downto 0) := "0011"; -- For acking any kind of non-prfetch Put
constant GRANT_SINGLE_BEAT_GET : std_logic_vector(3 downto 0) := "0100"; -- Supplying a single beat of Get
constant GRANT_BLOCK_GET : std_logic_vector(3 downto 0) := "0101"; -- Supplying all beats of a GetBlock
--! MESI coherence
constant CACHED_ACQUIRE_SHARED : std_logic_vector(2 downto 0) := "000"; -- get
constant CACHED_ACQUIRE_EXCLUSIVE : std_logic_vector(2 downto 0) := "001"; -- put
constant CACHED_GRANT_SHARED : std_logic_vector(3 downto 0) := "0000";
constant CACHED_GRANT_EXCLUSIVE : std_logic_vector(3 downto 0) := "0001";
constant CACHED_GRANT_EXCLUSIVE_ACK : std_logic_vector(3 downto 0) := "0010";
--! @brief Memory Operation size decoder
--! @details TileLink bus has encoded Memory Operation size
--! in the union[n+1:n] bits of the acquire request.
--! @warning Sign bit isn't transmitted in union since 20160930.
constant MEMOP_XSIZE_TOTAL : integer := 8;
type memop_xsize_type is array (0 to MEMOP_XSIZE_TOTAL-1) of std_logic_vector(2 downto 0);
constant opSizeToXSize : memop_xsize_type := (
MT_B => "000",
MT_H => "001",
MT_W => "010",
MT_D => "011",
MT_BU => "100",
MT_HU => "101",
MT_WU => "110",
MT_Q => conv_std_logic_vector(log2(CFG_SYSBUS_DATA_BYTES),3)
);
type tile_in_type is record
a_ready : std_logic;
b_valid : std_logic;
b_opcode : std_logic_vector(2 downto 0);
b_param : std_logic_vector(1 downto 0);
b_size : std_logic_vector(3 downto 0);
b_source : std_logic_vector(2 downto 0);
b_address : std_logic_vector(31 downto 0);
b_mask : std_logic_vector(7 downto 0);
b_data : std_logic_vector(63 downto 0);
c_ready : std_logic;
d_valid : std_logic;
d_opcode : std_logic_vector(2 downto 0);
d_param : std_logic_vector(1 downto 0);
d_size : std_logic_vector(3 downto 0);
d_source : std_logic_vector(2 downto 0);
d_sink : std_logic_vector(3 downto 0);
d_addr_lo : std_logic_vector(2 downto 0);
d_data : std_logic_vector(63 downto 0);
d_error : std_logic;
e_ready : std_logic;
end record;
type tile_out_type is record
a_valid : std_logic;
a_opcode : std_logic_vector(2 downto 0);
a_param : std_logic_vector(2 downto 0);
a_size : std_logic_vector(3 downto 0);
a_source : std_logic_vector(2 downto 0);
a_address : std_logic_vector(31 downto 0);
a_mask : std_logic_vector(7 downto 0);
a_data : std_logic_vector(63 downto 0);
b_ready : std_logic;
c_valid : std_logic;
c_opcode : std_logic_vector(2 downto 0);
c_param : std_logic_vector(2 downto 0);
c_size : std_logic_vector(3 downto 0);
c_source : std_logic_vector(2 downto 0);
c_address : std_logic_vector(31 downto 0);
c_data : std_logic_vector(63 downto 0);
c_error : std_logic;
d_ready : std_logic;
e_valid : std_logic;
e_sink : std_logic_vector(3 downto 0);
end record;
--! @brief Decode Acquire request from the Cached/Uncached TileLink
--! @param[in] a_type Request type depends of the built_in flag
--! @param[in] built_in This flag defines cached or uncached request. For
--! the uncached this value is set to 1.
--! @param[in] u Union bits. This value is decoding depending of
--! types operation (rd/wr) and cached/uncached.
procedure procedureDecodeTileAcquire (
a_type : in std_logic_vector(2 downto 0);
built_in : in std_logic;
u : in std_logic_vector(10 downto 0);--was 16
write : out std_logic;
wmask : out std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
axi_sz : out std_logic_vector(2 downto 0);
byte_addr : out std_logic_vector(2 downto 0);
beat_cnt : out integer
);
--! @brief RocketTile component declaration.
--! @details This module implements Risc-V Core with L1-cache,
--! branch predictor and other stuffs of the RocketTile.
--! @param[in] xindex1 Cached Tile AXI master index
--! @param[in] xindex2 Uncached Tile AXI master index
--! @param[in] hartid Tile ID. At least 0 must be implemented.
--! @param[in] reset_vector Reset instruction pointer value.
--! @param[in] rst Reset signal with active HIGH level.
--! @param[in] soft_rst Software Reset via DSU
--! @param[in] clk_sys System clock (BUS/CPU clock).
--! @param[in] slvo Bus-to-Slave device signals.
--! @param[in] msti Bus-to-Master device signals.
--! @param[out] msto1 CachedTile-to-Bus request signals.
--! @param[out] msto2 UncachedTile-to-Bus request signals.
--! @param[in] interrupts Interrupts line supported by Rocket chip.
component rocket_l1only is
generic (
hartid : integer := 0;
reset_vector : integer := 16#1000#
);
port (
nrst : in std_logic;
clk_sys : in std_logic;
msti1 : in axi4_master_in_type;
msto1 : out axi4_master_out_type;
mstcfg1 : out axi4_master_config_type;
msti2 : in axi4_master_in_type;
msto2 : out axi4_master_out_type;
mstcfg2 : out axi4_master_config_type;
interrupts : in std_logic_vector(CFG_CORE_IRQ_TOTAL-1 downto 0)
);
end component;
end; -- package declaration
--! -----------------
package body types_rocket is
function isAMO(cmd : std_logic_vector(4 downto 0))
return std_logic is
variable t1 : std_logic;
begin
t1 := '0';
if cmd = M_XA_SWAP then
t1 := '1';
end if;
return (cmd(3) or t1);
end;
function isWrite(cmd : std_logic_vector(4 downto 0))
return std_logic is
variable ret : std_logic;
begin
ret := isAMO(cmd);
if cmd = M_XWR then ret := '1'; end if;
if cmd = M_XSC then ret := '1'; end if;
return (ret);
end;
--! @brief Decode Acquire request from the Cached/Uncached TileLink
--! @param[in] a_type Request type depends of the built_in flag
--! @param[in] built_in This flag defines cached or uncached request. For
--! the uncached this value is set to 1.
--! @param[in] u Union bits. This value is decoding depending of
--! types operation (rd/wr) and cached/uncached.
procedure procedureDecodeTileAcquire(
a_type : in std_logic_vector(2 downto 0);
built_in : in std_logic;
u : in std_logic_vector(10 downto 0);--was 16
write : out std_logic;
wmask : out std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
axi_sz : out std_logic_vector(2 downto 0);
byte_addr : out std_logic_vector(2 downto 0);
beat_cnt : out integer
) is
begin
if built_in = '1' then
-- Cached request
case a_type is
when ACQUIRE_GET_SINGLE_DATA_BEAT =>
write := '0';
wmask := (others => '0');
--! union used as:
--! addr[2:0] & op_sz[1:0] & mem_op_code[M_SZ-1:0] & alloc[0]
--! [10:8][7:6][5:1][0]
byte_addr := u(10 downto 8);--tst.block.byte_addr;
axi_sz := opSizeToXSize(conv_integer(u(7 downto 6)));
beat_cnt := 0;
when ACQUIRE_GET_PREFETCH_BLOCK |
ACQUIRE_PUT_PREFETCH_BLOCK |
ACQUIRE_GET_BLOCK_DATA =>
-- cache line size / data bits width
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_SYSBUS_ADDR_OFFSET,3);
beat_cnt := 7;--3;--tlDataBeats-1;
when ACQUIRE_PUT_SINGLE_DATA_BEAT =>
-- Single beat data.
write := '1';
--! union used as:
--! wmask[log2(64)-1:0] & alloc[0]
wmask := u(CFG_SYSBUS_DATA_BYTES downto 1);
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_SYSBUS_ADDR_OFFSET,3);
beat_cnt := 0;
when ACQUIRE_PUT_BLOCK_DATA =>
-- Multibeat data.
write := '1';
wmask := (others => '1');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_SYSBUS_ADDR_OFFSET,3);
beat_cnt := 7;--3;--tlDataBeats-1;
when ACQUIRE_PUT_ATOMIC_DATA =>
-- Single beat data. 64 bits width
write := '1';
--if CFG_NASTI_DATA_BITS = 128 then
-- if u(12) = '0' then
-- wmask(7 downto 0) := (others => '1');
-- wmask(15 downto 8) := (others => '0');
-- else
-- wmask(7 downto 0) := (others => '0');
-- wmask(15 downto 8) := (others => '1');
-- end if;
--else
wmask := (others => '1');
--end if;
byte_addr := (others => '0');
axi_sz := opSizeToXSize(conv_integer(u(7 downto 6)));
beat_cnt := 0;
when others =>
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := (others => '0');
beat_cnt := 0;
end case;
else --! built_in = '0'
--! Cached request
case a_type is
when CACHED_ACQUIRE_SHARED =>
--! Uncore/coherence/Metadata.scala
--! union = op_code[4:0] & '1';
write := '0';
wmask := (others => '0');
byte_addr := u(10 downto 8);--tst.block.byte_addr;
axi_sz := opSizeToXSize(conv_integer(u(7 downto 6)));
beat_cnt := 0;
when CACHED_ACQUIRE_EXCLUSIVE =>
-- Single beat data.
write := '1';
--! Uncore/coherence/Metadata.scala
--! union = op_code[4:0] & '1';
--! unclear how to manage it.
--wmask := u(CFG_NASTI_DATA_BYTES downto 1);
wmask := (others => '1');
byte_addr := (others => '0');
axi_sz := conv_std_logic_vector(CFG_SYSBUS_ADDR_OFFSET,3);
beat_cnt := 0;
when others =>
write := '0';
wmask := (others => '0');
byte_addr := (others => '0');
axi_sz := (others => '0');
beat_cnt := 0;
end case;
end if;
end procedure;
end; -- package body
| apache-2.0 | d82a49a0d7d17889992ea48816e022f6 | 0.600124 | 3.444231 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/common/rd_pe_as.vhd | 19 | 25,238 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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| bsd-2-clause | fae0fe2e9247d18c245ce0d3c4cbf6a1 | 0.943815 | 1.845963 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/TEST_CTRL_TELEGRAM_CHECK/CTRL_TELEGRAM_CHECK.vhd | 4 | 24,417 | -- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"06")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"06"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"06"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FF") --255
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FF"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FF"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0E") --14
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0E"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0E"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"03")
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"03"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"03"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral;
| gpl-2.0 | 3519b9b0f4c0629df3d343359ffe13d0 | 0.431626 | 3.357673 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ambalib/axislv.vhd | 1 | 14,946 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
entity axi4_slave is
generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_xcfg : in axi4_slave_config_type;
i_xslvi : in axi4_slave_in_type;
o_xslvo : out axi4_slave_out_type;
i_ready : in std_logic;
i_rdata : in std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
o_re : out std_logic;
o_r32 : out std_logic;
o_radr : out global_addr_array_type;
o_wadr : out global_addr_array_type;
o_we : out std_logic;
o_wstrb : out std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
o_wdata : out std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0)
);
end;
architecture arch_axi4_slave of axi4_slave is
--! Slave device states during reading value operation.
type axi_slave_rstatetype is (rwait, rhold, rtrans);
--! Slave device states during writting data operation.
type axi_slave_wstatetype is (wwait, wtrans);
--! @brief Template bank of registers for any slave device.
type axi_slave_bank_type is record
rstate : axi_slave_rstatetype;
wstate : axi_slave_wstatetype;
rburst : std_logic_vector(1 downto 0);
rsize : integer;
raddr : global_addr_array_type;
rlen : integer; --! AXI4 supports 256 burst operation
rid : std_logic_vector(CFG_SYSBUS_ID_BITS-1 downto 0);
rresp : std_logic_vector(1 downto 0); --! OK=0
ruser : std_logic_vector(CFG_SYSBUS_USER_BITS-1 downto 0);
rswap : std_logic;
rwaitready : std_logic; --! Reading wait state flag: 0=waiting. User's waitstates
wburst : std_logic_vector(1 downto 0); -- 0=INCREMENT
wsize : integer; -- code in range 0=1 Bytes upto 7=128 Bytes.
waddr : global_addr_array_type; --! 4 KB bank
wlen : integer; --! AXI4 supports 256 burst operation
wid : std_logic_vector(CFG_SYSBUS_ID_BITS-1 downto 0);
wresp : std_logic_vector(1 downto 0); --! OK=0
wuser : std_logic_vector(CFG_SYSBUS_USER_BITS-1 downto 0);
wswap : std_logic;
b_valid : std_logic;
end record;
--! Reset value of the template bank of registers of a slave device.
constant AXI_SLAVE_BANK_RESET : axi_slave_bank_type := (
rwait, wwait,
AXI_BURST_FIXED, 0, (others=>(others=>'0')), 0, (others=>'0'), AXI_RESP_OKAY, (others => '0'), '0', '1',
AXI_BURST_FIXED, 0, (others=>(others=>'0')), 0, (others=>'0'), AXI_RESP_OKAY, (others => '0'), '0', '0'
);
signal rin, r : axi_slave_bank_type;
begin
comblogic : process(i_nrst, i_xcfg, i_xslvi, i_ready, i_rdata, r)
variable v : axi_slave_bank_type;
variable traddr : std_logic_vector(CFG_SYSBUS_ADDR_BITS-1 downto 0);
variable twaddr : std_logic_vector(CFG_SYSBUS_ADDR_BITS-1 downto 0);
variable v_raddr_bus : global_addr_array_type;
variable v_raddr_bus_swp : global_addr_array_type;
variable v_raddr_bus_nxt : global_addr_array_type;
variable v_raddr_bus_nxt_swp : global_addr_array_type;
variable v_raddr_burst_nxt_swp : global_addr_array_type;
variable v_wadr_bus : global_addr_array_type;
variable v_wadr_bus_swp : global_addr_array_type;
variable v_waddr_burst_nxt_swp : global_addr_array_type;
variable v_re : std_logic;
variable v_r32 : std_logic;
variable v_radr : global_addr_array_type;
variable v_we : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
variable v_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
variable v_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable v_aw_ready : std_logic;
variable v_w_ready : std_logic;
variable v_ar_ready : std_logic;
variable v_r_valid : std_logic;
variable v_r_last : std_logic;
variable vb_r_data : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
v := r;
traddr := (i_xslvi.ar_bits.addr(CFG_SYSBUS_ADDR_BITS-1 downto 12) and (not i_xcfg.xmask))
& i_xslvi.ar_bits.addr(11 downto 0);
twaddr := (i_xslvi.aw_bits.addr(CFG_SYSBUS_ADDR_BITS-1 downto 12) and (not i_xcfg.xmask))
& i_xslvi.aw_bits.addr(11 downto 0);
for n in 0 to CFG_WORDS_ON_BUS-1 loop
v_raddr_bus(n) := traddr + n*CFG_ALIGN_BYTES;
v_raddr_bus_nxt(n) := v_raddr_bus(n) + XSizeToBytes(conv_integer(i_xslvi.ar_bits.size));
if i_xslvi.ar_bits.burst = AXI_BURST_WRAP then
v_raddr_bus_nxt(n)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= v_raddr_bus(n)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
end if;
v_wadr_bus(n) := twaddr + n*CFG_ALIGN_BYTES;
end loop;
v_re := '0';
v_r32 := '0';
v_radr(0) := (others => '0');
v_radr(1) := (others => '0');
-- Next hold read address while write transaction not finished
if i_xslvi.ar_bits.addr(2) = '0' then
v_raddr_bus_swp := v_raddr_bus;
else
v_raddr_bus_swp(0) := v_raddr_bus(1);
v_raddr_bus_swp(1) := v_raddr_bus(0);
end if;
-- Next read accepted address if no write request
if (i_xslvi.ar_bits.addr(2) = '0' and i_xslvi.ar_bits.size = "011") or
(i_xslvi.ar_bits.addr(2) = '1' and i_xslvi.ar_bits.size = "010") then
v_raddr_bus_nxt_swp := v_raddr_bus_nxt;
else
v_raddr_bus_nxt_swp(0) := v_raddr_bus_nxt(1);
v_raddr_bus_nxt_swp(1) := v_raddr_bus_nxt(0);
end if;
-- Next burst read address
if r.rsize = 4 then
v_raddr_burst_nxt_swp(0) := r.raddr(1) + r.rsize;
v_raddr_burst_nxt_swp(1) := r.raddr(0) + r.rsize;
if r.rburst = AXI_BURST_WRAP then
v_raddr_burst_nxt_swp(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.raddr(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
v_raddr_burst_nxt_swp(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.raddr(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
end if;
else
v_raddr_burst_nxt_swp(0) := r.raddr(0) + r.rsize;
v_raddr_burst_nxt_swp(1) := r.raddr(1) + r.rsize;
if r.rburst = AXI_BURST_WRAP then
v_raddr_burst_nxt_swp(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.raddr(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
v_raddr_burst_nxt_swp(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.raddr(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
end if;
end if;
-- Write swapped address
if i_xslvi.aw_bits.addr(2) = '0' then
v_wadr_bus_swp := v_wadr_bus;
else
v_wadr_bus_swp(0) := v_wadr_bus(1);
v_wadr_bus_swp(1) := v_wadr_bus(0);
end if;
-- Next burst write address
if r.wsize = 4 then
v_waddr_burst_nxt_swp(0) := r.waddr(1) + r.wsize;
v_waddr_burst_nxt_swp(1) := r.waddr(0) + r.wsize;
if r.wburst = AXI_BURST_WRAP then
v_waddr_burst_nxt_swp(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.waddr(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
v_waddr_burst_nxt_swp(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.waddr(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
end if;
else
v_waddr_burst_nxt_swp(0) := r.waddr(0) + r.wsize;
v_waddr_burst_nxt_swp(1) := r.waddr(1) + r.wsize;
if r.wburst = AXI_BURST_WRAP then
v_waddr_burst_nxt_swp(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.waddr(0)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
v_waddr_burst_nxt_swp(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5)
:= r.waddr(1)(CFG_SYSBUS_ADDR_BITS-1 downto 5);
end if;
end if;
v_we := (others => '0');
v_ar_ready := '0';
v_r_valid := '0';
v_r_last := '0';
v_aw_ready := '0';
v_w_ready := '0';
-- Reading state machine:
case r.rstate is
when rwait =>
v_ar_ready := '1';
v_radr := v_raddr_bus_swp;
if i_xslvi.ar_valid = '1' then
if i_xslvi.aw_valid = '0' and r.wstate = wwait then
v_re := '1';
v.rstate := rtrans;
v.raddr := v_raddr_bus_nxt_swp;
else
v.rstate := rhold;
v.raddr := v_raddr_bus_swp;
end if;
if i_xslvi.ar_bits.size = "010" then
v_r32 := '1';
end if;
v.rswap := i_xslvi.ar_bits.addr(2);
v.rsize := XSizeToBytes(conv_integer(i_xslvi.ar_bits.size));
v.rburst := i_xslvi.ar_bits.burst;
v.rlen := conv_integer(i_xslvi.ar_bits.len);
v.rid := i_xslvi.ar_id;
v.rresp := AXI_RESP_OKAY;
v.ruser := i_xslvi.ar_user;
end if;
when rhold =>
v_radr := r.raddr;
if r.rsize = 4 then
v_r32 := '1';
end if;
if i_xslvi.aw_valid = '0' and r.wstate = wwait then
v_re := '1';
v.rstate := rtrans;
v.raddr := v_raddr_burst_nxt_swp;
end if;
when rtrans =>
v_r_valid := i_ready;
v_radr := r.raddr;
if r.rlen /= 0 then
v_re := '1'; -- request next burst read address even if no ready data
end if;
if r.rsize = 4 then
v_r32 := '1';
end if;
if i_xslvi.r_ready = '1' and i_ready = '1' then
if r.rsize = 4 then
v.rswap := not r.rswap;
end if;
v.raddr := v_raddr_burst_nxt_swp;
-- End of transaction (or process another one):
if r.rlen = 0 then
v_r_last := '1';
v_ar_ready := '1';
v_radr := v_raddr_bus_swp;
if i_xslvi.ar_valid = '1' then
if i_xslvi.aw_valid = '0' and r.wstate = wwait then
v_re := '1';
v.rstate := rtrans;
v.raddr := v_raddr_bus_nxt_swp;
else
v.rstate := rhold;
v.raddr := v_raddr_bus_swp;
end if;
if i_xslvi.ar_bits.size = "010" then
v_r32 := '1';
end if;
v.rswap := i_xslvi.ar_bits.addr(2);
v.rsize := XSizeToBytes(conv_integer(i_xslvi.ar_bits.size));
v.rburst := i_xslvi.ar_bits.burst;
v.rlen := conv_integer(i_xslvi.ar_bits.len);
v.rid := i_xslvi.ar_id;
v.rresp := AXI_RESP_OKAY;
v.ruser := i_xslvi.ar_user;
else
v.rstate := rwait;
end if;
else
v.rlen := r.rlen - 1;
end if;
end if;
end case;
-- Writing state machine:
case r.wstate is
when wwait =>
if r.rlen = 0 or r.rstate = rhold then
v_aw_ready := '1';
end if;
if i_xslvi.aw_valid = '1' and (r.rlen = 0 or r.rstate = rhold) then
v.wstate := wtrans;
v.waddr := v_wadr_bus_swp;
v.wswap := i_xslvi.aw_bits.addr(2);
v.wsize := XSizeToBytes(conv_integer(i_xslvi.aw_bits.size));
v.wburst := i_xslvi.aw_bits.burst;
v.wlen := conv_integer(i_xslvi.aw_bits.len);
v.wid := i_xslvi.aw_id;
v.wresp := AXI_RESP_OKAY;
v.wuser := i_xslvi.aw_user;
end if;
when wtrans =>
v_we := (others => '1');
v_w_ready := i_ready;
if i_xslvi.w_valid = '1' and i_ready = '1' then
if r.wsize = 4 then
v.wswap := not r.wswap;
end if;
v.waddr := v_waddr_burst_nxt_swp;
-- End of transaction:
if r.wlen = 0 then
v.b_valid := '1';
v_aw_ready := '1';
if i_xslvi.aw_valid = '0' then
v.wstate := wwait;
else
v.waddr := v_wadr_bus_swp;
v.wswap := i_xslvi.aw_bits.addr(2);
v.wsize := XSizeToBytes(conv_integer(i_xslvi.aw_bits.size));
v.wburst := i_xslvi.aw_bits.burst;
v.wlen := conv_integer(i_xslvi.aw_bits.len);
v.wid := i_xslvi.aw_id;
v.wresp := AXI_RESP_OKAY;
v.wuser := i_xslvi.aw_user;
end if;
else
v.wlen := r.wlen - 1;
end if;
end if;
end case;
if i_xslvi.b_ready = '1' and r.b_valid = '1' then
if r.wstate = wtrans and i_xslvi.w_valid = '1' and r.wlen = 0 then
v.b_valid := '1';
else
v.b_valid := '0';
end if;
end if;
-- AXI Lite must be 8-byte aligned in this implementation
if r.wswap = '0' then
v_wdata := i_xslvi.w_data;
v_wstrb := i_xslvi.w_strb and v_we;
else
v_wdata(31 downto 0) := i_xslvi.w_data(63 downto 32);
v_wdata(63 downto 32) := i_xslvi.w_data(31 downto 0);
v_wstrb := (i_xslvi.w_strb(3 downto 0) & i_xslvi.w_strb(7 downto 4))
and (v_we(3 downto 0) & v_we(7 downto 4));
end if;
o_re <= v_re;
o_radr <= v_radr;
o_r32 <= v_r32;
o_wadr <= r.waddr;
o_we <= v_we(0);
o_wdata <= v_wdata;
o_wstrb <= v_wstrb;
if r.rswap = '0' then
vb_r_data := i_rdata;
else
vb_r_data := i_rdata(31 downto 0) & i_rdata(63 downto 32);
end if;
if not async_reset and i_nrst = '0' then
v := AXI_SLAVE_BANK_RESET;
end if;
rin <= v;
o_xslvo.aw_ready <= v_aw_ready;
o_xslvo.w_ready <= v_w_ready;
o_xslvo.ar_ready <= v_ar_ready;
o_xslvo.r_valid <= v_r_valid;
o_xslvo.r_last <= v_r_last;
o_xslvo.r_data <= vb_r_data;
o_xslvo.r_id <= r.rid;
o_xslvo.r_resp <= r.rresp;
o_xslvo.r_user <= r.ruser;
-- Write Handshaking:
o_xslvo.b_id <= r.wid;
o_xslvo.b_resp <= r.wresp;
o_xslvo.b_user <= r.wuser;
o_xslvo.b_valid <= r.b_valid;
end process;
-- registers
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= AXI_SLAVE_BANK_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 8a47bb2b776c2a8c3de182c9c682d25d | 0.535327 | 3.028571 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/fifo_generator_v11_0_pkg.vhd | 19 | 129,958 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 94464)
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| bsd-2-clause | cecc195e2a82e9c3f01c1dc8263f331e | 0.953824 | 1.816857 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/igdsbuf_v6.vhd | 3 | 814 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Gigabits buffer with the differential signals.
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity igdsbuf_virtex6 is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end;
architecture rtl of igdsbuf_virtex6 is
begin
x1 : IBUFDS_GTXE1 port map (
I => gclk_p,
IB => gclk_n,
CEB => '0',
O => o_clk,
ODIV2 => open
);
end;
| apache-2.0 | 01d89a19ba7ea2b44a0f161ca7977645 | 0.468059 | 4.13198 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_s2mm_mngr.vhd | 1 | 50,285 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_s2mm_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA S2MM
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_s2mm_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_DM_STATUS_WIDTH : integer range 8 to 32 := 8;
-- Width of DataMover status word
-- 8 for Determinate BTT Mode
-- 32 for Indterminate BTT Mode
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_USE_STSAPP_LENGTH : integer range 0 to 1 := 1;
-- Enable or Disable use of Status Stream Rx Length. Only valid
-- if C_SG_INCLUDE_STSCNTRL_STRM = 1
-- 0 = Don't use Rx Length
-- 1 = Use Rx Length
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_S_AXIS_S2MM_STS_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Slave AXI Status Stream Data Width
-----------------------------------------------------------------------
-- Stream to Memory Map (S2MM) Parameters
-----------------------------------------------------------------------
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_M_AXI_S2MM_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for S2MM Write Port
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex5"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
-- MM2S Control and Status --
s2mm_run_stop : in std_logic ; --
s2mm_keyhole : in std_logic ;
s2mm_halted : in std_logic ; --
s2mm_ftch_idle : in std_logic ; --
s2mm_updt_idle : in std_logic ; --
s2mm_tailpntr_enble : in std_logic ; --
s2mm_ftch_err_early : in std_logic ; --
s2mm_ftch_stale_desc : in std_logic ; --
s2mm_halt : in std_logic ; --
s2mm_halt_cmplt : in std_logic ; --
s2mm_packet_eof_out : out std_logic ;
s2mm_halted_clr : out std_logic ; --
s2mm_halted_set : out std_logic ; --
s2mm_idle_set : out std_logic ; --
s2mm_idle_clr : out std_logic ; --
s2mm_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s2mm_new_curdesc_wren : out std_logic ; --
s2mm_stop : out std_logic ; --
s2mm_desc_flush : out std_logic ; --
s2mm_all_idle : out std_logic ; --
s2mm_error : out std_logic ; --
mm2s_error : in std_logic ; --
s2mm_desc_info_in : in std_logic_vector (13 downto 0) ;
-- Simple DMA Mode Signals
s2mm_da : in std_logic_vector --
(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); --
s2mm_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_length_wren : in std_logic ; --
s2mm_smple_done : out std_logic ; --
s2mm_interr_set : out std_logic ; --
s2mm_slverr_set : out std_logic ; --
s2mm_decerr_set : out std_logic ; --
s2mm_bytes_rcvd : out std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
s2mm_bytes_rcvd_wren : out std_logic ; --
--
-- SG S2MM Descriptor Fetch AXI Stream In --
m_axis_s2mm_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid : in std_logic ; --
m_axis_s2mm_ftch_tready : out std_logic ; --
m_axis_s2mm_ftch_tlast : in std_logic ; --
m_axis_s2mm_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_s2mm_ftch_tdata_mcdma_nxt : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_s2mm_ftch_tvalid_new : in std_logic ; --
m_axis_ftch2_desc_available : in std_logic;
--
--
-- SG S2MM Descriptor Update AXI Stream Out --
s_axis_s2mm_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtptr_tvalid : out std_logic ; --
s_axis_s2mm_updtptr_tready : in std_logic ; --
s_axis_s2mm_updtptr_tlast : out std_logic ; --
--
s_axis_s2mm_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0) ; --
s_axis_s2mm_updtsts_tvalid : out std_logic ; --
s_axis_s2mm_updtsts_tready : in std_logic ; --
s_axis_s2mm_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_s2mm_cmd_tvalid : out std_logic ; --
s_axis_s2mm_cmd_tready : in std_logic ; --
s_axis_s2mm_cmd_tdata : out std_logic_vector --
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_s2mm_sts_tvalid : in std_logic ; --
m_axis_s2mm_sts_tready : out std_logic ; --
m_axis_s2mm_sts_tdata : in std_logic_vector --
(C_DM_STATUS_WIDTH - 1 downto 0) ; --
m_axis_s2mm_sts_tkeep : in std_logic_vector((C_DM_STATUS_WIDTH/8-1) downto 0); --
s2mm_err : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : in std_logic ; --
--
-- Stream to Memory Map Status Stream Interface --
s_axis_s2mm_sts_tdata : in std_logic_vector --
(C_S_AXIS_S2MM_STS_TDATA_WIDTH-1 downto 0); --
s_axis_s2mm_sts_tkeep : in std_logic_vector --
((C_S_AXIS_S2MM_STS_TDATA_WIDTH/8)-1 downto 0); --
s_axis_s2mm_sts_tvalid : in std_logic ; --
s_axis_s2mm_sts_tready : out std_logic ; --
s_axis_s2mm_sts_tlast : in std_logic --
);
end axi_dma_s2mm_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_s2mm_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal s2mm_cmnd_wr : std_logic := '0';
signal s2mm_cmnd_data : std_logic_vector
((C_M_AXI_S2MM_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal s2mm_cmnd_pending : std_logic := '0';
-- Primary DataMover Status signals
signal s2mm_done : std_logic := '0';
signal s2mm_stop_i : std_logic := '0';
signal s2mm_interr : std_logic := '0';
signal s2mm_slverr : std_logic := '0';
signal s2mm_decerr : std_logic := '0';
signal s2mm_tag : std_logic_vector(3 downto 0) := (others => '0');
signal s2mm_brcvd : std_logic_vector(C_SG_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal dma_s2mm_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal s2mm_error_i : std_logic := '0';
signal sts_strm_stop : std_logic := '0';
signal s2mm_halted_set_i : std_logic := '0';
signal s2mm_sts_received_clr : std_logic := '0';
signal s2mm_sts_received : std_logic := '0';
signal s2mm_cmnd_idle : std_logic := '0';
signal s2mm_sts_idle : std_logic := '0';
signal s2mm_eof_set : std_logic := '0';
signal s2mm_packet_eof : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal s2mm_desc_baddress : std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_info : std_logic_vector(31 downto 0) := (others => '0');
signal s2mm_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_cmplt : std_logic := '0';
signal s2mm_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s2mm_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
-- S2MM Status Stream Signals
signal s2mm_rxlength_valid : std_logic := '0';
signal s2mm_rxlength_clr : std_logic := '0';
signal s2mm_rxlength : std_logic_vector(C_SG_LENGTH_WIDTH - 1 downto 0) := (others => '0');
signal stsstrm_fifo_rden : std_logic := '0';
signal stsstrm_fifo_empty : std_logic := '0';
signal stsstrm_fifo_dout : std_logic_vector(C_S_AXIS_S2MM_STS_TDATA_WIDTH downto 0) := (others => '0');
signal s2mm_desc_flush_i : std_logic := '0';
signal updt_pending : std_logic := '0';
signal s2mm_cmnd_wr_1 : std_logic := '0';
signal s2mm_eof_micro, s2mm_sof_micro : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include S2MM (Received) Channel
-------------------------------------------------------------------------------
GEN_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 1 generate
begin
-- pass out to register module
s2mm_halted_set <= s2mm_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
s2mm_error_i <= dma_s2mm_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or s2mm_ftch_err_early -- SG Fetch engine reports early error on S2MM
or s2mm_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down mm2s
s2mm_error <= s2mm_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- s2mm_stop_i <= s2mm_error -- Error
-- or soft_reset; -- Soft Reset issued
s2mm_stop_i <= s2mm_error_i -- Error on s2mm
or mm2s_error -- Error on mm2s
or soft_reset; -- Soft Reset issued
-- Register signals out
REG_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s2mm_stop <= '0';
s2mm_desc_flush_i <= '0';
else
s2mm_stop <= s2mm_stop_i;
-- Flush any fetch descriptors if error or if run stop cleared
s2mm_desc_flush_i <= s2mm_stop_i or not s2mm_run_stop;
end if;
end if;
end process REG_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not used in Scatter Gather mode
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
-- Flush descriptors
s2mm_desc_flush <= s2mm_desc_flush_i;
OLD_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 1 and C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_ENABLE_MULTI_CHANNEL = 0) generate
begin
s2mm_cmnd_wr <= s2mm_cmnd_wr_1;
end generate OLD_CMD_WR;
NEW_CMD_WR : if (C_SG_USE_STSAPP_LENGTH = 0 or C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_ENABLE_MULTI_CHANNEL = 1) generate
begin
s2mm_cmnd_wr <= m_axis_s2mm_ftch_tvalid_new;
end generate NEW_CMD_WR;
---------------------------------------------------------------------------
-- S2MM Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_S2MM_SM : entity axi_dma_v7_1_10.axi_dma_s2mm_sm
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_stop => s2mm_stop_i ,
-- Channel 1 Control and Status
s2mm_run_stop => s2mm_run_stop ,
s2mm_keyhole => s2mm_keyhole ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_desc_flush => s2mm_desc_flush_i ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Status Stream RX Length
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
desc_available => desc_available ,
-- DataMover Command
s2mm_cmnd_wr => s2mm_cmnd_wr_1 ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
-- Descriptor Fields
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_blength => s2mm_desc_blength,
s2mm_desc_blength_v => s2mm_desc_blength_v,
s2mm_desc_blength_s => s2mm_desc_blength_s
);
---------------------------------------------------------------------------
-- S2MM Scatter Gather State Machine
---------------------------------------------------------------------------
I_S2MM_SG_IF : entity axi_dma_v7_1_10.axi_dma_s2mm_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_NUM_S2MM_CHANNELS => C_NUM_S2MM_CHANNELS ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
s2mm_desc_info_in => s2mm_desc_info_in ,
-- SG S2MM Descriptor Fetch AXI Stream In
m_axis_s2mm_ftch_tdata => m_axis_s2mm_ftch_tdata ,
m_axis_s2mm_ftch_tvalid => m_axis_s2mm_ftch_tvalid ,
m_axis_s2mm_ftch_tready => m_axis_s2mm_ftch_tready ,
m_axis_s2mm_ftch_tlast => m_axis_s2mm_ftch_tlast ,
m_axis_s2mm_ftch_tdata_new => m_axis_s2mm_ftch_tdata_new ,
m_axis_s2mm_ftch_tdata_mcdma_new => m_axis_s2mm_ftch_tdata_mcdma_new ,
m_axis_s2mm_ftch_tdata_mcdma_nxt => m_axis_s2mm_ftch_tdata_mcdma_nxt ,
m_axis_s2mm_ftch_tvalid_new => m_axis_s2mm_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available ,
-- SG S2MM Descriptor Update AXI Stream Out
s_axis_s2mm_updtptr_tdata => s_axis_s2mm_updtptr_tdata ,
s_axis_s2mm_updtptr_tvalid => s_axis_s2mm_updtptr_tvalid ,
s_axis_s2mm_updtptr_tready => s_axis_s2mm_updtptr_tready ,
s_axis_s2mm_updtptr_tlast => s_axis_s2mm_updtptr_tlast ,
s_axis_s2mm_updtsts_tdata => s_axis_s2mm_updtsts_tdata ,
s_axis_s2mm_updtsts_tvalid => s_axis_s2mm_updtsts_tvalid ,
s_axis_s2mm_updtsts_tready => s_axis_s2mm_updtsts_tready ,
s_axis_s2mm_updtsts_tlast => s_axis_s2mm_updtsts_tlast ,
-- S2MM Descriptor Fetch Request (from s2mm_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
-- S2MM Status Stream Interface
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data (
((1+C_ENABLE_MULTI_CHANNEL)*
C_M_AXI_S2MM_ADDR_WIDTH+
CMD_BASE_WIDTH)-1 downto 0) ,
-- S2MM Descriptor Update Request (from s2mm_sm)
desc_update_done => desc_update_done ,
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
s2mm_done => s2mm_done ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag ,
s2mm_brcvd => s2mm_brcvd ,
s2mm_eof_set => s2mm_eof_set ,
s2mm_packet_eof => s2mm_packet_eof ,
s2mm_halt => s2mm_halt ,
s2mm_eof_micro => s2mm_eof_micro,
s2mm_sof_micro => s2mm_sof_micro,
-- S2MM Descriptor Field Output
s2mm_new_curdesc => s2mm_new_curdesc ,
s2mm_new_curdesc_wren => s2mm_new_curdesc_wren ,
s2mm_desc_baddress => s2mm_desc_baddress ,
s2mm_desc_blength => s2mm_desc_blength ,
s2mm_desc_blength_v => s2mm_desc_blength_v ,
s2mm_desc_blength_s => s2mm_desc_blength_s ,
s2mm_desc_info => s2mm_desc_info ,
s2mm_desc_app0 => s2mm_desc_app0 ,
s2mm_desc_app1 => s2mm_desc_app1 ,
s2mm_desc_app2 => s2mm_desc_app2 ,
s2mm_desc_app3 => s2mm_desc_app3 ,
s2mm_desc_app4 => s2mm_desc_app4
);
end generate GEN_SCATTER_GATHER_MODE;
s2mm_packet_eof_out <= s2mm_packet_eof;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
s2mm_desc_flush <= '0';
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others => '0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others => '0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
desc_fetch_req <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
desc_update_done <= '0';
s2mm_rxlength_clr <= '0';
stsstrm_fifo_rden <= '0';
s2mm_new_curdesc <= (others => '0');
s2mm_new_curdesc_wren <= '0';
s2mm_desc_baddress <= (others => '0');
s2mm_desc_info <= (others => '0');
s2mm_desc_blength <= (others => '0');
s2mm_desc_blength_v <= (others => '0');
s2mm_desc_blength_s <= (others => '0');
s2mm_desc_cmplt <= '0';
s2mm_desc_app0 <= (others => '0');
s2mm_desc_app1 <= (others => '0');
s2mm_desc_app2 <= (others => '0');
s2mm_desc_app3 <= (others => '0');
s2mm_desc_app4 <= (others => '0');
-- Simple DMA State Machine
I_S2MM_SMPL_SM : entity axi_dma_v7_1_10.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_MICRO_DMA => C_MICRO_DMA ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => s2mm_run_stop ,
keyhole => s2mm_keyhole ,
stop => s2mm_stop_i ,
cmnd_idle => s2mm_cmnd_idle ,
sts_idle => s2mm_sts_idle ,
-- DataMover Status
sts_received => s2mm_sts_received ,
sts_received_clr => s2mm_sts_received_clr ,
-- DataMover Command
cmnd_wr => s2mm_cmnd_wr ,
cmnd_data => s2mm_cmnd_data ,
cmnd_pending => s2mm_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => s2mm_length_wren ,
xfer_address => s2mm_da ,
xfer_length => s2mm_length
);
-- Pass Done/Error Status out to DMASR
s2mm_interr_set <= s2mm_interr;
s2mm_slverr_set <= s2mm_slverr;
s2mm_decerr_set <= s2mm_decerr;
s2mm_bytes_rcvd <= s2mm_brcvd;
s2mm_bytes_rcvd_wren <= s2mm_done;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
s2mm_smple_done <= s2mm_sts_received_clr when s2mm_stop_i = '0'
-- Else halt set prior to halted being set
else s2mm_halted_set_i when s2mm_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- S2MM DataMover Command / Status Interface
-------------------------------------------------------------------------------
I_S2MM_CMDSTS : entity axi_dma_v7_1_10.axi_dma_s2mm_cmdsts_if
generic map(
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH ,
C_DM_STATUS_WIDTH => C_DM_STATUS_WIDTH ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_INCLUDE_SG => C_INCLUDE_SG ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA ,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Update command write interface from s2mm sm
s2mm_cmnd_wr => s2mm_cmnd_wr ,
s2mm_cmnd_data => s2mm_cmnd_data ,
s2mm_cmnd_pending => s2mm_cmnd_pending ,
s2mm_packet_eof => s2mm_packet_eof , -- EOF Detected
s2mm_sts_received_clr => s2mm_sts_received_clr ,
s2mm_sts_received => s2mm_sts_received ,
s2mm_tailpntr_enble => s2mm_tailpntr_enble ,
s2mm_desc_cmplt => s2mm_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_s2mm_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_s2mm_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_s2mm_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_s2mm_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_s2mm_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_s2mm_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_s2mm_sts_tkeep ,
-- S2MM Primary DataMover Status
s2mm_brcvd => s2mm_brcvd ,
s2mm_err => s2mm_err ,
s2mm_done => s2mm_done ,
s2mm_error => dma_s2mm_error ,
s2mm_interr => s2mm_interr ,
s2mm_slverr => s2mm_slverr ,
s2mm_decerr => s2mm_decerr ,
s2mm_tag => s2mm_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_S2MM_STS_MNGR : entity axi_dma_v7_1_10.axi_dma_s2mm_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
s2mm_run_stop => s2mm_run_stop ,
s2mm_ftch_idle => s2mm_ftch_idle ,
s2mm_updt_idle => s2mm_updt_idle ,
s2mm_cmnd_idle => s2mm_cmnd_idle ,
s2mm_sts_idle => s2mm_sts_idle ,
-- stop and halt control/status
s2mm_stop => s2mm_stop_i ,
s2mm_halt_cmplt => s2mm_halt_cmplt ,
-- system state and control
s2mm_all_idle => s2mm_all_idle ,
s2mm_halted_clr => s2mm_halted_clr ,
s2mm_halted_set => s2mm_halted_set_i ,
s2mm_idle_set => s2mm_idle_set ,
s2mm_idle_clr => s2mm_idle_clr
);
-- S2MM Status Stream Included
GEN_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Status Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to sts strm
-- skid buffer.
sts_strm_stop <= s2mm_error_i -- Error
or soft_reset_re; -- Soft Reset issued
I_S2MM_STS_STREAM : entity axi_dma_v7_1_10.axi_dma_s2mm_sts_strm
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_S_AXIS_S2MM_STS_TDATA_WIDTH=> C_S_AXIS_S2MM_STS_TDATA_WIDTH ,
C_SG_USE_STSAPP_LENGTH => C_SG_USE_STSAPP_LENGTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
axi_prmry_aclk => axi_prmry_aclk ,
p_reset_n => p_reset_n ,
s2mm_stop => sts_strm_stop ,
s2mm_rxlength_valid => s2mm_rxlength_valid ,
s2mm_rxlength_clr => s2mm_rxlength_clr ,
s2mm_rxlength => s2mm_rxlength ,
stsstrm_fifo_rden => stsstrm_fifo_rden ,
stsstrm_fifo_empty => stsstrm_fifo_empty ,
stsstrm_fifo_dout => stsstrm_fifo_dout ,
-- Stream to Memory Map Status Stream Interface ,
s_axis_s2mm_sts_tdata => s_axis_s2mm_sts_tdata ,
s_axis_s2mm_sts_tkeep => s_axis_s2mm_sts_tkeep ,
s_axis_s2mm_sts_tvalid => s_axis_s2mm_sts_tvalid ,
s_axis_s2mm_sts_tready => s_axis_s2mm_sts_tready ,
s_axis_s2mm_sts_tlast => s_axis_s2mm_sts_tlast
);
end generate GEN_STS_STREAM;
-- S2MM Status Stream Not Included
GEN_NO_STS_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
s2mm_rxlength_valid <= '0';
s2mm_rxlength <= (others => '0');
stsstrm_fifo_empty <= '1';
stsstrm_fifo_dout <= (others => '0');
s_axis_s2mm_sts_tready <= '0';
end generate GEN_NO_STS_STREAM;
end generate GEN_S2MM_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Do Not Include S2MM Channel
-------------------------------------------------------------------------------
GEN_NO_S2MM_DMA_CONTROL : if C_INCLUDE_S2MM = 0 generate
begin
m_axis_s2mm_ftch_tready <= '0';
s_axis_s2mm_updtptr_tdata <= (others =>'0');
s_axis_s2mm_updtptr_tvalid <= '0';
s_axis_s2mm_updtptr_tlast <= '0';
s_axis_s2mm_updtsts_tdata <= (others =>'0');
s_axis_s2mm_updtsts_tvalid <= '0';
s_axis_s2mm_updtsts_tlast <= '0';
s2mm_new_curdesc <= (others =>'0');
s2mm_new_curdesc_wren <= '0';
s_axis_s2mm_cmd_tvalid <= '0';
s_axis_s2mm_cmd_tdata <= (others =>'0');
m_axis_s2mm_sts_tready <= '0';
s2mm_halted_clr <= '0';
s2mm_halted_set <= '0';
s2mm_idle_set <= '0';
s2mm_idle_clr <= '0';
s_axis_s2mm_sts_tready <= '0';
s2mm_stop <= '0';
s2mm_desc_flush <= '0';
s2mm_all_idle <= '1';
s2mm_error <= '0'; -- CR#570587
s2mm_packet_eof_out <= '0';
s2mm_smple_done <= '0';
s2mm_interr_set <= '0';
s2mm_slverr_set <= '0';
s2mm_decerr_set <= '0';
s2mm_bytes_rcvd <= (others => '0');
s2mm_bytes_rcvd_wren <= '0';
end generate GEN_NO_S2MM_DMA_CONTROL;
end implementation;
| mit | 14bea59758c9d6d873d0d70a3d0c0206 | 0.398687 | 4.340152 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/otp_clocked.vhd | 1 | 2,191 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
use std.textio.all;
library commonlib;
use commonlib.types_common.all;
entity otp_clocked is
port (
clk : in std_ulogic;
we : in std_ulogic;
re : in std_ulogic;
address : in std_logic_vector(11 downto 0);
wdata : in std_logic_vector(15 downto 0);
rdata : out std_logic_vector(15 downto 0)
);
end;
architecture arch_otp_clocked of otp_clocked is
constant SRAM_LENGTH : integer := 2**12;
constant FILE_IMAGE_LINES_TOTAL : integer := SRAM_LENGTH;
type ram_type is array (0 to SRAM_LENGTH-1) of std_logic_vector(15 downto 0);
impure function init_ram(file_name : in string) return ram_type is
file ram_file : text open read_mode is file_name;
variable ram_line : line;
variable temp_bv : std_logic_vector(15 downto 0);
variable temp_mem : ram_type;
begin
for i in 0 to (FILE_IMAGE_LINES_TOTAL-1) loop
readline(ram_file, ram_line);
hread(ram_line, temp_bv);
temp_mem(i) := temp_bv;
end loop;
return temp_mem;
end function;
--! @warning SIMULATION INITIALIZATION
signal ram : ram_type;-- := init_ram(init_file);
begin
reg : process (clk, address, we, re, wdata, ram) begin
if rising_edge(clk) then
if we = '1' then
ram(conv_integer(address)) <= wdata;
end if;
end if;
if wdata = X"FFFF" and re = '1' then
rdata <= ram(conv_integer(address));
else
rdata <= X"CCCC";
end if;
end process;
end;
| apache-2.0 | 57473b45f84a9bae29e56666c7e7e9eb | 0.666362 | 3.455836 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine_old/PROFIBUS_MONITOR/CTRL_RS232_TX_VHDL.vhd | 4 | 9,084 | -- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 24.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic); --1: Initialzustand annehmen
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
--signal not_CLK : std_logic; --negierte Taktvariable
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
--Konstanten, lang 9600 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
--constant CNT01 : std_logic_vector := x"1458"; --16 Bit
--constant CNT02 : std_logic_vector := x"2C98"; --usw.
--constant CNT03 : std_logic_vector := x"3D08";
--constant CNT04 : std_logic_vector := x"5160";
--constant CNT05 : std_logic_vector := x"65B8";
--constant CNT06 : std_logic_vector := x"7A10";
--constant CNT07 : std_logic_vector := x"8E68";
--constant CNT08 : std_logic_vector := x"A2C0";
--constant CNT09 : std_logic_vector := x"B718";
--constant CNT10 : std_logic_vector := x"CB70";
--Konstanten, lang 19200 Baud, 1 Startbit, 8 Datenbit, 1 Stoppbit, keine Parität
constant CNT01 : std_logic_vector := x"0A2C"; --16 Bit
constant CNT02 : std_logic_vector := x"1458"; --usw.
constant CNT03 : std_logic_vector := x"1E84";
constant CNT04 : std_logic_vector := x"28B0";
constant CNT05 : std_logic_vector := x"32DC";
constant CNT06 : std_logic_vector := x"3D09";
constant CNT07 : std_logic_vector := x"4735";
constant CNT08 : std_logic_vector := x"5161";
constant CNT09 : std_logic_vector := x"5B8D";
constant CNT10 : std_logic_vector := x"65B9";
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND, SEND_BYTE) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
end Behavioral;
| gpl-2.0 | dcb73eed821e7eececfc8bc196b54f06 | 0.545354 | 3.149792 | false | false | false | false |
szanni/aeshw | aes-core/cipher_tb.vhd | 1 | 718 | library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity cipher_tb is
end cipher_tb;
architecture behavior of cipher_tb is
component cipher
port (
din : in state;
dout : out state
);
end component;
--Inputs
signal din : state;
--Outputs
signal dout : state;
begin
uut: cipher port map (
din => din,
dout => dout
);
stim_proc: process
begin
--din <= x"d42711aee0bf98f1b8b45de51e415230";
din <= x"d4bf5d30e0b452aeb84111f11e2798e5";
wait for 10 ns;
--assert dout = x"d4bf5d30e0b452aeb84111f11e2798e5" report "cipher: lookup failure" severity failure;
assert dout = x"046681e5e0cb199a48f8d37a2806264c" report "cipher: mix failure" severity failure;
wait;
end process;
end;
| bsd-2-clause | 677dc2af561f74174cc7ecd9e718948f | 0.724234 | 2.592058 | false | false | false | false |
AlessandroSpallina/CalcolatoriElettronici | VHDL/09-12-14/09-12-14_TEST.vhd | 2 | 1,207 | -- Copyright (C) 2016 by Spallina Ind.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity TESTANTONELLA is
end entity;
architecture beh of TESTANTONELLA is
component antonella is
port (
op : in std_logic_vector(1 downto 0);
din : in std_logic_vector(15 downto 0);
start, clk : in std_logic;
res : out std_logic_vector(15 downto 0);
fine : out std_logic
);
end component;
signal op : std_logic_vector(1 downto 0);
signal din, res : std_logic_vector(15 downto 0);
signal start, clk, fine : std_logic;
begin
DUT: antonella port map (op, din, start, clk, res, fine);
process
begin
clk <= '0';
wait for 5 ns;
clk <= '1';
wait for 5 ns;
end process;
start <= '1' after 1 ns, '0' after 11 ns,
'1' after 46 ns, '0' after 56 ns,
'1' after 86 ns, '0' after 96 ns,
'1' after 131 ns, '0' after 141 ns;
op <= "00" after 11 ns, -- OP "00" aka LD->R0
"01" after 56 ns, -- OP "01" aka LD->R1
"10" after 96 ns, -- OP "10" aka AND
"11" after 131 ns; -- OP "11" aka ADD
din <= conv_std_logic_vector(5, 16) after 11 ns,
conv_std_logic_vector(6, 16) after 56 ns;
end beh; | mit | 614737e1153ee40000fc328dfa77241c | 0.623032 | 2.652747 | false | false | false | false |
szanni/aeshw | aes-core/cipher_cu.vhd | 1 | 2,709 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:06:05 07/16/2014
-- Design Name:
-- Module Name: cipher_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cipher_cu is
port(
clk : in std_logic;
reset : in std_logic;
x_start : in std_logic; -- start encryption
x_comp : in std_logic; -- '1' if last round is reached
y_1_2 : out std_logic_vector(1 downto 0); -- controlling values for cipher
y_3_4 : out std_logic_vector(1 downto 0); -- controlling values for counter
y_end : out std_logic -- encryption finished
);
end cipher_cu;
architecture Behavioral of cipher_cu is
type States is (S0, S1, S2, S3, S4, S5);
signal S, S_next : States;
begin
delta : process (S, x_start, x_comp)
begin
case S is
when S0 => y_1_2 <="--";
y_3_4 <="00"; -- initialize counter
y_end <= '0';
if x_start = '1' then
S_next <= S1;
else
S_next <= S0;
end if;
when S1 => y_1_2 <= "--"; -- round key 0 not yet available (due to synchonous read)
y_3_4 <= "01"; -- increment counter
y_end <= '0';
S_next <= S2;
when S2 => y_1_2 <= "00"; -- load in plaintext (round key 0 now available)
y_3_4 <= "01"; -- increment counter
y_end <= '0';
S_next <= S3;
when S3 => y_1_2 <= "01"; -- include mix columns stage
y_3_4 <= "01";
y_end <= '0';
if x_comp = '1' then
S_next <= S4; -- last round starts after the next cycle
else
S_next <= S3;
end if;
when S4 => y_1_2 <= "10"; -- leave out mix columns stage
y_3_4 <= "--";
y_end <= '0';
S_next <= S5;
when S5 => y_1_2 <= "--";
y_3_4 <= "--";
y_end <= '1'; -- finished (output valid for one cycle)
S_next <= S0;
end case;
end process delta;
feedback_loop : process (clk, reset, S_next)
begin
if reset = '1' then
S <= S0;
elsif rising_edge(clk) then
S <= S_next;
end if;
end process feedback_loop;
end Behavioral;
| bsd-2-clause | 2f89e896fa0f6baabfbc1c44abd6db91 | 0.525655 | 3.259928 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/axi4_irqctrl.vhd | 1 | 8,248 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
library misclib;
use misclib.types_misc.all;
entity axi4_irqctrl is
generic (
async_reset : boolean := false;
xaddr : integer := 0;
xmask : integer := 16#fffff#
);
port
(
clk : in std_logic;
nrst : in std_logic;
i_irqs : in std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
o_cfg : out axi4_slave_config_type;
i_axi : in axi4_slave_in_type;
o_axi : out axi4_slave_out_type;
o_irq_meip : out std_logic
);
end;
architecture axi4_irqctrl_rtl of axi4_irqctrl is
constant xconfig : axi4_slave_config_type := (
descrtype => PNP_CFG_TYPE_SLAVE,
descrsize => PNP_CFG_SLAVE_DESCR_BYTES,
irq_idx => conv_std_logic_vector(0, 8),
xaddr => conv_std_logic_vector(xaddr, CFG_SYSBUS_CFG_ADDR_BITS),
xmask => conv_std_logic_vector(xmask, CFG_SYSBUS_CFG_ADDR_BITS),
vid => VENDOR_GNSSSENSOR,
did => GNSSSENSOR_IRQCTRL
);
constant IRQ_ZERO : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1) := (others => '0');
type registers is record
--! interrupt signal delay signal to detect interrupt positive edge
irqs_z : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
irqs_zz : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
--! mask irq disabled: 1=disabled; 0=enabled
irqs_mask : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
--! irq pending bit mask
irqs_pending : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
--! interrupt handler address initialized by FW:
isr_table : std_logic_vector(63 downto 0);
--! hold-on generation of interrupt.
irq_lock : std_logic;
--! delayed interrupt
irq_wait_unlock : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
irq_cause_idx : std_logic_vector(31 downto 0);
--! Function trap_entry copies the values of CSRs into these two regs:
dbg_cause : std_logic_vector(63 downto 0);
dbg_epc : std_logic_vector(63 downto 0);
raddr : global_addr_array_type;
end record;
constant R_RESET : registers := (
(others => '0'), (others => '0'), -- irqs_z, irqs_zz
(others => '1'), (others => '0'), -- irqs_mask, irqs_pending
(others => '0'), '0', -- isr_table, isr_lock
(others => '0'), (others => '0'), -- irq_wait_unlock, irq_cause_idx
(others => '0'), (others => '0'), -- dbg_cause, dbg_epc
((others => '0'), (others => '0'))
);
signal r, rin: registers;
signal wb_dev_rdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
signal wb_bus_raddr : global_addr_array_type;
signal w_bus_re : std_logic;
signal wb_bus_waddr : global_addr_array_type;
signal w_bus_we : std_logic;
signal wb_bus_wstrb : std_logic_vector(CFG_SYSBUS_DATA_BYTES-1 downto 0);
signal wb_bus_wdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
begin
axi0 : axi4_slave generic map (
async_reset => async_reset
) port map (
i_clk => clk,
i_nrst => nrst,
i_xcfg => xconfig,
i_xslvi => i_axi,
o_xslvo => o_axi,
i_ready => '1',
i_rdata => wb_dev_rdata,
o_re => w_bus_re,
o_r32 => open,
o_radr => wb_bus_raddr,
o_wadr => wb_bus_waddr,
o_we => w_bus_we,
o_wstrb => wb_bus_wstrb,
o_wdata => wb_bus_wdata
);
comblogic : process(nrst, i_irqs, r, w_bus_re, wb_bus_raddr, wb_bus_waddr,
w_bus_we, wb_bus_wstrb, wb_bus_wdata)
variable v : registers;
variable raddr : integer;
variable waddr : integer;
variable vrdata : std_logic_vector(CFG_SYSBUS_DATA_BITS-1 downto 0);
variable tmp : std_logic_vector(31 downto 0);
variable wstrb : std_logic_vector(CFG_ALIGN_BYTES-1 downto 0);
variable w_generate_ipi : std_logic;
begin
v := r;
v.raddr := wb_bus_raddr;
w_generate_ipi := '0';
vrdata := (others => '0');
for n in 0 to CFG_WORDS_ON_BUS-1 loop
raddr := conv_integer(r.raddr(n)(11 downto 2));
tmp := (others => '0');
case raddr is
when 0 => tmp(CFG_IRQ_TOTAL-1 downto 1) := r.irqs_mask; --! [RW]: 1=irq disable; 0=enable
when 1 => tmp(CFG_IRQ_TOTAL-1 downto 1) := r.irqs_pending; --! [RO]: Rised interrupts.
when 2 => tmp := (others => '0'); --! [WO]: Clear interrupts mask.
when 3 => tmp := (others => '0'); --! [WO]: Rise interrupts mask.
when 4 => tmp := r.isr_table(31 downto 0); --! [RW]: LSB of the function address
when 5 => tmp := r.isr_table(63 downto 32); --! [RW]: MSB of the function address
when 6 => tmp := r.dbg_cause(31 downto 0); --! [RW]: Cause of the interrupt
when 7 => tmp := r.dbg_cause(63 downto 32); --! [RW]:
when 8 => tmp := r.dbg_epc(31 downto 0); --! [RW]: Instruction pointer
when 9 => tmp := r.dbg_epc(63 downto 32); --! [RW]:
when 10 => tmp(0) := r.irq_lock;
when 11 => tmp := r.irq_cause_idx;
when others =>
end case;
vrdata(8*CFG_ALIGN_BYTES*(n+1)-1 downto 8*CFG_ALIGN_BYTES*n) := tmp;
end loop;
if w_bus_we = '1' then
for n in 0 to CFG_WORDS_ON_BUS-1 loop
if conv_integer(wb_bus_wstrb(CFG_ALIGN_BYTES*(n+1)-1 downto CFG_ALIGN_BYTES*n)) /= 0 then
waddr := conv_integer(wb_bus_waddr(n)(11 downto 2));
tmp := wb_bus_wdata(32*(n+1)-1 downto 32*n);
case waddr is
when 0 => v.irqs_mask := tmp(CFG_IRQ_TOTAL-1 downto 1);
when 1 => --! Read only
when 2 =>
v.irqs_pending := r.irqs_pending and (not tmp(CFG_IRQ_TOTAL-1 downto 1));
when 3 =>
w_generate_ipi := '1';
v.irqs_pending := (not r.irqs_mask) and tmp(CFG_IRQ_TOTAL-1 downto 1);
when 4 => v.isr_table(31 downto 0) := tmp;
when 5 => v.isr_table(63 downto 32) := tmp;
when 6 => v.dbg_cause(31 downto 0) := tmp;
when 7 => v.dbg_cause(63 downto 32) := tmp;
when 8 => v.dbg_epc(31 downto 0) := tmp;
when 9 => v.dbg_epc(63 downto 32) := tmp;
when 10 => v.irq_lock := tmp(0);
when 11 => v.irq_cause_idx := tmp;
when others =>
end case;
end if;
end loop;
end if;
v.irqs_z := i_irqs;
v.irqs_zz := r.irqs_z;
for n in 1 to CFG_IRQ_TOTAL-1 loop
if (r.irqs_z(n) = '1' and r.irqs_zz(n) = '0') or r.irq_wait_unlock(n) = '1' then
if r.irq_lock = '0' then
v.irq_wait_unlock(n) := '0';
v.irqs_pending(n) := not r.irqs_mask(n);
w_generate_ipi := w_generate_ipi or (not r.irqs_mask(n));
else
v.irq_wait_unlock(n) := '1';
end if;
end if;
end loop;
if r.irqs_pending = IRQ_ZERO or r.irq_lock = '1' then
o_irq_meip <= '0';
else
o_irq_meip <= '1';
end if;
if not async_reset and nrst = '0' then
v := R_RESET;
end if;
rin <= v;
wb_dev_rdata <= vrdata;
end process;
o_cfg <= xconfig;
-- registers:
regs : process(clk, nrst)
begin
if async_reset and nrst = '0' then
r <= R_RESET;
elsif rising_edge(clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | 8ef8423c48cc5fa7daaeca2808aca17e | 0.561469 | 3.267829 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/work/riscv_soc.vhd | 1 | 24,812 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! AMBA system bus specific library
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
use ambalib.types_bus0.all;
--! Misc modules library
library misclib;
use misclib.types_misc.all;
--! Ethernet related declarations.
library ethlib;
use ethlib.types_eth.all;
--! gnss sub-system library
library gnsslib;
use gnsslib.types_gnss.all;
--! River CPU specific library
library riverlib;
--! River top level with AMBA interface module declaration
use riverlib.types_river.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! @brief SOC Top-level entity declaration.
--! @details This module implements full SOC functionality and all IO signals
--! are available on FPGA/ASIC IO pins.
entity riscv_soc is port
(
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic; -- GNSS ADC clock (4..40 MHz)
i_gps_I : in std_logic_vector(1 downto 0); -- Channel 0 sampled I value
i_gps_Q : in std_logic_vector(1 downto 0); -- Channel 0 sampled Q value
i_glo_I : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
i_glo_Q : in std_logic_vector(1 downto 0); -- Channel 1 sampled I value
o_pps : out std_logic; -- Pulse Per Second signal
i_gps_ld : in std_logic; -- Channel 0 RF front-end Lock detect
i_glo_ld : in std_logic; -- Channel 1 RF front-end Lock detect
o_max_sclk : out std_logic; -- RF synthesizer SPI clock
o_max_sdata : out std_logic; -- RF synthesizer SPI data
o_max_ncs : out std_logic_vector(1 downto 0); -- RF synthesizer channel 0/1 selector
i_antext_stat : in std_logic; -- Antenna powered status
i_antext_detect : in std_logic; -- Antenna connected status
o_antext_ena : out std_logic; -- Enabling/disabling antenna
o_antint_contr : out std_logic -- Antenna Internal/External selector
);
--! @}
end riscv_soc;
--! @brief SOC top-level architecture declaration.
architecture arch_riscv_soc of riscv_soc is
signal w_glob_rst : std_ulogic; -- Global reset active HIGH
signal w_glob_nrst : std_ulogic; -- Global reset active LOW
signal w_soft_rst : std_ulogic; -- Software reset (acitve HIGH) from DSU
signal w_bus_nrst : std_ulogic; -- Global reset and Soft Reset active LOW
signal uart1i : uart_in_type;
signal uart1o : uart_out_type;
signal uart2i : uart_in_type;
signal uart2o : uart_out_type;
signal spiflashi : spi_in_type;
signal spiflasho : spi_out_type;
--! Arbiter is switching only slaves output signal, data from noc
--! is connected to all slaves and to the arbiter itself.
signal aximi : bus0_xmst_in_vector;
signal aximo : bus0_xmst_out_vector;
signal axisi : bus0_xslv_in_vector;
signal axiso : bus0_xslv_out_vector;
signal slv_cfg : bus0_xslv_cfg_vector;
signal mst_cfg : bus0_xmst_cfg_vector;
signal wb_core_irq : std_logic_vector(CFG_TOTAL_CPU_MAX-1 downto 0);
signal w_ext_irq : std_logic;
signal dport_i : dport_in_vector;
signal dport_o : dport_out_vector;
signal dmi_dport_i : dport_in_vector;
signal dmi_dport_o : dport_out_vector;
signal dsu_dport_i : dport_in_vector;
signal dsu_dport_o : dport_out_vector;
signal wb_bus_util_w : std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
signal wb_bus_util_r : std_logic_vector(CFG_BUS0_XMST_TOTAL-1 downto 0);
signal w_dmi_jtag_req_valid : std_logic;
signal w_dmi_jtag_req_ready : std_logic;
signal w_dmi_jtag_write : std_logic;
signal wb_dmi_jtag_addr : std_logic_vector(6 downto 0);
signal wb_dmi_jtag_wdata : std_logic_vector(31 downto 0);
signal w_dmi_jtag_resp_valid : std_logic;
signal w_dmi_jtag_resp_ready : std_logic;
signal wb_dmi_jtag_rdata : std_logic_vector(31 downto 0);
signal w_dmi_dsu_req_valid : std_logic;
signal w_dmi_dsu_req_ready : std_logic;
signal w_dmi_dsu_write : std_logic;
signal wb_dmi_dsu_addr : std_logic_vector(6 downto 0);
signal wb_dmi_dsu_wdata : std_logic_vector(31 downto 0);
signal w_dmi_dsu_resp_valid : std_logic;
signal w_dmi_dsu_resp_ready : std_logic;
signal wb_dmi_dsu_rdata : std_logic_vector(31 downto 0);
signal wb_dmi_hartsel : std_logic_vector(CFG_LOG2_CPU_MAX-1 downto 0);
signal eth_i : eth_in_type;
signal eth_o : eth_out_type;
signal irq_pins : std_logic_vector(CFG_IRQ_TOTAL-1 downto 1);
signal w_otp_busy : std_logic;
signal wb_otp_cfg_rsetup : std_logic_vector(3 downto 0);
signal wb_otp_cfg_wadrsetup : std_logic_vector(3 downto 0);
signal wb_otp_cfg_wactive : std_logic_vector(31 downto 0);
signal wb_otp_cfg_whold : std_logic_vector(3 downto 0);
begin
------------------------------------
--! @brief System Reset device instance.
rst0 : reset_global port map (
inSysReset => i_rst,
inSysClk => i_clk,
outReset => w_glob_rst
);
w_glob_nrst <= not w_glob_rst;
w_bus_nrst <= not (w_glob_rst or w_soft_rst);
--! @brief AXI4 controller.
ctrl0 : axictrl_bus0 generic map (
async_reset => CFG_ASYNC_RESET
) port map (
i_clk => i_clk,
i_nrst => w_glob_nrst,
i_slvcfg => slv_cfg,
i_slvo => axiso,
i_msto => aximo,
o_slvi => axisi,
o_msti => aximi,
o_bus_util_w => wb_bus_util_w, -- Bus write access utilization per master statistic
o_bus_util_r => wb_bus_util_r -- Bus read access utilization per master statistic
);
wb_core_irq(CFG_TOTAL_CPU_MAX-1 downto 1) <= (others => '0');
wb_core_irq(0) <= w_ext_irq; -- TODO: other CPU interrupts
group0 : river_workgroup generic map (
cpunum => CFG_CPU_NUM,
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
fpu_ena => true,
coherence_ena => false,
tracer_ena => false
) port map (
i_nrst => w_bus_nrst,
i_clk => i_clk,
i_msti => aximi(CFG_BUS0_XMST_WORKGROUP),
o_msto => aximo(CFG_BUS0_XMST_WORKGROUP),
o_mstcfg => mst_cfg(CFG_BUS0_XMST_WORKGROUP),
i_dport => dport_i,
o_dport => dport_o,
i_ext_irq => wb_core_irq
);
-- Access to Debug port of the CPUs workgroup
dmregs0 : dmi_regs generic map (
async_reset => CFG_ASYNC_RESET,
cpu_available => CFG_CPU_NUM
) port map (
clk => i_clk,
nrst => w_glob_nrst,
-- port[0] connected to JTAG TAP has access to AXI master interface (SBA registers)
i_dmi_jtag_req_valid => w_dmi_jtag_req_valid,
o_dmi_jtag_req_ready => w_dmi_jtag_req_ready,
i_dmi_jtag_write => w_dmi_jtag_write,
i_dmi_jtag_addr => wb_dmi_jtag_addr,
i_dmi_jtag_wdata => wb_dmi_jtag_wdata,
o_dmi_jtag_resp_valid => w_dmi_jtag_resp_valid,
i_dmi_jtag_resp_ready => w_dmi_jtag_resp_ready,
o_dmi_jtag_rdata => wb_dmi_jtag_rdata,
-- port[1] connected to DSU doesn't have access to AXI master interface
i_dmi_dsu_req_valid => w_dmi_dsu_req_valid,
o_dmi_dsu_req_ready => w_dmi_dsu_req_ready,
i_dmi_dsu_write => w_dmi_dsu_write,
i_dmi_dsu_addr => wb_dmi_dsu_addr,
i_dmi_dsu_wdata => wb_dmi_dsu_wdata,
o_dmi_dsu_resp_valid => w_dmi_dsu_resp_valid,
i_dmi_dsu_resp_ready => w_dmi_dsu_resp_ready,
o_dmi_dsu_rdata => wb_dmi_dsu_rdata,
o_hartsel => wb_dmi_hartsel,
o_dmstat => open,
o_ndmreset => w_soft_rst,
o_cfg => mst_cfg(CFG_BUS0_XMST_DMI),
i_xmsti => aximi(CFG_BUS0_XMST_DMI),
o_xmsto => aximo(CFG_BUS0_XMST_DMI),
o_dporti => dmi_dport_i,
i_dporto => dmi_dport_o
);
-- Interconnect between DMI register and DSU debug interfaces
icdport0 : ic_dport_2s_1m generic map (
async_reset => CFG_ASYNC_RESET
) port map (
clk => i_clk,
nrst => w_glob_nrst,
i_sdport0i => dmi_dport_i,
o_sdport0o => dmi_dport_o,
i_sdport1i => dsu_dport_i,
o_sdport1o => dsu_dport_o,
o_mdporti => dport_i,
i_mdporto => dport_o
);
dsu_ena : if CFG_DSU_ENABLE generate
------------------------------------
--! @brief Debug Support Unit with access to the CSRs
--! @details Map address:
--! 0x80080000..0x8009ffff (128 KB total)
dsu0 : axi_dsu generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80080#,
xmask => 16#fffe0#
) port map (
clk => i_clk,
nrst => w_glob_nrst,
o_cfg => slv_cfg(CFG_BUS0_XSLV_DSU),
i_axi => axisi(CFG_BUS0_XSLV_DSU),
o_axi => axiso(CFG_BUS0_XSLV_DSU),
o_dporti => dsu_dport_i,
i_dporto => dsu_dport_o,
i_dmi_hartsel => wb_dmi_hartsel,
o_dmi_req_valid => w_dmi_dsu_req_valid,
i_dmi_req_ready => w_dmi_dsu_req_ready,
o_dmi_write => w_dmi_dsu_write,
o_dmi_addr => wb_dmi_dsu_addr,
o_dmi_wdata => wb_dmi_dsu_wdata,
i_dmi_resp_valid => w_dmi_dsu_resp_valid,
o_dmi_resp_ready => w_dmi_dsu_resp_ready,
i_dmi_rdata => wb_dmi_dsu_rdata,
-- Run time platform statistic signals (move to tracer):
i_bus_util_w => wb_bus_util_w, -- Write access bus utilization per master statistic
i_bus_util_r => wb_bus_util_r -- Read access bus utilization per master statistic
);
end generate;
dsu_dis : if not CFG_DSU_ENABLE generate
slv_cfg(CFG_BUS0_XSLV_DSU) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_DSU) <= axi4_slave_out_none;
dsu_dport_i <= (others => dport_in_none);
w_dmi_dsu_req_valid <= '0';
w_dmi_dsu_write <= '0';
wb_dmi_dsu_addr <= (others => '0');
wb_dmi_dsu_wdata <= (others => '0');
w_dmi_dsu_resp_ready <= '0';
end generate;
------------------------------------
-- JTAG TAP interface
jtag0 : tap_jtag port map (
nrst => w_glob_nrst,
clk => i_clk,
i_tck => i_jtag_tck,
i_ntrst => i_jtag_ntrst,
i_tms => i_jtag_tms,
i_tdi => i_jtag_tdi,
o_tdo => o_jtag_tdo,
o_jtag_vref => o_jtag_vref,
-- DMI interface
o_dmi_req_valid => w_dmi_jtag_req_valid,
i_dmi_req_ready => w_dmi_jtag_req_ready,
o_dmi_write => w_dmi_jtag_write,
o_dmi_addr => wb_dmi_jtag_addr,
o_dmi_wdata => wb_dmi_jtag_wdata,
i_dmi_resp_valid => w_dmi_jtag_resp_valid,
o_dmi_resp_ready => w_dmi_jtag_resp_ready,
i_dmi_rdata => wb_dmi_jtag_rdata
);
------------------------------------
--! @brief TAP via UART (debug port) with master interface.
uart2i.cts <= not i_uart2_ctsn;
uart2i.rd <= i_uart2_rd;
uart2 : uart_tap port map (
nrst => w_glob_nrst,
clk => i_clk,
i_uart => uart2i,
o_uart => uart2o,
i_msti => aximi(CFG_BUS0_XMST_MSTUART),
o_msto => aximo(CFG_BUS0_XMST_MSTUART),
o_mstcfg => mst_cfg(CFG_BUS0_XMST_MSTUART)
);
o_uart2_td <= uart2o.td;
o_uart2_rtsn <= not uart2o.rts;
------------------------------------
--! @brief BOOT ROM module instance with the AXI4 interface.
--! @details Map address:
--! 0x00000000..0x00007fff (32 KB total)
boot0 : axi4_rom generic map (
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00000#,
xmask => 16#ffff8#,
sim_hexfile => CFG_SIM_BOOTROM_HEX
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_BOOTROM),
i => axisi(CFG_BUS0_XSLV_BOOTROM),
o => axiso(CFG_BUS0_XSLV_BOOTROM)
);
------------------------------------
--! @brief OTP module instance with the AXI4 interface.
--! @details Map address:
--! 0x00010000..0x00011fff (8 KB total)
otp_ena : if CFG_OTP8KB_ENA generate
otp0 : axi4_otp generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00010#,
xmask => 16#ffffe#
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_OTP),
i_axi => axisi(CFG_BUS0_XSLV_OTP),
o_axi => axiso(CFG_BUS0_XSLV_OTP),
o_otp_we => o_otp_we,
o_otp_re => o_otp_re,
o_otp_addr => o_otp_a,
o_otp_wdata => o_otp_d,
i_otp_rdata => i_otp_d,
i_cfg_rsetup => wb_otp_cfg_rsetup,
i_cfg_wadrsetup => wb_otp_cfg_wadrsetup,
i_cfg_wactive => wb_otp_cfg_wactive,
i_cfg_whold => wb_otp_cfg_whold,
o_busy => w_otp_busy
);
end generate;
otp_dis : if not CFG_OTP8KB_ENA generate
slv_cfg(CFG_BUS0_XSLV_OTP) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_OTP) <= axi4_slave_out_none;
o_otp_d <= X"0000";
o_otp_a <= X"000";
o_otp_we <= '0';
o_otp_re <= '0';
w_otp_busy <= '0';
end generate;
------------------------------------
--! @brief Firmware Image ROM with the AXI4 interface.
--! @details Map address:
--! 0x00100000..0x0013ffff (256 KB total)
--! @warning Don't forget to change ROM_ADDR_WIDTH in rom implementation
img0 : axi4_rom generic map (
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00100#,
xmask => 16#fffc0#,
sim_hexfile => CFG_SIM_FWIMAGE_HEX
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_ROMIMAGE),
i => axisi(CFG_BUS0_XSLV_ROMIMAGE),
o => axiso(CFG_BUS0_XSLV_ROMIMAGE)
);
------------------------------------
--! @brief SPI FLASH module isntance with the AXI4 interface.
--! @details Map address:
--! 0x00200000..0x0023ffff (256 KB total)
spiflashi.SDI <= i_flash_si;
flash_ena : if CFG_EXT_FLASH_ENA generate
flash0 : axi4_flashspi generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#00200#,
xmask => 16#fffc0#,
wait_while_write => true
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_EXTFLASH),
i_spi => spiflashi,
o_spi => spiflasho,
i_axi => axisi(CFG_BUS0_XSLV_EXTFLASH),
o_axi => axiso(CFG_BUS0_XSLV_EXTFLASH)
);
end generate;
flash_dis : if not CFG_EXT_FLASH_ENA generate
slv_cfg(CFG_BUS0_XSLV_EXTFLASH) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_EXTFLASH) <= axi4_slave_out_none;
spiflasho <= spi_out_none;
end generate;
o_flash_so <= spiflasho.SDO;
o_flash_sck <= spiflasho.SCK;
o_flash_csn <= spiflasho.nCS;
o_flash_wpn <= spiflasho.nWP;
o_flash_holdn <= spiflasho.nHOLD;
o_flash_reset <= spiflasho.RESET;
------------------------------------
--! Internal SRAM module instance with the AXI4 interface.
--! @details Map address:
--! 0x10000000..0x1007ffff (512 KB total)
sram0 : axi4_sram generic map (
memtech => CFG_MEMTECH,
async_reset => CFG_ASYNC_RESET,
xaddr => 16#10000#,
xmask => 16#fff80#, -- 512 KB mask
abits => (10 + log2(512)), -- 512 KB address
init_file => CFG_SIM_FWIMAGE_HEX -- Used only for inferred
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_SRAM),
i => axisi(CFG_BUS0_XSLV_SRAM),
o => axiso(CFG_BUS0_XSLV_SRAM)
);
------------------------------------
--! @brief Controller of the LEDs, DIPs and GPIO with the AXI4 interface.
--! @details Map address:
--! 0x80000000..0x80000fff (4 KB total)
gpio0 : axi4_gpio generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80000#,
xmask => 16#fffff#,
xirq => 0,
width => 12
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_GPIO),
i => axisi(CFG_BUS0_XSLV_GPIO),
o => axiso(CFG_BUS0_XSLV_GPIO),
i_gpio => i_gpio,
o_gpio => o_gpio,
o_gpio_dir => o_gpio_dir
);
------------------------------------
uart1i.cts <= not i_uart1_ctsn;
uart1i.rd <= i_uart1_rd;
--! @brief UART Controller with the AXI4 interface.
--! @details Map address:
--! 0x80001000..0x80001fff (4 KB total)
uart1 : axi4_uart generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80001#,
xmask => 16#FFFFF#,
xirq => CFG_IRQ_UART1,
fifosz => 16
) port map (
nrst => w_glob_nrst,
clk => i_clk,
cfg => slv_cfg(CFG_BUS0_XSLV_UART1),
i_uart => uart1i,
o_uart => uart1o,
i_axi => axisi(CFG_BUS0_XSLV_UART1),
o_axi => axiso(CFG_BUS0_XSLV_UART1),
o_irq => irq_pins(CFG_IRQ_UART1)
);
o_uart1_td <= uart1o.td;
o_uart1_rtsn <= not uart1o.rts;
------------------------------------
--! @brief Interrupt controller with the AXI4 interface.
--! @details Map address:
--! 0x80002000..0x80002fff (4 KB total)
irq0 : axi4_irqctrl generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80002#,
xmask => 16#FFFFF#
) port map (
clk => i_clk,
nrst => w_bus_nrst,
i_irqs => irq_pins,
o_cfg => slv_cfg(CFG_BUS0_XSLV_IRQCTRL),
i_axi => axisi(CFG_BUS0_XSLV_IRQCTRL),
o_axi => axiso(CFG_BUS0_XSLV_IRQCTRL),
o_irq_meip => w_ext_irq
);
--! @brief Timers with the AXI4 interface.
--! @details Map address:
--! 0x80005000..0x80005fff (4 KB total)
gptmr0 : axi4_gptimers generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#80005#,
xmask => 16#fffff#,
xirq => CFG_IRQ_GPTIMERS,
tmr_total => 2
) port map (
clk => i_clk,
nrst => w_glob_nrst,
cfg => slv_cfg(CFG_BUS0_XSLV_GPTIMERS),
i_axi => axisi(CFG_BUS0_XSLV_GPTIMERS),
o_axi => axiso(CFG_BUS0_XSLV_GPTIMERS),
o_pwm => o_pwm,
o_irq => irq_pins(CFG_IRQ_GPTIMERS)
);
--! @brief GNSS Sub-System with the AXI4 interface.
--! @details Map address:
--! 0x80008000..0x8000ffff (32 KB total)
--!
--! 0x80008000..0x80008fff (4 KB total) RF Controller
--! 0x80009000..0x80009fff (4 KB total) Engine
--! 0x8000a000..0x8000afff (4 KB total) GPS FSE
gnss_ena : if CFG_GNSS_SS_ENA generate
gnss0 : gnss_ss generic map (
async_reset => CFG_ASYNC_RESET,
tech => CFG_MEMTECH,
xaddr => 16#80008#,
xmask => 16#FFFF8#,
xirq => CFG_IRQ_GNSSENGINE
) port map (
i_nrst => w_glob_nrst,
i_clk_bus => i_clk,
i_clk_adc => i_clk_adc,
i_gps_I => i_gps_I,
i_gps_Q => i_gps_Q,
i_glo_I => i_glo_I,
i_glo_Q => i_glo_Q,
o_pps => o_pps,
i_gps_ld => i_gps_ld,
i_glo_ld => i_glo_ld,
o_max_sclk => o_max_sclk,
o_max_sdata => o_max_sdata,
o_max_ncs => o_max_ncs,
i_antext_stat => i_antext_stat,
i_antext_detect => i_antext_detect,
o_antext_ena => o_antext_ena,
o_antint_contr => o_antint_contr,
o_cfg => slv_cfg(CFG_BUS0_XSLV_GNSS_SS),
i_axi => axisi(CFG_BUS0_XSLV_GNSS_SS),
o_axi => axiso(CFG_BUS0_XSLV_GNSS_SS),
o_irq => irq_pins(CFG_IRQ_GNSSENGINE)
);
end generate;
gnss_dis : if not CFG_GNSS_SS_ENA generate
axiso(CFG_BUS0_XSLV_GNSS_SS) <= axi4_slave_out_none;
slv_cfg(CFG_BUS0_XSLV_GNSS_SS) <= axi4_slave_config_none;
irq_pins(CFG_IRQ_GNSSENGINE) <= '0';
end generate;
--! @brief Ethernet MAC with the AXI4 interface.
--! @details Map address:
--! 0x80040000..0x8007ffff (256 KB total)
--! EDCL IP: 192.168.1.51 = C0.A8.01.33
eth0_ena : if CFG_ETHERNET_ENABLE generate
eth_i.tx_clk <= i_etx_clk;
eth_i.rx_clk <= i_erx_clk;
eth_i.rxd <= i_erxd;
eth_i.rx_dv <= i_erx_dv;
eth_i.rx_er <= i_erx_er;
eth_i.rx_col <= i_erx_col;
eth_i.rx_crs <= i_erx_crs;
eth_i.mdint <= i_emdint;
eth_i.mdio_i <= i_eth_mdio;
eth_i.gtx_clk <= i_eth_gtx_clk;
mac0 : grethaxi generic map (
xaddr => 16#80040#,
xmask => 16#FFFC0#,
xirq => CFG_IRQ_ETHMAC,
memtech => CFG_MEMTECH,
mdcscaler => 60, --! System Bus clock in MHz
enable_mdio => 1,
fifosize => 16,
nsync => 1,
edcl => 1,
edclbufsz => 16,
macaddrh => 16#20789#,
macaddrl => 16#123#,
ipaddrh => 16#C0A8#,
ipaddrl => 16#0033#,
phyrstadr => 7,
enable_mdint => 1,
maxsize => 1518
) port map (
rst => w_glob_nrst,
clk => i_clk,
msti => aximi(CFG_BUS0_XMST_ETHMAC),
msto => aximo(CFG_BUS0_XMST_ETHMAC),
mstcfg => mst_cfg(CFG_BUS0_XMST_ETHMAC),
msto2 => open, -- EDCL separate access is disabled
mstcfg2 => open, -- EDCL separate access is disabled
slvi => axisi(CFG_BUS0_XSLV_ETHMAC),
slvo => axiso(CFG_BUS0_XSLV_ETHMAC),
slvcfg => slv_cfg(CFG_BUS0_XSLV_ETHMAC),
ethi => eth_i,
etho => eth_o,
irq => irq_pins(CFG_IRQ_ETHMAC)
);
end generate;
--! Ethernet disabled
eth0_dis : if not CFG_ETHERNET_ENABLE generate
slv_cfg(CFG_BUS0_XSLV_ETHMAC) <= axi4_slave_config_none;
axiso(CFG_BUS0_XSLV_ETHMAC) <= axi4_slave_out_none;
mst_cfg(CFG_BUS0_XMST_ETHMAC) <= axi4_master_config_none;
aximo(CFG_BUS0_XMST_ETHMAC) <= axi4_master_out_none;
irq_pins(CFG_IRQ_ETHMAC) <= '0';
eth_i.gtx_clk <= '0';
eth_o <= eth_out_none;
end generate;
o_etxd <= eth_o.txd;
o_etx_en <= eth_o.tx_en;
o_etx_er <= eth_o.tx_er;
o_emdc <= eth_o.mdc;
o_eth_mdio <= eth_o.mdio_o;
o_eth_mdio_oe <= eth_o.mdio_oe;
o_erstn <= w_glob_nrst;
--! @brief Plug'n'Play controller of the current configuration with the
--! AXI4 interface.
--! @details Map address:
--! 0xfffff000..0xffffffff (4 KB total)
pnp0 : axi4_pnp generic map (
async_reset => CFG_ASYNC_RESET,
xaddr => 16#fffff#,
xmask => 16#fffff#,
tech => CFG_MEMTECH,
hw_id => CFG_HW_ID
) port map (
sys_clk => i_clk,
adc_clk => '0',
nrst => w_glob_nrst,
mstcfg => mst_cfg,
slvcfg => slv_cfg,
cfg => slv_cfg(CFG_BUS0_XSLV_PNP),
i => axisi(CFG_BUS0_XSLV_PNP),
o => axiso(CFG_BUS0_XSLV_PNP),
-- OTP Timing control
i_otp_busy => w_otp_busy,
o_otp_cfg_rsetup => wb_otp_cfg_rsetup,
o_otp_cfg_wadrsetup => wb_otp_cfg_wadrsetup,
o_otp_cfg_wactive => wb_otp_cfg_wactive,
o_otp_cfg_whold => wb_otp_cfg_whold
);
end arch_riscv_soc;
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`protect end_protected
| bsd-2-clause | dba66e38f1e5f9fa4fb8932f1ef41dc0 | 0.9504 | 1.813279 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg.vhd | 1 | 84,412 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
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-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg.vhd
-- Description: This entity is the top level entity for the AXI Scatter Gather
-- Engine.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_pkg.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXI_SG_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream out for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_UPDT_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH1_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH1_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch
C_SG_CH2_WORDS_TO_UPDATE : integer range 1 to 16 := 8;
-- Number of words to update
C_SG_CH2_FIRST_UPDATE_WORD : integer range 0 to 15 := 0;
-- Starting update word offset
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_INCLUDE_DESC_UPDATE : integer range 0 to 1 := 1;
-- Include or Exclude Scatter Gather Descriptor Update
-- 0 = Exclude Descriptor Update
-- 1 = Include Descriptor Update
C_INCLUDE_INTRPT : integer range 0 to 1 := 1;
-- Include/Exclude interrupt logic coalescing
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_INCLUDE_DLYTMR : integer range 0 to 1 := 1;
-- Include/Exclude interrupt delay timer
-- 0 = Exclude Delay timer
-- 1 = Include Delay timer
C_DLYTMR_RESOLUTION : integer range 1 to 100000 := 125;
-- Interrupt Delay Timer resolution in usec
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_ENABLE_CDMA : integer range 0 to 1 := 0;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_NUM_S2MM_CHANNELS : integer range 1 to 16 := 1;
C_NUM_MM2S_CHANNELS : integer range 1 to 16 := 1;
C_ACTUAL_ADDR : integer range 32 to 64 := 32;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
p_reset_n : in std_logic ;
--
dm_resetn : in std_logic ; --
sg_ctl : in std_logic_vector (7 downto 0) ;
--
-- Scatter Gather Write Address Channel --
m_axi_sg_awaddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_awlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_awsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_awprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_awcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awuser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_awvalid : out std_logic ; --
m_axi_sg_awready : in std_logic ; --
--
-- Scatter Gather Write Data Channel --
m_axi_sg_wdata : out std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_wstrb : out std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
m_axi_sg_wlast : out std_logic ; --
m_axi_sg_wvalid : out std_logic ; --
m_axi_sg_wready : in std_logic ; --
--
-- Scatter Gather Write Response Channel --
m_axi_sg_bresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_bvalid : in std_logic ; --
m_axi_sg_bready : out std_logic ; --
--
-- Scatter Gather Read Address Channel --
m_axi_sg_araddr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axi_sg_arlen : out std_logic_vector(7 downto 0) ; --
m_axi_sg_arsize : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arburst : out std_logic_vector(1 downto 0) ; --
m_axi_sg_arcache : out std_logic_vector(3 downto 0) ; --
m_axi_sg_aruser : out std_logic_vector(3 downto 0) ; --
m_axi_sg_arprot : out std_logic_vector(2 downto 0) ; --
m_axi_sg_arvalid : out std_logic ; --
m_axi_sg_arready : in std_logic ; --
--
-- Memory Map to Stream Scatter Gather Read Data Channel --
m_axi_sg_rdata : in std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rlast : in std_logic ; --
m_axi_sg_rvalid : in std_logic ; --
m_axi_sg_rready : out std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_cyclic : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_cntrl_strm_stop : in std_logic ;
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_updt_idle : out std_logic ; --
ch1_updt_ioc_irq_set : out std_logic ; --
ch1_updt_interr_set : out std_logic ; --
ch1_updt_slverr_set : out std_logic ; --
ch1_updt_decerr_set : out std_logic ; --
ch1_dma_interr_set : out std_logic ; --
ch1_dma_slverr_set : out std_logic ; --
ch1_dma_decerr_set : out std_logic ; --
--
--
-- Channel 1 Interrupt Coalescing Signals --
ch1_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch1_dlyirq_dsble : in std_logic ; --
ch1_irqdelay_wren : in std_logic ; --
ch1_irqdelay : in std_logic_vector(7 downto 0) ; --
ch1_irqthresh_wren : in std_logic ; --
ch1_irqthresh : in std_logic_vector(7 downto 0) ; --
ch1_packet_sof : in std_logic ; --
ch1_packet_eof : in std_logic ; --
ch1_ioc_irq_set : out std_logic ; --
ch1_dly_irq_set : out std_logic ; --
ch1_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch1_irqthresh_status : out std_logic_vector(7 downto 0) ; --
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ; --
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
m_axis_ch1_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch1_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch1_ftch_tvalid_new : out std_logic ; --
m_axis_ftch1_desc_available : out std_logic;
--
--
-- Channel 1 AXI Update Stream In --
s_axis_ch1_updt_aclk : in std_logic ; --
s_axis_ch1_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch1_updtptr_tvalid : in std_logic ; --
s_axis_ch1_updtptr_tready : out std_logic ; --
s_axis_ch1_updtptr_tlast : in std_logic ; --
--
s_axis_ch1_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch1_updtsts_tvalid : in std_logic ; --
s_axis_ch1_updtsts_tready : out std_logic ; --
s_axis_ch1_updtsts_tlast : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_cyclic : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_updt_idle : out std_logic ; --
ch2_updt_ioc_irq_set : out std_logic ; --
ch2_updt_interr_set : out std_logic ; --
ch2_updt_slverr_set : out std_logic ; --
ch2_updt_decerr_set : out std_logic ; --
ch2_dma_interr_set : out std_logic ; --
ch2_dma_slverr_set : out std_logic ; --
ch2_dma_decerr_set : out std_logic ; --
--
-- Channel 2 Interrupt Coalescing Signals --
ch2_irqthresh_rstdsbl : in std_logic ;-- CR572013 --
ch2_dlyirq_dsble : in std_logic ; --
ch2_irqdelay_wren : in std_logic ; --
ch2_irqdelay : in std_logic_vector(7 downto 0) ; --
ch2_irqthresh_wren : in std_logic ; --
ch2_irqthresh : in std_logic_vector(7 downto 0) ; --
ch2_packet_sof : in std_logic ; --
ch2_packet_eof : in std_logic ; --
ch2_ioc_irq_set : out std_logic ; --
ch2_dly_irq_set : out std_logic ; --
ch2_irqdelay_status : out std_logic_vector(7 downto 0) ; --
ch2_irqthresh_status : out std_logic_vector(7 downto 0) ; --
ch2_update_active : out std_logic ;
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic ; --
--
m_axis_ch2_ftch_tdata_new : out std_logic_vector --
(96+31*C_ENABLE_CDMA+(2+C_ENABLE_CDMA)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_ch2_ftch_tdata_mcdma_new : out std_logic_vector --
(63 downto 0); --
m_axis_ch2_ftch_tdata_mcdma_nxt : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
m_axis_ch2_ftch_tvalid_new : out std_logic ; --
m_axis_ftch2_desc_available : out std_logic;
-- Channel 2 AXI Update Stream In --
s_axis_ch2_updt_aclk : in std_logic ; --
s_axis_ch2_updtptr_tdata : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_ch2_updtptr_tvalid : in std_logic ; --
s_axis_ch2_updtptr_tready : out std_logic ; --
s_axis_ch2_updtptr_tlast : in std_logic ; --
--
--
s_axis_ch2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_ch2_updtsts_tvalid : in std_logic ; --
s_axis_ch2_updtsts_tready : out std_logic ; --
s_axis_ch2_updtsts_tlast : in std_logic ; --
--
--
-- Error addresses --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_error : out std_logic ; --
updt_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(31 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
(3 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic := '0'; --
m_axis_mm2s_cntrl_tlast : out std_logic ;
bd_eq : out std_logic
);
end axi_sg;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant AXI_LITE_MODE : integer := 2; -- DataMover Lite Mode
constant EXCLUDE : integer := 0; -- Define Exclude as 0
constant NEVER_HALT : std_logic := '0'; -- Never halt sg datamover
-- Always include descriptor fetch (use lite datamover)
constant INCLUDE_DESC_FETCH : integer := AXI_LITE_MODE;
-- Selectable include descriptor update (use lite datamover)
constant INCLUDE_DESC_UPDATE : integer := AXI_LITE_MODE * C_INCLUDE_DESC_UPDATE;
-- Always allow address requests
constant ALWAYS_ALLOW : std_logic := '1';
-- If async mode and number of descriptors to fetch is zero then set number
-- of descriptors to fetch as 1.
constant SG_FTCH_DESC2QUEUE : integer := max2(C_SG_FTCH_DESC2QUEUE,C_AXIS_IS_ASYNC);
constant SG_UPDT_DESC2QUEUE : integer := max2(C_SG_UPDT_DESC2QUEUE,C_AXIS_IS_ASYNC);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- DataMover MM2S Fetch Command Stream Signals
signal s_axis_ftch_cmd_tvalid : std_logic := '0';
signal s_axis_ftch_cmd_tready : std_logic := '0';
signal s_axis_ftch_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover MM2S Fetch Status Stream Signals
signal m_axis_ftch_sts_tvalid : std_logic := '0';
signal m_axis_ftch_sts_tready : std_logic := '0';
signal m_axis_ftch_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_ftch_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal mm2s_err : std_logic := '0';
-- DataMover MM2S Fetch Stream Signals
signal m_axis_mm2s_tdata : std_logic_vector
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_axis_mm2s_tkeep : std_logic_vector
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_mm2s_tlast : std_logic := '0';
signal m_axis_mm2s_tvalid : std_logic := '0';
signal m_axis_mm2s_tready : std_logic := '0';
-- DataMover S2MM Update Command Stream Signals
signal s_axis_updt_cmd_tvalid : std_logic := '0';
signal s_axis_updt_cmd_tready : std_logic := '0';
signal s_axis_updt_cmd_tdata : std_logic_vector
(((1+C_ENABLE_MULTI_CHANNEL)*C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
-- DataMover S2MM Update Status Stream Signals
signal m_axis_updt_sts_tvalid : std_logic := '0';
signal m_axis_updt_sts_tready : std_logic := '0';
signal m_axis_updt_sts_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_updt_sts_tkeep : std_logic_vector(0 downto 0) := (others => '0');
signal s2mm_err : std_logic := '0';
-- DataMover S2MM Update Stream Signals
signal s_axis_s2mm_tdata : std_logic_vector
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_s2mm_tkeep : std_logic_vector
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0) := (others => '1');
signal s_axis_s2mm_tlast : std_logic := '0';
signal s_axis_s2mm_tvalid : std_logic := '0';
signal s_axis_s2mm_tready : std_logic := '0';
-- Channel 1 internals
signal ch1_ftch_active : std_logic := '0';
signal ch1_ftch_queue_empty : std_logic := '0';
signal ch1_ftch_queue_full : std_logic := '0';
signal ch1_nxtdesc_wren : std_logic := '0';
signal ch1_updt_active : std_logic := '0';
signal ch1_updt_queue_empty : std_logic := '0';
signal ch1_updt_curdesc_wren : std_logic := '0';
signal ch1_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch1_updt_ioc : std_logic := '0';
signal ch1_updt_ioc_irq_set_i : std_logic := '0';
signal ch1_dma_interr : std_logic := '0';
signal ch1_dma_slverr : std_logic := '0';
signal ch1_dma_decerr : std_logic := '0';
signal ch1_dma_interr_set_i : std_logic := '0';
signal ch1_dma_slverr_set_i : std_logic := '0';
signal ch1_dma_decerr_set_i : std_logic := '0';
signal ch1_updt_done : std_logic := '0';
signal ch1_ftch_pause : std_logic := '0';
-- Channel 2 internals
signal ch2_ftch_active : std_logic := '0';
signal ch2_ftch_queue_empty : std_logic := '0';
signal ch2_ftch_queue_full : std_logic := '0';
signal ch2_nxtdesc_wren : std_logic := '0';
signal ch2_updt_active : std_logic := '0';
signal ch2_updt_queue_empty : std_logic := '0';
signal ch2_updt_curdesc_wren : std_logic := '0';
signal ch2_updt_curdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ch2_updt_ioc : std_logic := '0';
signal ch2_updt_ioc_irq_set_i : std_logic := '0';
signal ch2_dma_interr : std_logic := '0';
signal ch2_dma_slverr : std_logic := '0';
signal ch2_dma_decerr : std_logic := '0';
signal ch2_dma_interr_set_i : std_logic := '0';
signal ch2_dma_slverr_set_i : std_logic := '0';
signal ch2_dma_decerr_set_i : std_logic := '0';
signal ch2_updt_done : std_logic := '0';
signal ch2_ftch_pause : std_logic := '0';
signal nxtdesc : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ftch_cmnd_wr : std_logic := '0';
signal ftch_cmnd_data : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) := (others => '0');
signal ftch_stale_desc : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal updt_error_i : std_logic := '0';
signal ch1_irqthresh_decr : std_logic := '0'; --CR567661
signal ch2_irqthresh_decr : std_logic := '0'; --CR567661
signal m_axi_sg_awaddr_int : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
signal m_axi_sg_awlen_int : std_logic_vector(7 downto 0) ; --
signal m_axi_sg_awsize_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awburst_int : std_logic_vector(1 downto 0) ; --
signal m_axi_sg_awprot_int : std_logic_vector(2 downto 0) ; --
signal m_axi_sg_awcache_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awuser_int : std_logic_vector(3 downto 0) ; --
signal m_axi_sg_awvalid_int : std_logic ; --
signal m_axi_sg_awready_int : std_logic ; --
--
-- Scatter Gather Write Data Channel --
signal m_axi_sg_wdata_int : std_logic_vector --
(C_M_AXI_SG_DATA_WIDTH-1 downto 0) ; --
signal m_axi_sg_wstrb_int : std_logic_vector --
((C_M_AXI_SG_DATA_WIDTH/8)-1 downto 0); --
signal m_axi_sg_wlast_int : std_logic ; --
signal m_axi_sg_wvalid_int : std_logic ; --
signal m_axi_sg_wready_int : std_logic ; --
signal m_axi_sg_bresp_int : std_logic_vector (1 downto 0);
signal m_axi_sg_bvalid_int : std_logic;
signal m_axi_sg_bready_int : std_logic;
signal m_axi_sg_bvalid_int_del : std_logic;
signal ch2_eof_detected : std_logic;
signal s_axis_ch2_updtsts_tready_i : std_logic;
signal ch2_sg_idle, tail_updt_latch : std_logic;
signal tail_updt : std_logic;
signal ch2_taildesc_wren_int : std_logic;
signal ch2_sg_idle_int : std_logic;
signal ftch_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal updt_error_addr_1 : std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ;
signal ch1_ftch_interr_set_i : std_logic := '0';
signal ch1_ftch_slverr_set_i : std_logic := '0';
signal ch1_ftch_decerr_set_i : std_logic := '0';
signal ch2_ftch_interr_set_i : std_logic := '0';
signal ch2_ftch_slverr_set_i : std_logic := '0';
signal ch2_ftch_decerr_set_i : std_logic := '0';
signal ch1_updt_interr_set_i : std_logic := '0';
signal ch1_updt_slverr_set_i : std_logic := '0';
signal ch1_updt_decerr_set_i : std_logic := '0';
signal ch2_updt_interr_set_i : std_logic := '0';
signal ch2_updt_slverr_set_i : std_logic := '0';
signal ch2_updt_decerr_set_i : std_logic := '0';
signal ftch_error_capture : std_logic := '0';
signal updt_error_capture : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
updt_error <= updt_error_i;
ftch_error <= ftch_error_i;
ftch_error_capture <= ch1_ftch_interr_set_i or
ch1_ftch_slverr_set_i or
ch1_ftch_decerr_set_i or
ch2_ftch_interr_set_i or
ch2_ftch_slverr_set_i or
ch2_ftch_decerr_set_i;
ch1_ftch_interr_set <= ch1_ftch_interr_set_i;
ch1_ftch_slverr_set <= ch1_ftch_slverr_set_i;
ch1_ftch_decerr_set <= ch1_ftch_decerr_set_i;
ch2_ftch_interr_set <= ch2_ftch_interr_set_i;
ch2_ftch_slverr_set <= ch2_ftch_slverr_set_i;
ch2_ftch_decerr_set <= ch2_ftch_decerr_set_i;
updt_error_capture <= ch1_updt_interr_set_i or
ch1_updt_slverr_set_i or
ch1_updt_decerr_set_i or
ch2_updt_interr_set_i or
ch2_updt_slverr_set_i or
ch2_updt_decerr_set_i or
ch2_dma_interr_set_i or
ch2_dma_slverr_set_i or
ch2_dma_decerr_set_i or
ch1_dma_interr_set_i or
ch1_dma_slverr_set_i or
ch1_dma_decerr_set_i;
ch1_updt_interr_set <= ch1_updt_interr_set_i;
ch1_updt_slverr_set <= ch1_updt_slverr_set_i;
ch1_updt_decerr_set <= ch1_updt_decerr_set_i;
ch2_updt_interr_set <= ch2_updt_interr_set_i;
ch2_updt_slverr_set <= ch2_updt_slverr_set_i;
ch2_updt_decerr_set <= ch2_updt_decerr_set_i;
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (31 downto 6) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (31 downto 6)<= ftch_error_addr_1(31 downto 6);
elsif (updt_error_capture = '1') then
ftch_error_addr (31 downto 6)<= updt_error_addr_1(31 downto 6);
end if;
end if;
end process;
ADDR_64 : if (C_M_AXI_SG_ADDR_WIDTH > 32) generate
begin
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
ftch_error_addr (63 downto 32) <= (others => '0');
elsif (ftch_error_capture = '1') then -- or updt_error_i = '1') then
ftch_error_addr (63 downto 32)<= ftch_error_addr_1(63 downto 32);
elsif (updt_error_capture = '1') then
ftch_error_addr (63 downto 32)<= updt_error_addr_1(63 downto 32);
end if;
end if;
end process;
end generate ADDR_64;
updt_error_addr <= (others => '0');
ftch_error_addr (5 downto 0) <= (others => '0');
-- Always valid therefore fix to '1'
s_axis_s2mm_tkeep <= (others => '1');
-- Drive interrupt on complete set out
--ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i; -- CR567661
--ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i; -- CR567661
ch1_dma_interr_set <= ch1_dma_interr_set_i;
ch1_dma_slverr_set <= ch1_dma_slverr_set_i;
ch1_dma_decerr_set <= ch1_dma_decerr_set_i;
ch2_dma_interr_set <= ch2_dma_interr_set_i;
ch2_dma_slverr_set <= ch2_dma_slverr_set_i;
ch2_dma_decerr_set <= ch2_dma_decerr_set_i;
s_axis_ch2_updtsts_tready <= s_axis_ch2_updtsts_tready_i;
EOF_DET : if (C_ENABLE_MULTI_CHANNEL = 1) generate
ch2_eof_detected <= s_axis_ch2_updtsts_tdata (26)
and s_axis_ch2_updtsts_tready_i
and s_axis_ch2_updtsts_tvalid
and s_axis_ch2_updtsts_tlast;
-- ch2_eof_detected <= '0';
ch2_sg_idle_int <= ch2_sg_idle;
-- ch2_sg_idle_int <= '0'; --ch2_sg_idle;
TAILUPDT_LATCH : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or tail_updt = '1' ) then -- nned to have some reset condition here
tail_updt <= '0';
elsif(ch2_sg_idle = '1' and tail_updt_latch = '1' and tail_updt = '0')then
tail_updt <= '1';
end if;
end if;
end process TAILUPDT_LATCH;
ch2_taildesc_wren_int <= ch2_taildesc_wren or tail_updt;
--ch2_taildesc_wren_int <= ch2_taildesc_wren;
end generate EOF_DET;
NOEOF_DET : if (C_ENABLE_MULTI_CHANNEL = 0) generate
tail_updt <= '0';
ch2_eof_detected <= '0';
ch2_taildesc_wren_int <= ch2_taildesc_wren;
ch2_sg_idle_int <= '0'; --ch2_sg_idle;
end generate NOEOF_DET;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Manager
-------------------------------------------------------------------------------
I_SG_FETCH_MNGR : entity axi_sg_v4_1_3.axi_sg_ftch_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,
ch1_updt_done => ch1_updt_done ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_interr_set => ch1_ftch_interr_set_i ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set_i ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set_i ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_curdesc => ch1_curdesc ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,
ch2_updt_done => ch2_updt_done ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_interr_set => ch2_ftch_interr_set_i ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set_i ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set_i ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren_int ,
ch2_taildesc => ch2_taildesc ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_curdesc => ch2_curdesc ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
ch2_eof_detected => ch2_eof_detected ,
tail_updt => tail_updt ,
tail_updt_latch => tail_updt_latch ,
ch2_sg_idle => ch2_sg_idle ,
nxtdesc => nxtdesc ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
mm2s_err => mm2s_err ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
updt_error => updt_error_i ,
ftch_error => ftch_error_i ,
ftch_error_addr => ftch_error_addr_1 ,
bd_eq => bd_eq
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Queue
-------------------------------------------------------------------------------
I_SG_FETCH_QUEUE : entity axi_sg_v4_1_3.axi_sg_ftch_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => SG_FTCH_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_ASYNC => C_ASYNC ,
C_ENABLE_CDMA => C_ENABLE_CDMA,
C_ACTUAL_ADDR => C_ACTUAL_ADDR,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aclk => m_axi_mm2s_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
p_reset_n => p_reset_n ,
ch2_sg_idle => ch2_sg_idle_int ,
-- Channel 1 Control
ch1_desc_flush => ch1_desc_flush ,
ch1_cyclic => ch1_cyclic ,
ch1_cntrl_strm_stop => ch1_cntrl_strm_stop ,
ch1_ftch_active => ch1_ftch_active ,
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control
ch2_ftch_active => ch2_ftch_active ,
ch2_cyclic => ch2_cyclic ,
ch2_desc_flush => ch2_desc_flush ,
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_ftch_pause => ch2_ftch_pause ,
nxtdesc => nxtdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
ftch_stale_desc => ftch_stale_desc ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ch1_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ch1_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ch1_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ch1_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ch1_ftch_tlast => m_axis_ch1_ftch_tlast ,
m_axis_ch1_ftch_tdata_new => m_axis_ch1_ftch_tdata_new ,
m_axis_ch1_ftch_tdata_mcdma_new => m_axis_ch1_ftch_tdata_mcdma_new ,
m_axis_ch1_ftch_tvalid_new => m_axis_ch1_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available,
m_axis_ch2_ftch_tdata_new => m_axis_ch2_ftch_tdata_new ,
m_axis_ch2_ftch_tdata_mcdma_new => m_axis_ch2_ftch_tdata_mcdma_new ,
m_axis_ch2_ftch_tdata_mcdma_nxt => m_axis_ch2_ftch_tdata_mcdma_nxt ,
m_axis_ch2_ftch_tvalid_new => m_axis_ch2_ftch_tvalid_new ,
m_axis_ftch2_desc_available => m_axis_ftch2_desc_available,
-- Channel 2 AXI Fetch Stream Out
m_axis_ch2_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ch2_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ch2_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ch2_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ch2_ftch_tlast => m_axis_ch2_ftch_tlast ,
m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
);
-- Include Scatter Gather Descriptor Update logic
GEN_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 1 generate
begin
-- CR567661
-- Route update version of IOC set to threshold
-- counter decrement control
ch1_irqthresh_decr <= ch1_updt_ioc_irq_set_i;
ch2_irqthresh_decr <= ch2_updt_ioc_irq_set_i;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_updt_ioc_irq_set_i;
ch2_updt_ioc_irq_set <= ch2_updt_ioc_irq_set_i;
-------------------------------------------------------------------------------
-- Scatter Gather Update Manager
-------------------------------------------------------------------------------
I_SG_UPDATE_MNGR : entity axi_sg_v4_1_3.axi_sg_updt_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH1_FIRST_UPDATE_WORD => C_SG_CH1_FIRST_UPDATE_WORD ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_SG_CH2_FIRST_UPDATE_WORD => C_SG_CH2_FIRST_UPDATE_WORD
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
ch1_updt_idle => ch1_updt_idle ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
ch1_updt_interr_set => ch1_updt_interr_set_i ,
ch1_updt_slverr_set => ch1_updt_slverr_set_i ,
ch1_updt_decerr_set => ch1_updt_decerr_set_i ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_done => ch1_updt_done ,
-- Channel 2 Control and Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_updt_idle => ch2_updt_idle ,
ch2_updt_active => ch2_updt_active ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
ch2_updt_interr_set => ch2_updt_interr_set_i ,
ch2_updt_slverr_set => ch2_updt_slverr_set_i ,
ch2_updt_decerr_set => ch2_updt_decerr_set_i ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_done => ch2_updt_done ,
-- User Command Interface Ports (AXI Stream)
s_axis_updt_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_updt_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_updt_cmd_tdata => s_axis_updt_cmd_tdata ((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0) ,
-- User Status Interface Ports (AXI Stream)
m_axis_updt_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_updt_sts_tready => m_axis_updt_sts_tready ,
m_axis_updt_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_updt_sts_tkeep => m_axis_updt_sts_tkeep ,
s2mm_err => s2mm_err ,
ftch_error => ftch_error_i ,
updt_error => updt_error_i ,
updt_error_addr => updt_error_addr_1
);
-------------------------------------------------------------------------------
-- Scatter Gather Update Queue
-------------------------------------------------------------------------------
I_SG_UPDATE_QUEUE : entity axi_sg_v4_1_3.axi_sg_updt_q_mngr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_SG_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_SG_UPDT_DESC2QUEUE => SG_UPDT_DESC2QUEUE ,
C_SG_CH1_WORDS_TO_UPDATE => C_SG_CH1_WORDS_TO_UPDATE ,
C_SG_CH2_WORDS_TO_UPDATE => C_SG_CH2_WORDS_TO_UPDATE ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control
ch1_updt_curdesc_wren => ch1_updt_curdesc_wren ,
ch1_updt_curdesc => ch1_updt_curdesc ,
ch1_updt_active => ch1_updt_active ,
ch1_updt_queue_empty => ch1_updt_queue_empty ,
ch1_updt_ioc => ch1_updt_ioc ,
ch1_updt_ioc_irq_set => ch1_updt_ioc_irq_set_i ,
-- Channel 1 Update Descriptor Status
ch1_dma_interr => ch1_dma_interr ,
ch1_dma_slverr => ch1_dma_slverr ,
ch1_dma_decerr => ch1_dma_decerr ,
ch1_dma_interr_set => ch1_dma_interr_set_i ,
ch1_dma_slverr_set => ch1_dma_slverr_set_i ,
ch1_dma_decerr_set => ch1_dma_decerr_set_i ,
-- Channel 2 Control
ch2_updt_active => ch2_updt_active ,
-- ch2_updt_curdesc_wren => ch2_updt_curdesc_wren ,
-- ch2_updt_curdesc => ch2_updt_curdesc ,
ch2_updt_queue_empty => ch2_updt_queue_empty ,
ch2_updt_ioc => ch2_updt_ioc ,
ch2_updt_ioc_irq_set => ch2_updt_ioc_irq_set_i ,
-- Channel 2 Update Descriptor Status
ch2_dma_interr => ch2_dma_interr ,
ch2_dma_slverr => ch2_dma_slverr ,
ch2_dma_decerr => ch2_dma_decerr ,
ch2_dma_interr_set => ch2_dma_interr_set_i ,
ch2_dma_slverr_set => ch2_dma_slverr_set_i ,
ch2_dma_decerr_set => ch2_dma_decerr_set_i ,
-- S2MM Stream Out To DataMover
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Channel 1 AXI Update Stream In
s_axis_ch1_updt_aclk => s_axis_ch1_updt_aclk ,
s_axis_ch1_updtptr_tdata => s_axis_ch1_updtptr_tdata ,
s_axis_ch1_updtptr_tvalid => s_axis_ch1_updtptr_tvalid ,
s_axis_ch1_updtptr_tready => s_axis_ch1_updtptr_tready ,
s_axis_ch1_updtptr_tlast => s_axis_ch1_updtptr_tlast ,
s_axis_ch1_updtsts_tdata => s_axis_ch1_updtsts_tdata ,
s_axis_ch1_updtsts_tvalid => s_axis_ch1_updtsts_tvalid ,
s_axis_ch1_updtsts_tready => s_axis_ch1_updtsts_tready ,
s_axis_ch1_updtsts_tlast => s_axis_ch1_updtsts_tlast ,
-- Channel 2 AXI Update Stream In
s_axis_ch2_updt_aclk => s_axis_ch2_updt_aclk ,
s_axis_ch2_updtptr_tdata => s_axis_ch2_updtptr_tdata ,
s_axis_ch2_updtptr_tvalid => s_axis_ch2_updtptr_tvalid ,
s_axis_ch2_updtptr_tready => s_axis_ch2_updtptr_tready ,
s_axis_ch2_updtptr_tlast => s_axis_ch2_updtptr_tlast ,
s_axis_ch2_updtsts_tdata => s_axis_ch2_updtsts_tdata ,
s_axis_ch2_updtsts_tvalid => s_axis_ch2_updtsts_tvalid ,
s_axis_ch2_updtsts_tready => s_axis_ch2_updtsts_tready_i ,
s_axis_ch2_updtsts_tlast => s_axis_ch2_updtsts_tlast
);
end generate GEN_DESC_UPDATE;
-- Exclude Scatter Gather Descriptor Update logic
GEN_NO_DESC_UPDATE : if C_INCLUDE_DESC_UPDATE = 0 generate
begin
ch1_updt_idle <= '1';
ch1_updt_active <= '0';
-- ch1_updt_ioc_irq_set <= '0';--CR#569609
ch1_updt_interr_set <= '0';
ch1_updt_slverr_set <= '0';
ch1_updt_decerr_set <= '0';
ch1_dma_interr_set_i <= '0';
ch1_dma_slverr_set_i <= '0';
ch1_dma_decerr_set_i <= '0';
ch1_updt_done <= '1'; -- Always done
ch2_updt_idle <= '1';
ch2_updt_active <= '0';
-- ch2_updt_ioc_irq_set <= '0'; --CR#569609
ch2_updt_interr_set <= '0';
ch2_updt_slverr_set <= '0';
ch2_updt_decerr_set <= '0';
ch2_dma_interr_set_i <= '0';
ch2_dma_slverr_set_i <= '0';
ch2_dma_decerr_set_i <= '0';
ch2_updt_done <= '1'; -- Always done
s_axis_updt_cmd_tvalid <= '0';
s_axis_updt_cmd_tdata <= (others => '0');
m_axis_updt_sts_tready <= '0';
updt_error_i <= '0';
updt_error_addr <= (others => '0');
ch1_updt_curdesc_wren <= '0';
ch1_updt_curdesc <= (others => '0');
ch1_updt_queue_empty <= '0';
ch1_updt_ioc <= '0';
ch1_dma_interr <= '0';
ch1_dma_slverr <= '0';
ch1_dma_decerr <= '0';
ch2_updt_curdesc_wren <= '0';
ch2_updt_curdesc <= (others => '0');
ch2_updt_queue_empty <= '0';
ch2_updt_ioc <= '0';
ch2_dma_interr <= '0';
ch2_dma_slverr <= '0';
ch2_dma_decerr <= '0';
s_axis_s2mm_tdata <= (others => '0');
s_axis_s2mm_tlast <= '0';
s_axis_s2mm_tvalid <= '0';
s_axis_ch1_updtptr_tready <= '0';
s_axis_ch2_updtptr_tready <= '0';
s_axis_ch1_updtsts_tready <= '0';
s_axis_ch2_updtsts_tready <= '0';
-- CR567661
-- Route packet eof to threshold counter decrement control
ch1_irqthresh_decr <= ch1_packet_eof;
ch2_irqthresh_decr <= ch2_packet_eof;
-- Drive interrupt on complete set out
ch1_updt_ioc_irq_set <= ch1_packet_eof;
ch2_updt_ioc_irq_set <= ch2_packet_eof;
end generate GEN_NO_DESC_UPDATE;
-------------------------------------------------------------------------------
-- Scatter Gather Interrupt Coalescing
-------------------------------------------------------------------------------
GEN_INTERRUPT_LOGIC : if C_INCLUDE_INTRPT = 1 generate
begin
I_AXI_SG_INTRPT : entity axi_sg_v4_1_3.axi_sg_intrpt
generic map(
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_INCLUDE_DLYTMR => C_INCLUDE_DLYTMR ,
C_DLYTMR_RESOLUTION => C_DLYTMR_RESOLUTION
)
port map(
-- Secondary Clock and Reset
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
ch1_irqthresh_decr => ch1_irqthresh_decr , -- CR567661
ch1_irqthresh_rstdsbl => ch1_irqthresh_rstdsbl , -- CR572013
ch1_dlyirq_dsble => ch1_dlyirq_dsble ,
ch1_irqdelay_wren => ch1_irqdelay_wren ,
ch1_irqdelay => ch1_irqdelay ,
ch1_irqthresh_wren => ch1_irqthresh_wren ,
ch1_irqthresh => ch1_irqthresh ,
ch1_packet_sof => ch1_packet_sof ,
ch1_packet_eof => ch1_packet_eof ,
ch1_ioc_irq_set => ch1_ioc_irq_set ,
ch1_dly_irq_set => ch1_dly_irq_set ,
ch1_irqdelay_status => ch1_irqdelay_status ,
ch1_irqthresh_status => ch1_irqthresh_status ,
ch2_irqthresh_decr => ch2_irqthresh_decr , -- CR567661
ch2_irqthresh_rstdsbl => ch2_irqthresh_rstdsbl , -- CR572013
ch2_dlyirq_dsble => ch2_dlyirq_dsble ,
ch2_irqdelay_wren => ch2_irqdelay_wren ,
ch2_irqdelay => ch2_irqdelay ,
ch2_irqthresh_wren => ch2_irqthresh_wren ,
ch2_irqthresh => ch2_irqthresh ,
ch2_packet_sof => ch2_packet_sof ,
ch2_packet_eof => ch2_packet_eof ,
ch2_ioc_irq_set => ch2_ioc_irq_set ,
ch2_dly_irq_set => ch2_dly_irq_set ,
ch2_irqdelay_status => ch2_irqdelay_status ,
ch2_irqthresh_status => ch2_irqthresh_status
);
end generate GEN_INTERRUPT_LOGIC;
GEN_NO_INTRPT_LOGIC : if C_INCLUDE_INTRPT = 0 generate
begin
ch1_ioc_irq_set <= '0';
ch1_dly_irq_set <= '0';
ch1_irqdelay_status <= (others => '0');
ch1_irqthresh_status <= (others => '0');
ch2_ioc_irq_set <= '0';
ch2_dly_irq_set <= '0';
ch2_irqdelay_status <= (others => '0');
ch2_irqthresh_status <= (others => '0');
end generate GEN_NO_INTRPT_LOGIC;
-------------------------------------------------------------------------------
-- Scatter Gather DataMover Lite
-------------------------------------------------------------------------------
I_SG_AXI_DATAMOVER : entity axi_sg_v4_1_3.axi_sg_datamover
generic map(
C_INCLUDE_MM2S => 2, --INCLUDE_DESC_FETCH, -- Lite
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_MM2S_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_M_AXIS_MM2S_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_MM2S_STSFIFO => 0, -- Exclude
C_MM2S_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_MM2S_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_MM2S_DRE => 0, -- No DRE
C_MM2S_BURST_SIZE => 16, -- Set to Min
C_MM2S_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_MM2S_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL, --
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_INCLUDE_S2MM => 2, --INCLUDE_DESC_UPDATE, -- Lite
C_M_AXI_S2MM_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH, -- 32 or 64
C_M_AXI_S2MM_DATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_S_AXIS_S2MM_TDATA_WIDTH => C_M_AXI_SG_DATA_WIDTH, -- Fixed at 32
C_INCLUDE_S2MM_STSFIFO => 0, -- Exclude
C_S2MM_STSCMD_FIFO_DEPTH => 1, -- Set to Min
C_S2MM_STSCMD_IS_ASYNC => 0, -- Synchronous
C_INCLUDE_S2MM_DRE => 0, -- No DRE
C_S2MM_BURST_SIZE => 16, -- Set to Min;
C_S2MM_ADDR_PIPE_DEPTH => 1, -- Only 1 outstanding request
C_S2MM_INCLUDE_SF => 0, -- Exclude Store-and-Forward
C_FAMILY => C_FAMILY
)
port map(
-- MM2S Primary Clock / Reset input
m_axi_mm2s_aclk => m_axi_sg_aclk ,
m_axi_mm2s_aresetn => dm_resetn ,
mm2s_halt => NEVER_HALT ,
mm2s_halt_cmplt => open ,
mm2s_err => mm2s_err ,
mm2s_allow_addr_req => ALWAYS_ALLOW ,
mm2s_addr_req_posted => open ,
mm2s_rd_xfer_cmplt => open ,
sg_ctl => sg_ctl ,
-- Memory Map to Stream Command FIFO and Status FIFO I/O --------------
m_axis_mm2s_cmdsts_aclk => m_axi_sg_aclk ,
m_axis_mm2s_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_ftch_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- MM2S AXI Address Channel I/O --------------------------------------
m_axi_mm2s_arid => open ,
m_axi_mm2s_araddr => m_axi_sg_araddr ,
m_axi_mm2s_arlen => m_axi_sg_arlen ,
m_axi_mm2s_arsize => m_axi_sg_arsize ,
m_axi_mm2s_arburst => m_axi_sg_arburst ,
m_axi_mm2s_arprot => m_axi_sg_arprot ,
m_axi_mm2s_arcache => m_axi_sg_arcache ,
m_axi_mm2s_aruser => m_axi_sg_aruser ,
m_axi_mm2s_arvalid => m_axi_sg_arvalid ,
m_axi_mm2s_arready => m_axi_sg_arready ,
-- MM2S AXI MMap Read Data Channel I/O -------------------------------
m_axi_mm2s_rdata => m_axi_sg_rdata ,
m_axi_mm2s_rresp => m_axi_sg_rresp ,
m_axi_mm2s_rlast => m_axi_sg_rlast ,
m_axi_mm2s_rvalid => m_axi_sg_rvalid ,
m_axi_mm2s_rready => m_axi_sg_rready ,
-- MM2S AXI Master Stream Channel I/O --------------------------------
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tkeep => m_axis_mm2s_tkeep ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => m_axis_mm2s_tready ,
-- Testing Support I/O
mm2s_dbg_sel => (others => '0') ,
mm2s_dbg_data => open ,
-- S2MM Primary Clock/Reset input
m_axi_s2mm_aclk => m_axi_sg_aclk ,
m_axi_s2mm_aresetn => dm_resetn ,
s2mm_halt => NEVER_HALT ,
s2mm_halt_cmplt => open ,
s2mm_err => s2mm_err ,
s2mm_allow_addr_req => ALWAYS_ALLOW ,
s2mm_addr_req_posted => open ,
s2mm_wr_xfer_cmplt => open ,
s2mm_ld_nxt_len => open ,
s2mm_wr_len => open ,
-- Stream to Memory Map Command FIFO and Status FIFO I/O --------------
m_axis_s2mm_cmdsts_awclk => m_axi_sg_aclk ,
m_axis_s2mm_cmdsts_aresetn => dm_resetn ,
-- User Command Interface Ports (AXI Stream)
s_axis_s2mm_cmd_tvalid => s_axis_updt_cmd_tvalid ,
s_axis_s2mm_cmd_tready => s_axis_updt_cmd_tready ,
s_axis_s2mm_cmd_tdata => s_axis_updt_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_s2mm_sts_tvalid => m_axis_updt_sts_tvalid ,
m_axis_s2mm_sts_tready => m_axis_updt_sts_tready ,
m_axis_s2mm_sts_tdata => m_axis_updt_sts_tdata ,
m_axis_s2mm_sts_tkeep => m_axis_updt_sts_tkeep ,
-- S2MM AXI Address Channel I/O --------------------------------------
m_axi_s2mm_awid => open ,
m_axi_s2mm_awaddr => m_axi_sg_awaddr_int ,
m_axi_s2mm_awlen => m_axi_sg_awlen_int ,
m_axi_s2mm_awsize => m_axi_sg_awsize_int ,
m_axi_s2mm_awburst => m_axi_sg_awburst_int ,
m_axi_s2mm_awprot => m_axi_sg_awprot_int ,
m_axi_s2mm_awcache => m_axi_sg_awcache_int ,
m_axi_s2mm_awuser => m_axi_sg_awuser_int ,
m_axi_s2mm_awvalid => m_axi_sg_awvalid_int ,
m_axi_s2mm_awready => m_axi_sg_awready_int ,
-- S2MM AXI MMap Write Data Channel I/O ------------------------------
m_axi_s2mm_wdata => m_axi_sg_wdata ,
m_axi_s2mm_wstrb => m_axi_sg_wstrb ,
m_axi_s2mm_wlast => m_axi_sg_wlast ,
m_axi_s2mm_wvalid => m_axi_sg_wvalid_int ,
m_axi_s2mm_wready => m_axi_sg_wready_int ,
-- S2MM AXI MMap Write response Channel I/O --------------------------
m_axi_s2mm_bresp => m_axi_sg_bresp_int ,
m_axi_s2mm_bvalid => m_axi_sg_bvalid_int ,
m_axi_s2mm_bready => m_axi_sg_bready_int ,
-- S2MM AXI Slave Stream Channel I/O ---------------------------------
s_axis_s2mm_tdata => s_axis_s2mm_tdata ,
s_axis_s2mm_tkeep => s_axis_s2mm_tkeep ,
s_axis_s2mm_tlast => s_axis_s2mm_tlast ,
s_axis_s2mm_tvalid => s_axis_s2mm_tvalid ,
s_axis_s2mm_tready => s_axis_s2mm_tready ,
-- Testing Support I/O
s2mm_dbg_sel => (others => '0') ,
s2mm_dbg_data => open
);
--ENABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS = 1) generate
-- begin
m_axi_sg_awaddr <= m_axi_sg_awaddr_int ;
m_axi_sg_awlen <= m_axi_sg_awlen_int ;
m_axi_sg_awsize <= m_axi_sg_awsize_int ;
m_axi_sg_awburst <= m_axi_sg_awburst_int;
m_axi_sg_awprot <= m_axi_sg_awprot_int ;
m_axi_sg_awcache <= m_axi_sg_awcache_int;
m_axi_sg_awuser <= m_axi_sg_awuser_int ;
m_axi_sg_awvalid <= m_axi_sg_awvalid_int;
m_axi_sg_awready_int <= m_axi_sg_awready;
m_axi_sg_wvalid <= m_axi_sg_wvalid_int;
m_axi_sg_wready_int <= m_axi_sg_wready;
m_axi_sg_bresp_int <= m_axi_sg_bresp;
m_axi_sg_bvalid_int <= m_axi_sg_bvalid;
m_axi_sg_bready <= m_axi_sg_bready_int;
-- end generate ENABLE_MM2S_STATUS;
--DISABLE_MM2S_STATUS: if (C_NUM_MM2S_CHANNELS > 1) generate
--
-- m_axi_sg_awaddr <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awaddr_int;
-- m_axi_sg_awlen <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awlen_int;
-- m_axi_sg_awsize <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awsize_int;
-- m_axi_sg_awburst <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awburst_int;
-- m_axi_sg_awprot <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awprot_int;
-- m_axi_sg_awcache <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awcache_int;
-- m_axi_sg_awuser <= (others => '0') when ch1_updt_active = '1' else m_axi_sg_awuser_int;
-- m_axi_sg_awvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_awvalid_int;
-- m_axi_sg_awready_int <= m_axi_sg_awvalid_int when ch1_updt_active = '1' else m_axi_sg_awready; -- to make sure that AXI logic is fine.
--
-- m_axi_sg_wvalid <= '0' when ch1_updt_active = '1' else m_axi_sg_wvalid_int;
-- m_axi_sg_wready_int <= m_axi_sg_wvalid_int when ch1_updt_active = '1' else m_axi_sg_wready; -- to make sure that AXI logic is fine
--
-- m_axi_sg_bresp_int <= m_axi_sg_bresp;
-- m_axi_sg_bvalid_int <= m_axi_sg_bvalid_int_del when ch1_updt_active = '1' else m_axi_sg_bvalid;
-- m_axi_sg_bready <= m_axi_sg_bready_int;
--
ch2_update_active <= ch2_updt_active;
--
---- A dummy response is needed to keep things running on DMA side
-- PROC_DUMMY_RESP : process (m_axi_sg_aclk)
-- begin
-- if (dm_resetn = '0') then
-- m_axi_sg_bvalid_int_del <= '0';
-- elsif (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
-- m_axi_sg_bvalid_int_del <= m_axi_sg_wvalid_int;
-- end if;
-- end process PROC_DUMMY_RESP;
--
-- end generate DISABLE_MM2S_STATUS;
end implementation;
| mit | 0b4b1cc143994d175c7ad94ab25f673f | 0.402502 | 4.026522 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/pll/SysPLL_zynq.vhd | 1 | 4,501 | -- 50 MHz PS to 40 MHz PL
-- 50 *
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity SysPLL_zynq is
port
(-- Clock in ports
CLK_IN : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end SysPLL_zynq;
architecture xilinx of SysPLL_zynq is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "SysPLL_zynq,clk_wiz_v3_6,{component_name=SysPLL_k7,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=5.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 20.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 25.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 20.000)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_IN,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
end xilinx;
| apache-2.0 | c45c736440f9278ded2eea2fcd81b060 | 0.571429 | 3.782353 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_mm2s_cmdsts_if.vhd | 1 | 15,459 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
| mit | 1439d7b0a845e998ca78c22205e734f7 | 0.443302 | 4.388022 | false | false | false | false |
mharndt/profibusmonitor | VHDL_Bausteine/TEST_CTRL_RS232_TX/CTRL_RS232_TX_VHDL.vhd | 2 | 13,128 | -- CTRL_RS232_TX
-- Input wird bitweise via RS232 versendet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 10.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 10.01.2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RS232_TX_VHDL is
Port(SEND_BYTE : in std_logic_vector (7 downto 0); --Eingangsvariable, zu Daten Input, 8 bit
SEND : in std_logic; --Eingangsvariable, Byte OK
TX : out std_logic; --Ausgangsvariable, Transmit Bit
READY: out std_logic; --Ausgangsvariable, bereit zum Senden
CLK : in std_logic; --Taktvariable
CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
DISPL_COUNT : in std_logic; --Eingangsvariable, Counter anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_RS232_TX_VHDL;
architecture Behavioral of CTRL_RS232_TX_VHDL is
type TYPE_STATE is
(ST_TX_00, --Zustaende CTRL_RS232_TX
ST_TX_01,
ST_TX_02,
ST_TX_03,
ST_TX_04,
ST_TX_05,
ST_TX_06,
ST_TX_07,
ST_TX_08,
ST_TX_09,
ST_TX_10,
ST_TX_11);
signal SV : TYPE_STATE; --Zustandsvariable
signal n_SV: TYPE_STATE; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE; --Zustandsvariable, Ausgang Master
signal not_CLK : std_logic; --negierte Taktvariable
signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal SEND_BYTE_S : std_logic_vector (7 downto 0); --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal SEND_S : std_logic; --Eingangsvariable, Zwischengespeichern im Eingangsregister
signal COUNT : std_logic_vector (15 downto 0); --Zaehler, Vektor, 16 Bit
signal n_COUNT : std_logic_vector (15 downto 0); --Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_M : std_logic_vector (15 downto 0); --Zaehler, Ausgang Master, Vektor, 16 Bit
signal CNT01 : std_logic_vector (15 downto 0);
signal CNT02 : std_logic_vector (15 downto 0);
signal CNT03 : std_logic_vector (15 downto 0);
signal CNT04 : std_logic_vector (15 downto 0);
signal CNT05 : std_logic_vector (15 downto 0);
signal CNT06 : std_logic_vector (15 downto 0);
signal CNT07 : std_logic_vector (15 downto 0);
signal CNT08 : std_logic_vector (15 downto 0);
signal CNT09 : std_logic_vector (15 downto 0);
signal CNT10 : std_logic_vector (15 downto 0);
--Konstanten, lang
constant long_CNT01 : std_logic_vector := x"1458"; --16 Bit
constant long_CNT02 : std_logic_vector := x"2C98"; --usw.
constant long_CNT03 : std_logic_vector := x"3D08";
constant long_CNT04 : std_logic_vector := x"5160";
constant long_CNT05 : std_logic_vector := x"65B8";
constant long_CNT06 : std_logic_vector := x"7A10";
constant long_CNT07 : std_logic_vector := x"8E68";
constant long_CNT08 : std_logic_vector := x"A2C0";
constant long_CNT09 : std_logic_vector := x"B718";
constant long_CNT10 : std_logic_vector := x"CB70";
--Konstanten, kurz
constant short_CNT01 : std_logic_vector := x"0003"; --3
constant short_CNT02 : std_logic_vector := x"0006"; --6
constant short_CNT03 : std_logic_vector := x"0009"; --9
constant short_CNT04 : std_logic_vector := x"000C"; --12
constant short_CNT05 : std_logic_vector := x"000F"; --15
constant short_CNT06 : std_logic_vector := x"0012"; --18
constant short_CNT07 : std_logic_vector := x"0015"; --21
constant short_CNT08 : std_logic_vector := x"0018"; --24
constant short_CNT09 : std_logic_vector := x"001B"; --27
constant short_CNT10 : std_logic_vector := x"001E"; --30
begin
NOT_CLK_PROC: process (CLK) --negieren Taktvariable
begin
not_CLK <= not CLK;
end process;
NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
begin
not_CLK_IO <= not CLK_IO;
end process;
IREG_PROC: process (not_CLK_IO) --Eingangsregister
begin
if (not_CLK_IO'event and not_CLK_IO = '1') --Eingangsregister
then SEND_BYTE_S <= SEND_BYTE;
SEND_S <= SEND;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TX_00;
else
if (CLK'event and CLK = '1')
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_M <= n_COUNT;
else SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, not_CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_TX_00;
else
if (not_CLK'event and not_CLK = '1')
then SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
CTRL_RS232_TX_PROC:process (SV, COUNT, SEND_S, SEND_BYTE_S, CNT01, CNT02, CNT03, CNT04, CNT05, CNT06, CNT07, CNT08, CNT09, CNT10) --Daten über RS232 senden
begin
case SV is
when ST_TX_00 =>
if (SEND_S = '1')
then
--TX01
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --Zustandsübergang
else
--TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '1'; --Bereit zum Senden
n_SV <= ST_TX_00; --bleibt im gleichen Zustand
end if;
when ST_TX_01 =>
if (COUNT = CNT01) --Zaehler = 5208
then
--TX03
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --Zustandsübergang
else
--TX02
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '0'; --Startbit
READY <= '0';
n_SV <= ST_TX_01; --bleibt im gleichen Zustand
end if;
when ST_TX_02 =>
if (COUNT = CNT02) --Zaehler = 11416
then
--TX05
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --Zustandsübergang
else
--TX04
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(0); --Bit 0
READY <= '0';
n_SV <= ST_TX_02; --bleibt im gleichen Zustand
end if;
when ST_TX_03 =>
if (COUNT = CNT03) --Zaehler = 15624
then
--TX07
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --Zustandsübergang
else
--TX06
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(1); --Bit 1
READY <= '0';
n_SV <= ST_TX_03; --bleibt im gleichen Zustand
end if;
when ST_TX_04 =>
if (COUNT = CNT04) --Zaehler = 20832
then
--TX09
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --Zustandsübergang
else
--TX08
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(2); --Bit 2
READY <= '0';
n_SV <= ST_TX_04; --bleibt im gleichen Zustand
end if;
when ST_TX_05 =>
if (COUNT = CNT05) --Zaehler = 26040
then
--TX11
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --Zustandsübergang
else
--TX10
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(3); --Bit 3
READY <= '0';
n_SV <= ST_TX_05; --bleibt im gleichen Zustand
end if;
when ST_TX_06 =>
if (COUNT = CNT06) --Zaehler = 31248
then
--TX13
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --Zustandsübergang
else
--TX12
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(4); --Bit 4
READY <= '0';
n_SV <= ST_TX_06; --bleibt im gleichen Zustand
end if;
when ST_TX_07 =>
if (COUNT = CNT07) --Zaehler = 36456
then
--TX15
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --Zustandsübergang
else
--TX14
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(5); --Bit 5
READY <= '0';
n_SV <= ST_TX_07; --bleibt im gleichen Zustand
end if;
when ST_TX_08 =>
if (COUNT = CNT08) --Zaehler = 41664
then
--TX17
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --Zustandsübergang
else
--TX16
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(6); --Bit 6
READY <= '0';
n_SV <= ST_TX_08; --bleibt im gleichen Zustand
end if;
when ST_TX_09 =>
if (COUNT = CNT09) --Zaehler = 46872
then
--TX19
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --Zustandsübergang
else
--TX18
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= SEND_BYTE_S(7); --Bit 7
READY <= '0';
n_SV <= ST_TX_09; --bleibt im gleichen Zustand
end if;
when ST_TX_10 =>
if (COUNT = CNT10) --Zaehler = 52080
then
--TX21
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --Zustandsübergang
else
--TX20
n_COUNT <= COUNT+1; -- Zaehler erhoehen
TX <= '1'; --Stoppbit
READY <= '0';
n_SV <= ST_TX_10; --bleibt im gleichen Zustand
end if;
when ST_TX_11 =>
if (SEND_S = '0') -- Wenn SEND=0 dann warten auf SEND sonst Idle senden
then
--TX00
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '1';--Bereit zum Senden
n_SV <= ST_TX_00; --Zustandsübergang
else
--TX22
n_COUNT <= x"0000"; -- Zaehler neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_11; --bleibt im gleichen Zustand
end if;
when others =>
-- TX00
n_COUNT <= x"0000"; -- kleiner Zaehler Neustart
TX <= '1'; --Idle
READY <= '0';
n_SV <= ST_TX_00; --Zustandsübergang
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, DISPL_COUNT, STATE_SV, STATE_n_SV,COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
--aktuellen Zustand anzeigen
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT ='0')
then --Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
else --Zähler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
end if;
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNT01 <= long_CNT01;
CNT02 <= long_CNT02;
CNT03 <= long_CNT03;
CNT04 <= long_CNT04;
CNT05 <= long_CNT05;
CNT06 <= long_CNT06;
CNT07 <= long_CNT07;
CNT08 <= long_CNT08;
CNT09 <= long_CNT09;
CNT10 <= long_CNT10;
else
--kurze Werte
CNT01 <= short_CNT01;
CNT02 <= short_CNT02;
CNT03 <= short_CNT03;
CNT04 <= short_CNT04;
CNT05 <= short_CNT05;
CNT06 <= short_CNT06;
CNT07 <= short_CNT07;
CNT08 <= short_CNT08;
CNT09 <= short_CNT09;
CNT10 <= short_CNT10;
end if;
end process;
end Behavioral;
| gpl-2.0 | 153cbb1b915da6f40f3709a6cddf3240 | 0.563681 | 3.070159 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/ethlib/greth_rx.vhd | 1 | 11,630 | ------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library commonlib;
use commonlib.types_common.all;
library ethlib;
use ethlib.types_eth.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
v.mcasthash := (others => '0');
v.dataout := (others => '0');
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
| apache-2.0 | 92ff53d0f656b86a53983c6449e053d8 | 0.49957 | 3.244978 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/fifo_generator_top.vhd | 19 | 34,705 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | 140a3ce745129f5482e9987e2997203e | 0.945541 | 1.833915 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/mem/syncram_2p_inferred.vhd | 1 | 2,121 | -----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Synchronous 2-port ram, common clock
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity syncram_2p_inferred is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture arch_syncram_2p_inferred of syncram_2p_inferred is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
--! This fuinction just to check with C++ reference model. Can be removed.
impure function init_ram(file_name : in string) return dregtype is
variable temp_mem : dregtype;
begin
for i in 0 to (2**abits - 1) loop
if dbits = 64 then
temp_mem(i) := X"0000000000000000";--X"CCCCCCCC";
elsif dbits = 32 then
temp_mem(i) := X"00000000";--X"CCCCCCCC";
else
temp_mem(i) := X"0000";--X"CCCC";
end if;
end loop;
return temp_mem;
end function;
signal rfd : dregtype := init_ram("");
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then
q <= rfd(conv_integer(rdaddress));
end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
| apache-2.0 | d1780766f11866948f78901a56174a25 | 0.58133 | 3.7875 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/misclib/dcom_jtag.vhd | 1 | 7,416 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
entity dcom_jtag is
generic (
id : std_logic_vector(31 downto 0) := X"01040093");
port (
rst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapi_tdo : in std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(4 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic
);
end;
architecture rtl of dcom_jtag is
type ltap_out_type is record
tck : std_ulogic;
tdi : std_ulogic;
inst : std_logic_vector(4 downto 0);
asel : std_ulogic;
dsel : std_ulogic;
reset : std_ulogic;
capt : std_ulogic;
shift : std_ulogic;
upd : std_ulogic;
end record;
constant IDCODE : std_logic_vector(4 downto 0) := "00001";
constant DTMCS : std_logic_vector(4 downto 0) := "10000";
constant DMI_ACCESS : std_logic_vector(4 downto 0) := "10001";
type state_type is (test_rst, run_idle, select_dr, capture_dr, shift_dr, exit1_dr,
pause_dr, exit2_dr, update_dr, select_ir, capture_ir, shift_ir,
exit1_ir, pause_ir, exit2_ir, update_ir);
type reg_type is record
state : state_type;
inst : std_logic_vector(4 downto 0);
shft : std_logic_vector(31 downto 0);
tdo : std_ulogic;
sel_user1 : std_logic;
sel_user2 : std_logic;
end record;
signal r, rin : reg_type;
begin
comb : process(tck, tms, tdi, tapi_tdo, r)
variable v : reg_type;
variable vtapo : ltap_out_type;
variable vtdo : std_ulogic;
begin
v := r;
vtapo.tck := tck;
vtapo.reset := '0';
vtapo.tdi := tdi;
vtapo.inst := (others => '0');
vtapo.inst(4 downto 0) := r.inst;
vtapo.capt := '0';
vtapo.upd := '0';
vtapo.shift := '0';
vtapo.asel := '0';
vtapo.dsel := '0';
if r.inst /= DMI_ACCESS then
v.tdo := r.shft(0);
else
v.tdo := tapi_tdo;
end if;
--if (r.inst = IDCODE_I) or (r.inst = BYPASS) then v.tdo := r.shft(0);
--else v.tdo := tapi_tdo; end if;
case r.state is
when test_rst => if tms = '0' then v.state := run_idle; end if;
when run_idle => if tms = '1' then v.state := select_dr; end if;
when select_dr => if tms = '0' then v.state := capture_dr; else v.state := select_ir; end if;
when capture_dr => if tms = '0' then v.state := shift_dr; else v.state := exit1_dr; end if;
when shift_dr => if tms = '1' then v.state := exit1_dr; end if;
when exit1_dr => if tms = '0' then v.state := pause_dr; else v.state := update_dr; end if;
when pause_dr => if tms = '1' then v.state := exit2_dr; end if;
when exit2_dr => if tms = '0' then v.state := shift_dr; else v.state := update_dr; end if;
when update_dr => if tms = '0' then v.state := run_idle; else v.state := select_dr; end if;
when select_ir => if tms = '0' then v.state := capture_ir; else v.state := test_rst; end if;
when capture_ir => if tms = '0' then v.state := shift_ir; else v.state := exit1_ir; end if;
when shift_ir => if tms = '1' then v.state := exit1_ir; end if;
when exit1_ir => if tms = '0' then v.state := pause_ir; else v.state := update_ir; end if;
when pause_ir => if tms = '1' then v.state := exit2_ir; end if;
when exit2_ir => if tms = '0' then v.state := shift_ir; else v.state := update_ir; end if;
when update_ir => if tms = '0' then v.state := run_idle; else v.state := select_dr; end if;
end case;
case r.state is
when test_rst =>
vtapo.reset := '1';
v.inst := IDCODE;
when capture_dr =>
vtapo.capt := '1';
if r.inst = IDCODE then
v.shft := id;
elsif r.inst = DTMCS then
v.shft := (others => '0');
v.shft(14 downto 12) := "001"; -- idle: 1=Enter Run-Test/Idle and leave it immediately
v.shft(11 downto 10) := "00"; -- dmstat: TODO
v.shft(9 downto 4) := conv_std_logic_vector(7, 6); -- abits: 7 bits dmi address width
v.shft(3 downto 0) := X"1"; -- version: 1=spec 0.13
elsif r.inst = DMI_ACCESS then
v.sel_user1 := '1';
else
v.shft(0) := '0'; -- BYPASS
end if;
-- if r.inst = BYPASS then v.shft(0) := '0'; end if;
-- if r.inst = IDCODE_I then v.shft := id; end if;
when shift_dr =>
vtapo.shift := '1';
if (r.inst = IDCODE) or (r.inst = DTMCS) then
v.shft(31 downto 0) := tdi & r.shft(31 downto 1);
else
v.shft(0) := tdi; -- BYPASS
end if;
-- if r.inst = BYPASS then v.shft(0) := tdi; end if;
-- if r.inst = IDCODE_I then v.shft := tdi & r.shft(31 downto 1); end if;
when update_dr =>
vtapo.upd := '1';
v.sel_user1 := '0';
v.sel_user2 := '0';
when capture_ir =>
v.shft(4 downto 2) := r.inst(4 downto 2);
v.shft(1 downto 0) := "01";
v.sel_user1 := '0';
v.sel_user2 := '0';
when shift_ir =>
v.shft(4 downto 0) := tdi & r.shft(4 downto 1);
when update_ir =>
v.inst := r.shft(4 downto 0);
when others =>
end case;
rin <= v;
tdo <= r.tdo;
tapo_tck <= tck;
--if (r.sel_user1 or r.sel_user2)='1' then tapo_tck <= tck;
--else tapo_tck <= '1'; end if;
tapo_tdi <= tdi;
tapo_inst <= vtapo.inst;
tapo_rst <= vtapo.reset;
tapo_capt <= vtapo.capt;
tapo_shft <= vtapo.shift;
tapo_upd <= vtapo.upd;
tapo_xsel1 <= r.sel_user1;
tapo_xsel2 <= r.sel_user2;
end process;
posreg : process(tck, rst) begin
if rising_edge(tck) then
r.state <= rin.state;
r.shft <= rin.shft;
end if;
if rst = '0' then
r.state <= test_rst;
r.shft <= id;
end if;
end process;
negreg : process(tck, rst) begin
if falling_edge(tck) then
r.inst <= rin.inst;
r.tdo <= rin.tdo;
r.sel_user1 <= rin.sel_user1;
r.sel_user2 <= rin.sel_user2;
end if;
if rst = '0' then
r.inst <= IDCODE;
r.sel_user1 <= '0';
r.sel_user2 <= '0';
end if;
end process;
end;
| apache-2.0 | ce8b539bc8ab135d81276814f0b7cf10 | 0.532632 | 3.137056 | false | false | false | false |
codepainters/vhdl-utils | tests/t_i2c_slave.vhd | 1 | 4,525 | --------------------------------------------------------------------------------
-- Copyright (c) 2015, Przemyslaw Wegrzyn <[email protected]>
-- This file is distributed under the Modified BSD License.
--
-- Testbench for I2C slave interface
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t_i2c_slave is
end t_i2c_slave;
architecture behavior of t_i2c_slave is
component i2c_slave
generic (
address: std_logic_vector(6 downto 0));
port(
clk : in std_logic;
-- I2C interface
scl : inout std_logic;
sda : inout std_logic;
-- received data interface
wr_data : out std_logic_vector(7 downto 0);
wr_data_valid : out std_logic;
wr_data_ack : in std_logic;
-- transmitted data interface
rd_data : in std_logic_vector(7 downto 0);
rd_data_req : out std_logic;
rd_data_valid : in std_logic);
end component;
-- clock
signal clk : std_logic := '0';
constant clk_period : time := 20 ns;
signal clk_enabled : boolean := true;
-- I2C interface
signal scl : std_logic;
signal sda : std_logic;
signal scl_out : std_logic := '1';
signal sda_out : std_logic := '1';
-- RX interface
signal wr_data : std_logic_vector(7 downto 0);
signal wr_data_valid : std_logic;
signal wr_data_ack : std_logic := '0';
-- TX interface
signal rd_data : std_logic_vector(7 downto 0) := (others => '0');
signal rd_data_req : std_logic;
signal rd_data_valid : std_logic := '0';
-- 400kHz I2C clock
constant i2c_clk_period : time := 2.5 us;
procedure i2c_start(signal sda : out std_logic; signal scl : out std_logic) is
begin
sda <= '1';
scl <= '1';
wait for i2c_clk_period / 2;
sda <= '0';
wait for i2c_clk_period / 2;
scl <= '0';
end procedure;
procedure i2c_stop(signal sda : out std_logic; signal scl : out std_logic) is
begin
sda <= '0';
scl <= '0';
wait for i2c_clk_period / 2;
scl <= '1';
wait for i2c_clk_period / 2;
sda <= '1';
end procedure;
procedure i2c_clock_pulse(signal sda : out std_logic; signal scl : out std_logic) is
begin
scl <= '0';
wait for i2c_clk_period / 4;
scl <= '1';
wait for i2c_clk_period / 2;
scl <= '0';
wait for i2c_clk_period / 4;
end procedure;
procedure i2c_send_addr(signal sda : out std_logic; signal scl : out std_logic;
address : std_logic_vector(6 downto 0); wr : boolean) is
begin
for i in address'high downto address'low loop
sda <= address(i);
i2c_clock_pulse(sda, scl);
end loop;
if wr then
sda <= '1';
else
sda <= '0';
end if;
i2c_clock_pulse(sda, scl);
end procedure;
procedure i2c_ack(signal sda : out std_logic; signal scl : out std_logic;
signal sda_in : in std_logic; ack : out boolean) is
begin
sda <= '1';
scl <= '0';
wait for i2c_clk_period / 4;
scl <= '1';
ack := (sda_in = '0');
wait for i2c_clk_period / 2;
scl <= '0';
wait for i2c_clk_period / 4;
end procedure;
begin
uut: i2c_slave
generic map (address => "1010110")
port map (
clk => clk,
scl => scl,
sda => sda,
wr_data => wr_data,
wr_data_valid => wr_data_valid,
wr_data_ack => wr_data_ack,
rd_data => rd_data,
rd_data_req => rd_data_req,
rd_data_valid => rd_data_valid);
-- clock generator
clk <= not clk after clk_period / 2 when clk_enabled = true else '0';
-- I2C drivers, note: weak H emulates pull-ups
scl <= 'H' when scl_out = '1' else '0';
sda <= 'H' when sda_out = '1' else '0';
stimulation : process is
variable ack : boolean;
begin
-- write with valid address
i2c_start(sda_out, scl_out);
i2c_send_addr(sda_out, scl_out, B"101_0110", true);
i2c_ack(sda_out, scl_out, sda, ack);
i2c_stop(sda_out, scl_out);
assert ack report "test failed - no ACK" severity error;
wait for 2 * i2c_clk_period;
clk_enabled <= false;
wait until false;
end process;
end;
| bsd-2-clause | f7314c5f51c6f23a051d3152d771a441 | 0.520221 | 3.513199 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/techmap/bufg/types_buf.vhd | 1 | 4,315 | ----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_buf package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Technology constants definition.
library techmap;
use techmap.gencomp.all;
--! @brief Declaration of 'virtual' Buffers components.
package types_buf is
--! @brief Clock signals multiplexer.
--! @param[in] tech Technology selector.
--! @param[out] O Output clock signal.
--! @param[in] I1 Input clock signal 1.
--! @param[in] I2 Input clock signal 2.
--! @param[in] S Input signals switcher:
--! 0 = I1; 1 = I2.
component bufgmux_tech is
generic (
tech : integer := 0;
rf_frontend_ena : boolean := false
);
port (
O : out std_ulogic;
I1 : in std_ulogic;
I2 : in std_ulogic;
S : in std_ulogic);
end component;
--! @brief Input PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered signal.
--! @param[in] i Input unbuffered signal.
component ibuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input clocking PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output buffered clock signal.
--! @param[in] i Input unbuffered clock signal.
component ibufg_tech is generic (tech : integer := 0);
port (
O : out std_ulogic;
I : in std_ulogic
);
end component;
--! @brief Output PAD buffer.
--! @details This buffer makes sense only for ASIC implementation.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal directly connected to the ASIC output pin.
--! @param[in] i Input signal.
component obuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
i : in std_logic
);
end component;
--! @brief Input/Output PAD buffer.
--! @param[in] tech Technology selector.
--! @param[out] o Output signal
--! @param[inout] io Bi-directional signal.
--! @param[in] i Input signal
--! @param[in] t Controlling signal: 0 = in; 1=out
--!
--! Example:
--! @code
--! entity foo is port (
--! io_gpio : inout std_logic
--! )
--! end foo;
--! architecture rtl of foo is
--! signal ob_gpio_direction : std_logic;
--! signal ob_gpio_opins : std_logic;
--! signal ib_gpio_ipins : std_logic;
--! ...
--! begin
--! ob_gpio_direction <= '1';
--!
--! iob : iobuf_tech generic map(kintex7)
--! port map (ib_gpio_ipins, io_gpio, ob_gpio_opins, ob_gpio_direction);
--!
--! reg : process(clk, nrst) begin
--! if rising_edge(clk) then
--! reg1 <= ib_gpio_ipins;
--! ob_gpio_opins <= reg2;
--! end;
--! end process;
--! end;
--! @endcode
component iobuf_tech is generic (generic_tech : integer := 0);
port (
o : out std_logic;
io : inout std_logic;
i : in std_logic;
t : in std_logic
);
end component;
--! @brief Gigabit buffer with differential inputs.
--! @param[in] gclk_p Differential clock input.
--! @param[in] gclk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component igdsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
gclk_p : in std_logic;
gclk_n : in std_logic;
o_clk : out std_logic
);
end component;
--! @brief Input buffer with differential inputs.
--! @param[in] clk_p Differential clock input.
--! @param[in] clk_n Differential clock inversed input.
--! @param[out] o_clk Unbuffered clock output.
component idsbuf_tech is
generic (
generic_tech : integer := 0
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
o_clk : out std_logic
);
end component;
end;
| apache-2.0 | 9decba5630ce27574b3f4ed2ee89b2d2 | 0.565469 | 3.707045 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_pe_sshft.vhd | 19 | 17,676 | `protect begin_protected
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`protect end_protected
| bsd-2-clause | 57ea7383db35549e78ce0fd13e1beaa9 | 0.937938 | 1.859066 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/prj/zynq/zynq_top.vhd | 1 | 12,048 | --!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
--! Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
--! Data transformation and math functions library
library commonlib;
use commonlib.types_common.all;
--! Technology definition library.
library techmap;
--! Technology constants definition.
use techmap.gencomp.all;
--! "Virtual" PLL declaration.
use techmap.types_pll.all;
--! "Virtual" buffers declaration.
use techmap.types_buf.all;
--! Top-level implementaion library
library work;
--! Target dependable configuration: RTL, FPGA or ASIC.
use work.config_target.all;
--! Warning: this project wasn't verified on real FPGA (2018 Nov 18). No board is available.
entity zynq_top is port
(
io_gpio : inout std_logic_vector(11 downto 0);
--! UART1 signals:
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
--! UART2 (TAP) signals:
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
--! JTAG
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic
);
end zynq_top;
architecture arch_zynq_top of zynq_top is
component riscv_soc is port (
i_rst : in std_logic;
i_clk : in std_logic;
--! GPIO.
i_gpio : in std_logic_vector(11 downto 0);
o_gpio : out std_logic_vector(11 downto 0);
o_gpio_dir : out std_logic_vector(11 downto 0);
--! GPTimers
o_pwm : out std_logic_vector(1 downto 0);
--! JTAG signals:
i_jtag_tck : in std_logic;
i_jtag_ntrst : in std_logic;
i_jtag_tms : in std_logic;
i_jtag_tdi : in std_logic;
o_jtag_tdo : out std_logic;
o_jtag_vref : out std_logic;
--! UART1 signals:
i_uart1_ctsn : in std_logic;
i_uart1_rd : in std_logic;
o_uart1_td : out std_logic;
o_uart1_rtsn : out std_logic;
--! UART2 (debug port) signals:
i_uart2_ctsn : in std_logic;
i_uart2_rd : in std_logic;
o_uart2_td : out std_logic;
o_uart2_rtsn : out std_logic;
--! SPI Flash
i_flash_si : in std_logic;
o_flash_so : out std_logic;
o_flash_sck : out std_logic;
o_flash_csn : out std_logic;
o_flash_wpn : out std_logic;
o_flash_holdn : out std_logic;
o_flash_reset : out std_logic;
--! OTP Memory
i_otp_d : in std_logic_vector(15 downto 0);
o_otp_d : out std_logic_vector(15 downto 0);
o_otp_a : out std_logic_vector(11 downto 0);
o_otp_we : out std_logic;
o_otp_re : out std_logic;
--! Ethernet MAC PHY interface signals
i_etx_clk : in std_ulogic;
i_erx_clk : in std_ulogic;
i_erxd : in std_logic_vector(3 downto 0);
i_erx_dv : in std_ulogic;
i_erx_er : in std_ulogic;
i_erx_col : in std_ulogic;
i_erx_crs : in std_ulogic;
i_emdint : in std_ulogic;
o_etxd : out std_logic_vector(3 downto 0);
o_etx_en : out std_ulogic;
o_etx_er : out std_ulogic;
o_emdc : out std_ulogic;
i_eth_mdio : in std_logic;
o_eth_mdio : out std_logic;
o_eth_mdio_oe : out std_logic;
i_eth_gtx_clk : in std_logic;
i_eth_gtx_clk_90 : in std_logic;
o_erstn : out std_ulogic;
-- GNSS Sub-system signals:
i_clk_adc : in std_logic;
i_gps_I : in std_logic_vector(1 downto 0);
i_gps_Q : in std_logic_vector(1 downto 0);
i_glo_I : in std_logic_vector(1 downto 0);
i_glo_Q : in std_logic_vector(1 downto 0);
o_pps : out std_logic;
i_gps_ld : in std_logic;
i_glo_ld : in std_logic;
o_max_sclk : out std_logic;
o_max_sdata : out std_logic;
o_max_ncs : out std_logic_vector(1 downto 0);
i_antext_stat : in std_logic;
i_antext_detect : in std_logic;
o_antext_ena : out std_logic;
o_antint_contr : out std_logic
);
end component;
COMPONENT processing_system7_0
PORT (
M_AXI_GP0_ARVALID : OUT STD_LOGIC;
M_AXI_GP0_AWVALID : OUT STD_LOGIC;
M_AXI_GP0_BREADY : OUT STD_LOGIC;
M_AXI_GP0_RREADY : OUT STD_LOGIC;
M_AXI_GP0_WLAST : OUT STD_LOGIC;
M_AXI_GP0_WVALID : OUT STD_LOGIC;
M_AXI_GP0_ARID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_AWID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_WID : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWLOCK : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_GP0_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_GP0_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWLEN : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_GP0_ACLK : IN STD_LOGIC;
M_AXI_GP0_ARREADY : IN STD_LOGIC;
M_AXI_GP0_AWREADY : IN STD_LOGIC;
M_AXI_GP0_BVALID : IN STD_LOGIC;
M_AXI_GP0_RLAST : IN STD_LOGIC;
M_AXI_GP0_RVALID : IN STD_LOGIC;
M_AXI_GP0_WREADY : IN STD_LOGIC;
M_AXI_GP0_BID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_RID : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
M_AXI_GP0_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_GP0_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
FCLK_CLK0 : OUT STD_LOGIC;
FCLK_RESET0_N : OUT STD_LOGIC;
MIO : INOUT STD_LOGIC_VECTOR(53 DOWNTO 0);
DDR_CAS_n : INOUT STD_LOGIC;
DDR_CKE : INOUT STD_LOGIC;
DDR_Clk_n : INOUT STD_LOGIC;
DDR_Clk : INOUT STD_LOGIC;
DDR_CS_n : INOUT STD_LOGIC;
DDR_DRSTB : INOUT STD_LOGIC;
DDR_ODT : INOUT STD_LOGIC;
DDR_RAS_n : INOUT STD_LOGIC;
DDR_WEB : INOUT STD_LOGIC;
DDR_BankAddr : INOUT STD_LOGIC_VECTOR(2 DOWNTO 0);
DDR_Addr : INOUT STD_LOGIC_VECTOR(14 DOWNTO 0);
DDR_VRN : INOUT STD_LOGIC;
DDR_VRP : INOUT STD_LOGIC;
DDR_DM : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
DDR_DQS_n : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DDR_DQS : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0);
PS_SRSTB : INOUT STD_LOGIC;
PS_CLK : INOUT STD_LOGIC;
PS_PORB : INOUT STD_LOGIC
);
END COMPONENT;
signal FCLK_RESET0_N : std_logic;
signal FCLK_RESET0 : std_logic;
signal locked : std_logic;
signal w_ext_clk : std_logic;
signal w_ext_clk_buf : std_logic;
signal w_pll_clk : std_logic;
signal w_pll_lock : std_logic;
signal w_rst : std_logic;
signal ob_gpio_direction : std_logic_vector(11 downto 0);
signal ob_gpio_opins : std_logic_vector(11 downto 0);
signal ib_gpio_ipins : std_logic_vector(11 downto 0);
begin
procsys0 : processing_system7_0
PORT MAP (
M_AXI_GP0_ARVALID => open,
M_AXI_GP0_AWVALID => open,
M_AXI_GP0_BREADY => open,
M_AXI_GP0_RREADY => open,
M_AXI_GP0_WLAST => open,
M_AXI_GP0_WVALID => open,
M_AXI_GP0_ARID => open,
M_AXI_GP0_AWID => open,
M_AXI_GP0_WID => open,
M_AXI_GP0_ARBURST => open,
M_AXI_GP0_ARLOCK => open,
M_AXI_GP0_ARSIZE => open,
M_AXI_GP0_AWBURST => open,
M_AXI_GP0_AWLOCK => open,
M_AXI_GP0_AWSIZE => open,
M_AXI_GP0_ARPROT => open,
M_AXI_GP0_AWPROT => open,
M_AXI_GP0_ARADDR => open,
M_AXI_GP0_AWADDR => open,
M_AXI_GP0_WDATA => open,
M_AXI_GP0_ARCACHE => open,
M_AXI_GP0_ARLEN => open,
M_AXI_GP0_ARQOS => open,
M_AXI_GP0_AWCACHE => open,
M_AXI_GP0_AWLEN => open,
M_AXI_GP0_AWQOS => open,
M_AXI_GP0_WSTRB => open,
M_AXI_GP0_ACLK => w_ext_clk,
M_AXI_GP0_ARREADY => '1',
M_AXI_GP0_AWREADY => '1',
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WREADY => '1',
M_AXI_GP0_BID => X"000",
M_AXI_GP0_RID => X"000",
M_AXI_GP0_BRESP => "00",
M_AXI_GP0_RRESP => "00",
M_AXI_GP0_RDATA => X"00000000",
FCLK_CLK0 => w_ext_clk,
FCLK_RESET0_N => FCLK_RESET0_N,
MIO => open,
DDR_CAS_n => open,
DDR_CKE => open,
DDR_Clk_n => open,
DDR_Clk => open,
DDR_CS_n => open,
DDR_DRSTB => open,
DDR_ODT => open,
DDR_RAS_n => open,
DDR_WEB => open,
DDR_BankAddr => open,
DDR_Addr => open,
DDR_VRN => open,
DDR_VRP => open,
DDR_DM => open,
DDR_DQ => open,
DDR_DQS_n => open,
DDR_DQS => open,
PS_SRSTB => open,
PS_CLK => open,
PS_PORB => open
);
FCLK_RESET0 <= not FCLK_RESET0_N;
buf0 : BUFG port map (
I => w_ext_clk,
O => w_ext_clk_buf
);
gpiox : for i in 0 to 11 generate
iob0 : iobuf_tech generic map(zynq7000)
port map (ib_gpio_ipins(i), io_gpio(i), ob_gpio_opins(i), ob_gpio_direction(i));
end generate;
pll0 : SysPLL_tech generic map (
tech => zynq7000
) port map (
i_reset => FCLK_RESET0,
i_clk_tcxo => w_ext_clk_buf,
o_clk_bus => w_pll_clk,
o_locked => w_pll_lock
);
w_rst <= w_pll_lock;
soc0 : riscv_soc port map (
i_rst => w_rst,
i_clk => w_pll_lock,
--! GPIO.
i_gpio => ib_gpio_ipins,
o_gpio => ob_gpio_opins,
o_gpio_dir => ob_gpio_direction,
--! GPTimers
o_pwm => open,
--! JTAG signals:
i_jtag_tck => i_jtag_tck,
i_jtag_ntrst => i_jtag_ntrst,
i_jtag_tms => i_jtag_tms,
i_jtag_tdi => i_jtag_tdi,
o_jtag_tdo => o_jtag_tdo,
o_jtag_vref => o_jtag_vref,
--! UART1 signals:
i_uart1_ctsn => '0',
i_uart1_rd => i_uart1_rd,
o_uart1_td => o_uart1_td,
o_uart1_rtsn => open,
--! UART2 (debug port) signals:
i_uart2_ctsn => '0',
i_uart2_rd => i_uart2_rd,
o_uart2_td => o_uart2_td,
o_uart2_rtsn => open,
--! SPI Flash
i_flash_si => '0',
o_flash_so => open,
o_flash_sck => open,
o_flash_csn => open,
o_flash_wpn => open,
o_flash_holdn => open,
o_flash_reset => open,
--! OTP Memory
i_otp_d => X"0000",
o_otp_d => open,
o_otp_a => open,
o_otp_we => open,
o_otp_re => open,
--! Ethernet MAC PHY interface signals
i_etx_clk => '0',
i_erx_clk => '0',
i_erxd => X"0",
i_erx_dv => '0',
i_erx_er => '0',
i_erx_col => '0',
i_erx_crs => '0',
i_emdint => '0',
o_etxd => open,
o_etx_en => open,
o_etx_er => open,
o_emdc => open,
i_eth_mdio => '0',
o_eth_mdio => open,
o_eth_mdio_oe => open,
i_eth_gtx_clk => '0',
i_eth_gtx_clk_90 => '0',
o_erstn => open,
-- GNSS Sub-system signals:
i_clk_adc => '0',
i_gps_I => "00",
i_gps_Q => "00",
i_glo_I => "00",
i_glo_Q => "00",
o_pps => open,
i_gps_ld => '0',
i_glo_ld => '0',
o_max_sclk => open,
o_max_sdata => open,
o_max_ncs => open,
i_antext_stat => '0',
i_antext_detect => '0',
o_antext_ena => open,
o_antint_contr => open
);
end arch_zynq_top;
| apache-2.0 | b49043c3fd41c1c2858e7af5b9c2fdd5 | 0.591799 | 2.787598 | false | false | false | false |
szanni/aeshw | zybo-base/zybo_bsd/zybo_bsd.srcs/sources_1/bd/system/ip/system_auto_pc_5/fifo_generator_v11_0/ramfifo/rd_dc_fwft_ext_as.vhd | 19 | 12,811 | `protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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T1kWm6bsuw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7744)
`protect data_block
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`protect end_protected
| bsd-2-clause | 0570fe2c59467628daf153ccb52cfe95 | 0.933885 | 1.884248 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_rst_module.vhd | 1 | 24,263 | -- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_rst_module.vhd
-- Description: This entity is the top level reset module entity for the
-- AXI VDMA core.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_10;
use axi_dma_v7_1_10.axi_dma_pkg.all;
library lib_cdc_v1_0_2;
-------------------------------------------------------------------------------
entity axi_dma_rst_module is
generic(
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_INCLUDE_S2MM : integer range 0 to 1 := 1;
-- Include or exclude S2MM primary data path
-- 0 = Exclude S2MM primary data path
-- 1 = Include S2MM primary data path
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000;
-- Primary clock frequency in hertz
C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000
-- Scatter Gather clock frequency in hertz
);
port (
-----------------------------------------------------------------------
-- Clock Sources
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ;
m_axi_sg_aclk : in std_logic ; --
m_axi_mm2s_aclk : in std_logic ; --
m_axi_s2mm_aclk : in std_logic ; --
--
----------------------------------------------------------------------- --
-- Hard Reset --
----------------------------------------------------------------------- --
axi_resetn : in std_logic ; --
----------------------------------------------------------------------- --
-- Soft Reset --
----------------------------------------------------------------------- --
soft_reset : in std_logic ; --
soft_reset_clr : out std_logic := '0' ; --
--
----------------------------------------------------------------------- --
-- MM2S Soft Reset Support --
----------------------------------------------------------------------- --
mm2s_all_idle : in std_logic ; --
mm2s_stop : in std_logic ; --
mm2s_halt : out std_logic := '0' ; --
mm2s_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- S2MM Soft Reset Support --
----------------------------------------------------------------------- --
s2mm_all_idle : in std_logic ; --
s2mm_stop : in std_logic ; --
s2mm_halt : out std_logic := '0' ; --
s2mm_halt_cmplt : in std_logic ; --
--
----------------------------------------------------------------------- --
-- MM2S Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_mm2s_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_mm2s_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
mm2s_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
mm2s_cntrl_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
mm2s_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
mm2s_prmry_resetn : out std_logic := '1' ; --
--
--
----------------------------------------------------------------------- --
-- S2MM Distributed Reset Out --
----------------------------------------------------------------------- --
-- AXI DataMover Primary Reset (Raw) --
dm_s2mm_prmry_resetn : out std_logic := '1' ; --
-- AXI DataMover Secondary Reset (Raw) --
dm_s2mm_scndry_resetn : out std_logic := '1' ;
-- AXI Stream Primary Reset Outputs --
s2mm_prmry_reset_out_n : out std_logic := '1' ; --
-- AXI Stream Control Reset Outputs --
s2mm_sts_reset_out_n : out std_logic := '1' ; --
-- AXI Secondary reset
s2mm_scndry_resetn : out std_logic := '1' ; --
-- AXI Upsizer and Line Buffer --
s2mm_prmry_resetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Scatter Gather Distributed Reset Out
----------------------------------------------------------------------- --
-- AXI Scatter Gather Reset Out
m_axi_sg_aresetn : out std_logic := '1' ; --
-- AXI Scatter Gather Datamover Reset Out
dm_m_axi_sg_aresetn : out std_logic := '1' ; --
----------------------------------------------------------------------- --
-- Hard Reset Out --
----------------------------------------------------------------------- --
m_axi_sg_hrdresetn : out std_logic := '1' ; --
s_axi_lite_resetn : out std_logic := '1' --
);
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of s_axi_lite_resetn : signal is "TRUE";
Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no";
end axi_dma_rst_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_rst_module is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
ATTRIBUTE async_reg : STRING;
signal hrd_resetn_i_cdc_tig : std_logic := '1';
signal hrd_resetn_i_d1_cdc_tig : std_logic := '1';
--ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true";
-- Soft reset support
signal mm2s_soft_reset_clr : std_logic := '0';
signal s2mm_soft_reset_clr : std_logic := '0';
signal soft_reset_clr_i : std_logic := '0';
signal mm2s_soft_reset_done : std_logic := '0';
signal s2mm_soft_reset_done : std_logic := '0';
signal mm2s_scndry_resetn_i : std_logic := '0';
signal s2mm_scndry_resetn_i : std_logic := '0';
signal dm_mm2s_scndry_resetn_i : std_logic := '0';
signal dm_s2mm_scndry_resetn_i : std_logic := '0';
signal sg_hard_reset : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Register hard reset in
REG_HRD_RST : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => m_axi_sg_aclk,
scndry_resetn => '0',
scndry_out => sg_hard_reset,
scndry_vect_out => open
);
m_axi_sg_hrdresetn <= sg_hard_reset;
--REG_HRD_RST : process(m_axi_sg_aclk)
-- begin
-- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- hrd_resetn_i_cdc_tig <= axi_resetn;
-- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig;
-- end if;
-- end process REG_HRD_RST;
-- Regsiter hard reset out for axi lite interface
REG_HRD_RST_OUT : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => axi_resetn,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => s_axi_lite_resetn,
scndry_vect_out => open
);
--REG_HRD_RST_OUT : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig;
-- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig;
-- end if;
-- end process REG_HRD_RST_OUT;
dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i;
dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i;
-- mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface (default)
MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate
begin
-- both must be low before sg reset is asserted.
m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_BOTH;
-- Only s2mm channel included therefore map secondary resets to
-- from s2mm reset module to scatter gather interface
MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate
begin
m_axi_sg_aresetn <= s2mm_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i;
end generate MAP_SG_FOR_S2MM;
-- Only mm2s channel included therefore map secondary resets to
-- from mm2s reset module to scatter gather interface
MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= mm2s_scndry_resetn_i;
dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i;
end generate MAP_SG_FOR_MM2S;
-- Invalid configuration for axi dma - simply here for completeness
MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate
begin
m_axi_sg_aresetn <= '1';
dm_m_axi_sg_aresetn <= '1';
end generate MAP_NO_SG;
s2mm_scndry_resetn <= s2mm_scndry_resetn_i;
mm2s_scndry_resetn <= mm2s_scndry_resetn_i;
-- Generate MM2S reset signals
GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate
begin
RESET_I : entity axi_dma_v7_1_10.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_mm2s_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => mm2s_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => mm2s_all_idle ,
stop => mm2s_stop ,
halt => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
-- Secondary Reset
scndry_resetn => mm2s_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => mm2s_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_mm2s_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_mm2s_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => mm2s_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => mm2s_cntrl_reset_out_n
);
-- Sample an hold mm2s soft reset done to use in
-- combined reset done to DMACR
MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
mm2s_soft_reset_done <= '0';
elsif(mm2s_soft_reset_clr = '1')then
mm2s_soft_reset_done <= '1';
end if;
end if;
end process MM2S_SOFT_RST_DONE;
end generate GEN_RESET_FOR_MM2S;
-- No MM2S therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate
begin
mm2s_prmry_reset_out_n <= '1';
mm2s_cntrl_reset_out_n <= '1';
dm_mm2s_scndry_resetn_i <= '1';
dm_mm2s_prmry_resetn <= '1';
mm2s_prmry_resetn <= '1';
mm2s_scndry_resetn_i <= '1';
mm2s_halt <= '0';
mm2s_soft_reset_clr <= '0';
mm2s_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_MM2S;
-- Generate S2MM reset signals
GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate
begin
RESET_I : entity axi_dma_v7_1_10.axi_dma_reset
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ ,
C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_INCLUDE_SG => C_INCLUDE_SG
)
port map(
-- Clock Sources
m_axi_sg_aclk => m_axi_sg_aclk ,
axi_prmry_aclk => m_axi_s2mm_aclk ,
-- Hard Reset
axi_resetn => sg_hard_reset ,
-- Soft Reset
soft_reset => soft_reset ,
soft_reset_clr => s2mm_soft_reset_clr ,
soft_reset_done => soft_reset_clr_i ,
all_idle => s2mm_all_idle ,
stop => s2mm_stop ,
halt => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
-- Secondary Reset
scndry_resetn => s2mm_scndry_resetn_i ,
-- AXI Upsizer and Line Buffer
prmry_resetn => s2mm_prmry_resetn ,
-- AXI DataMover Primary Reset (Raw)
dm_prmry_resetn => dm_s2mm_prmry_resetn ,
-- AXI DataMover Secondary Reset (Raw)
dm_scndry_resetn => dm_s2mm_scndry_resetn_i ,
-- AXI Stream Primary Reset Outputs
prmry_reset_out_n => s2mm_prmry_reset_out_n ,
-- AXI Stream Alternate Reset Outputs
altrnt_reset_out_n => s2mm_sts_reset_out_n
);
-- Sample an hold s2mm soft reset done to use in
-- combined reset done to DMACR
S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then
s2mm_soft_reset_done <= '0';
elsif(s2mm_soft_reset_clr = '1')then
s2mm_soft_reset_done <= '1';
end if;
end if;
end process S2MM_SOFT_RST_DONE;
end generate GEN_RESET_FOR_S2MM;
-- No SsMM therefore tie off mm2s reset signals
GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_prmry_reset_out_n <= '1';
dm_s2mm_scndry_resetn_i <= '1';
dm_s2mm_prmry_resetn <= '1';
s2mm_prmry_resetn <= '1';
s2mm_scndry_resetn_i <= '1';
s2mm_halt <= '0';
s2mm_soft_reset_clr <= '0';
s2mm_soft_reset_done <= '1';
end generate GEN_NO_RESET_FOR_S2MM;
-- When both mm2s and s2mm are done then drive soft reset clear and
-- also clear s_h registers above
soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done;
soft_reset_clr <= soft_reset_clr_i;
end implementation;
| mit | 389c7cd7b53f6b6f7d954f6461dd819a | 0.422042 | 4.423519 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_sg_v4_1/hdl/src/vhdl/axi_sg_s2mm_basic_wrap.vhd | 1 | 49,604 | -- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
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-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
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-- special, incidental, or consequential loss or damage
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-- CRITICAL APPLICATIONS
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-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
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-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_s2mm_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover S2MM Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_reset;
use axi_sg_v4_1_3.axi_sg_cmd_status;
use axi_sg_v4_1_3.axi_sg_scc_wr;
use axi_sg_v4_1_3.axi_sg_addr_cntl;
use axi_sg_v4_1_3.axi_sg_wrdata_cntl;
use axi_sg_v4_1_3.axi_sg_wr_status_cntl;
Use axi_sg_v4_1_3.axi_sg_skid2mm_buf;
Use axi_sg_v4_1_3.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_s2mm_basic_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 2;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Basic S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0); --
-- S2MM Halt request input control ---------------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------------
-- S2MM Error discrete output --------------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------------
-- Optional Command/Status Interface Clock and Reset Inputs -------
-- Only used when C_S2MM_STSCMD_IS_ASYNC = 1 --
--
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) ------------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
---------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) ------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(7 downto 0); --
s2mm_sts_wstrb : out std_logic_vector(0 downto 0); --
s2mm_sts_wlast : out std_logic; --
--------------------------------------------------------------------
-- Address posting controls ----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
--------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ---------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O -----------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
--------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O -----------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O ------------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
-----------------------------------------------------------------
);
end entity axi_sg_s2mm_basic_wrap;
architecture implementation of axi_sg_s2mm_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_wdemux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Write Strobe demux select control.
--
-------------------------------------------------------------------
function func_calc_wdemux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_wdemux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant S2MM_AWID_VALUE : integer range 0 to 255 := C_S2MM_AWID;
Constant S2MM_AWID_WIDTH : integer range 1 to 8 := C_S2MM_ID_WIDTH;
Constant S2MM_ADDR_WIDTH : integer range 32 to 64 := C_S2MM_ADDR_WIDTH;
Constant S2MM_MDATA_WIDTH : integer range 32 to 256 := C_S2MM_MDATA_WIDTH;
Constant S2MM_SDATA_WIDTH : integer range 8 to 256 := C_S2MM_SDATA_WIDTH;
Constant S2MM_CMD_WIDTH : integer := (C_TAG_WIDTH+C_S2MM_ADDR_WIDTH+32);
Constant S2MM_STS_WIDTH : integer := 8; -- always 8 for S2MM Basic Version
Constant INCLUDE_S2MM_STSFIFO : integer range 0 to 1 := 1;
Constant S2MM_STSCMD_FIFO_DEPTH : integer range 1 to 16 := 1;
Constant S2MM_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant S2MM_BURST_SIZE : integer range 16 to 256 := 16;
Constant WR_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_S2MM_ADDR_PIPE_DEPTH;
Constant WR_STATUS_CNTL_FIFO_DEPTH : integer range 1 to 32 := WR_DATA_CNTL_FIFO_DEPTH+2;-- 2 added for going
-- full thresholding
-- in WSC
Constant SEL_ADDR_WIDTH : integer := func_calc_wdemux_sel_bits(S2MM_MDATA_WIDTH);
Constant INCLUDE_S2MM_DRE : integer range 0 to 1 := 1;
Constant OMIT_S2MM_DRE : integer range 0 to 1 := 0;
Constant OMIT_INDET_BTT : integer := 0;
Constant SF_BYTES_RCVD_WIDTH : integer := 1;
Constant ZEROS_8_BIT : std_logic_vector(7 downto 0) := (others => '0');
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_s2mm_cmd_wdata : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_s2mm_cache_data : std_logic_vector(7 downto 0) := (others => '0');
signal sig_cmd2mstr_command : std_logic_vector(S2MM_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(S2MM_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_last : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2addr_data_rdy : std_logic := '0';
signal sig_data2all_tlast_error : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2wsc_calc_error : std_logic := '0';
signal sig_addr2wsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2wsc_rresp : std_logic_vector(1 downto 0) := (others => '0');
signal sig_data2wsc_cmd_empty : std_logic := '0';
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_wsc2stat_status : std_logic_vector(7 downto 0) := (others => '0');
signal sig_stat2wsc_status_ready : std_logic := '0';
signal sig_wsc2stat_status_valid : std_logic := '0';
signal sig_wsc2mstr_halt_pipe : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_addr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_skid2data_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_skid2axi_wvalid : std_logic := '0';
signal sig_axi2skid_wready : std_logic := '0';
signal sig_skid2axi_wdata : std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_skid2axi_wstrb : std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_skid2axi_wlast : std_logic := '0';
signal sig_data2wsc_sof : std_logic := '0';
signal sig_data2wsc_eof : std_logic := '0';
signal sig_data2wsc_valid : std_logic := '0';
signal sig_wsc2data_ready : std_logic := '0';
signal sig_data2wsc_eop : std_logic := '0';
signal sig_data2wsc_bytes_rcvd : std_logic_vector(SF_BYTES_RCVD_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_wsc2rst_stop_cmplt : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_realign2wdc_eop_error : std_logic := '0';
signal skid2wdc_wvalid : std_logic := '0';
signal wdc2skid_wready : std_logic := '0';
signal skid2wdc_wdata : std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0) := (others => '0');
signal skid2wdc_wstrb : std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal skid2wdc_wlast : std_logic := '0';
signal s2mm_awcache_int : std_logic_vector (3 downto 0);
signal sig_cache2mstr_command : std_logic_vector (7 downto 0);
begin --(architecture implementation)
-- Debug Port Assignments
s2mm_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the s2mm_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (s2mm_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"CAFE2222" ; -- 32 bit Constant indicating S2MM Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2wsc_status_ready;
sig_dbg_data_1(7) <= sig_wsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2wsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_wsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_wsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_wsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_wsc2stat_status(6) ; -- Slave Error
--sig_dbg_data_1(19) <= sig_wsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(19) <= '0' ; -- OKAY not used by TB
sig_dbg_data_1(20) <= sig_stat2wsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_wsc2stat_status_valid ; -- Status Valid Handshake
sig_dbg_data_1(29 downto 22) <= sig_mstr2data_len ; -- WDC Cmd FIFO LEN input
sig_dbg_data_1(30) <= sig_mstr2data_cmd_valid ; -- WDC Cmd FIFO Valid Inpute
sig_dbg_data_1(31) <= sig_data2mstr_cmd_ready ; -- WDC Cmd FIFO Ready Output
-- Write Data Channel I/O
s2mm_wvalid <= sig_skid2axi_wvalid;
sig_axi2skid_wready <= s2mm_wready ;
s2mm_wdata <= sig_skid2axi_wdata ;
s2mm_wstrb <= sig_skid2axi_wstrb ;
s2mm_wlast <= sig_skid2axi_wlast ;
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
s2mm_awcache <= "0011"; -- pre Interface-X guidelines for Masters
s2mm_awuser <= "0000"; -- pre Interface-X guidelines for Masters
sig_s2mm_cache_data <= (others => '0'); --s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
s2mm_awcache <= sg_ctl (3 downto 0); -- SG Cache from register
s2mm_awuser <= sg_ctl (7 downto 4); -- SG Cache from register
sig_s2mm_cache_data <= s2mm_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Internal error output discrete
s2mm_err <= sig_calc2dm_calc_err or sig_data2all_tlast_error;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_s2mm_cmd_wdata <= s2mm_cmd_wdata(S2MM_CMD_WIDTH-1 downto 0);
-- No Realigner in S2MM Basic
sig_realign2wdc_eop_error <= '0';
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_3.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC
)
port map (
primary_aclk => s2mm_aclk ,
primary_aresetn => s2mm_aresetn ,
secondary_awclk => s2mm_cmdsts_awclk ,
secondary_aresetn => s2mm_cmdsts_aresetn ,
halt_req => s2mm_halt ,
halt_cmplt => s2mm_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => sig_wsc2rst_stop_cmplt ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_3.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_S2MM_STSFIFO ,
C_STSCMD_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => S2MM_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
secondary_awclk => s2mm_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => s2mm_cmd_wvalid ,
cmd_wready => s2mm_cmd_wready ,
cmd_wdata => sig_s2mm_cmd_wdata ,
cache_data => sig_s2mm_cache_data ,
sts_wvalid => s2mm_sts_wvalid ,
sts_wready => s2mm_sts_wready ,
sts_wdata => s2mm_sts_wdata ,
sts_wstrb => s2mm_sts_wstrb ,
sts_wlast => s2mm_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_wsc2stat_status ,
stat2mstr_status_ready => sig_stat2wsc_status_ready ,
mst2stst_status_valid => sig_wsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Write Status Controller Block
--
------------------------------------------------------------
I_WR_STATUS_CNTLR : entity axi_sg_v4_1_3.axi_sg_wr_status_cntl
generic map (
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_STS_FIFO_DEPTH => WR_STATUS_CNTL_FIFO_DEPTH ,
C_STS_WIDTH => S2MM_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2wsc_stop_request => sig_rst2all_stop_request ,
wsc2rst_stop_cmplt => sig_wsc2rst_stop_cmplt ,
addr2wsc_addr_posted => sig_addr2data_addr_posted ,
s2mm_bresp => s2mm_bresp ,
s2mm_bvalid => s2mm_bvalid ,
s2mm_bready => s2mm_bready ,
calc2wsc_calc_error => sig_calc2dm_calc_err ,
addr2wsc_calc_error => sig_addr2wsc_calc_error ,
addr2wsc_fifo_empty => sig_addr2wsc_cmd_fifo_empty ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_error => sig_data2wsc_calc_err ,
data2wsc_last_error => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
data2wsc_valid => sig_data2wsc_valid ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2stat_status => sig_wsc2stat_status ,
stat2wsc_status_ready => sig_stat2wsc_status_ready ,
wsc2stat_status_valid => sig_wsc2stat_status_valid ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_3.axi_sg_scc_wr
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_S2MM_BURST_SIZE ,
C_CMD_WIDTH => S2MM_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_3.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_ADDR_FIFO_DEPTH => WR_ADDR_CNTL_FIFO_DEPTH ,
--C_ADDR_FIFO_DEPTH => S2MM_STSCMD_FIFO_DEPTH ,
C_ADDR_WIDTH => S2MM_ADDR_WIDTH ,
C_ADDR_ID => S2MM_AWID_VALUE ,
C_ADDR_ID_WIDTH => S2MM_AWID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => s2mm_awid ,
addr2axi_aaddr => s2mm_awaddr ,
addr2axi_alen => s2mm_awlen ,
addr2axi_asize => s2mm_awsize ,
addr2axi_aburst => s2mm_awburst ,
addr2axi_aprot => s2mm_awprot ,
addr2axi_avalid => s2mm_awvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => s2mm_awready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => s2mm_allow_addr_req ,
addr_req_posted => s2mm_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2wsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2wsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_S2MM_STRM_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registerd Slave Stream inputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_S2MM_STRM_SKID_BUF : entity axi_sg_v4_1_3.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => S2MM_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => s2mm_aclk ,
-- arst => sig_mmap_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => s2mm_strm_wvalid ,
-- s_ready => s2mm_strm_wready ,
-- s_data => s2mm_strm_wdata ,
-- s_strb => s2mm_strm_wstrb ,
-- s_last => s2mm_strm_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => skid2wdc_wvalid ,
-- m_ready => wdc2skid_wready ,
-- m_data => skid2wdc_wdata ,
-- m_strb => skid2wdc_wstrb ,
-- m_last => skid2wdc_wlast
--
-- );
--
------------------------------------------------------------
-- Instance: I_WR_DATA_CNTL
--
-- Description:
-- Write Data Controller Block
--
------------------------------------------------------------
I_WR_DATA_CNTL : entity axi_sg_v4_1_3.axi_sg_wrdata_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => ENABLE_WAIT_FOR_DATA ,
C_REALIGNER_INCLUDED => OMIT_S2MM_DRE ,
C_ENABLE_INDET_BTT => OMIT_INDET_BTT ,
C_SF_BYTES_RCVD_WIDTH => SF_BYTES_RCVD_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => WR_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => S2MM_MDATA_WIDTH ,
C_STREAM_DWIDTH => S2MM_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => s2mm_aclk ,
mmap_reset => sig_mmap_rst ,
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
wr_xfer_cmplt => s2mm_wr_xfer_cmplt ,
s2mm_ld_nxt_len => s2mm_ld_nxt_len ,
s2mm_wr_len => s2mm_wr_len ,
data2skid_saddr_lsb => sig_data2skid_addr_lsb ,
data2skid_wdata => sig_skid2axi_wdata,-- sig_data2skid_wdata ,
data2skid_wstrb => sig_skid2axi_wstrb,-- sig_data2skid_wstrb ,
data2skid_wlast => sig_skid2axi_wlast,-- sig_data2skid_wlast ,
data2skid_wvalid => sig_skid2axi_wvalid,-- sig_data2skid_wvalid ,
skid2data_wready => sig_axi2skid_wready,-- sig_skid2data_wready ,
s2mm_strm_wvalid => s2mm_strm_wvalid, --skid2wdc_wvalid ,
s2mm_strm_wready => s2mm_strm_wready, --wdc2skid_wready ,
s2mm_strm_wdata => s2mm_strm_wdata, --skid2wdc_wdata ,
s2mm_strm_wstrb => s2mm_strm_wstrb, --skid2wdc_wstrb ,
s2mm_strm_wlast => s2mm_strm_wlast, --skid2wdc_wlast ,
s2mm_strm_eop => s2mm_strm_wlast, --skid2wdc_wlast ,
s2mm_stbs_asserted => ZEROS_8_BIT ,
realign2wdc_eop_error => sig_realign2wdc_eop_error ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_last ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => sig_data2addr_data_rdy ,
data2all_tlast_error => sig_data2all_tlast_error ,
data2all_dcntlr_halted => sig_data2all_dcntlr_halted ,
data2skid_halt => sig_data2skid_halt ,
data2wsc_tag => sig_data2wsc_tag ,
data2wsc_calc_err => sig_data2wsc_calc_err ,
data2wsc_last_err => sig_data2wsc_last_err ,
data2wsc_cmd_cmplt => sig_data2wsc_cmd_cmplt ,
wsc2data_ready => sig_wsc2data_ready ,
data2wsc_valid => sig_data2wsc_valid ,
data2wsc_eop => sig_data2wsc_eop ,
data2wsc_bytes_rcvd => sig_data2wsc_bytes_rcvd ,
wsc2mstr_halt_pipe => sig_wsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_S2MM_MMAP_SKID_BUF
--
-- Description:
-- Instance for the S2MM Skid Buffer which provides for
-- registered outputs and supports bi-dir throttling.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
------------------------------------------------------------
-- I_S2MM_MMAP_SKID_BUF : entity axi_sg_v4_1_3.axi_sg_skid2mm_buf
-- generic map (
--
-- C_MDATA_WIDTH => S2MM_MDATA_WIDTH ,
-- C_SDATA_WIDTH => S2MM_SDATA_WIDTH ,
-- C_ADDR_LSB_WIDTH => SEL_ADDR_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- ACLK => s2mm_aclk ,
-- ARST => sig_stream_rst ,
--
-- -- Slave Side (Wr Data Controller Input Side )
-- S_ADDR_LSB => sig_data2skid_addr_lsb,
-- S_VALID => sig_data2skid_wvalid ,
-- S_READY => sig_skid2data_wready ,
-- S_Data => sig_data2skid_wdata ,
-- S_STRB => sig_data2skid_wstrb ,
-- S_Last => sig_data2skid_wlast ,
--
-- -- Master Side (MMap Write Data Output Side)
-- M_VALID => sig_skid2axi_wvalid ,
-- M_READY => sig_axi2skid_wready ,
-- M_Data => sig_skid2axi_wdata ,
-- M_STRB => sig_skid2axi_wstrb ,
-- M_Last => sig_skid2axi_wlast
--
-- );
--
end implementation;
| mit | 5e51e82b797cd3c223f5f46bd8173729 | 0.439702 | 4.066235 | false | false | false | false |
Bjay1435/capstone | Geoff/Geoff.srcs/sources_1/ip/blk_mem_gen_1/synth/blk_mem_gen_1.vhd | 1 | 14,509 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_3;
USE blk_mem_gen_v8_3_3.blk_mem_gen_v8_3_3;
ENTITY blk_mem_gen_1 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
);
END blk_mem_gen_1;
ARCHITECTURE blk_mem_gen_1_arch OF blk_mem_gen_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF blk_mem_gen_1_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_3 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(18 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_3;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_3,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF blk_mem_gen_1_arch : ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_3_3,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF blk_mem_gen_1_arch: ARCHITECTURE IS "blk_mem_gen_1,blk_mem_gen_v8_3_3,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_fi" &
"le_loaded,C_INIT_FILE=blk_mem_gen_1.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=10,C_READ_WIDTH_A=10,C_WRITE_DEPTH_A=307200,C_READ_DEPTH_A=307200,C_ADDRA_WIDTH=19,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=10,C_READ_WIDTH_B" &
"=10,C_WRITE_DEPTH_B=307200,C_READ_DEPTH_B=307200,C_ADDRB_WIDTH=19,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFE" &
"TY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=84,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.847786 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_3
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "blk_mem_gen_1.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 10,
C_READ_WIDTH_A => 10,
C_WRITE_DEPTH_A => 307200,
C_READ_DEPTH_A => 307200,
C_ADDRA_WIDTH => 19,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 10,
C_READ_WIDTH_B => 10,
C_WRITE_DEPTH_B => 307200,
C_READ_DEPTH_B => 307200,
C_ADDRB_WIDTH => 19,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "84",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.847786 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 19)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END blk_mem_gen_1_arch;
| mit | 93d1a623f8947cb680ec5d2d0e33f02a | 0.625818 | 2.992163 | false | false | false | false |
szanni/aeshw | aes-core/inv_cipher_cu.vhd | 1 | 2,818 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:32:08 07/20/2014
-- Design Name:
-- Module Name: inv_cipher_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity inv_cipher_cu is
port(
clk : in std_logic;
reset : in std_logic;
x_start : in std_logic; -- start decryption
x_comp : in std_logic; -- '1' if last round is reached
y_1_2 : out std_logic_vector(1 downto 0); -- controlling values for inv_cipher
y_3_4 : out std_logic_vector(1 downto 0); -- controlling values for decrementor
y_end : out std_logic -- decryption finished
);
end inv_cipher_cu;
architecture Behavioral of inv_cipher_cu is
type States is (S0, S1, S2, S3, S4, S5);
signal S, S_next : States;
begin
delta : process (S, x_start, x_comp)
begin
case S is
when S0 => y_1_2 <="--";
y_3_4 <="00"; -- initialize decrementor (with "A")
y_end <= '0';
if x_start = '1' then
S_next <= S1;
else
S_next <= S0;
end if;
when S1 => y_1_2 <= "--"; -- round key A not yet available (due to synchonous read)
y_3_4 <= "01"; -- decrement
y_end <= '0';
S_next <= S2;
when S2 => y_1_2 <= "00"; -- load in plaintext (round key A is now available), leave out inv_mix_columns stage
y_3_4 <= "01"; -- decrement
y_end <= '0';
S_next <= S3;
when S3 => y_1_2 <= "11"; -- feedback previous round result, include inv_mix_columns stage
y_3_4 <= "01"; -- decrement
y_end <= '0';
if x_comp = '1' then
S_next <= S4; -- last round starts after the next cycle
else
S_next <= S3;
end if;
when S4 => y_1_2 <= "10"; -- leave out inv_mix_columns stage
y_3_4 <= "--";
y_end <= '0';
S_next <= S5;
when S5 => y_1_2 <= "--";
y_3_4 <= "--";
y_end <= '1'; -- finished (output valid for one cycle)
S_next <= S0;
end case;
end process delta;
feedback_loop : process (clk, reset, S_next)
begin
if reset = '1' then
S <= S0;
elsif rising_edge(clk) then
S <= S_next;
end if;
end process feedback_loop;
end Behavioral;
| bsd-2-clause | 6395ca842c0225d9ded8481c37e14aab | 0.535131 | 3.246544 | false | false | false | false |
sergeykhbr/riscv_vhdl | vhdl/rtl/riverlib/core/memaccess.vhd | 1 | 19,616 | --!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity MemAccess is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_e_valid : in std_logic; -- Execution stage outputs are valid
i_e_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Execution stage instruction pointer
i_e_instr : in std_logic_vector(31 downto 0); -- Execution stage instruction value
i_e_flushd : in std_logic;
o_flushd : out std_logic;
i_memop_waddr : in std_logic_vector(5 downto 0); -- Register address to be written (0=no writing)
i_memop_wtag : in std_logic_vector(3 downto 0);
i_memop_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Register value to be written
i_memop_sign_ext : in std_logic; -- Load data with sign extending (if less than 8 Bytes)
i_memop_load : in std_logic; -- Load data from memory and write to i_res_addr
i_memop_store : in std_logic; -- Store i_res_data value into memory
i_memop_size : in std_logic_vector(1 downto 0); -- Encoded memory transaction size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
i_memop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Memory access address
o_memop_ready : out std_logic; -- Ready to accept memop request
o_wb_wena : out std_logic; -- Write enable signal
o_wb_waddr : out std_logic_vector(5 downto 0); -- Output register address (0 = x0 = no write)
o_wb_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Register value
o_wb_wtag : out std_logic_vector(3 downto 0);
i_wb_ready : in std_logic;
-- Memory interface:
i_mem_req_ready : in std_logic;
o_mem_valid : out std_logic; -- Memory request is valid
o_mem_write : out std_logic; -- Memory write request
o_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Data path requested address
o_mem_wdata : out std_logic_vector(63 downto 0); -- Data path requested data (write transaction)
o_mem_wstrb : out std_logic_vector(7 downto 0); -- 8-bytes aligned strobs
i_mem_data_valid : in std_logic; -- Data path memory response is valid
i_mem_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Data path memory response address
i_mem_data : in std_logic_vector(63 downto 0); -- Data path memory response value
o_mem_resp_ready : out std_logic
);
end;
architecture arch_MemAccess of MemAccess is
constant State_Idle : std_logic_vector(1 downto 0) := "00";
constant State_WaitReqAccept : std_logic_vector(1 downto 0) := "01";
constant State_WaitResponse : std_logic_vector(1 downto 0) := "10";
constant State_Hold : std_logic_vector(1 downto 0) := "11";
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type RegistersType is record
state : std_logic_vector(1 downto 0);
memop_w : std_logic;
memop_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
memop_wdata : std_logic_vector(63 downto 0);
memop_wstrb : std_logic_vector(7 downto 0);
memop_sign_ext : std_logic;
memop_size : std_logic_vector(1 downto 0);
memop_res_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
memop_res_instr : std_logic_vector(31 downto 0);
memop_res_addr : std_logic_vector(5 downto 0);
memop_res_data : std_logic_vector(RISCV_ARCH-1 downto 0);
memop_res_wena : std_logic;
memop_wtag : std_logic_vector(3 downto 0);
hold_rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
end record;
constant R_RESET : RegistersType := (
State_Idle, -- state
'0', (others => '0'), -- memop_w, memop_addr
(others => '0'), (others => '0'), -- memop_wdata, memop_wstrb
'0', (others => '0'), -- memop_sign_ext, memop_size
(others => '0'), (others => '0'), -- memop_res_pc, memop_res_instr
(others => '0'), -- memop_res_addr
(others => '0'), '0', -- memop_res_data, memop_res_wena
(others => '0'), -- memop_wtag
(others => '0') -- hold_rdata
);
signal r, rin : RegistersType;
-- TODO: move into separate module
-- queue signals before move into separate module
constant QUEUE_WIDTH : integer := 1 -- i_e_flushd
+ 4 -- wtag
+ 64 -- wdata width
+ 8 -- wdata btyes
+ RISCV_ARCH
+ 6
+ 32
+ CFG_CPU_ADDR_BITS
+ 2
+ 1
+ 1
+ CFG_CPU_ADDR_BITS
;
signal queue_we : std_logic;
signal queue_re : std_logic;
signal queue_data_i : std_logic_vector(QUEUE_WIDTH-1 downto 0);
signal queue_data_o : std_logic_vector(QUEUE_WIDTH-1 downto 0);
signal queue_nempty : std_logic;
signal queue_full : std_logic;
begin
queue0 : Queue generic map (
async_reset => async_reset,
szbits => 2,
dbits => QUEUE_WIDTH
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_re => queue_re,
i_we => queue_we,
i_wdata => queue_data_i,
o_rdata => queue_data_o,
o_full => queue_full,
o_nempty => queue_nempty
);
comb : process(i_nrst, i_e_valid, i_e_pc, i_e_instr, i_memop_waddr, i_memop_wtag, i_memop_wdata,
i_memop_sign_ext, i_memop_load, i_memop_store, i_memop_size, i_memop_addr,
i_wb_ready, i_mem_data_addr, i_mem_req_ready, i_mem_data_valid,
i_mem_data_addr, i_mem_data, i_e_flushd,
queue_data_o, queue_nempty, queue_full, r)
variable v : RegistersType;
variable vb_memop_wdata : std_logic_vector(63 downto 0);
variable vb_memop_wstrb : std_logic_vector(7 downto 0);
variable v_mem_valid : std_logic;
variable v_mem_write : std_logic;
variable v_mem_sign_ext : std_logic;
variable vb_mem_sz : std_logic_vector(1 downto 0);
variable vb_mem_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_mem_rdata : std_logic_vector(63 downto 0);
variable v_queue_re : std_logic;
variable v_flushd : std_logic;
variable vb_mem_wtag : std_logic_vector(3 downto 0);
variable vb_mem_wdata : std_logic_vector(63 downto 0);
variable vb_mem_wstrb : std_logic_vector(7 downto 0);
variable vb_mem_resp_shifted : std_logic_vector(63 downto 0);
variable vb_mem_data_unsigned : std_logic_vector(63 downto 0);
variable vb_mem_data_signed : std_logic_vector(63 downto 0);
variable vb_res_data : std_logic_vector(RISCV_ARCH-1 downto 0);
variable vb_res_addr : std_logic_vector(5 downto 0);
variable vb_e_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_e_instr : std_logic_vector(31 downto 0);
variable v_memop_ready : std_logic;
variable v_o_wena : std_logic;
variable vb_o_waddr : std_logic_vector(5 downto 0);
variable vb_o_wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
variable vb_o_wtag : std_logic_vector(3 downto 0);
begin
v := r;
v_mem_valid := '0';
v_queue_re := '0';
vb_mem_resp_shifted := (others => '0');
vb_mem_data_unsigned := (others => '0');
vb_mem_data_signed := (others => '0');
vb_memop_wdata := (others => '0');
vb_memop_wstrb := (others => '0');
v_o_wena := '0';
vb_o_waddr := (others => '0');
vb_o_wdata := (others => '0');
vb_o_wtag := (others => '0');
case i_memop_size is
when "00" =>
vb_memop_wdata := i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0)
& i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0)
& i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0)
& i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0);
if i_memop_addr(2 downto 0) = "000" then
vb_memop_wstrb := X"01";
elsif i_memop_addr(2 downto 0) = "001" then
vb_memop_wstrb := X"02";
elsif i_memop_addr(2 downto 0) = "010" then
vb_memop_wstrb := X"04";
elsif i_memop_addr(2 downto 0) = "011" then
vb_memop_wstrb := X"08";
elsif i_memop_addr(2 downto 0) = "100" then
vb_memop_wstrb := X"10";
elsif i_memop_addr(2 downto 0) = "101" then
vb_memop_wstrb := X"20";
elsif i_memop_addr(2 downto 0) = "110" then
vb_memop_wstrb := X"40";
elsif i_memop_addr(2 downto 0) = "111" then
vb_memop_wstrb := X"80";
end if;
when "01" =>
vb_memop_wdata := i_memop_wdata(15 downto 0) & i_memop_wdata(15 downto 0)
& i_memop_wdata(15 downto 0) & i_memop_wdata(15 downto 0);
if i_memop_addr(2 downto 1) = "00" then
vb_memop_wstrb := X"03";
elsif i_memop_addr(2 downto 1) = "01" then
vb_memop_wstrb := X"0C";
elsif i_memop_addr(2 downto 1) = "10" then
vb_memop_wstrb := X"30";
else
vb_memop_wstrb := X"C0";
end if;
when "10" =>
vb_memop_wdata := i_memop_wdata(31 downto 0) & i_memop_wdata(31 downto 0);
if i_memop_addr(2) = '1' then
vb_memop_wstrb := X"F0";
else
vb_memop_wstrb := X"0F";
end if;
when "11" =>
vb_memop_wdata := i_memop_wdata;
vb_memop_wstrb := X"FF";
when others =>
end case;
-- Form Queue inputs:
queue_data_i <= i_e_flushd & i_memop_wtag & vb_memop_wdata & vb_memop_wstrb &
i_memop_wdata & i_memop_waddr & i_e_instr & i_e_pc &
i_memop_size & i_memop_sign_ext & i_memop_store &
i_memop_addr;
queue_we <= i_e_valid and (i_memop_load or i_memop_store or i_e_flushd);
-- Split Queue outputs:
v_flushd := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+46);
vb_mem_wtag := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+45 downto
2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+42);
vb_mem_wdata := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+42-1 downto
2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+42);
vb_mem_wstrb := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+42-1 downto
2*CFG_CPU_ADDR_BITS+RISCV_ARCH+42);
vb_res_data := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+42-1 downto
2*CFG_CPU_ADDR_BITS+42);
vb_res_addr := queue_data_o(2*CFG_CPU_ADDR_BITS+42-1 downto
2*CFG_CPU_ADDR_BITS+36);
vb_e_instr := queue_data_o(2*CFG_CPU_ADDR_BITS+36-1 downto
2*CFG_CPU_ADDR_BITS+4);
vb_e_pc := queue_data_o(2*CFG_CPU_ADDR_BITS+4-1 downto CFG_CPU_ADDR_BITS+4);
vb_mem_sz := queue_data_o(CFG_CPU_ADDR_BITS+3 downto CFG_CPU_ADDR_BITS+2);
v_mem_sign_ext := queue_data_o(CFG_CPU_ADDR_BITS+1);
v_mem_write := queue_data_o(CFG_CPU_ADDR_BITS);
vb_mem_addr := queue_data_o(CFG_CPU_ADDR_BITS-1 downto 0);
case r.memop_addr(2 downto 0) is
when "001" => vb_mem_resp_shifted := zero64(7 downto 0) & i_mem_data(63 downto 8);
when "010" => vb_mem_resp_shifted := zero64(15 downto 0) & i_mem_data(63 downto 16);
when "011" => vb_mem_resp_shifted := zero64(23 downto 0) & i_mem_data(63 downto 24);
when "100" => vb_mem_resp_shifted := zero64(31 downto 0) & i_mem_data(63 downto 32);
when "101" => vb_mem_resp_shifted := zero64(39 downto 0) & i_mem_data(63 downto 40);
when "110" => vb_mem_resp_shifted := zero64(47 downto 0) & i_mem_data(63 downto 48);
when "111" => vb_mem_resp_shifted := zero64(55 downto 0) & i_mem_data(63 downto 56);
when others => vb_mem_resp_shifted := i_mem_data;
end case;
case r.memop_size is
when MEMOP_1B =>
vb_mem_data_unsigned(7 downto 0) := vb_mem_resp_shifted(7 downto 0);
vb_mem_data_signed(7 downto 0) := vb_mem_resp_shifted(7 downto 0);
vb_mem_data_signed(63 downto 8) := (others => vb_mem_resp_shifted(7));
when MEMOP_2B =>
vb_mem_data_unsigned(15 downto 0) := vb_mem_resp_shifted(15 downto 0);
vb_mem_data_signed(15 downto 0) := vb_mem_resp_shifted(15 downto 0);
vb_mem_data_signed(63 downto 16) := (others => vb_mem_resp_shifted(15));
when MEMOP_4B =>
vb_mem_data_unsigned(31 downto 0) := vb_mem_resp_shifted(31 downto 0);
vb_mem_data_signed(31 downto 0) := vb_mem_resp_shifted(31 downto 0);
vb_mem_data_signed(63 downto 32) := (others => vb_mem_resp_shifted(31));
when others =>
vb_mem_data_unsigned := vb_mem_resp_shifted;
vb_mem_data_signed := vb_mem_resp_shifted;
end case;
if r.memop_w = '0' then
if r.memop_sign_ext = '1' then
vb_mem_rdata := vb_mem_data_signed;
else
vb_mem_rdata := vb_mem_data_unsigned;
end if;
else
vb_mem_rdata := r.memop_res_data;
end if;
case r.state is
when State_Idle =>
v_queue_re := '1';
if queue_nempty = '1' then
v_mem_valid := not v_flushd;
v.memop_res_pc := vb_e_pc;
v.memop_res_instr := vb_e_instr;
v.memop_res_addr := vb_res_addr;
v.memop_res_data := vb_res_data;
v.memop_res_wena := or_reduce(vb_res_addr);
v.memop_addr := vb_mem_addr;
v.memop_wdata := vb_mem_wdata;
v.memop_wtag := vb_mem_wtag;
v.memop_wstrb := vb_mem_wstrb;
v.memop_w := v_mem_write;
v.memop_sign_ext := v_mem_sign_ext;
v.memop_size := vb_mem_sz;
if v_flushd = '1' then
-- do nothing
elsif i_mem_req_ready = '1' then
v.state := State_WaitResponse;
else
v.state := State_WaitReqAccept;
end if;
end if;
when State_WaitReqAccept =>
v_mem_valid := '1';
v_mem_write := r.memop_w;
vb_mem_sz := r.memop_size;
vb_mem_addr := r.memop_addr;
vb_mem_wdata := r.memop_wdata;
vb_mem_wstrb := r.memop_wstrb;
vb_res_data := r.memop_res_data;
if i_mem_req_ready = '1' then
v.state := State_WaitResponse;
end if;
when State_WaitResponse =>
if i_mem_data_valid = '0' then
-- Do nothing
else
v_o_wena := r.memop_res_wena;
vb_o_waddr := r.memop_res_addr;
vb_o_wdata := vb_mem_rdata;
vb_o_wtag := r.memop_wtag;
v_queue_re := '1';
if r.memop_res_wena = '1' and i_wb_ready = '0' then
-- Inject only one clock hold-on and wait a couple of clocks
v_queue_re := '0';
v.state := State_Hold;
v.hold_rdata := vb_mem_rdata;
elsif queue_nempty = '1' then
v_mem_valid := not v_flushd;
v.memop_res_pc := vb_e_pc;
v.memop_res_instr := vb_e_instr;
v.memop_res_addr := vb_res_addr;
v.memop_res_data := vb_res_data;
v.memop_res_wena := or_reduce(vb_res_addr);
v.memop_addr := vb_mem_addr;
v.memop_wdata := vb_mem_wdata;
v.memop_wtag := vb_mem_wtag;
v.memop_wstrb := vb_mem_wstrb;
v.memop_w := v_mem_write;
v.memop_sign_ext := v_mem_sign_ext;
v.memop_size := vb_mem_sz;
if v_flushd = '1' then
v.state := State_Idle;
elsif i_mem_req_ready = '1' then
v.state := State_WaitResponse;
else
v.state := State_WaitReqAccept;
end if;
else
v.state := State_Idle;
end if;
end if;
when State_Hold =>
v_o_wena := r.memop_res_wena;
vb_o_waddr := r.memop_res_addr;
vb_o_wdata := r.hold_rdata;
vb_o_wtag := r.memop_wtag;
if i_wb_ready = '1' then
v_queue_re := '1';
if queue_nempty = '1' then
v_mem_valid := not v_flushd;
v.memop_res_pc := vb_e_pc;
v.memop_res_instr := vb_e_instr;
v.memop_res_addr := vb_res_addr;
v.memop_res_data := vb_res_data;
v.memop_res_wena := or_reduce(vb_res_addr);
v.memop_addr := vb_mem_addr;
v.memop_wdata := vb_mem_wdata;
v.memop_wtag := vb_mem_wtag;
v.memop_wstrb := vb_mem_wstrb;
v.memop_w := v_mem_write;
v.memop_sign_ext := v_mem_sign_ext;
v.memop_size := vb_mem_sz;
if v_flushd = '1' then
v.state := State_Idle;
elsif i_mem_req_ready = '1' then
v.state := State_WaitResponse;
else
v.state := State_WaitReqAccept;
end if;
else
v.state := State_Idle;
end if;
end if;
when others =>
end case;
v_memop_ready := '1';
if queue_full = '1' then
v_memop_ready := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
queue_re <= v_queue_re;
o_flushd <= queue_nempty and v_flushd and v_queue_re;
o_mem_resp_ready <= '1';
o_mem_valid <= v_mem_valid;
o_mem_write <= v_mem_write;
o_mem_addr <= vb_mem_addr(CFG_CPU_ADDR_BITS-1 downto 3) & "000";
o_mem_wdata <= vb_mem_wdata;
o_mem_wstrb <= vb_mem_wstrb;
o_memop_ready <= v_memop_ready;
o_wb_wena <= v_o_wena;
o_wb_waddr <= vb_o_waddr;
o_wb_wdata <= vb_o_wdata;
o_wb_wtag <= vb_o_wtag;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
| apache-2.0 | d777ddb4260b08a4616177f842ac1aee | 0.535991 | 3.278623 | false | false | false | false |
szanni/aeshw | aes-core/inv_cipher_tb.vhd | 1 | 746 | library ieee;
use ieee.std_logic_1164.all;
use work.types.all;
entity inv_cipher_tb is
end inv_cipher_tb;
architecture behavior of inv_cipher_tb is
component inv_cipher
port (
din : in state;
dout : out state
);
end component;
--Inputs
signal din : state;
--Outputs
signal dout : state;
begin
uut: inv_cipher port map (
din => din,
dout => dout
);
stim_proc: process
begin
--din <= x"d4bf5d30e0b452aeb84111f11e2798e5";
din <= x"fa636a2825b339c940668a3157244d17";
wait for 10 ns;
--assert dout = x"d42711aee0bf98f1b8b45de51e415230" report "inv_cipher: lookup failure" severity failure;
assert dout = x"fc1fc1f91934c98210fbfb8da340eb21" report "inv_cipher: mix failure" severity failure;
wait;
end process;
end;
| bsd-2-clause | ac1a18e8953f551b5757f016e9a37d90 | 0.725201 | 2.617544 | false | false | false | false |
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