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ptracton/Picoblaze | tools/Picoasm/ROM_form.vhd | 6 | 12,443 | ROM_form.vhd
Ken Chapman (Xilinx Ltd) July 2003
This is the VHDL template file for the KCPSM3 assembler.
It is used to configure a Spartan-3, Virtex-II or Virtex-IIPRO block RAM to act as
a single port program ROM.
This VHDL file is not valid as input directly into a synthesis or simulation tool.
The assembler will read this template and insert the data required to complete the
definition of program ROM and write it out to a new '.vhd' file associated with the
name of the original '.psm' file being assembled.
This template can be modified to define alternative memory definitions such as dual port.
However, you are responsible for ensuring the template is correct as the assembler does
not perform any checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
****************************************************************************************
This template defines a block RAM configured in 1024 x 18-bit single port mode and
conneceted to act as a single port ROM.
****************************************************************************************
The next line is used to determine where the template actually starts and must exist.
{begin template}
--
-- Definition of a single port ROM for KCPSM3 program defined by {name}.psm
--
-- Generated by KCPSM3 Assembler {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(9 downto 0);
instruction : out std_logic_vector(17 downto 0);
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
-- Attributes to define ROM contents during implementation synthesis.
-- The information is repeated in the generic map for functional simulation
--
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_02 : string;
attribute INIT_03 : string;
attribute INIT_04 : string;
attribute INIT_05 : string;
attribute INIT_06 : string;
attribute INIT_07 : string;
attribute INIT_08 : string;
attribute INIT_09 : string;
attribute INIT_0A : string;
attribute INIT_0B : string;
attribute INIT_0C : string;
attribute INIT_0D : string;
attribute INIT_0E : string;
attribute INIT_0F : string;
attribute INIT_10 : string;
attribute INIT_11 : string;
attribute INIT_12 : string;
attribute INIT_13 : string;
attribute INIT_14 : string;
attribute INIT_15 : string;
attribute INIT_16 : string;
attribute INIT_17 : string;
attribute INIT_18 : string;
attribute INIT_19 : string;
attribute INIT_1A : string;
attribute INIT_1B : string;
attribute INIT_1C : string;
attribute INIT_1D : string;
attribute INIT_1E : string;
attribute INIT_1F : string;
attribute INIT_20 : string;
attribute INIT_21 : string;
attribute INIT_22 : string;
attribute INIT_23 : string;
attribute INIT_24 : string;
attribute INIT_25 : string;
attribute INIT_26 : string;
attribute INIT_27 : string;
attribute INIT_28 : string;
attribute INIT_29 : string;
attribute INIT_2A : string;
attribute INIT_2B : string;
attribute INIT_2C : string;
attribute INIT_2D : string;
attribute INIT_2E : string;
attribute INIT_2F : string;
attribute INIT_30 : string;
attribute INIT_31 : string;
attribute INIT_32 : string;
attribute INIT_33 : string;
attribute INIT_34 : string;
attribute INIT_35 : string;
attribute INIT_36 : string;
attribute INIT_37 : string;
attribute INIT_38 : string;
attribute INIT_39 : string;
attribute INIT_3A : string;
attribute INIT_3B : string;
attribute INIT_3C : string;
attribute INIT_3D : string;
attribute INIT_3E : string;
attribute INIT_3F : string;
attribute INITP_00 : string;
attribute INITP_01 : string;
attribute INITP_02 : string;
attribute INITP_03 : string;
attribute INITP_04 : string;
attribute INITP_05 : string;
attribute INITP_06 : string;
attribute INITP_07 : string;
--
-- Attributes to define ROM contents during implementation synthesis.
--
attribute INIT_00 of ram_1024_x_18 : label is "{INIT_00}";
attribute INIT_01 of ram_1024_x_18 : label is "{INIT_01}";
attribute INIT_02 of ram_1024_x_18 : label is "{INIT_02}";
attribute INIT_03 of ram_1024_x_18 : label is "{INIT_03}";
attribute INIT_04 of ram_1024_x_18 : label is "{INIT_04}";
attribute INIT_05 of ram_1024_x_18 : label is "{INIT_05}";
attribute INIT_06 of ram_1024_x_18 : label is "{INIT_06}";
attribute INIT_07 of ram_1024_x_18 : label is "{INIT_07}";
attribute INIT_08 of ram_1024_x_18 : label is "{INIT_08}";
attribute INIT_09 of ram_1024_x_18 : label is "{INIT_09}";
attribute INIT_0A of ram_1024_x_18 : label is "{INIT_0A}";
attribute INIT_0B of ram_1024_x_18 : label is "{INIT_0B}";
attribute INIT_0C of ram_1024_x_18 : label is "{INIT_0C}";
attribute INIT_0D of ram_1024_x_18 : label is "{INIT_0D}";
attribute INIT_0E of ram_1024_x_18 : label is "{INIT_0E}";
attribute INIT_0F of ram_1024_x_18 : label is "{INIT_0F}";
attribute INIT_10 of ram_1024_x_18 : label is "{INIT_10}";
attribute INIT_11 of ram_1024_x_18 : label is "{INIT_11}";
attribute INIT_12 of ram_1024_x_18 : label is "{INIT_12}";
attribute INIT_13 of ram_1024_x_18 : label is "{INIT_13}";
attribute INIT_14 of ram_1024_x_18 : label is "{INIT_14}";
attribute INIT_15 of ram_1024_x_18 : label is "{INIT_15}";
attribute INIT_16 of ram_1024_x_18 : label is "{INIT_16}";
attribute INIT_17 of ram_1024_x_18 : label is "{INIT_17}";
attribute INIT_18 of ram_1024_x_18 : label is "{INIT_18}";
attribute INIT_19 of ram_1024_x_18 : label is "{INIT_19}";
attribute INIT_1A of ram_1024_x_18 : label is "{INIT_1A}";
attribute INIT_1B of ram_1024_x_18 : label is "{INIT_1B}";
attribute INIT_1C of ram_1024_x_18 : label is "{INIT_1C}";
attribute INIT_1D of ram_1024_x_18 : label is "{INIT_1D}";
attribute INIT_1E of ram_1024_x_18 : label is "{INIT_1E}";
attribute INIT_1F of ram_1024_x_18 : label is "{INIT_1F}";
attribute INIT_20 of ram_1024_x_18 : label is "{INIT_20}";
attribute INIT_21 of ram_1024_x_18 : label is "{INIT_21}";
attribute INIT_22 of ram_1024_x_18 : label is "{INIT_22}";
attribute INIT_23 of ram_1024_x_18 : label is "{INIT_23}";
attribute INIT_24 of ram_1024_x_18 : label is "{INIT_24}";
attribute INIT_25 of ram_1024_x_18 : label is "{INIT_25}";
attribute INIT_26 of ram_1024_x_18 : label is "{INIT_26}";
attribute INIT_27 of ram_1024_x_18 : label is "{INIT_27}";
attribute INIT_28 of ram_1024_x_18 : label is "{INIT_28}";
attribute INIT_29 of ram_1024_x_18 : label is "{INIT_29}";
attribute INIT_2A of ram_1024_x_18 : label is "{INIT_2A}";
attribute INIT_2B of ram_1024_x_18 : label is "{INIT_2B}";
attribute INIT_2C of ram_1024_x_18 : label is "{INIT_2C}";
attribute INIT_2D of ram_1024_x_18 : label is "{INIT_2D}";
attribute INIT_2E of ram_1024_x_18 : label is "{INIT_2E}";
attribute INIT_2F of ram_1024_x_18 : label is "{INIT_2F}";
attribute INIT_30 of ram_1024_x_18 : label is "{INIT_30}";
attribute INIT_31 of ram_1024_x_18 : label is "{INIT_31}";
attribute INIT_32 of ram_1024_x_18 : label is "{INIT_32}";
attribute INIT_33 of ram_1024_x_18 : label is "{INIT_33}";
attribute INIT_34 of ram_1024_x_18 : label is "{INIT_34}";
attribute INIT_35 of ram_1024_x_18 : label is "{INIT_35}";
attribute INIT_36 of ram_1024_x_18 : label is "{INIT_36}";
attribute INIT_37 of ram_1024_x_18 : label is "{INIT_37}";
attribute INIT_38 of ram_1024_x_18 : label is "{INIT_38}";
attribute INIT_39 of ram_1024_x_18 : label is "{INIT_39}";
attribute INIT_3A of ram_1024_x_18 : label is "{INIT_3A}";
attribute INIT_3B of ram_1024_x_18 : label is "{INIT_3B}";
attribute INIT_3C of ram_1024_x_18 : label is "{INIT_3C}";
attribute INIT_3D of ram_1024_x_18 : label is "{INIT_3D}";
attribute INIT_3E of ram_1024_x_18 : label is "{INIT_3E}";
attribute INIT_3F of ram_1024_x_18 : label is "{INIT_3F}";
attribute INITP_00 of ram_1024_x_18 : label is "{INITP_00}";
attribute INITP_01 of ram_1024_x_18 : label is "{INITP_01}";
attribute INITP_02 of ram_1024_x_18 : label is "{INITP_02}";
attribute INITP_03 of ram_1024_x_18 : label is "{INITP_03}";
attribute INITP_04 of ram_1024_x_18 : label is "{INITP_04}";
attribute INITP_05 of ram_1024_x_18 : label is "{INITP_05}";
attribute INITP_06 of ram_1024_x_18 : label is "{INITP_06}";
attribute INITP_07 of ram_1024_x_18 : label is "{INITP_07}";
--
begin
--
--Instantiate the Xilinx primitive for a block RAM
ram_1024_x_18: RAMB16_S18
--synthesis translate_off
--INIT values repeated to define contents for functional simulation
generic map ( INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
--synthesis translate_on
port map( DI => "0000000000000000",
DIP => "00",
EN => '1',
WE => '0',
SSR => '0',
CLK => clk,
ADDR => address,
DO => instruction(15 downto 0),
DOP => instruction(17 downto 16));
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
| mit | 77cbc004adff3169c2ec3e50221149ab | 0.58555 | 3.272751 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_dverif.vhd | 1 | 5,908 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_eb_fifo_counted_resized_pkg.ALL;
ENTITY k7_eb_fifo_counted_resized_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF k7_eb_fifo_counted_resized_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:k7_eb_fifo_counted_resized_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 81f927c2cf33eb56152d7b365d4f0edc | 0.571429 | 3.975774 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/memory.vhd | 1 | 1,181 | library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
entity MEMORY is
port (
clk : in std_logic;
we : in std_logic;
re : in std_logic;
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0)
);
end entity;
architecture MEMORY_ARCH of MEMORY is
type ram_type is array (0 to 63) of std_logic_vector(15 downto 0);
signal ram : ram_type;
signal read_address : std_logic_vector(7 downto 0);
begin
RamProc: process(clk) is
begin
ram(0) <= "1110000000010000";
ram(1) <= "1110000100010001";
ram(2) <= "0000000000010010";
ram(3) <= "1101001000000000";
ram(32) <= "0000000000000010";
ram(33) <= "0000000000000101";
if clk'event and clk = '1' then
if we = '1' then
ram(to_integer(unsigned(address))) <= datain;
end if;
read_address <= address;
end if;
end process RamProc;
OUTPUT : with re & we select
dataout <=
ram(to_integer(unsigned(address))) when "10",
"ZZZZZZZZZZZZZZZZ" when "00",
"ZZZZZZZZZZZZZZZZ" when "01 ",
"ZZZZZZZZZZZZZZZZ" when others;
end architecture; | gpl-3.0 | 65e695fda0c78168397d6fa20b94977f | 0.635902 | 3.235616 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_pctrl.vhd | 1 | 18,343 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF k7_prime_fifo_plain_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:k7_prime_fifo_plain_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:k7_prime_fifo_plain_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | 30634369912dce6ce01036b970c12d05 | 0.509949 | 3.244252 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weights/example_design/weights_exdes.vhd | 1 | 4,607 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weights_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weights_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weights_exdes;
ARCHITECTURE xilinx OF weights_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weights IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weights
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| bsd-2-clause | 05f7f61433d2f880135272db1bcc6f72 | 0.567397 | 4.774093 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/bcdtime_tb.vhd | 1 | 3,270 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : bcdtime_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-04
-- Last update: 2016-08-22
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: testbench for time counters
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-04 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity bcdtime_tb is
end bcdtime_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
use work.tb_pkg.all;
architecture STRUCTURE of bcdtime_tb is
component bcdtime
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
set : in std_logic;
set_time : in time_ty;
cur_time : out time_ty
);
end component;
SIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL tsc_1pps : std_logic;
SIGNAL tsc_1ppms : std_logic;
SIGNAL set : std_logic;
SIGNAL set_time : time_ty;
SIGNAL cur_time : time_ty;
begin
digits: bcdtime
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
set => set,
set_time => set_time,
cur_time => cur_time
);
clk_100MHZ: clk_gen(10 ns, 50, clk);
reset: rst_n_gen(1 us, rst_n);
process
begin
tsc_1pps <= '0';
run_clk(clk, 1000);
loop
tsc_1pps <= '1';
run_clk(clk, 1);
tsc_1pps <= '0';
run_clk(clk, 1999);
end loop;
end process;
process
begin
tsc_1ppms <= '0';
run_clk(clk, 1000);
loop
tsc_1ppms <= '1';
run_clk(clk, 1);
tsc_1ppms <= '0';
run_clk(clk, 1);
end loop;
end process;
set <= '0';
set_time.t_1ms <= (others => '0');
set_time.t_10ms <= (others => '0');
set_time.t_100ms <= (others => '0');
set_time.t_1s <= (others => '0');
set_time.t_10s <= (others => '0');
set_time.t_1m <= (others => '0');
set_time.t_10m <= (others => '0');
set_time.t_1h <= (others => '0');
set_time.t_10h <= (others => '0');
end STRUCTURE;
| gpl-3.0 | 298218f06b172b2f3f19dfbe176b1280 | 0.395413 | 3.724374 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_dgen.vhd | 1 | 5,120 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo8to32_pkg.ALL;
ENTITY fifo8to32_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo8to32_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo8to32_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 02ca2f68a179c84f689a098e7b55066e | 0.593945 | 3.987539 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_tb.vhd | 1 | 6,218 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_eb_fifo_counted_resized_pkg.ALL;
ENTITY k7_eb_fifo_counted_resized_tb IS
END ENTITY;
ARCHITECTURE k7_eb_fifo_counted_resized_arch OF k7_eb_fifo_counted_resized_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from k7_eb_fifo_counted_resized_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of k7_eb_fifo_counted_resized_synth
k7_eb_fifo_counted_resized_synth_inst:k7_eb_fifo_counted_resized_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 64
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | 7ac91c7ac8daad409e8eaa24f993ced0 | 0.619813 | 4.053455 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/FF_tagram64x36.vhd | 1 | 8,859 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FF_TagRam64x36 is
port (
wea : in STD_LOGIC;
web : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( C_TAGRAM_AWIDTH-1 downto 0 );
addrb : in STD_LOGIC_VECTOR ( C_TAGRAM_AWIDTH-1 downto 0 );
douta : out STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
dina : in STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
clk : in STD_LOGIC
);
end FF_TagRam64x36;
architecture STRUCTURE of FF_TagRam64x36 is
TYPE FF_RAM_Matrix is ARRAY (C_TAG_MAP_WIDTH-1 downto 0)
of std_logic_vector (C_TAGRAM_DWIDTH-1 downto 0);
signal FF_Reg : FF_RAM_Matrix;
signal FF_Muxer_a : STD_LOGIC_VECTOR ( C_TAG_MAP_WIDTH-1 downto 0 );
signal FF_Muxer_b : STD_LOGIC_VECTOR ( C_TAG_MAP_WIDTH-1 downto 0 );
--
signal wea_r1 : STD_LOGIC;
signal web_r1 : STD_LOGIC;
signal dina_r1 : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
signal dinb_r1 : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
signal douta_i : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
signal doutb_i : STD_LOGIC_VECTOR ( C_TAGRAM_DWIDTH-1 downto 0 );
begin
douta <= douta_i;
doutb <= (OTHERS=>'0'); -- doutb_i;
-- ---------------------------------------
--
Syn_Delay_Writes:
process ( clk )
begin
if clk'event and clk = '1' then
wea_r1 <= wea;
web_r1 <= web;
dina_r1 <= dina;
dinb_r1 <= dinb;
end if;
end process;
-- ---------------------------------------
--
FF_Address:
process ( clk )
begin
if clk'event and clk = '1' then
FOR k IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if addra=CONV_STD_LOGIC_VECTOR(k, C_TAGRAM_AWIDTH)
then
FF_Muxer_a(k) <= '1';
else
FF_Muxer_a(k) <= '0';
end if;
END LOOP;
FOR k IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if addrb=CONV_STD_LOGIC_VECTOR(k, C_TAGRAM_AWIDTH)
then
FF_Muxer_b(k) <= '1';
else
FF_Muxer_b(k) <= '0';
end if;
END LOOP;
end if;
end process;
-- ---------------------------------------
--
FF_Matrix_Write:
process ( clk )
begin
if clk'event and clk = '1' then
FOR k IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if wea_r1='1' and web_r1='1' and FF_Muxer_a(k)='1' and FF_Muxer_b(k)='1' then
FF_Reg(k) <= dina_r1;
elsif wea_r1='1' and FF_Muxer_a(k)='1' then
FF_Reg(k) <= dina_r1;
elsif web_r1='1' and FF_Muxer_b(k)='1' then
FF_Reg(k) <= dinb_r1;
else
FF_Reg(k) <= FF_Reg(k);
end if;
END LOOP;
end if;
end process;
-- ---------------------------------------
--
FF_Matrix_Read:
process ( clk )
begin
if clk'event and clk = '1' then
case FF_Muxer_a is
when X"0000000000000001" =>
douta_i <= FF_Reg(0);
when X"0000000000000002" =>
douta_i <= FF_Reg(1);
when X"0000000000000004" =>
douta_i <= FF_Reg(2);
when X"0000000000000008" =>
douta_i <= FF_Reg(3);
when X"0000000000000010" =>
douta_i <= FF_Reg(4);
when X"0000000000000020" =>
douta_i <= FF_Reg(5);
when X"0000000000000040" =>
douta_i <= FF_Reg(6);
when X"0000000000000080" =>
douta_i <= FF_Reg(7);
when X"0000000000000100" =>
douta_i <= FF_Reg(8);
when X"0000000000000200" =>
douta_i <= FF_Reg(9);
when X"0000000000000400" =>
douta_i <= FF_Reg(10);
when X"0000000000000800" =>
douta_i <= FF_Reg(11);
when X"0000000000001000" =>
douta_i <= FF_Reg(12);
when X"0000000000002000" =>
douta_i <= FF_Reg(13);
when X"0000000000004000" =>
douta_i <= FF_Reg(14);
when X"0000000000008000" =>
douta_i <= FF_Reg(15);
when X"0000000000010000" =>
douta_i <= FF_Reg(16);
when X"0000000000020000" =>
douta_i <= FF_Reg(17);
when X"0000000000040000" =>
douta_i <= FF_Reg(18);
when X"0000000000080000" =>
douta_i <= FF_Reg(19);
when X"0000000000100000" =>
douta_i <= FF_Reg(20);
when X"0000000000200000" =>
douta_i <= FF_Reg(21);
when X"0000000000400000" =>
douta_i <= FF_Reg(22);
when X"0000000000800000" =>
douta_i <= FF_Reg(23);
when X"0000000001000000" =>
douta_i <= FF_Reg(24);
when X"0000000002000000" =>
douta_i <= FF_Reg(25);
when X"0000000004000000" =>
douta_i <= FF_Reg(26);
when X"0000000008000000" =>
douta_i <= FF_Reg(27);
when X"0000000010000000" =>
douta_i <= FF_Reg(28);
when X"0000000020000000" =>
douta_i <= FF_Reg(29);
when X"0000000040000000" =>
douta_i <= FF_Reg(30);
when X"0000000080000000" =>
douta_i <= FF_Reg(31);
when X"0000000100000000" =>
douta_i <= FF_Reg(32);
when X"0000000200000000" =>
douta_i <= FF_Reg(33);
when X"0000000400000000" =>
douta_i <= FF_Reg(34);
when X"0000000800000000" =>
douta_i <= FF_Reg(35);
when X"0000001000000000" =>
douta_i <= FF_Reg(36);
when X"0000002000000000" =>
douta_i <= FF_Reg(37);
when X"0000004000000000" =>
douta_i <= FF_Reg(38);
when X"0000008000000000" =>
douta_i <= FF_Reg(39);
when X"0000010000000000" =>
douta_i <= FF_Reg(40);
when X"0000020000000000" =>
douta_i <= FF_Reg(41);
when X"0000040000000000" =>
douta_i <= FF_Reg(42);
when X"0000080000000000" =>
douta_i <= FF_Reg(43);
when X"0000100000000000" =>
douta_i <= FF_Reg(44);
when X"0000200000000000" =>
douta_i <= FF_Reg(45);
when X"0000400000000000" =>
douta_i <= FF_Reg(46);
when X"0000800000000000" =>
douta_i <= FF_Reg(47);
when X"0001000000000000" =>
douta_i <= FF_Reg(48);
when X"0002000000000000" =>
douta_i <= FF_Reg(49);
when X"0004000000000000" =>
douta_i <= FF_Reg(50);
when X"0008000000000000" =>
douta_i <= FF_Reg(51);
when X"0010000000000000" =>
douta_i <= FF_Reg(52);
when X"0020000000000000" =>
douta_i <= FF_Reg(53);
when X"0040000000000000" =>
douta_i <= FF_Reg(54);
when X"0080000000000000" =>
douta_i <= FF_Reg(55);
when X"0100000000000000" =>
douta_i <= FF_Reg(56);
when X"0200000000000000" =>
douta_i <= FF_Reg(57);
when X"0400000000000000" =>
douta_i <= FF_Reg(58);
when X"0800000000000000" =>
douta_i <= FF_Reg(59);
when X"1000000000000000" =>
douta_i <= FF_Reg(60);
when X"2000000000000000" =>
douta_i <= FF_Reg(61);
when X"4000000000000000" =>
douta_i <= FF_Reg(62);
-- when X"8000000000000000" =>
-- douta_i <= FF_Reg(63);
when OTHERS =>
douta_i <= FF_Reg(63);
end case;
end if;
end process;
end architecture STRUCTURE;
| gpl-2.0 | 867ff0a571c4d4c3738ec585a8f18339 | 0.449938 | 3.78105 | false | false | false | false |
peteut/nvc | test/regress/shift2.vhd | 2 | 3,781 | entity shift2 is
end entity;
architecture test of shift2 is
signal input : bit_vector(4 downto 0) := "11100";
begin
assert bit_vector'(input) ror -8 = "00111"
report "ror -8 is broken" severity error;
assert bit_vector'(input) ror -7 = "10011"
report "ror -7 is broken" severity error;
assert bit_vector'(input) ror -6 = "11001"
report "ror -6 is broken" severity error;
assert bit_vector'(input) ror -5 = input
report "ror -5 is broken" severity error;
assert bit_vector'(input) ror -4 = "01110"
report "ror -4 is broken" severity error;
assert bit_vector'(input) ror -3 = "00111"
report "ror -3 is broken" severity error;
assert bit_vector'(input) ror -2 = "10011"
report "ror -2 is broken" severity error;
assert bit_vector'(input) ror -1 = "11001"
report "ror -1 is broken" severity error;
assert bit_vector'(input) ror 0 = input
report "ror 0 is broken" severity error;
assert bit_vector'(input) ror 1 = "01110"
report "ror 1 is broken" severity error;
assert bit_vector'(input) ror 2 = "00111"
report "ror 2 is broken" severity error;
assert bit_vector'(input) ror 3 = "10011"
report "ror 3 is broken" severity error;
assert bit_vector'(input) ror 4 = "11001"
report "ror 4 is broken" severity error;
assert bit_vector'(input ror 5) = input
report "ror 5 is broken" severity error;
assert bit_vector'(input) ror 6 = "01110"
report "ror 6 is broken" severity error;
assert bit_vector'(input) ror 7 = "00111"
report "ror 7 is broken" severity error;
assert bit_vector'(input) ror 8 = "10011"
report "ror 8 is broken" severity error;
-- ROL
assert bit_vector'(input) rol -8 = "10011"
report "rol -8 is broken" severity error;
assert bit_vector'(input) rol -7 = "00111"
report "rol -7 is broken" severity error;
assert bit_vector'(input) rol -6 = "01110"
report "rol -6 is broken" severity error;
assert bit_vector'(input rol -5) = input
report "rol -5 is broken" severity error;
assert bit_vector'(input) rol -4 = "11001"
report "rol -4 is broken" severity error;
assert bit_vector'(input) rol -3 = "10011"
report "rol -3 is broken" severity error;
assert bit_vector'(input) rol -2 = "00111"
report "rol -2 is broken" severity error;
assert bit_vector'(input) rol -1 = "01110"
report "rol -1 is broken" severity error;
assert bit_vector'(input) rol 0 = input
report "rol 0 is broken" severity error;
assert bit_vector'(input) rol 1 = "11001"
report "rol 1 is broken" severity error;
assert bit_vector'(input) rol 2 = "10011"
report "rol 2 is broken" severity error;
assert bit_vector'(input) rol 3 = "00111"
report "rol 3 is broken" severity error;
assert bit_vector'(input) rol 4 = "01110"
report "rol 4 is broken" severity error;
assert bit_vector'(input) rol 5 = input
report "rol 5 is broken" severity error;
assert bit_vector'(input) rol 6 = "11001"
report "rol 6 is broken" severity error;
assert bit_vector'(input) rol 7 = "10011"
report "rol 7 is broken" severity error;
assert bit_vector'(input) rol 8 = "00111"
report "rol 8 is broken" severity error;
end architecture;
| gpl-3.0 | 47f7d595cee2b840e0515ef4ead03cb9 | 0.56731 | 3.838579 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/cpu_xadc_wiz_0_0.vhd | 1 | 12,229 | -- file: cpu_xadc_wiz_0_0.vhd
-- (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
Library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu_xadc_wiz_0_0 is
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector(10 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector(10 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
ot_out : out STD_LOGIC; -- Over-Temperature alarm output
vccddro_alarm_out : out STD_LOGIC; -- VCCDDRO-sensor alarm output
vccpint_alarm_out : out STD_LOGIC; -- VCCPINT-sensor alarm output
vccpaux_alarm_out : out STD_LOGIC; -- VCCPAUX-sensor alarm output
vccaux_alarm_out : out STD_LOGIC; -- VCCAUX-sensor alarm output
vccint_alarm_out : out STD_LOGIC; -- VCCINT-sensor alarm output
user_temp_alarm_out : out STD_LOGIC; -- Temperature-sensor alarm output
alarm_out : out STD_LOGIC; -- OR'ed output of all the Alarms
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end cpu_xadc_wiz_0_0;
architecture xilinx of cpu_xadc_wiz_0_0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "cpu_xadc_wiz_0_0,xadc_wiz_v3_0,{component_name=cpu_xadc_wiz_0_0,enable_axi=true,enable_axi4stream=false,dclk_frequency=100,enable_busy=true,enable_convst=false,enable_convstclk=false,enable_dclk=true,enable_drp=false,enable_eoc=true,enable_eos=true,enable_vbram_alaram=false,enable_vccddro_alaram=true,enable_Vccint_Alaram=true,enable_Vccaux_alaram=trueenable_vccpaux_alaram=true,enable_vccpint_alaram=true,ot_alaram=true,user_temp_alaram=true,timing_mode=continuous,channel_averaging=None,sequencer_mode=off,startup_channel_selection=single_channel}";
component cpu_xadc_wiz_0_0_axi_xadc
generic
(
-----------------------------------------
-- C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_HIGHADDR : std_logic_vector := X"0000_0000";
-----------------------------------------
-- AXI slave single block generics
C_INSTANCE : string := "cpu_xadc_wiz_0_0_axi_xadc";
C_FAMILY : string := "virtex7";
C_S_AXI_ADDR_WIDTH : integer range 2 to 32 := 11;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-----------------------------------------
-- SYSMON Generics
C_INCLUDE_INTR : integer range 0 to 1 := 1;
C_SIM_MONITOR_FILE : string := "/home/guest/cae/fpga/ntpserver/cpu/ip/cpu_xadc_wiz_0_0/cpu_xadc_wiz_0_0/simulation/functional/design.txt"
);
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
-- XADC External interface signals
-- Conversion start control signal for Event driven mode
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
ot_out : out STD_LOGIC; -- Over-Temperature alarm output
alarm_out : out STD_LOGIC_VECTOR(7 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end component;
signal alm_int : std_logic_vector (7 downto 0);
begin
alarm_out <= alm_int(7);
vccddro_alarm_out <= alm_int(6);
vccpaux_alarm_out <= alm_int(5);
vccpint_alarm_out <= alm_int(4);
vccaux_alarm_out <= alm_int(2);
vccint_alarm_out <= alm_int(1);
user_temp_alarm_out <= alm_int(0);
U0 : cpu_xadc_wiz_0_0_axi_xadc
generic map
(
C_INSTANCE => "cpu_xadc_wiz_0_0_axi_xadc",
C_FAMILY => "virtex7",
C_S_AXI_ADDR_WIDTH => 11,
C_S_AXI_DATA_WIDTH => 32,
C_INCLUDE_INTR => 1,
C_SIM_MONITOR_FILE => "/home/guest/cae/fpga/ntpserver/cpu/ip/cpu_xadc_wiz_0_0/cpu_xadc_wiz_0_0/simulation/functional/design.txt"
)
port map
(
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
ip2intc_irpt => ip2intc_irpt,
busy_out => busy_out,
channel_out => channel_out,
eoc_out => eoc_out,
eos_out => eos_out,
ot_out => ot_out,
alarm_out => alm_int,
vp_in => vp_in,
vn_in => vn_in
);
end xilinx;
| gpl-3.0 | 61bb3b173346cb06370603ce3984b9bc | 0.504538 | 4.20819 | false | false | false | false |
esar/hdmilight-v1 | fpga/ipcore_dir/resultRam.vhd | 2 | 6,177 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file resultRam.vhd when simulating
-- the core, resultRam. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY resultRam IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END resultRam;
ARCHITECTURE resultRam_a OF resultRam IS
-- synthesis translate_off
COMPONENT wrapped_resultRam
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_resultRam USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 9,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 512,
c_read_depth_b => 512,
c_read_width_a => 72,
c_read_width_b => 72,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 512,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 72,
c_write_width_b => 72,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_resultRam
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END resultRam_a;
| gpl-2.0 | 222e812c51aeb53013439926c61ac4bb | 0.538935 | 3.89225 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp_dark.vhd | 1 | 3,591 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_dark.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-19
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display pdm dimmer
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-19 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity disp_dark is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppus : in std_logic;
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
disp_blank : OUT std_logic;
disp_status : OUT std_logic
);
end disp_dark;
architecture rtl of disp_dark is
signal pdm_ce_div : std_logic_vector(0 downto 0);
signal pdm_ce : std_logic;
signal pdm_cnt : std_logic_vector(7 downto 0);
signal pdm_term : std_logic;
signal pdm_status : std_logic;
signal status_mux : std_logic;
signal status : std_logic;
begin
-- Divider to run pdm at 2 us intervals
disp_div:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pdm_ce_div <= (others => '0');
pdm_ce <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppus = '1') then
pdm_ce_div <= pdm_ce_div + 1;
end if;
if (tsc_1ppus = '1' and pdm_ce_div = 0) then
pdm_ce <= '1';
else
pdm_ce <= '0';
end if;
end if;
end process;
-- Pulse width modulator counter 512uS cycle
disp_pdmcnt:
process (rst_n, clk) is
variable pdm_sum : std_logic_vector(8 downto 0);
begin
if (rst_n = '0') then
pdm_cnt <= (others => '0');
pdm_term <= '1';
elsif (clk'event and clk = '1') then
if (pdm_ce = '1') then
pdm_sum := '0' & pdm_cnt + disp_pdm;
pdm_cnt <= pdm_sum(pdm_cnt'range);
pdm_term <= not pdm_sum(pdm_sum'left);
end if;
end if;
end process;
-- Status LED mux, generate minimum 10 mS pulse for status
disp_stat_sel:
process (rst_n, clk) is
begin
if (rst_n = '0') then
status_mux <= '0';
elsif (clk'event and clk = '1') then
status_mux <= stat(conv_integer(stat_src));
end if;
end process;
st: pulse_stretch generic map (1000000) port map (rst_n, clk, status_mux, status);
-- Final output register
disp_oreg: delay_sig generic map (1) port map (rst_n, clk, pdm_term, disp_blank);
pdm_status <= not pdm_term and status;
disp_status_oreg: delay_sig generic map (1) port map (rst_n, clk, pdm_status, disp_status);
end rtl;
| gpl-3.0 | 59de183bfc087989f8de5ea083b95cf0 | 0.455305 | 3.795983 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rom_8192x32/simulation/rom_8192x32_synth.vhd | 1 | 6,850 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_8192x32_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY rom_8192x32_synth IS
GENERIC (
C_ROM_SYNTH : INTEGER := 1
);
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE rom_8192x32_synth_ARCH OF rom_8192x32_synth IS
COMPONENT rom_8192x32_exdes
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
GENERIC MAP( C_ROM_SYNTH => C_ROM_SYNTH
)
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(ADDRA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: rom_8192x32_exdes PORT MAP (
--Port A
ADDRA => ADDRA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| gpl-2.0 | a38affb9f268d887f6c50daa4eb79068 | 0.581022 | 3.780353 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_dgen.vhd | 1 | 4,546 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
ENTITY counter_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF counter_fifo_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:counter_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 5a19899ccae8d86eb2901926af443f3d | 0.601408 | 4.244631 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_rng.vhd | 1 | 3,890 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY fifo8to32_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF fifo8to32_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 1d5671a18edf6d615bf0631447d22690 | 0.638303 | 4.341518 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_pkg.vhd | 1 | 11,390 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_mBuf_128x72_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_mBuf_128x72_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_mBuf_128x72_exdes IS
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_mBuf_128x72_pkg;
PACKAGE BODY k7_mBuf_128x72_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_mBuf_128x72_pkg;
| gpl-2.0 | 8546f508058b74eeca55df723d338357 | 0.506848 | 3.886046 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/async_statemachine.vhd | 1 | 44,470 | -----------------------------------------------------------------------------
-- async_statemachine.vhd - entity/architecture pair
-----------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-----------------------------------------------------------------------------
-- Filename: async_statemachine.vhd
-- Version: v1.00.a
-- Description: This state machine generates the control signal for --
-- asynchronous logic of the axi_epc.
-- VHDL-Standard: VHDL'93
-----------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-----------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-----------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.RESET_ACTIVE;
-----------------------------------------------------------------------------
-- Definition of Ports:
-----------------------------------------------------------------------------
-- Definition of Generics
-----------------------------------------------------------------------------
--C_ADDR_TH_CNT_WIDTH -- Address hold counter width generic
--C_ADDR_DATA_CS_TH_CNT_WIDTH -- Address,Data,Chip Select hold width generic
--C_CONTROL_CNT_WIDTH -- Control width generic
--C_DEV_VALID_CNT_WIDTH -- Device valid counter width generic
--C_DEV_RDY_CNT_WIDTH -- Device ready counter width generic
--C_ADS_CNT_WIDTH -- Address strobe counter width generic
--C_WR_REC_CNT_WIDTH -- Write recovery counter width generic
--C_RD_REC_CNT_WIDTH -- Read Recovery counter width generic
--C_NUM_PERIPHERALS -- Number of external peripherals
-----------------------------------------------------------------------------
-- --Inputs
-----------------------------------------------------------------------------
-- BUS2IP_CS -- BUS-to-IP chip select
-- BUS2IP_RNW -- BUS-to-IP Read/Write control signal
-- Asynch_rd_req -- asynch read request
-- Asynch_wr_req -- asynch write request
-- Dev_in_access -- Device in access mode with chip-select
-- Dev_FIFO_access -- Device FIFO access
-- Asynch_prh_rdy -- Asynch peripheral ready for communication
-- Dev_dwidth_match -- peripheral device data width match
-- Dev_dbus_width -- peripheral device data width
-- Dev_bus_multiplexed -- peripheral device addr-data bus muxed
-- Asynch_cycle -- Indication of current cycle of Asynch mode
-----------------------------------------------------------------------------
-- -- outputs
-----------------------------------------------------------------------------
-- *_load command to load the value in the counter
-- Taddr_hold_load -- address hold counter load
-- Tdata_hold_load -- data hold counter load
-- Tdev_valid_load -- device validity check counter
-- Tdev_rdy_load -- peripheral device ready counter load
-- Tcontrol_load -- control width cntr load(in asserted state)
-- Tads_load -- address strobe counter load
-- Trd_recovery_load -- read recovery counter load
-- Twr_recovery_load -- write recovery counter load
-- *_load_ce command to start the counter operation
-- Taddr_hold_load_ce -- address hold counter start
-- Tdata_hold_load_ce -- data hold up counter start
-- Tcontrol_load_ce -- control width counter start
-- Tdev_valid_load_ce -- device validity counter start
-- Tdev_rdy_load_ce -- device ready counter start
-- Tads_load_ce -- address strobe counter start
-- Twr_recovery_load_ce -- Write recovery counter start
-- Trd_muxed_recovery_load_ce -- Read recovery counter start
-- Asynch_Rd -- asynch read
-- Asynch_en -- Asynch enable to latch the rd/wr cycle data
-- Asynch_Wr -- asynch write
-- Asynch_addr_strobe -- Address Address Latch Signal(Strobe)
-- Asynch_addr_data_sel -- Address/Data selector
-- Asynch_data_sel -- asynch data select mode
-- Asynch_chip_select -- Asynch chip select
-- Asynch_addr_cnt_ld -- asynch address latch load/Reset
-- Asynch_addr_cnt_en -- asynch address latch enable
-- Asynch_Wrack -- asynchronous write acknowledge
-- Asynch_Rdack -- asynchronous read acknowledge
-- Asynch_error -- error acknowledge
-- -- Clocks and reset
-- Clk
-- Rst
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity async_statemachine is
generic
(
C_ADDR_TH_CNT_WIDTH : integer;
C_ADDR_DATA_CS_TH_CNT_WIDTH : integer;
C_CONTROL_CNT_WIDTH : integer;
C_DEV_VALID_CNT_WIDTH : integer;
C_DEV_RDY_CNT_WIDTH : integer;
C_ADS_CNT_WIDTH : integer;
C_WR_REC_NM_CNT_WIDTH : integer;
C_RD_REC_NM_CNT_WIDTH : integer;
C_WR_REC_M_CNT_WIDTH : integer;
C_RD_REC_M_CNT_WIDTH : integer;
C_NUM_PERIPHERALS : integer
);
port (
-- inputs form asynch_cntl
Bus2IP_CS : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_RNW : in std_logic;
Asynch_rd_req : in std_logic;
Asynch_wr_req : in std_logic;
Dev_in_access : in std_logic;
Dev_FIFO_access : in std_logic;
Asynch_prh_rdy : in std_logic;
-- inputs from top_level_file
Dev_dwidth_match : in std_logic;
Dev_bus_multiplexed : in std_logic;
-- input from IPIF
-- input from data steering logic
Asynch_cycle : in std_logic;
-- outputs to IPIF
Asynch_Wrack : out std_logic;
Asynch_Rdack : out std_logic;
Asynch_error : out std_logic;
Asynch_start : out std_logic;
-- outputs to counters
Taddr_hold_load : out std_logic;
Tdata_hold_load : out std_logic;
Tdev_valid_load : out std_logic;
Tdev_rdy_load : out std_logic;
Tcontrol_load : out std_logic;
Tads_load : out std_logic;
Twr_recovery_load : out std_logic;
Trd_recovery_load : out std_logic;
Taddr_hold_load_ce : out std_logic;
Tdata_hold_load_ce : out std_logic;
Tcontrol_load_ce : out std_logic;
Tdev_valid_load_ce : out std_logic;
Tdev_rdy_load_ce : out std_logic;
Tads_load_ce : out std_logic;
Twr_muxed_recovery_load_ce : out std_logic;
Trd_muxed_recovery_load_ce : out std_logic;
Twr_non_muxed_recovery_load_ce: out std_logic;
Trd_non_muxed_recovery_load_ce: out std_logic;
-- output to data_steering_logic file
Asynch_Rd : out std_logic;
Asynch_en : out std_logic;
Asynch_Wr : out std_logic;
Asynch_addr_strobe : out std_logic;
Asynch_addr_data_sel : out std_logic;
Asynch_data_sel : out std_logic;
Asynch_chip_select : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Asynch_addr_cnt_ld : out std_logic;
Asynch_addr_cnt_en : out std_logic;
Taddr_hold_cnt : in std_logic_vector(0 to C_ADDR_TH_CNT_WIDTH-1);
Tcontrol_wdth_cnt : in std_logic_vector(0 to C_CONTROL_CNT_WIDTH-1);
Tdevrdy_wdth_cnt : in std_logic_vector(0 to C_DEV_RDY_CNT_WIDTH-1);
Twr_muxed_rec_cnt : in std_logic_vector(0 to C_WR_REC_M_CNT_WIDTH-1);
Trd_muxed_rec_cnt : in std_logic_vector(0 to C_RD_REC_M_CNT_WIDTH-1);
Twr_non_muxed_rec_cnt : in std_logic_vector(0 to C_WR_REC_NM_CNT_WIDTH-1);
Trd_non_muxed_rec_cnt : in std_logic_vector(0 to C_RD_REC_NM_CNT_WIDTH-1);
Tdev_valid_cnt : in std_logic_vector(0 to C_DEV_VALID_CNT_WIDTH-1);
Tads_cnt : in std_logic_vector(0 to C_ADS_CNT_WIDTH-1);
Taddr_data_cs_hold_cnt: in std_logic_vector
(0 to C_ADDR_DATA_CS_TH_CNT_WIDTH-1);
-- Clocks and reset
Clk : in std_logic;
Rst : in std_logic
);
end entity async_statemachine;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of async_statemachine is
-- all outputs temp signals
signal taddr_hold_load_i : std_logic;
signal tdev_valid_load_i : std_logic;
signal tdev_rdy_load_i : std_logic;
signal tads_load_i : std_logic;
--signal tdata_hold_load_i : std_logic;
signal tcontrol_load_i : std_logic;
signal twr_recovery_load_i : std_logic;
signal trd_recovery_load_i : std_logic;
signal taddr_hold_load_ce_i : std_logic;
signal tdata_hold_load_ce_i : std_logic;
signal tcontrol_load_ce_i : std_logic;
signal tdev_valid_load_ce_i : std_logic;
signal tdev_rdy_load_ce_i : std_logic;
signal tads_load_ce_i : std_logic;
signal twr_muxed_recovery_ld_ce_i : std_logic;
signal trd_muxed_recovery_ld_ce_i : std_logic;
signal trd_non_muxed_recovery_ld_ce_i : std_logic;
signal twr_non_muxed_recovery_ld_ce_i : std_logic;
signal asynch_Rd_i : std_logic;
signal asynch_en_i : std_logic;-- this signal latches the data
--at every read and write operation
signal asynch_Wr_i : std_logic;
signal asynch_addr_strobe_i : std_logic;
signal asynch_addr_data_sel_i : std_logic;
signal asynch_chip_select_i : std_logic;
signal asynch_chip_select_n : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal asynch_addr_cnt_ld_i : std_logic;
signal asynch_addr_cnt_en_i : std_logic;
signal asynch_Wrack_i : std_logic;
signal asynch_Rdack_i : std_logic;
signal asynch_error_i : std_logic;
signal asynch_start_i : std_logic;--start of asynch cycle
signal data_sel : std_logic;--asynch address phase indicator
signal asynch_data_sel_i : std_logic;
-- The counter will start decrementing the value loaded, at the next clock. so,
-- here one clock is required to start decrementing the counter. To maintain the
-- exact count, the final value of the counter is set to '1' instaed of '0'.
constant ADDR_TH_CNTR2_END:
std_logic_vector(0 to C_ADDR_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_ADDR_TH_CNT_WIDTH);
-- control hold end count
constant CONTROL_TH_CNTR3_END:
std_logic_vector(0 to C_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_CONTROL_CNT_WIDTH);
-- dev rdy pulse width end count
constant DEV_RDY_CNTR4_END:
std_logic_vector(0 to C_DEV_RDY_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_DEV_RDY_CNT_WIDTH);
-- data set up pulse width
constant DEV_VALID_CNTR7_END
: std_logic_vector(0 to C_DEV_VALID_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_DEV_VALID_CNT_WIDTH);
-- address strobe counter end value
constant ADS_CNTR8_END
: std_logic_vector(0 to C_ADS_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_ADS_CNT_WIDTH);
-- address,data, chip select hold width
constant ADDR_DATA_CS_TH_CNTR12_END:
std_logic_vector(0 to C_ADDR_DATA_CS_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_ADDR_DATA_CS_TH_CNT_WIDTH);
-- read recovery pulse width end count
constant RD_MUXED_RECOVERY_CNTR9_END:
std_logic_vector(0 to C_RD_REC_M_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_RD_REC_M_CNT_WIDTH);
constant RD_NON_MUXED_RECOVERY_CNTR9_END:
std_logic_vector(0 to C_RD_REC_NM_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_RD_REC_NM_CNT_WIDTH);
-- write recovery pulse width end count
constant WR_MUXED_RECOVERY_CNTR5_END:
std_logic_vector(0 to C_WR_REC_M_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_WR_REC_M_CNT_WIDTH);
constant WR_NON_MUXED_RECOVERY_CNTR5_END:
std_logic_vector(0 to C_WR_REC_NM_CNT_WIDTH-1)
:= conv_std_logic_vector(1,C_WR_REC_NM_CNT_WIDTH);
-----------------------------------------------------------------------------
-- type declaration
type INTEGER_ARRAY is array (natural range <>) of integer;
-----------------------------------------------------------------------------
type COMMAND_STATE_TYPE is (
IDLE,DUMMY_ADS,START_STATE,
DUMMY_ST,
ADS_ASSERT, -- address set up time/ strobe time
NM_CONTROL_ASSERT, -- non-muxed control assert
M_CONTROL_ASSERT, -- muxed control assert
DEV_VALID, -- device valid in non-mux case
DEV_RDY, -- device ready check in non-mux case
DEV_VALID_M, -- device valid check in muxed case
DEV_RDY_M, -- multiplexed device ready check state
CONTROL_DEASSERT, -- control deassert
ACK_GEN_NON_MUXED, -- non-muxed acknowledge generation
ACK_GEN_MUXED, -- muxed acknowledge generation
WR_MUXED_RECOVERY, -- muxed write recovery
WR_NON_MUXED_RECOVERY, -- non muxed write recovery
RD_MUXED_RECOVERY, -- muxed read recovery
RD_NON_MUXED_RECOVERY -- non muxed read recovery
);
signal command_ns : COMMAND_STATE_TYPE;
signal command_cs : COMMAND_STATE_TYPE;
-----------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- COMMAND_ASYNCH_REG: process for asynch state next state flip-flop logic
-------------------------------------------------------------------------------
COMMAND_ASYNCH_REG: process (Clk)
begin
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
command_cs <= IDLE;
else
command_cs <= command_ns;
end if;
end if;
end process COMMAND_ASYNCH_REG;
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- CMB_ASYNCH_PROCESS
-----------------------------------------------------------------------------
-- This process generates the control signals, which will communicate with
-- other part of logic. The control signals include write, read, acknowledge,
-- error acknowledge and variouos load enable signals for the epc_counter.vhd
-----------------------------------------------------------------------------
CMB_ASYNCH_PROCESS: process (
command_cs,
Dev_in_access,
Dev_FIFO_access,
Asynch_rd_req,
Asynch_wr_req,
Asynch_prh_rdy,
Asynch_cycle,
Dev_dwidth_match,
Dev_bus_multiplexed,
Taddr_hold_cnt,
Tcontrol_wdth_cnt,
Tdevrdy_wdth_cnt,
Twr_muxed_rec_cnt,
Trd_muxed_rec_cnt,
Twr_non_muxed_rec_cnt,
Trd_non_muxed_rec_cnt,
Tdev_valid_cnt,
Tads_cnt,
Taddr_data_cs_hold_cnt
)
begin
--- default signal conditions
--these signals are activated only for single clock cycle
asynch_Wrack_i <= '0';
asynch_Rdack_i <= '0';
asynch_error_i <= '0';
asynch_start_i <= '0';
asynch_addr_cnt_en_i <= '0';
asynch_addr_cnt_ld_i <= '0';
asynch_addr_data_sel_i <= '0';
asynch_addr_strobe_i <= '0';
asynch_chip_select_i <= '1';
data_sel <= '0';
asynch_en_i <= '0';
asynch_wr_i <= '0';
asynch_rd_i <= '0';
tads_load_ce_i <= '0';
taddr_hold_load_ce_i <= '0';
tcontrol_load_ce_i <= '0';
tdev_valid_load_ce_i <= '0';
tdata_hold_load_ce_i <= '0';
tdev_rdy_load_ce_i <= '0';
trd_muxed_recovery_ld_ce_i <= '0';
twr_muxed_recovery_ld_ce_i <= '0';
trd_non_muxed_recovery_ld_ce_i<= '0';
twr_non_muxed_recovery_ld_ce_i<= '0';
taddr_hold_load_i <= '0';
tdev_valid_load_i <= '0';
tdev_rdy_load_i <= '0';
tads_load_i <= '0';
command_ns <= IDLE;
tcontrol_load_i <= '0';
trd_recovery_load_i <= '0';
twr_recovery_load_i <= '0';
asynch_addr_cnt_ld_i <= '0';
case command_cs is
-------------------------- IDLE --------------------------
-------------------------- IDLE --------------------------
when IDLE =>
-- Determines the conditional signal generation
-- the counters should be loaded with the final value always
-- these counters are downcounters
taddr_hold_load_i <= '1';
tdev_valid_load_i <= '1';
tdev_rdy_load_i <= '1';
tads_load_i <= '1';
tcontrol_load_i <= '1';
twr_recovery_load_i <= '1';
trd_recovery_load_i <= '1';
asynch_wr_i <= '0';
asynch_rd_i <= '0';
asynch_en_i <= '0';
asynch_addr_strobe_i <= '0';
asynch_addr_data_sel_i <= '0';
data_sel <= '0';
asynch_chip_select_i <= '1';
asynch_addr_cnt_ld_i <= '1';--reset signal for cntr load
-- check if access is given and if the device is multiplexed.
-- if yes, start the address load signal. this will initialize the address
-- counter and jump to START_STATE
if(Dev_in_access='1')then
if (Asynch_rd_req = '1' or Asynch_wr_req = '1') then
asynch_chip_select_i <= '1';
if (Dev_bus_multiplexed= '1') then
asynch_addr_data_sel_i <= '1';
else
asynch_addr_data_sel_i <= '0';
end if;
command_ns <= START_STATE;
else
command_ns <= IDLE;
end if;
else
command_ns <= IDLE;
end if;
-- START_STATE -- from this state onwards start the proper execution of core.
-- enable the following signals : address strobe, chip select, asynch start,
-- asynch cntr, address select signals
when START_STATE =>
asynch_chip_select_i <= '0';
asynch_start_i <= '1';
if (Dev_bus_multiplexed= '1') then
tdev_valid_load_ce_i <= '1';-- start the device valid counter
tdev_rdy_load_ce_i <= '1';-- start the device max wait time countr
asynch_addr_data_sel_i <= '1';
command_ns <= DEV_VALID_M;
else
tads_load_ce_i <= '1';
command_ns <= NM_CONTROL_ASSERT;
end if;
-- below is non multiplexed part of the code...
-------------------------------------------------------------------------------
-- NM_CONTROL_ASSERT -> Generates the write/read control signal in non-mxed mode
-- It will check for the address hold counter to be over.
-- If the address hold cntr is asserted then the "address data select"
-- line will indicate the data phase.
-- Also starts device valid and device ready counter
-------------------------------------------------------------------------------
when NM_CONTROL_ASSERT =>
asynch_chip_select_i <= '0';
tads_load_ce_i <= '1';
if(Tads_cnt = ADS_CNTR8_END)then
tads_load_ce_i <= '0';
asynch_wr_i <= Asynch_wr_req;
asynch_rd_i <= Asynch_rd_req;
data_sel <= '1';
tdev_valid_load_ce_i <= '1';
tdev_rdy_load_ce_i <= '1';
command_ns <= DEV_VALID;
else
command_ns <= NM_CONTROL_ASSERT;
end if;
-------------------------- DEV_VALID --------------------------
-- DEV_VALID -> Decides the state of the device.if the device is in valid state
-- then further communication with the device starts
-- If the device does not respond with in the given time, then state machine
-- will enter into the device ready check state.In the device ready check state
-- the design will wait till the end of device ready period. else the
-- communication is abruptly terminated and the
-- state machine will reset to IDLE state.
when DEV_VALID=>
asynch_chip_select_i <= '0';
data_sel <= '1';
asynch_wr_i <= Asynch_wr_req;
asynch_rd_i <= Asynch_rd_req;
tdev_valid_load_ce_i <= '1';
tdev_rdy_load_ce_i <= '1';
if ((Tdev_valid_cnt = DEV_VALID_CNTR7_END)) then
tdev_valid_load_ce_i <= '0';
--asynch_en_i <= Asynch_prh_rdy;
tdev_rdy_load_ce_i <= '1';
command_ns <= DEV_RDY;
else
command_ns <= DEV_VALID;
end if;
-- DEV_RDY : is meant for confirmation that the device is ready
when DEV_RDY=>
asynch_chip_select_i <= '0';
data_sel <= '1';
asynch_wr_i <= Asynch_wr_req;
asynch_rd_i <= Asynch_rd_req;
tdev_rdy_load_ce_i <= '1';
taddr_hold_load_i <= '1';
if (Asynch_prh_rdy='1') then
asynch_en_i <= '1';
tcontrol_load_ce_i <= '1';
command_ns <= CONTROL_DEASSERT;
elsif((Tdevrdy_wdth_cnt=DEV_RDY_CNTR4_END)and(Asynch_prh_rdy='0'))then
tdev_rdy_load_ce_i <= '0';
asynch_error_i <= '1';--generate error
asynch_Wrack_i <= Asynch_wr_req;--generate wr ack
asynch_Rdack_i <= Asynch_rd_req;--generate rd ack
asynch_chip_select_i <= '1';--deactivate chip select
asynch_wr_i <= '0';--deactivate control signal
asynch_rd_i <= '0';--deactivate control signal
command_ns <= IDLE;
else
command_ns <= DEV_RDY;
end if;
-------------------------- CONTROL_DEASSERT --------------------------
-- Deactivates the control signal depending upon the assertion of the signals
-- from the epc_counter.vhd. this is common state for mux and non-mux design.
-- starts the chip select deasert counter.
when CONTROL_DEASSERT =>
asynch_chip_select_i <= '0';
data_sel <= '1';
asynch_en_i <= '1';
asynch_wr_i <= Asynch_wr_req;
asynch_rd_i <= Asynch_rd_req;
tcontrol_load_ce_i <= '1';
if((Tcontrol_wdth_cnt=CONTROL_TH_CNTR3_END)) then
tcontrol_load_ce_i <= '0';
tdata_hold_load_ce_i<= '1';
asynch_wr_i <= '0';
asynch_rd_i <= '0';
asynch_en_i <= '0';
if(Dev_bus_multiplexed= '1') then
-- asynch_en_i <= '1';
command_ns <= ACK_GEN_MUXED;
else
-- asynch_en_i <= '0';
command_ns <= ACK_GEN_NON_MUXED;
end if;
else
command_ns <= CONTROL_DEASSERT;
end if;
-- ACK_GEN_NON_MUXED -------------------------------
when ACK_GEN_NON_MUXED =>
asynch_chip_select_i <= '0';
tdata_hold_load_ce_i <= '1';
data_sel <= '1';
tdev_valid_load_i <= '1';--load the device valid counter
tads_load_i <= '1';--load the ads counter
trd_recovery_load_i <= '1';--load the rd recovery cntr
twr_recovery_load_i <= '1';--load the wr recovery counter
tcontrol_load_i <= '1';--load the control width counter
if(Taddr_data_cs_hold_cnt = ADDR_DATA_CS_TH_CNTR12_END) then
tdata_hold_load_ce_i <= '0';
if(Asynch_cycle = '1' and Dev_dwidth_match = '1') then
asynch_addr_cnt_en_i <= '1';
data_sel <= '0';
else
asynch_addr_cnt_en_i <= '0';
asynch_Wrack_i <= Asynch_wr_req;
asynch_Rdack_i <= Asynch_rd_req;
data_sel <= '0';
end if;
if(Asynch_wr_req = '1') then
twr_non_muxed_recovery_ld_ce_i <= '1';
command_ns <= WR_NON_MUXED_RECOVERY;
elsif(Asynch_rd_req = '1') then
trd_non_muxed_recovery_ld_ce_i <= '1';
command_ns <= RD_NON_MUXED_RECOVERY;
end if;
else
command_ns <= ACK_GEN_NON_MUXED;
end if;
-- READ NON-MUXED RECOVERY state -> this is the recovery period between
---------------------------------- two consecutive reads in non-mux mode
when RD_NON_MUXED_RECOVERY =>
trd_non_muxed_recovery_ld_ce_i <= '1';
asynch_chip_select_i <= '0';
if (Trd_non_muxed_rec_cnt = RD_NON_MUXED_RECOVERY_CNTR9_END) then
trd_non_muxed_recovery_ld_ce_i <= '0';
if(Asynch_cycle = '1' and Dev_dwidth_match = '1') then
asynch_chip_select_i <= '0';
tads_load_ce_i <= '1';
command_ns <= NM_CONTROL_ASSERT;
else
command_ns <= IDLE;
end if;
else
command_ns <= RD_NON_MUXED_RECOVERY;
end if;
-- WR_NON_MUXED_RECOVERY : this is the recovery period between two consecutive
------------------------ writes in non-mux mode
when WR_NON_MUXED_RECOVERY =>
twr_non_muxed_recovery_ld_ce_i <= '1';
asynch_chip_select_i <= '0';
if (Twr_non_muxed_rec_cnt = WR_NON_MUXED_RECOVERY_CNTR5_END) then
twr_non_muxed_recovery_ld_ce_i <= '0';
if(Asynch_cycle = '1' and Dev_dwidth_match = '1') then
asynch_chip_select_i <= '0';
tads_load_ce_i <= '1';
command_ns <=NM_CONTROL_ASSERT;
else
command_ns <= IDLE;
end if;
else
command_ns <= WR_NON_MUXED_RECOVERY;
end if;
-- below is part of multiplexed code
------------------------------------
-------------------------------------------------------------------------------
-- if the address set up counter ends then check whether strobe counter width
-- is over, then the address strobe signal is deasserted and address hold sgnl
-- is enabled.
when ADS_ASSERT =>
asynch_addr_data_sel_i <= '1';
asynch_addr_strobe_i <= '1';
asynch_chip_select_i <= '0';
tads_load_ce_i <= '1';
if(Tads_cnt = ADS_CNTR8_END)then
tads_load_ce_i <= '0';
asynch_addr_strobe_i <= '0';
command_ns <= DUMMY_ADS;
else
command_ns <= ADS_ASSERT;
end if;
-----------------------------------------------
when DUMMY_ADS =>
asynch_addr_data_sel_i <= '0';
asynch_chip_select_i <= '0';
taddr_hold_load_ce_i <= '1';
command_ns <= M_CONTROL_ASSERT;
-- M_CONTROL_ASSERT state -> this state generates the multiplexed control sign
-- al
when M_CONTROL_ASSERT =>
asynch_addr_data_sel_i <= '0';
asynch_chip_select_i <= '0';
taddr_hold_load_ce_i <= '1';
if((Taddr_hold_cnt = ADDR_TH_CNTR2_END))then
asynch_wr_i <= Asynch_wr_req;
asynch_rd_i <= Asynch_rd_req;
asynch_addr_data_sel_i <= '0';
taddr_hold_load_ce_i <= '0';
data_sel <= '1';
if(Asynch_wr_req = '1') then
asynch_en_i <= '1';
tcontrol_load_ce_i <= '1';
command_ns <= CONTROL_DEASSERT;
elsif(Asynch_rd_req = '1') then
command_ns <= DUMMY_ST;
end if;
else
command_ns <= M_CONTROL_ASSERT;
end if;
---------------------------------------------------------
when DUMMY_ST =>
asynch_chip_select_i <= '0';
asynch_wr_i <= Asynch_wr_req;
asynch_rd_i <= Asynch_rd_req;
asynch_en_i <= '1';
tcontrol_load_ce_i <= '1';
data_sel <= '1';
command_ns <= CONTROL_DEASSERT;
------------------------------------------------------------------------------
when ACK_GEN_MUXED =>
asynch_chip_select_i <= '0';
tdata_hold_load_ce_i <= '1';
data_sel <= '1';
tads_load_i <= '1';
tdev_valid_load_i <= '1';
trd_recovery_load_i <= '1';
twr_recovery_load_i <= '1';
tcontrol_load_i <= '1';
taddr_hold_load_i <= '1';
if(Taddr_data_cs_hold_cnt = ADDR_DATA_CS_TH_CNTR12_END) then
tdata_hold_load_ce_i <= '0';
if(Asynch_cycle = '1' and Dev_dwidth_match = '1') then
data_sel <= '0';
else
asynch_addr_cnt_en_i <= '0';
asynch_Wrack_i <= Asynch_wr_req;
asynch_Rdack_i <= Asynch_rd_req;
data_sel <= '0';
--asynch_chip_select_i<= not(Dev_FIFO_access);
end if;
if(Asynch_wr_req = '1') then
twr_muxed_recovery_ld_ce_i <= '1';
command_ns <= WR_MUXED_RECOVERY;
elsif(Asynch_rd_req = '1') then
trd_muxed_recovery_ld_ce_i <= '1';
command_ns <= RD_MUXED_RECOVERY;
end if;
tads_load_i <= '1';
else
command_ns <= ACK_GEN_MUXED;
end if;
-- RD_MUXED_RECOVERY STATE ->
-- Determines the recovery time of the transaction
-- Depending upon the data width, will jump to the idle state or,
-- will generate the next write/read cycles and at the end generates
-- acknowledge to IPIF.
-- READ MUXED RECOVERY
-----------------------
when RD_MUXED_RECOVERY =>
trd_muxed_recovery_ld_ce_i <= '1';
asynch_chip_select_i <= '0';
if (Trd_muxed_rec_cnt = RD_MUXED_RECOVERY_CNTR9_END) then
trd_muxed_recovery_ld_ce_i <= '0';
if(Asynch_cycle = '1' and Dev_dwidth_match = '1') then
if(Dev_FIFO_access = '1') then
taddr_hold_load_ce_i <= '1';
asynch_addr_cnt_en_i <= '1';
command_ns <= M_CONTROL_ASSERT;
else
tdev_rdy_load_ce_i <= '1';
tdev_valid_load_ce_i <= '1';
asynch_addr_cnt_en_i <= '1';
asynch_addr_data_sel_i <= '1';
command_ns <= DEV_VALID_M;
end if;
else
command_ns <= IDLE;
end if;
else
command_ns <= RD_MUXED_RECOVERY;
end if;
-- These are muxed and non muxed write recovery states. Depending upon the
-- configured device mux and non mux property, particular state will be
-- executed.
-- WR_MUXED_RECOVERY
--------------------
when WR_MUXED_RECOVERY =>
twr_muxed_recovery_ld_ce_i <= '1';
asynch_chip_select_i <= '0';
if (Twr_muxed_rec_cnt = WR_MUXED_RECOVERY_CNTR5_END) then
twr_muxed_recovery_ld_ce_i <= '0';
if(Asynch_cycle = '1' and Dev_dwidth_match = '1') then
if(Dev_FIFO_access = '1') then
taddr_hold_load_ce_i <= '1';
asynch_addr_cnt_en_i <= '1';
command_ns <= M_CONTROL_ASSERT;
else
tdev_rdy_load_ce_i <= '1';
tdev_valid_load_ce_i <= '1';
asynch_addr_cnt_en_i <= '1';
asynch_addr_data_sel_i <= '1';
command_ns <= DEV_VALID_M;
end if;
else
command_ns <= IDLE;
end if;
else
command_ns <= WR_MUXED_RECOVERY;
end if;
-- DEV_VALID_M state : In case of multiplexing logic, check first if the device
-- is ready for communication. this is required as the same data lines carry the
-- address (in initial phase) and data (in later phase). the external device
-- should register the address first before the lines swith over to data.
-- this is confirm check for device ready signal.
when DEV_RDY_M =>
asynch_addr_data_sel_i <= '1'; --address selection on common line
asynch_chip_select_i <= '0'; --assert chip select
tdev_rdy_load_ce_i <= '1'; --device ready max time counter
--active signal
if(Asynch_prh_rdy='1') then
asynch_addr_strobe_i <= '1';--enable address strobe sig
tads_load_ce_i <= '1';--start the ads counter
tdev_rdy_load_ce_i <= '0';-- deactivate the dev max
-- time cntr,as its not
-- required now
command_ns <= ADS_ASSERT;
elsif((Tdevrdy_wdth_cnt=DEV_RDY_CNTR4_END)and(Asynch_prh_rdy='0'))then
tdev_rdy_load_ce_i <= '0'; -- deactivate the dev max time cntr
asynch_error_i <= '1'; --generate error
asynch_Wrack_i <= Asynch_wr_req;--generate wr ack
asynch_Rdack_i <= Asynch_rd_req;--generate rd ack
asynch_chip_select_i <= '1'; --deactivate chip select
command_ns <= IDLE;
else
command_ns <= DEV_RDY_M;
end if;
-- DEV_VALID_M: This state validates the readiness of the device in multiplexing
-- mode
when DEV_VALID_M =>
asynch_addr_data_sel_i <= '1'; --address selection on common line
asynch_chip_select_i <= '0'; --assert chip select
tdev_valid_load_ce_i <= '1'; --dev valid counter is active till
--the counter exits and the
--external device is not ready
tdev_rdy_load_ce_i <= '1'; --device ready max time counter
--active signal
-- the below condition checks that the device valid counter has ended
-- when the device is not ready
if((Tdev_valid_cnt = DEV_VALID_CNTR7_END)or(Asynch_prh_rdy='1')) then
tdev_valid_load_ce_i <= '0';--deactive dev valid counter
tdev_rdy_load_ce_i <= '1';
command_ns <= DEV_RDY_M;
else
command_ns <= DEV_VALID_M;
end if;
-----------------------------------------------------------------------------
-- coverage off
when others => command_ns <=IDLE;
-- coverage on
end case;
end process CMB_ASYNCH_PROCESS;
-----------------------------------------------------------------------------
-- NAME: ASYNC_CS_SEL_PROCESS
-----------------------------------------------------------------------------
-- Description: Drives an internal signal (ASYNC_CS_N) from the asynchronous
-- control logic to be used as the chip select for the external
-- peripheral device
-----------------------------------------------------------------------------
ASYNC_CS_SEL_PROCESS: process (Bus2IP_CS,asynch_chip_select_i) is
begin
asynch_chip_select_n <= (others => '1');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Bus2IP_CS(i) = '1') then
asynch_chip_select_n(i) <= not(Bus2IP_CS(i) and
(not asynch_chip_select_i));
end if;
end loop;
end process ASYNC_CS_SEL_PROCESS;
-----------------------------------------------------------------------------
asynch_data_sel_i <= asynch_addr_data_sel_i or (data_sel and (not BUS2IP_RNW));
-----------------------------------------------------------------------------
REGISTERED_OP: process (Clk)
begin
if (Clk'event and Clk = '1') then
Taddr_hold_load_ce <= taddr_hold_load_ce_i;
Tdata_hold_load_ce <= tdata_hold_load_ce_i;
Tcontrol_load_ce <= tcontrol_load_ce_i;
Tdev_valid_load_ce <= tdev_valid_load_ce_i;
Tdev_rdy_load_ce <= tdev_rdy_load_ce_i;
Tads_load_ce <= tads_load_ce_i;
Twr_muxed_recovery_load_ce <= twr_muxed_recovery_ld_ce_i;
Trd_muxed_recovery_load_ce <= trd_muxed_recovery_ld_ce_i;
Twr_non_muxed_recovery_load_ce <= twr_non_muxed_recovery_ld_ce_i;
Trd_non_muxed_recovery_load_ce <= trd_non_muxed_recovery_ld_ce_i;
Asynch_Rd <= not(asynch_Rd_i);
Asynch_Wr <= not(asynch_Wr_i);
Asynch_en <= asynch_en_i;
Asynch_chip_select <= asynch_chip_select_n;
Asynch_addr_strobe <= asynch_addr_strobe_i;
Asynch_addr_data_sel <= asynch_addr_data_sel_i;
Asynch_data_sel <= asynch_data_sel_i;
end if;
end process REGISTERED_OP;
------------------------------------------------------------------------------
Tdata_hold_load <= '1';
Tcontrol_load <= tcontrol_load_i;
Trd_recovery_load <= trd_recovery_load_i;
Twr_recovery_load <= twr_recovery_load_i;
Taddr_hold_load <= taddr_hold_load_i;
Tdev_valid_load <= tdev_valid_load_i;
Tdev_rdy_load <= tdev_rdy_load_i;
Tads_load <= tads_load_i;
Asynch_addr_cnt_en <= asynch_addr_cnt_en_i;
Asynch_addr_cnt_ld <= asynch_addr_cnt_ld_i;
Asynch_Wrack <= asynch_Wrack_i;
Asynch_Rdack <= asynch_Rdack_i;
Asynch_error <= asynch_error_i;
Asynch_start <= asynch_start_i;
end imp;
------------------------------------------------------------------------------
--End of File async_statemachine.vhd
------------------------------------------------------------------------------
| gpl-3.0 | 8f9bd12e8b2a984b862d0f1159b0bbdc | 0.468608 | 3.963811 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_tb.vhd | 1 | 6,155 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_tb IS
END ENTITY;
ARCHITECTURE k7_prime_fifo_plain_arch OF k7_prime_fifo_plain_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from k7_prime_fifo_plain_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of k7_prime_fifo_plain_synth
k7_prime_fifo_plain_synth_inst:k7_prime_fifo_plain_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 77
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | 17b840d5a19c68b313e4e676003dc401 | 0.617384 | 4.060026 | false | false | false | false |
UnofficialRepos/OSVVM | RandomProcedurePkg.vhd | 1 | 6,491 | --
-- File Name : RandomProcedurePkg.vhd
-- Design Unit Name : RandomProcedurePkg
-- Revision : STANDARD VERSION
--
-- Maintainer : Jim Lewis email : [email protected]
-- Contributor(s) :
-- Jim Lewis email: [email protected]
-- Lars Asplund email: [email protected] - RandBool, RandSl, RandBit, DistBool, DistSl, DistBit
-- *
--
-- * In writing procedures normal, poisson, the following sources were referenced :
-- Wikipedia
-- package rnd2 written by John Breen and Ken Christensen
-- package RNG written by Gnanasekaran Swaminathan
--
--
-- Description :
-- A minimal randomization package using procedures that
-- supports CoveragePkg.vhd.
-- Does not use protected types.
-- Does not use VHDL-2019.
--
-- Developed for :
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http ://www.SynthWorks.com
--
-- Revision History :
-- Date Version Description
-- 05/2021 2021/05 Refactored from RandomPkg.vhd
-- Needed minimal set of procedures to support randomization in CoveragePkg
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2021 by SynthWorks Design Inc.
-- Copyright (C) 2021 by OSVVM Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.SortListPkg_int.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.numeric_std_unsigned.all ;
use ieee.math_real.all ;
package RandomProcedurePkg is
------------------------------------------------------------
--
-- Uniform
-- Generate a random number with a Uniform distribution
--
------------------------------------------------------------
procedure Uniform (RandomSeed : inout RandomSeedType; R : out integer; Min, Max : integer) ;
procedure Uniform (RandomSeed : inout RandomSeedType; R : out integer; Min, Max : integer ; Exclude : integer_vector) ;
alias RandInt is Uniform [RandomSeedType, integer, integer, integer] ;
alias RandInt is Uniform [RandomSeedType, integer, integer, integer, integer_vector] ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
--- ///////////////////////////////////////////////////////////////////////////
-----------------------------------------------------------------
procedure DistInt (RandomSeed : inout RandomSeedType; R : out integer; Weight : integer_vector) ;
end RandomProcedurePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomProcedurePkg is
------------------------------------------------------------
--
-- Uniform
-- Generate a random number with a Uniform distribution
--
------------------------------------------------------------
procedure Uniform (RandomSeed : inout RandomSeedType; R : out integer; Min, Max : integer) is
------------------------------------------------------------
variable rRandomVal : real ;
begin
-- Checks done in CoveragePkg
-- AlertIf (OSVVM_RANDOM_ALERTLOG_ID, Max < Min, "RandomPkg.Uniform: Max < Min", FAILURE) ;
Uniform(rRandomVal, RandomSeed) ;
R := scale(rRandomVal, Min, Max) ;
end procedure Uniform ;
------------------------------------------------------------
procedure Uniform (RandomSeed : inout RandomSeedType; R : out integer; Min, Max : integer ; Exclude : integer_vector) is
------------------------------------------------------------
variable iRandomVal : integer ;
variable ExcludeList : SortListPType ;
variable count : integer ;
begin
ExcludeList.add(Exclude, Min, Max) ;
count := ExcludeList.count ;
Uniform(RandomSeed, iRandomVal, Min, Max - count) ;
-- adjust count, note iRandomVal changes while checking.
for i in 1 to count loop
exit when iRandomVal < ExcludeList.Get(i) ;
iRandomVal := iRandomVal + 1 ;
end loop ;
ExcludeList.erase ;
R := iRandomVal ;
end procedure Uniform ;
--- ///////////////////////////////////////////////////////////////////////////
--
-- Basic Discrete Distributions
-- Always uses Uniform
--
--- ///////////////////////////////////////////////////////////////////////////
-----------------------------------------------------------------
procedure DistInt (RandomSeed : inout RandomSeedType; R : out integer; Weight : integer_vector) is
-----------------------------------------------------------------
variable DistArray : integer_vector(weight'range) ;
variable sum : integer ;
variable iRandomVal : integer ;
begin
DistArray := Weight ;
sum := 0 ;
for i in DistArray'range loop
DistArray(i) := DistArray(i) + sum ;
if DistArray(i) < sum then
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.DistInt: negative weight or sum > 31 bits", FAILURE) ;
R := DistArray'low ; -- allows debugging vs integer'left, out of range
end if ;
sum := DistArray(i) ;
end loop ;
if sum >= 1 then
Uniform(RandomSeed, iRandomVal, 1, sum) ;
for i in DistArray'range loop
if iRandomVal <= DistArray(i) then
R := i ;
return ;
end if ;
end loop ;
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.DistInt: randomization failed", FAILURE) ;
else
Alert(OSVVM_RANDOM_ALERTLOG_ID, "RandomPkg.DistInt: No randomization weights", FAILURE) ;
end if ;
R := DistArray'low ; -- allows debugging vs integer'left, out of range
end procedure DistInt ;
end RandomProcedurePkg ;
| artistic-2.0 | 1623e661122f3a47afd93d4fd610e2b1 | 0.544908 | 4.467309 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_synth.vhd | 1 | 10,041 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_prime_fifo_plain_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF k7_prime_fifo_plain_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: k7_prime_fifo_plain_dgen
GENERIC MAP (
C_DIN_WIDTH => 72,
C_DOUT_WIDTH => 72,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: k7_prime_fifo_plain_dverif
GENERIC MAP (
C_DOUT_WIDTH => 72,
C_DIN_WIDTH => 72,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: k7_prime_fifo_plain_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 72,
C_DIN_WIDTH => 72,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
k7_prime_fifo_plain_inst : k7_prime_fifo_plain_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | bfdad34a14e630b69f98607cfd055c31 | 0.457325 | 4.039019 | false | false | false | false |
neogeodev/NeoGeoFPGA-sim | CPUs/tg68k.vhd | 1 | 7,381 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- --
-- Copyright (c) 2007-2008 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.02 2008/01/23
-- bugfix Timing
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FDC Output
-- add odd Address test
-- add TRACE
-- Movem with regmask==x0000
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity TG68 is
port(
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
dtack : in std_logic;
addr : out std_logic_vector(31 downto 0);
data_out : out std_logic_vector(15 downto 0);
as : out std_logic;
uds : out std_logic;
lds : out std_logic;
rw : out std_logic;
drive_data : out std_logic; --enable for data_out driver
REG_D6 : out std_logic_vector(15 downto 0) --NeoGeo
);
end TG68;
ARCHITECTURE logic OF TG68 IS
COMPONENT TG68_fast
PORT (
clk : in std_logic;
reset : in std_logic;
clkena_in : in std_logic;
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0);
test_IPL : in std_logic;
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
decodeOPC : buffer std_logic;
wr : out std_logic;
UDS, LDS : out std_logic;
REG_D6 : out std_logic_vector(15 downto 0) --NeoGeo
);
END COMPONENT;
SIGNAL as_s : std_logic;
SIGNAL as_e : std_logic;
SIGNAL uds_s : std_logic;
SIGNAL uds_e : std_logic;
SIGNAL lds_s : std_logic;
SIGNAL lds_e : std_logic;
SIGNAL rw_s : std_logic;
SIGNAL rw_e : std_logic;
SIGNAL waitm : std_logic;
SIGNAL clkena_e : std_logic;
SIGNAL S_state : std_logic_vector(1 downto 0);
SIGNAL decode : std_logic;
SIGNAL wr : std_logic;
SIGNAL uds_in : std_logic;
SIGNAL lds_in : std_logic;
SIGNAL state : std_logic_vector(1 downto 0);
SIGNAL clkena : std_logic;
SIGNAL n_clk : std_logic;
SIGNAL cpuIPL : std_logic_vector(2 downto 0);
BEGIN
n_clk <= NOT clk;
TG68_fast_inst: TG68_fast
PORT MAP (
clk => n_clk, -- : in std_logic;
reset => reset, -- : in std_logic;
clkena_in => clkena, -- : in std_logic;
data_in => data_in, -- : in std_logic_vector(15 downto 0);
IPL => cpuIPL, -- : in std_logic_vector(2 downto 0);
test_IPL => '0', -- : in std_logic;
address => addr, -- : out std_logic_vector(31 downto 0);
data_write => data_out, -- : out std_logic_vector(15 downto 0);
state_out => state, -- : out std_logic_vector(1 downto 0);
decodeOPC => decode, -- : buffer std_logic;
wr => wr, -- : out std_logic;
UDS => uds_in, -- : out std_logic;
LDS => lds_in, -- : out std_logic;
REG_D6 => REG_D6
);
PROCESS (clk)
BEGIN
IF clkena_in='1' AND (clkena_e='1' OR state="01") THEN
clkena <= '1';
ELSE
clkena <= '0';
END IF;
END PROCESS;
PROCESS (clk, reset, state, as_s, as_e, rw_s, rw_e, uds_s, uds_e, lds_s, lds_e)
BEGIN
IF state="01" THEN
as <= '1';
rw <= '1';
uds <= '1';
lds <= '1';
ELSE
as <= as_s AND as_e;
rw <= rw_s AND rw_e;
uds <= uds_s AND uds_e;
lds <= lds_s AND lds_e;
END IF;
IF reset='0' THEN
S_state <= "11";
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
as_s <= '1';
rw_s <= '1';
uds_s <= '1';
lds_s <= '1';
IF state/="01" OR decode='1' THEN
CASE S_state IS
WHEN "00" => as_s <= '0';
rw_s <= wr;
IF wr='1' THEN
uds_s <= uds_in;
lds_s <= lds_in;
END IF;
S_state <= "01";
WHEN "01" => as_s <= '0';
rw_s <= wr;
uds_s <= uds_in;
lds_s <= lds_in;
S_state <= "10";
WHEN "10" =>
rw_s <= wr;
IF waitm='0' THEN
S_state <= "11";
END IF;
WHEN "11" =>
S_state <= "00";
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END IF;
IF reset='0' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
cpuIPL <= "111";
drive_data <= '0';
ELSIF falling_edge(clk) THEN
IF clkena_in='1' THEN
as_e <= '1';
rw_e <= '1';
uds_e <= '1';
lds_e <= '1';
clkena_e <= '0';
drive_data <= '0';
CASE S_state IS
WHEN "00" => null;
WHEN "01" => drive_data <= NOT wr;
WHEN "10" => as_e <= '0';
uds_e <= uds_in;
lds_e <= lds_in;
cpuIPL <= IPL;
drive_data <= NOT wr;
IF state="01" THEN
clkena_e <= '1';
waitm <= '0';
ELSE
clkena_e <= NOT dtack;
waitm <= dtack;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
END IF;
END PROCESS;
END;
| gpl-3.0 | 1975abe8941a0b5783115cdb0556494c | 0.442352 | 3.479962 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/ip/ocxo_clk_pll/ocxo_clk_pll.vhd | 1 | 4,679 | -- file: ocxo_clk_pll.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______597.520____892.144
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary__________10.000___________0.00100
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ocxo_clk_pll is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end ocxo_clk_pll;
architecture xilinx of ocxo_clk_pll is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component ocxo_clk_pll_clk_wiz
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
begin
U0: ocxo_clk_pll_clk_wiz
port map (
-- Clock in ports
clk_in1 => clk_in1,
-- Clock out ports
clk_out1 => clk_out1,
-- Status and control signals
resetn => resetn,
locked => locked
);
end xilinx;
| gpl-3.0 | 8deee44715e59b44c06cad2b1b39b25b | 0.628767 | 4.122467 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_gpio_0_0/synth/cpu_axi_gpio_0_0.vhd | 1 | 9,960 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY cpu_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END cpu_axi_gpio_0_0;
ARCHITECTURE cpu_axi_gpio_0_0_arch OF cpu_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_axi_gpio_0_0_arch: ARCHITECTURE IS "axi_gpio,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_axi_gpio_0_0_arch : ARCHITECTURE IS "cpu_axi_gpio_0_0,axi_gpio,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_axi_gpio_0_0_arch: ARCHITECTURE IS "cpu_axi_gpio_0_0,axi_gpio,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_gpio,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_GPIO_WIDTH=16,C_GPIO2_WIDTH=32,C_ALL_INPUTS=0,C_ALL_INPUTS_2=0,C_ALL_OUTPUTS=0,C_ALL_OUTPUTS_2=0,C_INTERRUPT_PRESENT=0,C_DOUT_DEFAULT=0x00000013,C_TRI_DEFAULT=0xFFFFFF2C,C_IS_DUAL=0,C_DOUT_DEFAULT_2=0x00000000,C_TRI_DEFAULT_2=0xFFFFFFFF}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 16,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000013",
C_TRI_DEFAULT => X"FFFFFF2C",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END cpu_axi_gpio_0_0_arch;
| gpl-3.0 | 13bc210ea97de1383aea4d1489bb7c35 | 0.686145 | 3.155894 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_exdes.vhd | 1 | 4,657 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END blk_mem_gen_v7_3_exdes;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT blk_mem_gen_v7_3 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : blk_mem_gen_v7_3
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| bsd-2-clause | 6d124e28237da30fcd4a5b10b1df1559 | 0.566889 | 4.570167 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/ram_16x1k_sp_synth.vhd | 1 | 8,151 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_sp_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ram_16x1k_sp_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ram_16x1k_sp_synth_ARCH OF ram_16x1k_sp_synth IS
COMPONENT ram_16x1k_sp_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ram_16x1k_sp_exdes PORT MAP (
--Port A
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| bsd-3-clause | 8faa6b0f032e183693394bfb8346caa7 | 0.56079 | 3.718522 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weights.vhd | 1 | 5,575 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file weights.vhd when simulating
-- the core, weights. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY weights IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END weights;
ARCHITECTURE weights_a OF weights IS
-- synthesis translate_off
COMPONENT wrapped_weights
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_weights USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 5,
c_addrb_width => 5,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "artix7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "weights.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 24,
c_read_depth_b => 24,
c_read_width_a => 24,
c_read_width_b => 24,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 24,
c_write_depth_b => 24,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 24,
c_write_width_b => 24,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_weights
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END weights_a;
| bsd-2-clause | b699e45e5d197c8dd2a68a417fa37ca2 | 0.531121 | 3.98784 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/srl_fifo.vhd | 2 | 11,618 | -- SRL_FIFO entity and architecture
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: srl_fifo.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- srl_fifo.vhd
--
-------------------------------------------------------------------------------
-- Author: goran
-- Revision: $Revision: 1.1.4.1 $
-- Date: $Date: 2010/09/14 22:35:47 $
--
-- History:
-- goran 2001-05-11 First Version
-- KC 2001-06-20 Added Addr as an output port, for use as an occupancy
-- value
--
-- DCW 2002-03-12 Structural implementation of synchronous reset for
-- Data_Exists DFF (using FDR)
-- jam 2002-04-12 added C_XON generic for mixed vhdl/verilog sims
--
-- als 2002-04-18 added default for XON generic in SRL16E, FDRE, and FDR
-- component declarations
--
-- DET 1/17/2008 v5_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.all;
entity SRL_FIFO is
generic (
C_DATA_BITS : natural := 8;
C_DEPTH : natural := 16;
C_XON : boolean := false
);
port (
Clk : in std_logic;
Reset : in std_logic;
FIFO_Write : in std_logic;
Data_In : in std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Read : in std_logic;
Data_Out : out std_logic_vector(0 to C_DATA_BITS-1);
FIFO_Full : out std_logic;
Data_Exists : out std_logic;
Addr : out std_logic_vector(0 to 3) -- Added Addr as a port
);
end entity SRL_FIFO;
architecture IMP of SRL_FIFO is
component SRL16E is
-- pragma translate_off
generic (
INIT : bit_vector := X"0000"
);
-- pragma translate_on
port (
CE : in std_logic;
D : in std_logic;
Clk : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16E;
component LUT4
generic(
INIT : bit_vector := X"0000"
);
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic);
end component;
component MULT_AND
port (
I0 : in std_logic;
I1 : in std_logic;
LO : out std_logic);
end component;
component MUXCY_L
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
LO : out std_logic);
end component;
component XORCY
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDRE;
component FDR is
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic);
end component FDR;
signal addr_i : std_logic_vector(0 to 3);
signal buffer_Full : std_logic;
signal buffer_Empty : std_logic;
signal next_Data_Exists : std_logic;
signal data_Exists_I : std_logic;
signal valid_Write : std_logic;
signal hsum_A : std_logic_vector(0 to 3);
signal sum_A : std_logic_vector(0 to 3);
signal addr_cy : std_logic_vector(0 to 4);
begin -- architecture IMP
buffer_Full <= '1' when (addr_i = "1111") else '0';
FIFO_Full <= buffer_Full;
buffer_Empty <= '1' when (addr_i = "0000") else '0';
next_Data_Exists <= (data_Exists_I and not buffer_Empty) or
(buffer_Empty and FIFO_Write) or
(data_Exists_I and not FIFO_Read);
Data_Exists_DFF : FDR
port map (
Q => data_Exists_I, -- [out std_logic]
C => Clk, -- [in std_logic]
D => next_Data_Exists, -- [in std_logic]
R => Reset); -- [in std_logic]
Data_Exists <= data_Exists_I;
valid_Write <= FIFO_Write and (FIFO_Read or not buffer_Full);
addr_cy(0) <= valid_Write;
Addr_Counters : for I in 0 to 3 generate
hsum_A(I) <= (FIFO_Read xor addr_i(I)) and (FIFO_Write or not buffer_Empty);
MUXCY_L_I : MUXCY_L
port map (
DI => addr_i(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
S => hsum_A(I), -- [in std_logic]
LO => addr_cy(I+1)); -- [out std_logic]
XORCY_I : XORCY
port map (
LI => hsum_A(I), -- [in std_logic]
CI => addr_cy(I), -- [in std_logic]
O => sum_A(I)); -- [out std_logic]
FDRE_I : FDRE
port map (
Q => addr_i(I), -- [out std_logic]
C => Clk, -- [in std_logic]
CE => data_Exists_I, -- [in std_logic]
D => sum_A(I), -- [in std_logic]
R => Reset); -- [in std_logic]
end generate Addr_Counters;
FIFO_RAM : for I in 0 to C_DATA_BITS-1 generate
SRL16E_I : SRL16E
-- pragma translate_off
generic map (
INIT => x"0000")
-- pragma translate_on
port map (
CE => valid_Write, -- [in std_logic]
D => Data_In(I), -- [in std_logic]
Clk => Clk, -- [in std_logic]
A0 => addr_i(0), -- [in std_logic]
A1 => addr_i(1), -- [in std_logic]
A2 => addr_i(2), -- [in std_logic]
A3 => addr_i(3), -- [in std_logic]
Q => Data_Out(I)); -- [out std_logic]
end generate FIFO_RAM;
-------------------------------------------------------------------------------
-- INT_ADDR_PROCESS
-------------------------------------------------------------------------------
-- This process assigns the internal address to the output port
-------------------------------------------------------------------------------
INT_ADDR_PROCESS:process (addr_i)
begin -- process
Addr <= addr_i;
end process;
end architecture IMP;
| gpl-3.0 | e4f9ddb95ca0bdbc7c1201adf623c328 | 0.437425 | 4.335075 | false | false | false | false |
ObKo/USBCore | Extra/usb_flasher.vhdl | 1 | 16,089 | --
-- USB Full-Speed/Hi-Speed Device Controller core - usb_flasher.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity usb_flasher is
port (
clk : in std_logic;
rst : in std_logic;
ctl_xfer_endpoint : in std_logic_vector(3 downto 0);
ctl_xfer_type : in std_logic_vector(7 downto 0);
ctl_xfer_request : in std_logic_vector(7 downto 0);
ctl_xfer_value : in std_logic_vector(15 downto 0);
ctl_xfer_index : in std_logic_vector(15 downto 0);
ctl_xfer_length : in std_logic_vector(15 downto 0);
ctl_xfer_accept : out std_logic;
ctl_xfer : in std_logic;
ctl_xfer_done : out std_logic;
ctl_xfer_data_out : in std_logic_vector(7 downto 0);
ctl_xfer_data_out_valid : in std_logic;
ctl_xfer_data_in : out std_logic_vector(7 downto 0);
ctl_xfer_data_in_valid : out std_logic;
ctl_xfer_data_in_last : out std_logic;
ctl_xfer_data_in_ready : in std_logic;
blk_xfer_endpoint : in std_logic_vector(3 downto 0);
blk_in_xfer : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
spi_cs : out std_logic;
spi_sck : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic
);
end usb_flasher;
architecture usb_flasher of usb_flasher is
type FLASH_MACHINE is (S_Idle, S_WriteCommand, S_ReadResponse, S_CtlResponse, S_CtlStartReceive,
S_CtlReceive, S_WriteData, S_Wait, S_ReadResponseLast, S_PageProg,
S_PageRead, S_PageReadLast);
type SPI_MACHINE is (S_Idle, S_Xfer);
signal spi_state : SPI_MACHINE;
signal flash_state : FLASH_MACHINE;
signal flash_clk : std_logic := '0';
signal flash_clk180 : std_logic;
signal clk_en : std_logic;
signal out_data : std_logic_vector(7 downto 0);
signal in_data : std_logic_vector(7 downto 0);
signal in_data_valid : std_logic;
signal recieve_data : std_logic;
signal recieve_data_d : std_logic;
signal out_reg : std_logic_vector(7 downto 0);
signal in_reg : std_logic_vector(7 downto 0);
signal in_latch : std_logic;
signal is_edge : std_logic;
signal xfer_count : std_logic_vector(2 downto 0);
signal xfer_last : std_logic;
signal xfer_valid : std_logic;
signal flash_cmd : std_logic_vector(7 downto 0);
signal flash_resp_size : std_logic_vector(2 downto 0);
signal flash_xfer_count : std_logic_vector(7 downto 0);
signal flash_xfer_max_count : std_logic_vector(7 downto 0);
signal data_dir : std_logic;
signal page_prog : std_logic;
signal page_read : std_logic;
signal ctl_wr_addr : std_logic_vector(1 downto 0);
signal ctl_rd_addr : std_logic_vector(1 downto 0);
signal ctl_buf : BYTE_ARRAY(0 to 3);
signal blk_out_tvalid : std_logic;
signal blk_out_tready : std_logic;
signal blk_out_tdata : std_logic_vector(7 downto 0);
signal blk_out_tlast : std_logic;
signal blk_in_tvalid : std_logic;
signal blk_in_tready : std_logic;
signal blk_in_tdata : std_logic_vector(7 downto 0);
signal blk_in_tlast : std_logic;
begin
OUT_ENDPOINT: blk_ep_out_ctl
generic map (
USE_ASYNC_FIFO => false
)
port map (
rst => rst,
usb_clk => clk,
axis_clk => clk,
blk_out_xfer => blk_out_xfer,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid,
axis_tdata => blk_out_tdata,
axis_tvalid => blk_out_tvalid,
axis_tready => blk_out_tready,
axis_tlast => blk_out_tlast
);
IN_ENDPOINT: blk_ep_in_ctl
generic map (
USE_ASYNC_FIFO => false
)
port map (
rst => rst,
usb_clk => clk,
axis_clk => clk,
blk_in_xfer => blk_in_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
axis_tdata => blk_in_tdata,
axis_tvalid => blk_in_tvalid,
axis_tready => blk_in_tready,
axis_tlast => blk_in_tlast
);
flash_clk180 <= not flash_clk;
CLK_GEN : process(clk) is
begin
if rising_edge(clk) then
if spi_state = S_Xfer then
flash_clk <= not flash_clk;
else
flash_clk <= '0';
end if;
end if;
end process;
is_edge <= flash_clk;
SPI_OUT : process(clk) is
begin
if rising_edge(clk) then
if (spi_state = S_Idle and xfer_valid = '1') or
(spi_state = S_Xfer and xfer_count = "000" and xfer_valid = '1' and is_edge = '1') then
out_reg <= out_data;
elsif is_edge = '1' and spi_state = S_Xfer then
out_reg(7) <= out_reg(6);
out_reg(6) <= out_reg(5);
out_reg(5) <= out_reg(4);
out_reg(4) <= out_reg(3);
out_reg(3) <= out_reg(2);
out_reg(2) <= out_reg(1);
out_reg(1) <= out_reg(0);
end if;
end if;
end process;
SPI_IN : process(clk) is
begin
if rising_edge(clk) then
--if (spi_state = S_Idle AND xfer_valid = '1') OR
-- (spi_state = S_Xfer AND xfer_count = "000" AND xfer_valid = '1' AND is_edge = '1') then
-- out_reg <= out_data;
if is_edge = '1' and spi_state = S_Xfer then
in_reg(7) <= in_reg(6);
in_reg(6) <= in_reg(5);
in_reg(5) <= in_reg(4);
in_reg(4) <= in_reg(3);
in_reg(3) <= in_reg(2);
in_reg(2) <= in_reg(1);
in_reg(1) <= in_reg(0);
in_reg(0) <= spi_miso;
end if;
recieve_data_d <= recieve_data;
if is_edge = '1' and spi_state = S_Xfer and xfer_count = "000" and recieve_data_d = '1' then
in_latch <= '1';
else
in_latch <= '0';
end if;
if in_latch = '1' then
in_data <= in_reg;
in_data_valid <= '1';
else
in_data_valid <= '0';
end if;
end if;
end process;
SPI_FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
spi_state <= S_Idle;
else
case spi_state is
when S_Idle =>
if xfer_valid = '1' then
spi_state <= S_Xfer;
xfer_count <= (others => '0');
end if;
when S_Xfer =>
if is_edge = '0' then
xfer_count <= xfer_count + 1;
else
if xfer_count = "000" then
if xfer_valid = '0' then
spi_state <= S_Idle;
end if;
end if;
end if;
end case;
end if;
end if;
end process;
CTL_BUFFER : process(clk) is
begin
if rising_edge(clk) then
if flash_state = S_Idle then
ctl_wr_addr <= (others => '0');
ctl_rd_addr <= (others => '0');
elsif flash_state = S_ReadResponse or flash_state = S_ReadResponseLast then
if in_data_valid = '1' then
ctl_buf(to_integer(unsigned(ctl_wr_addr))) <= in_data;
ctl_wr_addr <= ctl_wr_addr + 1;
end if;
elsif flash_state = S_CtlResponse then
if ctl_xfer_data_in_ready = '1' then
ctl_rd_addr <= ctl_rd_addr + 1;
end if;
elsif flash_state = S_CtlReceive then
if ctl_xfer_data_out_valid = '1' then
ctl_buf(to_integer(unsigned(ctl_wr_addr))) <= ctl_xfer_data_out;
ctl_wr_addr <= ctl_wr_addr + 1;
end if;
elsif flash_state = S_WriteData then
if xfer_last = '1' then
ctl_rd_addr <= ctl_rd_addr + 1;
end if;
end if;
end if;
end process;
FLASH_FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
flash_state <= S_Idle;
else
case flash_state is
when S_Idle =>
if ctl_xfer = '1' then
data_dir <= ctl_xfer_type(7);
if ctl_xfer_request(7 downto 2) = "000001" then
flash_cmd <= ctl_xfer_value(7 downto 0);
flash_resp_size <= ctl_xfer_length(2 downto 0);
if ctl_xfer_type(7) = '1' then
flash_state <= S_WriteCommand;
else
flash_state <= S_CtlStartReceive;
end if;
if ctl_xfer_request(0) = '1' then
page_prog <= '1';
else
page_prog <= '0';
end if;
if ctl_xfer_request(1) = '1' then
page_read <= '1';
else
page_read <= '0';
end if;
ctl_xfer_accept <= '1';
ctl_xfer_done <= '0';
else
ctl_xfer_accept <= '0';
ctl_xfer_done <= '1';
end if;
else
ctl_xfer_accept <= '0';
ctl_xfer_done <= '1';
end if;
when S_WriteCommand =>
if xfer_last = '1' then
if flash_resp_size = 0 then
flash_state <= S_Wait;
else
flash_xfer_count <= flash_xfer_max_count;
if data_dir = '1' then
flash_state <= S_ReadResponse;
else
flash_state <= S_WriteData;
end if;
end if;
end if;
when S_ReadResponse =>
if xfer_last = '1' then
if flash_xfer_count = 0 then
flash_state <= S_ReadResponseLast;
else
flash_xfer_count <= flash_xfer_count - 1;
end if;
end if;
when S_ReadResponseLast =>
if in_data_valid = '1' then
flash_xfer_count <= flash_xfer_max_count;
ctl_xfer_done <= '1';
flash_state <= S_CtlResponse;
end if;
when S_CtlResponse =>
if ctl_xfer_data_in_ready = '1' then
if flash_xfer_count = 0 then
flash_state <= S_Wait;
else
flash_xfer_count <= flash_xfer_count - 1;
end if;
end if;
when S_CtlStartReceive =>
if flash_resp_size > 0 then
flash_xfer_count <= flash_xfer_max_count;
flash_state <= S_CtlReceive;
else
flash_state <= S_WriteCommand;
end if;
when S_CtlReceive =>
if ctl_xfer_data_out_valid = '1' then
if flash_xfer_count = 0 then
flash_state <= S_WriteCommand;
else
flash_xfer_count <= flash_xfer_count - 1;
end if;
end if;
when S_WriteData =>
if xfer_last = '1' then
if flash_xfer_count = 0 then
if page_prog = '0' and page_read = '0' then
flash_state <= S_Wait;
elsif page_prog = '1' and blk_out_tvalid = '0' then
flash_state <= S_Wait;
elsif page_prog = '1' then
flash_state <= S_PageProg;
elsif page_read = '1' then
flash_xfer_count <= (others => '1');
flash_state <= S_PageRead;
end if;
else
flash_xfer_count <= flash_xfer_count - 1;
end if;
end if;
when S_Wait =>
ctl_xfer_done <= '1';
if ctl_xfer = '0' then
flash_state <= S_Idle;
end if;
when S_PageProg =>
if xfer_last = '1' then
if blk_out_tvalid = '0' then
flash_state <= S_Wait;
end if;
end if;
when S_PageRead =>
if xfer_last = '1' then
if flash_xfer_count = 0 then
flash_state <= S_PageReadLast;
else
flash_xfer_count <= flash_xfer_count - 1;
end if;
end if;
when S_PageReadLast =>
if in_data_valid = '1' then
flash_state <= S_Wait;
end if;
end case;
end if;
end if;
end process;
flash_xfer_max_count <= "00000" & (flash_resp_size - 1); --when flash_state = S_ReadResponseLast OR flash_state = S_WriteCommand
out_data <= ctl_buf(to_integer(unsigned(ctl_rd_addr))) when flash_state = S_WriteData else
blk_out_tdata when flash_state = S_PageProg else
flash_cmd;
xfer_valid <= '1' when flash_state = S_WriteCommand or flash_state = S_ReadResponse or
flash_state = S_WriteData or flash_state = S_PageProg or
flash_state = S_PageRead else
'0';
recieve_data <= '1' when flash_state = S_ReadResponse or flash_state = S_PageRead else
'0';
xfer_last <= '1' when xfer_count = "111" and is_edge = '0' else
'0';
ctl_xfer_data_in <= ctl_buf(to_integer(unsigned(ctl_rd_addr)));
ctl_xfer_data_in_valid <= '1' when flash_state = S_CtlResponse else
'0';
ctl_xfer_data_in_last <= '1' when flash_state = S_CtlResponse and flash_xfer_count = 0 else
'0';
blk_out_tready <= '1' when flash_state = S_PageProg and xfer_count = "000" and is_edge = '1' else
'0';
blk_in_tlast <= '1' when flash_state = S_PageReadLast else
'0';
blk_in_tdata <= in_data;
blk_in_tvalid <= in_data_valid when flash_state = S_PageRead or flash_state = S_PageReadLast else
'0';
spi_mosi <= out_reg(7);
spi_sck <= flash_clk;
spi_cs <= '0' when spi_state = S_Xfer else
'1';
end usb_flasher;
| mit | 5194e2cc2277881c188a46c96adabfb9 | 0.514948 | 3.556366 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwstream.vhd | 1 | 21,277 | --
-- SpaceWire core with character-stream interface.
--
-- This entity provides a SpaceWire core with a character-stream interface.
-- The interface provides means for connection initiation, sending and
-- receiving of N-Chars and TimeCodes, and error reporting.
--
-- This entity instantiates spwlink, spwrecv, spwxmit and one of the
-- spwrecvfront implementations. It also implements a receive FIFO and
-- a transmit FIFO.
--
-- The SpaceWire standard requires that each transceiver use an initial
-- signalling rate of 10 Mbit/s. This implies that the system clock frequency
-- must be a multiple of 10 MHz. See the manual for further details on
-- bitrates and clocking.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.spwpkg.all;
entity spwstream is
generic (
-- System clock frequency in Hz.
-- This must be set to the frequency of "clk". It is used to setup
-- counters for reset timing, disconnect timeout and to transmit
-- at 10 Mbit/s during the link handshake.
sysfreq: integer;
-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
-- This must be set to the frequency of "txclk". It is used to
-- transmit at 10 Mbit/s during the link handshake.
txclkfreq: integer:= 0;
-- Selection of a receiver front-end implementation.
rximpl: spw_implementation_type := impl_generic;
-- Maximum number of bits received per system clock
-- (must be 1 in case of impl_generic).
rxchunk: integer range 1 to 4 := 1;
-- Selection of a transmitter implementation.
tximpl: spw_implementation_type := impl_generic;
-- Size of the receive FIFO as the 2-logarithm of the number of bytes.
-- Must be at least 6 (64 bytes).
rxfifosize_bits: integer range 6 to 14 := 11;
-- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
txfifosize_bits: integer range 2 to 14 := 11
);
port (
-- System clock.
clk: in std_logic;
-- Receiver sample clock (only for impl_fast)
rxclk: in std_logic;
-- Transmit clock (only for impl_fast)
txclk: in std_logic;
-- Synchronous reset (active-high).
rst: in std_logic;
-- Enables automatic link start on receipt of a NULL character.
autostart: in std_logic;
-- Enables link start once the Ready state is reached.
-- Without autostart or linkstart, the link remains in state Ready.
linkstart: in std_logic;
-- Do not start link (overrides linkstart and autostart) and/or
-- disconnect a running link.
linkdis: in std_logic;
-- Scaling factor minus 1, used to scale the transmit base clock into
-- the transmission bit rate. The system clock (for impl_generic) or
-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
-- Changing this signal will immediately change the transmission rate.
-- During link setup, the transmission rate is always 10 Mbit/s.
txdivcnt: in std_logic_vector(7 downto 0);
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside the entity until it can be processed.
tick_in: in std_logic;
-- Control bits of the TimeCode to be sent. Must be valid while tick_in is high.
ctrl_in: in std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent. Must be valid while tick_in is high.
time_in: in std_logic_vector(5 downto 0);
-- Pulled high by the application to write an N-Char to the transmit
-- queue. If "txwrite" and "txrdy" are both high on the rising edge
-- of "clk", a character is added to the transmit queue.
-- This signal has no effect if "txrdy" is low.
txwrite: in std_logic;
-- Control flag to be sent with the next N_Char.
-- Must be valid while txwrite is high.
txflag: in std_logic;
-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while txwrite is high.
txdata: in std_logic_vector(7 downto 0);
-- High if the entity is ready to accept an N-Char for transmission.
txrdy: out std_logic;
-- High if the transmission queue is at least half full.
txhalff: out std_logic;
-- High for one clock cycle if a TimeCode was just received.
tick_out: out std_logic;
-- Control bits of the last received TimeCode.
ctrl_out: out std_logic_vector(1 downto 0);
-- Counter value of the last received TimeCode.
time_out: out std_logic_vector(5 downto 0);
-- High if "rxflag" and "rxdata" contain valid data.
-- This signal is high unless the receive FIFO is empty.
rxvalid: out std_logic;
-- High if the receive FIFO is at least half full.
rxhalff: out std_logic;
-- High if the received character is EOP or EEP; low if the received
-- character is a data byte. Valid if "rxvalid" is high.
rxflag: out std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid if "rxvalid" is high.
rxdata: out std_logic_vector(7 downto 0);
-- Pulled high by the application to accept a received character.
-- If "rxvalid" and "rxread" are both high on the rising edge of "clk",
-- a character is removed from the receive FIFO and "rxvalid", "rxflag"
-- and "rxdata" are updated.
-- This signal has no effect if "rxvalid" is low.
rxread: in std_logic;
-- High if the link state machine is currently in the Started state.
started: out std_logic;
-- High if the link state machine is currently in the Connecting state.
connecting: out std_logic;
-- High if the link state machine is currently in the Run state, indicating
-- that the link is fully operational. If none of started, connecting or running
-- is high, the link is in an initial state and the transmitter is not yet enabled.
running: out std_logic;
-- Disconnect detected in state Run. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errdisc: out std_logic;
-- Parity error detected in state Run. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errpar: out std_logic;
-- Invalid escape sequence detected in state Run. Triggers a reset and reconnect of
-- the link. This indication is auto-clearing.
erresc: out std_logic;
-- Credit error detected. Triggers a reset and reconnect of the link.
-- This indication is auto-clearing.
errcred: out std_logic;
-- Data In signal from SpaceWire bus.
spw_di: in std_logic;
-- Strobe In signal from SpaceWire bus.
spw_si: in std_logic;
-- Data Out signal to SpaceWire bus.
spw_do: out std_logic;
-- Strobe Out signal to SpaceWire bus.
spw_so: out std_logic
);
end entity spwstream;
architecture spwstream_arch of spwstream is
constant rsysfreq : real := real(sysfreq);
constant rtxclkfreq : real := real(txclkfreq);
-- Convert boolean to std_logic.
type bool_to_logic_type is array(boolean) of std_ulogic;
constant bool_to_logic: bool_to_logic_type := (false => '0', true => '1');
-- Reset time (6.4 us) in system clocks
constant reset_time: integer := integer(rsysfreq * 6.4e-6);
-- Disconnect time (850 ns) in system clocks
constant disconnect_time: integer := integer(rsysfreq * 850.0e-9);
-- Initial tx clock scaler (10 Mbit).
type impl_to_real_type is array(spw_implementation_type) of real;
constant tximpl_to_txclk_freq: impl_to_real_type :=
(impl_generic => rsysfreq, impl_fast => rtxclkfreq);
constant effective_txclk_freq: real := tximpl_to_txclk_freq(tximpl);
constant default_divcnt: std_logic_vector(7 downto 0) :=
std_logic_vector(to_unsigned(integer(effective_txclk_freq / 10.0e6 - 1.0), 8));
-- Registers.
type regs_type is record
-- packet state
rxpacket: std_logic; -- '1' when receiving a packet
rxeep: std_logic; -- '1' when rx EEP character pending
txpacket: std_logic; -- '1' when transmitting a packet
txdiscard: std_logic; -- '1' when discarding a tx packet
-- FIFO pointers
rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
-- FIFO state
rxfifo_rvalid: std_logic; -- '1' if s_rxfifo_rdata is valid
txfifo_rvalid: std_logic; -- '1' if s_txfifo_rdata is valid
rxfull: std_logic; -- '1' if RX fifo is full
rxhalff: std_logic; -- '1' if RX fifo is at least half full
txfull: std_logic; -- '1' if TX fifo is full
txhalff: std_logic; -- '1' if TX fifo is at least half full
rxroom: std_logic_vector(5 downto 0);
end record;
constant regs_reset: regs_type := (
rxpacket => '0',
rxeep => '0',
txpacket => '0',
txdiscard => '0',
rxfifo_raddr => (others => '0'),
rxfifo_waddr => (others => '0'),
txfifo_raddr => (others => '0'),
txfifo_waddr => (others => '0'),
rxfifo_rvalid => '0',
txfifo_rvalid => '0',
rxfull => '0',
rxhalff => '0',
txfull => '0',
txhalff => '0',
rxroom => (others => '0') );
signal r: regs_type := regs_reset;
signal rin: regs_type;
-- Interface signals to components.
signal recv_rxen: std_logic;
signal recvo: spw_recv_out_type;
signal recv_inact: std_logic;
signal recv_inbvalid: std_logic;
signal recv_inbits: std_logic_vector(rxchunk-1 downto 0);
signal xmiti: spw_xmit_in_type;
signal xmito: spw_xmit_out_type;
signal xmit_divcnt: std_logic_vector(7 downto 0);
signal linki: spw_link_in_type;
signal linko: spw_link_out_type;
-- Memory interface signals.
signal s_rxfifo_raddr: std_logic_vector(rxfifosize_bits-1 downto 0);
signal s_rxfifo_rdata: std_logic_vector(8 downto 0);
signal s_rxfifo_wen: std_logic;
signal s_rxfifo_waddr: std_logic_vector(rxfifosize_bits-1 downto 0);
signal s_rxfifo_wdata: std_logic_vector(8 downto 0);
signal s_txfifo_raddr: std_logic_vector(txfifosize_bits-1 downto 0);
signal s_txfifo_rdata: std_logic_vector(8 downto 0);
signal s_txfifo_wen: std_logic;
signal s_txfifo_waddr: std_logic_vector(txfifosize_bits-1 downto 0);
signal s_txfifo_wdata: std_logic_vector(8 downto 0);
begin
-- Instantiate link controller.
link_inst: spwlink
generic map (
reset_time => reset_time )
port map (
clk => clk,
rst => rst,
linki => linki,
linko => linko,
rxen => recv_rxen,
recvo => recvo,
xmiti => xmiti,
xmito => xmito );
-- Instantiate receiver.
recv_inst: spwrecv
generic map(
disconnect_time => disconnect_time,
rxchunk => rxchunk )
port map (
clk => clk,
rxen => recv_rxen,
recvo => recvo,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits );
-- Instantiate transmitter.
xmit_sel0: if tximpl = impl_generic generate
xmit_inst: spwxmit
port map (
clk => clk,
rst => rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
xmit_sel1: if tximpl = impl_fast generate
xmit_fast_inst: spwxmit_fast
port map (
clk => clk,
txclk => txclk,
rst => rst,
divcnt => xmit_divcnt,
xmiti => xmiti,
xmito => xmito,
spw_do => spw_do,
spw_so => spw_so );
end generate;
-- Instantiate receiver front-end.
recvfront_sel0: if rximpl = impl_generic generate
recvfront_generic_inst: spwrecvfront_generic
port map (
clk => clk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
recvfront_sel1: if rximpl = impl_fast generate
recvfront_fast_inst: spwrecvfront_fast
generic map (
rxchunk => rxchunk )
port map (
clk => clk,
rxclk => rxclk,
rxen => recv_rxen,
inact => recv_inact,
inbvalid => recv_inbvalid,
inbits => recv_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
-- Instantiate RX memory.
rxmem: spwram
generic map (
abits => rxfifosize_bits,
dbits => 9 )
port map (
rclk => clk,
wclk => clk,
ren => '1',
raddr => s_rxfifo_raddr,
rdata => s_rxfifo_rdata,
wen => s_rxfifo_wen,
waddr => s_rxfifo_waddr,
wdata => s_rxfifo_wdata );
-- Instantiate TX memory.
txmem: spwram
generic map (
abits => txfifosize_bits,
dbits => 9 )
port map (
rclk => clk,
wclk => clk,
ren => '1',
raddr => s_txfifo_raddr,
rdata => s_txfifo_rdata,
wen => s_txfifo_wen,
waddr => s_txfifo_waddr,
wdata => s_txfifo_wdata );
-- Combinatorial process
process (r, linko, s_rxfifo_rdata, s_txfifo_rdata, rst, autostart, linkstart, linkdis, txdivcnt, tick_in, ctrl_in, time_in, txwrite, txflag, txdata, rxread) is
variable v: regs_type;
variable v_tmprxroom: unsigned(rxfifosize_bits-1 downto 0);
variable v_tmptxroom: unsigned(txfifosize_bits-1 downto 0);
begin
v := r;
v_tmprxroom := to_unsigned(0, v_tmprxroom'length);
v_tmptxroom := to_unsigned(0, v_tmptxroom'length);
-- Keep track of whether we are sending and/or receiving a packet.
if linko.rxchar = '1' then
-- got character
v.rxpacket := not linko.rxflag;
end if;
if linko.txack = '1' then
-- send character
v.txpacket := not s_txfifo_rdata(8);
end if;
-- Update RX fifo pointers.
if (rxread = '1') and (r.rxfifo_rvalid = '1') then
-- read from fifo
v.rxfifo_raddr := std_logic_vector(unsigned(r.rxfifo_raddr) + 1);
end if;
if r.rxfull = '0' then
if (linko.rxchar = '1') or (r.rxeep = '1') then
-- write to fifo (received char or pending EEP)
v.rxfifo_waddr := std_logic_vector(unsigned(r.rxfifo_waddr) + 1);
end if;
v.rxeep := '0';
end if;
-- Keep track of whether the RX fifo contains valid data.
-- (use new value of rxfifo_raddr)
v.rxfifo_rvalid := bool_to_logic(v.rxfifo_raddr /= r.rxfifo_waddr);
-- Update room in RX fifo (use new value of rxfifo_waddr).
v_tmprxroom := unsigned(r.rxfifo_raddr) - unsigned(v.rxfifo_waddr) - 1;
v.rxfull := bool_to_logic(v_tmprxroom = 0);
v.rxhalff := not v_tmprxroom(v_tmprxroom'high);
if v_tmprxroom > 63 then
v.rxroom := (others => '1');
else
v.rxroom := std_logic_vector(v_tmprxroom(5 downto 0));
end if;
-- Update TX fifo pointers.
if (r.txfifo_rvalid = '1') and ((linko.txack = '1') or (r.txdiscard = '1')) then
-- read from fifo
v.txfifo_raddr := std_logic_vector(unsigned(r.txfifo_raddr) + 1);
if s_txfifo_rdata(8) = '1' then
v.txdiscard := '0'; -- got EOP/EEP, stop discarding data
end if;
end if;
if (r.txfull = '0') and (txwrite = '1') then
-- write to fifo
v.txfifo_waddr := std_logic_vector(unsigned(r.txfifo_waddr) + 1);
end if;
-- Keep track of whether the TX fifo contains valid data.
-- (use new value of txfifo_raddr)
v.txfifo_rvalid := bool_to_logic(v.txfifo_raddr /= r.txfifo_waddr);
-- Update room in TX fifo (use new value of txfifo_waddr).
v_tmptxroom := unsigned(r.txfifo_raddr) - unsigned(v.txfifo_waddr) - 1;
v.txfull := bool_to_logic(v_tmptxroom = 0);
v.txhalff := not v_tmptxroom(v_tmptxroom'high);
-- If the link is lost, set a flag to discard the current packet.
if linko.running = '0' then
v.rxeep := v.rxeep or v.rxpacket; -- use new value of rxpacket
v.txdiscard := v.txdiscard or v.txpacket; -- use new value of txpacket
v.rxpacket := '0';
v.txpacket := '0';
end if;
-- Clear the discard flag when the link is explicitly disabled.
if linkdis = '1' then
v.txdiscard := '0';
end if;
-- Drive control signals to RX fifo.
s_rxfifo_raddr <= v.rxfifo_raddr; -- using new value of rxfifo_raddr
s_rxfifo_wen <= (not r.rxfull) and (linko.rxchar or r.rxeep);
s_rxfifo_waddr <= r.rxfifo_waddr;
if r.rxeep = '1' then
s_rxfifo_wdata <= "100000001";
else
s_rxfifo_wdata <= linko.rxflag & linko.rxdata;
end if;
-- Drive control signals to TX fifo.
s_txfifo_raddr <= v.txfifo_raddr; -- using new value of txfifo_raddr
s_txfifo_wen <= (not r.txfull) and txwrite;
s_txfifo_waddr <= r.txfifo_waddr;
s_txfifo_wdata <= txflag & txdata;
-- Drive inputs to spwlink.
linki.autostart <= autostart;
linki.linkstart <= linkstart;
linki.linkdis <= linkdis;
linki.rxroom <= r.rxroom;
linki.tick_in <= tick_in;
linki.ctrl_in <= ctrl_in;
linki.time_in <= time_in;
linki.txwrite <= r.txfifo_rvalid and not r.txdiscard;
linki.txflag <= s_txfifo_rdata(8);
linki.txdata <= s_txfifo_rdata(7 downto 0);
-- Drive divcnt input to spwxmit.
if linko.running = '1' then
xmit_divcnt <= txdivcnt;
else
xmit_divcnt <= default_divcnt;
end if;
-- Drive outputs.
txrdy <= not r.txfull;
txhalff <= r.txhalff;
tick_out <= linko.tick_out;
ctrl_out <= linko.ctrl_out;
time_out <= linko.time_out;
rxvalid <= r.rxfifo_rvalid;
rxhalff <= r.rxhalff;
rxflag <= s_rxfifo_rdata(8);
rxdata <= s_rxfifo_rdata(7 downto 0);
started <= linko.started;
connecting <= linko.connecting;
running <= linko.running;
errdisc <= linko.errdisc;
errpar <= linko.errpar;
erresc <= linko.erresc;
errcred <= linko.errcred;
-- Reset.
if rst = '1' then
v.rxpacket := '0';
v.rxeep := '0';
v.txpacket := '0';
v.txdiscard := '0';
v.rxfifo_raddr := (others => '0');
v.rxfifo_waddr := (others => '0');
v.txfifo_raddr := (others => '0');
v.txfifo_waddr := (others => '0');
v.rxfifo_rvalid := '0';
v.txfifo_rvalid := '0';
end if;
-- Update registers.
rin <= v;
end process;
-- Update registers.
process (clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end architecture spwstream_arch;
| mit | e557b754eaa97d8da842781159f32f42 | 0.547681 | 3.851041 | false | false | false | false |
peteut/nvc | test/regress/issue335.vhd | 2 | 637 | entity issue335 is
end entity;
use std.textio.all;
architecture a of issue335 is
begin
main : process is
variable tmp : integer;
variable l : line;
begin
l := new string'("1");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "1";
read(l, tmp);
assert tmp = 1;
l := new string'("22");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "22";
-- Uncomment this to make it work
l := new string'("333");
report integer'image(l.all'length) & ", '" & l.all & "'";
assert l.all = "333";
wait;
end process;
end architecture;
| gpl-3.0 | b5842644f6558eaaf0b53587dad0a156 | 0.563579 | 3.233503 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_13/lab13_5/lab13_6.vhd | 2 | 776 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary_counter_top is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (3 downto 0));
end binary_counter_top;
architecture Behavioral of binary_counter_top is
signal CLK_DIV : std_logic_vector (2 downto 0);
signal COUNT : std_logic_vector (3 downto 0);
begin
-- clock divider
process (CLK)
begin
if (CLK'Event and CLK = '1') then
CLK_DIV <= CLK_DIV + '1';
end if;
end process;
-- counter
process (CLK_DIV(2))
begin
if (CLK_DIV(2)'Event and CLK_DIV(2) = '1') then
COUNT <= COUNT + '1';
end if;
end process;
-- display the count on the LEDs
LED <= COUNT;
end Behavioral; | gpl-2.0 | cad5e56fdff8794797a1d88adaacd148 | 0.596649 | 3.403509 | false | false | false | false |
olgirard/openmsp430 | core/synthesis/xilinx/src/coregen/virtex6_pmem.vhd | 1 | 5,150 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file virtex6_pmem.vhd when simulating
-- the core, virtex6_pmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY virtex6_pmem IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END virtex6_pmem;
ARCHITECTURE virtex6_pmem_a OF virtex6_pmem IS
-- synthesis translate_off
component wrapped_virtex6_pmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_virtex6_pmem use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "virtex6",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "virtex6",
c_write_depth_b => 4096,
c_write_depth_a => 4096,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 12,
c_addrb_width => 12,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 4096,
c_read_depth_a => 4096,
c_byte_size => 8,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 2,
c_has_enb => 0,
c_web_width => 2,
c_has_ena => 1,
c_use_byte_web => 1,
c_use_byte_wea => 1,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_virtex6_pmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END virtex6_pmem_a;
| bsd-3-clause | ff46c12677a53727d822c22be911eb07 | 0.559417 | 3.683834 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/example_design/fifo8to32_exdes.vhd | 1 | 5,080 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity fifo8to32_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end fifo8to32_exdes;
architecture xilinx of fifo8to32_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component fifo8to32 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : fifo8to32
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | f097901c807b06bd7cf731aa4c519832 | 0.520669 | 4.792453 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weights/simulation/weights_synth.vhd | 1 | 7,879 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weights_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY weights_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE weights_synth_ARCH OF weights_synth IS
COMPONENT weights_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(23 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 24,
READ_WIDTH => 24 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: weights_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| bsd-2-clause | a4bf6dc7e1e9c37f71b7c57c0762a5a4 | 0.565173 | 3.787981 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/example_design/k7_prime_fifo_plain_exdes.vhd | 1 | 5,299 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity k7_prime_fifo_plain_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end k7_prime_fifo_plain_exdes;
architecture xilinx of k7_prime_fifo_plain_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component k7_prime_fifo_plain is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : k7_prime_fifo_plain
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | 8c6a8dc0659165ee4bb82fce3d18b2f1 | 0.517267 | 4.748208 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/module.vhd | 1 | 1,434 | library IEEE;
use IEEE.std_logic_1164.all;
entity SEMI_MIPS_MODULE is
port(
CLK : std_logic;
EXTERNAL_RESET : std_logic
);
end entity;
architecture RTL of SEMI_MIPS_MODULE is
component SEMI_MIPS is
port (
clk : in std_logic;
external_reset : in std_logic;
we : out std_logic;
re : out std_logic;
address : out std_logic_vector(7 downto 0);
memory_in : in std_logic_vector(15 downto 0);
memory_out : out std_logic_vector(15 downto 0)
);
end component;
component MEMORY is
port (
clk : in std_logic;
we : in std_logic;
re : in std_logic;
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0)
);
end component;
signal we, re : std_logic;
signal address : std_logic_vector(7 downto 0);
signal memory_in, memory_out : std_logic_vector(15 downto 0);
begin
MEMORY_inst : component MEMORY
port map(
clk => clk,
we => we,
re => re,
address => address,
datain => memory_out,
dataout => memory_in
);
SEMI_MIPS_inst : component SEMI_MIPS
port map(
clk => clk,
external_reset => external_reset,
we => we,
re => re,
address => address,
memory_in => memory_in,
memory_out => memory_out
);
end architecture RTL;
| gpl-3.0 | 90d2e08c2deb478211458ada18eea89a | 0.579498 | 3.057569 | false | false | false | false |
peteut/nvc | test/regress/attr9.vhd | 1 | 642 | entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert integer'value("-1") = -1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
assert boolean'value("FALSE") = false;
assert character'value("'x' ") = 'x';
assert integer'value(integer'image(integer'high)) = integer'high;
assert integer'value(integer'image(integer'low)) = integer'low;
wait;
end process;
end architecture;
| gpl-3.0 | bee468a3c35d6fe1c607907f20f10fc1 | 0.601246 | 3.647727 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_hid/example_design/weight_hid_prod.vhd | 1 | 10,102 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: weight_hid_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : weight_hid.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 320
-- C_READ_WIDTH_A : 320
-- C_WRITE_DEPTH_A : 230
-- C_READ_DEPTH_A : 230
-- C_ADDRA_WIDTH : 8
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 320
-- C_READ_WIDTH_B : 320
-- C_WRITE_DEPTH_B : 230
-- C_READ_DEPTH_B : 230
-- C_ADDRB_WIDTH : 8
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_hid_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END weight_hid_prod;
ARCHITECTURE xilinx OF weight_hid_prod IS
COMPONENT weight_hid_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : weight_hid_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| bsd-2-clause | fbb47d16156e80d32f609be29202c0d0 | 0.493764 | 3.833776 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_14/Lab_14_2_1/sync_D.vhd | 1 | 501 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sync_D is
port (
Q: out std_logic;
CLK: in std_logic;
CE: in std_logic;
CLR: in std_logic;
D: in std_logic;
PRE: in std_logic
);
end sync_D;
architecture Arch_sync_D of sync_D is
begin
FF: process (CLR, PRE, CLK)
begin
if (CLR = '1') then
Q <= '0';
else
if (PRE = '1') then
Q <= '1';
else
if ( CE = '1' and falling_edge(CLK) ) then
Q <= D;
end if;
end if;
end if;
end process FF;
end Arch_sync_D; | gpl-2.0 | b218b7526fd757bf1138222600692e33 | 0.576846 | 2.397129 | false | false | false | false |
UnofficialRepos/OSVVM | MessagePkg.vhd | 1 | 5,652 | --
-- File Name: MessagePkg.vhd
-- Design Unit Name: MessagePkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line name/message to be associated with a data structure.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2010 0.1 Initial revision
-- 07/2014 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- 07/2014 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 01/2015 2015.01 Removed initialized parameter from Get
-- 04/2018 2018.04 Minor updates to alert message
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2010 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
package MessagePkg is
type MessagePType is protected
procedure Set (MessageIn : String) ;
impure function Get (ItemNumber : integer) return string ;
impure function GetCount return integer ;
impure function IsSet return boolean ;
procedure Clear ; -- clear message
procedure Deallocate ; -- clear message
end protected MessagePType ;
end package MessagePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessagePkg is
-- Local Data Structure Types
type LineArrayType is array (natural range <>) of line ;
type LineArrayPtrType is access LineArrayType ;
type MessagePType is protected body
variable MessageCount : integer := 0 ;
constant INITIAL_ITEM_COUNT : integer := 16 ;
variable MaxMessageCount : integer := 0 ;
variable MessagePtr : LineArrayPtrType ;
------------------------------------------------------------
procedure Set (MessageIn : String) is
------------------------------------------------------------
variable NamePtr : line ;
variable OldMaxMessageCount : integer ;
variable OldMessagePtr : LineArrayPtrType ;
begin
MessageCount := MessageCount + 1 ;
if MessageCount > MaxMessageCount then
OldMaxMessageCount := MaxMessageCount ;
MaxMessageCount := MaxMessageCount + INITIAL_ITEM_COUNT ;
OldMessagePtr := MessagePtr ;
MessagePtr := new LineArrayType(1 to MaxMessageCount) ;
for i in 1 to OldMaxMessageCount loop
MessagePtr(i) := OldMessagePtr(i) ;
end loop ;
Deallocate( OldMessagePtr ) ;
end if ;
MessagePtr(MessageCount) := new string'(MessageIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ItemNumber : integer) return string is
------------------------------------------------------------
begin
if MessageCount > 0 then
if ItemNumber >= 1 and ItemNumber <= MessageCount then
return MessagePtr(ItemNumber).all ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get input value out of range", FAILURE) ;
return "" ; -- error if this happens
end if ;
else
Alert(OSVVM_ALERTLOG_ID, "OSVVM.MessagePkg.Get message is not set", FAILURE) ;
return "" ; -- error if this happens
end if ;
end function Get ;
------------------------------------------------------------
impure function GetCount return integer is
------------------------------------------------------------
begin
return MessageCount ;
end function GetCount ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return MessageCount > 0 ;
end function IsSet ;
------------------------------------------------------------
procedure Deallocate is -- clear message
------------------------------------------------------------
variable CurPtr : LineArrayPtrType ;
begin
for i in 1 to MessageCount loop
deallocate( MessagePtr(i) ) ;
end loop ;
MessageCount := 0 ;
MaxMessageCount := 0 ;
deallocate( MessagePtr ) ;
end procedure Deallocate ;
------------------------------------------------------------
procedure Clear is -- clear
------------------------------------------------------------
begin
Deallocate ;
end procedure Clear ;
end protected body MessagePType ;
end package body MessagePkg ; | artistic-2.0 | 939819dbd50908cb58479712ce84f0c7 | 0.546886 | 5.110307 | false | false | false | false |
UnofficialRepos/OSVVM | MessageListPkg.vhd | 1 | 5,146 | --
-- File Name: MessageListPkg.vhd
-- Design Unit Name: MessageListPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for multi-line message
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 07/2021 2021.07 Initial revision.
-- Written as a replacement for protected types (MessagePkg)
-- to simplify usage in new data structure.
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use std.textio.all ;
package MessageListPkg is
type MessageStructType ;
type MessageStructPtrType is access MessageStructType ;
type MessageStructType is record
Name : line ;
NextPtr : MessageStructPtrType ;
end record MessageStructType ;
procedure SetMessage (variable Message : inout MessageStructPtrType; Name : String) ;
procedure WriteMessage (variable buf : inout line; variable Message : inout MessageStructPtrType; prefix : string := "") ;
procedure WriteMessage (file f : text; variable Message : inout MessageStructPtrType; prefix : string := "") ;
procedure GetMessageCount (variable Message : inout MessageStructPtrType; variable Count : out integer) ;
procedure DeallocateMessage (variable Message : inout MessageStructPtrType) ;
end package MessageListPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body MessageListPkg is
------------------------------------------------------------
procedure SetMessage (variable Message : inout MessageStructPtrType; Name : String) is
------------------------------------------------------------
variable M : MessageStructPtrType ;
begin
if Message = NULL then
Message := new MessageStructType ;
Message.Name := new string'(Name) ;
Message.NextPtr := NULL ;
else
M := Message ;
while M.NextPtr /= NULL loop
M := M.NextPtr ;
end loop ;
M.NextPtr := new MessageStructType ;
M := M.NextPtr ;
M.Name := new string'(Name) ;
M.NextPtr := NULL ;
end if ;
end procedure SetMessage ;
------------------------------------------------------------
procedure WriteMessage (variable buf : inout line; variable Message : inout MessageStructPtrType; prefix : string := "") is
------------------------------------------------------------
variable M : MessageStructPtrType ;
begin
M := Message ;
while M /= NULL loop
write(buf, prefix & M.Name.all & LF) ;
M := M.NextPtr ;
end loop ;
end procedure WriteMessage ;
------------------------------------------------------------
procedure WriteMessage (file f : text; variable Message : inout MessageStructPtrType; prefix : string := "") is
------------------------------------------------------------
variable M : MessageStructPtrType ;
variable buf : line ;
begin
M := Message ;
while M /= NULL loop
write(buf, prefix & M.Name.all) ;
writeline(f, buf) ;
M := M.NextPtr ;
end loop ;
end procedure WriteMessage ;
------------------------------------------------------------
procedure GetMessageCount (variable Message : inout MessageStructPtrType; variable Count : out integer) is
------------------------------------------------------------
variable M : MessageStructPtrType ;
begin
Count := 0 ;
M := Message ;
while M /= NULL loop
Count := Count + 1 ;
M := M.NextPtr ;
end loop ;
end procedure GetMessageCount ;
------------------------------------------------------------
procedure DeallocateMessage (variable Message : inout MessageStructPtrType) is
------------------------------------------------------------
variable OldM : MessageStructPtrType ;
begin
while Message /= NULL loop
OldM := Message ;
Message := Message.NextPtr ;
deallocate(OldM) ;
end loop ;
end procedure DeallocateMessage ;
end package body MessageListPkg ; | artistic-2.0 | 24781805bef2a4547869163828744c8c | 0.540808 | 4.919694 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_synth.vhd | 1 | 11,001 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY counter_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF counter_fifo_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: counter_fifo_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: counter_fifo_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: counter_fifo_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
counter_fifo_inst : counter_fifo_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | aa335ff7cb60ac2d0a2d65e7618a7266 | 0.459685 | 3.980101 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/controller.vhd | 1 | 8,186 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.custom_pkg.all;
-- num_neurons defined in the custom_package --
entity controller is
port ( clk : in std_logic;
reset : in std_logic;
output : out std_logic_vector(7 downto 0)
);
end controller;
architecture Behavioral of controller is
signal num_operations, input, dina_image, image, output_temp, predict : std_logic_vector(7 downto 0);
signal in_weight_hid, out_weight_hid, in_weight_out, out_weight_out : std_logic_vector((num_neurons*8)-1 downto 0);
signal addr_weight_hid, addra_image : std_logic_vector(7 downto 0);
signal addr_weight_out : std_logic_vector(5 downto 0);
signal layer : layer_type;
signal weight : eight_bit(num_neurons-1 downto 0);
signal output_hid : eight_bit(num_neurons-1 downto 0);
signal layer_output : eight_bit(num_neurons downto 0);
signal shift_over_flag, active_activation, rst_layer, predict_en : std_logic;
signal curr_state,next_state : layer_type;
COMPONENT test_image
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT weight_hid
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END COMPONENT;
COMPONENT weight_out
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END COMPONENT;
COMPONENT hidden_layer
generic ( N : Integer );
port ( clk : in std_logic ;
num_operations : in std_logic_vector(7 downto 0);
layer : in layer_type;
rst : in std_logic ;
input : in std_logic_vector(7 downto 0);
weight : in eight_bit(N-1 downto 0);
shift_over_flag : out std_logic;
active_activation : out std_logic;
output_hid : out eight_bit(N-1 downto 0)
);
END COMPONENT;
COMPONENT prediction is
port (clk : in std_logic;
enable : in std_logic;
output_hid : in eight_bit(num_neurons-1 downto 0);
predict : out std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
-------------------------------------------------------------------------------------------------------------
output <= predict;
-------------------------------------------------------------------------------------------------------------
test_image_map : test_image
PORT MAP (clk, "0", addra_image, dina_image, image);
layer_map : hidden_layer
GENERIC MAP ( N => num_neurons )
PORT MAP (clk, num_operations, layer, rst_layer, input, weight, shift_over_flag, active_activation, output_hid);
weight_hid_map: weight_hid
PORT MAP (clk, "0", addr_weight_hid, in_weight_hid, out_weight_hid);
weight_out_map: weight_out
PORT MAP (clk, "0", addr_weight_out, in_weight_out, out_weight_out);
prediction_map : prediction
PORT MAP (clk, predict_en, output_hid, predict);
-------------------------------------------------------------------------------------------------------------
transition : process (clk,reset,curr_state)
variable num : Integer;
begin
if reset = '1' then
curr_state <= idle;
addra_image <= (others=>'0');
addr_weight_hid <= (others=>'0');
addr_weight_out <= (others=>'0');
layer_output <= (others=> (others=>'0'));
output_temp <= (others=>'0');
in_weight_hid <= (others=>'0');
in_weight_out <= (others=>'0');
dina_image <= (others=>'0');
num := 0;
elsif rising_edge(clk) then
if curr_state = weighted_sum_layer1 then
addra_image <= addra_image + 1;
addr_weight_hid <= addr_weight_hid + 1;
addr_weight_out <= (others=>'0');
elsif curr_state = weighted_sum_layer2 then
addra_image <= (others=>'0');
addr_weight_hid <= (others=>'0');
output_temp <= layer_output(num);
if num < num_neurons then
num := num + 1;
else
num := 0;
end if ;
addr_weight_out <= addr_weight_out + 1;
elsif curr_state = activate_layer1 then
layer_output(0) <= (others=>'0');
layer_output(num_neurons downto 1) <= output_hid;
addra_image <= (others=>'0');
addr_weight_hid <= (others=>'0');
addr_weight_out <= (others=>'0');
elsif curr_state = activate_layer2 then
layer_output(0) <= (others=>'0');
layer_output(num_neurons downto 1) <= output_hid;
addra_image <= (others=>'0');
addr_weight_hid <= (others=>'0');
addr_weight_out <= (others=>'0');
else
addra_image <= (others=>'0');
addr_weight_hid <= (others=>'0');
addr_weight_out <= (others=>'0') ;
end if;
curr_state <= next_state;
end if;
end process;
---------------------------------------------------------------------------------------------------------
image_weight_allocate : process (curr_state, image, out_weight_hid, out_weight_out, output_temp) begin
if curr_state = weighted_sum_layer1 then
input <= image;
for i in num_neurons-1 downto 0 loop
weight(i) <= out_weight_hid(((i+1)*8)-1 downto i*8);
end loop;
elsif curr_state = weighted_sum_layer2 then
input <= output_temp;
for i in num_neurons-1 downto 0 loop
weight(i) <= out_weight_out(((i+1)*8)-1 downto i*8);
end loop;
else
input <= (others=>'0');
weight <= ((others=> (others=>'0')));
end if;
end process;
---------------------------------------------------------------------------------------------------------
next_state_logic : process (curr_state, shift_over_flag, active_activation) begin
case curr_state is
when idle =>
if active_activation = '0' then
next_state <= weighted_sum_layer1;
else
next_state <= idle;
end if;
when weighted_sum_layer1 =>
if active_activation = '1' then
next_state <= activate_layer1;
else
next_state <= weighted_sum_layer1;
end if;
when activate_layer1 =>
if shift_over_flag = '1' then
next_state <= reset_layer;
else
next_state <= activate_layer1;
end if;
when reset_layer =>
if active_activation = '0' then
next_state <= weighted_sum_layer2;
else
next_state <= reset_layer;
end if;
when weighted_sum_layer2 =>
if active_activation = '1' then
next_state <= activate_layer2;
else
next_state <= weighted_sum_layer2;
end if;
when activate_layer2 =>
if shift_over_flag = '1' then
next_state <= predict_layer;
else
next_state <= activate_layer2;
end if;
when predict_layer =>
next_state <= predict_layer;
end case;
end process;
-----------------------------------------------------------------------------------------------------------
Output_process: process (curr_state) begin
case curr_state is
when idle =>
rst_layer <= '1';
num_operations <= (others=>'0');
layer <= idle;
predict_en <= '0';
when weighted_sum_layer1 =>
rst_layer <= '0';
num_operations <= "11100000";
layer <= weighted_sum_layer1;
predict_en <= '0';
when activate_layer1 =>
rst_layer <= '0';
num_operations <= "11100000";
layer <= activate_layer1;
predict_en <= '0';
when reset_layer =>
rst_layer <= '1';
num_operations <= (others=>'0');
layer <= idle;
predict_en <= '0';
when weighted_sum_layer2 =>
rst_layer <= '0';
num_operations <= "00101000";
layer <= weighted_sum_layer2;
predict_en <= '0';
when activate_layer2 =>
rst_layer <= '0';
num_operations <= "00101000";
layer <= activate_layer2;
predict_en <= '0';
when predict_layer =>
rst_layer <= '1';
num_operations <= (others=>'0');
layer <= idle;
predict_en <= '1';
end case;
end process;
--------------------------------------------------------------------------------------------------------
end Behavioral;
| bsd-2-clause | 6a3a40e28de2300c37cec3f4103c6134 | 0.557904 | 3.385443 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/ipic_if_decode.vhd | 1 | 43,664 | -------------------------------------------------------------------------------
-- ipic_if_decode.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : ipic_if_decode.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI bus ipif decode logic
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
--------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics --
-------------------------------------------------------------------------------
-- C_SPLB_DWIDTH - Data width of PLB BUS.
-- C_NUM_PERIPHERALS - No of peripherals supported by external
-- peripheral controller in the current
-- configuration
-- C_PRH_CLK_SUPPORT - Indication of whether the synchronous interface
-- operates on peripheral clock or on PLB clock
-- C_PRH(0:3)_DWIDTH_MATCH - Indication of whether external peripheral (0:3)
-- supports multiple access cycle on the
-- peripheral interface for a single PLB cycle
-- when the peripheral data bus width is less than
-- that of PLB bus data width
-- C_PRH(0:3)_DWIDTH - External peripheral (0:3) data bus width
-- MAX_PERIPHERALS - Maximum number of peripherals supported by the
-- external peripheral controller
-- NO_PRH_SYNC - Indicates all devices are configured for
-- asynchronous interface
-- NO_PRH_ASYNC - Indicates all devices are configured for
-- synchronous interface
-- PRH_SYNC - Indicates if the devices are configured for
-- asynchronous or synchronous interface
-- NO_PRH_BUS_MULTIPLEX - Indicates that no device is employing
-- multiplexed bus
-- PRH_BUS_MULTIPLEX - Indicates if each of the external device
-- is configured for multiplexed bus or not
-- NO_PRH_DWIDTH_MATCH - Indication that no device is employing data
-- width matching
-- PRH_DWIDTH_MATCH - Indicates if each of the external device
-- is configured for data width matching or not
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Rst - IPIC reset
-- Local_Clk - Operational clock for peripheral interface
-- Local_Rst - Reset for peripheral interface
-- Bus2IP_CS - IPIC chip select signals
-- Bus2IP_RNW - IPIC read/write control
-- IP2Bus_WrAck - Write data acknowledgment to IPIC interface
-- IP2Bus_RdAck - Read data acknowledgment to IPIC interface
-- IP2Bus_Error - Error indication to IPIC interface
-- FIFO_access - Indicates if the current access is to a FIFO
-- - within the external peripheral device
-- Dev_id - The decoded identification vector for the currently
-- - selected device
-- Dev_fifo_access - Indicates if the current access is to a FIFO
-- within the external peripheral device. Registered
-- output of FIFO_access
-- Dev_in_access - Indicates if any of the peripheral device is
-- currently being accessed
-- Dev_sync_in_access - Indicates if any of synchronous the peripheral
-- device is currently being accessed
-- Dev_async_in_access - Indicates if any of asynchronous the peripheral
-- device is currently being accessed
-- Dev_sync - Indicates if the current device being accessed
-- is synchronous device
-- Dev_rnw - Read/write control indication
-- Dev_bus_multiplex - Indicates if the currently selected device employs
-- multiplexed bus
-- Dev_dwidth_match - Indicates if the current device employs data
-- width matching
-- Dev_dbus_width - Indicates decoded value for the data bus
-- IPIC_sync_req - Request to the synchronous control logic
-- IP_sync_req_rst - Request reset from the synchronous control logic
-- IPIC_async_req - Request to the asynchronous control logic
-- IP_sync_ack - Acknowledgement from the synchronous control logic
-- IPIC_sync_ack_rst - Acknowledgement reset to the synchronous control
-- IP_async_ack - Acknowledgement from the asynchronous control logic
-- IP_async_addrack - Address acknowledgement for asynchronous access from
-- the asynchronous control logic
-- IP_sync_error - Error indication for synchronous access from
-- the synchronous control logic
-- IP_async_error - Error indication for asynchronous access from
-- the asynchronous control logic
-------------------------------------------------------------------------------
entity ipic_if_decode is
generic (
C_SPLB_DWIDTH : integer;
C_NUM_PERIPHERALS : integer;
C_PRH_CLK_SUPPORT : integer;
C_PRH0_DWIDTH_MATCH : integer;
C_PRH1_DWIDTH_MATCH : integer;
C_PRH2_DWIDTH_MATCH : integer;
C_PRH3_DWIDTH_MATCH : integer;
C_PRH0_DWIDTH : integer;
C_PRH1_DWIDTH : integer;
C_PRH2_DWIDTH : integer;
C_PRH3_DWIDTH : integer;
MAX_PERIPHERALS : integer;
NO_PRH_SYNC : integer;
NO_PRH_ASYNC : integer;
PRH_SYNC : std_logic_vector;
NO_PRH_BUS_MULTIPLEX : integer;
PRH_BUS_MULTIPLEX : std_logic_vector;
NO_PRH_DWIDTH_MATCH : integer;
PRH_DWIDTH_MATCH : std_logic_vector
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
Local_Clk : in std_logic;
Local_Rst : in std_logic;
-- IPIC interface
Bus2IP_CS : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_RNW : in std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
FIFO_access : in std_logic;
Dev_id : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Dev_fifo_access : out std_logic;
Dev_in_access : out std_logic;
Dev_sync_in_access : out std_logic;
Dev_async_in_access : out std_logic;
Dev_sync : out std_logic;
Dev_rnw : out std_logic;
Dev_bus_multiplex : out std_logic;
Dev_dwidth_match : out std_logic;
Dev_dbus_width : out std_logic_vector(0 to 2);
-- Local interface
IPIC_sync_req : out std_logic;
IPIC_async_req : out std_logic;
IP_sync_req_rst : in std_logic;
IP_sync_Wrack : in std_logic;
IP_sync_Rdack : in std_logic;
IPIC_sync_ack_rst : out std_logic;
IP_async_Wrack : in std_logic;
IP_async_Rdack : in std_logic;
IP_sync_error : in std_logic;
IP_async_error : in std_logic
);
end entity ipic_if_decode;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of ipic_if_decode is
attribute ASYNC_REG : string;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- NAME: get_dbus_width
-------------------------------------------------------------------------------
-- Description: Generate a decoded value of type std_logic_vector
-- corresponding to the current data bus width of the device
-------------------------------------------------------------------------------
function get_dbus_width(prh_width : integer)
return std_logic_vector is
variable decoded_dbus_width : std_logic_vector(0 to 2);
begin
case prh_width is
when 8 =>
decoded_dbus_width := "001";
when 16 =>
decoded_dbus_width := "010";
when 32 =>
decoded_dbus_width := "100";
-- coverage off
when others =>
decoded_dbus_width := (others => '0');
-- coverage on
end case;
return decoded_dbus_width;
end function get_dbus_width;
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV3_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 2);
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant PRH_DBUS_WIDTH : SLV3_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
(get_dbus_width(C_PRH0_DWIDTH),
get_dbus_width(C_PRH1_DWIDTH),
get_dbus_width(C_PRH2_DWIDTH),
get_dbus_width(C_PRH3_DWIDTH));
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal dev_in_access_int : std_logic := '0';
signal dev_in_access_int_d1 : std_logic := '0';
signal access_start : std_logic := '0';
signal ip_async_Wrack_d1 : std_logic := '0';
signal ip_async_Wrack_d2 : std_logic := '0';
signal ip_async_Wrack_d3 : std_logic := '0';
signal ip_async_Wrack_d4 : std_logic := '0';
signal ip_async_Rdack_d1 : std_logic := '0';
signal ip_async_Rdack_d2 : std_logic := '0';
signal ip_async_Rdack_d3 : std_logic := '0';
signal ip_async_Rdack_d4 : std_logic := '0';
signal async_access_on : std_logic := '0';
signal async_req : std_logic := '0';
signal local_async_req : std_logic := '0';
signal ip_sync_Wrack_d1 : std_logic := '0';
signal ip_sync_Wrack_d2 : std_logic := '0';
signal ip_sync_Wrack_d3 : std_logic := '0';
signal ip_sync_Wrack_d4 : std_logic := '0';
signal ip_sync_Rdack_d1 : std_logic := '0';
signal ip_sync_Rdack_d2 : std_logic := '0';
signal ip_sync_Rdack_d3 : std_logic := '0';
signal ip_sync_Rdack_d4 : std_logic := '0';
signal sync_access_on : std_logic := '0';
signal sync_req : std_logic := '0';
signal local_sync_req : std_logic := '0';
signal sync_req_d1 : std_logic := '0';
signal local_sync_req_rst : std_logic := '0';
signal local_sync_req_d1 : std_logic := '0';
signal local_sync_req_d2 : std_logic := '0';
signal local_sync_req_d3 : std_logic := '0';
signal dev_sync_int : std_logic := '0';
signal dev_sync_i : std_logic := '0';
signal dev_burst_i : std_logic := '0';
signal dev_bus_multiplex_int : std_logic := '0';
signal dev_bus_multiplex_i : std_logic := '0';
signal dev_dwidth_match_int : std_logic := '0';
signal dev_dwidth_match_i : std_logic := '0';
signal dev_dbus_width_int : std_logic_vector(0 to 2)
:= (others => '0');
signal dev_dbus_width_i : std_logic_vector(0 to 2)
:= (others => '0');
signal ip2bus_Wrack_i : std_logic := '0';
signal ip2bus_Rdack_i : std_logic := '0';
signal temp_i : std_logic;
signal local_sync_req_i : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- DEV_IN_ACCESS_INT indicates that the PLB EPC is currently accessing an
-- external peripheral device
dev_in_access_int <= or_reduce(Bus2IP_CS(0 to C_NUM_PERIPHERALS-1));
---------------------------------------------------------------------------
-- NAME: REG_IPIC_PROCESS
---------------------------------------------------------------------------
-- Description: Register the ipic signal for the local interface.
-- These signals are not stable in case of abort. Therefore,
-- registering is required
---------------------------------------------------------------------------
REG_IPIC_PROCESS : process (Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
Dev_id <= (others => '0');
Dev_fifo_access <= '0';
Dev_rnw <= '1';
else
if (access_start = '1') then
Dev_id <= Bus2IP_CS;
Dev_fifo_access <= FIFO_access;
Dev_rnw <= Bus2IP_RNW;
end if;
end if;
end if;
end process REG_IPIC_PROCESS;
-------------------------------------------------------------------------------
-- NAME: NO_DEV_SYNC_GEN
-------------------------------------------------------------------------------
-- Description: Tie DEV_SYNC to low if there are no synchronous external
-- peripheral device
-------------------------------------------------------------------------------
NO_DEV_SYNC_GEN: if NO_PRH_SYNC = 1 generate
dev_sync_int <= '0';
Dev_sync <= '0';
end generate NO_DEV_SYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_SYNC_GEN
-------------------------------------------------------------------------------
-- Description: Generate DEV_SYNC if there are external peripheral devices
-- that are configured as synchronous
-------------------------------------------------------------------------------
DEV_SYNC_GEN: if NO_PRH_SYNC = 0 generate
--------------------------------------------------------------------------
-- NAME: DEV_SYNC_PROCESS
--------------------------------------------------------------------------
-- Description: Generate DEV_SYNC_INT if the current access corresponds to
-- synchronous external peripheral device
--------------------------------------------------------------------------
DEV_SYNC_PROCESS: process (Bus2IP_CS)
begin
dev_sync_int <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Bus2IP_CS(i) = '1') then
dev_sync_int <= PRH_SYNC(i);
end if;
end loop;
end process DEV_SYNC_PROCESS;
---------------------------------------------------------------------------
-- NAME: REG_DEV_SYNC_PROCESS
---------------------------------------------------------------------------
-- Description: Register the device synchronous indication signal
-- DEV_SYNC_INT
---------------------------------------------------------------------------
REG_DEV_SYNC_PROCESS : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
dev_sync_i <= '0';
else
if (access_start = '1') then
dev_sync_i <= dev_sync_int;
end if;
end if;
end if;
end process REG_DEV_SYNC_PROCESS;
Dev_sync <= dev_sync_i;
end generate DEV_SYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: NO_DEV_BUS_MULTIPLEX_GEN
-------------------------------------------------------------------------------
-- Description: Tie DEV_BUS_MULTIPLEX to low when no external device is
-- employing bus multiplexing
-------------------------------------------------------------------------------
NO_DEV_BUS_MULTIPLEX_GEN: if NO_PRH_BUS_MULTIPLEX = 1 generate
Dev_bus_multiplex <= '0';
end generate NO_DEV_BUS_MULTIPLEX_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_BUS_MULTIPLEX_GEN
-------------------------------------------------------------------------------
-- Description: Generate DEV_BUS_MULTIPLEX when any of the external device is
-- employing bus multiplexing
-------------------------------------------------------------------------------
DEV_BUS_MULTIPLEX_GEN: if NO_PRH_BUS_MULTIPLEX = 0 generate
-----------------------------------------------------------------------------
-- NAME: DEV_BUS_MULTIPLEX_PROCESS
-----------------------------------------------------------------------------
-- Description: Generate DEV_BUS_MULTIPLEX_INT if the currently selected
-- device employs bus multiplexing
-----------------------------------------------------------------------------
DEV_BUS_MULTIPLEX_PROCESS: process (Bus2IP_CS) is
begin
dev_bus_multiplex_int <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Bus2IP_CS(i) = '1') then
dev_bus_multiplex_int <= PRH_BUS_MULTIPLEX(i);
end if;
end loop;
end process DEV_BUS_MULTIPLEX_PROCESS;
---------------------------------------------------------------------------
-- NAME: REG_DEV_BUS_MULTIPLEX_PROCESS
---------------------------------------------------------------------------
-- Description: Register the device bus multiplex indication signal,
-- DEV_BUS_MULTIPLEX_INT
---------------------------------------------------------------------------
REG_DEV_BUS_MULTIPLEX_PROCESS : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
dev_bus_multiplex_i <= '0';
else
if (access_start = '1') then
dev_bus_multiplex_i <= dev_bus_multiplex_int;
end if;
end if;
end if;
end process REG_DEV_BUS_MULTIPLEX_PROCESS;
Dev_bus_multiplex <= dev_bus_multiplex_i;
end generate DEV_BUS_MULTIPLEX_GEN;
-------------------------------------------------------------------------------
-- NAME: NO_DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: Tie DEV_DWIDTH_MATCH to low if data bus width matching is
-- not enabled for any of the external peripheral device
-------------------------------------------------------------------------------
NO_DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 1 generate
Dev_dwidth_match <= '0';
end generate NO_DEV_DWIDTH_MATCH_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: Generate DEV_DWIDTH_MATCH if data bus width matching is
-- enabled for any external peripheral device
-------------------------------------------------------------------------------
DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 0 generate
-----------------------------------------------------------------------------
-- NAME: DEV_DWIDTH_MATCH_PROCESS
-----------------------------------------------------------------------------
-- Description: Generate DEV_DWIDTH_MATCH_INT for the currently selected
-- device. DEV_DWIDTH_MATCH_INT indicates if the current device
-- employs datawidth matching
-----------------------------------------------------------------------------
DEV_DWIDTH_MATCH_PROCESS: process (Bus2IP_CS) is
begin
Dev_dwidth_match_int <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Bus2IP_CS(i) = '1') then
Dev_dwidth_match_int <= PRH_DWIDTH_MATCH(i);
end if;
end loop;
end process DEV_DWIDTH_MATCH_PROCESS;
---------------------------------------------------------------------------
-- NAME: REG_DEV_DWIDTH_MATCH_PROCESS
---------------------------------------------------------------------------
-- Description: Register the device dwidth match indication signal,
-- DEV_DWIDTH_MATCH_INT
---------------------------------------------------------------------------
REG_DEV_DWIDTH_MATCH_PROCESS : process(Bus2IP_Clk) is
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
dev_dwidth_match_i <= '0';
else
if (access_start = '1') then
dev_dwidth_match_i <= dev_dwidth_match_int;
end if;
end if;
end if;
end process REG_DEV_DWIDTH_MATCH_PROCESS;
Dev_dwidth_match <= dev_dwidth_match_i;
end generate DEV_DWIDTH_MATCH_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_DBUS_WIDTH_PROCESS
-------------------------------------------------------------------------------
-- Description: Generate DEV_DBUS_WIDTH_INT for the currently selected device
-- DEV_DBUS_WIDTH_INT indicates the data bus width of the
-- currently selected device
-------------------------------------------------------------------------------
DEV_DBUS_WIDTH_PROCESS: process (Bus2IP_CS) is
begin
dev_dbus_width_int <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Bus2IP_CS(i) = '1') then
dev_dbus_width_int <= PRH_DBUS_WIDTH(i);
end if;
end loop;
end process DEV_DBUS_WIDTH_PROCESS;
---------------------------------------------------------------------------
-- NAME: REG_DEV_DBUS_WIDTH_PROCESS
---------------------------------------------------------------------------
-- Description: Register the decoded value of device data bus width,
-- DEV_DBUS_WIDTH_INT
---------------------------------------------------------------------------
REG_DEV_DBUS_WIDTH_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
dev_dbus_width_i <= (others => '0');
else
if (access_start = '1') then
dev_dbus_width_i <= dev_dbus_width_int;
end if;
end if;
end if;
end process REG_DEV_DBUS_WIDTH_PROCESS;
Dev_dbus_width <= dev_dbus_width_i;
-------------------------------------------------------------------------------
-- NAME: ACCESS_START_PROCESS
-------------------------------------------------------------------------------
-- Description: Register the start of the transaction
-------------------------------------------------------------------------------
ACCESS_START_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1')then
dev_in_access_int_d1 <= '0';
else
dev_in_access_int_d1 <= dev_in_access_int;
end if;
end if;
end process ACCESS_START_PROCESS;
-- Generate a pulse to identify start of the transaction
access_start <= dev_in_access_int and not dev_in_access_int_d1;
-------------------------------------------------------------------------------
-- NAME: ASYNC_REQ_GEN
-------------------------------------------------------------------------------
-- Description: Generate asynchronous request signal if any of the device is
-- configured for asynchronous access
-------------------------------------------------------------------------------
ASYNC_REQ_GEN: if NO_PRH_ASYNC = 0 generate
---------------------------------------------------------------------------
-- NAME: DELAY_ASYNC_WR_ACK_PROCESS
---------------------------------------------------------------------------
-- Description: Delay the write acknowledgement from asynchronous control logic
-- to generate request in case of burst access
---------------------------------------------------------------------------
DELAY_ASYNC_WR_ACK_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1' or dev_in_access_int = '0') then
ip_async_Wrack_d1 <= '0';
ip_async_Wrack_d2 <= '0';
ip_async_Wrack_d3 <= '0';
ip_async_Wrack_d4 <= '0';
else
ip_async_Wrack_d1 <= IP_async_Wrack;
ip_async_Wrack_d2 <= ip_async_Wrack_d1;
ip_async_Wrack_d3 <= ip_async_Wrack_d2;
ip_async_Wrack_d4 <= ip_async_Wrack_d3;
end if;
end if;
end process DELAY_ASYNC_WR_ACK_PROCESS;
---------------------------------------------------------------------------
-- NAME: DELAY_ASYNC_RD_ACK_PROCESS
---------------------------------------------------------------------------
-- Description: Delay the Read acknowledgement from asynchronous control logic
-- to generate request in case of burst access
---------------------------------------------------------------------------
DELAY_ASYNC_RD_ACK_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1' or dev_in_access_int = '0') then
ip_async_Rdack_d1 <= '0';
ip_async_Rdack_d2 <= '0';
ip_async_Rdack_d3 <= '0';
ip_async_Rdack_d4 <= '0';
else
ip_async_Rdack_d1 <= IP_async_Rdack;
ip_async_Rdack_d2 <= ip_async_Rdack_d1;
ip_async_Rdack_d3 <= ip_async_Rdack_d2;
ip_async_Rdack_d4 <= ip_async_Rdack_d3;
end if;
end if;
end process DELAY_ASYNC_RD_ACK_PROCESS;
-- If the burst indication stays during delayed acknowledgement then,
-- generate ACCESS_ON signal. This signal will be high for only
-- one clock pulse because ip_async_Wrack_d4 and ip_async_Rdack_d4
-- will be only one clock.
async_access_on <= dev_in_access_int and (ip_async_Wrack_d4 or
ip_async_Rdack_d4);
-- Generate a one clock ASYNC_REQ signal for every access
async_req <= dev_in_access_int and
not dev_sync_int and
(access_start or async_access_on);
---------------------------------------------------------------------------
-- NAME: ASYNC_REQ_PROCESS
---------------------------------------------------------------------------
-- Description: Register and hold the asynchronous request signal until
-- acknowledged by the local interface or a master abort on
-- PLB bus occurs
---------------------------------------------------------------------------
ASYNC_REQ_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
local_async_req <= '0';
else
if (dev_in_access_int = '0' or IP_async_Wrack = '1'
or IP_async_Rdack = '1') then
local_async_req <= '0';
elsif (async_req = '1') then
local_async_req <= '1';
end if;
end if;
end if;
end process ASYNC_REQ_PROCESS;
IPIC_async_req <= not dev_sync_int and local_async_req;
Dev_async_in_access <= dev_in_access_int and (not dev_sync_int);
end generate ASYNC_REQ_GEN;
-------------------------------------------------------------------------------
-- NAME: NO_ASYNC_REQ_GEN
-------------------------------------------------------------------------------
-- Description: Tie asynchronous request signal and asynchronous device
-- interface in access indication low if no device is
-- configured for asynchronous access
-------------------------------------------------------------------------------
NO_ASYNC_REQ_GEN: if NO_PRH_ASYNC = 1 generate
Dev_async_in_access <= '0';
IPIC_async_req <= '0';
end generate NO_ASYNC_REQ_GEN;
-------------------------------------------------------------------------------
-- NAME: NO_SYNC_REQ_GEN
-------------------------------------------------------------------------------
-- Description: Tie synchronous request signal and synchronous device
-- interface in access indication low if no device is
-- configured for synchronous access
-------------------------------------------------------------------------------
NO_SYNC_REQ_GEN: if NO_PRH_SYNC = 1 generate
Dev_sync_in_access <= '0';
IPIC_sync_req <= '0';
IPIC_sync_ack_rst <= '1';
end generate NO_SYNC_REQ_GEN;
-------------------------------------------------------------------------------
-- NAME: SYNC_REQ_GEN
-------------------------------------------------------------------------------
-- Description: Generate synchronous request signal if any of the device is
-- configured for synchronous access
-------------------------------------------------------------------------------
SYNC_REQ_GEN: if NO_PRH_SYNC = 0 generate
---------------------------------------------------------------------------
-- NAME: DELAY_ACK_PROCESS
---------------------------------------------------------------------------
-- Description: Delay the acknowledgement from synchronous control logic
-- to generate request in case of burst access
---------------------------------------------------------------------------
DELAY_WR_ACK_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1' or dev_in_access_int = '0') then
ip_sync_Wrack_d1 <= '0';
ip_sync_Wrack_d2 <= '0';
ip_sync_Wrack_d3 <= '0';
ip_sync_Wrack_d4 <= '0';
else
ip_sync_Wrack_d1 <= IP_sync_Wrack;
ip_sync_Wrack_d2 <= ip_sync_Wrack_d1;
ip_sync_Wrack_d3 <= ip_sync_Wrack_d2;
ip_sync_Wrack_d4 <= ip_sync_Wrack_d3;
end if;
end if;
end process DELAY_WR_ACK_PROCESS;
---------------------------------------------------------------------------
-- NAME: DELAY_RD_ACK_PROCESS
---------------------------------------------------------------------------
-- Description: Delay the read acknowledgement from synchronous control logic
-- to generate request in case of burst access
---------------------------------------------------------------------------
DELAY_RD_ACK_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1' or dev_in_access_int = '0') then
ip_sync_Rdack_d1 <= '0';
ip_sync_Rdack_d2 <= '0';
ip_sync_Rdack_d3 <= '0';
ip_sync_Rdack_d4 <= '0';
else
ip_sync_Rdack_d1 <= IP_sync_Rdack;
ip_sync_Rdack_d2 <= ip_sync_Rdack_d1;
ip_sync_Rdack_d3 <= ip_sync_Rdack_d2;
ip_sync_Rdack_d4 <= ip_sync_Rdack_d3;
end if;
end if;
end process DELAY_RD_ACK_PROCESS;
-- If the burst indication stays during delayed acknowledgement then,
-- generate ACCESS_ON signal. This signal will be high for only
-- one clock pulse because ip_sync_Wrack_d4 will be only one clock.
sync_access_on <= dev_in_access_int and (ip_sync_Wrack_d4 or ip_sync_Rdack_d4);
-- Generate a one clock SYNC_REQ signal for every access
sync_req <= dev_in_access_int and
dev_sync_int and
(access_start or sync_access_on);
-----------------------------------------------------------------------------
-- NAME: SYNC_REQ_NO_PRH_CLK_GEN
-----------------------------------------------------------------------------
-- Description: Generate request when the synchronous interface operates
-- on PLB clock
-----------------------------------------------------------------------------
SYNC_REQ_NO_PRH_CLK_GEN: if C_PRH_CLK_SUPPORT = 0 generate
---------------------------------------------------------------------------
-- NAME: SYNC_NO_PRH_CLK_REQ_PROCESS
---------------------------------------------------------------------------
-- Description: Register the request until acknowledged by the local
-- interface or a master abort occurs
---------------------------------------------------------------------------
SYNC_NO_PRH_CLK_REQ_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
local_sync_req <= '0';
else
if (dev_in_access_int='0' or IP_sync_Wrack='1' or IP_sync_Rdack='1')
then
local_sync_req <= '0';
elsif (sync_req = '1') then
local_sync_req <= '1';
end if;
end if;
end if;
end process SYNC_NO_PRH_CLK_REQ_PROCESS;
IPIC_sync_req <= dev_sync_int and local_sync_req;
IPIC_sync_ack_rst <= '1';
Dev_sync_in_access <= dev_in_access_int and dev_sync_int;
end generate SYNC_REQ_NO_PRH_CLK_GEN;
-----------------------------------------------------------------------------
-- NAME: SYNC_REQ_PRH_CLK_GEN
-----------------------------------------------------------------------------
-- Description: The synchronous interface operates on the local clock.
-- Generate request and double synchronize it.
-----------------------------------------------------------------------------
SYNC_REQ_PRH_CLK_GEN: if C_PRH_CLK_SUPPORT = 1 generate
attribute ASYNC_REG of REG_SYNC_REQ : label is "TRUE";
begin
---------------------------------------------------------------------------
-- NAME: REQ_PULSE_GEN_PROCESS
---------------------------------------------------------------------------
-- Description: Register the SYNC_REQ signal: Needs to be an output of a
-- flip flop because this is going to be used as clocking
-- signal for the latch generating the request for the
-- synchronous control logic
---------------------------------------------------------------------------
REQ_PULSE_GEN_PROCESS : process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (Bus2IP_Rst = '1') then
sync_req_d1 <= '0';
else
sync_req_d1 <= sync_req;
end if;
end if;
end process REQ_PULSE_GEN_PROCESS;
temp_i <= (Local_Rst or IP_sync_req_rst) or not(dev_in_access_int);
---------------------------------------------------------------------------
-- Description: Latch the SYNC_REQ_D1 signal. Hold it until it is reset
-- from the synchronous control state machine which indicates
-- the current request is acknowledged by the local interface
-- The condition here is as soon as the sync_req_d1 is detected active the output
-- should be active "high". The output is reseted, with the condition of "temp_i".
---------------------------------------------------------------------------
REQ_HOLD_GEN_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (temp_i = '1') then
local_sync_req_i <= '0';
elsif(sync_req_d1 = '1') then
local_sync_req_i <= '1';
end if;
end if;
end process REQ_HOLD_GEN_PROCESS;
local_sync_req <= sync_req_d1 or (local_sync_req_i and (not temp_i));
--------------------------------------------------------------------------------
local_sync_req_rst <= Local_Rst or IP_sync_req_rst;
REG_SYNC_REQ: component FDRE
port map (
Q => local_sync_req_d1,
C => Local_Clk,
CE => '1',
D => local_sync_req,
R => local_sync_req_rst
);
---------------------------------------------------------------------------
-- NAME: DOUBLE_SYNC_REQ_PROCESS
---------------------------------------------------------------------------
-- Description: Double synchronize the synchronous request signal
---------------------------------------------------------------------------
DOUBLE_SYNC_REQ_PROCESS: process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1') then
if (local_sync_req_rst = '1') then
local_sync_req_d2 <= '0';
local_sync_req_d3 <= '0';
else
local_sync_req_d2 <= local_sync_req_d1;
local_sync_req_d3 <= local_sync_req_d2;
end if;
end if;
end process DOUBLE_SYNC_REQ_PROCESS;
-- Generate request for the syncrhonous control logic
IPIC_sync_req <= local_sync_req_d3;
dev_sync_in_access <= local_sync_req_d3 and dev_sync_i;
---------------------------------------------------------------------------
-- NAME: SYNC_ACK_RST_PROCESS
---------------------------------------------------------------------------
-- Description: Reset acknowldgement generation logic in synchronous
-- control; This signal is inactive during an active request
-- cycle i.e. from the time request is generated to the time
-- it is acknowledged by the local interface
---------------------------------------------------------------------------
SYNC_ACK_RST_PROCESS : process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Bus2IP_Rst = '1' or dev_in_access_int = '0' ) then
IPIC_sync_ack_rst <= '1';
else
if (sync_req_d1 = '1') then
IPIC_sync_ack_rst <= '0';
elsif (IP_sync_Wrack = '1' or IP_sync_Rdack = '1') then
IPIC_sync_ack_rst <= '1';
end if;
end if;
end if;
end process SYNC_ACK_RST_PROCESS;
end generate SYNC_REQ_PRH_CLK_GEN;
end generate SYNC_REQ_GEN;
Dev_in_access <= dev_in_access_int;
ip2bus_Wrack_i <= dev_in_access_int and (IP_sync_Wrack or IP_async_Wrack);
ip2bus_Rdack_i <= dev_in_access_int and (IP_sync_Rdack or IP_async_Rdack);
IP2Bus_WrAck <= ip2bus_Wrack_i;
IP2Bus_RdAck <= ip2bus_Rdack_i;
IP2Bus_Error <= dev_in_access_int and (IP_sync_error or IP_async_error);
end architecture imp;
--------------------------------end of file------------------------------------
| gpl-3.0 | 51f034f23eccc9b281081108f13837b2 | 0.442378 | 4.5803 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/blk_mem_gen_v7_3/simulation/blk_mem_gen_v7_3_synth.vhd | 1 | 7,926 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY blk_mem_gen_v7_3_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE blk_mem_gen_v7_3_synth_ARCH OF blk_mem_gen_v7_3_synth IS
COMPONENT blk_mem_gen_v7_3_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: blk_mem_gen_v7_3_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| bsd-2-clause | 774fe89f7dd58ee729aa833a8a2f87c8 | 0.564724 | 3.714152 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_pkg.vhd | 1 | 11,527 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE k7_prime_fifo_plain_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT k7_prime_fifo_plain_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT k7_prime_fifo_plain_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END k7_prime_fifo_plain_pkg;
PACKAGE BODY k7_prime_fifo_plain_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END k7_prime_fifo_plain_pkg;
| gpl-2.0 | d56d4f2d9e99c36208f5b4d830a94b7e | 0.507591 | 3.907458 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/vector_norer.vhd | 1 | 1,691 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 11-04-2017
-- Package Name: alu/components
-- Module Name: VECTOR_NORER
--------------------------------------------------------------------------------
-- This module can get a vector and nor all bits in a vector to the output
library IEEE;
use IEEE.std_logic_1164.all;
entity VECTOR_NORER is
port(
INPUT : in std_logic_vector(15 downto 0);
OUTPUT : out std_logic
);
end entity;
architecture VECTOR_NORER_ARCH of VECTOR_NORER is
signal BIT_RESULT : std_logic_vector(15 downto 1);
signal NOT_OF_INPUT : std_logic_vector(15 downto 0);
begin
NOT_OF_INPUT <= not INPUT;
BIT_RESULT(1) <= NOT_OF_INPUT(0) and NOT_OF_INPUT(1);
BIT_RESULT(2) <= NOT_OF_INPUT(2) and BIT_RESULT(1);
BIT_RESULT(3) <= NOT_OF_INPUT(3) and BIT_RESULT(2);
BIT_RESULT(4) <= NOT_OF_INPUT(4) and BIT_RESULT(3);
BIT_RESULT(5) <= NOT_OF_INPUT(5) and BIT_RESULT(4);
BIT_RESULT(6) <= NOT_OF_INPUT(6) and BIT_RESULT(5);
BIT_RESULT(7) <= NOT_OF_INPUT(7) and BIT_RESULT(6);
BIT_RESULT(8) <= NOT_OF_INPUT(8) and BIT_RESULT(7);
BIT_RESULT(9) <= NOT_OF_INPUT(9) and BIT_RESULT(8);
BIT_RESULT(10) <= NOT_OF_INPUT(10) and BIT_RESULT(9);
BIT_RESULT(11) <= NOT_OF_INPUT(11) and BIT_RESULT(10);
BIT_RESULT(12) <= NOT_OF_INPUT(12) and BIT_RESULT(11);
BIT_RESULT(13) <= NOT_OF_INPUT(13) and BIT_RESULT(12);
BIT_RESULT(14) <= NOT_OF_INPUT(14) and BIT_RESULT(13);
BIT_RESULT(15) <= NOT_OF_INPUT(15) and BIT_RESULT(14);
OUTPUT <= BIT_RESULT(15);
end architecture; | gpl-3.0 | a3a932aa9dc7c5da64a692844b47b6f5 | 0.561798 | 2.961471 | false | false | false | false |
UnofficialRepos/OSVVM | demo/AlertLog_Demo_Global.vhd | 2 | 7,049 | --
-- File Name: AlertLog_Demo_Global.vhd
-- Design Unit Name: AlertLog_Demo_Global
-- Revision: STANDARD VERSION, 2015.01
--
-- Copyright (c) 2015 by SynthWorks Design Inc. All rights reserved.
--
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description:
-- Demo showing use of the global counter in AlertLogPkg
--
-- Developed for:
-- SynthWorks Design Inc.
-- Training Courses
-- 11898 SW 128th Ave.
-- Tigard, Or 97223
-- http://www.SynthWorks.com
--
--
-- Revision History:
-- Date Version Description
-- 01/2015 2015.01 Refining tests
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use std.textio.all ;
use ieee.std_logic_textio.all ;
library osvvm ;
use osvvm.OsvvmGlobalPkg.all ;
use osvvm.TranscriptPkg.all ;
use osvvm.AlertLogPkg.all ;
entity AlertLog_Demo_Global is
end AlertLog_Demo_Global ;
architecture hierarchy of AlertLog_Demo_Global is
signal Clk : std_logic := '0';
begin
Clk <= not Clk after 10 ns ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Testbench_1 : block
begin
TbP0 : process
variable ClkNum : integer := 0 ;
begin
wait until Clk = '1' ;
ClkNum := ClkNum + 1 ;
print(LF & "Clock Number " & to_string(ClkNum)) ;
end process TbP0 ;
------------------------------------------------------------
TbP1 : process
begin
-- Uncomment this line to use a log file rather than OUTPUT
-- TranscriptOpen("./Demo_Global.txt") ;
-- Uncomment this line and the simulation will stop after 15 errors
-- SetAlertStopCount(ERROR, 15) ;
SetAlertLogName("AlertLog_Demo_Global") ;
wait for 0 ns ; -- make sure all processes have elaborated
SetLogEnable(DEBUG, TRUE) ; -- Enable DEBUG Messages for all levels of the hierarchy
-- Uncomment this line to justify alert and log reports
-- SetAlertLogJustify ;
for i in 1 to 5 loop
wait until Clk = '1' ;
if i = 4 then SetLogEnable(DEBUG, FALSE) ; end if ; -- DEBUG Mode OFF
wait for 1 ns ;
Alert("Tb.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log ("Tb.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait until Clk = '1' ;
wait until Clk = '1' ;
wait for 1 ns ;
ReportAlerts ;
print("") ;
-- Report Alerts with expected errors expressed as a negative ExternalErrors value
ReportAlerts(Name => "AlertLog_Demo_Hierarchy with expected errors", ExternalErrors => -(FAILURE => 0, ERROR => 20, WARNING => 15)) ;
TranscriptClose ;
print(LF & "The following is brought to you by std.env.stop:") ;
std.env.stop ;
wait ;
end process TbP1 ;
------------------------------------------------------------
TbP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 2 ns ;
Alert("Tb.P2.E alert " & to_string(i) & " of 5", ERROR) ;
-- example of a log that is not enabled, so it does not print
Log ("Tb.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait until Clk = '1' ;
wait for 2 ns ;
-- Uncomment this line to and the simulation will stop here
-- Alert("Tb.P2.F Message 1 of 1", FAILURE) ;
wait ;
end process TbP2 ;
------------------------------------------------------------
TbP3 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 3 ns ;
Alert("Tb.P3.W alert " & to_string(i) & " of 5", WARNING) ;
end loop ;
wait ;
end process TbP3 ;
end block Testbench_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Cpu_1 : block
begin
------------------------------------------------------------
CpuP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 5 ns ;
Alert("Cpu.P1.E Message " & to_string(i) & " of 5", ERROR) ;
Log ("Cpu.P1.D log " & to_string(i) & " of 5", DEBUG) ;
Log ("Cpu.P1.F log " & to_string(i) & " of 5", FINAL) ; -- enabled by Uart_1
end loop ;
wait ;
end process CpuP1 ;
------------------------------------------------------------
CpuP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 6 ns ;
Alert("Cpu.P2.W Message " & to_string(i) & " of 5", WARNING) ;
Log ("Cpu.P2.I log " & to_string(i) & " of 5", INFO) ;
end loop ;
wait ;
end process CpuP2 ;
end block Cpu_1 ;
-- /////////////////////////////////////////////////////////////
-- \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\
Uart_1 : block
begin
-- Enable FINAL logs for every level
-- Note it is expected that most control of alerts will occur only in the testbench block
-- Note that this also turns on FINAL messages for CPU - see hierarchy for better control
SetLogEnable(FINAL, TRUE) ; -- Runs once at initialization time
------------------------------------------------------------
UartP1 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 10 ns ;
Alert("Uart.P1.E alert " & to_string(i) & " of 5") ; -- ERROR by default
Log ("UART.P1.D log " & to_string(i) & " of 5", DEBUG) ;
end loop ;
wait ;
end process UartP1 ;
------------------------------------------------------------
UartP2 : process
begin
for i in 1 to 5 loop
wait until Clk = '1' ;
wait for 11 ns ;
Alert("Uart.P2.W alert " & to_string(i) & " of 5", WARNING) ;
-- Info not enabled
Log ("UART.P2.I log " & to_string(i) & " of 5", INFO) ;
Log ("UART.P2.F log " & to_string(i) & " of 5", FINAL) ;
end loop ;
wait ;
end process UartP2 ;
end block Uart_1 ;
end hierarchy ; | artistic-2.0 | 3b4d80fa9dec31207e9d3708e00bf538 | 0.509434 | 3.741507 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/tsc_tb.vhd | 1 | 5,445 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : tsc_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-06-28
-- Last update: 2017-05-27
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Testbench for time stamp counter
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-06-28 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity tsc_tb is
end tsc_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.tb_pkg.all;
architecture STRUCTURE of tsc_tb is
component tsc
port (
rst_n : in std_logic;
clk : in std_logic;
gps_1pps : in std_logic;
gps_3dfix_d : in std_logic;
tsc_read : in std_logic;
tsc_sync : in std_logic;
pfd_resync : in std_logic;
gps_1pps_d : out std_logic;
tsc_1pps_d : out std_logic;
pll_trig : out std_logic;
pfd_status : out std_logic;
pdiff_1pps : out std_logic_vector(31 downto 0);
fdiff_1pps : out std_logic_vector(31 downto 0);
tsc_cnt : out std_logic_vector(63 downto 0);
tsc_cnt1 : out std_logic_vector(63 downto 0);
tsc_1pps : out std_logic;
tsc_1ppms : out std_logic;
tsc_1ppus : out std_logic
);
end component;
SIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL gps_1pps : std_logic;
SIGNAL gps_3dfix_d : std_logic;
SIGNAL tsc_read : std_logic;
SIGNAL tsc_sync : std_logic;
SIGNAL pfd_resync : std_logic;
SIGNAL gps_1pps_d : std_logic;
SIGNAL tsc_1pps_d : std_logic;
SIGNAL pll_trig : std_logic;
SIGNAL pfd_status : std_logic;
SIGNAL pdiff_1pps : std_logic_vector(31 downto 0);
SIGNAL fdiff_1pps : std_logic_vector(31 downto 0);
SIGNAL tsc_cnt : std_logic_vector(63 downto 0);
SIGNAL tsc_cnt1 : std_logic_vector(63 downto 0);
SIGNAL tsc_1pps : std_logic;
SIGNAL tsc_1ppms : std_logic;
SIGNAL tsc_1ppus : std_logic;
begin
tsc_i: tsc
port map (
rst_n => rst_n,
clk => clk,
gps_1pps => gps_1pps,
gps_3dfix_d => gps_3dfix_d,
tsc_read => tsc_read,
tsc_sync => tsc_sync,
pfd_resync => pfd_resync,
gps_1pps_d => gps_1pps_d,
tsc_1pps_d => tsc_1pps_d,
pll_trig => pll_trig,
pfd_status => pfd_status,
pdiff_1pps => pdiff_1pps,
fdiff_1pps => fdiff_1pps,
tsc_cnt => tsc_cnt,
tsc_cnt1 => tsc_cnt1,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus
);
clk_100MHZ: clk_gen(10 ns, 50, clk);
reset: rst_n_gen(1 us, rst_n);
gps_3dfix_d <= '0';
tsc_read <= '0';
process
begin
gps_1pps <= '0';
tsc_sync <= '0';
pfd_resync <= '0';
run_clk(clk, 100000099);
-- tsc pps pulse starts here
run_clk(clk, 1000);
-- Generate gps pps pulse 1000 cycles later
-- 1s
gps_1pps <= '1';
run_clk(clk, 1);
gps_1pps <= '0';
run_clk(clk, 99997999);
-- 1000 cycles before tsc
-- 2s
gps_1pps <= '1';
run_clk(clk, 1);
gps_1pps <= '0';
run_clk(clk, 100000999);
-- In line with tsc
-- 3s
gps_1pps <= '0';
run_clk(clk, 1);
gps_1pps <= '0';
run_clk(clk, 100000999);
-- 1000 cycles after tsc
-- 4s
gps_1pps <= '1';
run_clk(clk, 1);
gps_1pps <= '0';
-- trigger resync
-- 4.5s
run_clk(clk, 49999999);
--tsc_sync <= '1';
run_clk(clk, 50000000);
-- tsc resynced
-- 4 cycles before tsc from pipeline delay
-- 5s
gps_1pps <= '1';
run_clk(clk, 1);
gps_1pps <= '0';
run_clk(clk, 4);
tsc_sync <= '0';
run_clk(clk, 99999995);
-- 4 cycles before tsc from pipeline delay
-- 6s...
loop
gps_1pps <= '1';
run_clk(clk, 1);
gps_1pps <= '0';
run_clk(clk, 99999999);
end loop;
end process;
end STRUCTURE;
| gpl-3.0 | d9da174498cf64759ec57dea6f1474d6 | 0.421671 | 3.506117 | false | false | false | false |
peteut/nvc | test/group/issue371.vhd | 2 | 1,837 | entity issue371 is
end issue371;
architecture behav of issue371 is
signal clock : bit;
signal chip_select_sig : bit;
signal address_sig : bit_vector(2 downto 0);
signal write_sig : bit;
signal host_data_bus_sig : bit_vector(7 downto 0);
function rising_edge(signal x : bit) return boolean is
begin
return x = '1' and x'last_value = '0';
end function;
procedure wait_for_ticks (num_clock_cycles : in integer) is
begin
for i in 1 to num_clock_cycles loop
wait until rising_edge(clock);
end loop;
end procedure wait_for_ticks;
procedure host_write (addr: in bit_vector;
byte : in bit_vector;
signal clock : in bit;
signal chip_select : out bit;
signal address : out bit_vector;
signal write : out bit;
signal host_data_bus : out bit_vector;
invert_cs_etc : in bit
) is
begin
wait until rising_edge(clock);
write <= '1' xor invert_cs_etc;
chip_select <= '1' xor invert_cs_etc;
address <= addr;
host_data_bus <= byte;
wait_for_ticks(1);
write <= '0' xor invert_cs_etc;
chip_select <= '0' xor invert_cs_etc;
for i in address'LOW to address'HIGH loop
address(i) <= '0';
end loop;
for i in host_data_bus'LOW to host_data_bus'HIGH loop
host_data_bus(i) <= '0';
end loop;
wait until rising_edge(clock);
end procedure host_write;
begin
process
begin
for i in 0 to 10 loop
clock <= '0';
wait for 1 us;
clock <= '1';
wait for 1 us;
end loop;
wait;
end process;
process
begin
host_write("001", X"aa", clock, chip_select_sig, address_sig, write_sig, host_data_bus_sig, '0');
for i in address_sig'LOW to address_sig'HIGH loop
assert address_sig(i) = '0';
end loop;
for i in host_data_bus_sig'LOW to host_data_bus_sig'HIGH loop
assert host_data_bus_sig(i) = '0';
end loop;
wait;
end process;
end behav;
| gpl-3.0 | 57e5fb7e85d4a49c84f3f2a7a0131bd9 | 0.656505 | 2.834877 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_dgen.vhd | 1 | 4,616 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_eb_fifo_counted_resized_pkg.ALL;
ENTITY k7_eb_fifo_counted_resized_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF k7_eb_fifo_counted_resized_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:k7_eb_fifo_counted_resized_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 5a975fad56bd8fd7b58459258b09b205 | 0.604203 | 4.173599 | false | false | false | false |
peteut/nvc | test/sem/issue340.vhd | 2 | 1,103 | entity submodule is
port (
sig : in bit);
end entity;
architecture a of submodule is
begin
main : process
begin
wait for 1 ns;
assert sig = '1';
report "Success";
wait;
end process;
end;
entity bug is
end entity;
architecture a of bug is
signal sig_vector : bit_vector(0 to 1) := "00";
alias sig_bit_alias : bit is sig_vector(0);
signal sig : bit := '0';
alias sig_alias : bit is sig;
procedure drive(signal value : out bit) is
begin
value <= '1';
end;
begin
main : process
begin
drive(sig_alias);
drive(sig_bit_alias);
wait for 1 ns;
assert sig_vector(0) = '1';
assert sig = '1';
assert sig_alias = '1';
assert sig_bit_alias = '1';
report "Success";
wait;
end process;
submodule0_inst : entity work.submodule
port map (
sig => sig_alias);
submodule1_inst : entity work.submodule
port map (
sig => sig_bit_alias);
submodule2_inst : entity work.submodule
port map (
sig => sig);
submodule3_inst : entity work.submodule
port map (
sig => sig_vector(0));
end;
| gpl-3.0 | 3ee61d8e9f93ca99f87f54a74e9e3786 | 0.608341 | 3.436137 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/hidden_layer.vhd | 1 | 4,266 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.custom_pkg.all;
-- num_neurons is defined in the custom_package --
entity hidden_layer is
generic ( N : Integer );
port ( clk : in std_logic ;
num_operations : in std_logic_vector(7 downto 0);
layer : in layer_type;
rst : in std_logic ;
input : in std_logic_vector(7 downto 0);
weight : in eight_bit(N-1 downto 0);
shift_over_flag : out std_logic;
active_activation: out std_logic;
output_hid : out eight_bit(N-1 downto 0)
);
end hidden_layer;
architecture Behavioral of hidden_layer is
signal ce, sclr, bypass, count_en, activation, shift_activate : std_logic := '0';
signal weighted_sum : sixteen_bit(num_neurons-1 downto 0) := (others=> (others=>'0'));
signal activ_output : thirtytwo_bit(num_neurons-1 downto 0);
type shift_array is array (num_neurons-1 downto 0) of std_logic;
signal shift_over : shift_array;
--signal activ_output : std_logic_vector(31 downto 0);
--signal weighted_sum, weighted_sum_reg,weighted_sum_reg_in : sixteen_bit(2 downto 0) := (others=> (others=>'0'));
COMPONENT neuron_hid
port ( clk : in std_logic;
ce : in std_logic;
sclr : in std_logic;
bypass : in std_logic;
im : in std_logic_vector(7 downto 0);
weig_hid : in std_logic_vector( 7 downto 0);
hid_out : out std_logic_vector (15 downto 0)
);
END COMPONENT;
COMPONENT activation_hid_count
port ( clk : in std_logic;
count_en : in std_logic;
num_operations : in std_logic_vector(7 downto 0);
activation : out std_logic
);
END COMPONENT;
COMPONENT shifter
port ( clk : in std_logic;
input : in std_logic_vector(15 downto 0);
enable : in std_logic;
shift_over_flag : out std_logic;
active_output : out std_logic_vector(31 downto 0)
);
END COMPONENT;
begin
neuron_map:
for n in num_neurons-1 downto 0 generate
begin
neurons : neuron_hid port map (clk,ce,sclr,bypass,input,weight(n),weighted_sum(n));
end generate neuron_map;
---------------
---- NOTE -----
---------------
--- it takes one clock cycle to read data from BRAM so the weighted_sum_layer has to operate for 1 cycle more ---
activation_hid_count_map : activation_hid_count
port map (clk,count_en,num_operations,activation);
shift_map:
for m in num_neurons-1 downto 0 generate
begin
shifter_map : shifter port map (clk,weighted_sum(m),shift_activate,shift_over(m),activ_output(m));
end generate shift_map;
active_activation <= activation;
concurrent_assignment : for i in num_neurons-1 downto 0 generate
output_hid(i) <= activ_output(i)(25 downto 24) & activ_output(i)(23 downto 18);
end generate;
shift_over_flag <= shift_over(0);
sclr <= '0';
bypass <= '0';
process (activation,layer,rst) begin
if rst = '1' then
count_en <= '0';
shift_activate <= '0';
ce <= '0';
else
ce <= '1';
if layer = weighted_sum_layer1 or layer = weighted_sum_layer2 then
count_en <= '1';
if activation = '1' then
shift_activate <= '1';
else
shift_activate <= '0';
end if;
else
count_en <= '0';
shift_activate <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------
--instead of registering the whole weighted_sum, it is efficient to input image as "zero" so the accumulated weight remains same
--------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------
--If you want to assign array of signal concurrently use generate signal
-------------------------------------------------------------------------
--Registering_Weighted_Sum : process (clk) begin
-- if rising_edge(clk) then
-- weighted_sum_reg <= weighted_sum_reg_in;
-- end if;
--end process;
--
--process (activation,weighted_sum,weighted_sum_reg) begin
-- if activation = '1' then
-- weighted_sum_reg_in <= weighted_sum;
-- else
-- weighted_sum_reg_in <= weighted_sum_reg;
-- end if;
--end process;
--
--process (shift_activate) begin
-- if
--
--end process;
end Behavioral;
| bsd-2-clause | 8f3d3aede3520409431f28a1962f41e3 | 0.598687 | 3.426506 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_13/lab13_3/lab13_3.vhd | 1 | 966 | library ieee;
use ieee.std_logic_1164.all;
entity JK_FF is
PORT ( K: in std_logic;
J: in std_logic;
CLK: in std_logic;
CLR: in std_logic;
PRE: in std_logic;
QN: out std_logic;
Q: out std_logic);
end JK_FF;
Architecture Arch_JK_FF of JK_FF is
begin
FF:process(CLK,PRE,CLR)
variable x:std_logic;
begin
if (CLR='0') then
x:='0';
else
if (PRE='0') then
x:='1';
else
if (CLK='1') and CLK'EVENT then
if (J='0' and K='0') then
x:= x;
elsif (J='1' and K='1') then
x:= not x;
elsif (J='0' and K='1') then
x:= '0';
else
x:='1';
end if;
end if;
end if;
end if;
Q<=x;
QN<= not x;
end process FF;
end Arch_JK_FF; | gpl-2.0 | 948ea9bec7f5d13733937e6f231ea15e | 0.39234 | 3.437722 | false | false | false | false |
UnofficialRepos/OSVVM | ScoreboardPkg_int_c.vhd | 1 | 137,764 | --
-- File Name: ScoreBoardPkg_int.vhd
-- Design Unit Name: ScoreBoardPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Removed deprecated SetAlertLogID in Singleton API
-- 02/2022 2022.02 Added WriteScoreboardYaml and GotScoreboards. Updated NewID with ParentID,
-- ReportMode, Search, PrintParent. Supports searching for Scoreboard models..
-- 01/2022 2022.01 Added CheckExpected. Added SetCheckCountZero to ScoreboardPType
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 10/2020 2020.10 Added Peek
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 11/2016 2016.11 Released as part of OSVVM
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2010 2010.08 Added Tailpointer
-- 12/2006 2006.12 Initial revision
--
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package ScoreBoardPkg_int is
-- generic (
-- type ExpectedType ;
-- type ActualType ;
-- function Match(Actual : ActualType ; -- defaults
-- Expected : ExpectedType) return boolean ; -- is "=" ;
-- function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
-- function actual_to_string (A : ActualType) return string -- is to_string ;
-- ) ;
--
-- For a VHDL-2002 package, comment out the generics and
-- uncomment the following, it replaces a generic instance of the package.
-- As a result, you will have multiple copies of the entire package.
-- Inconvenient, but ok as it still works the same.
subtype ExpectedType is integer ;
subtype ActualType is integer ;
alias Match is "=" [ActualType, ExpectedType return boolean] ; -- for std_logic_vector
alias expected_to_string is to_string [ExpectedType return string]; -- VHDL-2008
alias actual_to_string is to_string [ActualType return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreboardIdType is record
Id : integer_max ;
end record ScoreboardIdType ;
type ScoreboardIdArrayType is array (integer range <>) of ScoreboardIdType ;
type ScoreboardIdMatrixType is array (integer range <>, integer range <>) of ScoreboardIdType ;
-- Preparation for refactoring - if that ever happens.
subtype FifoIdType is ScoreboardIdType ;
subtype FifoIdArrayType is ScoreboardIdArrayType ;
subtype FifoIdMatrixType is ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) ; -- Deletes all allocated items
procedure Initialize (
constant ID : in ScoreboardIDType
) ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType ;
type ScoreBoardPType is protected
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-------------------------------
-- Array of Tagged Scoreboards
impure function CheckExpected (
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
-- ReportMode := ENABLED when not DoNotReport else DISABLED ;
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
-- Clear check counter. Caution does not change AffirmationCounters
procedure SetCheckCountZero ; -- Simple, with or without tags
procedure SetCheckCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
------------------------------------------------------------
------------------------------------------------------------
-- -- Deprecated Interface to NewID
-- impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- -- Vector: 1 to Size
-- impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Vector: X(X'Left) to X(X'Right)
-- impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Matrix: 1 to X, 1 to Y
-- impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
-- impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end protected ScoreBoardPType ;
------------------------------------------------------------
-- Deprecated Interface to NewID
impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- Vector: 1 to Size
impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end ScoreBoardPkg_int ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreBoardPkg_int is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
--!! Replace the following with
-- type ScoreboardRecType is record
-- HeadPointer : ListPointerType ;
-- TailPointer : ListPointerType ;
-- PopListPointer : ListPointerType ;
--
-- ErrCnt : integer ;
-- DropCount : integer ;
-- ItemNumber : integer ;
-- PopCount : integer ;
-- CheckCount : integer ;
-- AlertLogID : AlertLogIDType ;
-- Name : NameStoreIDType ;
-- ReportMode : ScoreboardReportType ;
-- end record ScoreboardRecType ;
--
-- type ScoreboardRecArrayType is array (integer range <>) of ScoreboardRecType ;
-- type ScoreboardRecArrayPointerType is access ScoreboardRecArrayType ;
-- variable ScoreboardPointer : ScoreboardRecArrayPointerType ;
--
-- -- Alas unfortunately aliases don't word as follows:
-- -- alias HeadPointer(I) is ScoreboardPointer(I).HeadPointer ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
-- Original Code
-- variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
--
-- Legal, but crashes simulator more thoroughly
-- variable HeadPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- Working work around for QS 2020.04 and 2021.02
variable Template : ListArrayType(1 to 1) ; -- Work around for QS 2020.04 and 2021.02
variable HeadPointer : ListArrayPointerType := new ListArrayType'(Template) ;
variable TailPointer : ListArrayPointerType := new ListArrayType'(Template) ;
-- PopListPointer needed for Pop to be a function - alternately need 2019 features
variable PopListPointer : ListArrayPointerType := new ListArrayType'(Template) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
variable PrintIndexVar : boolean := TRUE ;
variable CalledNewID : boolean := FALSE ;
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Used by ScoreboardStore
variable NumItems : integer := 0 ;
constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
-- constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
procedure SetPrintIndex (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
PrintIndexVar := Enable ;
end procedure SetPrintIndex ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
constant MinNumItems : in integer
) is
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if NewNumItems > HeadPointer'length then
SetArrayIndex(1, NormalizeArraySize(NewNumItems, MinNumItems)) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- Local/Private to package
impure function LocalNewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable NameID : integer ;
begin
NameID := LocalNameStore.find(Name, ParentID, Search) ;
-- Share the scoreboards if they match
if NameID /= ID_NOT_FOUND.ID then
return ScoreboardIDType'(ID => NameID) ;
else
-- Resize Data Structure as necessary
GrowNumberItems(NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
AlertLogIDVar(NumItems) := NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, Search) ;
AlertIfNotEqual(AlertLogIDVar(NumItems), NameID, NumItems, "ScoreboardPkg: Index of LocalNameStore /= ScoreboardID") ;
return ScoreboardIDType'(ID => NumItems) ;
end if ;
end function LocalNewID ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
return LocalNewID(Name, ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector. Assumes valid range (done by NewID)
impure function LocalNewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
variable Result : ScoreboardIDArrayType(X(X'left) to X(X'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in Result'range loop
Result(i) := LocalNewID(Name & "(" & to_string(i) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1, Size) , ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Array parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Array parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
return LocalNewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix. Assumes valid indices (done by NewID)
impure function LocalNewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable Result : ScoreboardIdMatrixType(X(X'left) to X(X'right), Y(Y'left) to Y(Y'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ;
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in X(X'left) to X(X'right) loop
for j in Y(Y'left) to Y(Y'right) loop
Result(i, j) := LocalNewID(Name & "(" & to_string(i) & ", " & to_string(j) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1,X), (1,Y), ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Matrix parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, Y'length /= 2, "ScoreboardPkg.NewID Matrix parameter Y has " & to_string(Y'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Matrix parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
AlertIf(ParentID, Y(Y'Left) > Y(Y'right), "ScoreboardPkg.NewID Matrix parameter Y(Y'left): " & to_string(Y'Left) & " must be <= Y(Y'right): " & to_string(Y(Y'right)), FAILURE) ;
return LocalNewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
NumItems := 0 ;
CalledNewID := FALSE ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(Index) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(FirstIndexVar) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean ;
constant ExpectedInFIFO : in boolean := TRUE
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 and PrintIndexVar then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
if ExpectedInFIFO then
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
else
write(WriteBuf, " Received: " & expected_to_string(ExpectedPtr.all)) ;
if FoundError then
write(WriteBuf, " Expected: " & actual_to_string(ActualData)) ;
end if ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Scoreboard Store. Index. Tag.
impure function CheckExpected (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ExpectedData, FoundError, ExpectedInFIFO => FALSE) ;
return not FoundError ;
end function CheckExpected ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero (Index : integer) is
------------------------------------------------------------
begin
CheckCountVar(Index) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero is
------------------------------------------------------------
begin
CheckCountVar(FirstIndexVar) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
impure function GotScoreboards return boolean is
------------------------------------------------------------
begin
return CalledNewID ;
end function GotScoreboards ;
------------------------------------------------------------
-- pt local
procedure WriteScoreboardYaml (Index : integer; file CovYamlFile : text) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
write(buf, NAME_PREFIX & "- Name: " & '"' & string'(GetAlertLogName(AlertLogIDVar(Index))) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemCount: " & '"' & to_string(ItemNumberVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ErrorCount: " & '"' & to_string(ErrCntVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsChecked: " & '"' & to_string(CheckCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsPopped: " & '"' & to_string(PopCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsDropped: " & '"' & to_string(DropCountVar(Index)) & '"' & LF) ;
writeline(CovYamlFile, buf) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_sb.yml", FileName) ;
file SbYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
if AlertLogIDVar = NULL or AlertLogIDVar'length <= 0 then
Alert("Scoreboard.WriteScoreboardYaml: no scoreboards defined ", ERROR) ;
return ;
end if ;
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "TestCase: " & '"' & GetAlertLogName & '"' & LF) ;
swrite(buf, "Scoreboards: ") ;
writeline(SbYamlFile, buf) ;
if CalledNewID then
-- Used by singleton
for i in 1 to NumItems loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
else
-- Used by PT method, but not singleton
for i in AlertLogIDVar'range loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
end if ;
file_close(SbYamlFile) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: 1 to Size
--!! impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, (1, Size) , ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: X(X'Left) to X(X'Right)
--!! impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: 1 to X, 1 to Y
--!! impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
--!! impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
end protected body ScoreBoardPType ;
shared variable ScoreboardStore : ScoreBoardPType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, Size, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (
------------------------------------------------------------
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Item) ;
end procedure Push ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, ActualData) ;
end procedure Check ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end procedure Check ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, ActualData) ;
end function Check ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end function Check ;
-------------
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end procedure CheckExpected ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end procedure CheckExpected ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end function CheckExpected ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end function CheckExpected ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Item) ;
end procedure Pop ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Tag, Item) ;
end procedure Pop ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID) ;
end function Pop ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID, Tag) ;
end function Pop ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Tag, Item) ;
end procedure Peek ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Item) ;
end procedure Peek ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
-- return ScoreboardStore.Peek(Tag) ;
log("Issues compiling return later");
return ScoreboardStore.Peek(Index => ID.ID, Tag => Tag) ;
end function Peek ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Peek(Index => ID.ID) ;
end function Peek ;
------------------------------------------------------------
-- ScoreboardEmpty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function ScoreboardEmpty ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function ScoreboardEmpty ;
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function Empty ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function Empty ;
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, Name, ParentID, CreateHierarchy, DoNotReport) ;
--!! end procedure SetAlertLogID ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, A) ;
--!! end procedure SetAlertLogID ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType is
begin
return ScoreboardStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetItemCount(ID.ID) ;
end function GetItemCount ;
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPushCount(ID.ID) ;
end function GetPushCount ;
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPopCount(ID.ID) ;
end function GetPopCount ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetFifoCount(ID.ID) ;
end function GetFifoCount ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetCheckCount(ID.ID) ;
end function GetCheckCount ;
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetDropCount(ID.ID) ;
end function GetDropCount ;
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, ActualData) ;
end function Find ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, ItemNumber) ;
end procedure Flush ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Scoreboard YAML Reports
impure function GotScoreboards return boolean is
begin
return ScoreboardStore.GotScoreboards ;
end function GotScoreboards ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
begin
ScoreboardStore.WriteScoreboardYaml(FileName, OpenKind) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Deallocate ;
end procedure Deallocate ;
procedure Initialize (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Initialize ;
end procedure Initialize ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer is
begin
return GetAlertCount(ScoreboardStore.GetAlertLogID(ID.ID)) ;
end function GetErrorCount ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
ScoreboardStore.CheckFinish(ID.ID, FinishCheckCount, FinishEmpty) ;
end procedure CheckFinish ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) is
begin
-- ScoreboardStore.SetReportMode(ID.ID, ReportModeIn) ;
ScoreboardStore.SetReportMode(ReportModeIn) ;
end procedure SetReportMode ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType is
begin
-- return ScoreboardStore.GetReportMode(ID.ID) ;
return ScoreboardStore.GetReportMode ;
end function GetReportMode ;
--==========================================================
--!! Deprecated Subprograms
--==========================================================
------------------------------------------------------------
-- Deprecated interface to NewID
impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, Size, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
end ScoreBoardPkg_int ; | artistic-2.0 | 436a5e0381e48a63735b7916d171f5c8 | 0.535074 | 5.359633 | false | false | false | false |
peteut/nvc | test/lower/arith1.vhd | 1 | 771 | entity arith1 is
end entity;
architecture test of arith1 is
begin
process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
assert 5 mod x = 2;
assert 5 rem x = 2;
assert (-5) rem x = -2;
assert (-5) mod x = 2;
assert x = +x;
wait;
end process;
end architecture;
| gpl-3.0 | 2e39058ef8ea446a9a40f8a465dcd40e | 0.428016 | 3.552995 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/i2s_rx_tx.vhd | 3 | 6,004 | library ieee;
use ieee.std_logic_1164.all;
------------------------------------------------------------------------
-- Module Declaration
------------------------------------------------------------------------
entity i2s_rx_tx is
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
-- Global signals
CLK_I : in std_logic;
RST_I : in std_logic;
-- Control signals
START_TX_I : in std_logic;
START_RX_I : in std_logic;
STOP_RX_I : in std_logic;
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0);
-- Data input from user logic
TX_DATA_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0);
OE_S_O : out std_logic;
-- Data output to user logic
RX_DATA_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0);
WE_S_O : out std_logic;
-- I2S Interface signals
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic
);
end i2s_rx_tx;
architecture Behavioral of i2s_rx_tx is
------------------------------------------------------------------------
-- Signal Declarations
------------------------------------------------------------------------
signal TxEn : std_logic;
signal RxEn : std_logic;
signal LRCLK_int : std_logic;
signal D_S_O_int : std_logic_vector(C_SLOT_WIDTH-1 downto 0);
signal WE_S_O_int : std_logic;
------------------------------------------------------------------------
-- Component Declarations
------------------------------------------------------------------------
component i2s_controller
generic(
C_SLOT_WIDTH : integer := 24; -- Width of one Slot
-- Synthesis parameters
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0 -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
);
port(
CLK_I : in std_logic; -- System clock (100 MHz)
RST_I : in std_logic; -- System reset
BCLK_O : out std_logic; -- Bit Clock
LRCLK_O : out std_logic; -- Frame Clock
SDATA_O : out std_logic; -- Serial Data Output
SDATA_I : in std_logic; -- Serial Data Input
EN_TX_I : in std_logic; -- Enable TX
EN_RX_I : in std_logic; -- Enable RX
OE_S_O : out std_logic; -- Request new Slot Data
WE_S_O : out std_logic; -- Valid Slot Data
D_S_I : in std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data in
D_S_O : out std_logic_vector(C_SLOT_WIDTH-1 downto 0); -- Slot Data out
-- Runtime parameters
DIV_RATE_I : in std_logic_vector(7 downto 0);
LRCLK_RATE_I : in std_logic_vector(7 downto 0)
);
end component;
------------------------------------------------------------------------
-- Module Implementation
------------------------------------------------------------------------
begin
------------------------------------------------------------------------
-- Instantiate the I2S transmitter module
------------------------------------------------------------------------
Inst_I2sRxTx: i2s_controller
generic map(
C_SLOT_WIDTH => C_SLOT_WIDTH,
C_MSB_POS => C_MSB_POS,
C_FRM_SYNC => C_FRM_SYNC,
C_LRCLK_POL => C_LRCLK_POL,
C_BCLK_POL => C_BCLK_POL
)
port map(
CLK_I => CLK_I,
RST_I => RST_I,
EN_TX_I => TxEn,
EN_RX_I => RxEn,
OE_S_O => OE_S_O,
WE_S_O => WE_S_O_int,
D_S_I => TX_DATA_I,
D_S_O => D_S_O_int,
BCLK_O => BCLK_O,
LRCLK_O => LRCLK_int,
SDATA_O => SDATA_O,
SDATA_I => SDATA_I,
DIV_RATE_I => DIV_RATE_I,
LRCLK_RATE_I => LRCLK_RATE_I
);
LRCLK_O <= LRCLK_int;
TxEn <= START_TX_I;
------------------------------------------------------------------------
-- Assert receive enable
------------------------------------------------------------------------
RXEN_PROC: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if (START_RX_I = '1') then
RxEn <= '1';
elsif (STOP_RX_I = '1') then
RxEn <= '0';
end if;
end if;
end process RXEN_PROC;
------------------------------------------------------------------------
-- Select RX Data
------------------------------------------------------------------------
RX_DATA_SEL: process(CLK_I)
begin
if(CLK_I'event and CLK_I = '1') then
if(WE_S_O_int = '1') then
RX_DATA_O <= D_S_O_int;
end if;
end if;
end process RX_DATA_SEL;
WE_S_O <= WE_S_O_int;
end Behavioral;
| mit | f367d8c04b5529bc0d24b43e131aaa63 | 0.39507 | 3.829082 | false | false | false | false |
UnofficialRepos/OSVVM | NamePkg.vhd | 1 | 4,579 | --
-- File Name: NamePkg.vhd
-- Design Unit Name: NamePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for name.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Added NameLength method to NamePType
-- 01/2020 2020.01 Updated Licenses to Apache
-- 05/2015 2015.06 Added input to Get to return when not initialized
-- 12/2014: 2014.07a Removed initialized pointers which can lead to memory leaks.
-- 07/2014: 2014.07 Moved specialization required by CoveragePkg to CoveragePkg
-- Separated name handling from message handling to simplify naming
-- 06/2010: 0.1 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2010 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
package NamePkg is
type NamePType is protected
procedure Set (NameIn : String) ;
impure function Get (DefaultName : string := "") return string ;
impure function GetOpt return string ;
impure function IsSet return boolean ;
impure function NameLength return integer ;
procedure Clear ; -- clear name
procedure Deallocate ; -- effectively alias to clear name
end protected NamePType ;
end package NamePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body NamePkg is
type NamePType is protected body
variable NamePtr : line ;
------------------------------------------------------------
procedure Set (NameIn : String) is
------------------------------------------------------------
begin
deallocate(NamePtr) ;
NamePtr := new string'(NameIn) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return DefaultName ;
else
return NamePtr.all ;
end if ;
end function Get ;
------------------------------------------------------------
impure function GetOpt return string is
------------------------------------------------------------
begin
if NamePtr = NULL then
return NUL & "" ;
else
return NamePtr.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet return boolean is
------------------------------------------------------------
begin
return NamePtr /= NULL ;
end function IsSet ;
------------------------------------------------------------
impure function NameLength return integer is
------------------------------------------------------------
begin
if NamePtr = NULL then
return 0 ;
else
return NamePtr.all'length ;
end if ;
end function NameLength ;
------------------------------------------------------------
procedure Clear is -- clear name
------------------------------------------------------------
begin
deallocate(NamePtr) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate is -- clear name
------------------------------------------------------------
begin
Clear ;
end procedure Deallocate ;
end protected body NamePType ;
end package body NamePkg ; | artistic-2.0 | 51a08f5a1c58102f1ca69b0bbe8b5c43 | 0.480236 | 5.438242 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/or_component.vhd | 1 | 1,310 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 06-04-2017
-- Package Name: alu_component
-- Module Name: OR_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity OR_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end entity;
architecture OR_COMPONENT_ARCH of OR_COMPONENT is
begin
OUTPUT(0) <= INPUT1(0) or INPUT2(0);
OUTPUT(1) <= INPUT1(1) or INPUT2(1);
OUTPUT(2) <= INPUT1(2) or INPUT2(2);
OUTPUT(3) <= INPUT1(3) or INPUT2(3);
OUTPUT(4) <= INPUT1(4) or INPUT2(4);
OUTPUT(5) <= INPUT1(5) or INPUT2(5);
OUTPUT(6) <= INPUT1(6) or INPUT2(6);
OUTPUT(7) <= INPUT1(7) or INPUT2(7);
OUTPUT(8) <= INPUT1(8) or INPUT2(8);
OUTPUT(9) <= INPUT1(9) or INPUT2(9);
OUTPUT(10) <= INPUT1(10) or INPUT2(10);
OUTPUT(11) <= INPUT1(11) or INPUT2(11);
OUTPUT(12) <= INPUT1(12) or INPUT2(12);
OUTPUT(13) <= INPUT1(13) or INPUT2(13);
OUTPUT(14) <= INPUT1(14) or INPUT2(14);
OUTPUT(15) <= INPUT1(15) or INPUT2(15);
end architecture;
| gpl-3.0 | 230230bb3ab66aac93f3b6db12a64b87 | 0.525954 | 2.904656 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xlconcat_0_0/sim/cpu_xlconcat_0_0.vhd | 1 | 7,830 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY cpu_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END cpu_xlconcat_0_0;
ARCHITECTURE cpu_xlconcat_0_0_arch OF cpu_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT xlconcat;
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 6,
NUM_PORTS => 6
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END cpu_xlconcat_0_0_arch;
| gpl-3.0 | e8d0b363ac788b8dcc145fa470ab24d8 | 0.628736 | 3.367742 | false | false | false | false |
neogeodev/NeoGeoFPGA-sim | CPUs/tg68k_fast.vhd | 1 | 104,552 | ------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the 68000 software compatible Kernal of TG68 --
-- --
-- Copyright (c) 2007-2010 Tobias Gubener <[email protected]> --
-- --
-- This source file is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published --
-- by the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This source file is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- Revision 1.08 2010/06/14
-- Bugfix Movem with regmask==xFFFF
-- Add missing Illegal $4AFC
--
-- Revision 1.07 2009/10/02
-- Bugfix Movem with regmask==x0000
--
-- Revision 1.06 2009/02/10
-- Bugfix shift and rotations opcodes when the bitcount and the data are in the same register:
-- Example lsr.l D2,D2
-- Thanks to Peter Graf for report
--
-- Revision 1.05 2009/01/26
-- Implement missing RTR
-- Thanks to Peter Graf for report
--
-- Revision 1.04 2007/12/29
-- size improvement
-- change signal "microaddr" to one hot state machine
--
-- Revision 1.03 2007/12/21
-- Thanks to Andreas Ehliar
-- Split regfile to use blockram for registers
-- insert "WHEN OTHERS => null;" on END CASE;
--
-- Revision 1.02 2007/12/17
-- Bugfix jsr nn.w
--
-- Revision 1.01 2007/11/28
-- add MOVEP
-- Bugfix Interrupt in MOVEQ
--
-- Revision 1.0 2007/11/05
-- Clean up code and first release
--
-- known bugs/todo:
-- Add CHK INSTRUCTION
-- full decode ILLEGAL INSTRUCTIONS
-- Add FC Output
-- add odd Address test
-- add TRACE
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.ALL;
entity TG68_fast is
port(clk : in std_logic;
reset : in std_logic; --low active
clkena_in : in std_logic:='1';
data_in : in std_logic_vector(15 downto 0);
IPL : in std_logic_vector(2 downto 0):="111";
test_IPL : in std_logic:='0'; --only for debugging
address : out std_logic_vector(31 downto 0);
data_write : out std_logic_vector(15 downto 0);
state_out : out std_logic_vector(1 downto 0);
LDS, UDS : out std_logic;
decodeOPC : buffer std_logic;
wr : out std_logic;
REG_D6 : out std_logic_vector(15 downto 0) --NeoGeo
);
end TG68_fast;
architecture logic of TG68_fast is
signal state : std_logic_vector(1 downto 0);
signal clkena : std_logic;
signal TG68_PC : std_logic_vector(31 downto 0);
signal TG68_PC_add : std_logic_vector(31 downto 0);
signal memaddr : std_logic_vector(31 downto 0);
signal memaddr_in : std_logic_vector(31 downto 0);
signal ea_data : std_logic_vector(31 downto 0);
signal ea_data_OP1 : std_logic;
signal setaddrlong : std_logic;
signal OP1out, OP2out : std_logic_vector(31 downto 0);
signal OP1outbrief : std_logic_vector(15 downto 0);
signal OP1in : std_logic_vector(31 downto 0);
signal data_write_tmp : std_logic_vector(31 downto 0);
signal Xtmp : std_logic_vector(31 downto 0);
signal PC_dataa, PC_datab, PC_result : std_logic_vector(31 downto 0);
signal setregstore : std_logic;
signal datatype : std_logic_vector(1 downto 0);
signal longread : std_logic;
signal longreaddirect : std_logic;
signal long_done : std_logic;
signal nextpass : std_logic;
signal setnextpass : std_logic;
signal setdispbyte : std_logic;
signal setdisp : std_logic;
signal setdispbrief : std_logic;
signal regdirectsource : std_logic;
signal endOPC : std_logic;
signal postadd : std_logic;
signal presub : std_logic;
signal addsub_a : std_logic_vector(31 downto 0);
signal addsub_b : std_logic_vector(31 downto 0);
signal addsub_q : std_logic_vector(31 downto 0);
signal briefext : std_logic_vector(31 downto 0);
signal setbriefext : std_logic;
signal addsub : std_logic;
signal c_in : std_logic_vector(3 downto 0);
signal c_out : std_logic_vector(2 downto 0);
signal add_result : std_logic_vector(33 downto 0);
signal addsub_ofl : std_logic_vector(2 downto 0);
signal flag_z : std_logic_vector(2 downto 0);
signal last_data_read : std_logic_vector(15 downto 0);
signal data_read : std_logic_vector(31 downto 0);
signal registerin : std_logic_vector(31 downto 0);
signal reg_QA : std_logic_vector(31 downto 0);
signal reg_QB : std_logic_vector(31 downto 0);
signal Hwrena,Lwrena : std_logic;
signal Regwrena : std_logic;
signal rf_dest_addr : std_logic_vector(6 downto 0);
signal rf_source_addr : std_logic_vector(6 downto 0);
signal rf_dest_addr_tmp : std_logic_vector(6 downto 0);
signal rf_source_addr_tmp : std_logic_vector(6 downto 0);
signal opcode : std_logic_vector(15 downto 0);
signal laststate : std_logic_vector(1 downto 0);
signal setstate : std_logic_vector(1 downto 0);
signal mem_address : std_logic_vector(31 downto 0);
signal memaddr_a : std_logic_vector(31 downto 0);
signal mem_data_read : std_logic_vector(31 downto 0);
signal mem_data_write : std_logic_vector(31 downto 0);
signal set_mem_rega : std_logic;
signal data_read_ram : std_logic_vector(31 downto 0);
signal data_read_uart : std_logic_vector(7 downto 0);
signal counter_reg : std_logic_vector(31 downto 0);
signal TG68_PC_br8 : std_logic;
signal TG68_PC_brw : std_logic;
signal TG68_PC_nop : std_logic;
signal setgetbrief : std_logic;
signal getbrief : std_logic;
signal brief : std_logic_vector(15 downto 0);
signal dest_areg : std_logic;
signal source_areg : std_logic;
signal data_is_source : std_logic;
signal set_store_in_tmp : std_logic;
signal store_in_tmp : std_logic;
signal write_back : std_logic;
signal setaddsub : std_logic;
signal setstackaddr : std_logic;
signal writePC : std_logic;
signal writePC_add : std_logic;
signal set_TG68_PC_dec: std_logic;
signal TG68_PC_dec : std_logic_vector(1 downto 0);
signal directPC : std_logic;
signal set_directPC : std_logic;
signal execOPC : std_logic;
signal fetchOPC : std_logic;
signal Flags : std_logic_vector(15 downto 0); --T.S..III ...XNZVC
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
signal exec_ADD : std_logic;
signal exec_OR : std_logic;
signal exec_AND : std_logic;
signal exec_EOR : std_logic;
signal exec_MOVE : std_logic;
signal exec_MOVEQ : std_logic;
signal exec_MOVESR : std_logic;
signal exec_DIRECT : std_logic;
signal exec_ADDQ : std_logic;
signal exec_CMP : std_logic;
signal exec_ROT : std_logic;
signal exec_exg : std_logic;
signal exec_swap : std_logic;
signal exec_write_back: std_logic;
signal exec_tas : std_logic;
signal exec_EXT : std_logic;
signal exec_ABCD : std_logic;
signal exec_SBCD : std_logic;
signal exec_MULU : std_logic;
signal exec_DIVU : std_logic;
signal exec_Scc : std_logic;
signal exec_CPMAW : std_logic;
signal set_exec_ADD : std_logic;
signal set_exec_OR : std_logic;
signal set_exec_AND : std_logic;
signal set_exec_EOR : std_logic;
signal set_exec_MOVE : std_logic;
signal set_exec_MOVEQ : std_logic;
signal set_exec_MOVESR: std_logic;
signal set_exec_ADDQ : std_logic;
signal set_exec_CMP : std_logic;
signal set_exec_ROT : std_logic;
signal set_exec_tas : std_logic;
signal set_exec_EXT : std_logic;
signal set_exec_ABCD : std_logic;
signal set_exec_SBCD : std_logic;
signal set_exec_MULU : std_logic;
signal set_exec_DIVU : std_logic;
signal set_exec_Scc : std_logic;
signal set_exec_CPMAW : std_logic;
signal condition : std_logic;
signal OP2out_one : std_logic;
signal OP1out_zero : std_logic;
signal ea_to_pc : std_logic;
signal ea_build : std_logic;
signal ea_only : std_logic;
signal get_ea_now : std_logic;
signal source_lowbits : std_logic;
signal dest_hbits : std_logic;
signal rot_rot : std_logic;
signal rot_lsb : std_logic;
signal rot_msb : std_logic;
signal rot_XC : std_logic;
signal set_rot_nop : std_logic;
signal rot_nop : std_logic;
signal rot_out : std_logic_vector(31 downto 0);
signal rot_bits : std_logic_vector(1 downto 0);
signal rot_cnt : std_logic_vector(5 downto 0);
signal set_rot_cnt : std_logic_vector(5 downto 0);
signal movem_busy : std_logic;
signal set_movem_busy : std_logic;
signal movem_addr : std_logic;
signal movem_regaddr : std_logic_vector(3 downto 0);
signal movem_mask : std_logic_vector(15 downto 0);
signal set_get_movem_mask : std_logic;
signal get_movem_mask : std_logic;
signal maskzero : std_logic;
signal test_maskzero : std_logic;
signal movem_muxa : std_logic_vector(7 downto 0);
signal movem_muxb : std_logic_vector(3 downto 0);
signal movem_muxc : std_logic_vector(1 downto 0);
signal movem_presub : std_logic;
signal save_memaddr : std_logic;
signal movem_bits : std_logic_vector(4 downto 0);
signal ea_calc_b : std_logic_vector(31 downto 0);
signal set_mem_addsub : std_logic;
signal bit_bits : std_logic_vector(1 downto 0);
signal bit_number_reg : std_logic_vector(4 downto 0);
signal bit_number : std_logic_vector(4 downto 0);
signal exec_Bits : std_logic;
signal bits_out : std_logic_vector(31 downto 0);
signal one_bit_in : std_logic;
signal one_bit_out : std_logic;
signal set_get_bitnumber : std_logic;
signal get_bitnumber : std_logic;
signal mem_byte : std_logic;
signal wait_mem_byte : std_logic;
signal movepl : std_logic;
signal movepw : std_logic;
signal set_movepl : std_logic;
signal set_movepw : std_logic;
signal set_direct_data: std_logic;
signal use_direct_data: std_logic;
signal direct_data : std_logic;
signal set_get_extendedOPC : std_logic;
signal get_extendedOPC: std_logic;
signal setstate_delay : std_logic_vector(1 downto 0);
signal setstate_mux : std_logic_vector(1 downto 0);
signal use_XZFlag : std_logic;
signal use_XFlag : std_logic;
signal dummy_a : std_logic_vector(8 downto 0);
signal niba_l : std_logic_vector(5 downto 0);
signal niba_h : std_logic_vector(5 downto 0);
signal niba_lc : std_logic;
signal niba_hc : std_logic;
signal bcda_lc : std_logic;
signal bcda_hc : std_logic;
signal dummy_s : std_logic_vector(8 downto 0);
signal nibs_l : std_logic_vector(5 downto 0);
signal nibs_h : std_logic_vector(5 downto 0);
signal nibs_lc : std_logic;
signal nibs_hc : std_logic;
signal dummy_mulu : std_logic_vector(31 downto 0);
signal dummy_div : std_logic_vector(31 downto 0);
signal dummy_div_sub : std_logic_vector(16 downto 0);
signal dummy_div_over : std_logic_vector(16 downto 0);
signal set_V_Flag : std_logic;
signal OP1sign : std_logic;
signal set_sign : std_logic;
signal sign : std_logic;
signal sign2 : std_logic;
signal muls_msb : std_logic;
signal mulu_reg : std_logic_vector(31 downto 0);
signal div_reg : std_logic_vector(31 downto 0);
signal div_sign : std_logic;
signal div_quot : std_logic_vector(31 downto 0);
signal div_ovl : std_logic;
signal pre_V_Flag : std_logic;
signal set_vectoraddr : std_logic;
signal writeSR : std_logic;
signal trap_illegal : std_logic;
signal trap_priv : std_logic;
signal trap_1010 : std_logic;
signal trap_1111 : std_logic;
signal trap_trap : std_logic;
signal trap_trapv : std_logic;
signal trap_interrupt : std_logic;
signal trapmake : std_logic;
signal trapd : std_logic;
-- signal trap_PC : std_logic_vector(31 downto 0);
signal trap_SR : std_logic_vector(15 downto 0);
signal set_directSR : std_logic;
signal directSR : std_logic;
signal set_directCCR : std_logic;
signal directCCR : std_logic;
signal set_stop : std_logic;
signal stop : std_logic;
signal trap_vector : std_logic_vector(31 downto 0);
signal to_USP : std_logic;
signal from_USP : std_logic;
signal to_SR : std_logic;
signal from_SR : std_logic;
signal illegal_write_mode : std_logic;
signal illegal_read_mode : std_logic;
signal illegal_byteaddr : std_logic;
signal use_SP : std_logic;
signal no_Flags : std_logic;
signal IPL_nr : std_logic_vector(2 downto 0);
signal rIPL_nr : std_logic_vector(2 downto 0);
signal interrupt : std_logic;
signal SVmode : std_logic;
signal trap_chk : std_logic;
signal test_delay : std_logic_vector(2 downto 0);
signal set_PCmarker : std_logic;
signal PCmarker : std_logic;
signal set_Z_error : std_logic;
signal Z_error : std_logic;
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_dAn2, ld_AnXn1, ld_AnXn2, ld_AnXn3, st_dAn1, st_dAn2,
st_AnXn1, st_AnXn2, st_AnXn3, bra1, bra2, bsr1, bsr2, dbcc1, dbcc2,
movem, andi, op_AxAy, cmpm, link, int1, int2, int3, int4, rte, trap1, trap2, trap3,
movep1, movep2, movep3, movep4, movep5, init1, init2,
mul1, mul2, mul3, mul4, mul5, mul6, mul7, mul8, mul9, mul10, mul11, mul12, mul13, mul14, mul15,
div1, div2, div3, div4, div5, div6, div7, div8, div9, div10, div11, div12, div13, div14, div15 );
signal micro_state : micro_states;
signal next_micro_state : micro_states;
type regfile_t is array(0 to 16) of std_logic_vector(15 downto 0);
signal regfile_low : regfile_t := (others => (others=>'0'));
signal regfile_high : regfile_t := (others => (others=>'0'));
signal RWindex_A : integer range 0 to 16;
signal RWindex_B : integer range 0 to 16;
BEGIN
-----------------------------------------------------------------------------
-- Registerfile
-----------------------------------------------------------------------------
RWindex_A <= conv_integer(rf_dest_addr(4)&(rf_dest_addr(3 downto 0) XOR "1111"));
RWindex_B <= conv_integer(rf_source_addr(4)&(rf_source_addr(3 downto 0) XOR "1111"));
PROCESS (clk)
BEGIN
IF falling_edge(clk) THEN
IF clkena='1' THEN
reg_QA <= regfile_high(RWindex_A) & regfile_low(RWindex_A);
reg_QB <= regfile_high(RWindex_B) & regfile_low(RWindex_B);
END IF;
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF Lwrena='1' THEN
regfile_low(RWindex_A) <= registerin(15 downto 0);
-- NeoGeo
IF (RWindex_A=9) THEN -- 6 ^ F = 9
REG_D6 <= registerin(15 downto 0);
END IF;
END IF;
IF Hwrena='1' THEN
regfile_high(RWindex_A) <= registerin(31 downto 16);
END IF;
END IF;
END IF;
END PROCESS;
address <= TG68_PC when state="00" else X"ffffffff" when state="01" else memaddr;
LDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='1') AND state/="01" ELSE '1';
UDS <= '0' WHEN (datatype/="00" OR state="00" OR memaddr(0)='0') AND state/="01" ELSE '1';
state_out <= state;
wr <= '0' WHEN state="11" ELSE '1';
IPL_nr <= NOT IPL;
-----------------------------------------------------------------------------
-- "ALU"
-----------------------------------------------------------------------------
PROCESS (addsub_a, addsub_b, addsub, add_result, c_in)
BEGIN
IF addsub='1' THEN --ADD
add_result <= (('0'&addsub_a&c_in(0))+('0'&addsub_b&c_in(0)));
ELSE --SUB
add_result <= (('0'&addsub_a&'0')-('0'&addsub_b&c_in(0)));
END IF;
addsub_q <= add_result(32 downto 1);
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
c_in(3) <= add_result(33);
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
c_out <= c_in(3 downto 1);
END PROCESS;
-----------------------------------------------------------------------------
-- MEM_IO
-----------------------------------------------------------------------------
PROCESS (clk, reset, clkena_in, opcode, rIPL_nr, longread, get_extendedOPC, memaddr, memaddr_a, set_mem_addsub, movem_presub,
movem_busy, state, PCmarker, execOPC, datatype, setdisp, setdispbrief, briefext, setdispbyte, brief,
set_mem_rega, reg_QA, setaddrlong, data_read, decodeOPC, TG68_PC, data_in, long_done, last_data_read, mem_byte,
data_write_tmp, addsub_q, set_vectoraddr, trap_vector, interrupt)
BEGIN
clkena <= clkena_in AND NOT longread AND NOT get_extendedOPC;
IF rising_edge(clk) THEN
IF clkena='1' THEN
trap_vector(31 downto 8) <= (others => '0');
-- IF trap_addr_fault='1' THEN
-- trap_vector(7 downto 0) <= X"08";
-- END IF;
-- IF trap_addr_error='1' THEN
-- trap_vector(7 downto 0) <= X"0C";
-- END IF;
IF trap_illegal='1' THEN
trap_vector(7 downto 0) <= X"10";
END IF;
IF z_error='1' THEN
trap_vector(7 downto 0) <= X"14";
END IF;
-- IF trap_chk='1' THEN
-- trap_vector(7 downto 0) <= X"18";
-- END IF;
IF trap_trapv='1' THEN
trap_vector(7 downto 0) <= X"1C";
END IF;
IF trap_priv='1' THEN
trap_vector(7 downto 0) <= X"20";
END IF;
-- IF trap_trace='1' THEN
-- trap_vector(7 downto 0) <= X"24";
-- END IF;
IF trap_1010='1' THEN
trap_vector(7 downto 0) <= X"28";
END IF;
IF trap_1111='1' THEN
trap_vector(7 downto 0) <= X"2C";
END IF;
IF trap_trap='1' THEN
trap_vector(7 downto 2) <= "10"&opcode(3 downto 0);
END IF;
IF interrupt='1' THEN
trap_vector(7 downto 2) <= "011"&rIPL_nr;
END IF;
END IF;
END IF;
memaddr_a(3 downto 0) <= "0000";
memaddr_a(7 downto 4) <= (OTHERS=>memaddr_a(3));
memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
memaddr_a(31 downto 16) <= (OTHERS=>memaddr_a(15));
IF movem_presub='1' THEN
IF movem_busy='1' OR longread='1' THEN
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF state(1)='1' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr_a(1) <= '1';
ELSIF execOPC='1' THEN
IF datatype="10" THEN
memaddr_a(3 downto 0) <= "1100";
ELSE
memaddr_a(3 downto 0) <= "1110";
END IF;
ELSIF setdisp='1' THEN
IF setdispbrief='1' THEN
memaddr_a <= briefext;
ELSIF setdispbyte='1' THEN
memaddr_a(7 downto 0) <= brief(7 downto 0);
ELSE
memaddr_a(15 downto 0) <= brief;
END IF;
END IF;
memaddr_in <= memaddr+memaddr_a;
IF longread='0' THEN
IF set_mem_addsub='1' THEN
memaddr_in <= addsub_q;
ELSIF set_vectoraddr='1' THEN
memaddr_in <= trap_vector;
ELSIF interrupt='1' THEN
memaddr_in <= "1111111111111111111111111111"&rIPL_nr&'0';
ELSIF set_mem_rega='1' THEN
memaddr_in <= reg_QA;
ELSIF setaddrlong='1' AND longread='0' THEN
memaddr_in <= data_read;
ELSIF decodeOPC='1' THEN
memaddr_in <= TG68_PC;
END IF;
END IF;
data_read(15 downto 0) <= data_in;
data_read(31 downto 16) <= (OTHERS=>data_in(15));
IF long_done='1' THEN
data_read(31 downto 16) <= last_data_read;
END IF;
IF mem_byte='1' AND memaddr(0)='0' THEN
data_read(7 downto 0) <= data_in(15 downto 8);
END IF;
IF longread='1' THEN
data_write <= data_write_tmp(31 downto 16);
ELSE
data_write(7 downto 0) <= data_write_tmp(7 downto 0);
IF mem_byte='1' THEN
data_write(15 downto 8) <= data_write_tmp(7 downto 0);
ELSE
data_write(15 downto 8) <= data_write_tmp(15 downto 8);
IF datatype="00" THEN
data_write(7 downto 0) <= data_write_tmp(15 downto 8);
END IF;
END IF;
END IF;
IF reset='0' THEN
longread <= '0';
long_done <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
last_data_read <= data_in;
long_done <= longread;
IF get_extendedOPC='0' OR (get_extendedOPC='1' AND PCmarker='1') THEN
memaddr <= memaddr_in;
END IF;
IF get_extendedOPC='0' THEN
IF ((setstate_mux(1)='1' AND datatype="10") OR longreaddirect='1') AND longread='0' AND interrupt='0' THEN
longread <= '1';
ELSE
longread <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- brief
-----------------------------------------------------------------------------
process (clk, brief, OP1out)
begin
IF brief(11)='1' THEN
OP1outbrief <= OP1out(31 downto 16);
ELSE
OP1outbrief <= (OTHERS=>OP1out(15));
END IF;
IF rising_edge(clk) THEN
IF clkena='1' THEN
briefext <= OP1outbrief&OP1out(15 downto 0);
-- CASE brief(10 downto 9) IS
-- WHEN "00" => briefext <= OP1outbrief&OP1out(15 downto 0);
-- WHEN "01" => briefext <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
-- WHEN "10" => briefext <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
-- WHEN "11" => briefext <= OP1outbrief(12 downto 0)&OP1out(15 downto 0)&"000";
-- END CASE;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- PC Calc + fetch opcode
-----------------------------------------------------------------------------
process (clk, reset, opcode, TG68_PC, TG68_PC_dec, TG68_PC_br8, TG68_PC_brw, PC_dataa, PC_datab, execOPC, last_data_read, get_extendedOPC,
setstate_delay, setstate)
begin
PC_dataa <= TG68_PC;
PC_datab(2 downto 0) <= "010";
PC_datab(7 downto 3) <= (others => PC_datab(2));
PC_datab(15 downto 8) <= (others => PC_datab(7));
PC_datab(31 downto 16) <= (others => PC_datab(15));
IF execOPC='0' THEN
IF TG68_PC_br8='1' THEN
PC_datab(7 downto 0) <= opcode(7 downto 0);
END IF;
IF TG68_PC_dec(1)='1' THEN
PC_datab(2) <= '1';
END IF;
IF TG68_PC_brw = '1' THEN
PC_datab(15 downto 0) <= last_data_read(15 downto 0);
END IF;
END IF;
TG68_PC_add <= PC_dataa+PC_datab;
IF get_extendedOPC='1' THEN
setstate_mux <= setstate_delay;
ELSE
setstate_mux <= setstate;
END IF;
IF reset = '0' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
TG68_PC <= (others =>'0');
state <= "01";
decodeOPC <= '0';
fetchOPC <= '0';
endOPC <= '0';
interrupt <= '0';
trap_interrupt <= '1';
execOPC <= '0';
getbrief <= '0';
TG68_PC_dec <= "00";
directPC <= '0';
directSR <= '0';
directCCR <= '0';
stop <= '0';
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_EXT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
exec_MULU <= '0';
exec_DIVU <= '0';
exec_Scc <= '0';
exec_CPMAW <= '0';
mem_byte <= '0';
rot_cnt <="000001";
rot_nop <= '0';
get_extendedOPC <= '0';
get_bitnumber <= '0';
get_movem_mask <= '0';
test_maskzero <= '0';
movepl <= '0';
movepw <= '0';
test_delay <= "000";
PCmarker <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' THEN
get_extendedOPC <= set_get_extendedOPC;
get_bitnumber <= set_get_bitnumber;
get_movem_mask <= set_get_movem_mask;
test_maskzero <= get_movem_mask;
setstate_delay <= setstate;
TG68_PC_dec <= TG68_PC_dec(0)&set_TG68_PC_dec;
IF directPC='1' AND clkena='1' THEN
TG68_PC <= data_read;
ELSIF ea_to_pc='1' AND longread='0' THEN
TG68_PC <= memaddr_in;
ELSIF (state ="00" AND TG68_PC_nop='0') OR TG68_PC_br8='1' OR TG68_PC_brw='1' OR TG68_PC_dec(1)='1' THEN
TG68_PC <= TG68_PC_add;
END IF;
IF get_bitnumber='1' THEN
bit_number_reg <= data_read(4 downto 0);
END IF;
IF clkena='1' OR get_extendedOPC='1' THEN
IF set_get_extendedOPC='1' THEN
state <= "00";
ELSIF get_extendedOPC='1' THEN
state <= setstate_mux;
ELSIF fetchOPC='1' OR (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR stop='1' THEN
state <= "01"; --decode cycle, execute cycle
ELSE
state <= setstate_mux;
END IF;
IF setstate_mux(1)='1' AND datatype="00" AND set_get_extendedOPC='0' AND wait_mem_byte='0' THEN
mem_byte <= '1';
ELSE
mem_byte <= '0';
END IF;
END IF;
END IF;
IF clkena='1' THEN
exec_ADD <= '0';
exec_OR <= '0';
exec_AND <= '0';
exec_EOR <= '0';
exec_MOVE <= '0';
exec_MOVEQ <= '0';
exec_MOVESR <= '0';
exec_ADDQ <= '0';
exec_CMP <= '0';
exec_ROT <= '0';
exec_ABCD <= '0';
exec_SBCD <= '0';
fetchOPC <= '0';
exec_CPMAW <= '0';
endOPC <= '0';
interrupt <= '0';
execOPC <= '0';
exec_EXT <= '0';
exec_Scc <= '0';
rot_nop <= '0';
decodeOPC <= fetchOPC;
directPC <= set_directPC;
directSR <= set_directSR;
directCCR <= set_directCCR;
exec_MULU <= set_exec_MULU;
exec_DIVU <= set_exec_DIVU;
movepl <= '0';
movepw <= '0';
stop <= set_stop OR (stop AND NOT interrupt);
IF set_PCmarker='1' THEN
PCmarker <= '1';
ELSIF (state="10" AND longread='0') OR (ea_only='1' AND get_ea_now='1') THEN
PCmarker <= '0';
END IF;
IF (decodeOPC OR execOPC)='1' THEN
rot_cnt <= set_rot_cnt;
END IF;
IF next_micro_state=idle AND setstate_mux="00" AND (setnextpass='0' OR ea_only='1') AND endOPC='0' AND movem_busy='0' AND set_movem_busy='0' AND set_get_bitnumber='0' THEN
nextpass <= '0';
IF (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" THEN
endOPC <= '1';
IF Flags(10 downto 8)<IPL_nr OR IPL_nr="111" THEN
interrupt <= '1';
rIPL_nr <= IPL_nr;
ELSE
IF stop='0' THEN
fetchOPC <= '1';
END IF;
END IF;
END IF;
IF exec_write_back='0' OR state/="11" THEN
IF stop='0' THEN
execOPC <= '1';
END IF;
exec_ADD <= set_exec_ADD;
exec_OR <= set_exec_OR;
exec_AND <= set_exec_AND;
exec_EOR <= set_exec_EOR;
exec_MOVE <= set_exec_MOVE;
exec_MOVEQ <= set_exec_MOVEQ;
exec_MOVESR <= set_exec_MOVESR;
exec_ADDQ <= set_exec_ADDQ;
exec_CMP <= set_exec_CMP;
exec_ROT <= set_exec_ROT;
exec_tas <= set_exec_tas;
exec_EXT <= set_exec_EXT;
exec_ABCD <= set_exec_ABCD;
exec_SBCD <= set_exec_SBCD;
exec_Scc <= set_exec_Scc;
exec_CPMAW <= set_exec_CPMAW;
rot_nop <= set_rot_nop;
END IF;
ELSE
IF endOPC='0' AND (setnextpass='1' OR (regdirectsource='1' AND decodeOPC='1')) THEN
nextpass <= '1';
END IF;
END IF;
IF interrupt='1' THEN
opcode(15 downto 12) <= X"7"; --moveq
opcode(8 downto 6) <= "010"; --long
-- trap_PC <= TG68_PC;
trap_interrupt <= '1';
END IF;
IF fetchOPC='1' THEN
trap_interrupt <= '0';
IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' THEN
-- IF (test_IPL='1' AND (Flags(10 downto 8)<IPL_nr OR IPL_nr="111")) OR to_SR='1' OR opcode(15 downto 6)="0100111011" THEN --nur f r Validator
opcode <= X"60FE";
IF to_SR='0' THEN
test_delay <= "001";
END IF;
ELSE
opcode <= data_read(15 downto 0);
END IF;
getbrief <= '0';
-- trap_PC <= TG68_PC;
ELSE
test_delay <= test_delay(1 downto 0)&'0';
getbrief <= setgetbrief;
movepl <= set_movepl;
movepw <= set_movepw;
END IF;
IF decodeOPC='1' OR interrupt='1' THEN
trap_SR <= Flags;
END IF;
IF getbrief='1' THEN
brief <= data_read(15 downto 0);
END IF;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- handle EA_data, data_write_tmp
-----------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset = '0' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
direct_data <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
direct_data <= '0';
IF endOPC='1' THEN
set_store_in_tmp <='0';
exec_DIRECT <= '0';
exec_write_back <= '0';
use_direct_data <= '0';
Z_error <= '0';
ELSE
IF set_Z_error='1' THEN
Z_error <= '1';
END IF;
exec_DIRECT <= set_exec_MOVE;
IF setstate_mux="10" AND write_back='1' THEN
exec_write_back <= '1';
END IF;
END IF;
IF set_direct_data='1' THEN
direct_data <= '1';
use_direct_data <= '1';
END IF;
IF set_exec_MOVE='1' AND state="11" THEN
use_direct_data <= '1';
END IF;
IF (exec_DIRECT='1' AND state="00" AND getbrief='0' AND endOPC='0') OR state="10" THEN
set_store_in_tmp <= '1';
ea_data <= data_read;
END IF;
IF writePC_add='1' THEN
data_write_tmp <= TG68_PC_add;
ELSIF writePC='1' OR fetchOPC='1' OR interrupt='1' OR (trap_trap='1' AND decodeOPC='1') THEN --fetchOPC f r Trap
data_write_tmp <= TG68_PC;
ELSIF execOPC='1' OR (get_ea_now='1' AND ea_only='1') THEN --get_ea_now='1' AND ea_only='1' ist f r pea
data_write_tmp <= registerin(31 downto 8)&(registerin(7)OR exec_tas)®isterin(6 downto 0);
ELSIF (exec_DIRECT='1' AND state="10") OR direct_data='1' THEN
data_write_tmp <= data_read;
IF movepl='1' THEN
data_write_tmp(31 downto 8) <= data_write_tmp(23 downto 0);
END IF;
ELSIF (movem_busy='1' AND datatype="10" AND movem_presub='1') OR movepl='1' THEN
data_write_tmp <= OP2out(15 downto 0)&OP2out(31 downto 16);
ELSIF (NOT trapmake AND decodeOPC)='1' OR movem_busy='1' OR movepw='1' THEN
data_write_tmp <= OP2out;
ELSIF writeSR='1'THEN
data_write_tmp(15 downto 0) <= trap_SR(15 downto 8)& Flags(7 downto 0);
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set dest regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, rf_dest_addr_tmp, to_USP, Flags, trapmake, movem_addr, movem_presub, movem_regaddr, setbriefext, brief, setstackaddr, dest_hbits, dest_areg, data_is_source)
BEGIN
rf_dest_addr <= rf_dest_addr_tmp;
IF rf_dest_addr_tmp(3 downto 0)="1111" AND to_USP='0' THEN
rf_dest_addr(4) <= Flags(13) OR trapmake;
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_dest_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_dest_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF setbriefext='1' THEN
rf_dest_addr_tmp <= ("000"&brief(15 downto 12));
ELSIF setstackaddr='1' THEN
rf_dest_addr_tmp <= "0001111";
ELSIF dest_hbits='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(11 downto 9);
ELSE
IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
rf_dest_addr_tmp <= "000"&dest_areg&opcode(2 downto 0);
ELSE
rf_dest_addr_tmp <= "0001"&opcode(2 downto 0);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP1
-----------------------------------------------------------------------------
PROCESS (reg_QA, OP1out_zero, from_SR, Flags, ea_data_OP1, set_store_in_tmp, ea_data)
BEGIN
OP1out <= reg_QA;
IF OP1out_zero='1' THEN
OP1out <= (OTHERS => '0');
ELSIF from_SR='1' THEN
OP1out(15 downto 0) <= Flags;
ELSIF ea_data_OP1='1' AND set_store_in_tmp='1' THEN
OP1out <= ea_data;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set source regaddr
-----------------------------------------------------------------------------
PROCESS (opcode, Flags, movem_addr, movem_presub, movem_regaddr, source_lowbits, source_areg, from_USP, rf_source_addr_tmp)
BEGIN
rf_source_addr <= rf_source_addr_tmp;
IF rf_source_addr_tmp(3 downto 0)="1111" AND from_USP='0' THEN
rf_source_addr(4) <= Flags(13);
END IF;
IF movem_addr='1' THEN
IF movem_presub='1' THEN
rf_source_addr_tmp <= "000"&(movem_regaddr XOR "1111");
ELSE
rf_source_addr_tmp <= "000"&movem_regaddr;
END IF;
ELSIF from_USP='1' THEN
rf_source_addr_tmp <= "0001111";
ELSIF source_lowbits='1' THEN
rf_source_addr_tmp <= "000"&source_areg&opcode(2 downto 0);
ELSE
rf_source_addr_tmp <= "000"&source_areg&opcode(11 downto 9);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- set OP2
-----------------------------------------------------------------------------
PROCESS (OP2out, reg_QB, opcode, datatype, OP2out_one, exec_EXT, exec_MOVEQ, EXEC_ADDQ, use_direct_data, data_write_tmp,
ea_data_OP1, set_store_in_tmp, ea_data, movepl)
BEGIN
OP2out(15 downto 0) <= reg_QB(15 downto 0);
OP2out(31 downto 16) <= (OTHERS => OP2out(15));
IF OP2out_one='1' THEN
OP2out(15 downto 0) <= "1111111111111111";
ELSIF exec_EXT='1' THEN
IF opcode(6)='0' THEN --ext.w
OP2out(15 downto 8) <= (OTHERS => OP2out(7));
END IF;
ELSIF use_direct_data='1' THEN
OP2out <= data_write_tmp;
ELSIF ea_data_OP1='0' AND set_store_in_tmp='1' THEN
OP2out <= ea_data;
ELSIF exec_MOVEQ='1' THEN
OP2out(7 downto 0) <= opcode(7 downto 0);
OP2out(15 downto 8) <= (OTHERS => opcode(7));
ELSIF exec_ADDQ='1' THEN
OP2out(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
OP2out(3) <='1';
ELSE
OP2out(3) <='0';
END IF;
OP2out(15 downto 4) <= (OTHERS => '0');
ELSIF datatype="10" OR movepl='1' THEN
OP2out(31 downto 16) <= reg_QB(31 downto 16);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- addsub
-----------------------------------------------------------------------------
PROCESS (OP1out, OP2out, presub, postadd, execOPC, OP2out_one, datatype, use_SP, use_XZFlag, use_XFlag, Flags, setaddsub)
BEGIN
addsub_a <= OP1out;
addsub_b <= OP2out;
addsub <= NOT presub;
c_in(0) <='0';
IF execOPC='0' AND OP2out_one='0' THEN
IF datatype="00" AND use_SP='0' THEN
addsub_b <= "00000000000000000000000000000001";
ELSIF datatype="10" AND (presub OR postadd)='1' THEN
addsub_b <= "00000000000000000000000000000100";
ELSE
addsub_b <= "00000000000000000000000000000010";
END IF;
ELSE
IF (use_XZFlag='1' OR use_XFlag='1') AND Flags(4)='1' THEN
c_in(0) <= '1';
END IF;
addsub <= setaddsub;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Write Reg
-----------------------------------------------------------------------------
PROCESS (clkena, OP1in, datatype, presub, postadd, endOPC, regwrena, state, execOPC, last_data_read, movem_addr, rf_dest_addr, reg_QA, maskzero)
BEGIN
Lwrena <= '0';
Hwrena <= '0';
registerin <= OP1in;
IF (presub='1' OR postadd='1') AND endOPC='0' THEN -- -(An)+
Hwrena <= '1';
Lwrena <= '1';
ELSIF Regwrena='1' AND maskzero='0' THEN --read (mem)
Lwrena <= '1';
CASE datatype IS
WHEN "00" => --BYTE
registerin(15 downto 8) <= reg_QA(15 downto 8);
WHEN "01" => --WORD
IF rf_dest_addr(3)='1' OR movem_addr='1' THEN
Hwrena <='1';
END IF;
WHEN OTHERS => --LONG
Hwrena <= '1';
END CASE;
END IF;
END PROCESS;
------------------------------------------------------------------------------
--ALU
------------------------------------------------------------------------------
PROCESS (opcode, OP1in, OP1out, OP2out, datatype, c_out, exec_ABCD, exec_SBCD, exec_CPMAW, exec_MOVESR, bits_out, Flags, flag_z, use_XZFlag, addsub_ofl,
dummy_s, dummy_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, addsub_q, movem_addr, data_read, exec_MULU, exec_DIVU, exec_OR,
exec_AND, exec_Scc, exec_EOR, exec_MOVE, exec_exg, exec_ROT, execOPC, exec_swap, exec_Bits, rot_out, dummy_mulu, dummy_div, save_memaddr, memaddr,
memaddr_in, ea_only, get_ea_now)
BEGIN
--BCD_ARITH-------------------------------------------------------------------
--ADC
dummy_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
--SBC
dummy_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
nibs_lc <= nibs_l(5);
nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
nibs_hc <= nibs_h(5);
------------------------------------------------------------------------------
flag_z <= "000";
OP1in <= addsub_q;
IF movem_addr='1' THEN
OP1in <= data_read;
ELSIF exec_ABCD='1' THEN
OP1in(7 downto 0) <= dummy_a(7 downto 0);
ELSIF exec_SBCD='1' THEN
OP1in(7 downto 0) <= dummy_s(7 downto 0);
ELSIF exec_MULU='1' THEN
OP1in <= dummy_mulu;
ELSIF exec_DIVU='1' AND execOPC='1' THEN
OP1in <= dummy_div;
ELSIF exec_OR='1' THEN
OP1in <= OP2out OR OP1out;
ELSIF exec_AND='1' OR exec_Scc='1' THEN
OP1in <= OP2out AND OP1out;
ELSIF exec_EOR='1' THEN
OP1in <= OP2out XOR OP1out;
ELSIF exec_MOVE='1' OR exec_exg='1' THEN
OP1in <= OP2out;
ELSIF exec_ROT='1' THEN
OP1in <= rot_out;
ELSIF save_memaddr='1' THEN
OP1in <= memaddr;
ELSIF get_ea_now='1' AND ea_only='1' THEN
OP1in <= memaddr_in;
ELSIF exec_swap='1' THEN
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
ELSIF exec_bits='1' THEN
OP1in <= bits_out;
ELSIF exec_MOVESR='1' THEN
OP1in(15 downto 0) <= Flags;
END IF;
IF use_XZFlag='1' AND flags(2)='0' THEN
flag_z <= "000";
ELSIF OP1in(7 downto 0)="00000000" THEN
flag_z(0) <= '1';
IF OP1in(15 downto 8)="00000000" THEN
flag_z(1) <= '1';
IF OP1in(31 downto 16)="0000000000000000" THEN
flag_z(2) <= '1';
END IF;
END IF;
END IF;
-- --Flags NZVC
IF datatype="00" THEN --Byte
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
IF exec_ABCD='1' THEN
set_flags(0) <= dummy_a(8);
ELSIF exec_SBCD='1' THEN
set_flags(0) <= dummy_s(8);
END IF;
ELSIF datatype="10" OR exec_CPMAW='1' THEN --Long
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
ELSE --Word
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
END IF;
END PROCESS;
------------------------------------------------------------------------------
--Flags
------------------------------------------------------------------------------
PROCESS (clk, reset, opcode)
BEGIN
IF reset='0' THEN
Flags(13) <= '1';
SVmode <= '1';
Flags(10 downto 8) <= "111";
ELSIF rising_edge(clk) THEN
IF clkena = '1' THEN
IF directSR='1' THEN
Flags <= data_read(15 downto 0);
END IF;
IF directCCR='1' THEN
Flags(7 downto 0) <= data_read(7 downto 0);
END IF;
IF interrupt='1' THEN
Flags(10 downto 8) <=rIPL_nr;
SVmode <= '1';
END IF;
IF writeSR='1' OR interrupt='1' THEN
Flags(13) <='1';
END IF;
IF endOPC='1' AND to_SR='0' THEN
SVmode <= Flags(13);
END IF;
IF execOPC='1' AND to_SR='1' THEN
Flags(7 downto 0) <= OP1in(7 downto 0); --CCR
IF datatype="01" AND (opcode(14)='0' OR opcode(9)='1') THEN --move to CCR wird als word gespeichert
Flags(15 downto 8) <= OP1in(15 downto 8); --SR
SVmode <= OP1in(13);
END IF;
ELSIF Z_error='1' THEN
IF opcode(8)='0' THEN
Flags(3 downto 0) <= "1000";
ELSE
Flags(3 downto 0) <= "0100";
END IF;
ELSIF no_Flags='0' AND trapmake='0' THEN
IF exec_ADD='1' THEN
Flags(4) <= set_flags(0);
ELSIF exec_ROT='1' AND rot_bits/="11" AND rot_nop='0' THEN
Flags(4) <= rot_XC;
END IF;
IF (exec_ADD OR exec_CMP)='1' THEN
Flags(3 downto 0) <= set_flags;
ELSIF decodeOPC='1' and set_exec_ROT='1' THEN
Flags(1) <= '0';
ELSIF exec_DIVU='1' THEN
IF set_V_Flag='1' THEN
Flags(3 downto 0) <= "1010";
ELSE
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
END IF;
ELSIF exec_OR='1' OR exec_AND='1' OR exec_EOR='1' OR exec_MOVE='1' OR exec_swap='1' OR exec_MULU='1' THEN
Flags(3 downto 0) <= set_flags(3 downto 2)&"00";
ELSIF exec_ROT='1' THEN
Flags(3 downto 2) <= set_flags(3 downto 2);
Flags(0) <= rot_XC;
IF rot_bits="00" THEN --ASL/ASR
Flags(1) <= ((set_flags(3) XOR rot_rot) OR Flags(1));
END IF;
ELSIF exec_bits='1' THEN
Flags(2) <= NOT one_bit_in;
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- execute opcode
-----------------------------------------------------------------------------
PROCESS (clk, reset, OP2out, opcode, fetchOPC, decodeOPC, execOPC, endOPC, nextpass, condition, set_V_flag, trapmake, trapd, interrupt, trap_interrupt, rot_nop,
Z_error, c_in, rot_cnt, one_bit_in, bit_number_reg, bit_number, ea_only, get_ea_now, ea_build, datatype, exec_write_back, get_extendedOPC,
Flags, SVmode, movem_addr, movem_busy, getbrief, set_exec_AND, set_exec_OR, set_exec_EOR, TG68_PC_dec, c_out, OP1out, micro_state)
BEGIN
TG68_PC_br8 <= '0';
TG68_PC_brw <= '0';
TG68_PC_nop <= '0';
setstate <= "00";
Regwrena <= '0';
postadd <= '0';
presub <= '0';
movem_presub <= '0';
setaddsub <= '1';
setaddrlong <= '0';
setnextpass <= '0';
regdirectsource <= '0';
setdisp <= '0';
setdispbyte <= '0';
setdispbrief <= '0';
setbriefext <= '0';
setgetbrief <= '0';
longreaddirect <= '0';
dest_areg <= '0';
source_areg <= '0';
data_is_source <= '0';
write_back <= '0';
setstackaddr <= '0';
writePC <= '0';
writePC_add <= '0';
set_TG68_PC_dec <= '0';
set_directPC <= '0';
set_exec_ADD <= '0';
set_exec_OR <= '0';
set_exec_AND <= '0';
set_exec_EOR <= '0';
set_exec_MOVE <= '0';
set_exec_MOVEQ <= '0';
set_exec_MOVESR <= '0';
set_exec_ADDQ <= '0';
set_exec_CMP <= '0';
set_exec_ROT <= '0';
set_exec_EXT <= '0';
set_exec_CPMAW <= '0';
OP2out_one <= '0';
ea_to_pc <= '0';
ea_build <= '0';
get_ea_now <= '0';
rot_bits <= "XX";
set_rot_nop <= '0';
set_rot_cnt <= "000001";
set_movem_busy <= '0';
set_get_movem_mask <= '0';
save_memaddr <= '0';
set_mem_addsub <= '0';
exec_exg <= '0';
exec_swap <= '0';
exec_Bits <= '0';
set_get_bitnumber <= '0';
dest_hbits <= '0';
source_lowbits <= '0';
set_mem_rega <= '0';
ea_data_OP1 <= '0';
ea_only <= '0';
set_direct_data <= '0';
set_get_extendedOPC <= '0';
set_exec_tas <= '0';
OP1out_zero <= '0';
use_XZFlag <= '0';
use_XFlag <= '0';
set_exec_ABCD <= '0';
set_exec_SBCD <= '0';
set_exec_MULU <= '0';
set_exec_DIVU <= '0';
set_exec_Scc <= '0';
trap_illegal <='0';
trap_priv <='0';
trap_1010 <='0';
trap_1111 <='0';
trap_trap <='0';
trap_trapv <= '0';
trapmake <='0';
set_vectoraddr <='0';
writeSR <= '0';
set_directSR <= '0';
set_directCCR <= '0';
set_stop <= '0';
from_SR <= '0';
to_SR <= '0';
from_USP <= '0';
to_USP <= '0';
illegal_write_mode <= '0';
illegal_read_mode <= '0';
illegal_byteaddr <= '0';
no_Flags <= '0';
set_PCmarker <= '0';
use_SP <= '0';
set_Z_error <= '0';
wait_mem_byte <= '0';
set_movepl <= '0';
set_movepw <= '0';
trap_chk <= '0';
next_micro_state <= idle;
------------------------------------------------------------------------------
--Sourcepass
------------------------------------------------------------------------------
IF ea_only='0' AND get_ea_now='1' THEN
setstate <= "10";
END IF;
IF ea_build='1' THEN
CASE opcode(5 downto 3) IS --source
WHEN "010"|"011"|"100" => -- -(An)+
get_ea_now <='1';
setnextpass <= '1';
IF opcode(4)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(3)='1' THEN --(An)+
postadd <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(5)='1' THEN -- -(An)
presub <= '1';
IF opcode(2 downto 0)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(4 downto 3)/="10" THEN
regwrena <= '1';
END IF;
WHEN "101" => --(d16,An)
next_micro_state <= ld_dAn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <='1';
set_mem_regA <= '1';
WHEN "111" =>
CASE opcode(2 downto 0) IS
WHEN "000" => --(xxxx).w
next_micro_state <= ld_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= ld_nn;
WHEN "010" => --(d16,PC)
next_micro_state <= ld_dAn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "011" => --(d8,PC,Xn)
next_micro_state <= ld_AnXn1;
setgetbrief <= '1';
set_PCmarker <= '1';
WHEN "100" => --#data
setnextpass <= '1';
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
------------------------------------------------------------------------------
--prepere opcode
------------------------------------------------------------------------------
CASE opcode(7 downto 6) IS
WHEN "00" => datatype <= "00"; --Byte
WHEN "01" => datatype <= "01"; --Word
WHEN OTHERS => datatype <= "10"; --Long
END CASE;
IF execOPC='1' AND endOPC='0' AND exec_write_back='1' THEN
setstate <="11";
END IF;
------------------------------------------------------------------------------
--test illegal mode
------------------------------------------------------------------------------
IF (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_write_mode <= '1';
END IF;
IF (opcode(5 downto 2)="1111" AND opcode(1 downto 0)/="00") OR (opcode(5 downto 3)="001" AND datatype="00") THEN
illegal_read_mode <= '1';
END IF;
IF opcode(5 downto 3)="001" AND datatype="00" THEN
illegal_byteaddr <= '1';
END IF;
CASE opcode(15 downto 12) IS
-- 0000 ----------------------------------------------------------------------------
WHEN "0000" =>
IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
datatype <= "00"; --Byte
use_SP <= '1';
no_Flags <='1';
IF opcode(7)='0' THEN
set_exec_move <= '1';
set_movepl <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7)='0' THEN
set_direct_data <= '1';
END IF;
next_micro_state <= movep1;
setgetbrief <='1';
set_mem_regA <= '1';
END IF;
IF opcode(7)='0' AND endOPC='1' THEN
IF opcode(6)='1' THEN
datatype <= "10"; --Long
ELSE
datatype <= "01"; --Word
END IF;
dest_hbits <='1';
regwrena <= '1';
END IF;
ELSE
IF opcode(8)='1' OR opcode(11 downto 8)="1000" THEN --Bits
IF execOPC='1' AND get_extendedOPC='0' THEN
IF opcode(7 downto 6)/="00" AND endOPC='1' THEN
regwrena <= '1';
END IF;
exec_Bits <= '1';
ea_data_OP1 <= '1';
END IF;
-- IF get_extendedOPC='1' THEN
-- datatype <= "01"; --Word
-- ELS
IF opcode(5 downto 4)="00" THEN
datatype <= "10"; --Long
ELSE
datatype <= "00"; --Byte
IF opcode(7 downto 6)/="00" THEN
write_back <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
IF opcode(8)='0' THEN
IF opcode(5 downto 4)/="00" THEN --Dn, An
set_get_extendedOPC <= '1';
END IF;
set_get_bitnumber <= '1';
END IF;
END IF;
ELSE --andi, ...xxxi
IF opcode(11 downto 8)="0000" THEN --ORI
set_exec_OR <= '1';
END IF;
IF opcode(11 downto 8)="0010" THEN --ANDI
set_exec_AND <= '1';
END IF;
IF opcode(11 downto 8)="0100" OR opcode(11 downto 8)="0110" THEN --SUBI, ADDI
set_exec_ADD <= '1';
END IF;
IF opcode(11 downto 8)="1010" THEN --EORI
set_exec_EOR <= '1';
END IF;
IF opcode(11 downto 8)="1100" THEN --CMPI
set_exec_CMP <= '1';
ELSIF trapmake='0' THEN
write_back <= '1';
END IF;
IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec_AND OR set_exec_OR OR set_exec_EOR)='1' THEN --SR
-- IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="1010") THEN --SR
IF SVmode='0' AND opcode(6)='1' THEN --SR
trap_priv <= '1';
trapmake <= '1';
ELSE
from_SR <= '1';
to_SR <= '1';
IF decodeOPC='1' THEN
setnextpass <= '1';
set_direct_data <= '1';
END IF;
END IF;
ELSE
IF decodeOPC='1' THEN
IF opcode(11 downto 8)="0010" OR opcode(11 downto 8)="0000" OR opcode(11 downto 8)="0100" --ANDI, ORI, SUBI
OR opcode(11 downto 8)="0110" OR opcode(11 downto 8)="1010" OR opcode(11 downto 8)="1100" THEN --ADDI, EORI, CMPI
-- IF (set_exec_AND OR set_exec_OR OR set_exec_ADD --ANDI, ORI, SUBI
-- OR set_exec_EOR OR set_exec_CMP)='1' THEN --ADDI, EORI, CMPI
next_micro_state <= andi;
set_direct_data <= '1';
IF datatype="10" THEN
longreaddirect <= '1';
END IF;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF opcode(11 downto 8)/="1100" THEN --CMPI
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
IF opcode(11 downto 8)="1100" OR opcode(11 downto 8)="0100" THEN --CMPI, SUBI
setaddsub <= '0';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 0001, 0010, 0011 -----------------------------------------------------------------
WHEN "0001"|"0010"|"0011" => --move.b, move.l, move.w
set_exec_MOVE <= '1';
IF opcode(8 downto 6)="001" THEN
no_Flags <= '1';
END IF;
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
CASE opcode(13 downto 12) IS
WHEN "01" => datatype <= "00"; --Byte
WHEN "10" => datatype <= "10"; --Long
WHEN OTHERS => datatype <= "01"; --Word
END CASE;
source_lowbits <= '1'; -- Dn=> An=>
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF getbrief='1' AND nextpass='1' THEN -- =>(d16,An) =>(d8,An,Xn)
set_mem_rega <= '1';
END IF;
IF execOPC='1' AND opcode(8 downto 7)="00" THEN
Regwrena <= '1';
END IF;
IF nextpass='1' OR execOPC='1' OR opcode(5 downto 4)="00" THEN
dest_hbits <= '1';
IF opcode(8 downto 6)/="000" THEN
dest_areg <= '1';
END IF;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
CASE opcode(8 downto 6) IS --destination
-- WHEN "000" => --Dn
-- WHEN "001" => --An
WHEN "010"|"011"|"100" => --destination -(an)+
IF opcode(7)='1' THEN
set_mem_rega <= '1';
ELSE
set_mem_addsub <= '1';
END IF;
IF opcode(6)='1' THEN --(An)+
postadd <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(8)='1' THEN -- -(An)
presub <= '1';
IF opcode(11 downto 9)="111" THEN
use_SP <= '1';
END IF;
END IF;
IF opcode(7 downto 6)/="10" THEN
regwrena <= '1';
END IF;
setstate <= "11";
next_micro_state <= nop;
WHEN "101" => --(d16,An)
next_micro_state <= st_dAn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "110" => --(d8,An,Xn)
next_micro_state <= st_AnXn1;
set_mem_regA <= '1';
setgetbrief <= '1';
WHEN "111" =>
CASE opcode(11 downto 9) IS
WHEN "000" => --(xxxx).w
next_micro_state <= st_nn;
WHEN "001" => --(xxxx).l
longreaddirect <= '1';
next_micro_state <= st_nn;
WHEN OTHERS =>
END CASE;
WHEN OTHERS =>
END CASE;
END IF;
-- 0100 ----------------------------------------------------------------------------
WHEN "0100" => --rts_group
IF opcode(8)='1' THEN --lea
IF opcode(6)='1' THEN --lea
IF opcode(7)='1' THEN
ea_only <= '1';
IF opcode(5 downto 3)="010" THEN --lea (Am),An
set_exec_move <='1';
no_Flags <='1';
dest_areg <= '1';
dest_hbits <= '1';
source_lowbits <= '1';
source_areg <= '1';
IF execOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
dest_areg <= '1';
dest_hbits <= '1';
regwrena <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --chk
IF opcode(7)='1' THEN
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
datatype <= "01"; --Word
IF execOPC='1' THEN
setaddsub <= '0';
--first alternative
ea_data_OP1 <= '1';
IF c_out(1)='1' OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- trap_chk <= '1'; --first I must change the Trap System
-- trapmake <= '1';
END IF;
--second alternative
-- IF (c_out(1)='0' AND flag_z(1)='0') OR OP1out(15)='1' OR OP2out(15)='1' THEN
-- -- trap_chk <= '1'; --first I must change the Trap System
-- -- trapmake <= '1';
-- END IF;
-- dest_hbits <= '1';
-- source_lowbits <='1';
END IF;
ELSE
trap_illegal <= '1'; -- chk long for 68020
trapmake <= '1';
END IF;
END IF;
ELSE
CASE opcode(11 downto 9) IS
WHEN "000"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move from SR
set_exec_MOVESR <= '1';
datatype <= "01";
write_back <='1'; -- im 68000 wird auch erst gelesen
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --negx
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "001"=>
IF opcode(7 downto 6)="11" THEN --move from CCR 68010
trap_illegal <= '1';
trapmake <= '1';
ELSE --clr
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_AND <= '1';
IF execOPC='1' THEN
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "010"=>
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --move to CCR
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE --neg
write_back <='1';
set_exec_ADD <= '1';
setaddsub <='0';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "011"=> --not, move toSR
IF opcode(7 downto 6)="11" THEN --move to SR
IF SVmode='1' THEN
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
set_exec_MOVE <= '1';
datatype <= "01";
IF execOPC='1' THEN
source_lowbits <= '1';
to_SR <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
ELSE --not
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
write_back <='1';
set_exec_EOR <= '1';
IF execOPC='1' THEN
OP2out_one <= '1';
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
WHEN "100"|"110"=>
IF opcode(7)='1' THEN --movem, ext
IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN --ext
source_lowbits <= '1';
IF decodeOPC='1' THEN
set_exec_EXT <= '1';
set_exec_move <= '1';
END IF;
IF opcode(6)='0' THEN
datatype <= "01"; --WORD
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE --movem
-- IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN --MOVEM
ea_only <= '1';
IF decodeOPC='1' THEN
datatype <= "01"; --Word
set_get_movem_mask <='1';
set_get_extendedOPC <='1';
IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
set_mem_rega <= '1';
setstate <= "01";
IF opcode(10)='0' THEN
set_movem_busy <='1';
ELSE
next_micro_state <= movem;
END IF;
ELSE
ea_build <= '1';
END IF;
ELSE
IF opcode(6)='0' THEN
datatype <= "01"; --Word
END IF;
END IF;
IF execOPC='1' THEN
IF opcode(5 downto 3)="100" OR opcode(5 downto 3)="011" THEN
regwrena <= '1';
save_memaddr <= '1';
END IF;
END IF;
IF get_ea_now='1' THEN
set_movem_busy <= '1';
IF opcode(10)='0' THEN
setstate <="01";
ELSE
setstate <="10";
END IF;
END IF;
IF opcode(5 downto 3)="100" THEN
movem_presub <= '1';
END IF;
IF movem_addr='1' THEN
IF opcode(10)='1' THEN
regwrena <= '1';
END IF;
END IF;
IF movem_busy='1' THEN
IF opcode(10)='0' THEN
setstate <="11";
ELSE
setstate <="10";
END IF;
END IF;
END IF;
ELSE
IF opcode(10)='1' THEN --MUL, DIV 68020
trap_illegal <= '1';
trapmake <= '1';
ELSE --pea, swap
IF opcode(6)='1' THEN
datatype <= "10";
IF opcode(5 downto 3)="000" THEN --swap
IF execOPC='1' THEN
exec_swap <= '1';
regwrena <= '1';
END IF;
ELSIF opcode(5 downto 3)="001" THEN --bkpt
ELSE --pea
ea_only <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF get_ea_now='1' THEN
setstate <="01";
END IF;
END IF;
ELSE --nbcd
IF decodeOPC='1' THEN --nbcd
ea_build <= '1';
END IF;
use_XFlag <= '1';
write_back <='1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF execOPC='1' THEN
source_lowbits <= '1';
OP1out_zero <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
WHEN "101"=> --tst, tas
IF opcode(7 downto 2)="111111" THEN --4AFC illegal
trap_illegal <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
dest_hbits <= '1'; --for Flags
source_lowbits <= '1';
-- IF opcode(3)='1' THEN --MC68020...
-- source_areg <= '1';
-- END IF;
END IF;
set_exec_MOVE <= '1';
IF opcode(7 downto 6)="11" THEN --tas
set_exec_tas <= '1';
write_back <= '1';
datatype <= "00"; --Byte
IF execOPC='1' AND endOPC='1' THEN
regwrena <= '1';
END IF;
END IF;
END IF;
-- WHEN "110"=>
WHEN "111"=> --4EXX
IF opcode(7)='1' THEN --jsr, jmp
datatype <= "10";
ea_only <= '1';
IF nextpass='1' AND micro_state=idle THEN
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <="11";
next_micro_state <= nop;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF get_ea_now='1' THEN --jsr
IF opcode(6)='0' THEN
setstate <="01";
END IF;
ea_to_pc <= '1';
IF opcode(5 downto 1)="11100" THEN
writePC_add <= '1';
ELSE
writePC <= '1';
END IF;
END IF;
ELSE --
CASE opcode(6 downto 0) IS
WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"| --trap
"1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" => --trap
trap_trap <='1';
trapmake <= '1';
WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111" => --link
datatype <= "10";
IF decodeOPC='1' THEN
next_micro_state <= link;
set_exec_MOVE <= '1'; --f r displacement
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
source_lowbits <= '1';
source_areg <= '1';
END IF;
IF execOPC='1' THEN
setstackaddr <='1';
regwrena <= '1';
END IF;
WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" => --unlink
datatype <= "10";
IF decodeOPC='1' THEN
setstate <= "10";
set_mem_rega <= '1';
ELSIF execOPC='1' THEN
regwrena <= '1';
exec_exg <= '1';
ELSE
setstackaddr <='1';
regwrena <= '1';
get_ea_now <= '1';
ea_only <= '1';
END IF;
WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" => --move An,USP
IF SVmode='1' THEN
no_Flags <= '1';
to_USP <= '1';
setstackaddr <= '1';
source_lowbits <= '1';
source_areg <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" => --move USP,An
IF SVmode='1' THEN
no_Flags <= '1';
from_USP <= '1';
set_exec_MOVE <= '1';
datatype <= "10";
IF execOPC='1' THEN
regwrena <= '1';
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110000" => --reset
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110001" => --nop
WHEN "1110010" => --stop
IF SVmode='0' THEN
trap_priv <= '1';
trapmake <= '1';
ELSE
IF decodeOPC='1' THEN
setnextpass <= '1';
set_directSR <= '1';
set_stop <= '1';
END IF;
END IF;
WHEN "1110011" => --rte
IF SVmode='1' THEN
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directSR <= '1';
next_micro_state <= rte;
END IF;
ELSE
trap_priv <= '1';
trapmake <= '1';
END IF;
WHEN "1110101" => --rts
IF decodeOPC='1' THEN
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
END IF;
WHEN "1110110" => --trapv
IF Flags(1)='1' THEN
trap_trapv <= '1';
trapmake <= '1';
END IF;
WHEN "1110111" => --rtr
IF decodeOPC='1' THEN
datatype <= "01";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directCCR <= '1';
next_micro_state <= rte;
END IF;
WHEN OTHERS =>
trap_illegal <= '1';
trapmake <= '1';
END CASE;
END IF;
WHEN OTHERS => null;
END CASE;
END IF;
-- 0101 ----------------------------------------------------------------------------
WHEN "0101" => --subq, addq
IF opcode(7 downto 6)="11" THEN --dbcc
IF opcode(5 downto 3)="001" THEN --dbcc
datatype <= "01"; --Word
IF decodeOPC='1' THEN
next_micro_state <= nop;
OP2out_one <= '1';
IF condition='0' THEN
Regwrena <= '1';
IF c_in(2)='1' THEN
next_micro_state <= dbcc1;
END IF;
END IF;
data_is_source <= '1';
END IF;
ELSE --Scc
datatype <= "00"; --Byte
write_back <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF condition='0' THEN
set_exec_Scc <= '1';
END IF;
IF execOPC='1' THEN
IF condition='1' THEN
OP2out_one <= '1';
exec_EXG <= '1';
ELSE
OP1out_zero <= '1';
END IF;
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
END IF;
ELSE --addq, subq
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(5 downto 3)="001" THEN
no_Flags <= '1';
END IF;
write_back <= '1';
set_exec_ADDQ <= '1';
set_exec_ADD <= '1';
IF execOPC='1' THEN
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 0110 ----------------------------------------------------------------------------
WHEN "0110" => --bra,bsr,bcc
datatype <= "10";
IF micro_state=idle THEN
IF opcode(11 downto 8)="0001" THEN --bsr
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bsr1;
ELSE
next_micro_state <= bsr2;
setstate <= "01";
END IF;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
ELSE --bra
IF opcode(7 downto 0)="00000000" THEN
next_micro_state <= bra1;
END IF;
IF condition='1' THEN
TG68_PC_br8 <= '1';
END IF;
END IF;
END IF;
-- 0111 ----------------------------------------------------------------------------
WHEN "0111" => --moveq
IF opcode(8)='0' THEN
IF trap_interrupt='0' THEN
datatype <= "10"; --Long
Regwrena <= '1';
set_exec_MOVEQ <= '1';
set_exec_MOVE <= '1';
dest_hbits <= '1';
END IF;
ELSE
trap_illegal <= '1';
trapmake <= '1';
END IF;
-- 1000 ----------------------------------------------------------------------------
WHEN "1000" => --or
IF opcode(7 downto 6)="11" THEN --divu, divs
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' AND z_error='0' AND set_V_Flag='0' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --sbcd, pack , unpack
IF opcode(7 downto 6)="00" THEN --sbcd
use_XZFlag <= '1';
set_exec_ADD <= '1';
set_exec_SBCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --pack, unpack
trap_illegal <= '1';
trapmake <= '1';
END IF;
ELSE --or
set_exec_OR <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1001, 1101 -----------------------------------------------------------------------
WHEN "1001"|"1101" => --sub, add
set_exec_ADD <= '1';
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --adda.w, suba.w
datatype <= "01"; --Word
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(14)='0' THEN
setaddsub <= '0';
END IF;
END IF;
IF opcode(8)='1' AND opcode(5 downto 4)="00" AND opcode(7 downto 6)/="11" THEN --addx, subx
use_XZFlag <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN
write_back <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(7 downto 6)="11" THEN --adda, suba
no_Flags <= '1';
dest_areg <='1';
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
ELSE
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
END IF;
-- 1010 ----------------------------------------------------------------------------
WHEN "1010" => --Trap 1010
trap_1010 <= '1';
trapmake <= '1';
-- 1011 ----------------------------------------------------------------------------
WHEN "1011" => --eor, cmp
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF opcode(8 downto 6)="011" THEN --cmpa.w
datatype <= "01"; --Word
set_exec_CPMAW <= '1';
END IF;
IF opcode(8)='1' AND opcode(5 downto 3)="001" AND opcode(7 downto 6)/="11" THEN --cmpm
set_exec_CMP <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_rega <= '1';
postadd <= '1';
next_micro_state <= cmpm;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
setaddsub <= '0';
END IF;
ELSE --sub, add
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
set_exec_EOR <= '1';
write_back <= '1';
ELSE --cmp
set_exec_CMP <= '1';
END IF;
IF execOPC='1' THEN
IF opcode(8)='1' AND opcode(7 downto 6)/="11" THEN --eor
ea_data_OP1 <= '1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
ELSE --cmp
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
IF opcode(7 downto 6)="11" THEN --cmpa
dest_areg <='1';
END IF;
dest_hbits <= '1';
setaddsub <= '0';
END IF;
END IF;
END IF;
-- 1100 ----------------------------------------------------------------------------
WHEN "1100" => --and, exg
IF opcode(7 downto 6)="11" THEN --mulu, muls
IF opcode(5 downto 4)="00" THEN --Dn, An
regdirectsource <= '1';
END IF;
IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul1;
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
regwrena <= '1';
END IF;
IF (micro_state/=idle AND nextpass='1') OR execOPC='1' THEN
dest_hbits <= '1';
source_lowbits <='1';
ELSE
datatype <= "01";
END IF;
ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN --exg, abcd
IF opcode(7 downto 6)="00" THEN --abcd
use_XZFlag <= '1';
-- datatype <= "00"; --ist schon default
set_exec_ADD <= '1';
set_exec_ABCD <= '1';
IF opcode(3)='1' THEN
write_back <= '1';
IF decodeOPC='1' THEN
set_direct_data <= '1';
setstate <= "10";
set_mem_addsub <= '1';
presub <= '1';
next_micro_state <= op_AxAy;
END IF;
END IF;
IF execOPC='1' THEN
ea_data_OP1 <= '1';
dest_hbits <= '1';
source_lowbits <='1';
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
END IF;
ELSE --exg
datatype <= "10";
regwrena <= '1';
IF opcode(6)='1' AND opcode(3)='1' THEN
dest_areg <= '1';
source_areg <= '1';
END IF;
IF decodeOPC='1' THEN
set_mem_rega <= '1';
exec_exg <= '1';
ELSE
save_memaddr <= '1';
dest_hbits <= '1';
END IF;
END IF;
ELSE --and
set_exec_AND <= '1';
IF opcode(8)='1' THEN
write_back <= '1';
END IF;
IF decodeOPC='1' THEN
ea_build <= '1';
END IF;
IF execOPC='1' THEN
IF endOPC='1' THEN
Regwrena <= '1';
END IF;
IF opcode(8)='1' THEN
ea_data_OP1 <= '1';
ELSE
dest_hbits <= '1';
source_lowbits <='1';
IF opcode(3)='1' THEN
source_areg <= '1';
END IF;
END IF;
END IF;
END IF;
-- 1110 ----------------------------------------------------------------------------
WHEN "1110" => --rotation
set_exec_ROT <= '1';
IF opcode(7 downto 6)="11" THEN
datatype <= "01";
rot_bits <= opcode(10 downto 9);
ea_data_OP1 <= '1';
write_back <= '1';
ELSE
rot_bits <= opcode(4 downto 3);
data_is_source <= '1';
END IF;
IF decodeOPC='1' THEN
IF opcode(7 downto 6)="11" THEN
ea_build <= '1';
ELSE
IF opcode(5)='1' THEN
IF OP2out(5 downto 0)/="000000" THEN
set_rot_cnt <= OP2out(5 downto 0);
ELSE
set_rot_nop <= '1';
END IF;
ELSE
set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
IF opcode(11 downto 9)="000" THEN
set_rot_cnt(3) <='1';
ELSE
set_rot_cnt(3) <='0';
END IF;
END IF;
END IF;
END IF;
IF opcode(7 downto 6)/="11" THEN
IF execOPC='1' AND rot_nop='0' THEN
Regwrena <= '1';
set_rot_cnt <= rot_cnt-1;
END IF;
END IF;
-- ----------------------------------------------------------------------------
WHEN OTHERS =>
trap_1111 <= '1';
trapmake <= '1';
END CASE;
-- END PROCESS;
-----------------------------------------------------------------------------
-- execute microcode
-----------------------------------------------------------------------------
--PROCESS (micro_state)
-- BEGIN
IF Z_error='1' THEN -- divu by zero
trapmake <= '1'; --wichtig f r USP
IF trapd='0' THEN
writePC <= '1';
END IF;
END IF;
IF trapmake='1' AND trapd='0' THEN
next_micro_state <= trap1;
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
END IF;
IF interrupt='1' THEN
next_micro_state <= int1;
setstate <= "10";
-- datatype <= "01"; --wirkt sich auf Flags aus
END IF;
IF reset='0' THEN
micro_state <= init1;
ELSIF rising_edge(clk) THEN
IF clkena='1' THEN
trapd <= trapmake;
IF fetchOPC='1' THEN
micro_state <= idle;
ELSE
micro_state <= next_micro_state;
END IF;
END IF;
END IF;
CASE micro_state IS
WHEN ld_nn => -- (nnnn).w/l=>
get_ea_now <='1';
setnextpass <= '1';
setaddrlong <= '1';
WHEN st_nn => -- =>(nnnn).w/l
setstate <= "11";
setaddrlong <= '1';
next_micro_state <= nop;
WHEN ld_dAn1 => -- d(An)=>, --d(PC)=>
setstate <= "01";
next_micro_state <= ld_dAn2;
WHEN ld_dAn2 => -- d(An)=>, --d(PC)=>
get_ea_now <='1';
setdisp <= '1'; --word
setnextpass <= '1';
WHEN ld_AnXn1 => -- d(An,Xn)=>, --d(PC,Xn)=>
setstate <= "01";
next_micro_state <= ld_AnXn2;
WHEN ld_AnXn2 => -- d(An,Xn)=>, --d(PC,Xn)=>
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= ld_AnXn3;
WHEN ld_AnXn3 =>
get_ea_now <='1';
setdisp <= '1'; --brief
setdispbrief <= '1';
setnextpass <= '1';
WHEN st_dAn1 => -- =>d(An)
setstate <= "01";
next_micro_state <= st_dAn2;
WHEN st_dAn2 => -- =>d(An)
setstate <= "11";
setdisp <= '1'; --word
next_micro_state <= nop;
WHEN st_AnXn1 => -- =>d(An,Xn)
setstate <= "01";
next_micro_state <= st_AnXn2;
WHEN st_AnXn2 => -- =>d(An,Xn)
setdisp <= '1'; --byte
setdispbyte <= '1';
setstate <= "01";
setbriefext <= '1';
next_micro_state <= st_AnXn3;
WHEN st_AnXn3 =>
setstate <= "11";
setdisp <= '1'; --brief
setdispbrief <= '1';
next_micro_state <= nop;
WHEN bra1 => --bra
IF condition='1' THEN
TG68_PC_br8 <= '1'; --pc+0000
setstate <= "01";
next_micro_state <= bra2;
END IF;
WHEN bra2 => --bra
TG68_PC_brw <= '1';
WHEN bsr1 => --bsr
set_TG68_PC_dec <= '1'; --in 2 Takten -2
setstate <= "01";
next_micro_state <= bsr2;
WHEN bsr2 => --bsr
IF TG68_PC_dec(0)='1' THEN
TG68_PC_brw <= '1';
ELSE
TG68_PC_br8 <= '1';
END IF;
writePC <= '1';
setstate <= "11";
next_micro_state <= nop;
WHEN dbcc1 => --dbcc
TG68_PC_nop <= '1';
setstate <= "01";
next_micro_state <= dbcc2;
WHEN dbcc2 => --dbcc
TG68_PC_brw <= '1';
WHEN movem => --movem
set_movem_busy <='1';
setstate <= "10";
WHEN andi => --andi
IF opcode(5 downto 4)/="00" THEN
ea_build <= '1';
setnextpass <= '1';
END IF;
WHEN op_AxAy => -- op -(Ax),-(Ay)
presub <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_addsub <= '1';
setstate <= "10";
WHEN cmpm => -- cmpm (Ay)+,(Ax)+
postadd <= '1';
dest_hbits <= '1';
dest_areg <= '1';
set_mem_rega <= '1';
setstate <= "10";
WHEN link => -- link
setstate <="11";
save_memaddr <= '1';
regwrena <= '1';
WHEN int1 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "10";
next_micro_state <= int2;
WHEN int2 => -- interrupt
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= int3;
WHEN int3 => -- interrupt
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
setstate <= "10";
next_micro_state <= int4;
WHEN int4 => -- interrupt
datatype <= "10";
WHEN rte => -- RTE
datatype <= "10";
setstate <= "10";
postadd <= '1';
setstackaddr <= '1';
set_mem_rega <= '1';
set_directPC <= '1';
next_micro_state <= nop;
WHEN trap1 => -- TRAP
presub <= '1';
setstackaddr <='1';
set_mem_addsub <= '1';
setstate <= "11";
datatype <= "01";
writeSR <= '1';
next_micro_state <= trap2;
WHEN trap2 => -- TRAP
set_vectoraddr <= '1';
datatype <= "10";
set_directPC <= '1';
-- longreaddirect <= '1';
setstate <= "10";
next_micro_state <= trap3;
WHEN trap3 => -- TRAP
datatype <= "10";
WHEN movep1 => -- MOVEP d(An)
setstate <= "01";
IF opcode(6)='1' THEN
set_movepl <= '1';
END IF;
next_micro_state <= movep2;
WHEN movep2 =>
setdisp <= '1';
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
wait_mem_byte <= '1';
END IF;
next_micro_state <= movep3;
WHEN movep3 =>
IF opcode(6)='1' THEN
set_movepw <= '1';
next_micro_state <= movep4;
END IF;
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN movep4 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
wait_mem_byte <= '1';
setstate <= "11";
END IF;
next_micro_state <= movep5;
WHEN movep5 =>
IF opcode(7)='0' THEN
setstate <= "10";
ELSE
setstate <= "11";
END IF;
WHEN init1 => -- init SP
longreaddirect <= '1';
next_micro_state <= init2;
WHEN init2 => -- init PC
get_ea_now <='1'; --\
ea_only <= '1'; --- OP1in <= memaddr_in
setaddrlong <= '1'; -- memaddr_in <= data_read
regwrena <= '1';
setstackaddr <='1'; -- dest_addr <= SP
set_directPC <= '1';
longreaddirect <= '1';
next_micro_state <= nop;
WHEN mul1 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul2;
WHEN mul2 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul3;
WHEN mul3 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul4;
WHEN mul4 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul5;
WHEN mul5 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul6;
WHEN mul6 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul7;
WHEN mul7 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul8;
WHEN mul8 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul9;
WHEN mul9 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul10;
WHEN mul10 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul11;
WHEN mul11 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul12;
WHEN mul12 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul13;
WHEN mul13 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul14;
WHEN mul14 => -- mulu
set_exec_MULU <= '1';
setstate <="01";
next_micro_state <= mul15;
WHEN mul15 => -- mulu
set_exec_MULU <= '1';
WHEN div1 => -- divu
IF OP2out(15 downto 0)=x"0000" THEN --div zero
set_Z_error <= '1';
ELSE
set_exec_DIVU <= '1';
next_micro_state <= div2;
END IF;
setstate <="01";
WHEN div2 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div3;
WHEN div3 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div4;
WHEN div4 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div5;
WHEN div5 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div6;
WHEN div6 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div7;
WHEN div7 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div8;
WHEN div8 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div9;
WHEN div9 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div10;
WHEN div10 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div11;
WHEN div11 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div12;
WHEN div12 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div13;
WHEN div13 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div14;
WHEN div14 => -- divu
set_exec_DIVU <= '1';
setstate <="01";
next_micro_state <= div15;
WHEN div15 => -- divu
set_exec_DIVU <= '1';
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Conditions
-----------------------------------------------------------------------------
PROCESS (opcode, Flags)
BEGIN
CASE opcode(11 downto 8) IS
WHEN X"0" => condition <= '1';
WHEN X"1" => condition <= '0';
WHEN X"2" => condition <= NOT Flags(0) AND NOT Flags(2);
WHEN X"3" => condition <= Flags(0) OR Flags(2);
WHEN X"4" => condition <= NOT Flags(0);
WHEN X"5" => condition <= Flags(0);
WHEN X"6" => condition <= NOT Flags(2);
WHEN X"7" => condition <= Flags(2);
WHEN X"8" => condition <= NOT Flags(1);
WHEN X"9" => condition <= Flags(1);
WHEN X"a" => condition <= NOT Flags(3);
WHEN X"b" => condition <= Flags(3);
WHEN X"c" => condition <= (Flags(3) AND Flags(1)) OR (NOT Flags(3) AND NOT Flags(1));
WHEN X"d" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1));
WHEN X"e" => condition <= (Flags(3) AND Flags(1) AND NOT Flags(2)) OR (NOT Flags(3) AND NOT Flags(1) AND NOT Flags(2));
WHEN X"f" => condition <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR Flags(2);
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Bits
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, OP2out, one_bit_in, one_bit_out, bit_Number, bit_number_reg)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --btst
one_bit_out <= one_bit_in;
WHEN "01" => --bchg
one_bit_out <= NOT one_bit_in;
WHEN "10" => --bclr
one_bit_out <= '0';
WHEN "11" => --bset
one_bit_out <= '1';
WHEN OTHERS => null;
END CASE;
IF opcode(8)='0' THEN
IF opcode(5 downto 4)="00" THEN
bit_number <= bit_number_reg(4 downto 0);
ELSE
bit_number <= "00"&bit_number_reg(2 downto 0);
END IF;
ELSE
IF opcode(5 downto 4)="00" THEN
bit_number <= OP2out(4 downto 0);
ELSE
bit_number <= "00"&OP2out(2 downto 0);
END IF;
END IF;
bits_out <= OP1out;
CASE bit_Number IS
WHEN "00000" => one_bit_in <= OP1out(0);
bits_out(0) <= one_bit_out;
WHEN "00001" => one_bit_in <= OP1out(1);
bits_out(1) <= one_bit_out;
WHEN "00010" => one_bit_in <= OP1out(2);
bits_out(2) <= one_bit_out;
WHEN "00011" => one_bit_in <= OP1out(3);
bits_out(3) <= one_bit_out;
WHEN "00100" => one_bit_in <= OP1out(4);
bits_out(4) <= one_bit_out;
WHEN "00101" => one_bit_in <= OP1out(5);
bits_out(5) <= one_bit_out;
WHEN "00110" => one_bit_in <= OP1out(6);
bits_out(6) <= one_bit_out;
WHEN "00111" => one_bit_in <= OP1out(7);
bits_out(7) <= one_bit_out;
WHEN "01000" => one_bit_in <= OP1out(8);
bits_out(8) <= one_bit_out;
WHEN "01001" => one_bit_in <= OP1out(9);
bits_out(9) <= one_bit_out;
WHEN "01010" => one_bit_in <= OP1out(10);
bits_out(10) <= one_bit_out;
WHEN "01011" => one_bit_in <= OP1out(11);
bits_out(11) <= one_bit_out;
WHEN "01100" => one_bit_in <= OP1out(12);
bits_out(12) <= one_bit_out;
WHEN "01101" => one_bit_in <= OP1out(13);
bits_out(13) <= one_bit_out;
WHEN "01110" => one_bit_in <= OP1out(14);
bits_out(14) <= one_bit_out;
WHEN "01111" => one_bit_in <= OP1out(15);
bits_out(15) <= one_bit_out;
WHEN "10000" => one_bit_in <= OP1out(16);
bits_out(16) <= one_bit_out;
WHEN "10001" => one_bit_in <= OP1out(17);
bits_out(17) <= one_bit_out;
WHEN "10010" => one_bit_in <= OP1out(18);
bits_out(18) <= one_bit_out;
WHEN "10011" => one_bit_in <= OP1out(19);
bits_out(19) <= one_bit_out;
WHEN "10100" => one_bit_in <= OP1out(20);
bits_out(20) <= one_bit_out;
WHEN "10101" => one_bit_in <= OP1out(21);
bits_out(21) <= one_bit_out;
WHEN "10110" => one_bit_in <= OP1out(22);
bits_out(22) <= one_bit_out;
WHEN "10111" => one_bit_in <= OP1out(23);
bits_out(23) <= one_bit_out;
WHEN "11000" => one_bit_in <= OP1out(24);
bits_out(24) <= one_bit_out;
WHEN "11001" => one_bit_in <= OP1out(25);
bits_out(25) <= one_bit_out;
WHEN "11010" => one_bit_in <= OP1out(26);
bits_out(26) <= one_bit_out;
WHEN "11011" => one_bit_in <= OP1out(27);
bits_out(27) <= one_bit_out;
WHEN "11100" => one_bit_in <= OP1out(28);
bits_out(28) <= one_bit_out;
WHEN "11101" => one_bit_in <= OP1out(29);
bits_out(29) <= one_bit_out;
WHEN "11110" => one_bit_in <= OP1out(30);
bits_out(30) <= one_bit_out;
WHEN "11111" => one_bit_in <= OP1out(31);
bits_out(31) <= one_bit_out;
WHEN OTHERS => null;
END CASE;
END PROCESS;
-----------------------------------------------------------------------------
-- Rotation
-----------------------------------------------------------------------------
PROCESS (opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, rot_nop)
BEGIN
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_rot <= OP1out(7);
WHEN "01"|"11" => --Word
rot_rot <= OP1out(15);
WHEN "10" => --Long
rot_rot <= OP1out(31);
WHEN OTHERS => null;
END CASE;
CASE rot_bits IS
WHEN "00" => --ASL, ASR
rot_lsb <= '0';
rot_msb <= rot_rot;
WHEN "01" => --LSL, LSR
rot_lsb <= '0';
rot_msb <= '0';
WHEN "10" => --ROXL, ROXR
rot_lsb <= Flags(4);
rot_msb <= Flags(4);
WHEN "11" => --ROL, ROR
rot_lsb <= rot_rot;
rot_msb <= OP1out(0);
WHEN OTHERS => null;
END CASE;
IF rot_nop='1' THEN
rot_out <= OP1out;
rot_XC <= Flags(0);
ELSE
IF opcode(8)='1' THEN --left
rot_out <= OP1out(30 downto 0)&rot_lsb;
rot_XC <= rot_rot;
ELSE --right
rot_XC <= OP1out(0);
rot_out <= rot_msb&OP1out(31 downto 1);
CASE opcode(7 downto 6) IS
WHEN "00" => --Byte
rot_out(7) <= rot_msb;
WHEN "01"|"11" => --Word
rot_out(15) <= rot_msb;
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- MULU/MULS
-----------------------------------------------------------------------------
PROCESS (clk, opcode, OP2out, muls_msb, mulu_reg, OP1sign, sign2)
BEGIN
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(15)='1' THEN --MULS Neg faktor
OP1sign <= '1';
mulu_reg <= "0000000000000000"&(0-reg_QB(15 downto 0));
ELSE
OP1sign <= '0';
mulu_reg <= "0000000000000000"®_QB(15 downto 0);
END IF;
ELSIF exec_MULU='1' THEN
mulu_reg <= dummy_mulu;
END IF;
END IF;
END IF;
IF (opcode(8)='1' AND OP2out(15)='1') OR OP1sign='1' THEN
muls_msb <= mulu_reg(31);
ELSE
muls_msb <= '0';
END IF;
IF opcode(8)='1' AND OP2out(15)='1' THEN
sign2 <= '1';
ELSE
sign2 <= '0';
END IF;
IF mulu_reg(0)='1' THEN
IF OP1sign='1' THEN
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))-(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
ELSE
dummy_mulu <= (muls_msb&mulu_reg(31 downto 16))+(sign2&OP2out(15 downto 0))& mulu_reg(15 downto 1);
END IF;
ELSE
dummy_mulu <= muls_msb&mulu_reg(31 downto 1);
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- DIVU
-----------------------------------------------------------------------------
PROCESS (clk, execOPC, opcode, OP1out, OP2out, div_reg, dummy_div_sub, div_quot, div_sign, dummy_div_over, dummy_div)
BEGIN
set_V_Flag <= '0';
IF rising_edge(clk) THEN
IF clkena='1' THEN
IF decodeOPC='1' THEN
IF opcode(8)='1' AND reg_QB(31)='1' THEN -- Neg divisor
div_sign <= '1';
div_reg <= 0-reg_QB;
ELSE
div_sign <= '0';
div_reg <= reg_QB;
END IF;
ELSIF exec_DIVU='1' THEN
div_reg <= div_quot;
END IF;
END IF;
END IF;
dummy_div_over <= ('0'&OP1out(31 downto 16))-('0'&OP2out(15 downto 0));
IF opcode(8)='1' AND OP2out(15) ='1' THEN
dummy_div_sub <= (div_reg(31 downto 15))+('1'&OP2out(15 downto 0));
ELSE
dummy_div_sub <= (div_reg(31 downto 15))-('0'&OP2out(15 downto 0));
END IF;
IF (dummy_div_sub(16))='1' THEN
div_quot(31 downto 16) <= div_reg(30 downto 15);
ELSE
div_quot(31 downto 16) <= dummy_div_sub(15 downto 0);
END IF;
div_quot(15 downto 0) <= div_reg(14 downto 0)&NOT dummy_div_sub(16);
IF execOPC='1' AND opcode(8)='1' AND (OP2out(15) XOR div_sign)='1' THEN
dummy_div(15 downto 0) <= 0-div_quot(15 downto 0);
ELSE
dummy_div(15 downto 0) <= div_quot(15 downto 0);
END IF;
IF div_sign='1' THEN
dummy_div(31 downto 16) <= 0-div_quot(31 downto 16);
ELSE
dummy_div(31 downto 16) <= div_quot(31 downto 16);
END IF;
IF (opcode(8)='1' AND (OP2out(15) XOR div_sign XOR dummy_div(15))='1' AND dummy_div(15 downto 0)/=X"0000") --Overflow DIVS
OR (opcode(8)='0' AND dummy_div_over(16)='0') THEN --Overflow DIVU
set_V_Flag <= '1';
END IF;
END PROCESS;
-----------------------------------------------------------------------------
-- Movem
-----------------------------------------------------------------------------
PROCESS (reset, clk, movem_mask, movem_muxa ,movem_muxb, movem_muxc)
BEGIN
IF movem_mask(7 downto 0)="00000000" THEN
movem_muxa <= movem_mask(15 downto 8);
movem_regaddr(3) <= '1';
ELSE
movem_muxa <= movem_mask(7 downto 0);
movem_regaddr(3) <= '0';
END IF;
IF movem_muxa(3 downto 0)="0000" THEN
movem_muxb <= movem_muxa(7 downto 4);
movem_regaddr(2) <= '1';
ELSE
movem_muxb <= movem_muxa(3 downto 0);
movem_regaddr(2) <= '0';
END IF;
IF movem_muxb(1 downto 0)="00" THEN
movem_muxc <= movem_muxb(3 downto 2);
movem_regaddr(1) <= '1';
ELSE
movem_muxc <= movem_muxb(1 downto 0);
movem_regaddr(1) <= '0';
END IF;
IF movem_muxc(0)='0' THEN
movem_regaddr(0) <= '1';
ELSE
movem_regaddr(0) <= '0';
END IF;
movem_bits <= ("0000"&movem_mask(0))+("0000"&movem_mask(1))+("0000"&movem_mask(2))+("0000"&movem_mask(3))+
("0000"&movem_mask(4))+("0000"&movem_mask(5))+("0000"&movem_mask(6))+("0000"&movem_mask(7))+
("0000"&movem_mask(8))+("0000"&movem_mask(9))+("0000"&movem_mask(10))+("0000"&movem_mask(11))+
("0000"&movem_mask(12))+("0000"&movem_mask(13))+("0000"&movem_mask(14))+("0000"&movem_mask(15));
IF reset = '0' THEN
movem_busy <= '0';
movem_addr <= '0';
maskzero <= '0';
ELSIF rising_edge(clk) THEN
IF clkena_in='1' AND get_movem_mask='1' THEN
movem_mask <= data_read(15 downto 0);
END IF;
IF clkena_in='1' AND test_maskzero='1' THEN
IF movem_mask=X"0000" THEN
maskzero <= '1';
END IF;
END IF;
IF clkena_in='1' AND endOPC='1' THEN
maskzero <= '0';
END IF;
IF clkena='1' THEN
IF set_movem_busy='1' THEN
IF movem_bits(4 downto 1) /= "0000" OR opcode(10)='0' THEN
movem_busy <= '1';
END IF;
movem_addr <= '1';
END IF;
IF movem_addr='1' THEN
CASE movem_regaddr IS
WHEN "0000" => movem_mask(0) <= '0';
WHEN "0001" => movem_mask(1) <= '0';
WHEN "0010" => movem_mask(2) <= '0';
WHEN "0011" => movem_mask(3) <= '0';
WHEN "0100" => movem_mask(4) <= '0';
WHEN "0101" => movem_mask(5) <= '0';
WHEN "0110" => movem_mask(6) <= '0';
WHEN "0111" => movem_mask(7) <= '0';
WHEN "1000" => movem_mask(8) <= '0';
WHEN "1001" => movem_mask(9) <= '0';
WHEN "1010" => movem_mask(10) <= '0';
WHEN "1011" => movem_mask(11) <= '0';
WHEN "1100" => movem_mask(12) <= '0';
WHEN "1101" => movem_mask(13) <= '0';
WHEN "1110" => movem_mask(14) <= '0';
WHEN "1111" => movem_mask(15) <= '0';
WHEN OTHERS => null;
END CASE;
IF opcode(10)='1' THEN
IF movem_bits="00010" OR movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
END IF;
END IF;
IF movem_bits="00001" OR movem_bits="00000" THEN
movem_busy <= '0';
movem_addr <= '0';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
END;
| gpl-3.0 | ac9943074ee535033f81572cbe2c4242 | 0.482105 | 3.110093 | false | false | false | false |
esar/hdmilight-v1 | fpga/ipcore_dir/line_buffer_ram.vhd | 2 | 6,305 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file line_buffer_ram.vhd when simulating
-- the core, line_buffer_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY line_buffer_ram IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END line_buffer_ram;
ARCHITECTURE line_buffer_ram_a OF line_buffer_ram IS
-- synthesis translate_off
COMPONENT wrapped_line_buffer_ram
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_line_buffer_ram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 7,
c_addrb_width => 7,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 1,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 1,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 128,
c_read_depth_b => 128,
c_read_width_a => 64,
c_read_width_b => 64,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 128,
c_write_depth_b => 128,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 64,
c_write_width_b => 64,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_line_buffer_ram
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END line_buffer_ram_a;
| gpl-2.0 | 2d59443673d9e26146cb610be9f6f549 | 0.540048 | 3.849206 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/shift8.vhd | 2 | 7,262 | -------------------------------------------------------------------------------
-- shift8.vhd - Entity and Architecture
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: shift8.vhd
-- Version: v1.01.b
-- Description:
-- This file contains an 8 bit shift register
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- System reset
-- Data_ld -- Shift register data load enable
-- Data_in -- Shift register data in
-- Shift_in -- Shift register serial data in
-- Shift_en -- Shift register shift enable
-- Shift_out -- Shift register serial data out
-- Data_out -- Shift register shift data out
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity shift8 is
port(
Clk : in std_logic; -- Clock
Clr : in std_logic; -- Clear
Data_ld : in std_logic; -- Data load enable
Data_in : in std_logic_vector (7 downto 0);-- Data to load in
Shift_in : in std_logic; -- Serial data in
Shift_en : in std_logic; -- Shift enable
Shift_out : out std_logic; -- Shift serial data out
Data_out : out std_logic_vector (7 downto 0) -- Shifted data
);
end shift8;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of shift8 is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal data_int : std_logic_vector (7 downto 0);
begin
----------------------------------------------------------------------------
-- PROCESS: SHIFT_REG_GEN
-- purpose: generate shift register
----------------------------------------------------------------------------
SHIFT_REG_GEN : process(Clk)
begin
if Clk'event and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
data_int <= (others => '0');
elsif (Data_ld = '1') then -- Load data
data_int <= Data_in;
elsif Shift_en = '1' then -- If shift enable is high
data_int <= data_int(6 downto 0) & Shift_in; -- Shift the data
end if;
end if;
end process SHIFT_REG_GEN;
Shift_out <= data_int(7);
Data_out <= data_int;
end architecture RTL;
| gpl-3.0 | 10ac2e40fdebf06cfcce51e7bb3cd380 | 0.404434 | 5.165007 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/xor_component.vhd | 1 | 1,348 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 06-04-2017
-- Package Name: alu_component
-- Module Name: XOR_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity XOR_COMPONENT is
port(
INPUT1 : in std_logic_vector(15 downto 0);
INPUT2 : in std_logic_vector(15 downto 0);
OUTPUT : out std_logic_vector(15 downto 0)
);
end entity;
architecture XOR_COMPONENT_ARCH of XOR_COMPONENT is
begin
OUTPUT(0) <= INPUT1(0) xor INPUT2(0);
OUTPUT(1) <= INPUT1(1) xor INPUT2(1);
OUTPUT(2) <= INPUT1(2) xor INPUT2(2);
OUTPUT(3) <= INPUT1(3) xor INPUT2(3);
OUTPUT(4) <= INPUT1(4) xor INPUT2(4);
OUTPUT(5) <= INPUT1(5) xor INPUT2(5);
OUTPUT(6) <= INPUT1(6) xor INPUT2(6);
OUTPUT(7) <= INPUT1(7) xor INPUT2(7);
OUTPUT(8) <= INPUT1(8) xor INPUT2(8);
OUTPUT(9) <= INPUT1(9) xor INPUT2(9);
OUTPUT(10) <= INPUT1(10) xor INPUT2(10);
OUTPUT(11) <= INPUT1(11) xor INPUT2(11);
OUTPUT(12) <= INPUT1(12) xor INPUT2(12);
OUTPUT(13) <= INPUT1(13) xor INPUT2(13);
OUTPUT(14) <= INPUT1(14) xor INPUT2(14);
OUTPUT(15) <= INPUT1(15) xor INPUT2(15);
end architecture; | gpl-3.0 | 169d7c57dd5e1d172016b54b363cc76c | 0.523739 | 3.056689 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | tb/rf_tb.vhd | 1 | 1,083 | library IEEE;
use IEEE.std_logic_1164.all;
entity RF_TB is
end entity;
architecture RF_TB_ARCH of RF_TB is
signal clock : std_logic := '0';
signal we : std_logic;
signal input, output1, output2 : std_logic_vector(15 downto 0);
signal inAdr, outAdr1, outAdr2 : std_logic_vector(3 downto 0);
component registerFile is
port (
CLK : in std_logic;
W_EN : in std_logic;
INPUT : in std_logic_vector(15 downto 0);
IN_ADR : in std_logic_vector(3 downto 0);
OUT1_ADR: in std_logic_vector(3 downto 0);
OUT2_ADR: in std_logic_vector(3 downto 0);
OUTPUT1 : out std_logic_vector(15 downto 0);
OUTPUT2 : out std_logic_vector(15 downto 0)
);
end component;
begin
registerFileIns : registerFile port map(clock, we, input, inAdr, outAdr1, outAdr2, output1, output2);
clock <= not clock after 100 ns;
we <= '0', '1' after 90 ns, '0' after 500 ns;
input <= "0000000000001110", "1010101010101010" after 290 ns;
inAdr <= "0001", "0111" after 290 ns;
outAdr1 <= "0001";
outAdr2 <= "0111";
end architecture;
| gpl-3.0 | c82fef0114ad4b4ebd60c0ec59a5c1df | 0.649123 | 3 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/multiplication_component.vhd | 1 | 1,981 |
library IEEE;
use IEEE.std_logic_1164.all;
entity MULTIPLICATION_COMPONENT is
port(
INPUT1 : in std_logic_vector(7 downto 0);
INPUT2 : in std_logic_vector(7 downto 0);
OUTPUT : out std_logic_vector(15 downto 0)
);
end entity;
architecture MULTIPLICATION_COMPONENT_ARCH of MULTIPLICATION_COMPONENT is
component ADDER_SUBTRACTOR_COMPONENT is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(15 downto 0);
INPUT2 : in std_logic_vector(15 downto 0);
IS_SUB : in std_logic; -- 0 for add and 1 for subtraction
SUM : out std_logic_vector(15 downto 0);
CARRY_OUT : out std_logic;
OVERFLOW : out std_logic
);
end component;
type arraySignals is array (0 to 7) of std_logic;
type arr_8_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type arr_8_16 is array (0 to 7) of std_logic_vector(15 downto 0);
signal cables : arraySignals;
signal khar, gav, ain, summ : arr_8_8;
signal gav16, ain16, summ16 : arr_8_16;
begin
MAKING_IN:
for W in 0 to 7 generate
ANDING:
for J in 0 to 7 generate
gav(W)(j) <= INPUT1(J) and INPUT2(W);
end generate;
end generate;
ain(0)(7) <= '0';
KHAAR:
for L in 0 to 6 generate
ain(0)(L) <= gav(0)(L + 1);
end generate;
output(0) <= gav(0)(0);
CONNECT:
for I in 0 to 6 generate
gav16(I + 1) <= "00000000" & gav(I + 1);
ain16(I) <= "00000000" & ain(I);
summ(I) <= summ16(I)(7 downto 0);
MODULE: ADDER_SUBTRACTOR_COMPONENT
port map('0',gav16(I + 1) ,ain16(I) , '0', summ16(I), cables(I), open);
ain(I + 1)(7) <= cables(I);
MAKING:
for K in 0 to 6 generate
ain(I + 1)(K) <= summ(I)(K + 1);
end generate;
output(I + 1) <= summ(I)(0);
end generate;
-- AH:
-- for Q in 0 to COMPONENT_SIZE/2 - 1 generate
-- output(Q + COMPONENT_SIZE/2) <= summ(COMPONENT_SIZE/2 - 2)(Q);
-- end generate;
AH:
for Q in 0 to 6 generate
output(Q + 8) <= summ(6)(Q + 1);
end generate;
output(15) <= cables(6);
end architecture;
| gpl-3.0 | 01f16df38762be34bada0fd9d1418a77 | 0.625442 | 2.54955 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_pctrl.vhd | 1 | 15,411 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
ENTITY k7_mBuf_128x72_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF k7_mBuf_128x72_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:k7_mBuf_128x72_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:k7_mBuf_128x72_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | f85a410c6e0db2c4dc33efb8ff047a1f | 0.520278 | 3.359712 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/tb/cross_clock_two_inst_tb.vhd | 1 | 6,806 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.axistream_spw_lite_v1_0_pkg.all;
entity cross_clock_two_inst_tb is
generic (
sysfreq_i0 : real := 100000000.0;
aclk_period_i0 : time := 10 ns; -- 100 MHz clock
txclkfreq_i0 : real := 200000000.0;
txclk_period_i0 : time := 5 ns;
rxclk_period_i0 : time := 5 ns;
sysfreq_i1 : real := 33000000.0;
aclk_period_i1 : time := 30.3030303 ns; -- 33 MHz clock
txclkfreq_i1 : real := 200000000.0;
txclk_period_i1 : time := 5 ns;
rxclk_period_i1 : time := 5 ns;
--rximpl : spw_implementation_type := impl_generic;
rxchunk_fast : integer range 1 to 4 := 1;
--tximpl : spw_implementation_type := impl_generic;
rxfifosize_bits : integer range 6 to 14 := 11; -- 11 (2 kByte)
txfifosize_bits : integer range 2 to 14 := 11; -- 11 (2 kByte)
txdivcnt : std_logic_vector(7 downto 0) := x"04";
rximpl_fast : boolean := false; -- true to use rx_clk
tximpl_fast : boolean := false -- true to use tx_clk
);
end cross_clock_two_inst_tb;
architecture arch_imp of cross_clock_two_inst_tb is
signal start : boolean := true;
-- control signals instance 0
signal aclk_i0, txclk_i0, rxclk_i0 : std_logic := '0';
signal aresetn_i0 : std_logic := '0';
-- control signals instance 1
signal aclk_i1, txclk_i1, rxclk_i1 : std_logic := '1';
signal aresetn_i1 : std_logic := '0';
-- data connections
signal s_do : std_logic := '0';
signal s_di : std_logic := '0';
signal s_so : std_logic := '0';
signal s_si : std_logic := '0';
-- slave axis lines
signal s_axis_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal s_axis_tvalid : std_logic := '0';
signal s_axis_tready : std_logic := '0';
signal s_axis_tlast : std_logic := '0';
-- master axis lines
signal m_axis_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_tvalid : std_logic := '0';
signal m_axis_tready : std_logic := '0';
signal m_axis_tlast : std_logic := '0';
signal rx_error : std_logic := '0';
-- loopback axis
signal lb_axis_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal lb_axis_tvalid : std_logic := '0';
signal lb_axis_tready : std_logic := '0';
signal lb_axis_tlast : std_logic := '0';
-- test data
signal word_in : unsigned(7 downto 0) := (others => '0');
signal word_out : unsigned(7 downto 0) := (others => '0');
signal expected_word : unsigned(7 downto 0) := (others => '0');
signal TLAST_NOT_ASSERTED : std_logic := '0';
signal INVALID_WORD_RECEIVED : std_logic := '0';
begin
------- INSTANCE 0 CLOCKS
aclk_i0_gen : process
begin
if(start) then
wait for aclk_period_i0/7;
start <= false;
end if;
aclk_i0 <= not aclk_i0;
wait for aclk_period_i0/2;
end process aclk_i0_gen;
txclk_i0_gen : process
begin
if(start) then
wait for txclk_period_i0/3;
end if;
txclk_i0 <= not txclk_i0;
wait for txclk_period_i0/2;
end process txclk_i0_gen;
rxclk_i0_gen : process
begin
if(start) then
wait for rxclk_period_i0/4;
end if;
rxclk_i0 <= not rxclk_i0;
wait for rxclk_period_i0/2;
end process rxclk_i0_gen;
------- INSTANCE 1 CLOCKS
aclk_i1_gen : process
begin
aclk_i1 <= not aclk_i1;
wait for aclk_period_i1/2;
end process aclk_i1_gen;
txclk_i1_gen : process
begin
txclk_i1 <= not txclk_i1;
wait for txclk_period_i1/2;
end process txclk_i1_gen;
rxclk_i1_gen : process
begin
rxclk_i1 <= not rxclk_i1;
wait for rxclk_period_i1/2;
end process rxclk_i1_gen;
reset_i1_gen : process
begin
aresetn_i1 <= '0';
aresetn_i0 <= '0';
wait for aclk_period_i1*5;
aresetn_i1 <= '1';
aresetn_i1 <= '0';
wait for 1000 ms;
end process reset_i1_gen;
axistream_spw_lite_v1_0_inst_i0 : axistream_spw_lite_v1_0
generic map (
sysfreq => sysfreq_i0,
txclkfreq => txclkfreq_i0,
rximpl_fast => rximpl_fast,
rxchunk_fast => rxchunk_fast,
tximpl_fast => tximpl_fast,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits,
txdivcnt => txdivcnt
)
port map (
aclk => aclk_i0,
aresetn => aresetn_i0,
rx_clk => rxclk_i0,
tx_clk => txclk_i0,
spw_di => s_di,
spw_si => s_si,
spw_do => s_do,
spw_so => s_so,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
rx_error => rx_error
);
axistream_spw_lite_v1_0_inst_i1 : axistream_spw_lite_v1_0
generic map (
sysfreq => sysfreq_i1,
txclkfreq => txclkfreq_i1,
rximpl_fast => rximpl_fast,
rxchunk_fast => rxchunk_fast,
tximpl_fast => tximpl_fast,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits,
txdivcnt => txdivcnt
)
port map (
aclk => aclk_i1,
aresetn => aresetn_i1,
rx_clk => rxclk_i1,
tx_clk => txclk_i1,
spw_di => s_do,
spw_si => s_so,
spw_do => s_di,
spw_so => s_si,
s_axis_tdata => lb_axis_tdata,
s_axis_tvalid => lb_axis_tvalid,
s_axis_tready => lb_axis_tready,
s_axis_tlast => lb_axis_tlast,
m_axis_tdata => lb_axis_tdata,
m_axis_tvalid => lb_axis_tvalid,
m_axis_tready => lb_axis_tready,
m_axis_tlast => lb_axis_tlast,
rx_error => rx_error
);
s_axis_tvalid <= '1';
m_axis_tready <= '1';
s_axis_tdata <= std_logic_vector(word_in);
s_axis_tlast <= '1' when word_in = to_unsigned(255, 8) else '0';
word_out <= unsigned(m_axis_tdata) when m_axis_tvalid = '1' else word_out;
process(aclk_i0)
begin
if(rising_edge(aclk_i0)) then
if(m_axis_tvalid = '1') then
expected_word <= expected_word + 1;
if(unsigned(m_axis_tdata) /= expected_word) then
report "INVALID WORD RECEIVED" severity warning;
INVALID_WORD_RECEIVED <= '1';
end if;
if(unsigned(m_axis_tdata) = 255 and m_axis_tlast = '0' and m_axis_tvalid = '1') then
report "TLAST NOT ASSERTED" severity warning;
TLAST_NOT_ASSERTED <= '1';
end if;
end if;
end if;
end process;
process(aclk_i0)
begin
if(rising_edge(aclk_i0)) then
if(s_axis_tready = '1') then
word_in <= word_in + 1;
end if;
end if;
end process;
end arch_imp;
| mit | baace74e2d697483663e07818332d6c7 | 0.576403 | 2.888795 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/DDR_Blinker.vhd | 1 | 6,016 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DDR_Blink is
Port (
DDR_blinker : OUT std_logic;
DDR_Write : IN std_logic;
DDR_Read : IN std_logic;
DDR_Both : IN std_logic;
ddr_Clock : IN std_logic;
DDr_Rst_n : IN std_logic
);
end entity DDR_Blink;
architecture Behavioral of DDR_Blink is
-- Blinking -_-_-_-_
Constant C_BLINKER_MSB : integer := 15; -- 4; -- 15;
Constant CBIT_SLOW_BLINKER : integer := 11; -- 2; -- 11;
signal DDR_blinker_i : std_logic;
signal Fast_blinker : std_logic_vector(C_BLINKER_MSB downto 0);
signal Fast_blinker_MSB_r1 : std_logic;
signal Blink_Pulse : std_logic;
signal Slow_blinker : std_logic_vector(CBIT_SLOW_BLINKER downto 0);
signal DDR_write_extension : std_logic;
signal DDR_write_extension_Cnt: std_logic_vector(1 downto 0);
signal DDR_read_extension : std_logic;
signal DDR_read_extension_Cnt : std_logic_vector(1 downto 0);
begin
--
Syn_DDR_Fast_blinker:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
Fast_blinker <= (OTHERS=>'0');
Fast_blinker_MSB_r1 <= '0';
Blink_Pulse <= '0';
Slow_blinker <= (OTHERS=>'0');
elsif ddr_Clock'event and ddr_Clock = '1' then
Fast_blinker <= Fast_blinker + '1';
Fast_blinker_MSB_r1 <= Fast_blinker(C_BLINKER_MSB);
Blink_Pulse <= Fast_blinker(C_BLINKER_MSB) and not Fast_blinker_MSB_r1;
Slow_blinker <= Slow_blinker + Blink_Pulse;
end if;
end process;
--
Syn_DDR_Write_Extenstion:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_write_extension_Cnt <= (OTHERS=>'0');
DDR_write_extension <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_write_extension_Cnt is
when "00" =>
if DDR_Write='1' then
DDR_write_extension_Cnt <= "01";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_write_extension_Cnt <= "11";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
DDR_write_extension_Cnt <= "10";
DDR_write_extension <= '1';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
when Others =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_write_extension_Cnt <= "00";
DDR_write_extension <= '0';
else
DDR_write_extension_Cnt <= DDR_write_extension_Cnt;
DDR_write_extension <= DDR_write_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Read_Extenstion:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_read_extension_Cnt <= (OTHERS=>'0');
DDR_read_extension <= '1';
elsif ddr_Clock'event and ddr_Clock = '1' then
case DDR_read_extension_Cnt is
when "00" =>
if DDR_Read='1' then
DDR_read_extension_Cnt <= "01";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "01" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_read_extension_Cnt <= "11";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when "11" =>
if Slow_blinker(CBIT_SLOW_BLINKER)='0' then
DDR_read_extension_Cnt <= "10";
DDR_read_extension <= '0';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
when Others =>
if Slow_blinker(CBIT_SLOW_BLINKER)='1' then
DDR_read_extension_Cnt <= "00";
DDR_read_extension <= '1';
else
DDR_read_extension_Cnt <= DDR_read_extension_Cnt;
DDR_read_extension <= DDR_read_extension;
end if;
end case;
end if;
end process;
--
Syn_DDR_Working_blinker:
process ( ddr_Clock, DDr_Rst_n)
begin
if DDr_Rst_n = '0' then
DDR_Blinker_i <= '0';
elsif ddr_Clock'event and ddr_Clock = '1' then
DDR_Blinker_i <= (Slow_blinker(CBIT_SLOW_BLINKER-2) or DDR_write_extension) and DDR_read_extension;
-- DDR_Blinker_i <= Slow_blinker(CBIT_SLOW_BLINKER-2);
end if;
end process;
DDR_blinker <= DDR_blinker_i;
end architecture Behavioral;
| gpl-2.0 | 929b1f72bbe83ea821ca0ea1b286ddff | 0.506316 | 3.778894 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwlink_tb.vhd | 1 | 41,480 | --
-- Test Bench for Link interface.
--
-- Unfortunately rather incomplete.
-- The following items are verified:
-- * reset;
-- * link start, NULL exchange, FCT exchange;
-- * link autostart on first NULL;
-- * send/receive time codes, data characters, EOP/EEP;
-- * detection of timeout, disconnection, parity error, escape error.
--
library ieee;
use ieee.std_logic_1164.all, ieee.numeric_std.all;
use std.textio.all;
use work.spwpkg.all;
entity spwlink_tb is
-- Tests should be done with several different combinations
-- of values for the generics.
generic (
-- System clock frequency
sys_clock_freq: real := 20.0e6 ;
-- Receiver sample clock frequency
rx_clock_freq: real := 20.0e6 ;
-- Transmitter clock frequency
tx_clock_freq: real := 20.0e6 ;
-- Input bit rate
input_rate: real := 10.0e6 ;
-- TX clock division factor (actual factor is one tx_clock_div+1)
tx_clock_div: integer := 1 ;
-- Receiver implementation
rximpl: spw_implementation_type := impl_generic ;
-- Bits per sysclk for fast receiver
rxchunk: integer := 1 ;
-- Transmitter implementation
tximpl: spw_implementation_type := impl_generic ;
-- Wait before starting test bench
startwait: time := 0 sec
);
end spwlink_tb;
architecture tb_arch of spwlink_tb is
-- Bit periods for incoming / outgoing signal
constant inbit_period: time := (1 sec) / input_rate ;
constant outbit_period: time := (1 sec) * real(tx_clock_div + 1) / tx_clock_freq ;
constant txclk_period: time := (1 sec) / tx_clock_freq ;
-- clock generation
signal sys_clock_enable: std_logic := '0';
signal sysclk: std_logic;
signal rxclk: std_logic;
signal txclk: std_logic;
-- output monitoring
type t_output_chars is array(natural range <>) of std_logic_vector(9 downto 0);
signal output_collect: std_logic;
signal output_ptr: integer;
signal output_bits: std_logic_vector(0 to 4095);
signal output_nchars: integer;
signal output_chars: t_output_chars(0 to 4095);
-- input generation
signal input_par: std_logic;
signal input_idle: std_logic;
signal input_pattern: integer := 0;
signal input_strobeflip: std_logic := '0';
-- interconnect signals
signal s_linki: spw_link_in_type;
signal s_linko: spw_link_out_type;
signal s_rxen: std_logic;
signal s_recvo: spw_recv_out_type;
signal s_xmiti: spw_xmit_in_type;
signal s_xmito: spw_xmit_out_type;
signal s_inact: std_logic;
signal s_inbvalid: std_logic;
signal s_inbits: std_logic_vector(rxchunk-1 downto 0);
-- interface signals
signal rst: std_logic := '1';
signal autostart: std_logic;
signal linkstart: std_logic;
signal linkdis: std_logic;
signal divcnt: std_logic_vector(7 downto 0) := (others => '0');
signal tick_in: std_logic;
signal ctrl_in: std_logic_vector(1 downto 0);
signal time_in: std_logic_vector(5 downto 0);
signal rxroom: std_logic_vector(5 downto 0);
signal txwrite: std_logic;
signal txflag: std_logic;
signal txdata: std_logic_vector(7 downto 0);
signal txrdy: std_logic;
signal tick_out: std_logic;
signal ctrl_out: std_logic_vector(1 downto 0);
signal time_out: std_logic_vector(5 downto 0);
signal rxchar: std_logic;
signal rxflag: std_logic;
signal rxdata: std_logic_vector(7 downto 0);
signal started: std_logic;
signal connecting:std_logic;
signal running: std_logic;
signal errdisc: std_logic;
signal errpar: std_logic;
signal erresc: std_logic;
signal errcred: std_logic;
signal spw_di: std_logic;
signal spw_si: std_logic;
signal spw_do: std_logic;
signal spw_so: std_logic;
-- misc
signal errany: std_logic;
procedure print(i: integer) is
variable v: LINE;
begin
write(v, i);
writeline(output, v);
end procedure;
procedure print(x: std_logic_vector) is
variable v: LINE;
begin
write(v, to_bitvector(x));
writeline(output, v);
end procedure;
procedure prints(s: string) is
variable v: LINE;
begin
write(v, s);
writeline(output, v);
end procedure;
procedure print(lbl: string; x: integer) is
variable v: LINE;
begin
write(v, lbl & " = ");
write(v, x);
writeline(output, v);
end procedure;
procedure print(lbl: string; x: real) is
variable v: LINE;
begin
write(v, lbl & " = ");
write(v, x);
writeline(output, v);
end procedure;
begin
-- Instantiate components.
spwlink_inst: spwlink
generic map (
reset_time => integer(sys_clock_freq * 0.0000064) ) -- 6.4 us
port map (
clk => sysclk,
rst => rst,
linki => s_linki,
linko => s_linko,
rxen => s_rxen,
recvo => s_recvo,
xmiti => s_xmiti,
xmito => s_xmito );
spwrecv_inst: spwrecv
generic map (
disconnect_time => integer(sys_clock_freq * 0.00000085), -- 850 ns
rxchunk => rxchunk )
port map (
clk => sysclk,
rxen => s_rxen,
recvo => s_recvo,
inact => s_inact,
inbvalid => s_inbvalid,
inbits => s_inbits );
spwxmit_if: if tximpl = impl_generic generate
spwxmit_inst: spwxmit
port map (
clk => sysclk,
rst => rst,
divcnt => divcnt,
xmiti => s_xmiti,
xmito => s_xmito,
spw_so => spw_so,
spw_do => spw_do );
end generate;
spwxmit_fast_if: if tximpl = impl_fast generate
spwxmit_fast_inst: spwxmit_fast
port map (
clk => sysclk,
txclk => txclk,
rst => rst,
divcnt => divcnt,
xmiti => s_xmiti,
xmito => s_xmito,
spw_so => spw_so,
spw_do => spw_do );
end generate;
spwrecvfront_generic_if: if rximpl = impl_generic generate
spwrecvfront_generic_inst: spwrecvfront_generic
port map (
clk => sysclk,
rxen => s_rxen,
inact => s_inact,
inbvalid => s_inbvalid,
inbits => s_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
spwrecvfront_fast_if: if rximpl = impl_fast generate
spwrecvfront_fast_inst: spwrecvfront_fast
generic map (
rxchunk => rxchunk )
port map (
clk => sysclk,
rxclk => rxclk,
rxen => s_rxen,
inact => s_inact,
inbvalid => s_inbvalid,
inbits => s_inbits,
spw_di => spw_di,
spw_si => spw_si );
end generate;
s_linki <= ( autostart => autostart,
linkstart => linkstart,
linkdis => linkdis,
rxroom => rxroom,
tick_in => tick_in,
ctrl_in => ctrl_in,
time_in => time_in,
txwrite => txwrite,
txflag => txflag,
txdata => txdata );
started <= s_linko.started;
connecting <= s_linko.connecting;
running <= s_linko.running;
errdisc <= s_linko.errdisc;
errpar <= s_linko.errpar;
erresc <= s_linko.erresc;
errcred <= s_linko.errcred;
txrdy <= s_linko.txack;
tick_out <= s_linko.tick_out;
ctrl_out <= s_linko.ctrl_out;
time_out <= s_linko.time_out;
rxchar <= s_linko.rxchar;
rxflag <= s_linko.rxflag;
rxdata <= s_linko.rxdata;
-- Logic OR of all error signals.
errany <= errdisc or errpar or erresc or errcred;
-- Generate system clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
sysclk <= '1';
wait for (0.5 sec) / sys_clock_freq;
sysclk <= '0';
wait for (0.5 sec) / sys_clock_freq;
end process;
-- Generate rx sample clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
rxclk <= '1';
wait for (0.5 sec) / rx_clock_freq;
rxclk <= '0';
wait for (0.5 sec) / rx_clock_freq;
end process;
-- Generate tx clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
txclk <= '1';
wait for (0.5 sec) / tx_clock_freq;
txclk <= '0';
wait for (0.5 sec) / tx_clock_freq;
end process;
-- Collect output bits on SPW_DO and SPW_SO.
process is
variable t_last: time;
variable output_last_do: std_logic;
variable output_last_so: std_logic;
begin
if output_collect = '1' then
-- wait for next bit
if output_ptr <= output_bits'high then
output_bits(output_ptr) <= spw_do;
output_ptr <= output_ptr + 1;
end if;
output_last_do := spw_do;
output_last_so := spw_so;
t_last := now;
wait until (output_collect = '0') or (output_last_do /= spw_do) or (output_last_so /= spw_so);
if output_collect = '1' and output_ptr > 1 then
assert now > t_last + outbit_period - 1 ns
report "output bit period too short";
assert now < t_last + outbit_period + 1 ns
report "output bit period too long";
end if;
else
-- reset
output_ptr <= 0;
output_last_do := '0';
output_last_so := '0';
wait until output_collect = '1';
end if;
end process;
-- Collect received data on rxdata and tick_out.
process is
begin
wait until ((output_collect = '1') and rising_edge(sysclk)) or
((output_collect = '0') and (output_nchars /= 0));
if output_collect = '0' then
output_nchars <= 0;
elsif rising_edge(sysclk) and (output_nchars <= output_chars'high) then
assert (rxchar = '0') or (tick_out = '0');
if tick_out = '1' then
output_chars(output_nchars) <= "10" & ctrl_out & time_out;
output_nchars <= output_nchars + 1;
elsif rxchar = '1' then
output_chars(output_nchars) <= "0" & (rxflag) & rxdata;
output_nchars <= output_nchars + 1;
end if;
end if;
end process;
-- Generate input data.
process is
procedure input_reset is
begin
spw_di <= '0';
spw_si <= input_strobeflip;
input_par <= '0';
end procedure;
procedure genbit(b: std_logic) is
begin
spw_si <= not (spw_si xor spw_di xor b);
spw_di <= b;
wait for inbit_period;
end procedure;
procedure genfct is
begin
genbit(input_par);
genbit('1');
genbit('0');
input_par <= '0';
genbit('0');
end procedure;
procedure genesc is
begin
genbit(input_par);
genbit('1');
genbit('1');
input_par <= '0';
genbit('1');
end procedure;
procedure geneop(e: std_logic) is
begin
genbit(input_par);
genbit('1');
genbit(e);
input_par <= '1';
genbit(not e);
end procedure;
procedure gendat(dat: std_logic_vector(7 downto 0)) is
begin
genbit(not input_par);
genbit('0');
genbit(dat(0)); genbit(dat(1)); genbit(dat(2)); genbit(dat(3));
genbit(dat(4)); genbit(dat(5)); genbit(dat(6));
input_par <= dat(0) xor dat(1) xor dat(2) xor dat(3) xor
dat(4) xor dat(5) xor dat(6) xor dat(7);
genbit(dat(7));
end procedure;
begin
input_idle <= '1';
input_reset;
wait until input_pattern /= 0;
input_idle <= '0';
while input_pattern /= 0 loop
if input_pattern = 1 then
-- NULL tokens
genesc; genfct;
elsif input_pattern = 2 then
-- FCT tokens
genfct;
elsif input_pattern = 3 then
-- invalid bit pattern
genbit('0');
genbit('1');
elsif input_pattern = 4 then
-- EOP token
geneop('0');
elsif input_pattern = 5 then
-- FCT, TIME, 8 chars, NULLs
genfct;
genesc; gendat("00111000");
gendat("01010101");
gendat("10101010");
gendat("01010101");
gendat("10101010");
gendat("01010101");
gendat("10101010");
gendat("01010101");
gendat("10101010");
while input_pattern = 5 loop
genesc; genfct;
end loop;
elsif input_pattern = 6 then
-- ESC tokens
genesc;
elsif input_pattern = 7 then
-- FCT, NULL, NULL, EOP, EEP, NULLs
genfct;
genesc; genfct;
genesc; genfct;
geneop('0');
geneop('1');
while input_pattern = 7 loop
genesc; genfct;
end loop;
elsif input_pattern = 8 then
-- FCT, NULL, NULL, NULL, NULL, NULL, char, parity error
genfct;
genesc; genfct;
genesc; genfct;
genesc; genfct;
genesc; genfct;
genesc; genfct;
gendat("01010101");
genbit(not input_par);
genbit('0');
genbit('1'); genbit('0'); genbit('1'); genbit('0');
genbit('1'); genbit('0'); genbit('1');
input_par <= '1'; -- wrong parity !!
genbit('0');
while input_pattern = 8 loop
genesc; genfct;
end loop;
elsif input_pattern = 9 then
-- FCT, FCT, NULLs
genfct;
genfct;
while input_pattern = 9 loop
genesc; genfct;
end loop;
elsif input_pattern = 10 then
-- data and strobe both high
spw_di <= '1';
spw_si <= not input_strobeflip;
wait until input_pattern /= 10;
else
assert false;
end if;
end loop;
end process;
-- Main process.
process is
-- Skip NULL tokens and return position of first non-NULL.
function skip_null(data: in std_logic_vector; start: in integer; len: in integer) return integer is
variable i: integer;
begin
i := start;
if (i + 7 < len) and (data((i+1) to (i+7)) = "1110100") then
i := i + 8;
end if;
while (i + 7 < len) and (data(i to (i+7)) = "01110100") loop
i := i + 8;
end loop;
return i;
end function;
function check_parity(data: in std_logic_vector; start: in integer; len: in integer) return boolean is
variable i: integer;
variable p: std_logic;
begin
i := start;
p := data(start);
while i + 3 < len loop
if data(i+1) = '1' then
if data(0) /= p then return false; end if;
p := data(2) xor data(3);
i := i + 4;
else
if i + 9 < len then return true; end if;
if data(0) /= not p then return false; end if;
p := not (data(2) xor data(3) xor data(4) xor data(5) xor
data(6) xor data(7) xor data(8) xor data(9));
i := i + 10;
end if;
end loop;
return true;
end function;
variable i: integer;
begin
-- Wait for start of test.
wait for startwait;
-- Initialize.
rst <= '1';
input_pattern <= 0;
input_strobeflip <= '0';
sys_clock_enable <= '1';
output_collect <= '0';
-- Say hello
report "Starting spwlink test bench";
print(" sys_clock_freq", sys_clock_freq);
print(" rx_clock_freq ", rx_clock_freq);
print(" tx_clock_freq ", tx_clock_freq);
print(" input_rate ", input_rate);
print(" tx_clock_div ", tx_clock_div);
case rximpl is
when impl_generic => prints(" rximpl = impl_generic");
when impl_fast => prints(" rximpl = impl_fast");
end case;
print(" rxchunk ", rxchunk);
case tximpl is
when impl_generic => prints(" tximpl = impl_generic");
when impl_fast => prints(" tximpl = impl_fast");
end case;
-- Test 1: Reset.
autostart <= '0'; linkstart <= '0'; linkdis <= '0';
divcnt <= std_logic_vector(to_unsigned(tx_clock_div, divcnt'length));
tick_in <= '0'; ctrl_in <= "00"; time_in <= "000000"; rxroom <= "000000";
txwrite <= '0'; txflag <= '0'; txdata <= "00000000";
wait until rising_edge(sysclk);
wait until rising_edge(sysclk);
wait for 1 ns;
rst <= '0';
assert (txrdy = '0') report " 1. reset (txrdy = 0)";
assert (tick_out = '0') report " 1. reset (tick_out = 0)";
assert (rxchar = '0') report " 1. reset (rxchar = 0)";
assert (started = '0') report " 1. reset (started = 0)";
assert (connecting = '0') report " 1. reset (connecting = 0)";
assert (running = '0') report " 1. reset (running = 0)";
assert (errdisc = '0') report " 1. reset (errdisc = 0)";
assert (errpar = '0') report " 1. reset (errpar = 0)";
assert (erresc = '0') report " 1. reset (erresc = 0)";
assert (errcred = '0') report " 1. reset (errcred = 0)";
assert (spw_do = '0') report " 1. reset (spw_do = 0)";
assert (spw_so = '0') report " 1. reset (spw_so = 0)";
-- Test 2: Remain idle after one clock cycle.
wait until rising_edge(sysclk);
wait until falling_edge(sysclk);
assert (started = '0') and (running = '0')
report " 2. init (state)";
assert (spw_do = '0') and (spw_so = '0')
report " 2. init (SPW idle)";
-- Test 3: Move to Ready state.
wait on started, running, spw_do, spw_so for 50 us;
assert (started = '0') and (running = '0')
report " 3. ready (state)";
assert (spw_do = '0') and (spw_so = '0')
report " 3. ready (SPW idle)";
-- Test 4: Start link; wait for NULL patterns.
linkstart <= '1';
rxroom <= "001111";
wait on started, connecting, running, spw_do, spw_so for 1 us;
assert (started = '1') and (running = '0')
report " 4. nullgen (started)";
if spw_so = '0' then
wait on started, connecting, running, spw_do, spw_so for 1.2 us;
end if;
assert (started = '1') and (connecting = '0') and (running = '0') and
(spw_do = '0') and (spw_so = '1')
report " 4. nullgen (SPW strobe)";
output_collect <= '1';
wait on started, connecting, running for (7.1 * outbit_period);
assert (started = '1') and (running = '0')
report " 4. nullgen (state 2)";
assert (output_ptr = 8) and (output_bits(0 to 7) = "01110100")
report " 4. nullgen (NULL 1)";
-- got the first NULL, wait for the second one ...
wait on started, connecting, running for (8.0 * outbit_period);
assert (started = '1') and (running = '0')
report " 4. nullgen (state 3)";
assert (output_ptr = 16) and (output_bits(8 to 15) = "01110100")
report " 4. nullgen (NULL 2)";
output_collect <= '0';
-- Test 5: Timeout in Started state.
wait on started, connecting, running, errany for 9.5 us - (15.0 * outbit_period);
assert (started = '1') and (running = '0') and (errany = '0')
report " 5. started_timeout (wait)";
wait on started, connecting, running, errany for 4 us;
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 5. started_timeout (trigger)";
wait for (3.1 * outbit_period + 20 * txclk_period);
assert (spw_do = '0') and (spw_so = '0')
report " 5. started_timeout (SPW to zero)";
-- Test 6: Start link; simulate NULL pattern; wait for FCT pattern.
wait on started, connecting, running, spw_so for 18 us - (3.1 * outbit_period + 20 * txclk_period);
assert (started = '0') and (connecting = '0') and (running = '0') and (spw_so = '0')
report " 6. fctgen (SPW idle)";
wait on started, connecting, running, spw_so for 2 us;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 6. fctgen (started)";
if spw_so = '0' then
wait on started, connecting, running, spw_do, spw_so for 1.2 us;
end if;
assert (spw_do = '0') and (spw_so = '1')
report " 6. fctgen (SPW strobe)";
output_collect <= '1';
input_pattern <= 1;
wait on started, connecting, running for 8 us;
assert (started = '0') and (connecting = '1') and (running = '0')
report " 6. fctgen (detect NULL)";
wait for (1.1 sec) / sys_clock_freq;
wait on started, connecting, running, errany for 12 us;
assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
report " 6. fctgen (connecting failed early)";
assert (output_ptr > 7) and (output_bits(0 to 7) = "01110100")
report " 6. fctgen (gen NULL)";
i := skip_null(output_bits, 0, output_ptr);
assert (i > 0) and (i + 11 < output_ptr) and (output_bits(i to (i+11)) = "010001110100")
report " 6. fctgen (gen FCT NULL)";
output_collect <= '0';
-- Test 7: Timeout in Connecting state.
wait on started, connecting, running, errany for 4 us;
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 7. connecting_timeout";
input_pattern <= 0;
wait until rising_edge(sysclk);
-- Test 8: Autostart link; simulate NULL and FCT; move to Run state; disconnect.
linkstart <= '0';
autostart <= '1';
rxroom <= "010000";
wait on started, connecting, running, errany for 50 us;
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 8. autostart (wait)";
output_collect <= '1';
input_pattern <= 1;
wait on started, connecting, running for 200 ns + 24 * inbit_period;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 8. autostart (Started)";
input_pattern <= 9;
wait on started, connecting, running for 1 us;
assert (started = '0') and (connecting = '1') and (running = '0')
report " 8. autostart (Connecting)";
wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
report " 8. autostart (Run)";
input_pattern <= 1;
txwrite <= '1';
if txrdy = '0' then
wait on running, errany, txrdy for (20 * outbit_period);
end if;
assert (running = '1') and (errany = '0') and (txrdy = '1')
report " 8. running (txrdy = 1)";
txwrite <= '0';
wait on running, errany for 50 us;
assert (running = '1') and (errany = '0')
report " 8. running stable";
assert output_bits(1 to 24) = "011101000100010001110100"
report " 8. NULL FCT FCT NULL";
output_collect <= '0';
linkdis <= '1';
wait on started, running, errany for (2.1 sec) / sys_clock_freq;
assert (started = '0') and (running = '0') and (errany = '0')
report " 8. link disable";
autostart <= '0';
linkdis <= '0';
input_pattern <= 0;
wait until rising_edge(sysclk);
-- Test 9: Start link until Run state; disconnect.
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
wait on started, connecting, running for 20 us;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 9. running_disconnect (Started)";
linkstart <= '0';
wait until rising_edge(sysclk);
input_pattern <= 9;
wait on started, connecting, running, errany for 20 * inbit_period;
assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
report " 9. running_disconnect (Connecting)";
wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
report " 9. running_disconnect (Run)";
input_pattern <= 0;
wait until input_idle = '1';
wait on started, connecting, running, errany for 1500 ns;
assert errdisc = '1'
report " 9. running_disconnect (errdisc = 1)";
if running = '1' then
wait on started, connecting, running for (1.1 sec) / sys_clock_freq;
end if;
assert (started = '0') and (connecting = '0') and (running = '0')
report " 9. running_disconnect (running = 0)";
wait until rising_edge(sysclk);
assert (started = '0') and (connecting = '0') and (running = '0') and (errany = '0')
report " 9. running_disconnect (reset)";
wait until rising_edge(sysclk);
-- Test 10: Junk signal before starting link.
autostart <= '1';
input_pattern <= 3;
wait on started, errany for 6 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (ignore noise)";
input_pattern <= 2;
wait on started, errany for 4 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (ignore FCT)";
input_pattern <= 0;
wait until input_idle = '1';
input_pattern <= 1; -- send NULL
wait until input_idle = '0';
input_pattern <= 3; -- send invalid pattern; spw should now reset
wait on started, errany for 8 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (hidden reset)";
input_pattern <= 1; -- send NULL
wait on started, errany for 10 us;
assert (started = '0') and (errany = '0')
report "10. junk signal (waiting)";
wait on started, errany for 10 us;
assert (started = '1') and (errany = '0')
report "10. junk signal (Started)";
autostart <= '0';
rst <= '1';
wait until rising_edge(sysclk);
rst <= '0';
wait until rising_edge(sysclk);
assert (started = '0') and (errany = '0')
report "10. junk signal (rst)";
wait until rising_edge(sysclk);
-- Test 11: Incoming EOP before first FCT.
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "11. unexpected EOP (Connecting)";
input_pattern <= 4;
linkstart <= '0';
wait on connecting, running, errany for 200 ns + 24 * inbit_period;
assert (connecting = '0') and (running = '0') and (errany = '0')
report "11. unexpected EOP (reset on EOP)";
input_pattern <= 0;
wait for (10 * outbit_period);
-- Test 12: Send and receive characters, time codes, abort on double ESC.
wait until falling_edge(sysclk);
linkstart <= '1';
wait on started, errany for 21 us;
assert (started = '1') and (errany = '0')
report "12. characters (Started)";
rxroom <= "001000";
input_pattern <= 1;
output_collect <= '1';
tick_in <= '1';
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "12. characters (Connecting)";
wait until output_ptr > 9 for 2 us;
input_pattern <= 5; -- FCT, TIME, 8 chars, NULLs
time_in <= "000111";
txwrite <= '1';
txflag <= '0';
txdata <= "01101100";
wait on connecting, running, errany for 200 ns + (24 * inbit_period);
assert (running = '1') and (errany = '0')
report "12. characters (Run)";
wait until rising_edge(sysclk);
assert (running = '1') and (errany = '0')
report "12. characters (running = 1)";
tick_in <= '0';
wait for 4 * outbit_period; -- wait until first FCT sent
rxroom <= "000111";
wait until txrdy = '1' for 200 ns + (20 * outbit_period);
assert (running = '1') and (txrdy = '1')
report "12. characters (txrdy = 1)";
wait on running, errany for 50 us + (80 * outbit_period);
assert (running = '1') and (errany = '0')
report "12. characters (stable)";
input_pattern <= 6; -- just ESC tokens
wait on running, errany for 200 ns + (32 * inbit_period);
assert erresc = '1'
report "12. characters (erresc = 1)";
wait until rising_edge(sysclk);
wait for 1 ns;
assert (started = '0') and (connecting = '0') and (running = '0')
report "12. characters (reset)";
assert (output_ptr > 8) and (output_bits(1 to 8) = "01110100")
report "12. characters (gen NULL 1)";
i := skip_null(output_bits, 1, output_ptr);
assert (i > 0) and (output_bits(i to (i+3)) = "0100")
report "12. characters (gen FCT)";
i := skip_null(output_bits, i + 4, output_ptr);
assert (i + 13 < output_ptr) and (output_bits(i to (i+13)) = "01111011100000")
report "12. characters (gen TimeCode)";
i := i + 14;
assert (i + 79 < output_ptr) and (output_bits(i to (i+79)) = "00001101101000110110100011011010001101101000110110100011011010001101101000110110")
report "12. characters (gen Data)";
i := i + 80;
assert (i + 7 < output_ptr) and (output_bits(i to (i+7)) = "01110100")
report "12. characters (gen NULL 2)";
assert (output_nchars > 0) and (output_chars(0) = "1000111000")
report "12. characters (got TimeCode)";
assert (output_nchars > 1) and (output_chars(1) = "0001010101")
report "12. characters (got byte 1)";
assert (output_nchars > 2) and (output_chars(2) = "0010101010")
report "12. characters (got byte 2)";
assert (output_nchars > 3) and (output_chars(3) = "0001010101")
report "12. characters (got byte 3)";
assert (output_nchars > 4) and (output_chars(4) = "0010101010")
report "12. characters (got byte 4)";
assert check_parity(output_bits, 1, output_ptr)
report "12. parity of output bits";
output_collect <= '0';
input_pattern <= 0;
txwrite <= '0';
linkstart <= '0';
wait for (20 * outbit_period);
-- Test 13: Send and receive EOP, EEP, abort on credit error.
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
output_collect <= '1';
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "13. eop, eep (Connecting)";
wait until output_ptr > 9 for 2 us;
input_pattern <= 7; -- FCT, NULL, NULL, EOP, EEP, NULLs
wait for (1.1 sec) / sys_clock_freq;
wait on connecting, running, errany for 12 us;
assert (running = '1') and (errany = '0')
report "13. eop, eep (Run)";
wait for 1 ns;
txwrite <= '1';
txflag <= '1';
txdata <= "01101100";
wait until rising_edge(sysclk) and txrdy = '1' for 1 us + (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 1)";
rxroom <= "000111" after 1 ns;
txdata <= "00000001" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for 1 us + (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 2)";
txdata <= "00000000" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 3)";
txdata <= "11111111" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 4)";
txdata <= "11111110" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 5)";
txdata <= "01010101" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 6)";
txdata <= "10101010" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 7)";
txdata <= "01010101" after 1 ns;
wait until rising_edge(sysclk) and txrdy = '1' for (14 * outbit_period);
assert (txrdy = '1') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 8)";
txdata <= "10101010" after 1 ns;
wait until rising_edge(sysclk) and (txrdy = '1') for (14 * outbit_period);
assert (txrdy = '0') and (running = '1') and (errany = '0')
report "13. eop, eep (txrdy 9)";
txwrite <= '0';
txflag <= '0';
wait on running, errany for (10 * outbit_period);
assert (running = '1') and (errany = '0')
report "13. eop, eep (flush out)";
input_pattern <= 2; -- FCT tokens
wait on running, errany for (80 * inbit_period);
assert errcred = '1'
report "13. eop, eep (errcred = 1)";
wait until running = '0';
assert (output_ptr > 8) and (output_bits(1 to 8) = "01110100")
report "13. eop, eep (gen NULL 1)";
i := skip_null(output_bits, 1, output_ptr);
assert (i > 0) and (output_bits(i to (i+3)) = "0100")
report "13. eop, eep (gen FCT)";
i := i + 4;
for j in 0 to 3 loop
i := skip_null(output_bits, i, output_ptr);
assert (i + 3 < output_ptr) and (output_bits(i+1 to (i+3)) = "101")
report "13. eop, eep (eop)";
i := skip_null(output_bits, i + 4, output_ptr);
assert (i + 3 < output_ptr) and (output_bits(i+1 to (i+3)) = "110")
report "13. eop, eep (eep)";
i := i + 4;
end loop;
assert (i + 8 < output_ptr) and (output_bits(i to (i+8)) = "111101000")
report "13. eop, eep (gen NULL 2)";
assert check_parity(output_bits, 1, output_ptr)
report "12. parity of output bits";
assert (output_nchars > 0) and (output_chars(0) = "0100000000")
report "13. eop, eep (got EOP)";
assert (output_nchars = 2) and (output_chars(1) = "0100000001")
report "13. eop, eep (got EEP)";
output_collect <= '0';
input_pattern <= 0;
linkstart <= '0';
wait until rising_edge(sysclk);
-- Test 14: Abort on parity error.
wait for 10 us;
assert spw_do = '0' and spw_so = '0'
report "14. output still babbling";
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
output_collect <= '1';
wait for 1 ns; -- ghdl is totally fucked up
wait on connecting, running, errany for 21 us;
assert (connecting = '1') and (errany = '0')
report "14. partity (Connecting)";
input_pattern <= 8; -- FCT, NULL, NULL, NULL, NULL, NULL, char, error
wait for (1.1 sec) / sys_clock_freq;
wait on running, errany for 12 us;
assert (running = '1') and (errany = '0')
report "14. parity (Run)";
wait on running, errany for 150 ns + (84 * inbit_period);
assert errpar = '1'
report "14. parity (errpar = 1)";
wait until running = '0';
assert (output_nchars = 1) and (output_chars(0) = "0001010101")
report "14. parity (received char)";
output_collect <= '0';
input_pattern <= 0;
linkstart <= '0';
wait until rising_edge(sysclk);
-- Test 15: start with wrong strobe polarity.
input_strobeflip <= '1';
linkstart <= '1';
rxroom <= "001000";
input_pattern <= 1;
wait on started, connecting, running for 20 us;
assert (started = '1') and (connecting = '0') and (running = '0')
report " 15. weird_strobe (Started)";
linkstart <= '0';
wait until rising_edge(sysclk);
input_pattern <= 9;
wait on started, connecting, running, errany for 20 * inbit_period;
assert (started = '0') and (connecting = '1') and (running = '0') and (errany = '0')
report " 15. weird_strobe (Connecting)";
wait on started, connecting, running, errany for 200 ns + 24 * inbit_period;
assert (started = '0') and (connecting = '0') and (running = '1') and (errany = '0')
report " 15. weird_strobe (Run)";
linkdis <= '1';
wait until rising_edge(sysclk);
input_pattern <= 0;
input_strobeflip <= '0';
wait until input_idle = '1';
linkdis <= '0';
wait until rising_edge(sysclk);
-- Test 16: start with wrong data polarity.
input_pattern <= 10;
linkstart <= '1';
rxroom <= "001111";
wait on started, connecting, running for 25 us;
assert (started = '1') and (running = '0')
report " 16. weird_data (started)";
if spw_so = '0' then
wait on started, connecting, running, spw_do, spw_so for 1.2 us;
end if;
assert (started = '1') and (connecting = '0') and (running = '0') and
(spw_do = '0') and (spw_so = '1')
report " 16. weird_data (SPW strobe)";
output_collect <= '1';
wait on started, connecting, running for (7.1 * outbit_period);
assert (started = '1') and (running = '0')
report " 16. weird_data (state 2)";
assert (output_ptr = 8) and (output_bits(0 to 7) = "01110100")
report " 16. weird_data (NULL 1)";
-- got the first NULL, wait for the second one ...
wait on started, connecting, running for (8.0 * outbit_period);
assert (started = '1') and (running = '0')
report " 16. weird_data (state 3)";
assert (output_ptr = 16) and (output_bits(8 to 15) = "01110100")
report " 16. weird_data (NULL 2)";
output_collect <= '0';
linkstart <= '0';
linkdis <= '1';
input_pattern <= 0;
wait until rising_edge(sysclk);
linkdis <= '0';
wait until rising_edge(sysclk);
-- Stop simulation
input_pattern <= 0;
wait for 100 us;
sys_clock_enable <= '0';
report "Done.";
wait;
end process;
end tb_arch;
| mit | 71567ead8d82f88671d7fc37ecdc6ab7 | 0.511283 | 3.733237 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/clock_tb.vhd | 1 | 9,559 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : clock_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-03-22
-- Last update: 2017-06-17
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top level test bench
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-22 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
--configuration testbench of clock is
-- for STRUCTURE
-- for all : cpu
-- use entity work.cpu(TEST);
-- end for;
-- end for;
--end configuration;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity clock_tb is
end clock_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
use work.tb_pkg.all;
architecture STRUCTURE of clock_tb is
component clock
port (
DDR_addr : INOUT std_logic_vector (14 DOWNTO 0);
DDR_ba : INOUT std_logic_vector (2 DOWNTO 0);
DDR_cas_n : INOUT std_logic;
DDR_ck_n : INOUT std_logic;
DDR_ck_p : INOUT std_logic;
DDR_cke : INOUT std_logic;
DDR_cs_n : INOUT std_logic;
DDR_dm : INOUT std_logic_vector (3 DOWNTO 0);
DDR_dq : INOUT std_logic_vector (31 DOWNTO 0);
DDR_dqs_n : INOUT std_logic_vector (3 DOWNTO 0);
DDR_dqs_p : INOUT std_logic_vector (3 DOWNTO 0);
DDR_odt : INOUT std_logic;
DDR_ras_n : INOUT std_logic;
DDR_reset_n : INOUT std_logic;
DDR_we_n : INOUT std_logic;
FIXED_IO_ddr_vrn : INOUT std_logic;
FIXED_IO_ddr_vrp : INOUT std_logic;
FIXED_IO_mio : INOUT std_logic_vector (53 DOWNTO 0);
FIXED_IO_ps_clk : INOUT std_logic;
FIXED_IO_ps_porb : INOUT std_logic;
FIXED_IO_ps_srstb : INOUT std_logic;
Vp_Vn_v_n : in std_logic;
Vp_Vn_v_p : in std_logic;
rtc_scl : INOUT std_logic;
rtc_sda : INOUT std_logic;
rtc_32khz : IN std_logic;
rtc_int_n : IN std_logic;
ocxo_ena : INOUT std_logic;
ocxo_clk : IN std_logic;
ocxo_scl : INOUT std_logic;
ocxo_sda : INOUT std_logic;
dac_sclk : OUT std_logic;
dac_cs_n : OUT std_logic;
dac_sin : OUT std_logic;
gps_ena : INOUT std_logic;
gps_rxd : IN std_logic;
gps_txd : OUT std_logic;
gps_3dfix : IN std_logic;
gps_1pps : IN std_logic;
temp_scl : INOUT std_logic;
temp_sda : INOUT std_logic;
temp_int1_n : IN std_logic;
temp_int2_n : IN std_logic;
disp_sclk : OUT std_logic;
disp_blank : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic;
fan_tach : IN std_logic;
fan_pwm : OUT std_logic;
gpio : INOUT std_logic_vector (7 DOWNTO 0)
);
end component;
SIGNAL DDR_addr : std_logic_vector (14 DOWNTO 0);
SIGNAL DDR_ba : std_logic_vector (2 DOWNTO 0);
SIGNAL DDR_cas_n : std_logic;
SIGNAL DDR_ck_n : std_logic;
SIGNAL DDR_ck_p : std_logic;
SIGNAL DDR_cke : std_logic;
SIGNAL DDR_cs_n : std_logic;
SIGNAL DDR_dm : std_logic_vector (3 DOWNTO 0);
SIGNAL DDR_dq : std_logic_vector (31 DOWNTO 0);
SIGNAL DDR_dqs_n : std_logic_vector (3 DOWNTO 0);
SIGNAL DDR_dqs_p : std_logic_vector (3 DOWNTO 0);
SIGNAL DDR_odt : std_logic;
SIGNAL DDR_ras_n : std_logic;
SIGNAL DDR_reset_n : std_logic;
SIGNAL DDR_we_n : std_logic;
signal FIXED_IO_ddr_vrn : std_logic;
signal FIXED_IO_ddr_vrp : std_logic;
signal FIXED_IO_mio : std_logic_vector (53 downto 0);
signal FIXED_IO_ps_clk : std_logic;
signal FIXED_IO_ps_porb : std_logic;
signal FIXED_IO_ps_srstb : std_logic;
SIGNAL Vp_Vn_v_n : std_logic;
SIGNAL Vp_Vn_v_p : std_logic;
SIGNAL rtc_scl : std_logic;
SIGNAL rtc_sda : std_logic;
SIGNAL rtc_32khz : std_logic;
SIGNAL rtc_int_n : std_logic;
SIGNAL ocxo_ena : std_logic;
SIGNAL ocxo_clk : std_logic;
SIGNAL ocxo_scl : std_logic;
SIGNAL ocxo_sda : std_logic;
SIGNAL dac_sclk : std_logic;
SIGNAL dac_cs_n : std_logic;
SIGNAL dac_sin : std_logic;
SIGNAL gps_ena : std_logic;
SIGNAL gps_rxd : std_logic;
SIGNAL gps_txd : std_logic;
SIGNAL gps_3dfix : std_logic;
SIGNAL gps_1pps : std_logic;
SIGNAL temp_scl : std_logic;
SIGNAL temp_sda : std_logic;
SIGNAL temp_int1_n : std_logic;
SIGNAL temp_int2_n : std_logic;
SIGNAL disp_sclk : std_logic;
SIGNAL disp_blank : std_logic;
SIGNAL disp_lat : std_logic;
SIGNAL disp_sin : std_logic;
SIGNAL fan_tach : std_logic;
SIGNAL fan_pwm : std_logic;
SIGNAL gpio : std_logic_vector (7 DOWNTO 0);
begin
fpga: clock
port map (
DDR_addr => DDR_addr,
DDR_ba => DDR_ba,
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm => DDR_dm,
DDR_dq => DDR_dq,
DDR_dqs_n => DDR_dqs_n,
DDR_dqs_p => DDR_dqs_p,
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio => FIXED_IO_mio,
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
Vp_Vn_v_n => Vp_Vn_v_n,
Vp_Vn_v_p => Vp_Vn_v_p,
rtc_scl => rtc_scl,
rtc_sda => rtc_sda,
rtc_32khz => rtc_32khz,
rtc_int_n => rtc_int_n,
ocxo_ena => ocxo_ena,
ocxo_clk => ocxo_clk,
ocxo_scl => ocxo_scl,
ocxo_sda => ocxo_sda,
dac_sclk => dac_sclk,
dac_cs_n => dac_cs_n,
dac_sin => dac_sin,
gps_ena => gps_ena,
gps_rxd => gps_rxd,
gps_txd => gps_txd,
gps_3dfix => gps_3dfix,
gps_1pps => gps_1pps,
temp_scl => temp_scl,
temp_sda => temp_sda,
temp_int1_n => temp_int1_n,
temp_int2_n => temp_int2_n,
disp_sclk => disp_sclk,
disp_blank => disp_blank,
disp_lat => disp_lat,
disp_sin => disp_sin,
fan_tach => fan_tach,
fan_pwm => fan_pwm,
gpio => gpio
);
ocxo_10MHZ: clk_gen(100 ns, 50, ocxo_clk);
process
begin
loop
fan_tach <= '1';
run_clk(ocxo_clk, 10000);
fan_tach <= '0';
run_clk(ocxo_clk, 20000);
fan_tach <= '1';
run_clk(ocxo_clk, 30000);
fan_tach <= '0';
run_clk(ocxo_clk, 40000);
end loop;
end process;
process
begin
gps_1pps <= '0';
run_clk(ocxo_clk, 10000);
loop
gps_1pps <= '1';
run_clk(ocxo_clk, 1);
gps_1pps <= '0';
run_clk(ocxo_clk, 9999999);
gps_1pps <= '1';
run_clk(ocxo_clk, 1);
gps_1pps <= '0';
run_clk(ocxo_clk, 9999989);
gps_1pps <= '1';
run_clk(ocxo_clk, 1);
gps_1pps <= '0';
run_clk(ocxo_clk, 10000019);
end loop;
end process;
gps_3dfix <= '0';
gps_rxd <= '0';
Vp_Vn_v_n <= '0';
Vp_Vn_v_p <= '0';
rtc_int_n <= '1';
temp_int1_n <= '1';
temp_int2_n <= '1';
end STRUCTURE;
| gpl-3.0 | ce8793120fee5545473c18598d23c3d1 | 0.428706 | 3.515631 | false | false | false | false |
ObKo/USBCore | Extra/sync_fifo.vhdl | 1 | 5,831 | --
-- USB Full-Speed/Hi-Speed Device Controller core - sync_fifo.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
-- Copyright (c) 2015 [email protected]
-- http://www.deathbylogic.com/2015/01/vhdl-first-word-fall-through-fifo/
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
entity sync_fifo is
generic (
constant FIFO_WIDTH : positive := 8;
constant FIFO_DEPTH : positive := 256;
constant PROG_FULL_VALUE: positive := 128
);
port (
clk : in std_logic;
rst : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(FIFO_WIDTH - 1 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(FIFO_WIDTH - 1 downto 0);
m_axis_tlast : out std_logic;
prog_full : out std_logic
);
end sync_fifo;
architecture sync_fifo of sync_fifo is
type FIFO_MEMORY is array (0 to FIFO_DEPTH - 1) of std_logic_vector (FIFO_WIDTH downto 0);
signal memory : FIFO_MEMORY;
subtype ADDRESS_TYPE is natural range 0 to FIFO_DEPTH - 1;
signal rd_addr : ADDRESS_TYPE;
signal wr_addr : ADDRESS_TYPE;
signal mem_we : std_logic;
signal mem_in : std_logic_vector(FIFO_WIDTH downto 0);
signal mem_out : std_logic_vector(FIFO_WIDTH downto 0);
signal buf_we : std_logic;
signal buf : std_logic_vector(FIFO_WIDTH downto 0);
signal buf_valid : std_logic;
signal full : std_logic;
signal empty : std_logic;
signal empty_d : std_logic;
signal empty_dd : std_logic;
signal looped : std_logic;
signal count : ADDRESS_TYPE;
signal first : std_logic;
begin
-- That structure guaranteed that dual-port BRAM will be inferred.
-- At least on Xilinx...
mem_we <= '1' when s_axis_tvalid = '1' and full = '0' else
'0';
mem_in <= s_axis_tlast & s_axis_tdata;
MEM_PROC: process(clk) is
begin
if rising_edge(clk) then
mem_out <= memory(rd_addr);
if mem_we = '1' then
memory(wr_addr) <= mem_in;
end if;
end if;
end process;
-- Sync empty signal with memory reading
EMPTY_OUT: process(clk) is
begin
if rising_edge(clk) then
empty_d <= empty;
empty_dd <= empty_d;
end if;
end process;
FWFT_BUF: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
buf_valid <= '0';
else
if buf_we = '1' then
buf <= mem_out;
buf_valid <= '1';
elsif buf_valid = '1' and m_axis_tready = '1' then
buf_valid <= '0';
end if;
end if;
end if;
end process;
FIFO_PROC: process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
wr_addr <= 0;
rd_addr <= 0;
looped <= '0';
else
if mem_we = '1' then
if wr_addr = FIFO_DEPTH - 1 then
wr_addr <= 0;
looped <= '1';
else
wr_addr <= wr_addr + 1;
end if;
end if;
if (empty = '0' and m_axis_tready = '1') or first = '1' then
if rd_addr = FIFO_DEPTH - 1 then
rd_addr <= 0;
looped <= '0';
else
rd_addr <= rd_addr + 1;
end if;
end if;
if buf_valid = '1' then
if count >= PROG_FULL_VALUE - 1 then
prog_full <= '1';
else
prog_full <= '0';
end if;
else
if count >= PROG_FULL_VALUE then
prog_full <= '1';
else
prog_full <= '0';
end if;
end if;
end if;
end if;
end process;
count <= FIFO_DEPTH - rd_addr + wr_addr when looped = '1' else
wr_addr - rd_addr;
first <= '1' when empty_d = '0' and buf_valid = '0' and empty_dd = '1' else
'0';
buf_we <= '1' when first = '1' else
'1' when empty_d = '0' and buf_valid = '0' and m_axis_tready = '0' else
'0';
full <= '1' when looped = '1' AND wr_addr = rd_addr else
'0';
empty <= '1' when looped = '0' AND wr_addr = rd_addr else
'0';
m_axis_tdata <= buf(FIFO_WIDTH - 1 downto 0) when buf_valid = '1' else
mem_out(FIFO_WIDTH - 1 downto 0);
m_axis_tlast <= buf(FIFO_WIDTH) when buf_valid = '1' else
mem_out(FIFO_WIDTH);
m_axis_tvalid <= (((NOT empty_dd) AND (NOT empty_d)) OR buf_valid);
s_axis_tready <= NOT full;
end sync_fifo;
| mit | b959ecf34e2cba7b28578cf997650d61 | 0.574173 | 3.540376 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/ld_arith_reg.vhd | 1 | 14,568 | -- Loadable arithmetic register.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: ld_arith_reg.vhd
-- Version:
--------------------------------------------------------------------------------
-- Description: A register that can be loaded and added to or subtracted from
-- (but not both). The width of the register is specified
-- with a generic. The load value and the arith
-- value, i.e. the value to be added (subtracted), may be of
-- lesser width than the register and may be
-- offset from the LSB position. (Uncovered positions
-- load or add (subtract) zero.) The register can be
-- reset, via the RST signal, to a freely selectable value.
-- The register is defined in terms of big-endian bit ordering.
--
-------------------------------------------------------------------------------
-- Structure:
--
-- ld_arith_reg.vhd
-------------------------------------------------------------------------------
-- Author: FO
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity ld_arith_reg is
generic (
------------------------------------------------------------------------
-- True if the arithmetic operation is add, false if subtract.
C_ADD_SUB_NOT : boolean := false;
------------------------------------------------------------------------
-- Width of the register.
C_REG_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Reset value. (No default, must be specified in the instantiation.)
C_RESET_VALUE : std_logic_vector;
------------------------------------------------------------------------
-- Width of the load data.
C_LD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB (toward more significant) of the load data.
C_LD_OFFSET : natural := 0;
------------------------------------------------------------------------
-- Width of the arithmetic data.
C_AD_WIDTH : natural := 8;
------------------------------------------------------------------------
-- Offset from the LSB of the arithmetic data.
C_AD_OFFSET : natural := 0
------------------------------------------------------------------------
-- Dependencies: (1) C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
-- (2) C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
------------------------------------------------------------------------
);
port (
CK : in std_logic;
RST : in std_logic; -- Reset to C_RESET_VALUE. (Overrides OP,LOAD)
Q : out std_logic_vector(0 to C_REG_WIDTH-1);
LD : in std_logic_vector(0 to C_LD_WIDTH-1); -- Load data.
AD : in std_logic_vector(0 to C_AD_WIDTH-1); -- Arith data.
LOAD : in std_logic; -- Enable for the load op, Q <= LD.
OP : in std_logic -- Enable for the arith op, Q <= Q + AD.
-- (Q <= Q - AD if C_ADD_SUB_NOT = false.)
-- (Overrrides LOAD.)
);
end ld_arith_reg;
library unisim;
use unisim.all;
library ieee;
use ieee.numeric_std.all;
architecture imp of ld_arith_reg is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
signal q_i,
q_i_ns,
xorcy_out,
gen_cry_kill_n : std_logic_vector(0 to C_REG_WIDTH-1);
signal cry : std_logic_vector(0 to C_REG_WIDTH);
begin
-- synthesis translate_off
assert C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_LD_WIDTH + C_LD_OFFSET <= C_REG_WIDTH"
severity error;
assert C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH
report "ld_arith_reg, constraint does not hold: " &
"C_AD_WIDTH + C_AD_OFFSET <= C_REG_WIDTH"
severity error;
-- synthesis translate_on
Q <= q_i;
cry(C_REG_WIDTH) <= '0' when C_ADD_SUB_NOT else OP;
PERBIT_GEN: for j in C_REG_WIDTH-1 downto 0 generate
signal load_bit, arith_bit, CE : std_logic;
begin
------------------------------------------------------------------------
-- Assign to load_bit either zero or the bit from input port LD.
------------------------------------------------------------------------
D_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_LD_OFFSET
or j < C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET generate
load_bit <= '0';
end generate;
D_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_LD_OFFSET
and j >= C_REG_WIDTH - C_LD_OFFSET - C_LD_WIDTH
generate
load_bit <= LD(j - (C_REG_WIDTH - C_LD_WIDTH - C_LD_OFFSET));
end generate;
------------------------------------------------------------------------
-- Assign to arith_bit either zero or the bit from input port AD.
------------------------------------------------------------------------
AD_ZERO_GEN: if j > C_REG_WIDTH - 1 - C_AD_OFFSET
or j < C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET
generate
arith_bit <= '0';
end generate;
AD_NON_ZERO_GEN: if j <= C_REG_WIDTH - 1 - C_AD_OFFSET
and j >= C_REG_WIDTH - C_AD_OFFSET - C_AD_WIDTH
generate
arith_bit <= AD(j - (C_REG_WIDTH - C_AD_WIDTH - C_AD_OFFSET));
end generate;
------------------------------------------------------------------------
-- LUT output generation.
-- Adder case
------------------------------------------------------------------------
Q_I_GEN_ADD: if C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Subtractor case
------------------------------------------------------------------------
Q_I_GEN_SUB: if not C_ADD_SUB_NOT generate
q_i_ns(j) <= q_i(j) xnor arith_bit when OP = '1' else load_bit;
end generate;
------------------------------------------------------------------------
-- Kill carries (borrows) for loads but
-- generate or kill carries (borrows) for add (sub).
------------------------------------------------------------------------
MULT_AND_i1: MULT_AND
port map (
LO => gen_cry_kill_n(j),
I1 => OP,
I0 => Q_i(j)
);
------------------------------------------------------------------------
-- Propagate the carry (borrow) out.
------------------------------------------------------------------------
MUXCY_i1: MUXCY
port map (
DI => gen_cry_kill_n(j),
CI => cry(j+1),
S => q_i_ns(j),
O => cry(j)
);
------------------------------------------------------------------------
-- Apply the effect of carry (borrow) in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => q_i_ns(j),
CI => cry(j+1),
O => xorcy_out(j)
);
CE <= LOAD or OP;
------------------------------------------------------------------------
-- Generate either a resettable or setable FF for bit j, depending
-- on C_RESET_VALUE at bit j.
------------------------------------------------------------------------
FF_RST0_GEN: if C_RESET_VALUE(j) = '0' generate
FDRE_i1: FDRE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
R => RST
);
end generate;
FF_RST1_GEN: if C_RESET_VALUE(j) = '1' generate
FDSE_i1: FDSE
port map (
Q => q_i(j),
C => CK,
CE => CE,
D => xorcy_out(j),
S => RST
);
end generate;
end generate;
end imp;
| gpl-3.0 | 804dbbcdde54f086a65a4db845d3281a | 0.382139 | 5.016529 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_pkg.vhd | 1 | 11,569 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE wr_fifo32to256_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT wr_fifo32to256_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT wr_fifo32to256_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT wr_fifo32to256_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT wr_fifo32to256_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT wr_fifo32to256_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT wr_fifo32to256_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END wr_fifo32to256_pkg;
PACKAGE BODY wr_fifo32to256_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END wr_fifo32to256_pkg;
| gpl-2.0 | 5b0c4dfe8c19576bf29187c72774d4dd | 0.507909 | 3.909767 | false | false | false | false |
ErikAndren/VGA3BitTestPattern | VgaPack.vhd | 1 | 1,627 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.Types.all;
package VgaPack is
constant hsync_end : positive := 95;
constant hdat_begin : positive := 143;
constant hdat_end : positive := 783;
constant hpixel_end : positive := 799;
--
constant vsync_end : positive := 1;
constant vdat_begin : positive := 34;
constant vdat_end : positive := 514;
constant vline_end : positive := 524;
constant VgaClkFreq : integer := 25000000;
constant VgaHFrontPorch : positive := 22;
constant VgaHVideo : positive := 640;
constant VgaHVideoW : positive := bits(VgaHVideo);
constant VgaHBackPorch : positive := 42;
--
constant VgaHPreHSync : positive := VgaHFrontPorch + VgaHVideo + VgaHBackPorch;
--
constant VgaHSync : positive := 96;
--
constant VgaHLine : positive := VgaHPreHSync + VgaHSync;
constant VgaHLineW : positive := bits(VgaHLine);
--
constant VgaVFrontPorch : positive := 30;
constant VgaVVideo : positive := 480;
constant VgaVVideoW : positive := bits(VgaVVideo);
constant VgaVBackPorch : positive := 12;
--
constant VgaVPreVSync : positive := VgaVFrontPorch + VgaVVideo + VgaVBackPorch;
--
constant VgaVSync : positive := 2;
--
constant VgaVLine : positive := VgaVPreVSync + VgaVSync;
constant HCnt : positive := VgaHLine; -- 800
constant HCntW : positive := bits(HCnt);
constant VCnt : positive := VgaVLine; -- 524
constant VCntW : positive := bits(VCnt);
end package;
package body VgaPack is
end package body VgaPack; | gpl-2.0 | 2f37b4269ab767637cb2a888b87dba15 | 0.656423 | 3.354639 | false | false | false | false |
peteut/nvc | test/simp/issue331.vhd | 1 | 2,144 | -- test_ng.vhd
entity TEST_NG is
generic (
INFO_BITS : integer := 1;
INFO_1_VAL : integer := 0
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
O_INFO_1 : out bit_vector(INFO_BITS-1 downto 0)
);
end TEST_NG;
architecture MODEL of TEST_NG is
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
INFO_0 : INFO_RANGE_TYPE;
INFO_1 : INFO_RANGE_TYPE;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
d_pos := d_pos + BITS;
end procedure;
begin
d_pos := 0;
v.DATA_LO := d_pos;
SET_INFO_RANGE(v.INFO_0, INFO_BITS);
if (INFO_1_VAL /= 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
v.DATA_HI := d_pos - 1;
if (INFO_1_VAL = 0) then
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
end if;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal i_data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
begin
i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO) <= I_INFO_0;
O_INFO_0 <= i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO);
INFO_1: if (INFO_1_VAL /= 0) generate
i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO) <= I_INFO_1;
O_INFO_1 <= i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO);
end generate;
end MODEL;
| gpl-3.0 | 59fb329ae66504316a6c0612493c7b0c | 0.529384 | 3.134503 | false | true | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/shifter.vhd | 1 | 2,137 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity shifter is
port ( clk : in std_logic;
input : in std_logic_vector(15 downto 0);
enable : in std_logic;
shift_over_flag : out std_logic; ---for pipelined shifter
active_output: out std_logic_vector(31 downto 0)
);
end shifter;
architecture Behavioral of shifter is
signal acticv_mul_en : std_logic ;
signal input_temp : std_logic_vector(15 downto 0);
constant const_one : std_logic_vector(15 downto 0) := "0001000000000000";
--signal shifted_output : std_logic_vector(15 downto 0);
signal shifted_output_temp : std_logic_vector(15 downto 0);
COMPONENT acticv_mul
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
begin
acticv_mul_map : acticv_mul
port map (clk,acticv_mul_en,shifted_output_temp,input_temp,const_one,active_output);
shifter : process (clk,enable)
variable temp_reg: std_logic_vector(15 downto 0) := (Others => '0');
variable shift_counter: integer := 0;
begin
if(enable = '0') then
temp_reg := (others => '0');
shift_counter := 0;
shifted_output_temp <= (others => '0');
input_temp <= (others => '0');
shift_over_flag <= '0';
acticv_mul_en <= '0';
else
if rising_edge(clk) then
acticv_mul_en <= '0';
if (shift_counter = 0) then
temp_reg := input;
input_temp <= input;
elsif (shift_counter > 2) then --- The activation function is approximated as
shifted_output_temp <= temp_reg; --- x(1+0.25*x) . The term 0.25*x is done by
temp_reg := input; --- shifting x by 4 times
if shift_counter > 4 then
acticv_mul_en <= '0';
shift_over_flag <= '1';
else
acticv_mul_en <= '1';
end if;
else
for i in 0 to 13 loop
temp_reg(i) := temp_reg(i+1);
end loop;
temp_reg(14) := '0';
end if;
shift_counter := shift_counter + 1;
end if;
end if;
end process;
end Behavioral;
| bsd-2-clause | a4bc348ee75b36ad7c5969405461e72d | 0.61956 | 2.992997 | false | false | false | false |
ObKo/USBCore | Extra/blk_ep_out_ctl.vhdl | 1 | 3,966 | --
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_out_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity blk_ep_out_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
axis_tdata : out std_logic_vector(7 downto 0);
axis_tvalid : out std_logic;
axis_tready : in std_logic;
axis_tlast : out std_logic
);
end blk_ep_out_ctl;
architecture blk_ep_out_ctl of blk_ep_out_ctl is
component blk_out_fifo
port (
m_aclk : in std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
axis_prog_full : out std_logic
);
end component;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal prog_full : std_logic;
begin
FULL_LATCH: process(usb_clk) is
begin
if rising_edge(usb_clk) then
blk_xfer_out_ready_read <= NOT prog_full;
end if;
end process;
ASYNC: if USE_ASYNC_FIFO generate
FIFO: blk_out_fifo
port map (
m_aclk => axis_clk,
s_aclk => usb_clk,
s_aresetn => NOT rst,
s_axis_tvalid => blk_xfer_out_data_valid,
s_axis_tready => open,
s_axis_tdata => blk_xfer_out_data,
m_axis_tvalid => axis_tvalid,
m_axis_tready => axis_tready,
m_axis_tdata => axis_tdata,
axis_prog_full => prog_full
);
end generate;
SYNC: if not USE_ASYNC_FIFO generate
FIFO: sync_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => 1024,
PROG_FULL_VALUE => 960
)
port map (
clk => usb_clk,
rst => rst,
s_axis_tvalid => blk_xfer_out_data_valid,
s_axis_tready => open,
s_axis_tdata => blk_xfer_out_data,
s_axis_tlast => '0',
m_axis_tvalid => axis_tvalid,
m_axis_tready => axis_tready,
m_axis_tdata => axis_tdata,
m_axis_tlast => open,
prog_full => prog_full
);
end generate;
axis_tlast <= '0';
end blk_ep_out_ctl; | mit | 216827e9811fe3664b9b0531bce04cee | 0.614725 | 3.488127 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_12/Lab_12_2/DC7.vhd | 1 | 902 | Library IEEE;
use IEEE.std_logic_1164.all;
entity DC7 is
port( A: in std_logic_vector (3 downto 0);
Q: out std_logic_vector (6 downto 0));
end entity DC7;
architecture Behave of DC7 is
begin
process (A)
begin
case A is
when "0000" => Q <= "0000001";
when "0001" => Q <= "1001111";
when "0010" => Q <= "0010011";
when "0011" => Q <= "0000110";
when "0100" => Q <= "1001100";
when "0101" => Q <= "0100100";
when "0110" => Q <= "0100000";
when "0111" => Q <= "0001111";
when "1000" => Q <= "0000000";
when "1001" => Q <= "0000100";
when "1010" => Q <= "0001000";
when "1011" => Q <= "1100000";
when "1100" => Q <= "1110010";
when "1101" => Q <= "1000010";
when "1110" => Q <= "0110000";
when "1111" => Q <= "0111000";
when others => Q <= "0000001";
end case;
end process;
end Behave; | gpl-2.0 | c74a51b63ca11dd8cf460677e10ace92 | 0.511086 | 2.938111 | false | false | false | false |
peteut/nvc | test/elab/issue305.vhd | 2 | 1,331 | -- a_ng.vhd
package TEST_TYPES is
type WIDTH_TYPE is record
DATA : integer;
end record;
end package;
use work.TEST_TYPES.all;
entity TEST_SUB is
generic (
WIDTH : WIDTH_TYPE
);
port (
DATA_I : in bit_vector(WIDTH.DATA-1 downto 0);
DATA_O : out bit_vector(WIDTH.DATA-1 downto 0)
);
end TEST_SUB;
architecture MODEL of TEST_SUB is
begin
DATA_O <= DATA_I;
end MODEL;
use work.TEST_TYPES.all;
entity TEST_NG is
end TEST_NG;
architecture MODEL of TEST_NG is
constant WIDTH : WIDTH_TYPE := (DATA => 8); -- Could not fold this
signal DATA_I : bit_vector(WIDTH.DATA-1 downto 0);
signal DATA_O : bit_vector(WIDTH.DATA-1 downto 0);
begin
DUT: entity WORK.TEST_SUB
generic map (WIDTH => WIDTH)
port map (DATA_I => DATA_I, DATA_O => DATA_O);
process begin
DATA_I <= "00000000";
wait for 10 ns;
assert(DATA_O /= "00000000") report "OK." severity NOTE;
assert(DATA_O = "00000000") report "NG." severity ERROR;
DATA_I <= "00000001";
wait for 10 ns;
assert(DATA_O /= "00000001") report "OK." severity NOTE;
assert(DATA_O = "00000001") report "NG." severity ERROR;
assert FALSE report "Simulation complete." severity FAILURE;
end process;
end MODEL;
| gpl-3.0 | 264cf83eb32a7a54bd2613c2c061dacd | 0.60556 | 3.439276 | false | true | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_synth.vhd | 1 | 9,389 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_sfifo_15x128_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF k7_sfifo_15x128_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL prog_empty : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(128-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: k7_sfifo_15x128_dgen
GENERIC MAP (
C_DIN_WIDTH => 128,
C_DOUT_WIDTH => 128,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: k7_sfifo_15x128_dverif
GENERIC MAP (
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: k7_sfifo_15x128_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 128,
C_DIN_WIDTH => 128,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
k7_sfifo_15x128_inst : k7_sfifo_15x128_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | 3186d713c76deac265cd4fb1f919c83f | 0.45564 | 4.17846 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/async_counters.vhd | 1 | 30,218 | -------------------------------------------------------------------------------
-- async_counters.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------
-- Filename: async_counters.vhd
-- Version: v1.00.a
-- Description:This file contains all of the counters for the EPC Async design
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: -Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library axi_epc_v2_0;
use axi_epc_v2_0.ld_arith_reg;
-------------------------------------------------------------------------------
-- Definition of Ports:
-------------------------------------------------------------------------------
------------Declaration of GENERICs which will go directly counters------------
-------------------------------------------------------------------------------
--C_ADDR_TH_CNT_WIDTH -- Address hold time counter data width
--C_ADDR_DATA_CS_TH_CNT_WIDTH --Address/Data/Chip select hold counter data width
--C_CONTROL_CNT_WIDTH -- Control signal counter width
--C_DEV_VALID_CNT_WIDTH -- Device valid signal width
--C_DEV_RDY_CNT_WIDTH -- Control siganl assert activate counter width
--C_ADS_CNT_WIDTH -- Address Strobe counter width
--C_WR_REC_NM_CNT_WIDTH --Non Muxed Recovery signal assert(wr)activate cntr wdth
--C_RD_REC_NM_CNT_WIDTH --Non Muxed Recovery signal assert(rd)activate cntr wdth
--C_WR_REC_M_CNT_WIDTH -- Muxed Recovery siganl assert(write)activate cntr wdth
--C_RD_REC_M_CNT_WIDTH -- Muxed Recovery siganl assert(read)activate cntr wdth
------------------------------------------------------------------------------
--***All inputs***
------------------------------------------------------------------------------
-- Taddr_hold_count -- address counter width
-- Taddr_data_cs_hold_count -- address data chip select hold count
-- Tcontrol_width_data -- control width count
-- Tdev_valid_data -- device valid count
-- Tdevrdy_width_data -- device ready count
-- Tads_data -- address strobe/chip select/data set up count
-- Twr_recovery_muxed_data -- muxed write recovery count
-- Twr_recovery_non_muxed_data -- non muxed write recovery count
-- Trd_recovery_muxed_data -- muxed read recovery count
-- Trd_recovery_non_muxed_data -- non muxed read recovery count
-- Taddr_hold_load -- Load the counter to hold the address lines
-- Tdata_hold_load -- Load the counter to hold the data lines
-- Tcontrol_load -- Load the counter to maintain the control signal
-- Tdev_valid_load -- Load the device valid counter
-- Tdev_rdy_load -- Load the device ready counter
-- Tads_load -- Load the address strobe counter
-- Twr_recovery_load -- Load the write recovery counter
-- Trd_recovery_load -- Load the read recovery counter
-- Taddr_hold_load_ce -- Address hold load counter enable
-- Tdata_hold_load_ce -- Data hold load counter enable
-- Tcontrol_load_ce -- Control load counter enable
-- Tdev_valid_load_ce -- Device valid load counter enable
-- Tdev_rdy_load_ce -- Device ready load counter enable
-- Tads_load_ce -- Address Strobe load counter enable
-- Twr_muxed_recovery_load_ce -- Muxed Write recovery load counter enable
-- Trd_muxed_recovery_load_ce -- Muxed Read recovery load counter enable
-- Twr_non_muxed_recovery_load_ce --Non muxed Write recovery load counter enable
-- Trd_non_muxed_recovery_load_ce --Non muxed read recovery load counter enable
------------------------------------------------------------------------------
-- ***All outputs***
------------------------------------------------------------------------------
--Taddr_hold_cnt -- output of address hold count
--Tcontrol_wdth_cnt -- output of control width count
--Tdevrdy_wdth_cnt -- output of device ready count
--Tdev_valid_cnt -- output of device valid count
--Tads_cnt -- output of address-strobe/data,adress set up count
--Taddr_data_cs_hold_cnt -- output of address,data,chip select hold count
--Twr_muxed_rec_cnt -- output of muxed write recovery count
--Trd_muxed_rec_cnt -- output of muxed read recovery count
--Twr_non_muxed_rec_cnt -- output of non muxed write recovery count
--Trd_non_muxed_rec_cnt -- output of non muxed read recovery count
------------------------------------------------------------------------------
-- ***Clocks and reset***
------------------------------------------------------------------------------
-- Clk -- AXI Clk
-- Rst -- AXI Reset
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity async_counters is
generic
(
C_ADDR_TH_CNT_WIDTH : integer;
C_ADDR_DATA_CS_TH_CNT_WIDTH : integer;
C_CONTROL_CNT_WIDTH : integer;
C_DEV_VALID_CNT_WIDTH : integer;
C_DEV_RDY_CNT_WIDTH : integer;
C_ADS_CNT_WIDTH : integer;
C_WR_REC_NM_CNT_WIDTH : integer;
C_RD_REC_NM_CNT_WIDTH : integer;
C_WR_REC_M_CNT_WIDTH : integer;
C_RD_REC_M_CNT_WIDTH : integer
);
port
(
-- inputs from asynch_cntrl
Taddr_hold_count : in std_logic_vector(0 to C_ADDR_TH_CNT_WIDTH-1);
Taddr_data_cs_hold_count: in std_logic_vector
(0 to C_ADDR_DATA_CS_TH_CNT_WIDTH-1);
Tcontrol_width_data : in std_logic_vector(0 to C_CONTROL_CNT_WIDTH-1);
Tdev_valid_data : in std_logic_vector(0 to C_DEV_VALID_CNT_WIDTH-1);
Tdevrdy_width_data : in std_logic_vector(0 to C_DEV_RDY_CNT_WIDTH-1);
Tads_data : in std_logic_vector(0 to C_ADS_CNT_WIDTH-1);
Twr_recovery_muxed_data : in std_logic_vector
(0 to C_WR_REC_M_CNT_WIDTH-1);
Twr_recovery_non_muxed_data : in std_logic_vector
(0 to C_WR_REC_NM_CNT_WIDTH-1);
Trd_recovery_muxed_data : in std_logic_vector
(0 to C_RD_REC_M_CNT_WIDTH-1);
Trd_recovery_non_muxed_data : in std_logic_vector
(0 to C_RD_REC_NM_CNT_WIDTH-1);
Taddr_hold_cnt : out std_logic_vector(0 to C_ADDR_TH_CNT_WIDTH-1);
Tcontrol_wdth_cnt : out std_logic_vector(0 to C_CONTROL_CNT_WIDTH-1);
Tdevrdy_wdth_cnt : out std_logic_vector(0 to C_DEV_RDY_CNT_WIDTH-1);
Twr_muxed_rec_cnt : out std_logic_vector(0 to C_WR_REC_M_CNT_WIDTH-1);
Trd_muxed_rec_cnt : out std_logic_vector(0 to C_RD_REC_M_CNT_WIDTH-1);
Twr_non_muxed_rec_cnt : out std_logic_vector(0 to C_WR_REC_NM_CNT_WIDTH-1);
Trd_non_muxed_rec_cnt : out std_logic_vector(0 to C_RD_REC_NM_CNT_WIDTH-1);
Tdev_valid_cnt : out std_logic_vector(0 to C_DEV_VALID_CNT_WIDTH-1);
Tads_cnt : out std_logic_vector(0 to C_ADS_CNT_WIDTH-1);
Taddr_data_cs_hold_cnt : out std_logic_vector
(0 to C_ADDR_DATA_CS_TH_CNT_WIDTH-1);
-- inputs from asynch_statemachine
Taddr_hold_load : in std_logic;
Tdata_hold_load : in std_logic;
Tcontrol_load : in std_logic;
Tdev_valid_load : in std_logic;
Tdev_rdy_load : in std_logic;
Tads_load : in std_logic;
Twr_recovery_load : in std_logic;
Trd_recovery_load : in std_logic;
Taddr_hold_load_ce : in std_logic;
Tdata_hold_load_ce : in std_logic;
Tcontrol_load_ce : in std_logic;
Tdev_valid_load_ce : in std_logic;
Tdev_rdy_load_ce : in std_logic;
Tads_load_ce : in std_logic;
Twr_muxed_recovery_load_ce : in std_logic;
Trd_muxed_recovery_load_ce : in std_logic;
Twr_non_muxed_recovery_load_ce: in std_logic;
Trd_non_muxed_recovery_load_ce: in std_logic;
-- Clocks and reset
Clk :in std_logic;
Rst :in std_logic
);
end entity async_counters;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture imp of async_counters is
------------------------------------------------------------------------------
-- Constant declarations
------------------------------------------------------------------------------
-- reset values
-- addr hold
constant ADDR_TH_CNTR2_RST: std_logic_vector(0 to C_ADDR_TH_CNT_WIDTH-1)
:= (others => '0');
-- control hold
constant CONTROL_TH_CNTR3_RST: std_logic_vector(0 to C_CONTROL_CNT_WIDTH-1)
:= (others => '0');
-- dev rdy pulse width
constant DEV_RDY_CNTR4_RST: std_logic_vector(0 to C_DEV_RDY_CNT_WIDTH-1)
:= (others => '0');
-- device set up pulse width
constant DEV_VALID_CNTR7_RST: std_logic_vector(0 to C_DEV_VALID_CNT_WIDTH-1)
:= (others => '0');
-- address strobe counter
constant ADS_CNTR8_RST: std_logic_vector(0 to C_ADS_CNT_WIDTH-1)
:= (others => '0');
-- address,data, chip select hold width
constant ADDR_DATA_CS_TH_CNTR12_RST
:std_logic_vector(0 to C_ADDR_DATA_CS_TH_CNT_WIDTH-1)
:= (others => '0');
-- read recovery pulse width
constant RD_MUXED_RECOVERY_CNTR9_RST:
std_logic_vector(0 to C_RD_REC_M_CNT_WIDTH-1)
:= (others => '0');
constant RD_NON_MUXED_RECOVERY_CNTR9_RST:
std_logic_vector(0 to C_RD_REC_NM_CNT_WIDTH-1)
:= (others => '0');
-- write recovery pulse width
constant WR_MUXED_RECOVERY_CNTR5_RST:
std_logic_vector(0 to C_WR_REC_M_CNT_WIDTH-1)
:= (others => '0');
constant WR_NON_MUXED_RECOVERY_CNTR5_RST:
std_logic_vector(0 to C_WR_REC_NM_CNT_WIDTH-1)
:= (others => '0');
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
-- Architecture start
-----------------------------------------------------------------------------
begin
-- Note: All the counters are down counters
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
--LD_ARITH_REG_I_CNTR2: The max time counter for address hold
------------------------------------------------------------------------------
LD_ARITH_REG_I_CNTR2: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_ADDR_TH_CNT_WIDTH,
C_RESET_VALUE => ADDR_TH_CNTR2_RST,
C_LD_WIDTH => C_ADDR_TH_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Taddr_hold_cnt,
LD => Taddr_hold_count,
AD => "1",
LOAD => Taddr_hold_load,
OP => Taddr_hold_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
--LD_ARITH_REG_I_CNTR3: The max time counter for control width
------------------------------------------------------------------------------
LD_ARITH_REG_I_CNTR3: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_CONTROL_CNT_WIDTH,
C_RESET_VALUE => CONTROL_TH_CNTR3_RST,
C_LD_WIDTH => C_CONTROL_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Tcontrol_wdth_cnt,
LD => Tcontrol_width_data,
AD => "1",
LOAD => Tcontrol_load,
OP => Tcontrol_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
--LD_ARITH_REG_I_CNTR4: The max time counter till device become ready for
--communication
-----------------------------------------------------------------------------
--The counter is a down counter and will be loaded with initial values.
--The initial value will be loaded from the asynch_cntl level file.
--these values are modified as per the device requirements.
--Once the counter reaches to '1', then disable signal will be activated which
--in turn "deactivates" the control signals in the state machine.Ulitmately this
--becomes the max time counter till device responds
------------------------------------------------------------------------------
LD_ARITH_REG_I_CNTR4: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_DEV_RDY_CNT_WIDTH,
C_RESET_VALUE => DEV_RDY_CNTR4_RST,
C_LD_WIDTH => C_DEV_RDY_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Tdevrdy_wdth_cnt,
LD => Tdevrdy_width_data,
AD => "1",
LOAD => Tdev_rdy_load,
OP => Tdev_rdy_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
-- LD_ARITH_REG_I_CNTR7: This counter is used to measure period for
-- device in to valid state
------------------------------------------------------------------------------
LD_ARITH_REG_I_CNTR7: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_DEV_VALID_CNT_WIDTH,
C_RESET_VALUE => DEV_VALID_CNTR7_RST,
C_LD_WIDTH => C_DEV_VALID_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Tdev_valid_cnt,
LD => Tdev_valid_data,
AD => "1",
LOAD => Tdev_valid_load,
OP => Tdev_valid_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
-- LD_ARITH_REG_I_CNTR8: This counter is used to measure period for
-- address strobe
------------------------------------------------------------------------------
LD_ARITH_REG_I_CNTR8: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_ADS_CNT_WIDTH,
C_RESET_VALUE => ADS_CNTR8_RST,
C_LD_WIDTH => C_ADS_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Tads_cnt,
LD => Tads_data,
AD => "1",
LOAD => Tads_load,
OP => Tads_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
-------------------------------------------------------------------------------
--LD_ARITH_REG_I_CNTR12: The max time counter for address,data,chip select hold
-------------------------------------------------------------------------------
LD_ARITH_REG_I_CNTR12: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_ADDR_DATA_CS_TH_CNT_WIDTH,
C_RESET_VALUE => ADDR_DATA_CS_TH_CNTR12_RST,
C_LD_WIDTH => C_ADDR_DATA_CS_TH_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Taddr_data_cs_hold_cnt,
LD => Taddr_data_cs_hold_count,
AD => "1",
LOAD => Tdata_hold_load,
OP => Tdata_hold_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
--LD_ARITH_REG_I_MUXED_CNTR5: The max time counter for the write muxed recovery.
------------------------------------------------------------------------------
--This counter enabled the write recovery non-muxed time period data is loaded
--when write recovery muxed signal is asserted.
--The counter is a down counter and will be loaded with initial values.
--The initial value will be loaded from the asynch_cntl level file. these
--values are modified as per the device requirements.
--Once the counter reaches to '1', then assert signal will be activated
--Ulitmately this becomes the max time counter for the next transition to start
------------------------------------------------------------------------------
LD_ARITH_REG_I_MUXED_CNTR5: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_WR_REC_M_CNT_WIDTH,
C_RESET_VALUE => WR_MUXED_RECOVERY_CNTR5_RST,
C_LD_WIDTH => C_WR_REC_M_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Twr_muxed_rec_cnt,
LD => Twr_recovery_muxed_data,
AD => "1",
LOAD => Twr_recovery_load,
OP => Twr_muxed_recovery_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
--LD_ARITH_REG_I_NON_MUXED_CNTR5: The max time counter for the write non-muxed
-- recovery.
------------------------------------------------------------------------------
--This counter enabled the write recovery non-muxed time period data is loaded
--when write recovery non-muxed signal is asserted.
--The counter is a down counter and will be loaded with initial values.
--The initial value will be loaded from the asynch_cntl level file. these
--values are modified as per the device requirements.
--Once the counter reaches to '1', then assert signal will be activated
--Ulitmately this becomes the max time counter for the next transition to start
------------------------------------------------------------------------------
LD_ARITH_REG_I_NON_MUXED_CNTR5: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_WR_REC_NM_CNT_WIDTH,
C_RESET_VALUE => WR_NON_MUXED_RECOVERY_CNTR5_RST,
C_LD_WIDTH => C_WR_REC_NM_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Twr_non_muxed_rec_cnt,
LD => Twr_recovery_non_muxed_data,
AD => "1",
LOAD => Twr_recovery_load,
OP => Twr_non_muxed_recovery_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
-- LD_ARITH_REG_I_MUXED_CNTR9: This counter is used to measure period for
-- read muxed recovery period
------------------------------------------------------------------------------
--This counter enabled the read recovery muxed time period data is loaded
--when read recovery muxed signal is asserted.
--The counter is a down counter and will be loaded with initial values.
--The initial value will be loaded from the asynch_cntl level file. these
--values are modified as per the device requirements.
--Once the counter reaches to '1', then assert signal will be activated
--Ulitmately this becomes the max time counter for the next transition to start
--LD_ARITH_REG_I_MUXED_CNTR9: The max time counter for the read muxed recovery
-------------------------------------------------------------------------------
LD_ARITH_REG_I_MUXED_CNTR9: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_RD_REC_M_CNT_WIDTH,
C_RESET_VALUE => RD_MUXED_RECOVERY_CNTR9_RST,
C_LD_WIDTH => C_RD_REC_M_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Trd_muxed_rec_cnt,
LD => Trd_recovery_muxed_data,
AD => "1",
LOAD => Trd_recovery_load,
OP => Trd_muxed_recovery_load_ce
);
------------------------------------------------------------------------------
-- component instantiation
------------------------------------------------------------------------------
-- LD_ARITH_REG_I_NON_MUXED_CNTR9: This counter is used to measure period for
-- read non muxed recovery period
------------------------------------------------------------------------------
--This counter enabled the read recovery non muxed time period data is loaded
--when read recovery non-muxed signal is asserted.
--The counter is a down counter and will be loaded with initial values.
--The initial value will be loaded from the asynch_cntl level file. these
--values are modified as per the device requirements.
--Once the counter reaches to '1', then assert signal will be activated
--Ulitmately this becomes the max time counter for the next transition to start
--LD_ARITH_REG_I_NON_MUXED_CNTR9: The max time counter for the read
--non muxed recovery
-------------------------------------------------------------------------------
LD_ARITH_REG_I_NON_MUXED_CNTR9: entity axi_epc_v2_0.ld_arith_reg
generic map (
C_ADD_SUB_NOT => false,
C_REG_WIDTH => C_RD_REC_NM_CNT_WIDTH,
C_RESET_VALUE => RD_NON_MUXED_RECOVERY_CNTR9_RST,
C_LD_WIDTH => C_RD_REC_NM_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map (
CK => Clk,
RST => Rst,
Q => Trd_non_muxed_rec_cnt,
LD => Trd_recovery_non_muxed_data,
AD => "1",
LOAD => Trd_recovery_load,
OP => Trd_non_muxed_recovery_load_ce
);
------------------------------------------------------------------------------
end imp;
------------------------------------------------------------------------------
-- End of async_counters.vhd file
------------------------------------------------------------------------------
| gpl-3.0 | be21dcbbbde48c9c1fc739014854e979 | 0.431564 | 4.554333 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/hdl/axistream_spw_lite_v1_0.vhd | 1 | 20,232 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.spwpkg.all;
package axistream_spw_lite_v1_0_pkg is
component axistream_spw_lite_v1_0 is
generic (
sysfreq : integer := 100000000;
txclkfreq : integer := 0;
rximpl_fast : boolean := false; -- true to use rx_clk
tximpl_fast : boolean := false; -- true to use tx_clk
rxchunk_fast : integer range 1 to 4 := 1;
rxfifosize_bits : integer range 6 to 14 := 14; -- 14 (16 kByte)
txfifosize_bits : integer range 2 to 14 := 14; -- 14 (16 kByte)
txdivcnt : std_logic_vector(7 downto 0) := x"01" -- spw rate will be sysfreq / 2
);
port (
aclk : in std_logic;
aresetn : in std_logic;
rx_clk : in std_logic;
tx_clk : in std_logic;
spw_di : in std_logic;
spw_si : in std_logic;
spw_do : out std_logic;
spw_so : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tlast : in std_logic;
s_axis_tready : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tlast : out std_logic;
rx_error : out std_logic
);
end component axistream_spw_lite_v1_0;
end package axistream_spw_lite_v1_0_pkg;
-------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.spwpkg.all;
use work.axistream_spw_lite_v1_0_pkg.all;
entity axistream_spw_lite_v1_0 is
generic (
-- System clock frequency in Hz.
-- This must be set to the frequency of "clk". It is used to setup
-- counters for reset timing, disconnect timeout and to transmit
-- at 10 Mbit/s during the link handshake.
sysfreq : integer := 100000000;
-- Transmit clock frequency in Hz (only if tximpl = impl_fast).
-- This must be set to the frequency of "txclk". It is used to
-- transmit at 10 Mbit/s during the link handshake.
txclkfreq : integer := 0;
-- Maximum number of bits received per system clock
-- (must be 1 in case of impl_generic).
rxchunk_fast : integer range 1 to 4 := 1;
-- Size of the receive FIFO as the 2-logarithm of the number of bytes.
-- Must be at least 6 (64 bytes).
rxfifosize_bits : integer range 6 to 14 := 11; -- 11 (2 kByte)
-- Size of the transmit FIFO as the 2-logarithm of the number of bytes.
txfifosize_bits : integer range 2 to 14 := 11; -- 11 (2 kByte)
-- Scaling factor minus 1, used to scale the transmit base clock into
-- the transmission bit rate. The system clock (for impl_generic) or
-- the txclk (for impl_fast) is divided by (unsigned(txdivcnt) + 1).
-- Changing this signal will immediately change the transmission rate.
-- During link setup, the transmission rate is always 10 Mbit/s.
txdivcnt : std_logic_vector(7 downto 0) := x"04";
rximpl_fast : boolean := false; -- true to use rx_clk
tximpl_fast : boolean := false -- true to use tx_clk
);
port (
aclk : in std_logic;
aresetn : in std_logic;
rx_clk : in std_logic;
tx_clk : in std_logic;
spw_di : in std_logic;
spw_si : in std_logic;
spw_do : out std_logic;
spw_so : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tvalid : in std_logic;
s_axis_tlast : in std_logic;
s_axis_tready : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tlast : out std_logic;
rx_error : out std_logic
);
end axistream_spw_lite_v1_0;
architecture arch_imp of axistream_spw_lite_v1_0 is
constant SPW_EOP : std_logic_vector(7 downto 0) := x"00";
constant SPW_EEP : std_logic_vector(7 downto 0) := x"01";
signal reset : std_logic := '0'; -- active high
-- spacewire tx signals
signal spw_txwrite : std_logic := '0';
signal spw_txflag : std_logic := '0';
signal spw_txready : std_logic := '0';
signal spw_txdata : std_logic_vector(7 downto 0) := (others => '0');
-- spacewire rx signals
signal spw_rxvalid : std_logic := '0';
signal spw_txhalff : std_logic := '0';
signal spw_tick_out : std_logic := '0';
signal spw_rxhalff : std_logic := '0';
signal spw_rxflag : std_logic := '0';
signal spw_rxdata : std_logic_vector(7 downto 0) := (others => '0');
signal spw_rxread : std_logic := '0';
-- spacewire status signals
signal spw_linkstart : std_logic := '0';
signal spw_started : std_logic := '0';
signal spw_connecting : std_logic := '0';
signal spw_running : std_logic := '0';
signal spw_errdisc : std_logic := '0';
signal spw_errpar : std_logic := '0';
signal spw_erresc : std_logic := '0';
signal spw_errcred : std_logic := '0';
-- AXIS Slave signals
type s_axis_proc_states is (ST_ACTIVE, ST_SYNC, ST_EOP);
signal fsm_s_axis_proc_states : s_axis_proc_states;
signal tx_eop : boolean := false;
-- AXIS Master signals and functions
type SPW_RXBUF_T is record
byte : std_logic_vector(7 downto 0);
eep : boolean;
eop : boolean;
valid : boolean;
end record;
signal rxbuf_0 : SPW_RXBUF_T;
signal rxbuf_1 : SPW_RXBUF_T;
type m_axis_proc_states is (ST_READ_SPW_WORDS, ST_SPW_WORD_SYNC, ST_SEND_AXIS);
signal fsm_m_axis_proc_states : m_axis_proc_states := ST_READ_SPW_WORDS;
function reset_spw_buf_t(noop : std_logic) return SPW_RXBUF_T is
variable a : SPW_RXBUF_T;
begin
a.byte := (others => '0');
a.eep := false;
a.eop := false;
a.valid := false;
return a;
end function;
function copy_spw_buf_t(BUF_IN : SPW_RXBUF_T) return SPW_RXBUF_T is
variable a : SPW_RXBUF_T;
begin
a.byte := BUF_IN.byte;
a.eep := BUF_IN.eep;
a.eop := BUF_IN.eop;
a.valid := BUF_IN.valid;
return a;
end function;
begin
-----------------------------------------------------------------------------------------------
reset <= (not aresetn) or spw_errdisc or spw_errpar or spw_erresc or spw_errcred;
rx_error <= '1' when (spw_running = '0' or rxbuf_0.eep or rxbuf_1.eep) else '0';
spw_linkstart <= '0' when reset = '1' else '1';
-----------------------------------------------------------------------------------------------
s_axis_proc : process(aclk)
variable fsm : s_axis_proc_states := ST_ACTIVE;
begin
if (reset = '1') then
s_axis_tready <= '0';
spw_txwrite <= '0';
spw_txflag <= '0';
spw_txdata <= (others => '0');
tx_eop <= false;
fsm := ST_ACTIVE;
elsif (rising_edge(aclk)) then
if (spw_running = '1') then
case (fsm) is
when ST_ACTIVE =>
if (spw_txready = '1' and s_axis_tvalid = '1') then
fsm := ST_SYNC;
if (s_axis_tlast = '1') then
tx_eop <= true;
end if;
spw_txdata <= s_axis_tdata;
spw_txwrite <= '1';
spw_txflag <= '0';
s_axis_tready <= '1';
end if;
when ST_SYNC =>
s_axis_tready <= '0';
spw_txwrite <= '0';
spw_txflag <= '0';
spw_txdata <= (others => '0');
if (tx_eop) then
fsm := ST_EOP;
else
fsm := ST_ACTIVE;
end if;
when ST_EOP =>
tx_eop <= false;
if (spw_txready = '1') then
fsm := ST_SYNC;
spw_txdata <= SPW_EOP;
spw_txwrite <= '1';
spw_txflag <= '1';
end if;
when others =>
fsm := ST_ACTIVE;
s_axis_tready <= '0';
spw_txwrite <= '0';
spw_txflag <= '0';
spw_txdata <= (others => '0');
tx_eop <= false;
end case;
fsm_s_axis_proc_states <= fsm;
else
s_axis_tready <= '0';
spw_txwrite <= '0';
spw_txflag <= '0';
spw_txdata <= (others => '0');
tx_eop <= false;
fsm := ST_ACTIVE;
end if;
end if;
end process s_axis_proc;
-----------------------------------------------------------------------------------------------
-- buffer two bytes so the EOP can be captured to generate the TLAST flag on
-- the correct byte
-----------------------------------------------------------------------------------------------
m_axis_proc : process(aclk)
variable fsm : m_axis_proc_states := ST_READ_SPW_WORDS;
begin
if (reset = '1') then
m_axis_tdata <= (others => '0');
m_axis_tvalid <= '0';
m_axis_tlast <= '0';
rxbuf_0 <= reset_spw_buf_t('0');
rxbuf_1 <= reset_spw_buf_t('0');
spw_rxread <= '0';
fsm := ST_READ_SPW_WORDS;
elsif (rising_edge(aclk)) then
if (spw_running = '1') then
case (fsm) is
when ST_READ_SPW_WORDS =>
if (spw_rxvalid = '1') then
spw_rxread <= '1';
fsm := ST_SPW_WORD_SYNC;
if (rxbuf_0.valid = false) then
rxbuf_0.valid <= true;
if (spw_rxflag = '1') then
if (spw_rxdata = SPW_EOP) then
rxbuf_0.eop <= true;
else
rxbuf_0.eep <= true;
end if;
else
rxbuf_0.byte <= spw_rxdata;
end if;
else
rxbuf_1.valid <= true;
if (spw_rxflag = '1') then
if (spw_rxdata = SPW_EOP) then
rxbuf_1.eop <= true;
else
rxbuf_1.eep <= true;
end if;
else
rxbuf_1.byte <= spw_rxdata;
end if;
end if;
end if;
when ST_SPW_WORD_SYNC =>
spw_rxread <= '0';
if (rxbuf_1.valid = false) then
fsm := ST_READ_SPW_WORDS;
else
fsm := ST_SEND_AXIS;
m_axis_tdata <= rxbuf_0.byte;
m_axis_tvalid <= '1';
if (rxbuf_1.eop) then
m_axis_tlast <= '1';
rxbuf_0 <= reset_spw_buf_t('0');
rxbuf_1 <= reset_spw_buf_t('0');
else
m_axis_tlast <= '0';
rxbuf_0 <= copy_spw_buf_t(rxbuf_1);
end if;
end if;
when ST_SEND_AXIS =>
if (m_axis_tready = '1') then
fsm := ST_READ_SPW_WORDS;
m_axis_tdata <= (others => '0');
m_axis_tvalid <= '0';
m_axis_tlast <= '0';
end if;
when others =>
fsm := ST_READ_SPW_WORDS;
rxbuf_0 <= reset_spw_buf_t('0');
rxbuf_1 <= reset_spw_buf_t('0');
m_axis_tdata <= (others => '0');
m_axis_tvalid <= '0';
m_axis_tlast <= '0';
end case;
fsm_m_axis_proc_states <= fsm;
else
fsm := ST_READ_SPW_WORDS;
rxbuf_0 <= reset_spw_buf_t('0');
rxbuf_1 <= reset_spw_buf_t('0');
m_axis_tdata <= (others => '0');
m_axis_tvalid <= '0';
m_axis_tlast <= '0';
end if;
end if;
end process m_axis_proc;
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
-- Generate Proper Instantiation of spwstream interface
-----------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------
txrx_fast_gen : if rximpl_fast and tximpl_fast generate
spwstream_inst_txrx_fast : spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => impl_fast,
rxchunk => rxchunk_fast,
tximpl => impl_fast,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits
)
port map (
clk => aclk,
rxclk => rx_clk,
txclk => tx_clk,
rst => reset,
autostart => '0',
linkstart => spw_linkstart,
linkdis => '0',
txdivcnt => txdivcnt,
tick_in => '0',
ctrl_in => "00",
time_in => "000000",
txwrite => spw_txwrite,
txflag => spw_txflag,
txdata => spw_txdata,
txrdy => spw_txready, -- out
txhalff => spw_txhalff, -- out
tick_out => spw_tick_out,
ctrl_out => open,
time_out => open,
rxvalid => spw_rxvalid,
rxhalff => spw_rxhalff,
rxflag => spw_rxflag,
rxdata => spw_rxdata,
rxread => spw_rxread,
started => spw_started,
connecting => spw_connecting,
running => spw_running,
errdisc => spw_errdisc,
errpar => spw_errpar,
erresc => spw_erresc,
errcred => spw_errcred,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so
);
end generate txrx_fast_gen;
-----------------------------------------------------------------------------------------------
rx_fast_gen : if rximpl_fast and not tximpl_fast generate
spwstream_inst_rx_fast : spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => impl_fast,
rxchunk => rxchunk_fast,
tximpl => impl_generic,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits
)
port map (
clk => aclk,
rxclk => rx_clk,
txclk => '0',
rst => reset,
autostart => '0',
linkstart => spw_linkstart,
linkdis => '0',
txdivcnt => txdivcnt,
tick_in => '0',
ctrl_in => "00",
time_in => "000000",
txwrite => spw_txwrite,
txflag => spw_txflag,
txdata => spw_txdata,
txrdy => spw_txready, -- out
txhalff => spw_txhalff, -- out
tick_out => spw_tick_out,
ctrl_out => open,
time_out => open,
rxvalid => spw_rxvalid,
rxhalff => spw_rxhalff,
rxflag => spw_rxflag,
rxdata => spw_rxdata,
rxread => spw_rxread,
started => spw_started,
connecting => spw_connecting,
running => spw_running,
errdisc => spw_errdisc,
errpar => spw_errpar,
erresc => spw_erresc,
errcred => spw_errcred,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so
);
end generate rx_fast_gen;
-----------------------------------------------------------------------------------------------
tx_fast_gen : if not rximpl_fast and tximpl_fast generate
spwstream_inst_tx_fast : spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => impl_generic,
rxchunk => rxchunk_fast,
tximpl => impl_fast,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits
)
port map (
clk => aclk,
rxclk => '0',
txclk => tx_clk,
rst => reset,
autostart => '0',
linkstart => spw_linkstart,
linkdis => '0',
txdivcnt => txdivcnt,
tick_in => '0',
ctrl_in => "00",
time_in => "000000",
txwrite => spw_txwrite,
txflag => spw_txflag,
txdata => spw_txdata,
txrdy => spw_txready, -- out
txhalff => spw_txhalff, -- out
tick_out => spw_tick_out,
ctrl_out => open,
time_out => open,
rxvalid => spw_rxvalid,
rxhalff => spw_rxhalff,
rxflag => spw_rxflag,
rxdata => spw_rxdata,
rxread => spw_rxread,
started => spw_started,
connecting => spw_connecting,
running => spw_running,
errdisc => spw_errdisc,
errpar => spw_errpar,
erresc => spw_erresc,
errcred => spw_errcred,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so
);
end generate tx_fast_gen;
-----------------------------------------------------------------------------------------------
generic_gen : if not rximpl_fast and not tximpl_fast generate
spwstream_inst_generic : spwstream
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl => impl_generic,
rxchunk => rxchunk_fast,
tximpl => impl_generic,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits
)
port map (
clk => aclk,
rxclk => '0',
txclk => '0',
rst => reset,
autostart => '0',
linkstart => spw_linkstart,
linkdis => '0',
txdivcnt => txdivcnt,
tick_in => '0',
ctrl_in => "00",
time_in => "000000",
txwrite => spw_txwrite,
txflag => spw_txflag,
txdata => spw_txdata,
txrdy => spw_txready, -- out
txhalff => spw_txhalff, -- out
tick_out => spw_tick_out,
ctrl_out => open,
time_out => open,
rxvalid => spw_rxvalid,
rxhalff => spw_rxhalff,
rxflag => spw_rxflag,
rxdata => spw_rxdata,
rxread => spw_rxread,
started => spw_started,
connecting => spw_connecting,
running => spw_running,
errdisc => spw_errdisc,
errpar => spw_errpar,
erresc => spw_erresc,
errcred => spw_errcred,
spw_di => spw_di,
spw_si => spw_si,
spw_do => spw_do,
spw_so => spw_so
);
end generate generic_gen;
end arch_imp;
| mit | 7d841d0d5b26fef94bc2bad71edca121 | 0.433076 | 3.914103 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/rx_dsDMA_Channel.vhd | 1 | 27,981 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dsDMA_Transact is
port (
-- downstream DMA Channel Buffer
MRd_dsp_Req : OUT std_logic;
MRd_dsp_RE : IN std_logic;
MRd_dsp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Downstream reset from MWr channel
dsDMA_Channel_Rst : IN std_logic;
-- Downstream Registers from MWr Channel
DMA_ds_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : IN std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : IN std_logic;
dsBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : IN std_logic;
dsLeng_Lo7b_True : IN std_logic;
-- from Cpl/D channel
dsDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Control Signals from MWr Channel
dsDMA_Start : IN std_logic; -- out of 1st dex
dsDMA_Stop : IN std_logic; -- out of 1st dex
-- Downstream Control Signals from CplD Channel
dsDMA_Start2 : IN std_logic; -- out of consecutive dex
dsDMA_Stop2 : IN std_logic; -- out of consecutive dex
-- Downstream DMA Acknowledge to the start command
DMA_Cmd_Ack : OUT std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear : IN std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
FC_pop : IN std_logic;
-- Downstream tRAM port A write request
tRAM_weB : OUT std_logic;
tRAM_AddrB : OUT std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : OUT std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
-- To Tx Port
DMA_ds_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- Common ports
trn_clk : IN std_logic
);
end entity dsDMA_Transact;
architecture Behavioral of dsDMA_Transact is
signal FC_push : std_logic;
signal FC_counter : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal dsFC_stop : std_logic;
signal dsFC_stop_128B : std_logic;
signal dsFC_stop_256B : std_logic;
signal dsFC_stop_512B : std_logic;
signal dsFC_stop_1024B : std_logic;
signal dsFC_stop_2048B : std_logic;
signal dsFC_stop_4096B : std_logic;
-- Reset
signal Local_Reset_i : std_logic;
signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
-- Tag RAM port B write
signal tRAM_dinB_i : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_AddrB_i : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic;
-- DMA calculation
COMPONENT DMA_Calculate
PORT(
-- Downstream Registers from MWr Channel
DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : IN std_logic;
BDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : IN std_logic;
Leng_Lo7b_True : IN std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : OUT std_logic;
-- Only for downstream channel
DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : OUT std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
--
DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Engine control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : OUT std_logic;
ThereIs_Snout : OUT std_logic;
ThereIs_Body : OUT std_logic;
ThereIs_Tail : OUT std_logic;
ThereIs_Dex : OUT std_logic;
HA64bit : OUT std_logic;
Addr_Inc : OUT std_logic;
-- FSM indicators
State_Is_LoadParam : IN std_logic;
State_Is_Snout : IN std_logic;
State_Is_Body : IN std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : IN std_logic_vector(2 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
END COMPONENT;
signal dsDMA_PA_Loaded : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_PA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_HA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BDA_fsm : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsBDA_is_64b_fsm : std_logic;
signal dsDMA_PA_snout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BAR_Number : std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
signal dsDMA_Snout_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal dsDMA_Body_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal dsDMA_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal dsNo_More_Bodies : std_logic;
signal dsThereIs_Snout : std_logic;
signal dsThereIs_Body : std_logic;
signal dsThereIs_Tail : std_logic;
signal dsThereIs_Dex : std_logic;
signal dsHA64bit : std_logic;
signal ds_AInc : std_logic;
-- DMA state machine
COMPONENT DMA_FSM
PORT(
-- Fixed information for 1st header of TLP: MRd/MWr
TLP_Has_Payload : IN std_logic;
TLP_Hdr_is_4DW : IN std_logic;
DMA_Addr_Inc : IN std_logic;
DMA_BAR_Number : IN std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
-- FSM control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic;
DMA_Stop : IN std_logic;
DMA_Stop2 : IN std_logic;
No_More_Bodies : IN std_logic;
ThereIs_Snout : IN std_logic;
ThereIs_Body : IN std_logic;
ThereIs_Tail : IN std_logic;
ThereIs_Dex : IN std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : IN std_logic;
DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : IN std_logic;
Done_Condition_2 : IN std_logic;
Done_Condition_3 : IN std_logic;
Done_Condition_4 : IN std_logic;
Done_Condition_5 : IN std_logic;
-- Channel buffer write
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
ChBuf_aFull : IN std_logic;
ChBuf_WrEn : OUT std_logic;
ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : OUT std_logic;
State_Is_Snout : OUT std_logic;
State_Is_Body : OUT std_logic;
State_Is_Tail : OUT std_logic;
DMA_Cmd_Ack : OUT std_logic;
-- To Tx Port
ChBuf_ValidRd : IN std_logic;
BDA_nAligned : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
DMA_Done : OUT std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
END COMPONENT;
signal Tag_DMA_dsp : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- FSM state indicators
signal dsState_Is_LoadParam : std_logic;
signal dsState_Is_Snout : std_logic;
signal dsState_Is_Body : std_logic;
signal dsState_Is_Tail : std_logic;
signal dsChBuf_ValidRd : std_logic;
signal dsBDA_nAligned : std_logic;
signal dsDMA_TimeOut_i : std_logic;
signal dsDMA_Busy_i : std_logic;
signal dsDMA_Done_i : std_logic;
signal DMA_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
---------------------------------------------------------------
-- Done state identification uses 2^C_TAGRAM_AWIDTH bits, 2 stages logic
signal Tag_Map_Bits : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Tag_Map_filling : std_logic_vector(C_SUB_TAG_MAP_WIDTH-1 downto 0);
signal All_CplD_have_come : std_logic;
-- Built-in single-port fifo as downstream DMA channel buffer
-- 128-bit wide, for 64-bit address
component k7_sfifo_15x128
port (
clk : IN std_logic;
rst : IN std_logic;
prog_full : OUT std_logic;
-- wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : OUT std_logic;
-- rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic
);
end component;
-- Signal with DMA_downstream channel FIFO
signal MRd_dsp_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal MRd_dsp_dout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal MRd_dsp_re_i : std_logic;
signal MRd_dsp_we : std_logic;
signal MRd_dsp_empty_i : std_logic;
signal MRd_dsp_full : std_logic;
signal MRd_dsp_prog_Full : std_logic;
signal MRd_dsp_prog_Full_r1 : std_logic;
signal MRd_dsp_re_r1 : std_logic;
signal MRd_dsp_empty_r1 : std_logic;
-- Request for output arbitration
signal MRd_dsp_Req_i : std_logic;
begin
-- DMA done signal
DMA_Done <= dsDMA_Done_i;
DMA_TimeOut <= dsDMA_TimeOut_i;
DMA_Busy <= dsDMA_Busy_i;
-- connecting FIFO's signals
MRd_dsp_Qout <= MRd_dsp_dout;
MRd_dsp_re_i <= MRd_dsp_RE;
MRd_dsp_Req <= MRd_dsp_Req_i;
-- tag RAM write request signals
tRAM_weB <= tRAM_weB_i;
tRAM_AddrB <= tRAM_AddrB_i;
tRAM_dinB <= tRAM_dinB_i;
-- positive local reset
Local_Reset_i <= dsDMA_Channel_Rst;
-- Max Read Request Size bits
cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
-- Kernel Engine
ds_DMA_Calculation:
DMA_Calculate
PORT MAP(
DMA_PA => DMA_ds_PA ,
DMA_HA => DMA_ds_HA ,
DMA_BDA => DMA_ds_BDA ,
DMA_Length => DMA_ds_Length ,
DMA_Control => DMA_ds_Control ,
HA_is_64b => dsHA_is_64b ,
BDA_is_64b => dsBDA_is_64b ,
Leng_Hi19b_True => dsLeng_Hi19b_True ,
Leng_Lo7b_True => dsLeng_Lo7b_True ,
DMA_PA_Loaded => dsDMA_PA_Loaded ,
DMA_PA_Var => dsDMA_PA_Var ,
DMA_HA_Var => dsDMA_HA_Var ,
DMA_BDA_fsm => dsDMA_BDA_fsm ,
BDA_is_64b_fsm => dsBDA_is_64b_fsm ,
-- Only for downstream channel
DMA_PA_Snout => dsDMA_PA_snout ,
DMA_BAR_Number => dsDMA_BAR_Number ,
-- Lengths
DMA_Snout_Length => dsDMA_Snout_Length ,
DMA_Body_Length => dsDMA_Body_Length ,
DMA_Tail_Length => dsDMA_Tail_Length ,
-- Control signals to FSM
No_More_Bodies => dsNo_More_Bodies ,
ThereIs_Snout => dsThereIs_Snout ,
ThereIs_Body => dsThereIs_Body ,
ThereIs_Tail => dsThereIs_Tail ,
ThereIs_Dex => dsThereIs_Dex ,
HA64bit => dsHA64bit ,
Addr_Inc => ds_AInc ,
DMA_Start => dsDMA_Start ,
DMA_Start2 => dsDMA_Start2 ,
State_Is_LoadParam => dsState_Is_LoadParam ,
State_Is_Snout => dsState_Is_Snout ,
State_Is_Body => dsState_Is_Body ,
-- State_Is_Tail => dsState_Is_Tail ,
Param_Max_Cfg => cfg_MRS ,
dma_clk => trn_clk ,
dma_reset => Local_Reset_i
);
-- Kernel FSM
ds_DMA_StateMachine:
DMA_FSM
PORT MAP(
TLP_Has_Payload => '0' ,
TLP_Hdr_is_4DW => dsHA64bit ,
DMA_Addr_Inc => '0' , -- of any value
DMA_BAR_Number => dsDMA_BAR_Number ,
DMA_Start => dsDMA_Start ,
DMA_Start2 => dsDMA_Start2 ,
DMA_Stop => dsDMA_Stop ,
DMA_Stop2 => dsDMA_Stop2 ,
-- Control signals to FSM
No_More_Bodies => dsNo_More_Bodies ,
ThereIs_Snout => dsThereIs_Snout ,
ThereIs_Body => dsThereIs_Body ,
ThereIs_Tail => dsThereIs_Tail ,
ThereIs_Dex => dsThereIs_Dex ,
DMA_PA_Loaded => dsDMA_PA_Loaded ,
DMA_PA_Var => dsDMA_PA_Var ,
DMA_HA_Var => dsDMA_HA_Var ,
DMA_BDA_fsm => dsDMA_BDA_fsm ,
BDA_is_64b_fsm => dsBDA_is_64b_fsm ,
DMA_Snout_Length => dsDMA_Snout_Length ,
DMA_Body_Length => dsDMA_Body_Length ,
DMA_Tail_Length => dsDMA_Tail_Length ,
ChBuf_ValidRd => dsChBuf_ValidRd,
BDA_nAligned => dsBDA_nAligned ,
DMA_TimeOut => dsDMA_TimeOut_i,
DMA_Busy => dsDMA_Busy_i ,
DMA_Done => dsDMA_Done_i ,
-- DMA_Done_Rise => open ,
Pkt_Tag => Tag_DMA_dsp ,
Dex_Tag => dsDMA_dex_Tag ,
Done_Condition_1 => '1' ,
Done_Condition_2 => MRd_dsp_empty_r1 ,
Done_Condition_3 => '1' ,
Done_Condition_4 => '1' ,
Done_Condition_5 => All_CplD_have_come ,
us_MWr_Param_Vec => "000000" ,
ChBuf_aFull => MRd_dsp_prog_Full_r1 ,
ChBuf_WrEn => MRd_dsp_we ,
ChBuf_WrDin => MRd_dsp_din ,
State_Is_LoadParam => dsState_Is_LoadParam ,
State_Is_Snout => dsState_Is_Snout ,
State_Is_Body => dsState_Is_Body ,
State_Is_Tail => dsState_Is_Tail ,
DMA_Cmd_Ack => DMA_Cmd_Ack ,
dma_clk => trn_clk ,
dma_reset => Local_Reset_i
);
dsChBuf_ValidRd <= MRd_dsp_RE; -- MRd_dsp_re_i and not MRd_dsp_empty_i;
-- -------------------------------------------------
--
DMA_ds_Status <= DMA_Status_i;
--
-- Synchronous output: DMA_Status
--
DS_DMA_Status_Concat:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DMA_Status_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
DMA_Status_i <= (
CINT_BIT_DMA_STAT_NALIGN => dsBDA_nAligned,
CINT_BIT_DMA_STAT_TIMEOUT => dsDMA_TimeOut_i,
CINT_BIT_DMA_STAT_BDANULL => dsDMA_BDA_eq_Null,
CINT_BIT_DMA_STAT_BUSY => dsDMA_Busy_i,
CINT_BIT_DMA_STAT_DONE => dsDMA_Done_i,
Others => '0'
);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: tRAM_weB
-- tRAM_AddrB
-- tRAM_dinB
--
FSM_dsDMA_tRAM_PortB:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_weB_i <= '0';
tRAM_AddrB_i <= (OTHERS =>'1');
tRAM_dinB_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
tRAM_AddrB_i <= Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i <= dsState_Is_Snout
or dsState_Is_Body
or dsState_Is_Tail;
if dsState_Is_Snout='1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_snout(C_TAGBAR_BIT_BOT-1 downto 2)&"00"
;
elsif dsState_Is_Body='1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_Var(C_TAGBAR_BIT_BOT-1 downto 2) &"00"
;
elsif dsState_Is_Tail='1' then
tRAM_dinB_i <=
ds_AInc -- DMA_ds_Control(CINT_BIT_DMA_CTRL_AINC)
& dsDMA_BAR_Number -- (C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0)
& dsDMA_PA_Var(C_TAGBAR_BIT_BOT-1 downto 2) &"00"
;
else
tRAM_dinB_i <= (Others=>'0');
end if;
end if;
end process;
-- ------------------------------------------
-- Loop: Tag_Map
--
Sync_Tag_set_reset_Bits:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Bits <= (Others=>'0');
elsif trn_clk'event and trn_clk = '1' then
FOR j IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
if tRAM_AddrB_i=CONV_STD_LOGIC_VECTOR(j, C_TAGRAM_AWIDTH) and tRAM_weB_i='1' then
Tag_Map_Bits(j) <= '1';
elsif Tag_Map_Clear(j)='1' then
Tag_Map_Bits(j) <= '0';
else
Tag_Map_Bits(j) <= Tag_Map_Bits(j);
end if;
END LOOP;
end if;
end process;
-- ------------------------------------------
-- Determination: All_CplD_have_come
--
Sync_Reg_All_CplD_have_come:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_filling <= (OTHERS =>'0');
All_CplD_have_come <= '0';
elsif trn_clk'event and trn_clk = '1' then
FOR k IN 0 TO C_SUB_TAG_MAP_WIDTH-1 LOOP
if Tag_Map_Bits((C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*(k+1)-1 downto (C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*k)
= C_ALL_ZEROS((C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*(k+1)-1 downto (C_TAG_MAP_WIDTH/C_SUB_TAG_MAP_WIDTH)*k)
then
Tag_Map_filling(k) <= '1';
else
Tag_Map_filling(k) <= '0';
end if;
END LOOP;
-- final signal : All_CplD_have_come
if Tag_Map_filling=C_ALL_ONES(C_SUB_TAG_MAP_WIDTH-1 downto 0) then
All_CplD_have_come <= '1';
else
All_CplD_have_come <= '0';
end if;
end if;
end process;
-- ------------------------------------------
-- Synchronous Output: Tag_DMA_dsp
--
FSM_dsDMA_Tag_DMA_dsp:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_DMA_dsp <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
if dsState_Is_Snout='1'
or dsState_Is_Body='1'
or dsState_Is_Tail='1'
then
Tag_DMA_dsp <= '0' & dsDMA_BAR_Number(1)
& ( Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(1, C_TAGRAM_AWIDTH));
else
Tag_DMA_dsp <= '0' & dsDMA_BAR_Number(1)
& Tag_DMA_dsp(C_TAGRAM_AWIDTH-1 downto 0);
end if;
end if;
end process;
-- -------------------------------------------------
-- ds MRd TLP Buffer
-- -------------------------------------------------
DMA_DSP_Buffer:
k7_sfifo_15x128
port map (
clk => trn_clk,
rst => Local_Reset_i,
prog_full => MRd_dsp_prog_Full,
-- wr_clk => trn_clk,
wr_en => MRd_dsp_we,
din => MRd_dsp_din,
full => MRd_dsp_full,
-- rd_clk => trn_clk,
rd_en => MRd_dsp_re_i,
dout => MRd_dsp_dout,
prog_empty => open,
empty => MRd_dsp_empty_i
);
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
MRd_dsp_re_r1 <= MRd_dsp_re_i;
MRd_dsp_empty_r1 <= MRd_dsp_empty_i;
MRd_dsp_prog_Full_r1 <= MRd_dsp_prog_Full;
MRd_dsp_Req_i <= not MRd_dsp_empty_i
and not dsDMA_Stop
and not dsDMA_Stop2
and not dsFC_stop
;
end if;
end process;
-- ------------------------------------------
-- Synchronous: FC_push
--
Synch_Calc_FC_push:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_push <= '0';
elsif trn_clk'event and trn_clk = '1' then
FC_push <= MRd_dsp_re_r1 and not MRd_dsp_empty_r1
and not MRd_dsp_dout(C_CHBUF_TAG_BIT_TOP);
end if;
end process;
-- ------------------------------------------
-- Synchronous: FC_counter
--
Synch_Calc_FC_counter:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_counter <= (Others=>'0');
elsif trn_clk'event and trn_clk = '1' then
if FC_push='1' and FC_pop='0' then
FC_counter <= FC_counter + '1';
elsif FC_push='0' and FC_pop='1' then
FC_counter <= FC_counter - '1';
else
FC_counter <= FC_counter;
end if;
end if;
end process;
-- ------------------------------------------
-- Synchronous: dsFC_stop
--
Synch_Calc_dsFC_stop:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
dsFC_stop_128B <= '1';
dsFC_stop_256B <= '1';
dsFC_stop_512B <= '1';
dsFC_stop_1024B <= '1';
dsFC_stop_2048B <= '1';
dsFC_stop_4096B <= '1';
elsif trn_clk'event and trn_clk = '1' then
if FC_counter(C_TAGRAM_AWIDTH-1 downto 0)/=C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 0) then
dsFC_stop_4096B <= '1';
else
dsFC_stop_4096B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 0)/=C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 0) then
dsFC_stop_2048B <= '1';
else
dsFC_stop_2048B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 1)/=C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 1) then
dsFC_stop_1024B <= '1';
else
dsFC_stop_1024B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 2)/=C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 2) then
dsFC_stop_512B <= '1';
else
dsFC_stop_512B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 3)/=C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 3) then
dsFC_stop_256B <= '1';
else
dsFC_stop_256B <= '0';
end if;
if FC_counter(C_TAGRAM_AWIDTH-1 downto 4)/=C_ALL_ZEROS(C_TAGRAM_AWIDTH-1 downto 4) then
dsFC_stop_128B <= '1';
else
dsFC_stop_128B <= '0';
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: cfg_MRS
--
Syn_Config_Param_cfg_MRS:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then -- 0x0080 Bytes
dsFC_stop <= '1';
elsif trn_clk'event and trn_clk = '1' then
case cfg_MRS is
when "000" => -- 0x0080 Bytes
dsFC_stop <= dsFC_stop_128B;
when "001" => -- 0x0100 Bytes
dsFC_stop <= dsFC_stop_256B;
when "010" => -- 0x0200 Bytes
dsFC_stop <= dsFC_stop_512B;
when "011" => -- 0x0400 Bytes
dsFC_stop <= dsFC_stop_1024B;
when "100" => -- 0x0800 Bytes
dsFC_stop <= dsFC_stop_2048B;
when "101" => -- 0x1000 Bytes
dsFC_stop <= dsFC_stop_4096B;
when Others => -- as 0x0080 Bytes
dsFC_stop <= dsFC_stop_128B;
end case;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | 964d99f4360d805c217d5c487ca9e179 | 0.49405 | 3.505952 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/MultiplierFP.vhd | 4 | 4,778 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:29:18 04/17/2015
-- Design Name:
-- Module Name: MultiplierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MultiplierFP is
generic ( INTBIT_WIDTH : positive := 24; --Size of the integer part of the input/output vectors
FRACBIT_WIDTH : positive := 8; --Bit width of the Fixed Point fraction of the input/output vectors
COUNT_WIDTH : positive := 6); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDTH is 16, COUNT_WIDTH needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
Port ( CLK : in std_logic; --clock
RESET : in std_logic; --RESET signal (pulse)
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --multiplicand
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --mutiplier
OUT_MULT : out signed (((INTBIT_WIDTH + FRACBIT_WIDTH)*2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end MultiplierFP;
architecture Behavioral of MultiplierFP is
type reg_type is record
counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
EN : std_logic;
tmp1 : signed (((INTBIT_WIDTH + FRACBIT_WIDTH)*2 - 1) downto 0); -- B / COEF
tmp2 : signed (((INTBIT_WIDTH + FRACBIT_WIDTH)*2 - 1) downto 0);
tmpA : signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); -- A / SIG
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal IN_SIG_TEMP : signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
signal IN_COEF_TEMP : signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
begin
IN_SIG_TEMP((INTBIT_WIDTH + FRACBIT_WIDTH - 1) downto FRACBIT_WIDTH) <= IN_SIG;
IN_SIG_TEMP((FRACBIT_WIDTH - 1) downto 0) <= "00000000";
--Control logic of the multiplication algorithm
combinational : process(IN_SIG_TEMP, IN_COEF, r, RESET)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
if (RESET = '1') then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
OUT_MULT <= (others => '0');
READY <= '0';
else
v := r;
v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
OUT_MULT <= v.tmp1;
if (v.counter = 2*(INTBIT_WIDTH + FRACBIT_WIDTH)-1) then
READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := IN_SIG_TEMP;
v.tmp1 := RESIZE(IN_COEF,OUT_MULT'LENGTH);
v.tmp2 := (others => '0');
else
READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2*(INTBIT_WIDTH + FRACBIT_WIDTH)-1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end process combinational;
sequential : process (CLK)
begin
if rising_edge(CLK) then
r <= rin;
end if;
end process sequential;
end Behavioral;
| mit | 751036c93096cf1dc9963a765758cd3f | 0.544161 | 3.756289 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_dverif.vhd | 1 | 5,848 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
ENTITY k7_mBuf_128x72_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF k7_mBuf_128x72_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:k7_mBuf_128x72_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | f675c40d116a4e3cae8e0f4e374780f6 | 0.568741 | 3.948683 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_tb.vhd | 1 | 6,065 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo8to32_pkg.ALL;
ENTITY fifo8to32_tb IS
END ENTITY;
ARCHITECTURE fifo8to32_arch OF fifo8to32_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fifo8to32_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fifo8to32_synth
fifo8to32_synth_inst:fifo8to32_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | f5c184d3e9aabab4045ae5976e209e05 | 0.616158 | 4.097973 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_clkgen_v1_00_a/hdl/vhdl/axi_clkgen.vhd | 3 | 9,592 | -- ***************************************************************************
-- ***************************************************************************
-- [email protected] (c) Analog Devices Inc.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
entity axi_clkgen is
generic
(
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
ref_clk : in std_logic;
clk : out std_logic;
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_clkgen;
architecture IMP of axi_clkgen is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(ZERO_ADDR_PAD & USER_SLV_BASEADDR, ZERO_ADDR_PAD & USER_SLV_HIGHADDR);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := (0 => (USER_SLV_NUM_REG));
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
component user_logic is
generic
(
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port
(
ref_clk : in std_logic;
clk : out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
end component user_logic;
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : component user_logic
generic map
(
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
ref_clk => ref_clk,
clk => clk,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
-- ***************************************************************************
-- ***************************************************************************
| mit | 9a68c22c749ec90e61f0d76284e3652a | 0.501981 | 3.363254 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/hdl/cpu_wrapper.vhd | 1 | 36,704 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Fri Sep 30 18:09:05 2016
--Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
--Command : generate_target cpu_wrapper.bd
--Design : cpu_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
EPC_INTF_addr : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_ads : out STD_LOGIC;
EPC_INTF_be : out STD_LOGIC_VECTOR ( 0 to 3 );
EPC_INTF_burst : out STD_LOGIC;
EPC_INTF_clk : in STD_LOGIC;
EPC_INTF_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_rd_n : out STD_LOGIC;
EPC_INTF_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_rnw : out STD_LOGIC;
EPC_INTF_rst : in STD_LOGIC;
EPC_INTF_wr_n : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
Int0 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int3 : in STD_LOGIC_VECTOR ( 0 to 0 );
OCXO_CLK100 : in STD_LOGIC;
OCXO_RESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
UART_0_rxd : in STD_LOGIC;
UART_0_txd : out STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
epc_intf_data_io : inout STD_LOGIC_VECTOR ( 31 downto 0 );
gpio_tri_io : inout STD_LOGIC_VECTOR ( 15 downto 0 );
iic_0_scl_io : inout STD_LOGIC;
iic_0_sda_io : inout STD_LOGIC;
iic_1_scl_io : inout STD_LOGIC;
iic_1_sda_io : inout STD_LOGIC;
iic_scl_io : inout STD_LOGIC;
iic_sda_io : inout STD_LOGIC
);
end cpu_wrapper;
architecture STRUCTURE of cpu_wrapper is
component cpu is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
UART_0_txd : out STD_LOGIC;
UART_0_rxd : in STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
IIC_1_sda_i : in STD_LOGIC;
IIC_1_sda_o : out STD_LOGIC;
IIC_1_sda_t : out STD_LOGIC;
IIC_1_scl_i : in STD_LOGIC;
IIC_1_scl_o : out STD_LOGIC;
IIC_1_scl_t : out STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
IIC_scl_i : in STD_LOGIC;
IIC_scl_o : out STD_LOGIC;
IIC_scl_t : out STD_LOGIC;
IIC_sda_i : in STD_LOGIC;
IIC_sda_o : out STD_LOGIC;
IIC_sda_t : out STD_LOGIC;
EPC_INTF_addr : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_ads : out STD_LOGIC;
EPC_INTF_be : out STD_LOGIC_VECTOR ( 0 to 3 );
EPC_INTF_burst : out STD_LOGIC;
EPC_INTF_clk : in STD_LOGIC;
EPC_INTF_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_data_i : in STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_data_o : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_data_t : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_rd_n : out STD_LOGIC;
EPC_INTF_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_rnw : out STD_LOGIC;
EPC_INTF_rst : in STD_LOGIC;
EPC_INTF_wr_n : out STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC;
OCXO_CLK100 : in STD_LOGIC;
OCXO_RESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
Int0 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int3 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu;
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal epc_intf_data_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal epc_intf_data_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal epc_intf_data_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal epc_intf_data_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal epc_intf_data_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal epc_intf_data_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal epc_intf_data_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal epc_intf_data_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal epc_intf_data_i_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal epc_intf_data_i_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal epc_intf_data_i_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal epc_intf_data_i_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal epc_intf_data_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal epc_intf_data_i_20 : STD_LOGIC_VECTOR ( 20 to 20 );
signal epc_intf_data_i_21 : STD_LOGIC_VECTOR ( 21 to 21 );
signal epc_intf_data_i_22 : STD_LOGIC_VECTOR ( 22 to 22 );
signal epc_intf_data_i_23 : STD_LOGIC_VECTOR ( 23 to 23 );
signal epc_intf_data_i_24 : STD_LOGIC_VECTOR ( 24 to 24 );
signal epc_intf_data_i_25 : STD_LOGIC_VECTOR ( 25 to 25 );
signal epc_intf_data_i_26 : STD_LOGIC_VECTOR ( 26 to 26 );
signal epc_intf_data_i_27 : STD_LOGIC_VECTOR ( 27 to 27 );
signal epc_intf_data_i_28 : STD_LOGIC_VECTOR ( 28 to 28 );
signal epc_intf_data_i_29 : STD_LOGIC_VECTOR ( 29 to 29 );
signal epc_intf_data_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal epc_intf_data_i_30 : STD_LOGIC_VECTOR ( 30 to 30 );
signal epc_intf_data_i_31 : STD_LOGIC_VECTOR ( 31 to 31 );
signal epc_intf_data_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal epc_intf_data_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal epc_intf_data_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal epc_intf_data_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal epc_intf_data_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal epc_intf_data_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal epc_intf_data_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal epc_intf_data_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal epc_intf_data_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal epc_intf_data_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal epc_intf_data_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal epc_intf_data_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal epc_intf_data_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal epc_intf_data_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal epc_intf_data_io_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal epc_intf_data_io_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal epc_intf_data_io_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal epc_intf_data_io_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal epc_intf_data_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal epc_intf_data_io_20 : STD_LOGIC_VECTOR ( 20 to 20 );
signal epc_intf_data_io_21 : STD_LOGIC_VECTOR ( 21 to 21 );
signal epc_intf_data_io_22 : STD_LOGIC_VECTOR ( 22 to 22 );
signal epc_intf_data_io_23 : STD_LOGIC_VECTOR ( 23 to 23 );
signal epc_intf_data_io_24 : STD_LOGIC_VECTOR ( 24 to 24 );
signal epc_intf_data_io_25 : STD_LOGIC_VECTOR ( 25 to 25 );
signal epc_intf_data_io_26 : STD_LOGIC_VECTOR ( 26 to 26 );
signal epc_intf_data_io_27 : STD_LOGIC_VECTOR ( 27 to 27 );
signal epc_intf_data_io_28 : STD_LOGIC_VECTOR ( 28 to 28 );
signal epc_intf_data_io_29 : STD_LOGIC_VECTOR ( 29 to 29 );
signal epc_intf_data_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal epc_intf_data_io_30 : STD_LOGIC_VECTOR ( 30 to 30 );
signal epc_intf_data_io_31 : STD_LOGIC_VECTOR ( 31 to 31 );
signal epc_intf_data_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal epc_intf_data_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal epc_intf_data_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal epc_intf_data_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal epc_intf_data_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal epc_intf_data_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal epc_intf_data_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal epc_intf_data_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal epc_intf_data_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal epc_intf_data_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal epc_intf_data_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal epc_intf_data_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal epc_intf_data_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal epc_intf_data_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal epc_intf_data_o_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal epc_intf_data_o_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal epc_intf_data_o_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal epc_intf_data_o_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal epc_intf_data_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal epc_intf_data_o_20 : STD_LOGIC_VECTOR ( 20 to 20 );
signal epc_intf_data_o_21 : STD_LOGIC_VECTOR ( 21 to 21 );
signal epc_intf_data_o_22 : STD_LOGIC_VECTOR ( 22 to 22 );
signal epc_intf_data_o_23 : STD_LOGIC_VECTOR ( 23 to 23 );
signal epc_intf_data_o_24 : STD_LOGIC_VECTOR ( 24 to 24 );
signal epc_intf_data_o_25 : STD_LOGIC_VECTOR ( 25 to 25 );
signal epc_intf_data_o_26 : STD_LOGIC_VECTOR ( 26 to 26 );
signal epc_intf_data_o_27 : STD_LOGIC_VECTOR ( 27 to 27 );
signal epc_intf_data_o_28 : STD_LOGIC_VECTOR ( 28 to 28 );
signal epc_intf_data_o_29 : STD_LOGIC_VECTOR ( 29 to 29 );
signal epc_intf_data_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal epc_intf_data_o_30 : STD_LOGIC_VECTOR ( 30 to 30 );
signal epc_intf_data_o_31 : STD_LOGIC_VECTOR ( 31 to 31 );
signal epc_intf_data_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal epc_intf_data_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal epc_intf_data_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal epc_intf_data_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal epc_intf_data_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal epc_intf_data_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal epc_intf_data_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal epc_intf_data_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal epc_intf_data_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal epc_intf_data_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal epc_intf_data_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal epc_intf_data_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal epc_intf_data_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal epc_intf_data_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal epc_intf_data_t_16 : STD_LOGIC_VECTOR ( 16 to 16 );
signal epc_intf_data_t_17 : STD_LOGIC_VECTOR ( 17 to 17 );
signal epc_intf_data_t_18 : STD_LOGIC_VECTOR ( 18 to 18 );
signal epc_intf_data_t_19 : STD_LOGIC_VECTOR ( 19 to 19 );
signal epc_intf_data_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal epc_intf_data_t_20 : STD_LOGIC_VECTOR ( 20 to 20 );
signal epc_intf_data_t_21 : STD_LOGIC_VECTOR ( 21 to 21 );
signal epc_intf_data_t_22 : STD_LOGIC_VECTOR ( 22 to 22 );
signal epc_intf_data_t_23 : STD_LOGIC_VECTOR ( 23 to 23 );
signal epc_intf_data_t_24 : STD_LOGIC_VECTOR ( 24 to 24 );
signal epc_intf_data_t_25 : STD_LOGIC_VECTOR ( 25 to 25 );
signal epc_intf_data_t_26 : STD_LOGIC_VECTOR ( 26 to 26 );
signal epc_intf_data_t_27 : STD_LOGIC_VECTOR ( 27 to 27 );
signal epc_intf_data_t_28 : STD_LOGIC_VECTOR ( 28 to 28 );
signal epc_intf_data_t_29 : STD_LOGIC_VECTOR ( 29 to 29 );
signal epc_intf_data_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal epc_intf_data_t_30 : STD_LOGIC_VECTOR ( 30 to 30 );
signal epc_intf_data_t_31 : STD_LOGIC_VECTOR ( 31 to 31 );
signal epc_intf_data_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal epc_intf_data_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal epc_intf_data_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal epc_intf_data_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal epc_intf_data_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal epc_intf_data_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_i_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_i_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_i_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_i_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_i_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal gpio_tri_i_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal gpio_tri_i_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal gpio_tri_i_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal gpio_tri_i_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_i_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_i_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_i_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_i_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_i_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_i_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_i_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_io_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_io_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_io_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_io_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_io_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal gpio_tri_io_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal gpio_tri_io_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal gpio_tri_io_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal gpio_tri_io_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_io_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_io_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_io_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_io_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_io_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_io_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_io_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_o_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_o_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_o_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_o_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_o_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal gpio_tri_o_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal gpio_tri_o_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal gpio_tri_o_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal gpio_tri_o_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_o_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_o_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_o_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_o_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_o_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_o_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_o_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal gpio_tri_t_0 : STD_LOGIC_VECTOR ( 0 to 0 );
signal gpio_tri_t_1 : STD_LOGIC_VECTOR ( 1 to 1 );
signal gpio_tri_t_10 : STD_LOGIC_VECTOR ( 10 to 10 );
signal gpio_tri_t_11 : STD_LOGIC_VECTOR ( 11 to 11 );
signal gpio_tri_t_12 : STD_LOGIC_VECTOR ( 12 to 12 );
signal gpio_tri_t_13 : STD_LOGIC_VECTOR ( 13 to 13 );
signal gpio_tri_t_14 : STD_LOGIC_VECTOR ( 14 to 14 );
signal gpio_tri_t_15 : STD_LOGIC_VECTOR ( 15 to 15 );
signal gpio_tri_t_2 : STD_LOGIC_VECTOR ( 2 to 2 );
signal gpio_tri_t_3 : STD_LOGIC_VECTOR ( 3 to 3 );
signal gpio_tri_t_4 : STD_LOGIC_VECTOR ( 4 to 4 );
signal gpio_tri_t_5 : STD_LOGIC_VECTOR ( 5 to 5 );
signal gpio_tri_t_6 : STD_LOGIC_VECTOR ( 6 to 6 );
signal gpio_tri_t_7 : STD_LOGIC_VECTOR ( 7 to 7 );
signal gpio_tri_t_8 : STD_LOGIC_VECTOR ( 8 to 8 );
signal gpio_tri_t_9 : STD_LOGIC_VECTOR ( 9 to 9 );
signal iic_0_scl_i : STD_LOGIC;
signal iic_0_scl_o : STD_LOGIC;
signal iic_0_scl_t : STD_LOGIC;
signal iic_0_sda_i : STD_LOGIC;
signal iic_0_sda_o : STD_LOGIC;
signal iic_0_sda_t : STD_LOGIC;
signal iic_1_scl_i : STD_LOGIC;
signal iic_1_scl_o : STD_LOGIC;
signal iic_1_scl_t : STD_LOGIC;
signal iic_1_sda_i : STD_LOGIC;
signal iic_1_sda_o : STD_LOGIC;
signal iic_1_sda_t : STD_LOGIC;
signal iic_scl_i : STD_LOGIC;
signal iic_scl_o : STD_LOGIC;
signal iic_scl_t : STD_LOGIC;
signal iic_sda_i : STD_LOGIC;
signal iic_sda_o : STD_LOGIC;
signal iic_sda_t : STD_LOGIC;
begin
cpu_i: component cpu
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
EPC_INTF_addr(0 to 31) => EPC_INTF_addr(0 to 31),
EPC_INTF_ads => EPC_INTF_ads,
EPC_INTF_be(0 to 3) => EPC_INTF_be(0 to 3),
EPC_INTF_burst => EPC_INTF_burst,
EPC_INTF_clk => EPC_INTF_clk,
EPC_INTF_cs_n(0) => EPC_INTF_cs_n(0),
EPC_INTF_data_i(0) => epc_intf_data_i_0(0),
EPC_INTF_data_i(1) => epc_intf_data_i_1(1),
EPC_INTF_data_i(2) => epc_intf_data_i_2(2),
EPC_INTF_data_i(3) => epc_intf_data_i_3(3),
EPC_INTF_data_i(4) => epc_intf_data_i_4(4),
EPC_INTF_data_i(5) => epc_intf_data_i_5(5),
EPC_INTF_data_i(6) => epc_intf_data_i_6(6),
EPC_INTF_data_i(7) => epc_intf_data_i_7(7),
EPC_INTF_data_i(8) => epc_intf_data_i_8(8),
EPC_INTF_data_i(9) => epc_intf_data_i_9(9),
EPC_INTF_data_i(10) => epc_intf_data_i_10(10),
EPC_INTF_data_i(11) => epc_intf_data_i_11(11),
EPC_INTF_data_i(12) => epc_intf_data_i_12(12),
EPC_INTF_data_i(13) => epc_intf_data_i_13(13),
EPC_INTF_data_i(14) => epc_intf_data_i_14(14),
EPC_INTF_data_i(15) => epc_intf_data_i_15(15),
EPC_INTF_data_i(16) => epc_intf_data_i_16(16),
EPC_INTF_data_i(17) => epc_intf_data_i_17(17),
EPC_INTF_data_i(18) => epc_intf_data_i_18(18),
EPC_INTF_data_i(19) => epc_intf_data_i_19(19),
EPC_INTF_data_i(20) => epc_intf_data_i_20(20),
EPC_INTF_data_i(21) => epc_intf_data_i_21(21),
EPC_INTF_data_i(22) => epc_intf_data_i_22(22),
EPC_INTF_data_i(23) => epc_intf_data_i_23(23),
EPC_INTF_data_i(24) => epc_intf_data_i_24(24),
EPC_INTF_data_i(25) => epc_intf_data_i_25(25),
EPC_INTF_data_i(26) => epc_intf_data_i_26(26),
EPC_INTF_data_i(27) => epc_intf_data_i_27(27),
EPC_INTF_data_i(28) => epc_intf_data_i_28(28),
EPC_INTF_data_i(29) => epc_intf_data_i_29(29),
EPC_INTF_data_i(30) => epc_intf_data_i_30(30),
EPC_INTF_data_i(31) => epc_intf_data_i_31(31),
EPC_INTF_data_o(0) => epc_intf_data_o_0(0),
EPC_INTF_data_o(1) => epc_intf_data_o_1(1),
EPC_INTF_data_o(2) => epc_intf_data_o_2(2),
EPC_INTF_data_o(3) => epc_intf_data_o_3(3),
EPC_INTF_data_o(4) => epc_intf_data_o_4(4),
EPC_INTF_data_o(5) => epc_intf_data_o_5(5),
EPC_INTF_data_o(6) => epc_intf_data_o_6(6),
EPC_INTF_data_o(7) => epc_intf_data_o_7(7),
EPC_INTF_data_o(8) => epc_intf_data_o_8(8),
EPC_INTF_data_o(9) => epc_intf_data_o_9(9),
EPC_INTF_data_o(10) => epc_intf_data_o_10(10),
EPC_INTF_data_o(11) => epc_intf_data_o_11(11),
EPC_INTF_data_o(12) => epc_intf_data_o_12(12),
EPC_INTF_data_o(13) => epc_intf_data_o_13(13),
EPC_INTF_data_o(14) => epc_intf_data_o_14(14),
EPC_INTF_data_o(15) => epc_intf_data_o_15(15),
EPC_INTF_data_o(16) => epc_intf_data_o_16(16),
EPC_INTF_data_o(17) => epc_intf_data_o_17(17),
EPC_INTF_data_o(18) => epc_intf_data_o_18(18),
EPC_INTF_data_o(19) => epc_intf_data_o_19(19),
EPC_INTF_data_o(20) => epc_intf_data_o_20(20),
EPC_INTF_data_o(21) => epc_intf_data_o_21(21),
EPC_INTF_data_o(22) => epc_intf_data_o_22(22),
EPC_INTF_data_o(23) => epc_intf_data_o_23(23),
EPC_INTF_data_o(24) => epc_intf_data_o_24(24),
EPC_INTF_data_o(25) => epc_intf_data_o_25(25),
EPC_INTF_data_o(26) => epc_intf_data_o_26(26),
EPC_INTF_data_o(27) => epc_intf_data_o_27(27),
EPC_INTF_data_o(28) => epc_intf_data_o_28(28),
EPC_INTF_data_o(29) => epc_intf_data_o_29(29),
EPC_INTF_data_o(30) => epc_intf_data_o_30(30),
EPC_INTF_data_o(31) => epc_intf_data_o_31(31),
EPC_INTF_data_t(0) => epc_intf_data_t_0(0),
EPC_INTF_data_t(1) => epc_intf_data_t_1(1),
EPC_INTF_data_t(2) => epc_intf_data_t_2(2),
EPC_INTF_data_t(3) => epc_intf_data_t_3(3),
EPC_INTF_data_t(4) => epc_intf_data_t_4(4),
EPC_INTF_data_t(5) => epc_intf_data_t_5(5),
EPC_INTF_data_t(6) => epc_intf_data_t_6(6),
EPC_INTF_data_t(7) => epc_intf_data_t_7(7),
EPC_INTF_data_t(8) => epc_intf_data_t_8(8),
EPC_INTF_data_t(9) => epc_intf_data_t_9(9),
EPC_INTF_data_t(10) => epc_intf_data_t_10(10),
EPC_INTF_data_t(11) => epc_intf_data_t_11(11),
EPC_INTF_data_t(12) => epc_intf_data_t_12(12),
EPC_INTF_data_t(13) => epc_intf_data_t_13(13),
EPC_INTF_data_t(14) => epc_intf_data_t_14(14),
EPC_INTF_data_t(15) => epc_intf_data_t_15(15),
EPC_INTF_data_t(16) => epc_intf_data_t_16(16),
EPC_INTF_data_t(17) => epc_intf_data_t_17(17),
EPC_INTF_data_t(18) => epc_intf_data_t_18(18),
EPC_INTF_data_t(19) => epc_intf_data_t_19(19),
EPC_INTF_data_t(20) => epc_intf_data_t_20(20),
EPC_INTF_data_t(21) => epc_intf_data_t_21(21),
EPC_INTF_data_t(22) => epc_intf_data_t_22(22),
EPC_INTF_data_t(23) => epc_intf_data_t_23(23),
EPC_INTF_data_t(24) => epc_intf_data_t_24(24),
EPC_INTF_data_t(25) => epc_intf_data_t_25(25),
EPC_INTF_data_t(26) => epc_intf_data_t_26(26),
EPC_INTF_data_t(27) => epc_intf_data_t_27(27),
EPC_INTF_data_t(28) => epc_intf_data_t_28(28),
EPC_INTF_data_t(29) => epc_intf_data_t_29(29),
EPC_INTF_data_t(30) => epc_intf_data_t_30(30),
EPC_INTF_data_t(31) => epc_intf_data_t_31(31),
EPC_INTF_rd_n => EPC_INTF_rd_n,
EPC_INTF_rdy(0) => EPC_INTF_rdy(0),
EPC_INTF_rnw => EPC_INTF_rnw,
EPC_INTF_rst => EPC_INTF_rst,
EPC_INTF_wr_n => EPC_INTF_wr_n,
FCLK_CLK0 => FCLK_CLK0,
FCLK_RESET0_N => FCLK_RESET0_N,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
GPIO_tri_i(15) => gpio_tri_i_15(15),
GPIO_tri_i(14) => gpio_tri_i_14(14),
GPIO_tri_i(13) => gpio_tri_i_13(13),
GPIO_tri_i(12) => gpio_tri_i_12(12),
GPIO_tri_i(11) => gpio_tri_i_11(11),
GPIO_tri_i(10) => gpio_tri_i_10(10),
GPIO_tri_i(9) => gpio_tri_i_9(9),
GPIO_tri_i(8) => gpio_tri_i_8(8),
GPIO_tri_i(7) => gpio_tri_i_7(7),
GPIO_tri_i(6) => gpio_tri_i_6(6),
GPIO_tri_i(5) => gpio_tri_i_5(5),
GPIO_tri_i(4) => gpio_tri_i_4(4),
GPIO_tri_i(3) => gpio_tri_i_3(3),
GPIO_tri_i(2) => gpio_tri_i_2(2),
GPIO_tri_i(1) => gpio_tri_i_1(1),
GPIO_tri_i(0) => gpio_tri_i_0(0),
GPIO_tri_o(15) => gpio_tri_o_15(15),
GPIO_tri_o(14) => gpio_tri_o_14(14),
GPIO_tri_o(13) => gpio_tri_o_13(13),
GPIO_tri_o(12) => gpio_tri_o_12(12),
GPIO_tri_o(11) => gpio_tri_o_11(11),
GPIO_tri_o(10) => gpio_tri_o_10(10),
GPIO_tri_o(9) => gpio_tri_o_9(9),
GPIO_tri_o(8) => gpio_tri_o_8(8),
GPIO_tri_o(7) => gpio_tri_o_7(7),
GPIO_tri_o(6) => gpio_tri_o_6(6),
GPIO_tri_o(5) => gpio_tri_o_5(5),
GPIO_tri_o(4) => gpio_tri_o_4(4),
GPIO_tri_o(3) => gpio_tri_o_3(3),
GPIO_tri_o(2) => gpio_tri_o_2(2),
GPIO_tri_o(1) => gpio_tri_o_1(1),
GPIO_tri_o(0) => gpio_tri_o_0(0),
GPIO_tri_t(15) => gpio_tri_t_15(15),
GPIO_tri_t(14) => gpio_tri_t_14(14),
GPIO_tri_t(13) => gpio_tri_t_13(13),
GPIO_tri_t(12) => gpio_tri_t_12(12),
GPIO_tri_t(11) => gpio_tri_t_11(11),
GPIO_tri_t(10) => gpio_tri_t_10(10),
GPIO_tri_t(9) => gpio_tri_t_9(9),
GPIO_tri_t(8) => gpio_tri_t_8(8),
GPIO_tri_t(7) => gpio_tri_t_7(7),
GPIO_tri_t(6) => gpio_tri_t_6(6),
GPIO_tri_t(5) => gpio_tri_t_5(5),
GPIO_tri_t(4) => gpio_tri_t_4(4),
GPIO_tri_t(3) => gpio_tri_t_3(3),
GPIO_tri_t(2) => gpio_tri_t_2(2),
GPIO_tri_t(1) => gpio_tri_t_1(1),
GPIO_tri_t(0) => gpio_tri_t_0(0),
IIC_0_scl_i => iic_0_scl_i,
IIC_0_scl_o => iic_0_scl_o,
IIC_0_scl_t => iic_0_scl_t,
IIC_0_sda_i => iic_0_sda_i,
IIC_0_sda_o => iic_0_sda_o,
IIC_0_sda_t => iic_0_sda_t,
IIC_1_scl_i => iic_1_scl_i,
IIC_1_scl_o => iic_1_scl_o,
IIC_1_scl_t => iic_1_scl_t,
IIC_1_sda_i => iic_1_sda_i,
IIC_1_sda_o => iic_1_sda_o,
IIC_1_sda_t => iic_1_sda_t,
IIC_scl_i => iic_scl_i,
IIC_scl_o => iic_scl_o,
IIC_scl_t => iic_scl_t,
IIC_sda_i => iic_sda_i,
IIC_sda_o => iic_sda_o,
IIC_sda_t => iic_sda_t,
Int0(0) => Int0(0),
Int1(0) => Int1(0),
Int2(0) => Int2(0),
Int3(0) => Int3(0),
OCXO_CLK100 => OCXO_CLK100,
OCXO_RESETN(0) => OCXO_RESETN(0),
UART_0_rxd => UART_0_rxd,
UART_0_txd => UART_0_txd,
Vp_Vn_v_n => Vp_Vn_v_n,
Vp_Vn_v_p => Vp_Vn_v_p
);
epc_intf_data_iobuf_0: component IOBUF
port map (
I => epc_intf_data_o_0(0),
IO => epc_intf_data_io(0),
O => epc_intf_data_i_0(0),
T => epc_intf_data_t_0(0)
);
epc_intf_data_iobuf_1: component IOBUF
port map (
I => epc_intf_data_o_1(1),
IO => epc_intf_data_io(1),
O => epc_intf_data_i_1(1),
T => epc_intf_data_t_1(1)
);
epc_intf_data_iobuf_10: component IOBUF
port map (
I => epc_intf_data_o_10(10),
IO => epc_intf_data_io(10),
O => epc_intf_data_i_10(10),
T => epc_intf_data_t_10(10)
);
epc_intf_data_iobuf_11: component IOBUF
port map (
I => epc_intf_data_o_11(11),
IO => epc_intf_data_io(11),
O => epc_intf_data_i_11(11),
T => epc_intf_data_t_11(11)
);
epc_intf_data_iobuf_12: component IOBUF
port map (
I => epc_intf_data_o_12(12),
IO => epc_intf_data_io(12),
O => epc_intf_data_i_12(12),
T => epc_intf_data_t_12(12)
);
epc_intf_data_iobuf_13: component IOBUF
port map (
I => epc_intf_data_o_13(13),
IO => epc_intf_data_io(13),
O => epc_intf_data_i_13(13),
T => epc_intf_data_t_13(13)
);
epc_intf_data_iobuf_14: component IOBUF
port map (
I => epc_intf_data_o_14(14),
IO => epc_intf_data_io(14),
O => epc_intf_data_i_14(14),
T => epc_intf_data_t_14(14)
);
epc_intf_data_iobuf_15: component IOBUF
port map (
I => epc_intf_data_o_15(15),
IO => epc_intf_data_io(15),
O => epc_intf_data_i_15(15),
T => epc_intf_data_t_15(15)
);
epc_intf_data_iobuf_16: component IOBUF
port map (
I => epc_intf_data_o_16(16),
IO => epc_intf_data_io(16),
O => epc_intf_data_i_16(16),
T => epc_intf_data_t_16(16)
);
epc_intf_data_iobuf_17: component IOBUF
port map (
I => epc_intf_data_o_17(17),
IO => epc_intf_data_io(17),
O => epc_intf_data_i_17(17),
T => epc_intf_data_t_17(17)
);
epc_intf_data_iobuf_18: component IOBUF
port map (
I => epc_intf_data_o_18(18),
IO => epc_intf_data_io(18),
O => epc_intf_data_i_18(18),
T => epc_intf_data_t_18(18)
);
epc_intf_data_iobuf_19: component IOBUF
port map (
I => epc_intf_data_o_19(19),
IO => epc_intf_data_io(19),
O => epc_intf_data_i_19(19),
T => epc_intf_data_t_19(19)
);
epc_intf_data_iobuf_2: component IOBUF
port map (
I => epc_intf_data_o_2(2),
IO => epc_intf_data_io(2),
O => epc_intf_data_i_2(2),
T => epc_intf_data_t_2(2)
);
epc_intf_data_iobuf_20: component IOBUF
port map (
I => epc_intf_data_o_20(20),
IO => epc_intf_data_io(20),
O => epc_intf_data_i_20(20),
T => epc_intf_data_t_20(20)
);
epc_intf_data_iobuf_21: component IOBUF
port map (
I => epc_intf_data_o_21(21),
IO => epc_intf_data_io(21),
O => epc_intf_data_i_21(21),
T => epc_intf_data_t_21(21)
);
epc_intf_data_iobuf_22: component IOBUF
port map (
I => epc_intf_data_o_22(22),
IO => epc_intf_data_io(22),
O => epc_intf_data_i_22(22),
T => epc_intf_data_t_22(22)
);
epc_intf_data_iobuf_23: component IOBUF
port map (
I => epc_intf_data_o_23(23),
IO => epc_intf_data_io(23),
O => epc_intf_data_i_23(23),
T => epc_intf_data_t_23(23)
);
epc_intf_data_iobuf_24: component IOBUF
port map (
I => epc_intf_data_o_24(24),
IO => epc_intf_data_io(24),
O => epc_intf_data_i_24(24),
T => epc_intf_data_t_24(24)
);
epc_intf_data_iobuf_25: component IOBUF
port map (
I => epc_intf_data_o_25(25),
IO => epc_intf_data_io(25),
O => epc_intf_data_i_25(25),
T => epc_intf_data_t_25(25)
);
epc_intf_data_iobuf_26: component IOBUF
port map (
I => epc_intf_data_o_26(26),
IO => epc_intf_data_io(26),
O => epc_intf_data_i_26(26),
T => epc_intf_data_t_26(26)
);
epc_intf_data_iobuf_27: component IOBUF
port map (
I => epc_intf_data_o_27(27),
IO => epc_intf_data_io(27),
O => epc_intf_data_i_27(27),
T => epc_intf_data_t_27(27)
);
epc_intf_data_iobuf_28: component IOBUF
port map (
I => epc_intf_data_o_28(28),
IO => epc_intf_data_io(28),
O => epc_intf_data_i_28(28),
T => epc_intf_data_t_28(28)
);
epc_intf_data_iobuf_29: component IOBUF
port map (
I => epc_intf_data_o_29(29),
IO => epc_intf_data_io(29),
O => epc_intf_data_i_29(29),
T => epc_intf_data_t_29(29)
);
epc_intf_data_iobuf_3: component IOBUF
port map (
I => epc_intf_data_o_3(3),
IO => epc_intf_data_io(3),
O => epc_intf_data_i_3(3),
T => epc_intf_data_t_3(3)
);
epc_intf_data_iobuf_30: component IOBUF
port map (
I => epc_intf_data_o_30(30),
IO => epc_intf_data_io(30),
O => epc_intf_data_i_30(30),
T => epc_intf_data_t_30(30)
);
epc_intf_data_iobuf_31: component IOBUF
port map (
I => epc_intf_data_o_31(31),
IO => epc_intf_data_io(31),
O => epc_intf_data_i_31(31),
T => epc_intf_data_t_31(31)
);
epc_intf_data_iobuf_4: component IOBUF
port map (
I => epc_intf_data_o_4(4),
IO => epc_intf_data_io(4),
O => epc_intf_data_i_4(4),
T => epc_intf_data_t_4(4)
);
epc_intf_data_iobuf_5: component IOBUF
port map (
I => epc_intf_data_o_5(5),
IO => epc_intf_data_io(5),
O => epc_intf_data_i_5(5),
T => epc_intf_data_t_5(5)
);
epc_intf_data_iobuf_6: component IOBUF
port map (
I => epc_intf_data_o_6(6),
IO => epc_intf_data_io(6),
O => epc_intf_data_i_6(6),
T => epc_intf_data_t_6(6)
);
epc_intf_data_iobuf_7: component IOBUF
port map (
I => epc_intf_data_o_7(7),
IO => epc_intf_data_io(7),
O => epc_intf_data_i_7(7),
T => epc_intf_data_t_7(7)
);
epc_intf_data_iobuf_8: component IOBUF
port map (
I => epc_intf_data_o_8(8),
IO => epc_intf_data_io(8),
O => epc_intf_data_i_8(8),
T => epc_intf_data_t_8(8)
);
epc_intf_data_iobuf_9: component IOBUF
port map (
I => epc_intf_data_o_9(9),
IO => epc_intf_data_io(9),
O => epc_intf_data_i_9(9),
T => epc_intf_data_t_9(9)
);
gpio_tri_iobuf_0: component IOBUF
port map (
I => gpio_tri_o_0(0),
IO => gpio_tri_io(0),
O => gpio_tri_i_0(0),
T => gpio_tri_t_0(0)
);
gpio_tri_iobuf_1: component IOBUF
port map (
I => gpio_tri_o_1(1),
IO => gpio_tri_io(1),
O => gpio_tri_i_1(1),
T => gpio_tri_t_1(1)
);
gpio_tri_iobuf_10: component IOBUF
port map (
I => gpio_tri_o_10(10),
IO => gpio_tri_io(10),
O => gpio_tri_i_10(10),
T => gpio_tri_t_10(10)
);
gpio_tri_iobuf_11: component IOBUF
port map (
I => gpio_tri_o_11(11),
IO => gpio_tri_io(11),
O => gpio_tri_i_11(11),
T => gpio_tri_t_11(11)
);
gpio_tri_iobuf_12: component IOBUF
port map (
I => gpio_tri_o_12(12),
IO => gpio_tri_io(12),
O => gpio_tri_i_12(12),
T => gpio_tri_t_12(12)
);
gpio_tri_iobuf_13: component IOBUF
port map (
I => gpio_tri_o_13(13),
IO => gpio_tri_io(13),
O => gpio_tri_i_13(13),
T => gpio_tri_t_13(13)
);
gpio_tri_iobuf_14: component IOBUF
port map (
I => gpio_tri_o_14(14),
IO => gpio_tri_io(14),
O => gpio_tri_i_14(14),
T => gpio_tri_t_14(14)
);
gpio_tri_iobuf_15: component IOBUF
port map (
I => gpio_tri_o_15(15),
IO => gpio_tri_io(15),
O => gpio_tri_i_15(15),
T => gpio_tri_t_15(15)
);
gpio_tri_iobuf_2: component IOBUF
port map (
I => gpio_tri_o_2(2),
IO => gpio_tri_io(2),
O => gpio_tri_i_2(2),
T => gpio_tri_t_2(2)
);
gpio_tri_iobuf_3: component IOBUF
port map (
I => gpio_tri_o_3(3),
IO => gpio_tri_io(3),
O => gpio_tri_i_3(3),
T => gpio_tri_t_3(3)
);
gpio_tri_iobuf_4: component IOBUF
port map (
I => gpio_tri_o_4(4),
IO => gpio_tri_io(4),
O => gpio_tri_i_4(4),
T => gpio_tri_t_4(4)
);
gpio_tri_iobuf_5: component IOBUF
port map (
I => gpio_tri_o_5(5),
IO => gpio_tri_io(5),
O => gpio_tri_i_5(5),
T => gpio_tri_t_5(5)
);
gpio_tri_iobuf_6: component IOBUF
port map (
I => gpio_tri_o_6(6),
IO => gpio_tri_io(6),
O => gpio_tri_i_6(6),
T => gpio_tri_t_6(6)
);
gpio_tri_iobuf_7: component IOBUF
port map (
I => gpio_tri_o_7(7),
IO => gpio_tri_io(7),
O => gpio_tri_i_7(7),
T => gpio_tri_t_7(7)
);
gpio_tri_iobuf_8: component IOBUF
port map (
I => gpio_tri_o_8(8),
IO => gpio_tri_io(8),
O => gpio_tri_i_8(8),
T => gpio_tri_t_8(8)
);
gpio_tri_iobuf_9: component IOBUF
port map (
I => gpio_tri_o_9(9),
IO => gpio_tri_io(9),
O => gpio_tri_i_9(9),
T => gpio_tri_t_9(9)
);
iic_0_scl_iobuf: component IOBUF
port map (
I => iic_0_scl_o,
IO => iic_0_scl_io,
O => iic_0_scl_i,
T => iic_0_scl_t
);
iic_0_sda_iobuf: component IOBUF
port map (
I => iic_0_sda_o,
IO => iic_0_sda_io,
O => iic_0_sda_i,
T => iic_0_sda_t
);
iic_1_scl_iobuf: component IOBUF
port map (
I => iic_1_scl_o,
IO => iic_1_scl_io,
O => iic_1_scl_i,
T => iic_1_scl_t
);
iic_1_sda_iobuf: component IOBUF
port map (
I => iic_1_sda_o,
IO => iic_1_sda_io,
O => iic_1_sda_i,
T => iic_1_sda_t
);
iic_scl_iobuf: component IOBUF
port map (
I => iic_scl_o,
IO => iic_scl_io,
O => iic_scl_i,
T => iic_scl_t
);
iic_sda_iobuf: component IOBUF
port map (
I => iic_sda_o,
IO => iic_sda_io,
O => iic_sda_i,
T => iic_sda_t
);
end STRUCTURE;
| gpl-3.0 | c0c4bfdd648be2d96969684625de5d5e | 0.572989 | 2.550837 | false | false | false | false |
peteut/nvc | test/sem/array.vhd | 1 | 10,824 | package p is
type int_array is array (integer range <>) of integer;
type ten_ints is array (1 to 10) of integer;
end package;
entity e is
end entity;
use work.p.all;
architecture a of e is
-- All these declarations are OK
signal x : int_array(1 to 5);
signal y : ten_ints;
signal z : int_array(1 to 3) := ( 0, 1, 2 );
signal m : int_array(1 to 3) := ( 1 to 3 => 0 );
alias a : int_array(2 to 3) is x(2 to 3);
begin
process is
-- Positional elements cannot follow named
variable e : int_array(1 to 2) := (
0 => 1, 2 );
begin
end process;
process is
-- Others element must be last
variable e : ten_ints := ( others => 5, 1 => 2 );
begin
end process;
process is
-- Only one others element
variable e : ten_ints := ( others => 5, others => 2 );
begin
end process;
process is
-- Single element aggregates must be named
variable a : int_array(0 to 0) := ( 0 => 1 );
variable b : int_array(0 to 0) := ( 1 ); -- Error
begin
end process;
process is
variable a : integer;
begin
x(0) <= 1; -- OK
x <= ( others => 2 ); -- OK
x <= 1; -- RHS not array
a := x(0); -- OK
a := x; -- LHS not array
end process;
process is
variable b : boolean;
begin
b := z = m; -- OK
b := z /= m; -- OK
b := z = y; -- Different types
end process;
process is
begin
x(1 to 3) <= z;
x(1 to 2) <= z(1 to 2);
x(x'range) <= (others => 0);
end process;
process is
begin
a(2) <= 4; -- OK
y(2) <= 1; -- OK
end process;
process is
type int2d is array (1 to 10, 1 to 4) of integer;
variable w : int2d := ( 1 => ( 1, 2, 3, 4 ),
2 => ( others => 5 ),
others => ( others => 0 ) );
begin
w(2, 4) := 6;
w(6) := 6; -- Too few indices
w(6, 7, 2) := 2; -- Too many indices
end process;
process is
type letter is (A, B, C);
type larray is array (letter) of integer;
variable w : larray;
begin
w(A) := 2; -- OK
w(5) := 66; -- Wrong index type
end process;
process is
variable n : int_array(1 to 3) := ( 0, 1 => 1, others => 2 ); -- Error
begin
end process;
process is
variable x : integer;
constant c : integer := 3;
variable y : int_array(1 to 3);
begin
y := ( 1 => 2, 2 => 3, x => 5 ); -- Error
y := ( 1 => 2, 2 => 3, c => 5 ); -- OK
end process;
process is
variable x : integer;
variable y : int_array(3 downto 0);
begin
x(1 to 3) := (others => 4); -- Error
y(1 to 3) := (others => 4); -- Error
assert y = (others => 4); -- Error
end process;
process is
subtype four_ints is int_array(1 to 4);
variable x : four_ints;
begin
x(1 to 3) := (1, 2, 3); -- OK
x(2) := 1; -- OK
x(3 downto 1) := (others => '0'); -- Error
assert x(2) = 5; -- OK
end process;
process is
function foo(size: integer) return int_array is
subtype rtype is int_array(size-1 downto 0);
variable result: rtype;
begin
assert result(0) = 1;
return result;
end;
begin
end process;
process is
function plus(A, B: int_array) return int_array is
variable BV, sum: int_array(A'left downto 0);
begin
return sum;
end;
begin
end process;
process is
subtype int4_t is int_array(1 to 4);
type foo_t is array (integer'left to 10) of integer;
variable v : int_array(foo_t'range);
variable u : foo_t;
begin
assert int4_t'length = 4;
assert foo_t'length = 50;
end process;
process is
subtype a_to_c is character range 'a' to 'c';
type abc_ints is array (a_to_c) of integer;
variable v : abc_ints;
begin
assert abc_ints'length = 3;
v('b') := 2;
end process;
process is
type bit_map is array (bit) of integer;
variable b : bit_map := ( '0' => 5, '1' => 6 );
type bit_map2 is array (bit, 0 to 1) of integer;
variable c : bit_map2 := (
'0' => (0 => 0, 1 => 1),
'1' => (0 => 2, 1 => 3) );
begin
b('0') := 6;
c('1', 1) := 5;
end process;
process is
constant c : ten_ints := (ten_ints'range => 5);
variable v : ten_ints;
begin
v := (v'range => 6); -- OK
end process;
process is
type mybit is ('0', '1');
type bit_map is array (bit range '0' to '1') of integer;
variable v : bit_map;
variable b : bit;
begin
v(b) := 1; -- OK
end process;
process is
begin
assert x'length(1) = 5; -- OK
end process;
process is
type bad is array (integer range <>) of int_array; -- Error
begin
end process;
process is
type int2d is array (natural range <>, natural range <>) of integer;
constant c : int2d := ( (0, 1, 2), (0, 1, 2) ); -- OK
constant d : int2d := ( (0, 1), (5, 6, 7) ); -- OK (at sem)
constant e : int2d := ( (0, 1), (others => 2) ); -- Error
begin
end process;
process is
variable b1 : bit_vector(7 downto 0);
begin
b1 := b1 sll 1;
b1 := b1 srl 2;
b1 := b1 sla 0;
b1 := b1 sra 1;
b1 := b1 rol 6;
b1 := b1 ror 1;
end process;
process is
variable i : integer;
alias xi is x(1 to i); -- Error
alias zi : integer is z(i); -- Error
alias xx : integer is x(1 to 2); -- Error
begin
end process;
process is
variable i : integer;
begin
i(6) := 2; -- Error
end process;
process is
constant c : integer := -1;
type bad_range is array (-1 to -5) of integer; -- Error
type ok_range is array(c to -5) of integer; -- OK
begin
end process;
process is
subtype bad_sub1 is int_array(1 to 3, 2 to 5); -- Error
begin
end process;
process is
type element is array (integer range 0 to 1) of bit_vector( 0 to 1);
begin
end process;
process is
type ten_ten_ints is array (1 to 10) of ten_ints;
type int2d is array (natural range <>, natural range <>) of integer;
variable t1, t2 : ten_ten_ints;
variable m1, m2 : int2d(1 to 3, 1 to 3);
begin
assert t1 = t2; -- OK
assert t1 /= t2; -- OK
assert t1 < t2; -- OK
assert t1 > t2; -- OK
assert m1 = m2; -- OK
assert m1 < m2; -- Error
end process;
process is
subtype num_array is int_array; -- OK
subtype bad_array is not_here; -- Error
variable a1 : num_array(1 to 3); -- OK
variable a2 : num_array; -- Error
begin
end process;
process is
constant k : integer := 5;
type a is array (k) of integer; -- Error
variable v : a; -- Error
begin
end process;
process is
type ibv is array (boolean range <>) of integer;
variable a : ibv(false to true);
begin
a(false) := 1; -- OK
a(4) := 2; -- Error
a(false to false) := (others => 1); -- OK
end process;
process is
subtype r is integer range 1 to 3;
begin
x(r'range) <= (others => 1);
x(r) <= (others => 1);
end process;
process is
subtype str is string;
constant x : str := "hello"; -- OK
begin
end process;
process is
type barry2d is array (boolean range <>, boolean range <>)
of integer;
variable b : barry2d(false to true, false to true);
type ibarray2d is array (integer range <>, boolean range <>)
of integer;
variable ib : ibarray2d(1 to 5, false to true);
begin
b(barry2d'left(1), barry2d'left(2)) := 5; -- OK
ib(integer'(5), boolean'(true)) := 1; -- OK
ib(ibarray2d'left(1), ibarray2d'left(2)) := 5; -- OK
end process;
process is
type enum1 is (m1, m2, m3, m4, m5);
type abase is array (enum1 range <>) of boolean;
subtype a1 is abase(enum1 range m1 to m5);
variable V1 : A1;
begin
assert v1 = (false, false, false); -- OK
end process;
process is
variable x : int_array(1 to 3);
begin
x := (1 | 2 to 3 => 5); -- OK
end process;
process is
variable b : bit_vector(1 to 3); -- OK
begin
b := "1fe"; -- Error
end process;
issue86: block is
type integer_vector is array (natural range <>) of integer;
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector;
function inside0 (constant E : ElementType;
constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop -- OK (issue #86)
if E = A(i) then
return TRUE;
end if ;
end loop ;
return FALSE ;
end function inside0;
begin
end block;
process is
subtype bad is ten_ints (1 to 4); -- Error
constant c : ten_ints(2 to 4) := (others => 0); -- Error
begin
end process;
process is
type e is (one, two, three);
type arr is array (e range <>) of integer;
constant c : arr := (1, 2, 3, 4);
begin
end process;
no_file_types: block is
type t_int_file is file of integer;
type t_file_array is array (0 to 1) of t_int_file; -- Error
begin
end block;
billowitch_tc586: block is
type real_cons_vector is array (15 downto 0) of real;
type real_cons_vector_file is file of real_cons_vector;
constant C19 : real_cons_vector := (others => 3.0); -- OK
begin
end block;
end architecture;
| gpl-3.0 | 6aaa7ea5c2b1b36bae383ad5cc9fb67b | 0.471822 | 3.753121 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/util_pkg_tb.vhd | 1 | 3,053 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : util_pkg_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-08-11
-- Last update: 2018-01-20
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Testbench for util package
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-08-11 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity util_pkg_tb is
end util_pkg_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.tb_pkg.all;
use work.util_pkg.all;
architecture STRUCTURE of util_pkg_tb is
SIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL i : std_logic;
SIGNAL i_vec : std_logic_vector(31 downto 0);
SIGNAL d : std_logic;
SIGNAL d_vec : std_logic_vector(31 downto 0);
type vec_arr is array (natural range <>) of std_logic_vector(31 downto 0);
SIGNAL q_vec : vec_arr(31 downto 0);
SIGNAL q_sig : std_logic_vector(31 downto 0);
SIGNAL q_pulse : std_logic_vector(31 downto 0);
SIGNAL q_stretch : std_logic_vector(31 downto 0);
begin
clk_100MHZ: clk_gen(10 ns, 50, clk);
reset: rst_n_gen(1 us, rst_n);
process
begin
i <= '0';
i_vec <= (others => '0');
run_clk(clk, 200);
i <= '1';
i_vec <= x"5555aaaa";
run_clk(clk, 1);
i <= '0';
i_vec <= (others => '0');
run_clk(clk, 64);
for j in 0 to 32 loop
i <= '1';
i_vec <= x"5555aaaa";
run_clk(clk, 1);
i <= '0';
i_vec <= (others => '0');
run_clk(clk, j);
end loop;
wait;
end process;
-- So the test input lines up with the clock edge...
d_s: delay_sig generic map (1) port map (rst_n, clk, i, d);
d_v: delay_vec generic map (1) port map (rst_n, clk, i_vec, d_vec);
tests:
for i in 0 to 31 generate
s: delay_sig generic map (i) port map (rst_n, clk, d, q_sig(i));
v: delay_vec generic map (i) port map (rst_n, clk, d_vec, q_vec(i));
p: delay_pulse generic map (i) port map (rst_n, clk, d, q_pulse(i));
st: pulse_stretch generic map (i) port map (rst_n, clk, d, q_stretch(i));
end generate;
end STRUCTURE;
| gpl-3.0 | ce93f4f234b8d1ccddcffb24ccc1edf9 | 0.452997 | 3.604486 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_dgen.vhd | 1 | 5,145 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.wr_fifo32to256_pkg.ALL;
ENTITY wr_fifo32to256_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF wr_fifo32to256_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
SIGNAL wr_d_sel : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '0');
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:wr_fifo32to256_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= (AND_REDUCE(wr_d_sel)) AND PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DOUT_WIDTH-C_DIN_WIDTH*conv_integer(wr_d_sel)-1 DOWNTO C_DOUT_WIDTH-C_DIN_WIDTH*(conv_integer(wr_d_sel)+1));
PROCESS(WR_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
wr_d_sel <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK = '1') THEN
IF(FULL = '0' AND PRC_WR_EN = '1') THEN
wr_d_sel <= wr_d_sel + "1";
END IF;
END IF;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 18959b24c7ad8f9e7844561d81310ab8 | 0.594947 | 3.976043 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_pctrl.vhd | 1 | 18,385 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_eb_fifo_counted_resized_pkg.ALL;
ENTITY k7_eb_fifo_counted_resized_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF k7_eb_fifo_counted_resized_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:k7_eb_fifo_counted_resized_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:k7_eb_fifo_counted_resized_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | f643facbc58cf11406e9dbe062d61f94 | 0.510742 | 3.244794 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weights/simulation/weights_tb.vhd | 1 | 4,316 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: weights_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY weights_tb IS
END ENTITY;
ARCHITECTURE weights_tb_ARCH OF weights_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
weights_synth_inst:ENTITY work.weights_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-2-clause | 95c1db33c672da92b9e22f3b31aa7e7a | 0.620019 | 4.701525 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64.vhd | 1 | 6,170 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_bram4096x64.vhd when simulating
-- the core, k7_bram4096x64. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_bram4096x64 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END k7_bram4096x64;
ARCHITECTURE k7_bram4096x64_a OF k7_bram4096x64 IS
-- synthesis translate_off
COMPONENT wrapped_k7_bram4096x64
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_bram4096x64 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 8,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "kintex7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 1,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 64,
c_read_width_b => 64,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 1,
c_use_byte_web => 1,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 8,
c_web_width => 8,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 64,
c_write_width_b => 64,
c_xdevicefamily => "kintex7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_bram4096x64
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END k7_bram4096x64_a;
| gpl-2.0 | 8bef6e2199fc80cf9245946beaab5fa4 | 0.541977 | 3.820433 | false | false | false | false |
ObKo/USBCore | Examples/SPI_Flasher/spi_flasher.vhdl | 1 | 11,634 | --
-- USB Full-Speed/Hi-Speed Device Controller core - spi_flasher.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity spi_flasher is
port (
led : out std_logic;
ulpi_data : inout std_logic_vector(7 downto 0);
ulpi_dir : in std_logic;
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_reset : out std_logic;
ulpi_clk60 : in std_logic;
spi_cs : out std_logic;
spi_sck : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic
);
end spi_flasher;
architecture spi_flasher of spi_flasher is
constant USE_HIGH_SPEED: boolean := true;
constant CONFIG_DESC : BYTE_ARRAY(0 to 8) := (
X"09", -- bLength = 9
X"02", -- bDescriptionType = Configuration Descriptor
X"20", X"00", -- wTotalLength = 32
X"01", -- bNumInterfaces = 1
X"01", -- bConfigurationValue
X"00", -- iConfiguration
X"C0", -- bmAttributes = Self-powered
X"32" -- bMaxPower = 100 mA
);
constant INTERFACE_DESC : BYTE_ARRAY(0 to 8) := (
X"09", -- bLength = 9
X"04", -- bDescriptorType = Interface Descriptor
X"00", -- bInterfaceNumber = 0
X"00", -- bAlternateSetting
X"02", -- bNumEndpoints = 2
X"00", -- bInterfaceClass
X"00", -- bInterfaceSubClass
X"00", -- bInterfaceProtocol
X"00" -- iInterface
);
constant EP1_IN_DESC : BYTE_ARRAY(0 to 6) := (
X"07", -- bLength = 7
X"05", -- bDescriptorType = Endpoint Descriptor
X"81", -- bEndpointAddress = IN1
B"00_00_00_10", -- bmAttributes = Bulk
X"00", X"02", -- wMaxPacketSize = 512 bytes
X"00" -- bInterval
);
constant EP1_OUT_DESC : BYTE_ARRAY(0 to 6) := (
X"07", -- bLength = 7
X"05", -- bDescriptorType = Endpoint Descriptor
X"01", -- bEndpointAddress = OUT1
B"00_00_00_10", -- bmAttributes = Bulk
X"00", X"02", -- wMaxPacketSize = 512 bytes
X"00" -- bInterval
);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal usb_clk : std_logic;
signal usb_reset : std_logic;
signal usb_idle : std_logic;
signal usb_suspend : std_logic;
signal usb_configured : std_logic;
signal usb_crc_error : std_logic;
signal usb_sof : std_logic;
signal ctl_xfer_endpoint : std_logic_vector(3 downto 0);
signal ctl_xfer_type : std_logic_vector(7 downto 0);
signal ctl_xfer_request : std_logic_vector(7 downto 0);
signal ctl_xfer_value : std_logic_vector(15 downto 0);
signal ctl_xfer_index : std_logic_vector(15 downto 0);
signal ctl_xfer_length : std_logic_vector(15 downto 0);
signal ctl_xfer_accept : std_logic;
signal ctl_xfer : std_logic;
signal ctl_xfer_done : std_logic;
signal ctl_xfer_data_out : std_logic_vector(7 downto 0);
signal ctl_xfer_data_out_valid: std_logic;
signal ctl_xfer_data_in : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid : std_logic;
signal ctl_xfer_data_in_last : std_logic;
signal ctl_xfer_data_in_ready : std_logic;
signal blk_xfer_endpoint : std_logic_vector(3 downto 0);
signal blk_in_xfer : std_logic;
signal blk_out_xfer : std_logic;
signal blk_xfer_in_has_data : std_logic;
signal blk_xfer_in_data : std_logic_vector(7 downto 0);
signal blk_xfer_in_data_valid : std_logic;
signal blk_xfer_in_data_ready : std_logic;
signal blk_xfer_in_data_last : std_logic;
signal blk_xfer_out_ready_read: std_logic;
signal blk_xfer_out_data : std_logic_vector(7 downto 0);
signal blk_xfer_out_data_valid: std_logic;
signal led_counter : std_logic_vector(25 downto 0);
component usb_flasher is
port (
clk : in std_logic;
rst : in std_logic;
ctl_xfer_endpoint : in std_logic_vector(3 downto 0);
ctl_xfer_type : in std_logic_vector(7 downto 0);
ctl_xfer_request : in std_logic_vector(7 downto 0);
ctl_xfer_value : in std_logic_vector(15 downto 0);
ctl_xfer_index : in std_logic_vector(15 downto 0);
ctl_xfer_length : in std_logic_vector(15 downto 0);
ctl_xfer_accept : out std_logic;
ctl_xfer : in std_logic;
ctl_xfer_done : out std_logic;
ctl_xfer_data_out : in std_logic_vector(7 downto 0);
ctl_xfer_data_out_valid : in std_logic;
ctl_xfer_data_in : out std_logic_vector(7 downto 0);
ctl_xfer_data_in_valid : out std_logic;
ctl_xfer_data_in_last : out std_logic;
ctl_xfer_data_in_ready : in std_logic;
blk_xfer_endpoint : in std_logic_vector(3 downto 0);
blk_in_xfer : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
spi_cs : out std_logic;
spi_sck : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic
);
end component;
begin
ULPI_IO: for i in 7 downto 0 generate
begin
ULPI_IOBUF : IOBUF
port map (
O => ulpi_data_in(i),
IO => ulpi_data(i),
I => ulpi_data_out(i),
T => ulpi_dir
);
end generate;
USB_CONTROLLER: usb_tlp
generic map (
VENDOR_ID => X"DEAD",
PRODUCT_ID => X"BEEF",
MANUFACTURER => "USBCore",
PRODUCT => "SPI Flasher",
SERIAL => "",
CONFIG_DESC => CONFIG_DESC & INTERFACE_DESC &
EP1_IN_DESC & EP1_OUT_DESC,
HIGH_SPEED => USE_HIGH_SPEED
)
port map (
ulpi_data_in => ulpi_data_in,
ulpi_data_out => ulpi_data_out,
ulpi_dir => ulpi_dir,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_reset => ulpi_reset,
ulpi_clk60 => ulpi_clk60,
usb_clk => usb_clk,
usb_reset => usb_reset,
usb_idle => usb_idle,
usb_suspend => usb_suspend,
usb_configured => usb_configured,
usb_crc_error => usb_crc_error,
usb_sof => usb_sof,
ctl_xfer_endpoint => ctl_xfer_endpoint,
ctl_xfer_type => ctl_xfer_type,
ctl_xfer_request => ctl_xfer_request,
ctl_xfer_value => ctl_xfer_value,
ctl_xfer_index => ctl_xfer_index,
ctl_xfer_length => ctl_xfer_length,
ctl_xfer_accept => ctl_xfer_accept,
ctl_xfer => ctl_xfer,
ctl_xfer_done => ctl_xfer_done,
ctl_xfer_data_out => ctl_xfer_data_out,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid,
ctl_xfer_data_in => ctl_xfer_data_in,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid,
ctl_xfer_data_in_last => ctl_xfer_data_in_last,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready,
blk_xfer_endpoint => blk_xfer_endpoint,
blk_in_xfer => blk_in_xfer,
blk_out_xfer => blk_out_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid
);
FLASHER: usb_flasher
port map (
clk => usb_clk,
rst => usb_reset,
ctl_xfer_endpoint => ctl_xfer_endpoint,
ctl_xfer_type => ctl_xfer_type,
ctl_xfer_request => ctl_xfer_request,
ctl_xfer_value => ctl_xfer_value,
ctl_xfer_index => ctl_xfer_index,
ctl_xfer_length => ctl_xfer_length,
ctl_xfer_accept => ctl_xfer_accept,
ctl_xfer => ctl_xfer,
ctl_xfer_done => ctl_xfer_done,
ctl_xfer_data_out => ctl_xfer_data_out,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid,
ctl_xfer_data_in => ctl_xfer_data_in,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid,
ctl_xfer_data_in_last => ctl_xfer_data_in_last,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready,
blk_xfer_endpoint => blk_xfer_endpoint,
blk_in_xfer => blk_in_xfer,
blk_out_xfer => blk_out_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid,
spi_cs => spi_cs,
spi_sck => spi_sck,
spi_mosi => spi_mosi,
spi_miso => spi_miso
);
COUNT: process(usb_clk) is
begin
if rising_edge(usb_clk) then
led_counter <= led_counter + 1;
end if;
end process;
led <= '1' when usb_idle = '1' AND usb_configured = '1' else
led_counter(led_counter'left) when usb_idle = '1' else
'1' when led_counter(led_counter'left downto led_counter'left - 2) = "000" else
'0';
end spi_flasher;
| mit | 44b5b27b8e92a0cb7ad84e543e6728f2 | 0.566615 | 3.37022 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_10/lab10_3/lpm_ram_dq0.vhd | 1 | 7,357 | -- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (9 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "lab10_3.mif",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 64,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 6,
width_a => 10,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => inclock,
clock1 => outclock,
address_a => address,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "lab10_3.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "64"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "6"
-- Retrieval info: PRIVATE: WidthData NUMERIC "10"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "lab10_3.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL address[5..0]
-- Retrieval info: USED_PORT: data 0 0 10 0 INPUT NODEFVAL data[9..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC inclock
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 10 0 data 0 0 10 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 5787f0faa07f4850740bad61cbb89234 | 0.674867 | 3.439458 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/iic_control.vhd | 2 | 89,082 | -------------------------------------------------------------------------------
-- iic_control.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
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-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
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-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic_control.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the main state machines for the iic
-- bus interface logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
use axi_iic_v2_0.upcnt_n;
use axi_iic_v2_0.shift8;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_ACLK_FREQ_HZ-- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum IIC frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
--
-- Definition of Ports:
-- Sys_clk -- System clock
-- Reset -- System Reset
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Txak -- Value for acknowledge when xmit
-- Gc_en -- General purpose outputs
-- Ro_prev -- Receive over run prevent
-- Dtre -- Data transmit register empty
-- Msms -- Data transmit register empty
-- Msms_rst -- Msms Reset signal
-- Msms_set -- Msms set
-- Rsta -- Repeated start
-- Rsta_rst -- Repeated start Reset
-- Tx -- Master read/write
-- Dtr -- Data transmit register
-- Adr -- IIC slave address
-- Ten_adr -- IIC slave 10 bit address
-- Bb -- Bus busy indicator
-- Dtc -- Data transfer
-- Aas -- Addressed as slave indicator
-- Al -- Arbitration lost indicator
-- Srw -- Slave read/write indicator
-- Txer -- Received acknowledge indicator
-- Abgc -- Addressed by general call indicator
-- Data_i2c -- IIC data for processor
-- New_rcv_dta -- New Receive Data ready
-- Rdy_new_xmt -- New data loaded in shift reg indicator
-- Tx_under_prev -- DTR or Tx FIFO empty IRQ indicator
-- EarlyAckHdr -- ACK_HEADER state strobe signal
-- EarlyAckDataState -- Data ack early acknowledge signal
-- AckDataState -- Data ack acknowledge signal
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic_control is
generic(
C_SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_SIZE : integer := 32;
C_TEN_BIT_ADR : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0 -- SMBUS/PMBUS support
);
port(
-- System signals
Sys_clk : in std_logic;
Reset : in std_logic;
-- iic bus tristate driver control signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Timing_param_tsusta : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsusto : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thdsta : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsudat : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tbuf : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thigh : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tlow : in std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thddat : in std_logic_vector(C_SIZE-1 downto 0);
-- interface signals from uP
Txak : in std_logic;
Gc_en : in std_logic;
Ro_prev : in std_logic;
Dtre : in std_logic;
Msms : in std_logic;
Msms_rst : out std_logic;
Msms_set : in std_logic;
Rsta : in std_logic;
Rsta_rst : out std_logic;
Tx : in std_logic;
Dtr : in std_logic_vector(7 downto 0);
Adr : in std_logic_vector(7 downto 0);
Ten_adr : in std_logic_vector(7 downto 5);
Bb : out std_logic;
Dtc : out std_logic;
Aas : out std_logic;
Al : out std_logic;
Srw : out std_logic;
Txer : out std_logic;
Abgc : out std_logic;
Data_i2c : out std_logic_vector(7 downto 0);
New_rcv_dta : out std_logic;
Rdy_new_xmt : out std_logic;
Tx_under_prev : out std_logic;
EarlyAckHdr : out std_logic;
EarlyAckDataState : out std_logic;
AckDataState : out std_logic;
reg_empty :out std_logic
);
end iic_control;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic_control is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant CLR_REG : std_logic_vector(7 downto 0) := "00000000";
constant START_CNT : std_logic_vector(3 downto 0) := "0000";
constant CNT_DONE : std_logic_vector(3 downto 0) := "1000";
constant ZERO_CNT : std_logic_vector(C_SIZE-1 downto 0):= (others => '0');
constant ZERO : std_logic := '0';
constant ENABLE_N : std_logic := '0';
constant CNT_ALMOST_DONE : std_logic_vector (3 downto 0) := "0111";
type state_type is (IDLE,
HEADER,
ACK_HEADER,
RCV_DATA,
ACK_DATA,
XMIT_DATA,
WAIT_ACK);
signal state : state_type;
type scl_state_type is (SCL_IDLE,
START,
START_EDGE,
SCL_LOW_EDGE,
SCL_LOW,
SCL_HIGH_EDGE,
SCL_HIGH,
STOP_EDGE,
STOP_WAIT);
signal scl_state : scl_state_type;
signal next_scl_state : scl_state_type;
signal scl_rin : std_logic; -- sampled version of scl
signal scl_d1 : std_logic; -- sampled version of scl
signal scl_rin_d1 : std_logic; -- delayed version of Scl_rin
signal scl_cout : std_logic; -- combinatorial scl output
signal scl_cout_reg : std_logic; -- registered version of scl_cout
signal scl_rising_edge : std_logic; -- falling edge of SCL
signal scl_falling_edge : std_logic; -- falling edge of SCL
signal scl_f_edg_d1 : std_logic; -- falling edge of SCL delayed one
-- clock
signal scl_f_edg_d2 : std_logic; -- falling edge of SCL delayed two
-- clock
signal scl_f_edg_d3 : std_logic; -- falling edge of SCL delayed three
-- clock
signal sda_rin : std_logic; -- sampled version of sda
signal sda_d1 : std_logic; -- sampled version of sda
signal sda_rin_d1 : std_logic; -- delayed version of sda_rin
signal sda_falling : std_logic; -- Pulses when SDA falls
signal sda_rising : std_logic; -- Pulses when SDA rises
signal sda_changing : std_logic; -- Pulses when SDA changes
signal sda_setup : std_logic; -- SDA setup time in progress
signal sda_setup_cnt : std_logic_vector (C_SIZE-1 downto 0);
-- SDA setup time count
signal sda_cout : std_logic; -- combinatorial sda output
signal sda_cout_reg : std_logic; -- registered version of sda_cout
signal sda_cout_reg_d1 : std_logic; -- delayed sda output for arb
-- comparison
signal sda_sample : std_logic; -- SDA_RIN sampled at SCL rising edge
signal slave_sda : std_logic; -- sda value when slave
signal master_sda : std_logic; -- sda value when master
signal sda_oe : std_logic;
signal master_slave : std_logic; -- 1 if master, 0 if slave
-- Shift Register and the controls
signal shift_reg : std_logic_vector(7 downto 0); -- iic data shift reg
signal shift_out : std_logic;
signal shift_reg_en : std_logic;
signal shift_reg_ld : std_logic;
signal shift_reg_ld_d1 : std_logic;
signal i2c_header : std_logic_vector(7 downto 0);-- I2C header register
signal i2c_header_en : std_logic;
signal i2c_header_ld : std_logic;
signal i2c_shiftout : std_logic;
-- Used to check slave address detected
signal addr_match : std_logic;
signal arb_lost : std_logic; -- 1 if arbitration is lost
signal msms_d1 : std_logic; -- Msms processed to initiate a stop
-- sequence after data has been transmitted
signal msms_d2 : std_logic; -- delayed sample of msms_d1
signal msms_rst_i : std_logic; -- internal msms_rst
signal detect_start : std_logic; -- START condition has been detected
signal detect_stop : std_logic; -- STOP condition has been detected
signal sm_stop : std_logic; -- STOP condition needs to be generated
-- from state machine
signal bus_busy : std_logic; -- indicates that the bus is busy
-- set when START, cleared when STOP
signal bus_busy_d1 : std_logic; -- delayed sample of bus busy
signal gen_start : std_logic; -- uP wants to generate a START
signal gen_stop : std_logic; -- uP wants to generate a STOP
signal rep_start : std_logic; -- uP wants to generate a repeated START
signal stop_scl : std_logic; -- signal in SCL state machine
-- indicating a STOP
signal stop_scl_reg : std_logic; -- registered version of STOP_SCL
-- Bit counter 0 to 7
signal bit_cnt : std_logic_vector(3 downto 0);
signal bit_cnt_ld : std_logic;
signal bit_cnt_clr : std_logic;
signal bit_cnt_en : std_logic;
-- Clock Counter
signal clk_cnt : std_logic_vector (C_SIZE-1 downto 0);
signal clk_cnt_rst : std_logic;
signal clk_cnt_en : std_logic;
-- the following signals are only here because Viewlogic's VHDL compiler won't
-- allow a constant to be used in a component instantiation
signal reg_clr : std_logic_vector(7 downto 0);
signal zero_sig : std_logic;
signal cnt_zero : std_logic_vector(C_SIZE-1 downto 0);
signal cnt_start : std_logic_vector(3 downto 0);
signal data_i2c_i : std_logic_vector(7 downto 0);
signal aas_i : std_logic; -- internal addressed as slave
-- signal
signal srw_i : std_logic; -- internal slave read write signal
signal abgc_i : std_logic; -- internal addressed by a general
-- call
signal dtc_i : std_logic; -- internal data transmit compete
-- signal
signal dtc_i_d1 : std_logic; -- delayed internal data transmit
-- complete
signal dtc_i_d2 : std_logic; -- 2nd register delay of dtc
signal al_i : std_logic; -- internal arbitration lost signal
signal al_prevent : std_logic; -- prevent arbitration lost when
-- last word
signal rdy_new_xmt_i : std_logic; -- internal ready to transmit new
-- data
signal tx_under_prev_i : std_logic; -- TX underflow prevent signal
signal rsta_tx_under_prev : std_logic; -- Repeated Start Tx underflow
-- prevent
signal rsta_d1 : std_logic; -- Delayed one clock version of Rsta
signal dtre_d1 : std_logic; -- Delayed one clock version of Dtre
signal txer_i : std_logic; -- internal Txer signal
signal txer_edge : std_logic; -- Pulse for Txer IRQ
-- the following signal are used only when 10-bit addressing has been
-- selected
signal msb_wr : std_logic; -- the 1st byte of 10 bit addressing
-- comp
signal msb_wr_d : std_logic; -- delayed version of msb_wr
signal msb_wr_d1 : std_logic; -- delayed version of msb_wr_d
signal sec_addr : std_logic := '0'; -- 2nd byte qualifier
signal sec_adr_match : std_logic; -- 2nd byte compare
signal adr_dta_l : std_logic := '0'; -- prevents 2nd adr byte load
-- in DRR
signal new_rcv_dta_i : std_logic; -- internal New_rcv_dta
signal ro_prev_d1 : std_logic; -- delayed version of Ro_prev
signal gen_stop_and_scl_hi : std_logic; -- signal to prevent SCL state
-- machine from getting stuck during a No Ack
signal setup_cnt_rst : std_logic;
signal tx_under_prev_d1 : std_logic;
signal tx_under_prev_fe : std_logic;
signal rsta_re : std_logic;
signal gen_stop_d1 : std_logic;
signal gen_stop_re : std_logic;
----Mathew
signal shift_cnt : std_logic_vector(8 downto 0);
-- signal reg_empty : std_logic;
----------
begin
----------------------------------------------------------------------------
-- SCL Tristate driver controls for open-collector emulation
----------------------------------------------------------------------------
Scl_T <= '0' when scl_cout_reg = '0'
-- Receive fifo overflow throttle condition
or Ro_prev = '1'
-- SDA changing requires additional setup to SCL change
or (sda_setup = '1' )
-- Restart w/ transmit underflow prevention throttle
-- condition
or rsta_tx_under_prev = '1' else
'1';
Scl_O <= '0';
----------------------------------------------------------------------------
-- SDA Tristate driver controls for open-collector emulation
----------------------------------------------------------------------------
Sda_T <= '0' when ((master_slave = '1' and arb_lost = '0'
and sda_cout_reg = '0')
or (master_slave = '0' and slave_sda = '0')
or stop_scl_reg = '1') else
'1';
Sda_O <= '0';
-- the following signals are only here because Viewlogic's VHDL compiler
-- won't allow a constant to be used in a component instantiation
reg_clr <= CLR_REG;
zero_sig <= ZERO;
cnt_zero <= ZERO_CNT;
cnt_start <= START_CNT;
----------------------------------------------------------------------------
-- INT_DTRE_RSTA_DELAY_PROCESS
----------------------------------------------------------------------------
-- This process delays Dtre and RSTA by one clock to edge detect
-- Dtre = data transmit register empty
-- Rsta = firmware restart command
----------------------------------------------------------------------------
INT_DTRE_RSTA_DELAY_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
rsta_d1 <= '0';
dtre_d1 <= '0';
ro_prev_d1 <= '0';
gen_stop_d1 <= '0';
tx_under_prev_d1 <= '0';
else
rsta_d1 <= Rsta;
dtre_d1 <= Dtre;
ro_prev_d1 <= Ro_prev;
gen_stop_d1 <= gen_stop;
tx_under_prev_d1 <= tx_under_prev_i;
end if;
end if;
end process INT_DTRE_RSTA_DELAY_PROCESS;
tx_under_prev_fe <= tx_under_prev_d1 and not tx_under_prev_i;
rsta_re <= Rsta and not rsta_d1 ;
gen_stop_re <= gen_stop and not gen_stop_d1;
----------------------------------------------------------------------------
-- INT_RSTA_TX_UNDER_PREV_PROCESS
----------------------------------------------------------------------------
-- This process creates a signal that prevent SCL from going high when a
-- underflow condition would be caused, by a repeated start condition.
----------------------------------------------------------------------------
INT_RSTA_TX_UNDER_PREV_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
rsta_tx_under_prev <= '0';
elsif (Rsta = '1' and rsta_d1 = '0' and Dtre = '1' ) then
rsta_tx_under_prev <= '1';
elsif (Dtre = '0' and dtre_d1 = '1') then
rsta_tx_under_prev <= '0';
else
rsta_tx_under_prev <= rsta_tx_under_prev;
end if;
end if;
end process INT_RSTA_TX_UNDER_PREV_PROCESS;
----------------------------------------------------------------------------
-- INT_TX_UNDER_PREV_PROCESS
----------------------------------------------------------------------------
-- This process creates a signal that prevent SCL from going high when a
-- underflow condition would be caused. Transmit underflow can occur in both
-- master and slave situations
----------------------------------------------------------------------------
INT_TX_UNDER_PREV_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
tx_under_prev_i <= '0';
elsif (Dtre = '1' and (state = WAIT_ACK or state = ACK_HEADER)
and scl_falling_edge = '1' and gen_stop = '0'
and ((aas_i = '0' and srw_i = '0')
or (aas_i = '1' and srw_i = '1'))) then
tx_under_prev_i <= '1';
elsif (state = RCV_DATA or state = IDLE or Dtre='0') then
tx_under_prev_i <= '0';
end if;
end if;
end process INT_TX_UNDER_PREV_PROCESS;
Tx_under_prev <= tx_under_prev_i;
----------------------------------------------------------------------------
-- SDASETUP
----------------------------------------------------------------------------
-- Whenever SDA changes there is an associated setup time that must be
-- obeyed before SCL can change. (The exceptions are starts/stops which
-- haven't other timing specifications.) It doesn't matter whether this is
-- a Slave | Master, TX | RX. The "setup" counter and the "sdasetup" process
-- guarantee this time is met regardless of the devices on the bus and their
-- attempts to manage setup time. The signal sda_setup, when asserted,
-- causes SCL to be held low until the setup condition is removed. Anytime a
-- change in SDA is detected on the bus the setup process is invoked. Also,
-- sda_setup is asserted if the transmit throttle condition is active.
-- When it deactivates, SDA **may** change on the SDA bus. In this way,
-- the SCL_STATE machine will be held off as well because it waits for SCL
-- to actually go high.
----------------------------------------------------------------------------
SETUP_CNT : entity axi_iic_v2_0.upcnt_n
generic map (
C_SIZE => C_SIZE
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_zero,
Cnt_en => sda_setup,
Load => sda_changing,
Qout => sda_setup_cnt
);
----------------------------------------------------------------------------
-- SDASETUP Process
----------------------------------------------------------------------------
SDASETUP : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
sda_setup <= '0';
elsif (
-- If SDA is changing on the bus then enforce setup time
sda_changing = '1'
-- or if SDA is about to change ...
or tx_under_prev_i = '1') -- modified
-- For either of the above cases the controller only cares
-- about SDA setup when it is legal to change SDA.
and scl_rin='0' then
sda_setup <= '1';
elsif (sda_setup_cnt=Timing_param_tsudat) then
sda_setup <= '0';
end if;
end if;
end process SDASETUP;
----------------------------------------------------------------------------
-- Arbitration Process
-- This process checks the master's outgoing SDA with the incoming SDA to
-- determine if control of the bus has been lost. SDA is checked only when
-- SCL is high and during the states HEADER and XMIT_DATA (when data is
-- actively being clocked out of the controller). When arbitration is lost,
-- a Reset is generated for the Msms bit per the product spec.
-- Note that when arbitration is lost, the mode is switched to slave.
-- arb_lost stays set until scl state machine goes to IDLE state
----------------------------------------------------------------------------
ARBITRATION : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
arb_lost <= '0';
msms_rst_i <= '0';
elsif scl_state = SCL_IDLE or scl_state = STOP_WAIT then
arb_lost <= '0';
msms_rst_i <= '0';
elsif (master_slave = '1') then
-- Actively generating SCL clock as the master and (possibly)
-- participating in multi-master arbitration.
if (scl_rising_edge='1'
and (state = HEADER or state = XMIT_DATA)) then
if (sda_cout_reg='1' and sda_rin = '0') then
-- Other master drove SDA to 0 but the controller is trying
-- to drive a 1. That is the exact case for loss of
-- arbitration
arb_lost <= '1';
msms_rst_i <= '1';
else
arb_lost <= '0';
msms_rst_i <= '0';
end if;
else
msms_rst_i <= '0';
end if;
end if;
end if;
end process ARBITRATION;
Msms_rst <= msms_rst_i
-- The spec states that the Msms bit should be cleared when an
-- address is not-acknowledged. The sm_stop indicates that
-- a not-acknowledge occured on either a data or address
-- (header) transfer. This fixes CR439859.
or sm_stop;
----------------------------------------------------------------------------
-- SCL_GENERATOR_COMB Process
-- This process generates SCL and SDA when in Master mode. It generates the
-- START and STOP conditions. If arbitration is lost, SCL will not be
-- generated until the end of the byte transfer.
----------------------------------------------------------------------------
SCL_GENERATOR_COMB : process (
scl_state,
arb_lost,
sm_stop,
gen_stop,
rep_start,
bus_busy,
gen_start,
master_slave,
stop_scl_reg,
clk_cnt,
scl_rin,
sda_rin,
state,
sda_cout_reg,
master_sda,
Timing_param_tsusta,
Timing_param_tsusto,
Timing_param_thdsta,
Timing_param_thddat,
Timing_param_tbuf,
Timing_param_tlow,
Timing_param_thigh
)
begin
-- state machine defaults
scl_cout <= '1';
sda_cout <= sda_cout_reg;
stop_scl <= stop_scl_reg;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
next_scl_state <= scl_state;
Rsta_rst <= (ENABLE_N);
case scl_state is
when SCL_IDLE =>
sda_cout <= '1';
stop_scl <= '0';
-- leave IDLE state when master, bus is idle, and gen_start
if master_slave = '1' and bus_busy = '0' and gen_start = '1' then
next_scl_state <= START;
else
next_scl_state <= SCL_IDLE;
end if;
when START =>
-- generate start condition
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
sda_cout <= '0';
stop_scl <= '0';
if sda_rin='0' then
next_scl_state <= START_EDGE;
else
next_scl_state <= START;
end if;
when START_EDGE =>
-- This state ensures that the hold time for the (repeated) start
-- condition is met. The hold time is measured from the Vih level
-- of SDA so it is critical for SDA to be sampled low prior to
-- starting the hold time counter.
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
-- generate Reset for repeat start bit if repeat start condition
if rep_start = '1' then
Rsta_rst <= not(ENABLE_N);
end if;
if clk_cnt = Timing_param_thdsta then
next_scl_state <= SCL_LOW_EDGE;
else
next_scl_state <= START_EDGE;
end if;
when SCL_LOW_EDGE =>
clk_cnt_rst <= '1';
scl_cout <= '0';
stop_scl <= '0';
if (scl_rin='0') then
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
end if;
if ((scl_rin = '0') and (clk_cnt = Timing_param_thddat)) then
-- SCL sampled to be 0 so everything on the bus can see that it
-- is low too. The very large propagation delays caused by
-- potentially large (~300ns or more) fall time should not be
-- ignored by the controller.It must VERIFY that the bus is low.
next_scl_state <= SCL_LOW;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
else
next_scl_state <= SCL_LOW_EDGE;
end if;
when SCL_LOW =>
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
scl_cout <= '0';
stop_scl <= '0';
-- SDA (the data) can only be changed when SCL is low. Note that
-- STOPS and RESTARTS could appear after the SCL low period
-- has expired because the controller is throttled.
if (sm_stop = '1' or gen_stop = '1')
and state /= ACK_DATA
and state /= ACK_HEADER
and state /= WAIT_ACK then
stop_scl <= '1';
-- Pull SDA low in anticipation of raising it to generate the
-- STOP edge
sda_cout <= '0';
elsif rep_start = '1' then
-- Release SDA in anticipation of dropping it to generate the
-- START edge
sda_cout <= '1';
else
sda_cout <= master_sda;
end if;
-- Wait until minimum low clock period requirement is met then
-- proceed to release the SCL_COUT so that it is "possible" for the
-- scl clock to go high on the bus. Note that a SLAVE device can
-- continue to hold SCL low to throttle the bus OR the master
-- itself may hold SCL low because of an internal throttle
-- condition.
if clk_cnt = Timing_param_tlow then
next_scl_state <= SCL_HIGH_EDGE;
else
next_scl_state <= SCL_LOW;
end if;
when SCL_HIGH_EDGE =>
clk_cnt_rst <= '1';
stop_scl <= '0';
-- SCL low time met. Try to release SCL to make it go high.
scl_cout <= '1';
-- SDA (the data) can only be changed when SCL is low. In this
-- state the fsm wants to change SCL to high and is waiting to see
-- it go high. However, other processes may be inhibiting SCL from
-- going high because the controller is throttled. While throttled,
-- and scl is still low:
-- (1) a STOP may be requested by the firmware, **OR**
-- (2) a RESTART may be requested (with or without data available)
-- by the firmware, **OR**
-- (3) new data may get loaded into the TX_FIFO and the first bit
-- is available to be loaded onto the SDA pin
-- Removed this condition as sda_cout should not go low when
-- SCL goes high. SDA should be changed in SCL_LOW state.
if (sm_stop = '1' or gen_stop = '1')
and state /= ACK_DATA
and state /= ACK_HEADER
and state /= WAIT_ACK then
stop_scl <= '1';
-- -- Pull SDA low in anticipation of raising it to generate the
-- -- STOP edge
sda_cout <= '0';
elsif rep_start = '1' then
--if stop_scl_reg = '1' then
-- stop_scl <= '1';
-- sda_cout <= '0';
--elsif rep_start = '1' then
-- Release SDA in anticipation of dropping it to generate the
-- START edge
sda_cout <= '1';
else
sda_cout <= master_sda;
end if;
-- Nothing in the controller should
-- a) sample SDA_RIN until the controller actually verifies that
-- SCL has gone high, and
-- b) change SDA_COUT given that it is trying to change SCL now.
-- Note that other processes may inhibit SCL from going high to
-- wait for the transmit data register to be filled with data. In
-- that case data setup requirements imposed by the I2C spec must
-- be satisfied. Regardless, the SCL clock generator can wait here
-- in SCL_HIGH_EDGE until that is accomplished.
if (scl_rin='1') then
next_scl_state <= SCL_HIGH;
else
next_scl_state <= SCL_HIGH_EDGE;
end if;
when SCL_HIGH =>
-- SCL is now high (released) on the external bus. At this point
-- the state machine doesn't have to worry about any throttle
-- conditions -- by definition they are removed as SCL is no longer
-- low. The firmware **must** signal the desire to STOP or Repeat
-- Start when throttled.
-- It is decision time. Should another SCL clock pulse get
-- generated? (IE a low period + high period?) The answer depends
-- on whether the previous clock was a DATA XFER clock or an ACK
-- CLOCK. Should a Repeated Start be generated? Should a STOP be
-- generated?
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
scl_cout <= '1';
if (arb_lost='1') then
-- No point in continuing! The other master will generate the
-- clock.
next_scl_state <= SCL_IDLE;
else
-- Determine HIGH time based on need to generate a repeated
-- start, a stop or the full high period of the SCL clock.
-- (Without some analysis it isn't clear if rep_start and
-- stop_scl_reg are mutually exclusive. Hence the priority
-- encoder.)
if rep_start = '1' then
if (clk_cnt=Timing_param_tsusta) then
-- The hidden assumption here is that SDA has been released
-- by the slave|master receiver after the ACK clock so that
-- a repeated start is possible
next_scl_state <= START;
clk_cnt_en <= '0';
clk_cnt_rst <= '1';
end if;
elsif stop_scl_reg = '1' then
if (clk_cnt=Timing_param_tsusto) then
-- The hidden assumption here is that SDA has been pulled
-- low by the master after the ACK clock so that a
-- stop is possible
next_scl_state <= STOP_EDGE;
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
sda_cout <= '1'; -- issue the stop
stop_scl <= '0';
end if;
else
-- Neither repeated start nor stop requested
if clk_cnt= Timing_param_thigh then
next_scl_state <= SCL_LOW_EDGE;
clk_cnt_rst <= '1';
clk_cnt_en <= '0';
end if;
end if;
end if;
when STOP_EDGE =>
if (sda_rin='1') then
next_scl_state <= STOP_WAIT;
else
next_scl_state <= STOP_EDGE;
end if;
when STOP_WAIT =>
-- The Stop setup time was satisfied and SDA was sampled high
-- indicating the stop occured. Now wait the TBUF time required
-- between a stop and the next start.
clk_cnt_en <= '1';
clk_cnt_rst <= '0';
stop_scl <= '0';
if clk_cnt = Timing_param_tbuf then
next_scl_state <= SCL_IDLE;
else
next_scl_state <= STOP_WAIT;
end if;
-- coverage off
when others =>
next_scl_state <= SCL_IDLE;
-- coverage on
end case;
end process SCL_GENERATOR_COMB;
----------------------------------------------------------------------------
--PROCESS : SCL_GENERATOR_REGS
----------------------------------------------------------------------------
SCL_GENERATOR_REGS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
scl_state <= SCL_IDLE;
sda_cout_reg <= '1';
scl_cout_reg <= '1';
stop_scl_reg <= '0';
else
scl_state <= next_scl_state;
sda_cout_reg <= sda_cout;
-- Ro_prev = receive overflow prevent = case where controller must
-- hold SCL low itself until receive fifo is emptied by the firmware
scl_cout_reg <= scl_cout and not Ro_prev;
stop_scl_reg <= stop_scl;
end if;
end if;
end process SCL_GENERATOR_REGS;
----------------------------------------------------------------------------
-- Clock Counter Implementation
-- The following code implements the counter that divides the sys_clock for
-- creation of SCL. Control lines for this counter are set in SCL state
-- machine
----------------------------------------------------------------------------
CLKCNT : entity axi_iic_v2_0.upcnt_n
generic map (
C_SIZE => C_SIZE
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_zero,
Cnt_en => clk_cnt_en,
Load => clk_cnt_rst,
Qout => clk_cnt
);
----------------------------------------------------------------------------
-- Input Registers Process
-- This process samples the incoming SDA and SCL with the system clock
----------------------------------------------------------------------------
sda_rin <= Sda_I;
scl_rin <= Scl_I;
INPUT_REGS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
sda_rin_d1 <= sda_rin; -- delay sda_rin to find edges
scl_rin_d1 <= scl_rin; -- delay Scl_rin to find edges
sda_cout_reg_d1 <= sda_cout_reg;
end if;
end process INPUT_REGS;
----------------------------------------------------------------------------
-- Master Slave Mode Select Process
-- This process allows software to write the value of Msms with each data
-- word to be transmitted. So writing a '0' to Msms will initiate a stop
-- sequence on the I2C bus after the that byte in the DTR has been sent.
----------------------------------------------------------------------------
MSMS_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msms_d1 <= '0';
msms_d2 <= '0';
else
msms_d1 <= (Msms and not msms_rst_i)
or ((msms_d1 and not (dtc_i_d1 and not dtc_i_d2) and
not msms_rst_i)
and not Msms_set and not txer_i) ;
msms_d2 <= msms_d1;
end if;
end if;
end process MSMS_PROCESS;
----------------------------------------------------------------------------
-- START/STOP Detect Process
-- This process detects the start condition by finding the falling edge of
-- sda_rin and checking that SCL is high. It detects the stop condition on
-- the bus by finding a rising edge of SDA when SCL is high.
----------------------------------------------------------------------------
sda_falling <= sda_rin_d1 and not sda_rin;
sda_rising <= not sda_rin_d1 and sda_rin;
sda_changing <= sda_falling or sda_rising or tx_under_prev_fe
or rsta_re or gen_stop_re;
----------------------------------------------------------------------------
-- START Detect Process
----------------------------------------------------------------------------
START_DET_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or state = HEADER then
detect_start <= '0';
elsif sda_falling = '1' then
if scl_rin = '1' then
detect_start <= '1';
else
detect_start <= '0';
end if;
end if;
end if;
end process START_DET_PROCESS;
----------------------------------------------------------------------------
-- STOP Detect Process
----------------------------------------------------------------------------
STOP_DET_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_start = '1' then
detect_stop <= '0';
elsif sda_rising = '1' then
if scl_rin = '1' then
detect_stop <= '1';
else
detect_stop <= '0';
end if;
elsif msms_d2 = '0' and msms_d1 = '1' then
-- rising edge of Msms - generate start condition
detect_stop <= '0'; -- clear on a generate start condition
end if;
end if;
end process STOP_DET_PROCESS;
----------------------------------------------------------------------------
-- Bus Busy Process
-- This process sets bus_busy as soon as START is detected which would
-- always set arb lost (Al).
----------------------------------------------------------------------------
SET_BUS_BUSY_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bus_busy <= '0';
else
if detect_stop = '1' then
bus_busy <= '0';
elsif detect_start = '1' then
bus_busy <= '1';
end if;
end if;
end if;
end process SET_BUS_BUSY_PROCESS;
----------------------------------------------------------------------------
-- BUS_BUSY_REG_PROCESS:
-- This process describes a delayed version of the bus busy bit which is
-- used to determine arb lost (Al).
----------------------------------------------------------------------------
BUS_BUSY_REG_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bus_busy_d1 <= '0';
else
bus_busy_d1 <= bus_busy;
end if;
end if;
end process BUS_BUSY_REG_PROCESS;
----------------------------------------------------------------------------
-- GEN_START_PROCESS
-- This process detects the rising and falling edges of Msms and sets
-- signals to control generation of start condition
----------------------------------------------------------------------------
GEN_START_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_start <= '0';
else
if msms_d2 = '0' and msms_d1 = '1' then
-- rising edge of Msms - generate start condition
gen_start <= '1';
elsif detect_start = '1' then
gen_start <= '0';
end if;
end if;
end if;
end process GEN_START_PROCESS;
----------------------------------------------------------------------------
-- GEN_STOP_PROCESS
-- This process detects the rising and falling edges of Msms and sets
-- signals to control generation of stop condition
----------------------------------------------------------------------------
GEN_STOP_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_stop <= '0';
else
if arb_lost = '0' and msms_d2 = '1' and msms_d1 = '0' then
-- falling edge of Msms - generate stop condition only
-- if arbitration has not been lost
gen_stop <= '1';
elsif detect_stop = '1' then
gen_stop <= '0';
end if;
end if;
end if;
end process GEN_STOP_PROCESS;
----------------------------------------------------------------------------
-- GEN_MASTRE_SLAVE_PROCESS
-- This process sets the master slave bit based on Msms if and only if
-- it is not in the middle of a cycle, i.e. bus_busy = '0'
----------------------------------------------------------------------------
GEN_MASTRE_SLAVE_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_slave <= '0';
else
if bus_busy = '0' then
master_slave <= msms_d1;
elsif arb_lost = '1' then
master_slave <= '0';
else
master_slave <= master_slave;
end if;
end if;
end if;
end process GEN_MASTRE_SLAVE_PROCESS;
rep_start <= Rsta; -- repeat start signal is Rsta control bit
----------------------------------------------------------------------------
-- GEN_STOP_AND_SCL_HIGH
----------------------------------------------------------------------------
-- This process does not go high until both gen_stop and SCL have gone high
-- This is used to prevent the SCL state machine from getting stuck when a
-- slave no acks during the last data byte being transmitted
----------------------------------------------------------------------------
GEN_STOP_AND_SCL_HIGH : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
gen_stop_and_scl_hi <= '0';
elsif gen_stop = '0' then
gen_stop_and_scl_hi <= '0'; --clear
elsif gen_stop = '1' and scl_rin = '1' then
gen_stop_and_scl_hi <= '1';
else
gen_stop_and_scl_hi <= gen_stop_and_scl_hi; --hold condition
end if;
end if;
end process GEN_STOP_AND_SCL_HIGH;
----------------------------------------------------------------------------
-- SCL_EDGE_PROCESS
----------------------------------------------------------------------------
-- This process generates a 1 Sys_clk wide pulse for both the rising edge
-- and the falling edge of SCL_RIN
----------------------------------------------------------------------------
SCL_EDGE_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
scl_falling_edge <= '0';
scl_rising_edge <= '0';
scl_f_edg_d1 <= '0';
scl_f_edg_d2 <= '0';
scl_f_edg_d3 <= '0';
else
scl_falling_edge <= scl_rin_d1 and (not scl_rin); -- 1 to 0
scl_rising_edge <= (not scl_rin_d1) and scl_rin; -- 0 to 1
scl_f_edg_d1 <= scl_falling_edge;
scl_f_edg_d2 <= scl_f_edg_d1;
scl_f_edg_d3 <= scl_f_edg_d2;
end if;
end if;
end process SCL_EDGE_PROCESS;
----------------------------------------------------------------------------
-- EARLY_ACK_HDR_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- the ACK_HEADER state
----------------------------------------------------------------------------
EARLY_ACK_HDR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
EarlyAckHdr <= '0';
elsif (scl_f_edg_d3 = '1' and state = ACK_HEADER) then
EarlyAckHdr <= '1';
else
EarlyAckHdr <= '0';
end if;
end if;
end process EARLY_ACK_HDR_PROCESS;
----------------------------------------------------------------------------
-- ACK_DATA_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- ACK_DATA state
----------------------------------------------------------------------------
ACK_DATA_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
AckDataState <= '0';
elsif (state = ACK_DATA) then
AckDataState <= '1';
else
AckDataState <= '0';
end if;
end if;
end process ACK_DATA_PROCESS;
----------------------------------------------------------------------------
-- EARLY_ACK_DATA_PROCESS
----------------------------------------------------------------------------
-- This process generates 1 Sys_clk wide pulses when the statemachine enters
-- the ACK_DATA ot RCV_DATA state state
----------------------------------------------------------------------------
EARLY_ACK_DATA_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
EarlyAckDataState <= '0';
elsif (state = ACK_DATA or (state = RCV_DATA and
(bit_cnt = CNT_ALMOST_DONE or bit_cnt = CNT_DONE))) then
EarlyAckDataState <= '1';
else
EarlyAckDataState <= '0';
end if;
end if;
end process EARLY_ACK_DATA_PROCESS;
----------------------------------------------------------------------------
-- uP Status Register Bits Processes
-- Dtc - data transfer complete. Since this only checks whether the
-- bit_cnt="0111" it will be true for both data and address transfers.
-- While one byte of data is being transferred, this bit is cleared.
-- It is set by the falling edge of the 9th clock of a byte transfer and
-- is not cleared at Reset
----------------------------------------------------------------------------
DTC_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
dtc_i <= '0';
elsif scl_falling_edge = '1' then
if bit_cnt = "0111" then
dtc_i <= '1';
else
dtc_i <= '0';
end if;
end if;
end if;
end process DTC_I_BIT;
Dtc <= dtc_i;
----------------------------------------------------------------------------
-- DTC_DELAY_PROCESS
----------------------------------------------------------------------------
DTC_DELAY_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
dtc_i_d1 <= '0';
dtc_i_d2 <= '0';
else
dtc_i_d1 <= dtc_i;
dtc_i_d2 <= dtc_i_d1;
end if;
end if;
end process DTC_DELAY_PROCESS;
----------------------------------------------------------------------------
-- aas_i - Addressed As Slave Bit
----------------------------------------------------------------------------
-- When its own specific address (adr) matches the I2C Address, this bit is
-- set.
-- Then the CPU needs to check the Srw bit and this bit when a
-- TX-RX mode accordingly.
----------------------------------------------------------------------------
AAS_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
aas_i <= '0';
elsif detect_stop = '1' or addr_match = '0' then
aas_i <= '0';
elsif state = ACK_HEADER then
aas_i <= addr_match;
-- the signal address match compares adr with I2_ADDR
else
aas_i <= aas_i;
end if;
end if;
end process AAS_I_BIT;
----------------------------------------------------------------------------
-- INT_AAS_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal aas_i signal to the output port Aas
----------------------------------------------------------------------------
INT_AAS_PROCESS : process (aas_i, sec_adr_match)
begin -- process
Aas <= aas_i and sec_adr_match;
end process INT_AAS_PROCESS;
----------------------------------------------------------------------------
-- Bb - Bus Busy Bit
----------------------------------------------------------------------------
-- This bit indicates the status of the bus. This bit is set when a START
-- signal is detected and cleared when a stop signal is detected. It is
-- also cleared on Reset. This bit is identical to the signal bus_busy set
-- in the process set_bus_busy.
----------------------------------------------------------------------------
Bb <= bus_busy;
----------------------------------------------------------------------------
-- Al - Arbitration Lost Bit
----------------------------------------------------------------------------
-- This bit is set when the arbitration procedure is lost.
-- Arbitration is lost when:
-- 1. SDA is sampled low when the master drives high during addr or data
-- transmit cycle
-- 2. SDA is sampled low when the master drives high during the
-- acknowledge bit of a data receive cycle
-- 3. A start cycle is attempted when the bus is busy
-- 4. A repeated start is requested in slave mode
-- 5. A stop condition is detected that the master did not request it.
-- This bit is cleared upon Reset and when the software writes a '0' to it
-- Conditions 1 & 2 above simply result in sda_rin not matching sda_cout
-- while SCL is high. This design will not generate a START condition while
-- the bus is busy. When a START is detected, this hardware will set the bus
-- busy bit and gen_start stays set until detect_start asserts, therefore
-- will have to compare with a delayed version of bus_busy. Condition 3 is
-- really just a check on the uP software control registers as is condition
-- 4. Condition 5 is also taken care of by the fact that sda_rin does not
-- equal sda_cout, however, this process also tests for if a stop condition
-- has been detected when this master did not generate it
----------------------------------------------------------------------------
AL_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
al_i <= '0';
elsif master_slave = '1' then
if (arb_lost = '1') or
(bus_busy_d1 = '1' and gen_start = '1') or
(detect_stop = '1' and al_prevent = '0' and sm_stop = '0') then
al_i <= '1';
else
al_i <= '0'; -- generate a pulse on al_i, arb lost interrupt
end if;
elsif Rsta = '1' then
-- repeated start requested while slave
al_i <= '1';
else
al_i <= '0';
end if;
end if;
end process AL_I_BIT;
----------------------------------------------------------------------------
-- INT_ARB_LOST_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal al_i signal to the output port Al
----------------------------------------------------------------------------
INT_ARB_LOST_PROCESS : process (al_i)
begin -- process
Al <= al_i;
end process INT_ARB_LOST_PROCESS;
----------------------------------------------------------------------------
-- PREVENT_ARB_LOST_PROCESS
----------------------------------------------------------------------------
-- This process prevents arb lost (al_i) when a stop has been initiated by
-- this device operating as a master.
----------------------------------------------------------------------------
PREVENT_ARB_LOST_PROCESS : process (Sys_clk)
begin -- make an SR flip flop that sets on gen_stop and resets on
-- detect_start
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
al_prevent <= '0';
elsif (gen_stop = '1' and detect_start = '0')
or (sm_stop = '1' and detect_start = '0')then
al_prevent <= '1';
elsif detect_start = '1' then
al_prevent <= '0';
else
al_prevent <= al_prevent;
end if;
end if;
end process PREVENT_ARB_LOST_PROCESS;
----------------------------------------------------------------------------
-- srw_i - Slave Read/Write Bit
----------------------------------------------------------------------------
-- When aas_i is set, srw_i indicates the value of the R/W command bit of
-- the calling address sent from the master. This bit is only valid when a
-- complete transfer has occurred and no other transfers have been
-- initiated. The CPU uses this bit to set the slave transmit/receive mode.
-- This bit is Reset by Reset
----------------------------------------------------------------------------
SRW_I_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
srw_i <= '0';
elsif state = ACK_HEADER then
srw_i <= i2c_header(0);
else
srw_i <= srw_i;
end if;
end if;
end process SRW_I_BIT;
Srw <= srw_i;
----------------------------------------------------------------------------
-- TXER_BIT process
----------------------------------------------------------------------------
-- This process determines the state of the acknowledge bit which may be
-- used as a transmit error or by a master receiver to indicate to the
-- slave that the last byte has been transmitted
----------------------------------------------------------------------------
TXER_BIT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
txer_i <= '0';
elsif scl_falling_edge = '1' then
if state = ACK_HEADER or state = ACK_DATA or state = WAIT_ACK then
txer_i <= sda_sample;
end if;
end if;
end if;
end process TXER_BIT;
----------------------------------------------------------------------------
-- TXER_EDGE process
----------------------------------------------------------------------------
-- This process creates a one wide clock pulse for Txer IRQ
----------------------------------------------------------------------------
TXER_EDGE_PROCESS : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
txer_edge <= '0';
elsif scl_falling_edge = '1' then
if state = ACK_HEADER or state = ACK_DATA or state = WAIT_ACK then
txer_edge <= sda_sample;
end if;
elsif scl_f_edg_d2 = '1' then
txer_edge <= '0';
end if;
end if;
end process TXER_EDGE_PROCESS;
Txer <= txer_edge;
----------------------------------------------------------------------------
-- uP Data Register
-- Register for uP interface data_i2c_i
----------------------------------------------------------------------------
DATA_I2C_I_PROC : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
data_i2c_i <= (others => '0');
new_rcv_dta_i <= '0';
elsif (state = ACK_DATA) and Ro_prev = '0' and scl_falling_edge = '1'
and adr_dta_l = '0' then
data_i2c_i <= shift_reg;
new_rcv_dta_i <= '1';
else
data_i2c_i <= data_i2c_i;
new_rcv_dta_i <= '0';
end if;
end if;
end process DATA_I2C_I_PROC;
----------------------------------------------------------------------------
-- INT_NEW_RCV_DATA_PROCESS
----------------------------------------------------------------------------
-- This process assigns the internal receive data signals to the output port
----------------------------------------------------------------------------
INT_NEW_RCV_DATA_PROCESS : process (new_rcv_dta_i)
begin -- process
New_rcv_dta <= new_rcv_dta_i;
end process INT_NEW_RCV_DATA_PROCESS;
Data_i2c <= data_i2c_i;
----------------------------------------------------------------------------
-- Determine if Addressed As Slave or by General Call
----------------------------------------------------------------------------
-- This process determines when the I2C has been addressed as a slave
-- that is the I2C header matches the slave address stored in ADR or a
-- general call has happened
----------------------------------------------------------------------------
NO_TEN_BIT_GEN : if C_TEN_BIT_ADR = 0 generate
addr_match <= '1' when (i2c_header(7 downto 1) = Adr(7 downto 1))
or (abgc_i = '1')
else '0';
-- Seven bit addressing, sec_adr_match is always true.
sec_adr_match <= '1';
end generate NO_TEN_BIT_GEN;
TEN_BIT_GEN : if (C_TEN_BIT_ADR = 1) generate
-------------------------------------------------------------------------
-- The msb_wr signal indicates that the just received i2c_header matches
-- the required first byte of a 2-byte, 10-bit address. Since the
-- i2c_header shift register clocks on the scl rising edge but the timing
-- of signals dependent on msb_wr expect it to change on the falling edge
-- the scl_f_edge_d1 qualifier is used to create the expected timing.
-------------------------------------------------------------------------
MSB_WR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msb_wr <= '0';
elsif (abgc_i = '1') or
(scl_f_edg_d1 = '1'
and i2c_header(7 downto 3) = "11110"
and (i2c_header(2 downto 1) = Ten_adr(7 downto 6)))
then
msb_wr <= '1';
elsif (scl_f_edg_d1='1') then
msb_wr <= '0';
end if;
end if;
end process MSB_WR_PROCESS;
-------------------------------------------------------------------------
-- MSB_WR_D_PROCESS
-------------------------------------------------------------------------
-- msb_wr delay process
-------------------------------------------------------------------------
MSB_WR_D_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
msb_wr_d <= '0';
msb_wr_d1 <= '0';
else
msb_wr_d <= msb_wr;
msb_wr_d1 <= msb_wr_d; -- delayed to align with srw_i
end if;
end if;
end process MSB_WR_D_PROCESS;
-------------------------------------------------------------------------
-- SRFF set on leading edge of MSB_WR, Reset on DTC and SCL falling edge
-- this will qualify the 2nd byte as address and prevent it from being
-- loaded into the DRR or Rc FIFO
-------------------------------------------------------------------------
SECOND_ADDR_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
sec_addr <= '0';
elsif (msb_wr = '1' and msb_wr_d = '0'
and i2c_header(0) = '0') then
-- First byte of two byte (10-bit addr) matched and
-- direction=write. Set sec_addr flag to indicate next byte
-- should be checked against remainder of the address.
sec_addr <= '1';
elsif dtc_i = '1' and Ro_prev = '0' and scl_f_edg_d1 = '1'
then
sec_addr <= '0';
else
sec_addr <= sec_addr;
end if;
end if;
end process SECOND_ADDR_PROCESS;
-------------------------------------------------------------------------
-- Compare 2nd byte to see if it matches slave address
-- A repeated start with the Master writing to the slave must also
-- compare the second address byte.
-- A repeated start with the Master reading from the slave only compares
-- the first (most significant).
-------------------------------------------------------------------------
SECOND_ADDR_COMP_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
sec_adr_match <= '0';
elsif detect_stop = '1'
-- Repeated Start and Master Writing to Slave
or (state = ACK_HEADER and i2c_header(0) = '0'
and master_slave = '0' and msb_wr_d = '1' and abgc_i = '0') then
sec_adr_match <= '0';
elsif (abgc_i = '1')
or (sec_addr = '1' and (shift_reg(7) = Ten_adr(5)
and shift_reg(6 downto 0) = Adr (7 downto 1)
and dtc_i = '1' and msb_wr_d1 = '1')) then
sec_adr_match <= '1';
else
sec_adr_match <= sec_adr_match;
end if;
end if;
end process SECOND_ADDR_COMP_PROCESS;
-------------------------------------------------------------------------
-- Prevents 2nd byte of 10 bit address from being loaded into DRR.
-- When in ACK_HEADER and srw_i is lo then a repeated start or start
-- condition occured and data is being written to slave so the next
-- byte will be the remaining portion of the 10 bit address
-------------------------------------------------------------------------
ADR_DTA_L_PROCESS : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
adr_dta_l <= '0';
elsif ((i2c_header(0) = '0' and
msb_wr = '1' and
msb_wr_d = '0') and
sec_adr_match = '0') or
(state = ACK_HEADER and srw_i = '0' and
master_slave = '0' and
msb_wr_d1 = '1') then
adr_dta_l <= '1';
elsif (state = ACK_HEADER and
master_slave = '1' and
msb_wr_d1 = '0') then
adr_dta_l <= '0';
elsif (state = ACK_DATA and Ro_prev = '0'
and scl_falling_edge = '1')
or (detect_start = '1') or (abgc_i = '1')
-- or (state = ACK_HEADER and srw_i = '1' and master_slave = '0')
then
adr_dta_l <= '0';
else
adr_dta_l <= adr_dta_l;
end if;
end if;
end process ADR_DTA_L_PROCESS;
-- Set address match high to get 2nd byte of slave address
addr_match <= '1' when (msb_wr = '1' and sec_adr_match = '1')
or (sec_addr = '1')
else '0';
end generate TEN_BIT_GEN;
----------------------------------------------------------------------------
-- Process : SDA_SMPL
-- Address by general call process
----------------------------------------------------------------------------
ABGC_PROCESS : process (Sys_clk)
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
abgc_i <= '0';
elsif detect_stop = '1' or detect_start = '1' then
abgc_i <= '0';
elsif i2c_header(7 downto 0) = "00000000" and Gc_en = '1'
and (state = ACK_HEADER) then
abgc_i <= '1';
end if;
end if;
end process ABGC_PROCESS;
Abgc <= abgc_i;
----------------------------------------------------------------------------
-- Process : SDA_SMPL
-- Sample the SDA_RIN for use in checking the acknowledge bit received by
-- the controller
----------------------------------------------------------------------------
SDA_SMPL: process (Sys_clk) is
begin
if (Sys_clk'event and Sys_clk = '1') then
if Reset = ENABLE_N then
sda_sample <= '0';
elsif (scl_rising_edge='1') then
sda_sample <= sda_rin;
end if;
end if;
end process SDA_SMPL;
----------------------------------------------------------------------------
-- Main State Machine Process
-- The following process contains the main I2C state machine for both master
-- and slave modes. This state machine is clocked on the falling edge of SCL
-- DETECT_STOP must stay as an asynchronous Reset because once STOP has been
-- generated, SCL clock stops. Note that the bit_cnt signal updates on the
-- scl_falling_edge pulse and is available on scl_f_edg_d1. So the count is
-- available prior to the STATE changing.
----------------------------------------------------------------------------
STATE_MACHINE : process (Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N or detect_stop = '1' then
state <= IDLE;
sm_stop <= '0';
elsif scl_f_edg_d2 = '1' or (Ro_prev = '0' and ro_prev_d1 = '1') then
case state is
------------- IDLE STATE -------------
when IDLE =>
--sm_stop <= sm_stop ;
if detect_start = '1' then
state <= HEADER;
end if;
------------- HEADER STATE -------------
when HEADER =>
--sm_stop <= sm_stop ;
if bit_cnt = CNT_DONE then
state <= ACK_HEADER;
end if;
------------- ACK_HEADER STATE -------------
when ACK_HEADER =>
-- sm_stop <= sm_stop ;
if arb_lost = '1' then
state <= IDLE;
elsif sda_sample = '0' then
-- ack has been received, check for master/slave
if master_slave = '1' then
-- master, so check tx bit for direction
if Tx = '0' then
-- receive mode
state <= RCV_DATA;
else
--transmit mode
state <= XMIT_DATA;
end if;
else
if addr_match = '1' then
--if aas_i = '1' then
-- addressed slave, so check I2C_HEADER(0)
-- for direction
if i2c_header(0) = '0' then
-- receive mode
state <= RCV_DATA;
else
-- transmit mode
state <= XMIT_DATA;
end if;
else
-- not addressed, go back to IDLE
state <= IDLE;
end if;
end if;
else
-- not acknowledge received, stop as the address put on
-- the bus was not recognized/accepted by any slave
state <= IDLE;
if master_slave = '1' then
sm_stop <= '1';
end if;
end if;
------------- RCV_DATA State --------------
when RCV_DATA =>
--sm_stop <= sm_stop ;
-- check for repeated start
if (detect_start = '1') then
state <= HEADER;
elsif bit_cnt = CNT_DONE then
if master_slave = '0' and addr_match = '0' then
state <= IDLE;
else
-- Send an acknowledge
state <= ACK_DATA;
end if;
end if;
------------ XMIT_DATA State --------------
when XMIT_DATA =>
--sm_stop <= sm_stop ;
-- check for repeated start
if (detect_start = '1') then
state <= HEADER;
elsif bit_cnt = CNT_DONE then
-- Wait for acknowledge
state <= WAIT_ACK;
end if;
------------- ACK_DATA State --------------
when ACK_DATA =>
--sm_stop <= sm_stop ;
if Ro_prev = '0' then -- stay in ACK_DATA until
state <= RCV_DATA; -- a read of DRR has occurred
else
state <= ACK_DATA;
end if;
------------- WAIT_ACK State --------------
when WAIT_ACK =>
if arb_lost = '1' then
state <= IDLE;
elsif (sda_sample = '0') then
if (master_slave = '0' and addr_match = '0') then
state <= IDLE;
else
state <= XMIT_DATA;
end if;
else
-- not acknowledge received. The master transmitter is
-- being told to quit sending data as the slave won't take
-- anymore. Generate a STOP per spec. (Note that it
-- isn't strickly necessary for the master to get off the
-- bus at this point. It could retain ownership. However,
-- product specification indicates that it will get off
-- the bus) The slave transmitter is being informed by the
-- master that it won't take any more data.
if master_slave = '1' then
sm_stop <= '1';
end if;
state <= IDLE;
end if;
-- coverage off
when others =>
state <= IDLE;
-- coverage on
end case;
end if;
end if;
end process STATE_MACHINE;
LEVEL_1_GEN: if C_SDA_LEVEL = 1 generate
begin
----------------------------------------------------------------------------
-- Master SDA
----------------------------------------------------------------------------
MAS_SDA : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_sda <= '1';
-- elsif state = HEADER or state = XMIT_DATA then
-- master_sda <= shift_out;
elsif state = HEADER or (state = XMIT_DATA and
tx_under_prev_i = '0' ) then
master_sda <= shift_out;
---------------------------------
-- Updated for CR 555648
---------------------------------
elsif (tx_under_prev_i = '1' and state = XMIT_DATA) then
master_sda <= '1';
elsif state = ACK_DATA then
master_sda <= Txak;
else
master_sda <= '1';
end if;
end if;
end process MAS_SDA;
end generate LEVEL_1_GEN;
LEVEL_0_GEN: if C_SDA_LEVEL = 0 generate
begin
----------------------------------------------------------------------------
-- Master SDA
----------------------------------------------------------------------------
MAS_SDA : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
master_sda <= '1';
-- elsif state = HEADER or state = XMIT_DATA then
-- master_sda <= shift_out;
elsif state = HEADER or (state = XMIT_DATA and
tx_under_prev_i = '0' ) then
master_sda <= shift_out;
---------------------------------
-- Updated for CR 555648
---------------------------------
elsif (tx_under_prev_i = '1' and state = XMIT_DATA) then
master_sda <= '0';
elsif state = ACK_DATA then
master_sda <= Txak;
else
master_sda <= '1';
end if;
end if;
end process MAS_SDA;
end generate LEVEL_0_GEN;
----------------------------------------------------------------------------
-- Slave SDA
----------------------------------------------------------------------------
SLV_SDA : process(Sys_clk)
begin
-- For the slave SDA, address match(aas_i) only has to be checked when
-- state is ACK_HEADER because state
-- machine will never get to state XMIT_DATA or ACK_DATA
-- unless address match is a one.
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
slave_sda <= '1';
elsif (addr_match = '1' and state = ACK_HEADER) or
(state = ACK_DATA) then
slave_sda <= Txak;
elsif (state = XMIT_DATA) then
slave_sda <= shift_out;
else
slave_sda <= '1';
end if;
end if;
end process SLV_SDA;
------------------------------------------------------------
--Mathew : Added below process for CR 707697
SHIFT_COUNT : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_cnt <= "000000000";
elsif(shift_reg_ld = '1') then
shift_cnt <= "000000001";
elsif(shift_reg_en = '1') then
shift_cnt <= shift_cnt(7 downto 0) & shift_cnt(8);
else
shift_cnt <= shift_cnt;
end if;
end if;
end process SHIFT_COUNT ;
reg_empty <= '1' when shift_cnt(8) = '1' else '0';
------------------------------------------------------------
----------------------------------------------------------------------------
-- I2C Data Shift Register
----------------------------------------------------------------------------
I2CDATA_REG : entity axi_iic_v2_0.shift8
port map (
Clk => Sys_clk,
Clr => Reset,
Data_ld => shift_reg_ld,
Data_in => Dtr,
Shift_in => sda_rin,
Shift_en => shift_reg_en,
Shift_out => shift_out,
Data_out => shift_reg);
----------------------------------------------------------------------------
-- Process : I2CDATA_REG_EN_CTRL
----------------------------------------------------------------------------
I2CDATA_REG_EN_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_en <= '0';
elsif (
-- Grab second byte of 10-bit address?
(master_slave = '1' and state = HEADER and scl_rising_edge='1')
-- Grab data byte
or (state = RCV_DATA and scl_rising_edge='1'
and detect_start = '0')
-- Send data byte. Note use of scl_f_edg_d2 which is the 2 clock
-- delayed version of the SCL falling edge signal
or (state = XMIT_DATA and scl_f_edg_d2 = '1'
and detect_start = '0')) then
shift_reg_en <= '1';
else
shift_reg_en <= '0';
end if;
end if;
end process I2CDATA_REG_EN_CTRL;
----------------------------------------------------------------------------
-- Process : I2CDATA_REG_LD_CTRL
----------------------------------------------------------------------------
I2CDATA_REG_LD_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_ld <= '0';
elsif (
(master_slave = '1' and state = IDLE)
or (state = WAIT_ACK)
-- Slave Transmitter (i2c_header(0)='1' mean master wants to read)
or (state = ACK_HEADER and i2c_header(0) = '1'
and master_slave = '0')
-- Master has a byte to transmit
or (state = ACK_HEADER and Tx = '1' and master_slave = '1')
-- ??
or (state = RCV_DATA and detect_start = '1'))
or tx_under_prev_i = '1' then
shift_reg_ld <= '1';
else
shift_reg_ld <= '0';
end if;
end if;
end process I2CDATA_REG_LD_CTRL;
----------------------------------------------------------------------------
-- SHFT_REG_LD_PROCESS
----------------------------------------------------------------------------
-- This process registers shift_reg_ld signal
----------------------------------------------------------------------------
SHFT_REG_LD_PROCESS : process (Sys_clk)
begin -- process
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
shift_reg_ld_d1 <= '0';
else -- Delay shift_reg_ld one clock
shift_reg_ld_d1 <= shift_reg_ld;
end if;
end if;
end process SHFT_REG_LD_PROCESS;
----------------------------------------------------------------------------
-- NEW_XMT_PROCESS
----------------------------------------------------------------------------
-- This process sets Rdy_new_xmt signal high for one sysclk after data has
-- been loaded into the shift register. This is used to create the Dtre
-- interrupt.
----------------------------------------------------------------------------
NEW_XMT_PROCESS : process (Sys_clk)
begin -- process
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
rdy_new_xmt_i <= '0';
elsif state = XMIT_DATA or (state = HEADER and Msms = '1') then
rdy_new_xmt_i <= (not (shift_reg_ld)) and shift_reg_ld_d1;
end if;
end if;
end process NEW_XMT_PROCESS;
Rdy_new_xmt <= rdy_new_xmt_i;
----------------------------------------------------------------------------
-- I2C Header Shift Register
-- Header/Address Shift Register
----------------------------------------------------------------------------
I2CHEADER_REG : entity axi_iic_v2_0.shift8
port map (
Clk => Sys_clk,
Clr => Reset,
Data_ld => i2c_header_ld,
Data_in => reg_clr,
Shift_in => sda_rin,
Shift_en => i2c_header_en,
Shift_out => i2c_shiftout,
Data_out => i2c_header);
----------------------------------------------------------------------------
-- Process : I2CHEADER_REG_CTRL
----------------------------------------------------------------------------
I2CHEADER_REG_CTRL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
i2c_header_en <= '0';
elsif (state = HEADER and scl_rising_edge='1') then
i2c_header_en <= '1';
else
i2c_header_en <= '0';
end if;
end if;
end process I2CHEADER_REG_CTRL;
i2c_header_ld <= '0';
----------------------------------------------------------------------------
-- Bit Counter
----------------------------------------------------------------------------
BITCNT : entity axi_iic_v2_0.upcnt_n
generic map (
C_SIZE => 4
)
port map(
Clk => Sys_clk,
Clr => Reset,
Data => cnt_start,
Cnt_en => bit_cnt_en,
Load => bit_cnt_ld,
Qout => bit_cnt);
----------------------------------------------------------------------------
-- Process : Counter control lines
----------------------------------------------------------------------------
BIT_CNT_EN_CNTL : process(Sys_clk)
begin
if Sys_clk'event and Sys_clk = '1' then
if Reset = ENABLE_N then
bit_cnt_en <= '0';
elsif (state = HEADER and scl_falling_edge = '1')
or (state = RCV_DATA and scl_falling_edge = '1')
or (state = XMIT_DATA and scl_falling_edge = '1') then
bit_cnt_en <= '1';
else
bit_cnt_en <= '0';
end if;
end if;
end process BIT_CNT_EN_CNTL;
bit_cnt_ld <= '1' when (state = IDLE) or (state = ACK_HEADER)
or (state = ACK_DATA)
or (state = WAIT_ACK)
or (detect_start = '1') else '0';
end architecture RTL;
| gpl-3.0 | 93408ba33780082956e448db10f4dc8c | 0.434476 | 4.66227 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rom_8192x32/simulation/bmg_stim_gen.vhd | 1 | 12,588 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port ROM
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SROM
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SROM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SROM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SROM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST /= '0' ) THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
GENERIC ( C_ROM_SYNTH : INTEGER := 0
);
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DATA_IN : IN STD_LOGIC_VECTOR (31 DOWNTO 0); --OUTPUT VECTOR
STATUS : OUT STD_LOGIC:= '0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
FUNCTION hex_to_std_logic_vector(
hex_str : STRING;
return_width : INTEGER)
RETURN STD_LOGIC_VECTOR IS
VARIABLE tmp : STD_LOGIC_VECTOR((hex_str'LENGTH*4)+return_width-1
DOWNTO 0);
BEGIN
tmp := (OTHERS => '0');
FOR i IN 1 TO hex_str'LENGTH LOOP
CASE hex_str((hex_str'LENGTH+1)-i) IS
WHEN '0' => tmp(i*4-1 DOWNTO (i-1)*4) := "0000";
WHEN '1' => tmp(i*4-1 DOWNTO (i-1)*4) := "0001";
WHEN '2' => tmp(i*4-1 DOWNTO (i-1)*4) := "0010";
WHEN '3' => tmp(i*4-1 DOWNTO (i-1)*4) := "0011";
WHEN '4' => tmp(i*4-1 DOWNTO (i-1)*4) := "0100";
WHEN '5' => tmp(i*4-1 DOWNTO (i-1)*4) := "0101";
WHEN '6' => tmp(i*4-1 DOWNTO (i-1)*4) := "0110";
WHEN '7' => tmp(i*4-1 DOWNTO (i-1)*4) := "0111";
WHEN '8' => tmp(i*4-1 DOWNTO (i-1)*4) := "1000";
WHEN '9' => tmp(i*4-1 DOWNTO (i-1)*4) := "1001";
WHEN 'a' | 'A' => tmp(i*4-1 DOWNTO (i-1)*4) := "1010";
WHEN 'b' | 'B' => tmp(i*4-1 DOWNTO (i-1)*4) := "1011";
WHEN 'c' | 'C' => tmp(i*4-1 DOWNTO (i-1)*4) := "1100";
WHEN 'd' | 'D' => tmp(i*4-1 DOWNTO (i-1)*4) := "1101";
WHEN 'e' | 'E' => tmp(i*4-1 DOWNTO (i-1)*4) := "1110";
WHEN 'f' | 'F' => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
WHEN OTHERS => tmp(i*4-1 DOWNTO (i-1)*4) := "1111";
END CASE;
END LOOP;
RETURN tmp(return_width-1 DOWNTO 0);
END hex_to_std_logic_vector;
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECK_READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL CHECK_DATA : STD_LOGIC := '0';
SIGNAL CHECK_DATA_R : STD_LOGIC := '0';
SIGNAL CHECK_DATA_2R : STD_LOGIC := '0';
SIGNAL DO_READ_REG: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
CONSTANT DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0):= hex_to_std_logic_vector("0",32);
BEGIN
SYNTH_COE: IF(C_ROM_SYNTH =0 ) GENERATE
type mem_type is array (8191 downto 0) of std_logic_vector(31 downto 0);
FUNCTION bit_to_sl(input: BIT) RETURN STD_LOGIC IS
VARIABLE temp_return : STD_LOGIC;
BEGIN
IF (input = '0') THEN
temp_return := '0';
ELSE
temp_return := '1';
END IF;
RETURN temp_return;
END bit_to_sl;
function char_to_std_logic (
char : in character)
return std_logic is
variable data : std_logic;
begin
if char = '0' then
data := '0';
elsif char = '1' then
data := '1';
elsif char = 'X' then
data := 'X';
else
assert false
report "character which is not '0', '1' or 'X'."
severity warning;
data := 'U';
end if;
return data;
end char_to_std_logic;
impure FUNCTION init_memory( C_USE_DEFAULT_DATA : INTEGER;
C_LOAD_INIT_FILE : INTEGER ;
C_INIT_FILE_NAME : STRING ;
DEFAULT_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0);
width : INTEGER;
depth : INTEGER)
RETURN mem_type IS
VARIABLE init_return : mem_type := (OTHERS => (OTHERS => '0'));
FILE init_file : TEXT;
VARIABLE mem_vector : BIT_VECTOR(width-1 DOWNTO 0);
VARIABLE bitline : LINE;
variable bitsgood : boolean := true;
variable bitchar : character;
VARIABLE i : INTEGER;
VARIABLE j : INTEGER;
BEGIN
--Display output message indicating that the behavioral model is being
--initialized
ASSERT (NOT (C_USE_DEFAULT_DATA=1 OR C_LOAD_INIT_FILE=1)) REPORT " Block Memory Generator CORE Generator module loading initial data..." SEVERITY NOTE;
-- Setup the default data
-- Default data is with respect to write_port_A and may be wider
-- or narrower than init_return width. The following loops map
-- default data into the memory
IF (C_USE_DEFAULT_DATA=1) THEN
FOR i IN 0 TO depth-1 LOOP
init_return(i) := DEFAULT_DATA;
END LOOP;
END IF;
-- Read in the .mif file
-- The init data is formatted with respect to write port A dimensions.
-- The init_return vector is formatted with respect to minimum width and
-- maximum depth; the following loops map the .mif file into the memory
IF (C_LOAD_INIT_FILE=1) THEN
file_open(init_file, C_INIT_FILE_NAME, read_mode);
i := 0;
WHILE (i < depth AND NOT endfile(init_file)) LOOP
mem_vector := (OTHERS => '0');
readline(init_file, bitline);
-- read(file_buffer, mem_vector(file_buffer'LENGTH-1 DOWNTO 0));
FOR j IN 0 TO width-1 LOOP
read(bitline,bitchar,bitsgood);
init_return(i)(width-1-j) := char_to_std_logic(bitchar);
END LOOP;
i := i + 1;
END LOOP;
file_close(init_file);
END IF;
RETURN init_return;
END FUNCTION;
--***************************************************************
-- convert bit to STD_LOGIC
--***************************************************************
constant c_init : mem_type := init_memory(0,
0,
"no_coe_file_loaded",
DEFAULT_DATA,
32,
8192);
constant rom : mem_type := c_init;
BEGIN
EXPECTED_DATA <= rom(conv_integer(unsigned(check_read_addr)));
CHECKER_RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => CHECK_DATA_2R,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => CHECK_READ_ADDR
);
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R ='1') THEN
IF(EXPECTED_DATA = DATA_IN) THEN
STATUS<='0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
-- Simulatable ROM
--Synthesizable ROM
SYNTH_CHECKER: IF(C_ROM_SYNTH = 1) GENERATE
PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(CHECK_DATA_2R='1') THEN
IF(DATA_IN=DEFAULT_DATA) THEN
STATUS <= '0';
ELSE
STATUS <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE;
READ_ADDR_INT(12 DOWNTO 0) <= READ_ADDR(12 DOWNTO 0);
ADDRA <= READ_ADDR_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
RD_PROCESS: PROCESS (CLK)
BEGIN
IF (RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_READ <= '0';
ELSE
DO_READ <= '1';
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(0),
CLK =>CLK,
RST=>RST,
D =>DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => DO_READ_REG(I),
CLK =>CLK,
RST=>RST,
D =>DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
CHECK_DATA_REG_1: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_2R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA_R
);
CHECK_DATA_REG: ENTITY work.REGISTER_LOGIC_SROM
PORT MAP(
Q => CHECK_DATA_R,
CLK =>CLK,
RST=>RST,
D =>CHECK_DATA
);
END ARCHITECTURE;
| gpl-2.0 | 4fd6255fa0abf8bb9e95cd31791bee1d | 0.547903 | 3.686091 | false | false | false | false |
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