repo_name
stringlengths 6
79
| path
stringlengths 6
236
| copies
int64 1
472
| size
int64 137
1.04M
| content
stringlengths 137
1.04M
| license
stringclasses 15
values | hash
stringlengths 32
32
| alpha_frac
float64 0.25
0.96
| ratio
float64 1.51
17.5
| autogenerated
bool 1
class | config_or_test
bool 2
classes | has_no_keywords
bool 1
class | has_few_assignments
bool 1
class |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
plessl/zippy | vhdl/testbenches/tb_fifo2.vhd | 1 | 9,268 | ------------------------------------------------------------------------------
-- Testbench for fifo2.vhd
--
-- Project :
-- File : tb_fifo2.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/25
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_Fifo2 is
end tb_Fifo2;
architecture arch of tb_Fifo2 is
constant WIDTH : integer := 8; -- Data width
constant DEPTH : integer := 4; -- FIFO depth
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, wr, wr1, wr2, wr3, wr4, wr5, wr6, wr7, wr0,
rd, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd0, r_w, done);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- FIFO data and control/status signals
signal FifoModexSI : std_logic;
signal FifoWExEI : std_logic;
signal FifoRExEI : std_logic;
signal FifoDinxDI : std_logic_vector(WIDTH-1 downto 0);
signal FifoDoutxDO : std_logic_vector(WIDTH-1 downto 0);
signal FifoEmptyxSO : std_logic;
signal FifoFullxSO : std_logic;
signal FifoFillLevelxDO : std_logic_vector(log2(DEPTH) downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : Fifo2
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ModexSI => FifoModexSI,
WExEI => FifoWExEI,
RExEI => FifoRExEI,
DinxDI => FifoDinxDI,
DoutxDO => FifoDoutxDO,
EmptyxSO => FifoEmptyxSO,
FullxSO => FifoFullxSO,
FillLevelxDO => FifoFillLevelxDO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
FifoModexSI <= '1';
tbStatus <= rst;
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= wr1; -- write #1
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(10, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr2; -- write #2
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(20, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr3; -- write #3
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(30, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd1; -- read #1
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= wr4; -- write #4
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(40, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd2; -- read #2
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= wr5; -- write #5
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(50, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr6; -- write #6
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(60, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr0; -- write #0 (fifo is full...)
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(61, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd3; -- read #3
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd4; -- read #4
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= wr7; -- write #7
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(70, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd5; -- read #5
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd6; -- read #6
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd7; -- read #7
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd0; -- read #0 (fifo is empty...)
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for 3*CLK_PERIOD;
-------------------------------------------------------------------------
-- now test what happens if read and write are both set at the same time
-------------------------------------------------------------------------
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(11, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(22, WIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= r_w; -- read AND write
FifoWExEI <= '1';
FifoRExEI <= '1';
FifoDinxDI <= std_logic_vector(to_unsigned(33, WIDTH));
wait for CLK_PERIOD;
FifoDinxDI <= std_logic_vector(to_unsigned(44, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(55, WIDTH));
wait for CLK_PERIOD;
tbStatus <= wr; -- write
FifoWExEI <= '1';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(66, WIDTH));
wait for CLK_PERIOD;
-- now FIFO is full ----------------------------------------------------
tbStatus <= r_w; -- read AND write
FifoWExEI <= '1';
FifoRExEI <= '1';
FifoDinxDI <= std_logic_vector(to_unsigned(67, WIDTH)); -- => no write
wait for CLK_PERIOD;
FifoDinxDI <= std_logic_vector(to_unsigned(77, WIDTH)); -- => write
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
-- now FIFO is empty ---------------------------------------------------
tbStatus <= r_w; -- read AND write
FifoWExEI <= '1';
FifoRExEI <= '1';
FifoDinxDI <= std_logic_vector(to_unsigned(88, WIDTH));
wait for CLK_PERIOD;
FifoDinxDI <= std_logic_vector(to_unsigned(99, WIDTH));
wait for CLK_PERIOD;
tbStatus <= rd; -- read
FifoWExEI <= '0';
FifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= done; -- done
FifoWExEI <= '0';
FifoRExEI <= '0';
FifoDinxDI <= std_logic_vector(to_unsigned(0, WIDTH));
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | d6419b1c865a6378930c647549b26bdb | 0.47432 | 3.69243 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_fifoctrl.vhd | 1 | 5,945 | ------------------------------------------------------------------------------
-- Testbench for fifoctrl.vhd
--
-- Project :
-- File : tb_fifoctrl.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/17
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_FifoCtrl is
end tb_FifoCtrl;
architecture arch of tb_FifoCtrl is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, ifwrite, ifread, engwrite, engread,
bothwrite, bothread);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- FIFO signals
signal RunningxSI : std_logic;
signal EngInPortxEI : std_logic;
signal EngOutPortxEI : std_logic;
signal DecFifoWExEI : std_logic;
signal DecFifoRExEI : std_logic;
signal FifoMuxSO : std_logic;
signal FifoWExEO : std_logic;
signal FifoRExEO : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : FifoCtrl
port map (
RunningxSI => RunningxSI,
EngInPortxEI => EngInPortxEI,
EngOutPortxEI => EngOutPortxEI,
DecFifoWExEI => DecFifoWExEI,
DecFifoRExEI => DecFifoRExEI,
FifoMuxSO => FifoMuxSO,
FifoWExEO => FifoWExEO,
FifoRExEO => FifoRExEO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal RunningxSI : out std_logic;
signal EngInPortxEI : out std_logic;
signal EngOutPortxEI : out std_logic;
signal DecFifoWExEI : out std_logic;
signal DecFifoRExEI : out std_logic) is
begin
RunningxSI <= '0';
EngInPortxEI <= '0';
EngOutPortxEI <= '0';
DecFifoWExEI <= '0';
DecFifoRExEI <= '0';
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= ifwrite; -- interface write
DecFifoWExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= ifread; -- interface read
DecFifoRExEI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= engwrite; -- engine write
EngOutPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= engread; -- engine read
EngInPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= bothwrite; -- interface AND engine write
DecFifoWExEI <= '1'; -- (should be prevented...)
EngOutPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for CLK_PERIOD;
tbStatus <= bothread; -- interface AND engine read
DecFifoRExEI <= '1'; -- (should be prevented...)
EngInPortxEI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '0';
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
init_stimuli(RunningxSI, EngInPortxEI, EngOutPortxEI, DecFifoWExEI,
DecFifoRExEI);
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 23b687a320c8f200b0483b5031a66898 | 0.515559 | 4.011471 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstadpcm_virt/tb_tstadpcm_virt.vhd | 1 | 14,660 | ------------------------------------------------------------------------------
-- Testbench for the ADPCM configuration for the zippy array
--
-- Project :
-- File : $Id: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- This testbench tests the ADPCM configuration for the zunit
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTADPCM_VIRT.all;
entity tb_tstadpcm_virt is
end tb_tstadpcm_virt;
architecture arch of tb_tstadpcm_virt is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 1024; -- nr. of data elements
constant DELAY : integer := 2; -- processing delay of circuit,
-- due to pipeliningq
constant CONTEXTS : integer := 3;
constant NRUNCYCLES : integer := NDATA+DELAY; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_context0, wr_context1,
wr_context2, set_cmptr, set_cntxt,
push_data_fifo0, push_data_fifo1, inlevel,
wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
signal processSample : integer := -1;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration signals
signal Context0Cfg : engineConfigRec := tstadpcmcfg_p0;
signal Context1Cfg : engineConfigRec := tstadpcmcfg_p1;
signal Context2Cfg : engineConfigRec := tstadpcmcfg_p2;
signal Context0xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context0Cfg);
signal Context1xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context1Cfg);
signal Context2xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context2Cfg);
signal Context0Prt : cfgPartArray := partition_config(Context0xD);
signal Context1Prt : cfgPartArray := partition_config(Context1xD);
signal Context2Prt : cfgPartArray := partition_config(Context2xD);
file HFILE : text open write_mode is "tstadpcm_virt_cfg.h";
-- set dumpResults to true if the response and the expected response
-- shall be dumped to HFILE for post simulation verification
-- (instead of doing the verification in the testbench)
signal dumpResults : boolean := false;
file RESFILE : text open write_mode is "tstadpcm_virt_cfg.simout";
type fifo_array is array (0 to (3*NDATA)-1) of
std_logic_vector(DATAWIDTH-1 downto 0);
file TVFILE : text open read_mode is "test.adpcm.txt"; -- adpcm encoded
-- input file
file ERFILE : text open read_mode is "test.pcm.txt"; -- decoded file in
-- PCM format
begin -- arch
assert (N_COLS = 4) report "configuration requires N_COLS = 4" severity failure;
assert (N_ROWS = 4) report "configuration requires N_ROWS = 4" severity failure;
assert (N_HBUSN >= 2) report "configuration requires N_HBUSN >=2" severity failure;
assert (N_HBUSS >= 1) report "configuration requires N_HBUSS >=1" severity failure;
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
variable contextArr : contextPartArray :=
(others => (others => (others => '0')));
begin -- process hFileGen
contextArr(0) := Context0Prt;
contextArr(1) := Context1Prt;
contextArr(2) := Context2Prt;
-- need only 3 contexts
gen_contexthfile2(HFILE, contextArr);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable expectedresponse : std_logic_vector(DATAWIDTH-1 downto 0) := (others => '0');
variable l : line;
variable tv : std_logic_vector(3 downto 0);
variable tvstring : string(tv'range);
variable expr : std_logic_vector(15 downto 0);
variable exprstring : string(expr'range);
variable tvcount : integer := 0;
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 0 (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_context0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in Context0Prt'low to Context0Prt'high loop
DataInxD <= Context0Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 1 (ZREG_CFGMEM1:W)
-- -----------------------------------------------
tbStatus <= wr_context1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1, IFWIDTH));
for i in Context1Prt'low to Context1Prt'high loop
DataInxD <= Context1Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 2 (ZREG_CFGMEM2:W)
-- -----------------------------------------------
tbStatus <= wr_context2;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM2, IFWIDTH));
for i in Context2Prt'low to Context2Prt'high loop
DataInxD <= Context2Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
while not endfile(TVFILE) loop
readline(TVFILE, l);
read(l, tvstring);
tv := to_std_logic_vector(tvstring); -- defined in txt_util
DataInxD <= (others => '0');
DataInxD(3 downto 0) <= tv;
tvcount := tvcount + 1;
wait for CLK_PERIOD;
end loop;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- run circuit with virtualization
---------------------------------------------------------------------------
for runcycle in 0 to NDATA+DELAY-1 loop
for context in 0 to CONTEXTS-1 loop
processSample <= runcycle;
-- set context select register (ZREG_CONTEXTSEL:W)
tbStatus <= set_cntxt;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CONTEXTSEL, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(context, IFWIDTH));
wait for CLK_PERIOD;
-- write cycle count register (ZREG_CYCLECNT:W)
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
wait for CLK_PERIOD;
-- run computation of current context
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
end loop; -- context
end loop; -- runcycle
-------------------------------------------------
-- pop DELAY words from out buffer (ZREG_FIFO1:R)
-- delay of circuit due to registers (pipelining)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for DELAY*CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
if dumpResults then
print(RESFILE, "result / expected result");
end if;
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
if not endfile(ERFILE) then
readline(ERFILE, l);
read(l, exprstring);
expr := to_std_logic_vector(exprstring);
else
expr := (others => '0');
end if;
expectedresponse := std_logic_vector(resize(signed(expr), DATAWIDTH));
response := DataOutxD(DATAWIDTH-1 downto 0);
if dumpResults then
print (RESFILE, str(to_integer(signed(response))) & " " &
str(to_integer(signed(expectedresponse))));
else
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & hstr(response) &
" does NOT match expected response "
& hstr(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & hstr(response) & " matches expected " &
"response " & hstr(expectedresponse) & " tv: " & str(i)
severity note;
end if;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 3743b7a1390f32ed970897b2267f21b3 | 0.493724 | 4.08812 | false | false | false | false |
rhalstea/cidr_15_fpga_join | probe_engine/vhdl/generic_register.vhd | 2 | 762 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity generic_register is
generic (
DATA_WIDTH : natural := 32
);
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_register;
architecture Behavioral of generic_register is
begin
process (clk)
begin
if rising_edge(clk) then
if rst = '1' then
data_out <= (others => '0');
else
data_out <= data_in;
end if;
end if;
end process;
end Behavioral;
| bsd-3-clause | 07931e36d37485043496987f67423599 | 0.476378 | 4.096774 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_schedulectrl.vhd | 1 | 4,782 | ------------------------------------------------------------------------------
-- Testbench for schedulectrl.vhd
--
-- Project :
-- File : tb_schedulectrl.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003-10-17
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.componentsPkg.all;
use work.auxPkg.all;
entity tb_ScheduleCtrl is
end tb_ScheduleCtrl;
architecture arch of tb_ScheduleCtrl is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, done ,fsm_idle, fsm_startswitch,
fsm_runswitch, fsm_run, fsm_last);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- DUT signals
signal StartxEI : std_logic;
signal RunningxSI : std_logic;
signal LastxSI : std_logic;
signal SwitchxEO : std_logic;
signal BusyxSO : std_logic;
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ScheduleCtrl
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
StartxEI => StartxEI,
RunningxSI => RunningxSI,
LastxSI => LastxSI,
SwitchxEO => SwitchxEO,
BusyxSO => BusyxSO);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
procedure init_stimuli (
signal StartxEI : out std_logic;
signal RunningxSI : out std_logic;
signal LastxSI : out std_logic
) is
begin
StartxEI <= '0';
RunningxSI <= '0';
LastxSI <= '0';
end init_stimuli;
begin -- process stimuliTb
tbStatus <= rst;
init_stimuli(StartxEI, RunningxSI, LastxSI);
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= idle;
init_stimuli(StartxEI, RunningxSI, LastxSI);
wait for CLK_PERIOD;
tbStatus <= fsm_idle;
RunningxSI <= '0';
LastxSI <= '0';
wait for CLK_PERIOD;
RunningxSI <= '1';
LastxSI <= '0';
wait for CLK_PERIOD;
RunningxSI <= '0';
LastxSI <= '1';
wait for CLK_PERIOD;
RunningxSI <= '1';
LastxSI <= '1';
wait for CLK_PERIOD;
tbStatus <= idle;
init_stimuli(StartxEI, RunningxSI, LastxSI);
wait for CLK_PERIOD;
tbStatus <= fsm_startswitch;
StartxEI <= '1';
wait for CLK_PERIOD;
tbStatus <= fsm_run;
StartxEI <= '0';
RunningxSI <= '1'; -- supposed to go high
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= fsm_runswitch;
StartxEI <= '0';
RunningxSI <= '0'; -- goes low
wait for CLK_PERIOD;
tbStatus <= fsm_run;
StartxEI <= '0';
RunningxSI <= '1'; -- supposed to go high
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= fsm_last;
StartxEI <= '0';
RunningxSI <= '0'; -- goes low
LastxSI <= '1'; -- is high
wait for CLK_PERIOD;
tbStatus <= fsm_idle;
StartxEI <= '0';
RunningxSI <= '0';
LastxSI <= '1'; -- is high
wait for CLK_PERIOD;
wait for CLK_PERIOD;
tbStatus <= done;
init_stimuli(StartxEI, RunningxSI, LastxSI);
wait for CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 4e8bc2b4c85bd6950e8e9616b152039b | 0.48578 | 4.059423 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/testePlaca/bcdTo7SEG.vhd | 1 | 1,171 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 17:04:14 05/14/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;
entity bcdTo7SEG is
port (
clk: in std_logic;
bcd: in std_logic_vector(3 downto 0);
segmented: out std_logic_vector(6 downto 0)
);
end bcdTo7SEG;
architecture Behavioral of bcdTo7SEG is
begin
process(clk)
begin
if(clk'event AND clk = '1') then
case bcd is
when "0000"=> segmented <="0000001";
when "0001"=> segmented <="1001111";
when "0010"=> segmented <="0010010";
when "0011"=> segmented <="0000110";
when "0100"=> segmented <="1001100";
when "0101"=> segmented <="0100100";
when "0110"=> segmented <="0100000";
when "0111"=> segmented <="0001111";
when "1000"=> segmented <="0000000";
when "1001"=> segmented <="0000100";
when others=> segmented <="1111111";
end case;
end if;
end process;
end Behavioral;
| mit | fd4784aedf966c4ec329e649b516477f | 0.656704 | 3.131016 | false | false | false | false |
tmeissner/raspberrypi | raspiFpga/src/EfbSpiSlave.vhd | 1 | 11,834 | -- VHDL netlist generated by SCUBA Diamond_2.2_Production (99)
-- Module Version: 1.1
--/usr/local/diamond/2.2/ispfpga/bin/lin/scuba -w -n EfbSpiSlave -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo2c00 -freq 26.6 -spi -spi_mode Slave -spi_rxr -spi_txr -spi_en -wb -dev 7000 -e
-- Thu Dec 4 21:37:18 2014
library IEEE;
use IEEE.std_logic_1164.all;
-- synopsys translate_off
library MACHXO2;
use MACHXO2.components.all;
-- synopsys translate_on
entity EfbSpiSlave is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_we_i: in std_logic;
wb_adr_i: in std_logic_vector(7 downto 0);
wb_dat_i: in std_logic_vector(7 downto 0);
wb_dat_o: out std_logic_vector(7 downto 0);
wb_ack_o: out std_logic;
spi_clk: inout std_logic;
spi_miso: inout std_logic;
spi_mosi: inout std_logic;
spi_scsn: in std_logic;
spi_irq: out std_logic);
end EfbSpiSlave;
architecture Structure of EfbSpiSlave is
-- internal signal declarations
signal scuba_vhi: std_logic;
signal spi_mosi_oe: std_logic;
signal spi_mosi_o: std_logic;
signal spi_miso_oe: std_logic;
signal spi_miso_o: std_logic;
signal spi_clk_oe: std_logic;
signal spi_clk_o: std_logic;
signal spi_mosi_i: std_logic;
signal spi_miso_i: std_logic;
signal spi_clk_i: std_logic;
signal scuba_vlo: std_logic;
-- local component declarations
component VHI
port (Z: out std_logic);
end component;
component VLO
port (Z: out std_logic);
end component;
component BB
port (I: in std_logic; T: in std_logic; O: out std_logic;
B: inout std_logic);
end component;
component EFB
generic (EFB_I2C1 : in String; EFB_I2C2 : in String;
EFB_SPI : in String; EFB_TC : in String;
EFB_TC_PORTMODE : in String; EFB_UFM : in String;
EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String;
UFM_INIT_PAGES : in Integer;
UFM_INIT_START_PAGE : in Integer;
UFM_INIT_ALL_ZEROS : in String;
UFM_INIT_FILE_NAME : in String;
UFM_INIT_FILE_FORMAT : in String;
I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String;
I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String;
I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String;
I2C1_CLK_DIVIDER : in Integer;
I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String;
I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String;
I2C2_WAKEUP : in String; SPI_MODE : in String;
SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String;
SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String;
SPI_SLAVE_HANDSHAKE : in String;
SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String;
SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String;
SPI_WAKEUP : in String; TC_MODE : in String;
TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer;
GSR : in String; TC_TOP_SET : in Integer;
TC_OCR_SET : in Integer; TC_OC_MODE : in String;
TC_RESETN : in String; TC_TOP_SEL : in String;
TC_OV_INT : in String; TC_OCR_INT : in String;
TC_ICR_INT : in String; TC_OVERFLOW : in String;
TC_ICAPTURE : in String);
port (WBCLKI: in std_logic; WBRSTI: in std_logic;
WBCYCI: in std_logic; WBSTBI: in std_logic;
WBWEI: in std_logic; WBADRI7: in std_logic;
WBADRI6: in std_logic; WBADRI5: in std_logic;
WBADRI4: in std_logic; WBADRI3: in std_logic;
WBADRI2: in std_logic; WBADRI1: in std_logic;
WBADRI0: in std_logic; WBDATI7: in std_logic;
WBDATI6: in std_logic; WBDATI5: in std_logic;
WBDATI4: in std_logic; WBDATI3: in std_logic;
WBDATI2: in std_logic; WBDATI1: in std_logic;
WBDATI0: in std_logic; PLL0DATI7: in std_logic;
PLL0DATI6: in std_logic; PLL0DATI5: in std_logic;
PLL0DATI4: in std_logic; PLL0DATI3: in std_logic;
PLL0DATI2: in std_logic; PLL0DATI1: in std_logic;
PLL0DATI0: in std_logic; PLL0ACKI: in std_logic;
PLL1DATI7: in std_logic; PLL1DATI6: in std_logic;
PLL1DATI5: in std_logic; PLL1DATI4: in std_logic;
PLL1DATI3: in std_logic; PLL1DATI2: in std_logic;
PLL1DATI1: in std_logic; PLL1DATI0: in std_logic;
PLL1ACKI: in std_logic; I2C1SCLI: in std_logic;
I2C1SDAI: in std_logic; I2C2SCLI: in std_logic;
I2C2SDAI: in std_logic; SPISCKI: in std_logic;
SPIMISOI: in std_logic; SPIMOSII: in std_logic;
SPISCSN: in std_logic; TCCLKI: in std_logic;
TCRSTN: in std_logic; TCIC: in std_logic;
UFMSN: in std_logic; WBDATO7: out std_logic;
WBDATO6: out std_logic; WBDATO5: out std_logic;
WBDATO4: out std_logic; WBDATO3: out std_logic;
WBDATO2: out std_logic; WBDATO1: out std_logic;
WBDATO0: out std_logic; WBACKO: out std_logic;
PLLCLKO: out std_logic; PLLRSTO: out std_logic;
PLL0STBO: out std_logic; PLL1STBO: out std_logic;
PLLWEO: out std_logic; PLLADRO4: out std_logic;
PLLADRO3: out std_logic; PLLADRO2: out std_logic;
PLLADRO1: out std_logic; PLLADRO0: out std_logic;
PLLDATO7: out std_logic; PLLDATO6: out std_logic;
PLLDATO5: out std_logic; PLLDATO4: out std_logic;
PLLDATO3: out std_logic; PLLDATO2: out std_logic;
PLLDATO1: out std_logic; PLLDATO0: out std_logic;
I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic;
I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic;
I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic;
I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic;
I2C1IRQO: out std_logic; I2C2IRQO: out std_logic;
SPISCKO: out std_logic; SPISCKEN: out std_logic;
SPIMISOO: out std_logic; SPIMISOEN: out std_logic;
SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic;
SPIMCSN7: out std_logic; SPIMCSN6: out std_logic;
SPIMCSN5: out std_logic; SPIMCSN4: out std_logic;
SPIMCSN3: out std_logic; SPIMCSN2: out std_logic;
SPIMCSN1: out std_logic; SPIMCSN0: out std_logic;
SPICSNEN: out std_logic; SPIIRQO: out std_logic;
TCINT: out std_logic; TCOC: out std_logic;
WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic;
CFGSTDBY: out std_logic);
end component;
attribute NGD_DRC_MASK : integer;
attribute NGD_DRC_MASK of Structure : architecture is 1;
begin
-- component instantiation statements
scuba_vhi_inst: VHI
port map (Z=>scuba_vhi);
BBspi_mosi: BB
port map (I=>spi_mosi_o, T=>spi_mosi_oe, O=>spi_mosi_i,
B=>spi_mosi);
BBspi_miso: BB
port map (I=>spi_miso_o, T=>spi_miso_oe, O=>spi_miso_i,
B=>spi_miso);
BBspi_clk: BB
port map (I=>spi_clk_o, T=>spi_clk_oe, O=>spi_clk_i, B=>spi_clk);
scuba_vlo_inst: VLO
port map (Z=>scuba_vlo);
EFBInst_0: EFB
generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 0,
UFM_INIT_PAGES=> 0, DEV_DENSITY=> "7000L", EFB_UFM=> "DISABLED",
TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM",
TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED",
SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED",
SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "ENABLED",
SPI_INTR_TXRDY=> "ENABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED",
SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "SLAVE",
EFB_SPI=> "ENABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010",
I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT",
EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "26.6")
port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3),
WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1),
WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7),
WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5),
WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3),
WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1),
WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo,
PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo,
PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo,
PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo,
PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo,
PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo,
PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo,
PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo,
PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo,
PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo,
I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo,
I2C2SDAI=>scuba_vlo, SPISCKI=>spi_clk_i,
SPIMISOI=>spi_miso_i, SPIMOSII=>spi_mosi_i,
SPISCSN=>spi_scsn, TCCLKI=>scuba_vlo, TCRSTN=>scuba_vlo,
TCIC=>scuba_vlo, UFMSN=>scuba_vhi, WBDATO7=>wb_dat_o(7),
WBDATO6=>wb_dat_o(6), WBDATO5=>wb_dat_o(5),
WBDATO4=>wb_dat_o(4), WBDATO3=>wb_dat_o(3),
WBDATO2=>wb_dat_o(2), WBDATO1=>wb_dat_o(1),
WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o, PLLCLKO=>open,
PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open, PLLWEO=>open,
PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open,
PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open,
PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open,
PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open,
PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open,
I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open,
I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open,
I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>spi_clk_o,
SPISCKEN=>spi_clk_oe, SPIMISOO=>spi_miso_o,
SPIMISOEN=>spi_miso_oe, SPIMOSIO=>spi_mosi_o,
SPIMOSIEN=>spi_mosi_oe, SPIMCSN7=>open, SPIMCSN6=>open,
SPIMCSN5=>open, SPIMCSN4=>open, SPIMCSN3=>open,
SPIMCSN2=>open, SPIMCSN1=>open, SPIMCSN0=>open,
SPICSNEN=>open, SPIIRQO=>spi_irq, TCINT=>open, TCOC=>open,
WBCUFMIRQ=>open, CFGWAKE=>open, CFGSTDBY=>open);
end Structure;
| gpl-2.0 | 0421d63a6b64e915e0e17e9c67db3e6b | 0.570644 | 2.904762 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/idle_pattern.vhd | 1 | 5,425 | ----------------------------------------------------------------------------------
-- Module Name: idle_pattern - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity idle_pattern is
port (
clk : in std_logic;
data0 : out std_logic_vector(7 downto 0);
data0k : out std_logic;
data1 : out std_logic_vector(7 downto 0);
data1k : out std_logic;
switch_point : out std_logic
);
end idle_pattern;
architecture arch of idle_pattern is
signal count : unsigned(12 downto 0) := (others => '0');
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0x3
constant VB_ID : std_logic_vector(8 downto 0) := "000001001"; -- 0x00 VB-ID with no video asserted
constant Mvid : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant D102 : std_logic_vector(8 downto 0) := "001001010"; -- D10.2
signal d0: std_logic_vector(8 downto 0);
signal d1: std_logic_vector(8 downto 0);
begin
data0 <= d0(7 downto 0);
data0k <= d0(8);
data1 <= d1(7 downto 0);
data1k <= d1(8);
process(clk)
begin
if rising_edge(clk) then
switch_point <= '0';
if count = 0 then
d0 <= DUMMY;
d1 <= DUMMY;
elsif count = 2 then
d0 <= BS;
d1 <= VB_ID;
elsif count = 4 then
d0 <= Mvid;
d1 <= Maud;
elsif count = 6 then
d0 <= VB_ID;
d1 <= Mvid;
elsif count = 8 then
d0 <= Maud;
d1 <= VB_ID;
elsif count = 10 then
d0 <= Mvid;
d1 <= Maud;
elsif count = 12 then
d0 <= VB_ID;
d1 <= Mvid;
elsif count = 14 then
d0 <= Maud;
d1 <= DUMMY;
elsif count = 16 then
d0 <= DUMMY;
d1 <= DUMMY;
else
d0 <= DUMMY;
d1 <= DUMMY;
switch_point <= '1'; -- can switch to the actual video at any other time
-- other than when the BS, VB-ID, Mvid, Maud sequence
end if;
count <= count + 2;
end if;
end process;
end architecture; | mit | 493fad1fd8b99a618070cc728f2cfbbf | 0.49106 | 4.29193 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpAudioCodec/unitI2SToAvalonST/hdl/I2SToAvalonST_tb.vhd | 1 | 2,702 | -------------------------------------------------------------------------------
-- Title : Testbench for design "I2SToAvalonST"
-- Project :
-------------------------------------------------------------------------------
-- File : I2SToAvalonST_tb.vhd
-- Author : <fxst@FXST-PC>
-- Company :
-- Created : 2017-05-23
-- Last update: 2017-05-23
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2017
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2017-05-23 1.0 fxst Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
entity I2SToAvalonST_tb is
end entity I2SToAvalonST_tb;
-------------------------------------------------------------------------------
architecture Bhv of I2SToAvalonST_tb is
-- component generics
constant gDataWidth : natural := 24;
constant gDataWidthLen : natural := 5;
-- component ports
signal iClk : std_logic := '1';
signal inReset : std_logic := '0';
signal iDAT : std_logic := '1';
signal iLRC : std_logic := '0';
signal iBCLK : std_logic := '1';
signal oLeftData : std_logic_vector(gDataWidth-1 downto 0);
signal oLeftValid : std_logic;
signal oRightData : std_logic_vector(gDataWidth-1 downto 0);
signal oRightValid : std_logic;
begin -- architecture Bhv
-- component instantiation
DUT: entity work.I2SToAvalonST
generic map (
gDataWidth => gDataWidth,
gDataWidthLen => gDataWidthLen)
port map (
iClk => iClk,
inReset => inReset,
iDAT => iDAT,
iLRC => iLRC,
iBCLK => iBCLK,
oLeftData => oLeftData,
oLeftValid => oLeftValid,
oRightData => oRightData,
oRightValid => oRightValid);
-- clock generation
iClk <= not iClk after 10 ns;
-- BCLK generation
iBCLK <= not iBCLK after 10 us;
process (iBCLK) is
begin -- process
if falling_edge(iBCLK) then
iDAT <= not iDAT;
end if;
end process;
-- waveform generation
WaveGen_Proc: process
begin
-- insert signal assignments here
inReset <= '1' after 10 ns;
iLRC <= '0' after 0 ns,
'1' after 30 us,
'0' after 600 us;
wait;
end process WaveGen_Proc;
end architecture Bhv;
| gpl-3.0 | dd97507a368c83776c11d0f86cefe561 | 0.458179 | 4.415033 | false | false | false | false |
rhalstea/cidr_15_fpga_join | probe_engine/vhdl/generic_register_chain.vhd | 2 | 1,550 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity generic_register_chain is
generic (
DATA_WIDTH : natural := 32;
CHAIN_LENGTH : natural := 1
);
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end generic_register_chain;
architecture Behavioral of generic_register_chain is
type CHAIN_ARRAY is array(CHAIN_LENGTH downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal chain : CHAIN_ARRAY;
component generic_register is
generic (
DATA_WIDTH : natural := 32
);
port (
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
begin
chain(CHAIN_LENGTH) <= data_in;
REGS: for i in CHAIN_LENGTH-1 downto 0 generate
REG_I: generic_register generic map (
DATA_WIDTH => DATA_WIDTH
)
port map (
clk => clk,
rst => rst,
data_in => chain(i+1),
data_out => chain(i)
);
end generate;
data_out <= chain(0);
end Behavioral;
| bsd-3-clause | 5f74628a65d082540d07c90f60a1f1a8 | 0.479355 | 4.144385 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpPlatform/unitPlatformHps/synlayQuartus/subsystemA/Platform_inst.vhd | 1 | 22,847 | component Platform is
port (
clk_clk : in std_logic := 'X'; -- clk
dds_left_strobe_export : in std_logic := 'X'; -- export
dds_right_strobe_export : in std_logic := 'X'; -- export
hex0_2_export : out std_logic_vector(20 downto 0); -- export
hex3_5_export : out std_logic_vector(20 downto 0); -- export
hps_io_hps_io_emac1_inst_TX_CLK : out std_logic; -- hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 : out std_logic; -- hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 : out std_logic; -- hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 : out std_logic; -- hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 : out std_logic; -- hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO : inout std_logic := 'X'; -- hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC : out std_logic; -- hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL : out std_logic; -- hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK : in std_logic := 'X'; -- hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 : in std_logic := 'X'; -- hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 : inout std_logic := 'X'; -- hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 : out std_logic; -- hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK : out std_logic; -- hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD : inout std_logic := 'X'; -- hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 : inout std_logic := 'X'; -- hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 : inout std_logic := 'X'; -- hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK : out std_logic; -- hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 : inout std_logic := 'X'; -- hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 : inout std_logic := 'X'; -- hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 : inout std_logic := 'X'; -- hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 : inout std_logic := 'X'; -- hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 : inout std_logic := 'X'; -- hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 : inout std_logic := 'X'; -- hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 : inout std_logic := 'X'; -- hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 : inout std_logic := 'X'; -- hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 : inout std_logic := 'X'; -- hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 : inout std_logic := 'X'; -- hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK : in std_logic := 'X'; -- hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP : out std_logic; -- hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR : in std_logic := 'X'; -- hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT : in std_logic := 'X'; -- hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK : out std_logic; -- hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI : out std_logic; -- hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO : in std_logic := 'X'; -- hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 : out std_logic; -- hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX : in std_logic := 'X'; -- hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX : out std_logic; -- hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA : inout std_logic := 'X'; -- hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL : inout std_logic := 'X'; -- hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 : inout std_logic := 'X'; -- hps_io_gpio_inst_GPIO61
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic; -- SCLK
i2s_codec_iadcdat : in std_logic := 'X'; -- iadcdat
i2s_codec_iadclrc : in std_logic := 'X'; -- iadclrc
i2s_codec_ibclk : in std_logic := 'X'; -- ibclk
i2s_codec_idaclrc : in std_logic := 'X'; -- idaclrc
i2s_codec_odacdat : out std_logic; -- odacdat
i2s_gpio_iadcdat : in std_logic := 'X'; -- iadcdat
i2s_gpio_iadclrc : in std_logic := 'X'; -- iadclrc
i2s_gpio_ibclk : in std_logic := 'X'; -- ibclk
i2s_gpio_idaclrc : in std_logic := 'X'; -- idaclrc
i2s_gpio_odacdat : out std_logic; -- odacdat
keys_export : in std_logic_vector(2 downto 0) := (others => 'X'); -- export
leds_export : out std_logic_vector(9 downto 0); -- export
memory_mem_a : out std_logic_vector(14 downto 0); -- mem_a
memory_mem_ba : out std_logic_vector(2 downto 0); -- mem_ba
memory_mem_ck : out std_logic; -- mem_ck
memory_mem_ck_n : out std_logic; -- mem_ck_n
memory_mem_cke : out std_logic; -- mem_cke
memory_mem_cs_n : out std_logic; -- mem_cs_n
memory_mem_ras_n : out std_logic; -- mem_ras_n
memory_mem_cas_n : out std_logic; -- mem_cas_n
memory_mem_we_n : out std_logic; -- mem_we_n
memory_mem_reset_n : out std_logic; -- mem_reset_n
memory_mem_dq : inout std_logic_vector(31 downto 0) := (others => 'X'); -- mem_dq
memory_mem_dqs : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs
memory_mem_dqs_n : inout std_logic_vector(3 downto 0) := (others => 'X'); -- mem_dqs_n
memory_mem_odt : out std_logic; -- mem_odt
memory_mem_dm : out std_logic_vector(3 downto 0); -- mem_dm
memory_oct_rzqin : in std_logic := 'X'; -- oct_rzqin
reset_reset_n : in std_logic := 'X'; -- reset_n
strobe_export : out std_logic; -- export
switches_export : in std_logic_vector(9 downto 0) := (others => 'X'); -- export
white_noise_left_strobe_export : in std_logic := 'X'; -- export
white_noise_right_strobe_export : in std_logic := 'X'; -- export
xck_clk : out std_logic -- clk
);
end component Platform;
u0 : component Platform
port map (
clk_clk => CONNECTED_TO_clk_clk, -- clk.clk
dds_left_strobe_export => CONNECTED_TO_dds_left_strobe_export, -- dds_left_strobe.export
dds_right_strobe_export => CONNECTED_TO_dds_right_strobe_export, -- dds_right_strobe.export
hex0_2_export => CONNECTED_TO_hex0_2_export, -- hex0_2.export
hex3_5_export => CONNECTED_TO_hex3_5_export, -- hex3_5.export
hps_io_hps_io_emac1_inst_TX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CLK, -- hps_io.hps_io_emac1_inst_TX_CLK
hps_io_hps_io_emac1_inst_TXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD0, -- .hps_io_emac1_inst_TXD0
hps_io_hps_io_emac1_inst_TXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD1, -- .hps_io_emac1_inst_TXD1
hps_io_hps_io_emac1_inst_TXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD2, -- .hps_io_emac1_inst_TXD2
hps_io_hps_io_emac1_inst_TXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_TXD3, -- .hps_io_emac1_inst_TXD3
hps_io_hps_io_emac1_inst_RXD0 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD0, -- .hps_io_emac1_inst_RXD0
hps_io_hps_io_emac1_inst_MDIO => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDIO, -- .hps_io_emac1_inst_MDIO
hps_io_hps_io_emac1_inst_MDC => CONNECTED_TO_hps_io_hps_io_emac1_inst_MDC, -- .hps_io_emac1_inst_MDC
hps_io_hps_io_emac1_inst_RX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CTL, -- .hps_io_emac1_inst_RX_CTL
hps_io_hps_io_emac1_inst_TX_CTL => CONNECTED_TO_hps_io_hps_io_emac1_inst_TX_CTL, -- .hps_io_emac1_inst_TX_CTL
hps_io_hps_io_emac1_inst_RX_CLK => CONNECTED_TO_hps_io_hps_io_emac1_inst_RX_CLK, -- .hps_io_emac1_inst_RX_CLK
hps_io_hps_io_emac1_inst_RXD1 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD1, -- .hps_io_emac1_inst_RXD1
hps_io_hps_io_emac1_inst_RXD2 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD2, -- .hps_io_emac1_inst_RXD2
hps_io_hps_io_emac1_inst_RXD3 => CONNECTED_TO_hps_io_hps_io_emac1_inst_RXD3, -- .hps_io_emac1_inst_RXD3
hps_io_hps_io_qspi_inst_IO0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO0, -- .hps_io_qspi_inst_IO0
hps_io_hps_io_qspi_inst_IO1 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO1, -- .hps_io_qspi_inst_IO1
hps_io_hps_io_qspi_inst_IO2 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO2, -- .hps_io_qspi_inst_IO2
hps_io_hps_io_qspi_inst_IO3 => CONNECTED_TO_hps_io_hps_io_qspi_inst_IO3, -- .hps_io_qspi_inst_IO3
hps_io_hps_io_qspi_inst_SS0 => CONNECTED_TO_hps_io_hps_io_qspi_inst_SS0, -- .hps_io_qspi_inst_SS0
hps_io_hps_io_qspi_inst_CLK => CONNECTED_TO_hps_io_hps_io_qspi_inst_CLK, -- .hps_io_qspi_inst_CLK
hps_io_hps_io_sdio_inst_CMD => CONNECTED_TO_hps_io_hps_io_sdio_inst_CMD, -- .hps_io_sdio_inst_CMD
hps_io_hps_io_sdio_inst_D0 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D0, -- .hps_io_sdio_inst_D0
hps_io_hps_io_sdio_inst_D1 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D1, -- .hps_io_sdio_inst_D1
hps_io_hps_io_sdio_inst_CLK => CONNECTED_TO_hps_io_hps_io_sdio_inst_CLK, -- .hps_io_sdio_inst_CLK
hps_io_hps_io_sdio_inst_D2 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D2, -- .hps_io_sdio_inst_D2
hps_io_hps_io_sdio_inst_D3 => CONNECTED_TO_hps_io_hps_io_sdio_inst_D3, -- .hps_io_sdio_inst_D3
hps_io_hps_io_usb1_inst_D0 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D0, -- .hps_io_usb1_inst_D0
hps_io_hps_io_usb1_inst_D1 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D1, -- .hps_io_usb1_inst_D1
hps_io_hps_io_usb1_inst_D2 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D2, -- .hps_io_usb1_inst_D2
hps_io_hps_io_usb1_inst_D3 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D3, -- .hps_io_usb1_inst_D3
hps_io_hps_io_usb1_inst_D4 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D4, -- .hps_io_usb1_inst_D4
hps_io_hps_io_usb1_inst_D5 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D5, -- .hps_io_usb1_inst_D5
hps_io_hps_io_usb1_inst_D6 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D6, -- .hps_io_usb1_inst_D6
hps_io_hps_io_usb1_inst_D7 => CONNECTED_TO_hps_io_hps_io_usb1_inst_D7, -- .hps_io_usb1_inst_D7
hps_io_hps_io_usb1_inst_CLK => CONNECTED_TO_hps_io_hps_io_usb1_inst_CLK, -- .hps_io_usb1_inst_CLK
hps_io_hps_io_usb1_inst_STP => CONNECTED_TO_hps_io_hps_io_usb1_inst_STP, -- .hps_io_usb1_inst_STP
hps_io_hps_io_usb1_inst_DIR => CONNECTED_TO_hps_io_hps_io_usb1_inst_DIR, -- .hps_io_usb1_inst_DIR
hps_io_hps_io_usb1_inst_NXT => CONNECTED_TO_hps_io_hps_io_usb1_inst_NXT, -- .hps_io_usb1_inst_NXT
hps_io_hps_io_spim1_inst_CLK => CONNECTED_TO_hps_io_hps_io_spim1_inst_CLK, -- .hps_io_spim1_inst_CLK
hps_io_hps_io_spim1_inst_MOSI => CONNECTED_TO_hps_io_hps_io_spim1_inst_MOSI, -- .hps_io_spim1_inst_MOSI
hps_io_hps_io_spim1_inst_MISO => CONNECTED_TO_hps_io_hps_io_spim1_inst_MISO, -- .hps_io_spim1_inst_MISO
hps_io_hps_io_spim1_inst_SS0 => CONNECTED_TO_hps_io_hps_io_spim1_inst_SS0, -- .hps_io_spim1_inst_SS0
hps_io_hps_io_uart0_inst_RX => CONNECTED_TO_hps_io_hps_io_uart0_inst_RX, -- .hps_io_uart0_inst_RX
hps_io_hps_io_uart0_inst_TX => CONNECTED_TO_hps_io_hps_io_uart0_inst_TX, -- .hps_io_uart0_inst_TX
hps_io_hps_io_i2c0_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SDA, -- .hps_io_i2c0_inst_SDA
hps_io_hps_io_i2c0_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c0_inst_SCL, -- .hps_io_i2c0_inst_SCL
hps_io_hps_io_i2c1_inst_SDA => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SDA, -- .hps_io_i2c1_inst_SDA
hps_io_hps_io_i2c1_inst_SCL => CONNECTED_TO_hps_io_hps_io_i2c1_inst_SCL, -- .hps_io_i2c1_inst_SCL
hps_io_hps_io_gpio_inst_GPIO09 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO09, -- .hps_io_gpio_inst_GPIO09
hps_io_hps_io_gpio_inst_GPIO35 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO35, -- .hps_io_gpio_inst_GPIO35
hps_io_hps_io_gpio_inst_GPIO48 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO48, -- .hps_io_gpio_inst_GPIO48
hps_io_hps_io_gpio_inst_GPIO53 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO53, -- .hps_io_gpio_inst_GPIO53
hps_io_hps_io_gpio_inst_GPIO54 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO54, -- .hps_io_gpio_inst_GPIO54
hps_io_hps_io_gpio_inst_GPIO61 => CONNECTED_TO_hps_io_hps_io_gpio_inst_GPIO61, -- .hps_io_gpio_inst_GPIO61
i2c_SDAT => CONNECTED_TO_i2c_SDAT, -- i2c.SDAT
i2c_SCLK => CONNECTED_TO_i2c_SCLK, -- .SCLK
i2s_codec_iadcdat => CONNECTED_TO_i2s_codec_iadcdat, -- i2s_codec.iadcdat
i2s_codec_iadclrc => CONNECTED_TO_i2s_codec_iadclrc, -- .iadclrc
i2s_codec_ibclk => CONNECTED_TO_i2s_codec_ibclk, -- .ibclk
i2s_codec_idaclrc => CONNECTED_TO_i2s_codec_idaclrc, -- .idaclrc
i2s_codec_odacdat => CONNECTED_TO_i2s_codec_odacdat, -- .odacdat
i2s_gpio_iadcdat => CONNECTED_TO_i2s_gpio_iadcdat, -- i2s_gpio.iadcdat
i2s_gpio_iadclrc => CONNECTED_TO_i2s_gpio_iadclrc, -- .iadclrc
i2s_gpio_ibclk => CONNECTED_TO_i2s_gpio_ibclk, -- .ibclk
i2s_gpio_idaclrc => CONNECTED_TO_i2s_gpio_idaclrc, -- .idaclrc
i2s_gpio_odacdat => CONNECTED_TO_i2s_gpio_odacdat, -- .odacdat
keys_export => CONNECTED_TO_keys_export, -- keys.export
leds_export => CONNECTED_TO_leds_export, -- leds.export
memory_mem_a => CONNECTED_TO_memory_mem_a, -- memory.mem_a
memory_mem_ba => CONNECTED_TO_memory_mem_ba, -- .mem_ba
memory_mem_ck => CONNECTED_TO_memory_mem_ck, -- .mem_ck
memory_mem_ck_n => CONNECTED_TO_memory_mem_ck_n, -- .mem_ck_n
memory_mem_cke => CONNECTED_TO_memory_mem_cke, -- .mem_cke
memory_mem_cs_n => CONNECTED_TO_memory_mem_cs_n, -- .mem_cs_n
memory_mem_ras_n => CONNECTED_TO_memory_mem_ras_n, -- .mem_ras_n
memory_mem_cas_n => CONNECTED_TO_memory_mem_cas_n, -- .mem_cas_n
memory_mem_we_n => CONNECTED_TO_memory_mem_we_n, -- .mem_we_n
memory_mem_reset_n => CONNECTED_TO_memory_mem_reset_n, -- .mem_reset_n
memory_mem_dq => CONNECTED_TO_memory_mem_dq, -- .mem_dq
memory_mem_dqs => CONNECTED_TO_memory_mem_dqs, -- .mem_dqs
memory_mem_dqs_n => CONNECTED_TO_memory_mem_dqs_n, -- .mem_dqs_n
memory_mem_odt => CONNECTED_TO_memory_mem_odt, -- .mem_odt
memory_mem_dm => CONNECTED_TO_memory_mem_dm, -- .mem_dm
memory_oct_rzqin => CONNECTED_TO_memory_oct_rzqin, -- .oct_rzqin
reset_reset_n => CONNECTED_TO_reset_reset_n, -- reset.reset_n
strobe_export => CONNECTED_TO_strobe_export, -- strobe.export
switches_export => CONNECTED_TO_switches_export, -- switches.export
white_noise_left_strobe_export => CONNECTED_TO_white_noise_left_strobe_export, -- white_noise_left_strobe.export
white_noise_right_strobe_export => CONNECTED_TO_white_noise_right_strobe_export, -- white_noise_right_strobe.export
xck_clk => CONNECTED_TO_xck_clk -- xck.clk
);
| gpl-3.0 | 1210e66722ac8edafd3d3f21a717a959 | 0.438219 | 3.167036 | false | false | false | false |
plessl/zippy | vhdl/testbenches/tb_contextmux.vhd | 1 | 5,583 | ------------------------------------------------------------------------------
-- Testbench for contextmux.vhd
--
-- Project :
-- File : tb_contextmux.vhd
-- Author : Rolf Enzler <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/15
-- Last changed: $LastChangedDate: 2004-10-05 17:10:36 +0200 (Tue, 05 Oct 2004) $
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ComponentsPkg.all;
use work.AuxPkg.all;
use work.ConfigPkg.all;
entity tb_ContextMux is
end tb_ContextMux;
architecture arch of tb_ContextMux is
constant NINP : integer := 8; -- 8:1 MUX
constant NSEL : integer := log2(NINP); -- width of select signal
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal ccount : integer := 1;
type tbstatusType is (rst, idle, sel0, sel1, sel2, sel3, sel4, sel5, sel6,
sel7);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data and control/status signals
signal SelxS : std_logic_vector(NSEL-1 downto 0);
signal Inp : contextArray;
signal OutxD : contextType;
signal OutTailxD : std_logic_vector(15 downto 0);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ContextMux
generic map (
NINP => NINP)
port map (
SelxSI => SelxS,
InpxI => Inp,
OutxDO => OutxD);
----------------------------------------------------------------------------
-- aux. signals for easier waveform inspection
----------------------------------------------------------------------------
OutTailxD <= OutxD(15 downto 0);
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
begin -- process stimuliTb
tbStatus <= rst;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
Inp(0) <= std_logic_vector(to_unsigned(0, ENGN_CFGLEN));
Inp(1) <= std_logic_vector(to_unsigned(1, ENGN_CFGLEN));
Inp(2) <= std_logic_vector(to_unsigned(2, ENGN_CFGLEN));
Inp(3) <= std_logic_vector(to_unsigned(3, ENGN_CFGLEN));
Inp(4) <= std_logic_vector(to_unsigned(4, ENGN_CFGLEN));
Inp(5) <= std_logic_vector(to_unsigned(5, ENGN_CFGLEN));
Inp(6) <= std_logic_vector(to_unsigned(6, ENGN_CFGLEN));
Inp(7) <= std_logic_vector(to_unsigned(7, ENGN_CFGLEN));
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
wait for CLK_PERIOD*0.25;
tbStatus <= sel0; -- sel0
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel1; -- sel1
SelxS <= std_logic_vector(to_unsigned(1, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel2; -- sel2
SelxS <= std_logic_vector(to_unsigned(2, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel3; -- sel3
SelxS <= std_logic_vector(to_unsigned(3, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel4; -- sel4
SelxS <= std_logic_vector(to_unsigned(4, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel5; -- sel5
SelxS <= std_logic_vector(to_unsigned(5, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel6; -- sel6
SelxS <= std_logic_vector(to_unsigned(6, NSEL));
wait for CLK_PERIOD;
tbStatus <= sel7; -- sel7
SelxS <= std_logic_vector(to_unsigned(7, NSEL));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
Inp(0) <= std_logic_vector(to_unsigned(0, ENGN_CFGLEN));
wait for 2*CLK_PERIOD;
tbStatus <= sel1; -- sel1, vary input
SelxS <= std_logic_vector(to_unsigned(1, NSEL));
wait for CLK_PERIOD;
Inp(1) <= std_logic_vector(to_unsigned(30, ENGN_CFGLEN));
wait for CLK_PERIOD;
Inp(1) <= std_logic_vector(to_unsigned(31, ENGN_CFGLEN));
wait for CLK_PERIOD;
Inp(1) <= std_logic_vector(to_unsigned(32, ENGN_CFGLEN));
wait for CLK_PERIOD;
tbStatus <= idle;
SelxS <= std_logic_vector(to_unsigned(0, NSEL));
Inp(1) <= std_logic_vector(to_unsigned(0, ENGN_CFGLEN));
wait for 2*CLK_PERIOD;
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "stimuli processed; sim. terminated after " & int2str(ccount) &
" cycles"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
ccount <= ccount + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | 9cf9f85568fe2110106af496d2cab11f | 0.497403 | 3.726969 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/PC.vhd | 1 | 1,041 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 00:17:12 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity PC_register is
port (
clk : in std_logic;
rst : in std_logic;
cargaPC : in std_logic;
incrementaPC: in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0)
);
end PC_register;
architecture Behavioral of PC_register is
signal data: std_logic_vector(7 downto 0);
begin
process(clk, rst)
begin
if (rst = '1') then
data <= "00000000";
elsif(clk = '1' AND clk'event) then
if (cargaPC = '1') then
data <= data_in;
elsif (incrementaPC = '1') then
data <= std_logic_vector(unsigned(data) + 1);
end if;
end if;
end process;
data_out <= data;
end Behavioral; | mit | f9ef15c0a76406c537e6943c2b55cb26 | 0.621518 | 2.907821 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/test_streams/test_source_800_600_RGB_444_ch1.vhd | 1 | 13,918 | ----------------------------------------------------------------------------------
-- Module Name: test_source_800_600_RGB_444 - Behavioral
--
-- Description: Generate a valid DisplayPort symbol stream for testing. In this
-- case 800x600 white screen.
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity test_source_800_600_RGB_444_ch1 is
port (
-----------------------------------------------------
-- The MSA values (some are range reduced and could
-- be 16 bits ins size)
-----------------------------------------------------
M_value : out std_logic_vector(23 downto 0);
N_value : out std_logic_vector(23 downto 0);
H_visible : out std_logic_vector(11 downto 0);
V_visible : out std_logic_vector(11 downto 0);
H_total : out std_logic_vector(11 downto 0);
V_total : out std_logic_vector(11 downto 0);
H_sync_width : out std_logic_vector(11 downto 0);
V_sync_width : out std_logic_vector(11 downto 0);
H_start : out std_logic_vector(11 downto 0);
V_start : out std_logic_vector(11 downto 0);
H_vsync_active_high : out std_logic;
V_vsync_active_high : out std_logic;
flag_sync_clock : out std_logic;
flag_YCCnRGB : out std_logic;
flag_422n444 : out std_logic;
flag_YCC_colour_709 : out std_logic;
flag_range_reduced : out std_logic;
flag_interlaced_even : out std_logic;
flags_3d_Indicators : out std_logic_vector(1 downto 0);
bits_per_colour : out std_logic_vector(4 downto 0);
stream_channel_count : out std_logic_vector(2 downto 0);
clk : in std_logic;
ready : out std_logic;
data : out std_logic_vector(72 downto 0) := (others => '0')
);
end test_source_800_600_RGB_444_ch1;
architecture arch of test_source_800_600_RGB_444_ch1 is
type a_test_data_blocks is array (0 to 64*6-1) of std_logic_vector(8 downto 0);
constant DUMMY : std_logic_vector(8 downto 0) := "000000011"; -- 0xAA
constant SPARE : std_logic_vector(8 downto 0) := "011111111"; -- 0xFF
constant ZERO : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant PIX_80 : std_logic_vector(8 downto 0) := "011001100"; -- 0x80
constant SS : std_logic_vector(8 downto 0) := "101011100"; -- K28.2
constant SE : std_logic_vector(8 downto 0) := "111111101"; -- K29.7
constant BE : std_logic_vector(8 downto 0) := "111111011"; -- K27.7
constant BS : std_logic_vector(8 downto 0) := "110111100"; -- K28.5
constant SR : std_logic_vector(8 downto 0) := "100011100"; -- K28.0
constant FS : std_logic_vector(8 downto 0) := "111111110"; -- K30.7
constant FE : std_logic_vector(8 downto 0) := "111110111"; -- K23.7
constant VB_VS : std_logic_vector(8 downto 0) := "000000001"; -- 0x00 VB-ID with Vertical blank asserted
constant VB_NVS : std_logic_vector(8 downto 0) := "000000000"; -- 0x00 VB-ID without Vertical blank asserted
constant Mvid : std_logic_vector(8 downto 0) := "001101000"; -- 0x68
constant Maud : std_logic_vector(8 downto 0) := "000000000"; -- 0x00
constant test_data_blocks : a_test_data_blocks := (
--- Block 0 - Junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 1 - 8 white pixels and padding
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
FS, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, FE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
BS, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, VB_NVS, MVID, MAUD, VB_NVS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
PIX_80, PIX_80, PIX_80, PIX_80, PIX_80, PIX_80,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
BS, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, VB_VS, MVID, MAUD, VB_VS, MVID,
MAUD, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE,
--- Block 5 - just blank end
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, DUMMY,
DUMMY, DUMMY, DUMMY, DUMMY, DUMMY, BE,
SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE, SPARE);
signal index : unsigned (8 downto 0) := (others => '0'); -- Index up to 32 x 64 symbol blocks
signal d0: std_logic_vector(8 downto 0) := (others => '0');
signal d1: std_logic_vector(8 downto 0) := (others => '0');
signal line_count : unsigned(9 downto 0) := (others => '0');
signal row_count : unsigned(7 downto 0) := (others => '0');
signal switch_point : std_logic := '0';
begin
M_value <= x"012F68";
N_value <= x"080000";
H_visible <= x"320"; -- 800
V_visible <= x"258"; -- 600
H_total <= x"420"; -- 1056
V_total <= x"274"; -- 628
H_sync_width <= x"080"; -- 128
V_sync_width <= x"004"; -- 4
H_start <= x"0D8"; -- 216
V_start <= x"01b"; -- 37
H_vsync_active_high <= '0';
V_vsync_active_high <= '0';
flag_sync_clock <= '1';
flag_YCCnRGB <= '0';
flag_422n444 <= '0';
flag_range_reduced <= '0';
flag_interlaced_even <= '0';
flag_YCC_colour_709 <= '0';
flags_3d_Indicators <= (others => '0');
bits_per_colour <= "01000";
stream_channel_count <= "001";
ready <= '1';
data(72) <= switch_point;
data(71 downto 18) <= (others => '0');
data(17 downto 0) <= d1 & d0;
process(clk)
begin
if rising_edge(clk) then
d0 <= test_data_blocks(to_integer(index+0));
d1 <= test_data_blocks(to_integer(index+1));
if index(5 downto 0) = 52 then
index(5 downto 0) <= (others => '0');
if row_count = 131 then
row_count <= (others => '0');
if line_count = 627 then
line_count <= (others => '0');
else
line_count <= line_count + 1;
end if;
else
row_count <= row_count +1;
end if;
--- Block 0 - Junk
--- Block 1- 8 white pixels and padding
--- Block 2 - 8 white pixels and padding, VB-ID (-vsync), Mvid, MAud and junk
--- Block 3 - 8 white pixels and padding, VB-ID (+vsync), Mvid, MAud and junk
--- Block 4 - DUMMY,Blank Start, VB-ID (+vsync), Mvid, MAud and junk
--- Block 5 - just blank end
index(8 downto 6) <= "000"; -- Dummy symbols
switch_point <= '0';
if line_count < 599 then -- lines of active video (except first and last)
if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE
elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill
elsif row_count = 100 then index(8 downto 6) <= "010"; -- Pixels BS and VS-ID block (no VBLANK flag)
end if;
elsif line_count = 599 then -- Last line of active video
if row_count < 1 then index(8 downto 6) <= "101"; -- Just blank end BE
elsif row_count < 100 then index(8 downto 6) <= "001"; -- Pixels plus fill
elsif row_count = 100 then index(8 downto 6) <= "011"; -- Pixels BS and VS-ID block (with VBLANK flag)
end if;
else
-----------------------------------------------------------------
-- Allow switching to/from the idle pattern during the vertical blank
-----------------------------------------------------------------
if row_count < 100 then switch_point <= '1';
elsif row_count = 100 then index(8 downto 6) <= "100"; -- Dummy symbols, BS and VS-ID block (with VBLANK flag)
end if;
end if;
else
index <= index + 2;
end if;
end if;
end process;
end architecture; | mit | 49ae98c86724efebd0bc013d3a67f8c5 | 0.515088 | 3.642502 | false | false | false | false |
plessl/zippy | vhdl/zunit.vhd | 1 | 21,745 | ------------------------------------------------------------------------------
-- multi-context ZIPPY unit
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/zunit.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2002/06/25
-- $Id: zunit.vhd 478 2006-03-21 13:37:54Z plessl $
------------------------------------------------------------------------------
-- Top level entity the defines the whole multi-context Zippy unit. All
-- top-level comonents (Engine, Configuration memory, host interface decoder,
-- FIFOs, Controllers, context scheduler) are instantiated and connected.
-------------------------------------------------------------------------------
-- TODO: Check for all occurences of RunningxS and CycleDnCntxD whether they
-- are used to control activities of the zunit. These signals are generated by
-- the old scheduler, and should be replaced by the corresponding signals that
-- are generated by the new generic Scheduler component.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
entity ZUnit is
generic (
IFWIDTH : integer;
DATAWIDTH : integer;
CCNTWIDTH : integer;
FIFODEPTH : integer);
port (
ClkxC : in std_logic;
RstxRB : in std_logic;
WExEI : in std_logic;
RExEI : in std_logic;
AddrxDI : in std_logic_vector(IFWIDTH-1 downto 0);
DataxDI : in std_logic_vector(IFWIDTH-1 downto 0);
DataxDO : out std_logic_vector(IFWIDTH-1 downto 0));
begin
-- assert statements (is there a better place for this?)
SIWformat : assert SIW_WRDWIDTH >= SIW_CONWIDTH+SIW_CYCWIDTH+SIW_ADRWIDTH+1
report "ERROR: incorrect SIW format definition"
severity error;
end ZUnit;
architecture simple of ZUnit is
-- Interface Signals
signal IFWExE : std_logic;
signal IFRExE : std_logic;
signal IFAddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal IFDataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal IFDataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- Decoded Control Signals
signal DecRstxRB : std_logic;
signal DecLoadCCxE : std_logic;
signal DecFifo0WExE : std_logic;
signal DecFifo0RExE : std_logic;
signal DecFifo1WExE : std_logic;
signal DecFifo1RExE : std_logic;
signal DecCMWExE : std_logic_vector(N_CONTEXTS-1 downto 0);
signal DecCMLoadPtrxE : std_logic_vector(N_CONTEXTS-1 downto 0);
signal DecCSRxE : std_logic;
signal DecEngClrCntxtxE : std_logic;
signal DecDoutMuxS : std_logic_vector(2 downto 0);
signal DecSSWExE : std_logic;
signal DecSSIAddrxD : std_logic_vector(SIW_ADRWIDTH-1 downto 0);
signal DecScheduleStartxE : std_logic;
signal DecContextSchedulerSelectxE : std_logic;
-- signals for context sequencer
signal SchedContextSequencerxD : EngineScheduleControlType;
signal SchedTemporalPartitioningxD : EngineScheduleControlType;
signal EngineScheduleControlxE : EngineScheduleControlType;
-- indicates that the currently selected context scheduler has done
-- its work
signal ContextSchedulerDonexS : std_logic;
-- 0: old context sequencer/cycle counter scheduler
-- 1: temporal partitioning scheduler
signal ContextSchedulerSelectxD : std_logic;
signal TPSchedulerStartxE : std_logic;
signal TPSchedulerDonexS : std_logic;
-- signals for virtualization support (temporal partitioning)
signal dummy0, dummy1 : std_logic;
signal DecVirtContextNoxE : std_logic;
signal VirtContextNoxD : std_logic_vector(IFWIDTH-1 downto 0);
signal VirtContextNoxDus : unsigned(CNTXTWIDTH-1 downto 0);
signal VirtUserCycleNoxD : std_logic_vector(IFWIDTH-1 downto 0);
signal VirtUserCycleNoxDus : unsigned(IFWIDTH-1 downto 0);
-- Misc. Signals
signal CSSchedulerRunningxS : std_logic;
signal CCLoadxE : std_logic;
signal CCMuxS : std_logic;
signal IFCCinxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CCinxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleDnCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal CycleUpCntxD : std_logic_vector(CCNTWIDTH-1 downto 0);
signal ContextxS : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal Contexts : contextArray;
signal DataInxD : data_word;
signal IFCSRinxD : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal CSRinxD : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal CSREnxE : std_logic;
-- signal CSRMuxS : std_logic;
-- FIFO signals
signal Fifo0MuxS : std_logic;
signal Fifo0WExE : std_logic;
signal Fifo0RExE : std_logic;
signal Fifo0InxD : data_word;
signal Fifo0OutxD : data_word;
signal Fifo0FillxD : std_logic_vector(log2(FIFODEPTH) downto 0);
signal Fifo1MuxS : std_logic;
signal Fifo1WExE : std_logic;
signal Fifo1RExE : std_logic;
signal Fifo1InxD : data_word;
signal Fifo1OutxD : data_word;
signal Fifo1FillxD : std_logic_vector(log2(FIFODEPTH) downto 0);
-- computation engine signals
signal EngCfg : engineConfigRec;
signal EngCfgxD : contextType;
signal EngInPort0xE : std_logic;
signal EngInPort1xE : std_logic;
signal EngOutPort0xE : std_logic;
signal EngOutPort1xE : std_logic;
signal EngOut0xD : data_word;
signal EngOut1xD : data_word;
signal EngClrCntxtxE : std_logic;
-- FIXME: make more generic, works only for N_IOP=2, FIFOs hardcoded
signal FifoOutxD : engineInoutDataType;
signal EngOutxD : engineInoutDataType;
signal EngInPortxE : std_logic_vector(N_IOP-1 downto 0);
signal EngOutPortxE : std_logic_vector(N_IOP-1 downto 0);
-- context scheduler signals (controller and store)
signal SchedSwitchxE : std_logic;
signal SchedBusyxS : std_logic;
signal NotSchedBusyxS : std_logic;
signal CSSchedulerDonexS : std_logic;
signal SchedLastxS : std_logic;
signal SSLastxS : std_logic;
signal SSIWordxD : std_logic_vector(SIW_WRDWIDTH-1 downto 0);
signal SSContextxD : std_logic_vector(SIW_CONWIDTH-1 downto 0);
signal SSCyclesxD : std_logic_vector(SIW_CYCWIDTH-1 downto 0);
signal SSCSRinxD : std_logic_vector(CNTXTWIDTH-1 downto 0);
signal SSCCinxD : std_logic_vector(CCNTWIDTH-1 downto 0);
-- resized output mux signals
signal Fifo0OutResxD : std_logic_vector(IFWIDTH-1 downto 0);
signal Fifo1OutResxD : std_logic_vector(IFWIDTH-1 downto 0);
signal Fifo0FillResxD : std_logic_vector(IFWIDTH-1 downto 0);
signal Fifo1FillResxD : std_logic_vector(IFWIDTH-1 downto 0);
signal CycleDnCntResxD : std_logic_vector(IFWIDTH-1 downto 0);
signal ContextSchedulerStatusResxD : std_logic_vector(IFWIDTH-1 downto 0);
-- Aux. signals
signal NCsignxS : std_logic; -- not connected
signal NCdataxS : data_word; -- not connected
signal NCifxS : std_logic_vector(IFWIDTH-1 downto 0); -- not connected
begin -- simple
Decdr : Decoder
generic map (
REGWIDTH => IFWIDTH)
port map (
RstxRB => RstxRB,
WrReqxEI => IFWExE,
RdReqxEI => IFRExE,
RegNrxDI => IFAddrxD,
SystRstxRBO => DecRstxRB,
CCloadxEO => DecLoadCCxE,
VirtContextNoxEO => DecVirtContextNoxE,
ContextSchedulerSelectxEO => DecContextSchedulerSelectxE,
Fifo0WExEO => DecFifo0WExE,
Fifo0RExEO => DecFifo0RExE,
Fifo1WExEO => DecFifo1WExE,
Fifo1RExEO => DecFifo1RExE,
CMWExEO => DecCMWExE,
CMLoadPtrxEO => DecCMLoadPtrxE,
CSRxEO => DecCSRxE,
EngClrCntxtxEO => DecEngClrCntxtxE,
SSWExEO => DecSSWExE,
SSIAddrxDO => DecSSIAddrxD,
ScheduleStartxE => DecScheduleStartxE,
DoutMuxSO => DecDoutMuxS);
MCMem : for i in N_CONTEXTS-1 downto 0 generate
CfgMem_i : ConfigMem
generic map (
CFGWIDTH => ENGN_CFGLEN,
PTRWIDTH => IFWIDTH, -- FIXME: too wide, but ok for now
SLCWIDTH => IFWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
WExEI => DecCMWExE(i),
CfgSlicexDI => IFDataInxD,
LoadSlicePtrxEI => DecCMLoadPtrxE(i),
SlicePtrxDI => IFDataInxD,
ConfigWordxDO => Contexts(i));
end generate MCMem;
VirtContextNoxDus <= resize(unsigned(VirtContextNoxD), CNTXTWIDTH);
VirtUserCycleNoxDus <= unsigned(VirtUserCycleNoxD);
TPSchedulerStartxE <= DecScheduleStartxE when (ContextSchedulerSelectxD = '1') else '0';
ContextSchedulerTp : SchedulerTemporalPartitioning
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ScheduleStartxEI => TPSchedulerStartxE,
ScheduleDonexSO => TPSchedulerDonexS,
NoTpContextsxSI => VirtContextNoxDus,
NoTpUserCyclesxSI => VirtUserCycleNoxDus,
CExEO => SchedTemporalPartitioningxD.CExE,
ClrContextxSO => SchedTemporalPartitioningxD.ClrContextxS,
ClrContextxEO => SchedTemporalPartitioningxD.ClrContextxE,
ContextxSO => SchedTemporalPartitioningxD.ContextxS,
CycleUpCntxDO => SchedTemporalPartitioningxD.CycleUpCntxD,
CycleDnCntxDO => SchedTemporalPartitioningxD.CycleDnCntxD
);
ContextScheduler : Scheduler
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
SchedulerSelectxSI => ContextSchedulerSelectxD,
SchedContextSequencerxDI => SchedContextSequencerxD,
SchedTemporalPartitioningxDI => SchedTemporalPartitioningxD,
EngineScheduleControlxEO => EngineScheduleControlxE);
ContSelReg : Reg_En
generic map (
WIDTH => CNTXTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
EnxEI => CSREnxE,
DinxDI => CSRinxD,
DoutxDO => ContextxS); -- context select for old context scheduler
-- context de-multiplexer. select one of the contexts that is fed to
-- the engine
EngCfgxD <= Contexts(to_integer(unsigned(EngineScheduleControlxE.ContextxS)));
-- FIXME: find a better name for Fifo0MuxS
-- Select source for FIFO input, either data from host interface of data
-- generated by engine.
Fifo0InxD <= DataInxD when (Fifo0MuxS = '0') else EngOut0xD;
Fifo0 : Fifo
generic map (
WIDTH => DATAWIDTH,
DEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
WExEI => Fifo0WExE,
RExEI => Fifo0RExE,
DinxDI => Fifo0InxD,
DoutxDO => Fifo0OutxD,
EmptyxSO => NCsignxS,
FullxSO => NCsignxS,
FillLevelxDO => Fifo0FillxD);
Fifo0Ctrl : FifoCtrl
port map (
RunningxSI => EngineScheduleControlxE.CExE,
EngInPortxEI => EngInPort0xE,
EngOutPortxEI => EngOutPort0xE,
DecFifoWExEI => DecFifo0WExE,
DecFifoRExEI => DecFifo0RExE,
FifoMuxSO => Fifo0MuxS,
FifoWExEO => Fifo0WExE,
FifoRExEO => Fifo0RExE);
-- FIXME: find a better name for Fifo0MuxS
-- Select source for FIFO input, either data from host interface of data
-- generated by engine.
Fifo1InxD <= DataInxD when (Fifo1MuxS = '0') else EngOut1xD;
Fifo1 : Fifo
generic map (
WIDTH => DATAWIDTH,
DEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
WExEI => Fifo1WExE,
RExEI => Fifo1RExE,
DinxDI => Fifo1InxD,
DoutxDO => Fifo1OutxD,
EmptyxSO => NCsignxS,
FullxSO => NCsignxS,
FillLevelxDO => Fifo1FillxD);
Fifo1Ctrl : FifoCtrl
port map (
RunningxSI => EngineScheduleControlxE.CExE,
EngInPortxEI => EngInPort1xE,
EngOutPortxEI => EngOutPort1xE,
DecFifoWExEI => DecFifo1WExE,
DecFifoRExEI => DecFifo1RExE,
FifoMuxSO => Fifo1MuxS,
FifoWExEO => Fifo1WExE,
FifoRExEO => Fifo1RExE);
-- connect signals from FIFOs to engine inputs (arrays). This is a workaround,
-- since the FIFOs and the corresponding signals are not generated
-- automatically generated.
FifoOutxD(0) <= Fifo0OutxD;
FifoOutxD(1) <= Fifo1OutxD;
EngOut0xD <= EngOutxD(0);
EngOut1xD <= EngOutxD(1);
EngInPort1xE <= EngInPortxE(1);
EngInPort0xE <= EngInPortxE(0);
EngOutPort1xE <= EngOutPortxE(1);
EngOutPort0xE <= EngOutPortxE(0);
CompEng : Engine
generic map (
DATAWIDTH => DATAWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
CExEI => EngineScheduleControlxE.CExE, -- RunningxS,
ConfigxI => EngCfg,
ClrContextxSI => EngineScheduleControlxE.ClrContextxS, -- CSRinxD,
ClrContextxEI => EngineScheduleControlxE.ClrContextxE, -- EngClrCntxtxE,
ContextxSI => EngineScheduleControlxE.ContextxS, -- ContextxS,
CycleDnCntxDI => EngineScheduleControlxE.CycleDnCntxD, -- CycleDnCntxD,
CycleUpCntxDI => EngineScheduleControlxE.CycleUpCntxD, -- CycleUpCntxD,
InPortxDI => FifoOutxD,
OutPortxDO => EngOutxD,
InPortxEO => EngInPortxE,
OutPortxEO => EngOutPortxE);
-- Rename the signals at the right hand side of the following assignments, to
-- better fit the new concept of a generic scheduler, that can implement many
-- context scheduling schemes.
-- FIXME: or better propagate the signal names in the component
-- instantiations
-- FIXME: even better, try to collect all context sequencer related code into
-- a SchedulerContextSequencer component
SchedContextSequencerxD.CExE <= CSSchedulerRunningxS;
SchedContextSequencerxD.ClrContextxS <= CSRinxD;
-----------------------------------------------------------------------------
-- TODO: FIXES for ADPCM temporal partitioning
-----------------------------------------------------------------------------
-- directly use the decoded signal instead of the output of Enzler's
-- context sequencer. Otherwise, we cannot use the context clear feature of
-- the architecture (ZREG_CONTEXTSELCLR).
SchedContextSequencerxD.ClrContextxE <= DecEngClrCntxtxE;
-- SchedContextSequencerxD.ClrContextxE <= EngClrCntxtxE;
-- CHANGE: always use register interface input and not the output of
-- the context scheduler
-- CSRinxD <= IFCSRinxD when (SchedBusyxS = '0') else SSCSRinxD;
CSRinxD <= IFCSRinxD;
-------------------------------------------------------------------------------
SchedContextSequencerxD.ContextxS <= ContextxS;
SchedContextSequencerxD.CycleDnCntxD <= CycleDnCntxD;
SchedContextSequencerxD.CycleUpCntxD <= CycleUpCntxD;
process (ContextSchedulerSelectxD, CSSchedulerDonexS, TPSchedulerDonexS)
begin -- process
if (ContextSchedulerSelectxD = '0') then
ContextSchedulerDonexS <= CSSchedulerDonexS;
else
ContextSchedulerDonexS <= TPSchedulerDonexS;
end if;
end process;
OutMux : Mux8to1
generic map (
WIDTH => IFWIDTH)
port map (
SelxSI => DecDoutMuxS,
In0xDI => Fifo0OutResxD,
In1xDI => Fifo0FillResxD,
In2xDI => Fifo1OutResxD,
In3xDI => Fifo1FillResxD,
In4xDI => VirtContextNoxD,
In5xDI => NCifxS,
In6xDI => ContextSchedulerStatusResxD,
In7xDI => EngineScheduleControlxE.CycleDnCntxD,
OutxDO => IFDataOutxD);
CycleDnCnt : CycleDnCntr
generic map (
CNTWIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
LoadxEI => CCLoadxE,
CinxDI => CCinxD,
OnxSO => CSSchedulerRunningxS,
CoutxDO => CycleDnCntxD);
CycleUpCnt : UpDownCounter
generic map (
WIDTH => CCNTWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => DecRstxRB,
LoadxEI => CCLoadxE,
CExEI => CSSchedulerRunningxS,
ModexSI => '0',
CinxDI => (others => '0'),
CoutxDO => CycleUpCntxD);
CtxSchedSelReg : process (ClkxC, RstxRB)
begin
if RstxRB = '0' then
ContextSchedulerSelectxD <= '0';
elsif rising_edge(ClkxC) then
if (DecContextSchedulerSelectxE = '1') then
ContextSchedulerSelectxD <= IFDataInxD(0);
end if;
end if;
end process;
-- FIXME: move these two registers into the scheduler components
VirtContextReg : Reg_En
generic map (
WIDTH => IFWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
EnxEI => DecVirtContextNoxE,
DinxDI => IFDataInxD,
DoutxDO => VirtContextNoxD);
VirtUserCycleReg : Reg_En
generic map (
WIDTH => IFWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
EnxEI => DecLoadCCxE,
DinxDI => IFDataInxD,
DoutxDO => VirtUserCycleNoxD);
SchedStore : ScheduleStore
generic map (
WRDWIDTH => SIW_WRDWIDTH,
CONWIDTH => SIW_CONWIDTH,
CYCWIDTH => SIW_CYCWIDTH,
ADRWIDTH => SIW_ADRWIDTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => DecSSWExE,
IAddrxDI => DecSSIAddrxD,
IWordxDI => SSIWordxD,
SPCclrxEI => NotSchedBusyxS,
SPCloadxEI => SchedSwitchxE,
ContextxDO => SSContextxD,
CyclesxDO => SSCyclesxD,
LastxSO => SSLastxS);
SchedCtrl : ScheduleCtrl
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
StartxEI => DecScheduleStartxE,
RunningxSI => CSSchedulerRunningxS,
LastxSI => SchedLastxS,
SwitchxEO => SchedSwitchxE,
BusyxSO => SchedBusyxS);
CSREnxE <= DecCSRxE when (SchedBusyxS = '0') else SchedSwitchxE;
-- CSRMuxS <= SchedBusyxS;
CCinxD <= IFCCinxD when (SchedBusyxS = '0') else SSCCinxD;
CycleCounterCtrl : CycleCntCtrl
port map (
DecLoadxEI => DecLoadCCxE,
SchedLoadxEI => SchedSwitchxE,
SchedBusyxSI => SchedBusyxS,
CCLoadxEO => CCLoadxE,
CCMuxSO => CCMuxS);
LastContextStatusFF : FlipFlop_Clr
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
ClrxEI => NotSchedBusyxS,
EnxEI => SchedSwitchxE,
DinxDI => SSLastxS,
DoutxDO => SchedLastxS);
ScheduleBusyStatusFF : FlipFlop
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
EnxEI => '1',
DinxDI => SchedBusyxS,
DoutxDO => CSSchedulerDonexS);
-- If the context scheduler is started the LSB of the DataInxD determines,
-- whether the context registers get cleared (1) or not (0).
-- SchedEngClrxSI => IFDataInxD(0)
EngClrCntxtCtrl : EngClearCtrl
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
DecEngClrxEI => DecEngClrCntxtxE,
SchedStartxEI => DecScheduleStartxE,
SchedSwitchxEI => SchedSwitchxE,
SchedBusyxSI => SchedBusyxS,
SchedEngClrxSI => IFDataInxD(0),
EngClrxEO => EngClrCntxtxE);
NotSchedBusyxS <= not SchedBusyxS;
-- interface signals
IFWExE <= WExEI;
IFRExE <= RExEI;
IFAddrxD <= AddrxDI;
IFDataInxD <= DataxDI;
DataxDO <= IFDataOutxD;
-- configuration format conversion
EngCfg <= to_engineConfig_rec(EngCfgxD);
-- interface signal conversion/resizing
IFCCinxD <= std_logic_vector(resize(unsigned(IFDataInxD), CCNTWIDTH));
IFCSRinxD <= std_logic_vector(resize(unsigned(IFDataInxD), CNTXTWIDTH));
DataInxD <= std_logic_vector(resize(unsigned(IFDataInxD), DATAWIDTH));
SSIWordxD <= std_logic_vector(resize(unsigned(IFDataInxD), SIW_WRDWIDTH));
Fifo0OutResxD <= std_logic_vector(resize(signed(Fifo0OutxD), IFWIDTH));
Fifo1OutResxD <= std_logic_vector(resize(signed(Fifo1OutxD), IFWIDTH));
Fifo0FillResxD <= std_logic_vector(resize(unsigned(Fifo0FillxD), IFWIDTH));
Fifo1FillResxD <= std_logic_vector(resize(unsigned(Fifo1FillxD), IFWIDTH));
CycleDnCntResxD <= std_logic_vector(resize(unsigned(CycleDnCntxD), IFWIDTH));
ContextSchedulerStatusResxD(IFWIDTH-1 downto 1) <= (others => '0');
ContextSchedulerStatusResxD(0) <= ContextSchedulerDonexS;
-- SIW format resizing
SIWContextRes : process (SSContextxD)
begin -- process SIWContextRes
if SIW_CONWIDTH > CNTXTWIDTH then
SSCSRinxD <= SSContextxD(CNTXTWIDTH-1 downto 0);
else
SSCSRinxD(CNTXTWIDTH-1 downto SIW_CONWIDTH) <= (others => '0');
SSCSRinxD(SIW_CONWIDTH-1 downto 0) <= SSContextxD;
end if;
end process SIWContextRes;
-- SIW format resizing
SIWCyclesRes : process (SSCyclesxD)
begin -- process SIWCyclesRes
if SIW_CYCWIDTH > CCNTWIDTH then
SSCCinxD <= SSCyclesxD(CNTXTWIDTH-1 downto 0);
else
SSCCinxD(CCNTWIDTH-1 downto SIW_CYCWIDTH) <= (others => '0');
SSCCinxD(SIW_CYCWIDTH-1 downto 0) <= SSCyclesxD;
end if;
end process SIWCyclesRes;
end simple;
| bsd-3-clause | c7184c5213f6577b019fe282e8e0aa85 | 0.628788 | 3.61573 | false | false | false | false |
plessl/zippy | vhdl/tb_arch/tstpass_virt/tb_tstpass_virt.vhd | 1 | 11,887 | ------------------------------------------------------------------------------
-- Testbench for the tstpass_virt configuration
--
-- Project :
-- File : $Id: $
-- Author : Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Changed : $LastChangedDate: 2004-10-26 14:50:34 +0200 (Tue, 26 Oct 2004) $
------------------------------------------------------------------------------
-- This testbench tests the tstpass_virt configuration
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.txt_util.all;
use work.AuxPkg.all;
use work.archConfigPkg.all;
use work.ZArchPkg.all;
use work.ComponentsPkg.all;
use work.ConfigPkg.all;
use work.CfgLib_TSTPASS_VIRT.all;
entity tb_tstpass_virt is
end tb_tstpass_virt;
architecture arch of tb_tstpass_virt is
-- simulation stuff
constant CLK_PERIOD : time := 100 ns;
signal cycle : integer := 1;
constant NDATA : integer := 16; -- nr. of data elements
constant DELAY : integer := 1; -- processing delay of circuit,
-- due to pipeliningq
constant CONTEXTS : integer := 2;
constant NRUNCYCLES : integer := NDATA+DELAY; -- nr. of run cycles
type tbstatusType is (tbstart, idle, done, rst, wr_context0, wr_context1,
wr_context2, set_cmptr, set_cntxt,
push_data_fifo0, wr_ncycl, rd_ncycl, running,
outlevel, pop_data, finished);
signal tbStatus : tbstatusType := idle;
-- general control signals
signal ClkxC : std_logic := '1';
signal RstxRB : std_logic;
-- data/control signals
signal WExE : std_logic;
signal RExE : std_logic;
signal AddrxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataInxD : std_logic_vector(IFWIDTH-1 downto 0);
signal DataOutxD : std_logic_vector(IFWIDTH-1 downto 0);
-- configuration signals
signal Context0Cfg : engineConfigRec := tstpasscfg_p0;
signal Context1Cfg : engineConfigRec := tstpasscfg_p1;
signal Context0xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context0Cfg);
signal Context1xD : std_logic_vector(ENGN_CFGLEN-1 downto 0) :=
to_engineConfig_vec(Context1Cfg);
signal Context0Prt : cfgPartArray := partition_config(Context0xD);
signal Context1Prt : cfgPartArray := partition_config(Context1xD);
file HFILE : text open write_mode is "tstpass_virt_cfg.h";
type tv_array is array (0 to NDATA-1) of integer;
constant TESTV : tv_array :=
( 1, 2, 3, 5,
7, 11, 13, 17,
19, 23, 29, 31,
37, 41, 43, 47);
constant EXPRES : tv_array :=
( 1, 3, 6, 11,
18, 29, 42, 59,
78, 101, 130, 161,
198, 239, 282, 329);
begin -- arch
----------------------------------------------------------------------------
-- device under test
----------------------------------------------------------------------------
dut : ZUnit
generic map (
IFWIDTH => IFWIDTH,
DATAWIDTH => DATAWIDTH,
CCNTWIDTH => CCNTWIDTH,
FIFODEPTH => FIFODEPTH)
port map (
ClkxC => ClkxC,
RstxRB => RstxRB,
WExEI => WExE,
RExEI => RExE,
AddrxDI => AddrxD,
DataxDI => DataInxD,
DataxDO => DataOutxD);
----------------------------------------------------------------------------
-- generate .h file for coupled simulation
----------------------------------------------------------------------------
hFileGen : process
variable contextArr : contextPartArray :=
(others => (others => (others => '0')));
begin -- process hFileGen
contextArr(0) := Context0Prt;
contextArr(1) := Context1Prt;
-- need only 2 contexts
gen_contexthfile2(HFILE, contextArr);
wait;
end process hFileGen;
----------------------------------------------------------------------------
-- stimuli
----------------------------------------------------------------------------
stimuliTb : process
variable response : integer;
variable expectedresponse : integer;
variable l : line;
begin -- process stimuliTb
tbStatus <= tbstart;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '0');
wait until (ClkxC'event and ClkxC = '1' and RstxRB = '1');
tbStatus <= idle;
-- wait for CLK_PERIOD*0.25;
wait for CLK_PERIOD*0.1;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-------------------------------------------------
-- reset (ZREG_RST:W)
-------------------------------------------------
tbStatus <= rst;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_RST, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(0, IFWIDTH));
wait for CLK_PERIOD;
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 0 (ZREG_CFGMEM0:W)
-- -----------------------------------------------
tbStatus <= wr_context0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM0, IFWIDTH));
for i in Context0Prt'low to Context0Prt'high loop
DataInxD <= Context0Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-- -----------------------------------------------
-- write configuration slices to context mem 1 (ZREG_CFGMEM1:W)
-- -----------------------------------------------
tbStatus <= wr_context1;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CFGMEM1, IFWIDTH));
for i in Context1Prt'low to Context1Prt'high loop
DataInxD <= Context1Prt(i);
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
-------------------------------------------------
-- push data into FIFO0 (ZREG_FIFO0:W)
-------------------------------------------------
tbStatus <= push_data_fifo0;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO0, IFWIDTH));
for i in 0 to NDATA-1 loop
DataInxD <= (others => '0');
DataInxD(DATAWIDTH-1 downto 0) <=
std_logic_vector(to_unsigned(TESTV(i),DATAWIDTH));
-- assert false
-- report "writing to FIFO0:" & hstr(TESTV(i*3))
-- severity note;
wait for CLK_PERIOD;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
wait for CLK_PERIOD;
for runcycle in 0 to NDATA+DELAY-1 loop
for context in 0 to CONTEXTS-1 loop
-- set context select register (ZREG_CONTEXTSEL:W)
tbStatus <= set_cntxt;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CONTEXTSEL, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(context, IFWIDTH));
wait for CLK_PERIOD;
-- write cycle count register (ZREG_CYCLECNT:W)
tbStatus <= wr_ncycl;
WExE <= '1';
RExE <= '0';
AddrxD <= std_logic_vector(to_unsigned(ZREG_CYCLECNT, IFWIDTH));
DataInxD <= std_logic_vector(to_signed(1, IFWIDTH));
wait for CLK_PERIOD;
-- run computation of current context
tbStatus <= running;
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
end loop; -- context
end loop; -- runcycle
-------------------------------------------------
-- pop 1 words from out buffer (ZREG_FIFO1:R)
-- delay of circuit due to registers (pipelining)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
wait for DELAY*CLK_PERIOD;
-------------------------------------------------
-- pop data from out buffer (ZREG_FIFO1:R)
-------------------------------------------------
tbStatus <= pop_data;
WExE <= '0';
RExE <= '1';
DataInxD <= (others => '0');
AddrxD <= std_logic_vector(to_unsigned(ZREG_FIFO1, IFWIDTH));
for i in 0 to NDATA-1 loop
wait for CLK_PERIOD;
response := to_integer(signed(DataOutxD(DATAWIDTH-1 downto 0)));
expectedresponse := EXPRES(i);
assert response = expectedresponse
report "FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE" & LF &
"regression test failed, response " & str(response) &
" does NOT match expected response "
& str(expectedresponse) & " tv: " & str(i) & LF &
"FAILURE--FAILURE--FAILURE--FAILURE--FAILURE--FAILURE"
severity failure;
assert not(response = expectedresponse)
report "response " & str(response) & " matches expected " &
"response " & str(expectedresponse) & " tv: " & str(i)
severity note;
end loop; -- i
tbStatus <= idle; -- idle
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
-----------------------------------------------
-- done stop simulation
-----------------------------------------------
tbStatus <= done; -- done
WExE <= '0';
RExE <= '0';
AddrxD <= (others => '0');
DataInxD <= (others => '0');
wait for CLK_PERIOD;
---------------------------------------------------------------------------
-- stopping the simulation is done by using the following TCL script
-- in modelsim, since terminating the simulation with an assert failure is
-- a crude hack:
--
-- when {/tbStatus == done} {
-- echo "At Time $now Ending the simulation"
-- quit -f
-- }
---------------------------------------------------------------------------
-- stop simulation
wait until (ClkxC'event and ClkxC = '1');
assert false
report "Testbench successfully terminated after " & str(cycle) &
" cycles, no errors found!"
severity failure;
end process stimuliTb;
----------------------------------------------------------------------------
-- clock and reset generation
----------------------------------------------------------------------------
ClkxC <= not ClkxC after CLK_PERIOD/2;
RstxRB <= '0', '1' after CLK_PERIOD*1.25;
----------------------------------------------------------------------------
-- cycle counter
----------------------------------------------------------------------------
cyclecounter : process (ClkxC)
begin
if (ClkxC'event and ClkxC = '1') then
cycle <= cycle + 1;
end if;
end process cyclecounter;
end arch;
| bsd-3-clause | b8ebc06c6e4aab33836d503cd930bc52 | 0.474889 | 4.034963 | false | false | false | false |
FranciscoKnebel/ufrgs-projects | neander/neanderImplementation/controlunit.vhd | 1 | 6,613 | --
-- Authors: Francisco Paiva Knebel
-- Gabriel Alexandre Zillmer
--
-- Universidade Federal do Rio Grande do Sul
-- Instituto de Informática
-- Sistemas Digitais
-- Prof. Fernanda Lima Kastensmidt
--
-- Create Date: 10:16:51 05/03/2016
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity controlunit is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
enable_neander : in STD_LOGIC;
--regNZ
N : in STD_LOGIC;
Z : in STD_LOGIC;
--decoder
execNOP, execSTA, execLDA, execADD, execOR, execSHR, execSHL, execMUL,
execAND, execNOT, execJMP, execJN, execJZ, execHLT : in STD_LOGIC;
-- operation selector
sel_ula : out STD_LOGIC_VECTOR(2 downto 0);
-- registers loads
loadAC : out STD_LOGIC;
loadPC : out STD_LOGIC;
loadREM : out STD_LOGIC;
loadRDM : out STD_LOGIC;
loadRI : out STD_LOGIC;
loadN : out STD_LOGIC;
loadZ : out STD_LOGIC;
-- write in memory
wr_enable_mem : out STD_LOGIC_VECTOR (0 downto 0);
-- mux_rem: 0 for PC, 1 for RDM
sel : out STD_LOGIC;
-- PC increment
PC_inc : out STD_LOGIC;
-- mux_rdm: 0 for MEM, 1 for AC
sel_mux_RDM : out STD_LOGIC;
-- stop
stop : out STD_LOGIC
);
end controlunit;
architecture Behavioral of controlunit is
type state_machine is (
IDLE, BUSCA_INSTRUCAO, LER_INSTRUCAO, CARREGA_RI,
EXEC_STA2, EXEC_STA1, BUSCA_DADOS, BUSCA_ENDERECO, TRATA_JUMP, TRATA_JUMP_FAIL,
READ_MEMORY, TRATA_HLT, EXEC_ULA, EXEC_ULA2);
signal current_state : state_machine;
signal next_state : state_machine;
signal stop_s : STD_LOGIC;
begin
sync_proc: process(NEXT_STATE, RST, CLK)
begin
if (rst = '1') then
current_state <= IDLE;
elsif (clk'event AND clk = '1') then
current_state <= next_state;
end if;
end process sync_proc;
process (clk, rst)
begin
if (rst = '1') then
stop_s <= '0';
loadAC <= '0';
loadPC <= '0';
loadREM <= '0';
loadRDM <= '0';
loadRI <= '0';
loadN <= '0';
loadZ <= '0';
wr_enable_mem <= "0";
next_state <= IDLE;
elsif (clk = '1' and clk'EVENT) then
case current_state is
when IDLE =>
if (enable_neander = '1' AND stop_s /= '1') then
next_state <= BUSCA_INSTRUCAO;
else
next_state <= IDLE;
end if;
when BUSCA_INSTRUCAO => -- E0: REM <- PC
sel_mux_RDM <= '0';
loadAC <= '0';
loadPC <= '0';
PC_inc <= '0';
loadRDM <= '0';
loadRI <= '0';
wr_enable_mem <= "0";
loadN <= '0';
loadZ <= '0';
sel <= '0'; -- select 0 for PC->REM
loadREM <= '1'; -- load REM
next_state <= LER_INSTRUCAO;
when LER_INSTRUCAO => -- E1: RDM <- MEM(read), PC+
loadREM <= '0';
loadRDM <= '1';
PC_inc <= '1';
next_state <= CARREGA_RI;
when CARREGA_RI => -- E2: RI <- RDM
loadRDM <= '0';
PC_inc <= '0';
loadRI <= '1';
if (execHLT = '1') then -- HLT
next_state <= TRATA_HLT;
elsif (execNOP = '1') then -- NOP
next_state <= BUSCA_INSTRUCAO;
elsif (execNOT = '1') then -- NOT
next_state <= EXEC_ULA2;
elsif ((execJN = '1') and (N = '0')) or ((execJZ = '1') and (Z = '0')) then -- jump error
next_state <= TRATA_JUMP_FAIL;
else
next_state <= BUSCA_DADOS;
end if;
when BUSCA_DADOS => -- E3: REM <- PC
loadRI <= '0';
sel <= '0';
loadREM <= '1';
next_state <= READ_MEMORY;
when READ_MEMORY => -- E4: RDM <- MEM(read), PC+
loadREM <= '0';
loadRDM <= '1';
PC_inc <= '1';
if (execADD = '1') then -- ADD
next_state <= BUSCA_ENDERECO;
elsif (execOR = '1') then -- OR
next_state <= BUSCA_ENDERECO;
elsif (execAND = '1') then -- AND
next_state <= BUSCA_ENDERECO;
elsif (execLDA = '1') then -- LDA
next_state <= BUSCA_ENDERECO;
elsif (execSHR = '1') then -- SHR
next_state <= BUSCA_ENDERECO;
elsif (execSHL = '1') then -- SHL
next_state <= BUSCA_ENDERECO;
elsif (execMUL = '1') then -- MUL
next_state <= BUSCA_ENDERECO;
elsif (execSTA = '1') then -- STA
next_state <= BUSCA_ENDERECO;
elsif ((execJMP = '1') or ((execJN = '1') and (N = '1')) or ((execJZ = '1') and (Z = '1'))) then -- real jump
next_state <= TRATA_JUMP;
else
next_state <= IDLE;
end if;
when BUSCA_ENDERECO => -- E5: REM <- RDM
loadRDM <= '0';
PC_inc <= '0';
sel <= '1'; -- select 1 for REM<-RDM
loadREM <= '1';
if (execADD = '1') then -- ADD
next_state <= EXEC_ULA;
elsif (execOR = '1') then -- OR
next_state <= EXEC_ULA;
elsif (execAND = '1') then -- AND
next_state <= EXEC_ULA;
elsif (execLDA = '1') then -- LDA
next_state <= EXEC_ULA;
elsif (execSHR = '1') then -- SHR
next_state <= EXEC_ULA;
elsif (execSHL = '1') then -- SHL
next_state <= EXEC_ULA;
elsif (execMUL = '1') then -- MUL
next_state <= EXEC_ULA;
elsif (execSTA = '1') then -- STA
next_state <= EXEC_STA1;
end if;
when EXEC_ULA => -- E6: RDM <- MEM(read)
loadREM <= '0';
loadRDM <= '1';
if (execADD = '1') then -- ADD
sel_ula <= "000";
elsif (execAND = '1') then -- AND
sel_ula <= "001";
elsif (execOR = '1') then -- OR
sel_ula <= "010";
elsif (execNOT = '1') then -- NOT
sel_ula <= "011";
elsif (execLDA = '1') then -- LDA
sel_ula <= "100";
elsif (execSHR = '1') then -- SHR
sel_ula <= "101";
elsif (execSHL = '1') then -- SHL
sel_ula <= "110";
elsif (execMUL = '1') then -- MUL
sel_ula <= "111";
end if;
next_state <= EXEC_ULA2;
when EXEC_ULA2 => -- E7: AC <- ULA
loadRDM <= '0';
loadRI <= '0';
loadAC <= '1';
loadN <= '1';
loadZ <= '1';
next_state <= BUSCA_INSTRUCAO;
when EXEC_STA1 => -- E8: RDM <- AC
loadREM <= '0';
sel_mux_RDM <= '1'; -- select 1 for AC->RDM
loadRDM <= '1';
next_state <= EXEC_STA2;
when EXEC_STA2 => -- E9: MEM <- RDM(write)
sel_mux_RDM <= '0';
loadRDM <= '0';
wr_enable_mem <= "1";
next_state <= BUSCA_INSTRUCAO;
when TRATA_JUMP => -- E10: PC <- RDM
loadRDM <= '0';
PC_inc <= '0';
loadPC <= '1';
next_state <= BUSCA_INSTRUCAO;
when TRATA_JUMP_FAIL => -- E11: PC+
loadRI <= '0';
PC_inc <= '1';
next_state <= BUSCA_INSTRUCAO;
when TRATA_HLT => -- E12: STOP
loadRI <= '0';
stop_s <= '1';
next_state <= IDLE;
when others =>
next_state <= IDLE;
end case;
end if;
end process;
stop <= stop_s;
end; | mit | ce269a1889ece6f3ca7d1577253800a3 | 0.538334 | 2.743983 | false | false | false | false |
tmeissner/raspberrypi | raspiFpga/src/FiRoCtrlE.vhd | 1 | 6,326 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FiRoCtrlE is
generic (
EXTRACT : boolean := true
);
port (
--+ system if
Clk_i : in std_logic;
Reset_i : in std_logic;
--+ ctrl/status
Start_i : in std_logic;
Wait_i : in std_logic_vector(7 downto 0);
Run_i : in std_logic_vector(7 downto 0);
--+ rnd data
DataValid_o : out std_logic;
Data_o : out std_logic_vector(7 downto 0);
-- firo
Run_o : out std_logic;
Data_i : in std_logic
);
end entity FiRoCtrlE;
architecture rtl of FiRoCtrlE is
signal s_firo_run : std_logic;
signal s_firo_valid : std_logic;
type t_neumann_state is (BIT1, BIT2, BIT3, BIT4);
signal s_neumann_state : t_neumann_state;
signal s_neumann_buffer : std_logic_vector(2 downto 0);
type t_register_state is (SLEEP, COLLECT);
signal s_register_state : t_register_state;
signal s_register_enable : std_logic;
signal s_register_din : std_logic_vector(1 downto 0);
signal s_register_data : std_logic_vector(8 downto 0);
signal s_register_counter : unsigned(2 downto 0);
signal s_register_length : natural range 1 to 2;
signal s_data : std_logic_vector(3 downto 0);
begin
Run_o <= s_run when s_register_state = COLLECT else '0';
s_data <= s_neumann_buffer & Data_i;
ControllerP : process (Clk_i) is
variable v_wait_cnt : unsigned(7 downto 0);
variable v_run_cnt : unsigned(7 downto 0);
begin
if (rising_edge(Clk_i)) then
if (s_register_state = SLEEP) then
v_wait_cnt := unsigned(Wait_i);
v_run_cnt := unsigned(Run_i);
s_firo_run <= '0';
s_firo_valid <= '0';
else
s_firo_valid <= '0';
if (v_wait_cnt = 0) then
s_firo_run <= '1';
else
v_wait_cnt := v_wait_cnt - 1;
end if;
if (v_run_cnt = 0) then
s_firo_run <= '0';
elsif (v_run_cnt = 1) then
s_firo_valid <= '1';
else
if (v_wait_cnt = 0) then
v_run_cnt := v_run_cnt - 1;
end if;
end if;
end if;
end if;
end process ControllerP;
extractor : if EXTRACT generate
VonNeumannP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Reset_i = '0') then
s_neumann_state <= BIT1;
else
case s_neumann_state is
when BIT1 =>
s_register_enable <= '0';
if (s_firo_valid = '1') then
s_neumann_buffer(2) <= Data_i;
s_neumann_state <= BIT2;
end if;
when BIT2 =>
if (s_firo_valid = '1') then
s_neumann_buffer(1) <= Data_i;
s_neumann_state <= BIT3;
end if;
when BIT3 =>
if (s_firo_valid = '1') then
s_neumann_buffer(0) <= Data_i;
s_neumann_state <= BIT4;
end if;
when BIT4 =>
if (s_firo_valid = '1') then
s_register_enable <= '1';
s_register_length <= 1;
s_register_din <= "00";
s_neumann_state <= BIT1;
case (s_data) is
when x"5" =>
s_register_din <= "01";
when x"1" | x"6" | x"7" =>
s_register_length <= 2;
when x"2" | x"9" | x"b" =>
s_register_din <= "01";
s_register_length <= 2;
when x"4" | x"a" | x"d" =>
s_register_din <= "10";
s_register_length <= 2;
when x"8" | x"c" | x"e" =>
s_register_din <= "11";
s_register_length <= 2;
when x"0" | x"f" =>
s_register_enable <= '0';
when others => -- incl. x"3"
null;
end case;
end if;
when others =>
null;
end case;
end if;
end if;
end process VonNeumannP;
end generate;
no_extractor : if not(EXTRACT) generate
s_register_enable <= s_firo_valid;
s_register_din(0) <= Data_i;
s_register_length <= 1;
end generate;
Data_o <= s_register_data(7 downto 0);
ShiftRegisterP : process (Clk_i) is
begin
if (rising_edge(Clk_i)) then
if (Reset_i = '0') then
s_register_counter <= (others => '1');
s_register_state <= SLEEP;
DataValid_o <= '0';
else
case s_register_state is
when SLEEP =>
DataValid_o <= '0';
if (Start_i = '1' and Run_i /= x"00") then
s_register_state <= COLLECT;
s_register_data(0) <= s_register_data(8);
end if;
when COLLECT =>
if (s_register_enable = '1') then
if (s_register_counter = 0) then
s_register_data <= s_register_din(1) & s_register_data(6 downto 0) & s_register_din(0);
DataValid_o <= '1';
s_register_state <= SLEEP;
elsif (s_register_counter = 1) then
if (s_register_length = 1) then
s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
end if;
if (s_register_length = 2) then
s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
DataValid_o <= '1';
s_register_state <= SLEEP;
end if;
else
if (s_register_length = 1) then
s_register_data(7 downto 0) <= s_register_data(6 downto 0) & s_register_din(0);
else
s_register_data(7 downto 0) <= s_register_data(5 downto 0) & s_register_din;
end if;
end if;
s_register_counter <= s_register_counter - s_register_length;
end if;
when others =>
null;
end case;
end if;
end if;
end process ShiftRegisterP;
end architecture rtl;
| gpl-2.0 | 8a1e6330406fa0e1190831dcfedd244c | 0.47202 | 3.485399 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/dp_aux_messages.vhd | 1 | 12,459 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]<
--
-- Module Name: dp_aux_messages - Behavioral
--
-- Description: Messages that will be sent over thr DisplayPort AUX interface
--
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity dp_aux_messages is
port ( clk : in std_logic;
-- Interface to send messages
msg_de : in std_logic;
msg : in std_logic_vector(7 downto 0);
busy : out std_logic;
--- Interface to the AUX Channel
aux_tx_wr_en : out std_logic;
aux_tx_data : out std_logic_vector(7 downto 0));
end dp_aux_messages;
architecture arch of dp_aux_messages is
signal counter : unsigned(11 downto 0) := (others => '0');
begin
process(clk)
begin
if rising_edge(clk) then
case counter is
-- Write to I2C device at x50 (EDID)
when x"010" => aux_tx_data <= x"40"; aux_tx_wr_en <= '1';
when x"011" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"012" => aux_tx_data <= x"50"; aux_tx_wr_en <= '1';
when x"013" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"014" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Read a block of EDID data
when x"020" => aux_tx_data <= x"50"; aux_tx_wr_en <= '1';
when x"021" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"022" => aux_tx_data <= x"50"; aux_tx_wr_en <= '1';
when x"023" => aux_tx_data <= x"0F"; aux_tx_wr_en <= '1';
-- Read Sink count
when x"030" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"031" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"032" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"033" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Read DP configuration registers (12 of them)
when x"040" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"041" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"042" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"043" => aux_tx_data <= x"0B"; aux_tx_wr_en <= '1';
-- Write DPCD powerstate D3
when x"050" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"051" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"052" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"053" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"054" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
-- Set channel coding (8b/10b)
when x"060" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"061" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"062" => aux_tx_data <= x"08"; aux_tx_wr_en <= '1';
when x"063" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"064" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
-- Set link bandwidth 2.70 Gb/s
when x"070" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"071" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"072" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"073" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"074" => aux_tx_data <= x"0A"; aux_tx_wr_en <= '1';
-- Write Link Downspread
when x"080" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"081" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"082" => aux_tx_data <= x"07"; aux_tx_wr_en <= '1';
when x"083" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"084" => aux_tx_data <= x"10"; aux_tx_wr_en <= '1';
-- Set link count 1
when x"090" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"091" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"092" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"093" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"094" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1'; -- Standard framing, one channel
-- Set link count 2
when x"0A0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0A1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0A2" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0A3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0A4" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
-- Set link count 4
when x"0B0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0B1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0B2" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0B3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0B4" => aux_tx_data <= x"04"; aux_tx_wr_en <= '1';
-- Set training pattern 1
when x"0C0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0C1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0C2" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0C3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0C4" => aux_tx_data <= x"21"; aux_tx_wr_en <= '1';
-- Read link status for all four lanes
when x"0D0" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"0D1" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0D2" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0D3" => aux_tx_data <= x"07"; aux_tx_wr_en <= '1';
-- Read the Adjust_Request registers
when x"0E0" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"0E1" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0E2" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"0E3" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
-- Set training pattern 2
when x"0F0" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"0F1" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"0F2" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"0F3" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"0F4" => aux_tx_data <= x"22"; aux_tx_wr_en <= '1';
-- Resd lane align status for all four lanes
when x"100" => aux_tx_data <= x"90"; aux_tx_wr_en <= '1';
when x"101" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"102" => aux_tx_data <= x"04"; aux_tx_wr_en <= '1';
when x"103" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Turn off training patterns / Switch to normal
when x"110" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"111" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"112" => aux_tx_data <= x"02"; aux_tx_wr_en <= '1';
when x"113" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"114" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1'; -- Scrambler enabled
-- Set Premp level 0, votage 0.4V
when x"140" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"141" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"142" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"143" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"144" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"145" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"146" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
when x"147" => aux_tx_data <= x"00"; aux_tx_wr_en <= '1';
-- Set Premp level 0, votage 0.6V
when x"160" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"161" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"162" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"163" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"164" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"165" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"166" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"167" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
-- Set Premp level 0, votage 0.8V -- Max voltage
when x"180" => aux_tx_data <= x"80"; aux_tx_wr_en <= '1';
when x"181" => aux_tx_data <= x"01"; aux_tx_wr_en <= '1';
when x"182" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"183" => aux_tx_data <= x"03"; aux_tx_wr_en <= '1';
when x"184" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"185" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"186" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when x"187" => aux_tx_data <= x"06"; aux_tx_wr_en <= '1';
when others => aux_tx_data <= x"00"; aux_tx_wr_en <= '0';
end case;
----------------------------
-- Move on to the next word?
----------------------------
if counter(3 downto 0) = x"F" then
busy <= '0';
else
counter <= counter+1;
end if;
----------------------------------------
-- Are we being asked to send a message?
--
-- But only do it of we are not already
-- sending something!
----------------------------------------
if msg_de = '1' and counter(3 downto 0) = x"F" then
counter <= unsigned(msg & x"0");
busy <= '1';
end if;
end if;
end process;
end architecture; | mit | efe23026b56cb7db4c36e189f83cb57d | 0.462878 | 3.072503 | false | false | false | false |
hamsternz/FPGA_DisplayPort | src/spartan6/transceiver.vhd | 1 | 80,451 | ----------------------------------------------------------------------------------
-- Module Name: transceiver_gtp_dual - Behavioral
--
-- Description: A wrapper around the Xilinx Spartan 6 GTP Dual transceiver
--
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
-- 0.2 | 2015-09-18 | Move bit reordering here from the 8b/10b encoder
-- 0.3 | 2015-09-30 | Created version for Spartan 6
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Transceiver is
generic( use_hw_8b10b_support : std_logic := '0');
Port ( mgmt_clk : in STD_LOGIC;
powerup_channel : in STD_LOGIC_VECTOR(3 downto 0);
debug : out std_logic_vector(7 downto 0);
preemp_0p0 : in STD_LOGIC;
preemp_3p5 : in STD_LOGIC;
preemp_6p0 : in STD_LOGIC;
swing_0p4 : in STD_LOGIC;
swing_0p6 : in STD_LOGIC;
swing_0p8 : in STD_LOGIC;
tx_running : out STD_LOGIC_VECTOR := (others => '0');
symbolclk : out STD_LOGIC;
in_symbols : in std_logic_vector(79 downto 0);
gtptxp : out std_logic_vector(3 downto 0);
gtptxn : out std_logic_vector(3 downto 0));
end transceiver;
architecture Behavioral of transceiver is
signal gclk135 : STD_LOGIC;
signal gclk135_unbuffered : STD_LOGIC;
signal clkfb_for_135 : STD_LOGIC;
signal powerup_pll : std_logic_vector( 3 downto 0) := "1111";
signal powerup_refclk : std_logic_vector( 3 downto 0) := "1000";
signal txdata_for_tx0 : std_logic_vector(31 downto 0) := (others => '0');
signal txchardispmode0 : std_logic_vector( 3 downto 0) := (others => '0');
signal txchardispval0 : std_logic_vector( 3 downto 0) := (others => '0'); -- Note Forces negative disparity.
signal is_kchar_tx0 : std_logic_vector( 3 downto 0) := (others => '0');
signal txdata_for_tx1 : std_logic_vector(31 downto 0) := (others => '0');
signal txchardispmode1 : std_logic_vector( 3 downto 0) := (others => '0');
signal txchardispval1 : std_logic_vector( 3 downto 0) := (others => '0');
signal is_kchar_tx1 : std_logic_vector( 3 downto 0) := (others => '0');
signal txdata_for_tx2 : std_logic_vector(31 downto 0) := (others => '0');
signal txchardispmode2 : std_logic_vector( 3 downto 0) := (others => '0');
signal txchardispval2 : std_logic_vector( 3 downto 0) := (others => '0');
signal is_kchar_tx2 : std_logic_vector( 3 downto 0) := (others => '0');
signal txdata_for_tx3 : std_logic_vector(31 downto 0) := (others => '0');
signal txchardispmode3 : std_logic_vector( 3 downto 0) := (others => '0');
signal txchardispval3 : std_logic_vector( 3 downto 0) := (others => '0');
signal is_kchar_tx3 : std_logic_vector( 3 downto 0) := (others => '0');
component gtpa1_dual_reset_controller is
port ( clk : in STD_LOGIC;
powerup_refclk : in std_logic;
powerup_pll : in std_logic;
required_pll_lock : in std_logic; -- PLL lock for the one that is driving this GTP
usrclklock : in STD_LOGIC; -- PLL lock for the USRCLK/USRCLK2 clock signals
powerup_channel : in STD_LOGIC;
tx_running : out STD_LOGIC;
-- link to GTP signals
refclken : out STD_LOGIC;
pllpowerdown : out STD_LOGIC;
plllock : in STD_LOGIC;
plllocken : out STD_LOGIC;
gtpreset : out STD_LOGIC;
txreset : out STD_LOGIC;
txpowerdown : out STD_LOGIC_VECTOR(1 downto 0);
gtpresetdone : in STD_LOGIC);
end component;
signal refclk : std_logic_vector(3 downto 0);
signal pllpowerdown : std_logic_vector(3 downto 0);
signal plllock : std_logic_vector(3 downto 0);
signal plllocken : std_logic_vector(3 downto 0);
signal gtpreset : std_logic_vector(3 downto 0);
signal txpowerdown : std_logic_vector(7 downto 0);
signal txreset : std_logic_vector(3 downto 0);
signal txresetdone : std_logic_vector(3 downto 0);
signal gtpresetdone : std_logic_vector(3 downto 0);
signal pll_in_use : std_logic_vector(3 downto 0);
signal gtpclkout : std_logic_vector(7 downto 0);
signal preemp_level : std_logic_vector(2 downto 0);
signal swing_level : std_logic_vector(3 downto 0);
signal txoutclk : STD_LOGIC_vector(gtptxp'length-1 downto 0);
signal txusrclk_u : STD_LOGIC;
signal txusrclk_buffered : STD_LOGIC;
signal txusrclk2_u : STD_LOGIC;
signal txusrclk2_buffered : STD_LOGIC;
signal gtpclkout_buffered : STD_LOGIC;
signal gtpclkout_divided : STD_LOGIC;
signal dcm_reset_sr : STD_LOGIC_vector(3 downto 0);
signal out_ref_clk : std_logic_vector(3 downto 0);
signal testlock0 : std_logic;
signal testlock1 : std_logic;
signal usrclklock : std_logic;
begin
pll_gen135: PLL_BASE generic map (
BANDWIDTH => "HIGH",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT => 54,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 8,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 10.0,
REF_JITTER => 0.010)
port map (
CLKFBOUT => clkfb_for_135,
CLKOUT0 => gclk135_unbuffered,
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
-- Input clock control
CLKFBIN => clkfb_for_135,
CLKIN => mgmt_clk);
gclk135_buf : BUFG
port map (
O => gclk135,
I => gclk135_unbuffered
);
pll_in_use <= (0=>'1', others => '1');
symbolclk <= txusrclk2_buffered;
preemp_level <= "110" when preemp_6p0 = '1' else -- +6.0 db from table 3-30 in UG476
"100" when preemp_3p5 = '1' else -- +3.5 db
"000"; -- +0.0 db
swing_level <= "0110" when swing_0p8 = '1' else -- 0.762 V (should be 0.8)
"0100" when swing_0p6 = '1' else -- 0.578 V (should be 0.6)
"0011"; -- 0.487 V + plus a bit more (should be 0.4)
i_bufg_txusrclk: BUFG PORT MAP (
i => txusrclk_u,
o => txusrclk_buffered
);
i_bufg_txusrclk2: BUFG PORT MAP (
i => txusrclk2_u,
o => txusrclk2_buffered
);
i_bufg_io2: BUFIO2 GENERIC MAP (
DIVIDE => 1
) PORT MAP (
i => gtpclkout(0),
ioclk => open,
divclk => gtpclkout_buffered,
serdesstrobe => open
);
debug(0) <= plllock(0);
debug(1) <= plllock(1);
debug(2) <= plllock(2);
debug(3) <= plllock(3);
debug(4) <= '1';
debug(5) <= '1';
debug(6) <= '1';
debug(7) <= '1';
process(mgmt_clk, plllock(0))
-- The DCM reset must be asserted for at least 3 cycles after
-- the GTP PLL gets lock
begin
if plllock(0) = '0' then
dcm_reset_sr <= (others => '1');
elsif rising_edge(mgmt_clk) then
dcm_reset_sr <= '0' & dcm_reset_sr(dcm_reset_sr'high downto 1);
end if;
end process;
DCM_SP_inst : DCM_SP
generic map (
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 4,
CLKFX_MULTIPLY => 2,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 3.7,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DSS_MODE => "NONE",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => X"c080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE
)
port map (
CLK0 => txusrclk_u,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLK90 => open,
CLKDV => txusrclk2_u,
CLKFX => open,
CLKFX180 => open,
LOCKED => usrclklock,
PSDONE => open,
STATUS => open,
CLKFB => txusrclk_u,
CLKIN => gtpclkout_buffered,
DSSEN => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => dcm_reset_sr(0)
);
Inst_gtpa1_dual_reset_controller0: gtpa1_dual_reset_controller PORT MAP(
clk => mgmt_clk,
powerup_pll => powerup_pll(0),
powerup_refclk => powerup_refclk(0),
powerup_channel => powerup_channel(0),
tx_running => tx_running(0),
pllpowerdown => pllpowerdown(0),
plllock => plllock(0),
plllocken => plllocken(0),
required_pll_lock => plllock(0),
usrclklock => usrclklock,
gtpreset => gtpreset(0),
txreset => txreset(0),
txpowerdown => txpowerdown(0*2+1 downto 0*2),
gtpresetdone => gtpresetdone(0)
);
Inst_gtpa1_dual_reset_controller1: gtpa1_dual_reset_controller PORT MAP(
clk => mgmt_clk,
powerup_pll => powerup_pll(1),
powerup_refclk => powerup_refclk(1),
powerup_channel => powerup_channel(1),
tx_running => tx_running(1),
pllpowerdown => pllpowerdown(1),
plllock => plllock(1),
plllocken => plllocken(1),
required_pll_lock => plllock(0), -- Clocked from PLL0 in the first tile
usrclklock => usrclklock,
gtpreset => gtpreset(1),
txreset => txreset(1),
txpowerdown => txpowerdown(1*2+1 downto 1*2),
gtpresetdone => gtpresetdone(1)
);
Inst_gtpa1_dual_reset_controller2: gtpa1_dual_reset_controller PORT MAP(
clk => mgmt_clk,
powerup_pll => powerup_pll(2),
powerup_refclk => powerup_refclk(2),
powerup_channel => powerup_channel(2),
tx_running => tx_running(2),
pllpowerdown => pllpowerdown(2),
plllock => plllock(2),
plllocken => plllocken(2),
required_pll_lock => plllock(2),
usrclklock => usrclklock,
gtpreset => gtpreset(2),
txreset => txreset(2),
txpowerdown => txpowerdown(2*2+1 downto 2*2),
gtpresetdone => gtpresetdone(2)
);
Inst_gtpa1_dual_reset_controller3: gtpa1_dual_reset_controller PORT MAP(
clk => mgmt_clk,
powerup_pll => powerup_pll(3),
powerup_refclk => powerup_refclk(3),
powerup_channel => powerup_channel(3),
tx_running => tx_running(3),
pllpowerdown => pllpowerdown(3),
plllock => plllock(3),
plllocken => plllocken(3),
required_pll_lock => plllock(2), -- Clocked from PLL0 in the second tile
usrclklock => usrclklock,
gtpreset => gtpreset(3),
txreset => txreset(3),
txpowerdown => txpowerdown(3*2+1 downto 3*2),
gtpresetdone => gtpresetdone(3)
);
g_soft_8b10b: if use_hw_8b10b_support = '0' generate
---------------------------------------------------
-- Data mapping when the input is raw binary values
---------------------------------------------------
-- First channel
---------------------------------------------------
txdata_for_tx0( 0) <= in_symbols( 9);
txdata_for_tx0( 1) <= in_symbols( 8);
txdata_for_tx0( 2) <= in_symbols( 7);
txdata_for_tx0( 3) <= in_symbols( 6);
txdata_for_tx0( 4) <= in_symbols( 5);
txdata_for_tx0( 5) <= in_symbols( 4);
txdata_for_tx0( 6) <= in_symbols( 3);
txdata_for_tx0( 7) <= in_symbols( 2);
txchardispval0 (0) <= in_symbols( 1);
txchardispmode0(0) <= in_symbols( 0);
txdata_for_tx0( 8) <= in_symbols(19);
txdata_for_tx0( 9) <= in_symbols(18);
txdata_for_tx0(10) <= in_symbols(17);
txdata_for_tx0(11) <= in_symbols(16);
txdata_for_tx0(12) <= in_symbols(15);
txdata_for_tx0(13) <= in_symbols(14);
txdata_for_tx0(14) <= in_symbols(13);
txdata_for_tx0(15) <= in_symbols(12);
txchardispval0 (1) <= in_symbols(11);
txchardispmode0(1) <= in_symbols(10);
---------------------------------------------------
-- Second channel
---------------------------------------------------
txdata_for_tx1( 0) <= in_symbols(29);
txdata_for_tx1( 1) <= in_symbols(28);
txdata_for_tx1( 2) <= in_symbols(27);
txdata_for_tx1( 3) <= in_symbols(26);
txdata_for_tx1( 4) <= in_symbols(25);
txdata_for_tx1( 5) <= in_symbols(24);
txdata_for_tx1( 6) <= in_symbols(23);
txdata_for_tx1( 7) <= in_symbols(22);
txchardispval1 (0) <= in_symbols(21);
txchardispmode1(0) <= in_symbols(20);
txdata_for_tx1( 8) <= in_symbols(39);
txdata_for_tx1( 9) <= in_symbols(38);
txdata_for_tx1(10) <= in_symbols(37);
txdata_for_tx1(11) <= in_symbols(36);
txdata_for_tx1(12) <= in_symbols(35);
txdata_for_tx1(13) <= in_symbols(34);
txdata_for_tx1(14) <= in_symbols(33);
txdata_for_tx1(15) <= in_symbols(32);
txchardispval1 (1) <= in_symbols(31);
txchardispmode1(1) <= in_symbols(30);
---------------------------------------------------
-- Third channel
---------------------------------------------------
txdata_for_tx2( 0) <= in_symbols(49);
txdata_for_tx2( 1) <= in_symbols(48);
txdata_for_tx2( 2) <= in_symbols(47);
txdata_for_tx2( 3) <= in_symbols(46);
txdata_for_tx2( 4) <= in_symbols(45);
txdata_for_tx2( 5) <= in_symbols(44);
txdata_for_tx2( 6) <= in_symbols(43);
txdata_for_tx2( 7) <= in_symbols(42);
txchardispval2 (0) <= in_symbols(41);
txchardispmode2(0) <= in_symbols(40);
txdata_for_tx2( 8) <= in_symbols(59);
txdata_for_tx2( 9) <= in_symbols(58);
txdata_for_tx2(10) <= in_symbols(57);
txdata_for_tx2(11) <= in_symbols(56);
txdata_for_tx2(12) <= in_symbols(55);
txdata_for_tx2(13) <= in_symbols(54);
txdata_for_tx2(14) <= in_symbols(53);
txdata_for_tx2(15) <= in_symbols(52);
txchardispval2 (1) <= in_symbols(51);
txchardispmode2(1) <= in_symbols(50);
-------------------------------------
-- Fourth channel
-------------------------------------
txdata_for_tx3( 0) <= in_symbols(69);
txdata_for_tx3( 1) <= in_symbols(68);
txdata_for_tx3( 2) <= in_symbols(67);
txdata_for_tx3( 3) <= in_symbols(66);
txdata_for_tx3( 4) <= in_symbols(65);
txdata_for_tx3( 5) <= in_symbols(64);
txdata_for_tx3( 6) <= in_symbols(63);
txdata_for_tx3( 7) <= in_symbols(62);
txchardispval3 (0) <= in_symbols(61);
txchardispmode3(0) <= in_symbols(60);
txdata_for_tx3( 8) <= in_symbols(79);
txdata_for_tx3( 9) <= in_symbols(78);
txdata_for_tx3(10) <= in_symbols(77);
txdata_for_tx3(11) <= in_symbols(76);
txdata_for_tx3(12) <= in_symbols(75);
txdata_for_tx3(13) <= in_symbols(74);
txdata_for_tx3(14) <= in_symbols(73);
txdata_for_tx3(15) <= in_symbols(72);
txchardispval3 (1) <= in_symbols(71);
txchardispmode3(1) <= in_symbols(70);
end generate;
g_hard_8b10b: if use_hw_8b10b_support = '1' generate
---------------------------------------------------
-- Data mapping when the input is raw binary values
---------------------------------------------------
-- First channel
txdata_for_tx0( 7 downto 0) <= in_symbols( 7 downto 0);
is_kchar_tx0(0) <= in_symbols( 8);
txchardispval0(0) <= in_symbols( 9);
txchardispmode0(0) <= '0';
txdata_for_tx0(15 downto 8) <= in_symbols(17 downto 10);
is_kchar_tx0(1) <= in_symbols(18);
txchardispval0(1) <= in_symbols(19);
txchardispmode0(1) <= '0';
-- Second channel
txdata_for_tx1( 7 downto 0) <= in_symbols(27 downto 20);
is_kchar_tx1(0) <= in_symbols(28);
txchardispmode1(0) <= in_symbols(29); --force neg (txchardispval is 0)
txdata_for_tx1(15 downto 8) <= in_symbols(37 downto 30);
is_kchar_tx1(1) <= in_symbols(38);
txchardispmode1(1) <= in_symbols(39); --force neg (txchardispval is 0)
-- Third channel
txdata_for_tx2( 7 downto 0) <= in_symbols(47 downto 40);
is_kchar_tx2(0) <= in_symbols(48);
txchardispmode2(0) <= in_symbols(49); --force neg (txchardispval is 0)
txdata_for_tx2(15 downto 8) <= in_symbols(57 downto 50);
is_kchar_tx2(1) <= in_symbols(58);
txchardispmode2(1) <= in_symbols(59); --force neg (txchardispval is 0)
-- Fourth channel
txdata_for_tx3( 7 downto 0) <= in_symbols(67 downto 60);
is_kchar_tx3(0) <= in_symbols(68);
txchardispmode3(0) <= in_symbols(69); --force neg (txchardispval is 0)
txdata_for_tx3(15 downto 8) <= in_symbols(77 downto 70);
is_kchar_tx3(1) <= in_symbols(78);
txchardispmode3(1) <= in_symbols(79); --force neg (txchardispval is 0)
end generate;
----------------------------- GTPA1_DUAL Instance X0Y0 --------------------------
-- This is the driver for Display port channels 3 and 2.
--
-- The reference clock goes into the DisplayPort RX tile, so
-- it needs to be configured to pass out the 135MHz reference
-- out the to the other tile's CLKINEAST0/1 ports
--
--
-------------------------------------------------------------
gtpa1_dual_X0Y0:GTPA1_DUAL
generic map
(
SIM_REFCLK0_SOURCE => ("100"), -- CLK10
SIM_REFCLK1_SOURCE => ("100"), -- CLK11
PLL_SOURCE_0 => ("PLL0"), -- Source from PLL 0
PLL_SOURCE_1 => ("PLL1"), -- Source from PLL 0
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
SIM_VERSION => ("2.0"),
SIM_GTPRESET_SPEEDUP => (1),
CLK25_DIVIDER_0 => (5),
CLK25_DIVIDER_1 => (5),
PLL_DIVSEL_FB_0 => (2),
PLL_DIVSEL_FB_1 => (2),
PLL_DIVSEL_REF_0 => (1),
PLL_DIVSEL_REF_1 => (1),
CLK_OUT_GTP_SEL_0 => ("TXOUTCLK0"),
CLK_OUT_GTP_SEL_1 => ("TXOUTCLK1"),
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (1),
PLL_SATA_0 => (FALSE),
PLL_TXDIVSEL_OUT_0 => (1),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (1),
PLL_SATA_1 => (FALSE),
PLL_TXDIVSEL_OUT_1 => (1),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"00000a000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
TX_TDCC_CFG_0 => ("11"),
TX_TDCC_CFG_1 => ("11"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (TRUE),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce089"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (FALSE),
RCV_TERM_VTTRX_0 => (TRUE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (TRUE),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce089"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (FALSE),
RCV_TERM_VTTRX_1 => (TRUE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (TRUE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (TRUE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (TRUE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (TRUE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (5),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0100000000"),
CLK_COR_SEQ_1_3_0 => ("0100000000"),
CLK_COR_SEQ_1_4_0 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0100000000"),
CLK_COR_SEQ_2_3_0 => ("0100000000"),
CLK_COR_SEQ_2_4_0 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (FALSE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (5),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0100000000"),
CLK_COR_SEQ_1_3_1 => ("0100000000"),
CLK_COR_SEQ_1_4_1 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0100000000"),
CLK_COR_SEQ_2_3_1 => ("0100000000"),
CLK_COR_SEQ_2_4_1 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (FALSE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0110111100"),
CHAN_BOND_SEQ_1_2_0 => ("0011001011"),
CHAN_BOND_SEQ_1_3_0 => ("0110111100"),
CHAN_BOND_SEQ_1_4_0 => ("0011001011"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (FALSE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0110111100"),
CHAN_BOND_SEQ_1_2_1 => ("0011001011"),
CHAN_BOND_SEQ_1_3_1 => ("0110111100"),
CHAN_BOND_SEQ_1_4_1 => ("0011001011"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (FALSE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (FALSE),
RX_EN_IDLE_HOLD_CDR_0 => (FALSE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (FALSE),
RX_EN_IDLE_HOLD_CDR_1 => (FALSE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (10),
SATA_MAX_INIT_0 => (29),
SATA_MAX_WAKE_0 => (10),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (16),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (10),
SATA_MAX_INIT_1 => (29),
SATA_MAX_WAKE_1 => (10),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (16),
SATA_MIN_WAKE_1 => (5)
)
port map
(
TXPOWERDOWN0 => txpowerdown(5 downto 4),
TXPOWERDOWN1 => txpowerdown(7 downto 6),
CLK00 => '0',
CLK01 => '0',
CLK10 => '0',
CLK11 => '0',
GCLK00 => gclk135,
GCLK01 => gclk135,
GCLK10 => '0',
GCLK11 => '0',
GTPRESET0 => gtpreset(2),
GTPRESET1 => gtpreset(3),
PLLLKDET0 => plllock(2),
PLLLKDET1 => plllock(3),
PLLLKDETEN0 => plllocken(2),
PLLLKDETEN1 => plllocken(3),
PLLPOWERDOWN0 => pllpowerdown(2),
PLLPOWERDOWN1 => pllpowerdown(3),
REFCLKPLL0 => out_ref_clk(2),
REFCLKPLL1 => out_ref_clk(3),
REFSELDYPLL0 => "001", -- use GCLK135
REFSELDYPLL1 => "001", -- use GCLK135
RESETDONE0 => gtpresetdone(2),
RESETDONE1 => gtpresetdone(3),
GTPCLKOUT0 => gtpclkout(5 downto 4),
GTPCLKOUT1 => gtpclkout(7 downto 6),
TXCHARDISPMODE0 => TXCHARDISPMODE2,
TXCHARDISPMODE1 => TXCHARDISPMODE3,
TXCHARDISPVAL0 => TXCHARDISPVAL2,
TXCHARDISPVAL1 => TXCHARDISPVAL3,
TXDATA0 => txdata_for_tx2,
TXDATA1 => txdata_for_tx3,
TXOUTCLK0 => txoutclk(2),
TXOUTCLK1 => txoutclk(3),
TXRESET0 => txreset(2),
TXRESET1 => txreset(3),
TXUSRCLK0 => txusrclk_buffered,
TXUSRCLK1 => txusrclk_buffered,
TXUSRCLK20 => txusrclk2_buffered,
TXUSRCLK21 => txusrclk2_buffered,
TXDIFFCTRL0 => swing_level,
TXDIFFCTRL1 => swing_level,
TXP0 => gtptxp(2),
TXN0 => gtptxn(2),
TXP1 => gtptxp(3),
TXN1 => gtptxn(3),
TXPREEMPHASIS0 => preemp_level,
TXPREEMPHASIS1 => preemp_level,
-- Only so resetdone works..
RXUSRCLK0 => txusrclk_buffered,
RXUSRCLK1 => txusrclk_buffered,
RXUSRCLK20 => txusrclk2_buffered,
RXUSRCLK21 => txusrclk2_buffered,
TXCHARISK0 => is_kchar_tx2,
TXCHARISK1 => is_kchar_tx3,
TXENC8B10BUSE0 => use_hw_8b10b_support,
TXENC8B10BUSE1 => use_hw_8b10b_support,
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => (others => '0'),
LOOPBACK1 => (others => '0'),
RXPOWERDOWN0 => "11", --- Maybe I should tie these low to allow the reset to finish?
RXPOWERDOWN1 => "11",
--------------------------------- PLL Ports --------------------------------
CLKINEAST0 => '0',
CLKINEAST1 => '0',
CLKINWEST0 => '0',
CLKINWEST1 => '0',
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => '1',
INTDATAWIDTH1 => '1',
PLLCLK00 => '0',
PLLCLK01 => '0',
PLLCLK10 => '0',
PLLCLK11 => '0',
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => '1', -- Not used - should power down
REFCLKPWRDNB1 => '1', -- Used- must be powered up
TSTCLK0 => '0',
TSTCLK1 => '0',
TSTIN0 => (others => '0'),
TSTIN1 => (others => '0'),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => open,
RXCHARISK1 => open,
RXDEC8B10BUSE0 => '1',
RXDEC8B10BUSE1 => '1',
RXDISPERR0 => open,
RXDISPERR1 => open,
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => '0',
USRCODEERR1 => '0',
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => (others => '0'),
RXCHBONDMASTER0 => '0',
RXCHBONDMASTER1 => '0',
RXCHBONDO => open,
RXCHBONDSLAVE0 => '0',
RXCHBONDSLAVE1 => '0',
RXENCHANSYNC0 => '0',
RXENCHANSYNC1 => '0',
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => '1',
RXCOMMADETUSE1 => '1',
RXENMCOMMAALIGN0 => '0',
RXENMCOMMAALIGN1 => '0',
RXENPCOMMAALIGN0 => '0',
RXENPCOMMAALIGN1 => '0',
RXSLIDE0 => '0',
RXSLIDE1 => '0',
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => '1',
PRBSCNTRESET1 => '1',
RXENPRBSTST0 => "000",
RXENPRBSTST1 => "000",
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => open,
RXDATA1 => open,
RXDATAWIDTH0 => "01",
RXDATAWIDTH1 => "01",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => '0',
RXRESET1 => '0',
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => '0',
GATERXELECIDLE1 => '0',
IGNORESIGDET0 => '1',
IGNORESIGDET1 => '1',
RCALINEAST => (others =>'0'),
RCALINWEST => (others =>'0'),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => '0',
RXCDRRESET1 => '0',
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXN0 => '0',
RXN1 => '0',
RXP0 => '1',
RXP1 => '1',
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => '0',
RXBUFRESET1 => '0',
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => '0',
RXENPMAPHASEALIGN1 => '0',
RXPMASETPHASE0 => '0',
RXPMASETPHASE1 => '0',
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => '0',
RXPOLARITY1 => '0',
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => (others=>'0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DRDY => open,
DRPDO => open,
DWE => '0',
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => "0000",
TXBYPASS8B10B1 => "0000",
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => '0',
TXENPMAPHASEALIGN1 => '0',
TXPMASETPHASE0 => '0',
TXPMASETPHASE1 => '0',
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATAWIDTH0 => "01",
TXDATAWIDTH1 => "01",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXINHIBIT0 => '0',
TXINHIBIT1 => '0',
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => "000",
TXENPRBSTST1 => "000",
TXPRBSFORCEERR0 => '0',
TXPRBSFORCEERR1 => '0',
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => '0',
TXPOLARITY1 => '0',
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => '0',
TXDETECTRX1 => '0',
TXELECIDLE0 => '0',
TXELECIDLE1 => '0',
TXPDOWNASYNCH0 => '0',
TXPDOWNASYNCH1 => '0',
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => '0',
TXCOMSTART1 => '0',
TXCOMTYPE0 => '0',
TXCOMTYPE1 => '0'
);
----------------------------- GTPA1_DUAL Instance X1Y0 --------------------------
-- This is the driver for Display port channels 1 and 0.
-- It is clocked from X0Y0 on gclk00 over the clkinwest1 ports
----------------------------------------------------------------------------------
gtpa1_dual_X1Y0:GTPA1_DUAL
generic map
(
SIM_REFCLK0_SOURCE => ("111"),
SIM_REFCLK1_SOURCE => ("111"),
PLL_SOURCE_0 => ("PLL0"), -- Source from PLL 0
PLL_SOURCE_1 => ("PLL1"), -- Source from PLL 0
--_______________________ Simulation-Only Attributes ___________________
SIM_RECEIVER_DETECT_PASS => (TRUE),
SIM_TX_ELEC_IDLE_LEVEL => ("Z"),
SIM_VERSION => ("2.0"),
SIM_GTPRESET_SPEEDUP => (1),
CLK25_DIVIDER_0 => (5),
CLK25_DIVIDER_1 => (5),
PLL_DIVSEL_FB_0 => (2),
PLL_DIVSEL_FB_1 => (2),
PLL_DIVSEL_REF_0 => (1),
PLL_DIVSEL_REF_1 => (1),
CLK_OUT_GTP_SEL_0 => ("TXOUTCLK0"),
CLK_OUT_GTP_SEL_1 => ("TXOUTCLK1"),
--PLL Attributes
CLKINDC_B_0 => (TRUE),
CLKRCV_TRST_0 => (TRUE),
OOB_CLK_DIVIDER_0 => (4),
PLL_COM_CFG_0 => (x"21680a"),
PLL_CP_CFG_0 => (x"00"),
PLL_RXDIVSEL_OUT_0 => (1),
PLL_SATA_0 => (FALSE),
PLL_TXDIVSEL_OUT_0 => (1),
PLLLKDET_CFG_0 => ("111"),
--
CLKINDC_B_1 => (TRUE),
CLKRCV_TRST_1 => (TRUE),
OOB_CLK_DIVIDER_1 => (4),
PLL_COM_CFG_1 => (x"21680a"),
PLL_CP_CFG_1 => (x"00"),
PLL_RXDIVSEL_OUT_1 => (1),
PLL_SATA_1 => (FALSE),
PLL_TXDIVSEL_OUT_1 => (1),
PLLLKDET_CFG_1 => ("111"),
PMA_COM_CFG_EAST => (x"000008000"),
PMA_COM_CFG_WEST => (x"00000a000"),
TST_ATTR_0 => (x"00000000"),
TST_ATTR_1 => (x"00000000"),
--TX Interface Attributes
TX_TDCC_CFG_0 => ("11"),
TX_TDCC_CFG_1 => ("11"),
--TX Buffer and Phase Alignment Attributes
PMA_TX_CFG_0 => (x"00082"),
TX_BUFFER_USE_0 => (TRUE),
TX_XCLK_SEL_0 => ("TXOUT"),
TXRX_INVERT_0 => ("111"),
PMA_TX_CFG_1 => (x"00082"),
TX_BUFFER_USE_1 => (TRUE),
TX_XCLK_SEL_1 => ("TXOUT"),
TXRX_INVERT_1 => ("111"),
--TX Driver and OOB signalling Attributes
CM_TRIM_0 => ("00"),
TX_IDLE_DELAY_0 => ("011"),
CM_TRIM_1 => ("00"),
TX_IDLE_DELAY_1 => ("011"),
--TX PIPE/SATA Attributes
COM_BURST_VAL_0 => ("1111"),
COM_BURST_VAL_1 => ("1111"),
--RX Driver,OOB signalling,Coupling and Eq,CDR Attributes
AC_CAP_DIS_0 => (TRUE),
OOBDETECT_THRESHOLD_0 => ("110"),
PMA_CDR_SCAN_0 => (x"6404040"),
PMA_RX_CFG_0 => (x"05ce089"),
PMA_RXSYNC_CFG_0 => (x"00"),
RCV_TERM_GND_0 => (FALSE),
RCV_TERM_VTTRX_0 => (TRUE),
RXEQ_CFG_0 => ("01111011"),
TERMINATION_CTRL_0 => ("10100"),
TERMINATION_OVRD_0 => (FALSE),
TX_DETECT_RX_CFG_0 => (x"1832"),
AC_CAP_DIS_1 => (TRUE),
OOBDETECT_THRESHOLD_1 => ("110"),
PMA_CDR_SCAN_1 => (x"6404040"),
PMA_RX_CFG_1 => (x"05ce089"),
PMA_RXSYNC_CFG_1 => (x"00"),
RCV_TERM_GND_1 => (FALSE),
RCV_TERM_VTTRX_1 => (TRUE),
RXEQ_CFG_1 => ("01111011"),
TERMINATION_CTRL_1 => ("10100"),
TERMINATION_OVRD_1 => (FALSE),
TX_DETECT_RX_CFG_1 => (x"1832"),
--PRBS Detection Attributes
RXPRBSERR_LOOPBACK_0 => ('0'),
RXPRBSERR_LOOPBACK_1 => ('0'),
--Comma Detection and Alignment Attributes
ALIGN_COMMA_WORD_0 => (1),
COMMA_10B_ENABLE_0 => ("1111111111"),
DEC_MCOMMA_DETECT_0 => (TRUE),
DEC_PCOMMA_DETECT_0 => (TRUE),
DEC_VALID_COMMA_ONLY_0 => (TRUE),
MCOMMA_10B_VALUE_0 => ("1010000011"),
MCOMMA_DETECT_0 => (TRUE),
PCOMMA_10B_VALUE_0 => ("0101111100"),
PCOMMA_DETECT_0 => (TRUE),
RX_SLIDE_MODE_0 => ("PCS"),
ALIGN_COMMA_WORD_1 => (1),
COMMA_10B_ENABLE_1 => ("1111111111"),
DEC_MCOMMA_DETECT_1 => (TRUE),
DEC_PCOMMA_DETECT_1 => (TRUE),
DEC_VALID_COMMA_ONLY_1 => (TRUE),
MCOMMA_10B_VALUE_1 => ("1010000011"),
MCOMMA_DETECT_1 => (TRUE),
PCOMMA_10B_VALUE_1 => ("0101111100"),
PCOMMA_DETECT_1 => (TRUE),
RX_SLIDE_MODE_1 => ("PCS"),
--RX Loss-of-sync State Machine Attributes
RX_LOS_INVALID_INCR_0 => (8),
RX_LOS_THRESHOLD_0 => (128),
RX_LOSS_OF_SYNC_FSM_0 => (TRUE),
RX_LOS_INVALID_INCR_1 => (8),
RX_LOS_THRESHOLD_1 => (128),
RX_LOSS_OF_SYNC_FSM_1 => (TRUE),
--RX Elastic Buffer and Phase alignment Attributes
RX_BUFFER_USE_0 => (TRUE),
RX_EN_IDLE_RESET_BUF_0 => (TRUE),
RX_IDLE_HI_CNT_0 => ("1000"),
RX_IDLE_LO_CNT_0 => ("0000"),
RX_XCLK_SEL_0 => ("RXREC"),
RX_BUFFER_USE_1 => (TRUE),
RX_EN_IDLE_RESET_BUF_1 => (TRUE),
RX_IDLE_HI_CNT_1 => ("1000"),
RX_IDLE_LO_CNT_1 => ("0000"),
RX_XCLK_SEL_1 => ("RXREC"),
--Clock Correction Attributes
CLK_COR_ADJ_LEN_0 => (1),
CLK_COR_DET_LEN_0 => (1),
CLK_COR_INSERT_IDLE_FLAG_0 => (FALSE),
CLK_COR_KEEP_IDLE_0 => (FALSE),
CLK_COR_MAX_LAT_0 => (18),
CLK_COR_MIN_LAT_0 => (16),
CLK_COR_PRECEDENCE_0 => (TRUE),
CLK_COR_REPEAT_WAIT_0 => (5),
CLK_COR_SEQ_1_1_0 => ("0100000000"),
CLK_COR_SEQ_1_2_0 => ("0100000000"),
CLK_COR_SEQ_1_3_0 => ("0100000000"),
CLK_COR_SEQ_1_4_0 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_1_0 => ("0100000000"),
CLK_COR_SEQ_2_2_0 => ("0100000000"),
CLK_COR_SEQ_2_3_0 => ("0100000000"),
CLK_COR_SEQ_2_4_0 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_0 => ("0000"),
CLK_COR_SEQ_2_USE_0 => (FALSE),
CLK_CORRECT_USE_0 => (FALSE),
RX_DECODE_SEQ_MATCH_0 => (TRUE),
CLK_COR_ADJ_LEN_1 => (1),
CLK_COR_DET_LEN_1 => (1),
CLK_COR_INSERT_IDLE_FLAG_1 => (FALSE),
CLK_COR_KEEP_IDLE_1 => (FALSE),
CLK_COR_MAX_LAT_1 => (18),
CLK_COR_MIN_LAT_1 => (16),
CLK_COR_PRECEDENCE_1 => (TRUE),
CLK_COR_REPEAT_WAIT_1 => (5),
CLK_COR_SEQ_1_1_1 => ("0100000000"),
CLK_COR_SEQ_1_2_1 => ("0100000000"),
CLK_COR_SEQ_1_3_1 => ("0100000000"),
CLK_COR_SEQ_1_4_1 => ("0100000000"),
CLK_COR_SEQ_1_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_1_1 => ("0100000000"),
CLK_COR_SEQ_2_2_1 => ("0100000000"),
CLK_COR_SEQ_2_3_1 => ("0100000000"),
CLK_COR_SEQ_2_4_1 => ("0100000000"),
CLK_COR_SEQ_2_ENABLE_1 => ("0000"),
CLK_COR_SEQ_2_USE_1 => (FALSE),
CLK_CORRECT_USE_1 => (FALSE),
RX_DECODE_SEQ_MATCH_1 => (TRUE),
--Channel Bonding Attributes
CHAN_BOND_1_MAX_SKEW_0 => (1),
CHAN_BOND_2_MAX_SKEW_0 => (1),
CHAN_BOND_KEEP_ALIGN_0 => (FALSE),
CHAN_BOND_SEQ_1_1_0 => ("0110111100"),
CHAN_BOND_SEQ_1_2_0 => ("0011001011"),
CHAN_BOND_SEQ_1_3_0 => ("0110111100"),
CHAN_BOND_SEQ_1_4_0 => ("0011001011"),
CHAN_BOND_SEQ_1_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_1_0 => ("0000000000"),
CHAN_BOND_SEQ_2_2_0 => ("0000000000"),
CHAN_BOND_SEQ_2_3_0 => ("0000000000"),
CHAN_BOND_SEQ_2_4_0 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_0 => ("0000"),
CHAN_BOND_SEQ_2_USE_0 => (FALSE),
CHAN_BOND_SEQ_LEN_0 => (1),
RX_EN_MODE_RESET_BUF_0 => (FALSE),
CHAN_BOND_1_MAX_SKEW_1 => (1),
CHAN_BOND_2_MAX_SKEW_1 => (1),
CHAN_BOND_KEEP_ALIGN_1 => (FALSE),
CHAN_BOND_SEQ_1_1_1 => ("0110111100"),
CHAN_BOND_SEQ_1_2_1 => ("0011001011"),
CHAN_BOND_SEQ_1_3_1 => ("0110111100"),
CHAN_BOND_SEQ_1_4_1 => ("0011001011"),
CHAN_BOND_SEQ_1_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_1_1 => ("0000000000"),
CHAN_BOND_SEQ_2_2_1 => ("0000000000"),
CHAN_BOND_SEQ_2_3_1 => ("0000000000"),
CHAN_BOND_SEQ_2_4_1 => ("0000000000"),
CHAN_BOND_SEQ_2_ENABLE_1 => ("0000"),
CHAN_BOND_SEQ_2_USE_1 => (FALSE),
CHAN_BOND_SEQ_LEN_1 => (1),
RX_EN_MODE_RESET_BUF_1 => (FALSE),
--RX PCI Express Attributes
CB2_INH_CC_PERIOD_0 => (8),
CDR_PH_ADJ_TIME_0 => ("01010"),
PCI_EXPRESS_MODE_0 => (FALSE),
RX_EN_IDLE_HOLD_CDR_0 => (FALSE),
RX_EN_IDLE_RESET_FR_0 => (TRUE),
RX_EN_IDLE_RESET_PH_0 => (TRUE),
RX_STATUS_FMT_0 => ("PCIE"),
TRANS_TIME_FROM_P2_0 => (x"03c"),
TRANS_TIME_NON_P2_0 => (x"19"),
TRANS_TIME_TO_P2_0 => (x"064"),
CB2_INH_CC_PERIOD_1 => (8),
CDR_PH_ADJ_TIME_1 => ("01010"),
PCI_EXPRESS_MODE_1 => (FALSE),
RX_EN_IDLE_HOLD_CDR_1 => (FALSE),
RX_EN_IDLE_RESET_FR_1 => (TRUE),
RX_EN_IDLE_RESET_PH_1 => (TRUE),
RX_STATUS_FMT_1 => ("PCIE"),
TRANS_TIME_FROM_P2_1 => (x"03c"),
TRANS_TIME_NON_P2_1 => (x"19"),
TRANS_TIME_TO_P2_1 => (x"064"),
--RX SATA Attributes
SATA_BURST_VAL_0 => ("100"),
SATA_IDLE_VAL_0 => ("100"),
SATA_MAX_BURST_0 => (10),
SATA_MAX_INIT_0 => (29),
SATA_MAX_WAKE_0 => (10),
SATA_MIN_BURST_0 => (5),
SATA_MIN_INIT_0 => (16),
SATA_MIN_WAKE_0 => (5),
SATA_BURST_VAL_1 => ("100"),
SATA_IDLE_VAL_1 => ("100"),
SATA_MAX_BURST_1 => (10),
SATA_MAX_INIT_1 => (29),
SATA_MAX_WAKE_1 => (10),
SATA_MIN_BURST_1 => (5),
SATA_MIN_INIT_1 => (16),
SATA_MIN_WAKE_1 => (5)
)
port map
(
TXPOWERDOWN0 => txpowerdown(1 downto 0),
TXPOWERDOWN1 => txpowerdown(3 downto 2),
CLK00 => '0',
CLK01 => '0',
CLK10 => '0',
CLK11 => '0',
GCLK00 => '0',
GCLK01 => '0',
GCLK10 => '0',
GCLK11 => '0',
CLKINEAST0 => '0',
CLKINEAST1 => '0',
CLKINWEST0 => out_ref_clk(3),
CLKINWEST1 => out_ref_clk(3),
GTPRESET0 => gtpreset(0),
GTPRESET1 => gtpreset(1),
PLLLKDET0 => plllock(0),
PLLLKDET1 => plllock(1),
PLLLKDETEN0 => plllocken(0),
PLLLKDETEN1 => plllocken(1),
PLLPOWERDOWN0 => pllpowerdown(0),
PLLPOWERDOWN1 => pllpowerdown(1),
REFSELDYPLL0 => "111", -- use West clock
REFSELDYPLL1 => "111", -- use West clock
RESETDONE0 => gtpresetdone(0),
RESETDONE1 => gtpresetdone(1),
GTPCLKOUT0 => gtpclkout(1 downto 0),
GTPCLKOUT1 => gtpclkout(3 downto 2),
TXCHARDISPMODE0 => TXCHARDISPMODE0,
TXCHARDISPMODE1 => TXCHARDISPMODE1,
TXCHARDISPVAL0 => TXCHARDISPVAL0,
TXCHARDISPVAL1 => TXCHARDISPVAL1,
TXDATA0 => txdata_for_tx0,
TXDATA1 => txdata_for_tx1,
TXOUTCLK0 => txoutclk(0),
TXOUTCLK1 => txoutclk(1),
TXRESET0 => txreset(0),
TXRESET1 => txreset(1),
TXUSRCLK0 => txusrclk_buffered,
TXUSRCLK1 => txusrclk_buffered,
TXUSRCLK20 => txusrclk2_buffered,
TXUSRCLK21 => txusrclk2_buffered,
TXDIFFCTRL0 => swing_level,
TXDIFFCTRL1 => swing_level,
TXP0 => gtptxp(0),
TXN0 => gtptxn(0),
TXP1 => gtptxp(1),
TXN1 => gtptxn(1),
TXPREEMPHASIS0 => preemp_level,
TXPREEMPHASIS1 => preemp_level,
-- Only so resetdone works..
RXUSRCLK0 => txusrclk_buffered,
RXUSRCLK1 => txusrclk_buffered,
RXUSRCLK20 => txusrclk2_buffered,
RXUSRCLK21 => txusrclk2_buffered,
TXCHARISK0 => is_kchar_tx0,
TXCHARISK1 => is_kchar_tx1,
TXENC8B10BUSE0 => use_hw_8b10b_support,
TXENC8B10BUSE1 => use_hw_8b10b_support,
------------------------ Loopback and Powerdown Ports ----------------------
LOOPBACK0 => (others => '0'),
LOOPBACK1 => (others => '0'),
RXPOWERDOWN0 => "11",
RXPOWERDOWN1 => "11",
--------------------------------- PLL Ports --------------------------------
GTPTEST0 => "00010000",
GTPTEST1 => "00010000",
INTDATAWIDTH0 => '1',
INTDATAWIDTH1 => '1',
PLLCLK00 => '0',
PLLCLK01 => '0',
PLLCLK10 => '0',
PLLCLK11 => '0',
REFCLKOUT0 => open,
REFCLKOUT1 => open,
REFCLKPLL0 => open,
REFCLKPLL1 => open,
REFCLKPWRDNB0 => '1', -- Not used - should power down
REFCLKPWRDNB1 => '1', -- Used- must be powered up
TSTCLK0 => '0',
TSTCLK1 => '0',
TSTIN0 => (others => '0'),
TSTIN1 => (others => '0'),
TSTOUT0 => open,
TSTOUT1 => open,
----------------------- Receive Ports - 8b10b Decoder ----------------------
RXCHARISCOMMA0 => open,
RXCHARISCOMMA1 => open,
RXCHARISK0 => open,
RXCHARISK1 => open,
RXDEC8B10BUSE0 => '1',
RXDEC8B10BUSE1 => '1',
RXDISPERR0 => open,
RXDISPERR1 => open,
RXNOTINTABLE0 => open,
RXNOTINTABLE1 => open,
RXRUNDISP0 => open,
RXRUNDISP1 => open,
USRCODEERR0 => '0',
USRCODEERR1 => '0',
---------------------- Receive Ports - Channel Bonding ---------------------
RXCHANBONDSEQ0 => open,
RXCHANBONDSEQ1 => open,
RXCHANISALIGNED0 => open,
RXCHANISALIGNED1 => open,
RXCHANREALIGN0 => open,
RXCHANREALIGN1 => open,
RXCHBONDI => (others => '0'),
RXCHBONDMASTER0 => '0',
RXCHBONDMASTER1 => '0',
RXCHBONDO => open,
RXCHBONDSLAVE0 => '0',
RXCHBONDSLAVE1 => '0',
RXENCHANSYNC0 => '0',
RXENCHANSYNC1 => '0',
---------------------- Receive Ports - Clock Correction --------------------
RXCLKCORCNT0 => open,
RXCLKCORCNT1 => open,
--------------- Receive Ports - Comma Detection and Alignment --------------
RXBYTEISALIGNED0 => open,
RXBYTEISALIGNED1 => open,
RXBYTEREALIGN0 => open,
RXBYTEREALIGN1 => open,
RXCOMMADET0 => open,
RXCOMMADET1 => open,
RXCOMMADETUSE0 => '1',
RXCOMMADETUSE1 => '1',
RXENMCOMMAALIGN0 => '0',
RXENMCOMMAALIGN1 => '0',
RXENPCOMMAALIGN0 => '0',
RXENPCOMMAALIGN1 => '0',
RXSLIDE0 => '0',
RXSLIDE1 => '0',
----------------------- Receive Ports - PRBS Detection ---------------------
PRBSCNTRESET0 => '1',
PRBSCNTRESET1 => '1',
RXENPRBSTST0 => "000",
RXENPRBSTST1 => "000",
RXPRBSERR0 => open,
RXPRBSERR1 => open,
------------------- Receive Ports - RX Data Path interface -----------------
RXDATA0 => open,
RXDATA1 => open,
RXDATAWIDTH0 => "01",
RXDATAWIDTH1 => "01",
RXRECCLK0 => open,
RXRECCLK1 => open,
RXRESET0 => '0',
RXRESET1 => '0',
------- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
GATERXELECIDLE0 => '0',
GATERXELECIDLE1 => '0',
IGNORESIGDET0 => '1',
IGNORESIGDET1 => '1',
RCALINEAST => (others =>'0'),
RCALINWEST => (others =>'0'),
RCALOUTEAST => open,
RCALOUTWEST => open,
RXCDRRESET0 => '0',
RXCDRRESET1 => '0',
RXELECIDLE0 => open,
RXELECIDLE1 => open,
RXEQMIX0 => "11",
RXEQMIX1 => "11",
RXN0 => '0',
RXN1 => '0',
RXP0 => '1',
RXP1 => '1',
----------- Receive Ports - RX Elastic Buffer and Phase Alignment ----------
RXBUFRESET0 => '0',
RXBUFRESET1 => '0',
RXBUFSTATUS0 => open,
RXBUFSTATUS1 => open,
RXENPMAPHASEALIGN0 => '0',
RXENPMAPHASEALIGN1 => '0',
RXPMASETPHASE0 => '0',
RXPMASETPHASE1 => '0',
RXSTATUS0 => open,
RXSTATUS1 => open,
--------------- Receive Ports - RX Loss-of-sync State Machine --------------
RXLOSSOFSYNC0 => open,
RXLOSSOFSYNC1 => open,
-------------- Receive Ports - RX Pipe Control for PCI Express -------------
PHYSTATUS0 => open,
PHYSTATUS1 => open,
RXVALID0 => open,
RXVALID1 => open,
-------------------- Receive Ports - RX Polarity Control -------------------
RXPOLARITY0 => '0',
RXPOLARITY1 => '0',
------------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
DADDR => (others=>'0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DRDY => open,
DRPDO => open,
DWE => '0',
---------------------------- TX/RX Datapath Ports --------------------------
GTPCLKFBEAST => open,
GTPCLKFBSEL0EAST => "10",
GTPCLKFBSEL0WEST => "00",
GTPCLKFBSEL1EAST => "11",
GTPCLKFBSEL1WEST => "01",
GTPCLKFBWEST => open,
------------------- Transmit Ports - 8b10b Encoder Control -----------------
TXBYPASS8B10B0 => "0000",
TXBYPASS8B10B1 => "0000",
TXKERR0 => open,
TXKERR1 => open,
TXRUNDISP0 => open,
TXRUNDISP1 => open,
--------------- Transmit Ports - TX Buffer and Phase Alignment -------------
TXBUFSTATUS0 => open,
TXBUFSTATUS1 => open,
TXENPMAPHASEALIGN0 => '0',
TXENPMAPHASEALIGN1 => '0',
TXPMASETPHASE0 => '0',
TXPMASETPHASE1 => '0',
------------------ Transmit Ports - TX Data Path interface -----------------
TXDATAWIDTH0 => "01",
TXDATAWIDTH1 => "01",
--------------- Transmit Ports - TX Driver and OOB signalling --------------
TXBUFDIFFCTRL0 => "101",
TXBUFDIFFCTRL1 => "101",
TXINHIBIT0 => '0',
TXINHIBIT1 => '0',
--------------------- Transmit Ports - TX PRBS Generator -------------------
TXENPRBSTST0 => "000",
TXENPRBSTST1 => "000",
TXPRBSFORCEERR0 => '0',
TXPRBSFORCEERR1 => '0',
-------------------- Transmit Ports - TX Polarity Control ------------------
TXPOLARITY0 => '0',
TXPOLARITY1 => '0',
----------------- Transmit Ports - TX Ports for PCI Express ----------------
TXDETECTRX0 => '0',
TXDETECTRX1 => '0',
TXELECIDLE0 => '0',
TXELECIDLE1 => '0',
TXPDOWNASYNCH0 => '0',
TXPDOWNASYNCH1 => '0',
--------------------- Transmit Ports - TX Ports for SATA -------------------
TXCOMSTART0 => '0',
TXCOMSTART1 => '0',
TXCOMTYPE0 => '0',
TXCOMTYPE1 => '0'
);
end Behavioral; | mit | dadee05f10a4c70edf6b208642fdd916 | 0.356441 | 4.398393 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpFilter/unitFIR/hdl/unitFIR-e.vhd | 1 | 2,389 | -------------------------------------------------------------------------------
-- Title : Finite Impulse Response Filter
-- Author : Steiger Martin <[email protected]>
-------------------------------------------------------------------------------
-- Description : Simple FIR filter structure for damping, amplifying and
-- compounding audio signals
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use work.pkgFIR.all;
use work.Global.all;
entity FIR is
generic
(
gDataWidth : natural := 24; -- bit width of audio data
gMaxNumCoeffs : natural := 16 -- number of available coefficients
);
port
(
----------------------------------------------------
-- avalon mm signals --
----------------------------------------------------
csi_clk : in std_logic; -- AVALON clock
rsi_reset_n : in std_logic; -- coefficient and data reset
avs_s0_address : in std_logic_vector(LogDualis(gMaxNumCoeffs) - 1 downto 0); -- coefficient address
avs_s0_write : in std_logic; -- write enable
avs_s0_writedata : in std_logic_vector(31 downto 0); -- coefficient to be written
--avs_s0_read : in std_logic; -- read enable
avs_s0_readdata : out std_logic_vector(31 downto 0); -- read coefficient
----------------------------------------------------
-- streaming interface --
----------------------------------------------------
asi_valid : in std_logic; -- input signal valid
asi_data : in std_logic_vector(gDataWidth - 1 downto 0); -- input audio signal
aso_valid : out std_logic; -- output data valid
aso_data : out std_logic_vector(gDataWidth - 1 downto 0) -- output audio signal
);
begin
assert (gDataWidth = 24)
report "ERROR: DataWidth is out of range!"
severity failure;
--assert(gNumberOfCoeffs <= cOrder)
--report "ERROR: larger number of coefficients than cOrder (pkgFIR.vhd) is not recommended"
--severity failure;
--assert(gNumberOfCoeffs <= 2**gNrAddressLines)
--report("ERROR: not eough address lines to reach every coefficient")
--severity failure;
end entity FIR;
| gpl-3.0 | 60e0501e78e393523e06cf6e046b769b | 0.53537 | 4.008389 | false | false | false | false |
ASP-SoC/ASP-SoC | libASP/grpSimulation/unitSinGen/hdl/SinGen-Bhv-ea.vhd | 1 | 1,376 | -------------------------------------------------------------------------------
-- Title : Sine Generator, only for simulation
-------------------------------------------------------------------------------
-- File : SinGen-Bhv-ea.vhd
-- Author : Franz Steinbacher
-------------------------------------------------------------------------------
-- Copyright (c) 2018
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library ieee_proposed;
use ieee_proposed.fixed_float_types.all;
use ieee_proposed.fixed_pkg.all;
use work.Global.all;
entity SinGen is
generic (
periode_g : time := 100 us;
sample_time_g : time := 200 ns
);
port (
clk_i : in std_ulogic;
data_o : out audio_data_t;
data_valid_o : out std_ulogic
);
end entity SinGen;
architecture Bhv of SinGen is
begin -- architecture Bhv
sin_gen : process is
begin -- process sin_gen
data_valid_o <= '0';
wait for sample_time_g;
wait until rising_edge(clk_i);
data_o <= to_sfixed(0.999999999999 * sin(MATH_2_PI * real(now/sample_time_g)/real(periode_g/sample_time_g)),0, -(data_width_c-1));
data_valid_o <= '1';
wait until rising_edge(clk_i);
end process sin_gen;
end architecture Bhv;
| gpl-3.0 | 27d9a6384fb90753b487ad837640b4f5 | 0.489099 | 3.811634 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp_sr_tb.vhd | 1 | 4,023 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_sr_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-15
-- Last update: 2016-05-15
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Disp shift register test bench
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-15 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity disp_sr_tb is
end disp_sr_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.tb_pkg.all;
architecture STRUCTURE of disp_sr_tb is
component disp_sr
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_data : in std_logic_vector(255 downto 0);
disp_sclk : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic
);
end component;
SIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL tsc_1pps : std_logic;
SIGNAL tsc_1ppms : std_logic;
SIGNAL tsc_1ppus : std_logic;
SIGNAL disp_data : std_logic_vector(255 downto 0);
SIGNAL disp_sclk : std_logic;
SIGNAL disp_lat : std_logic;
SIGNAL disp_sin : std_logic;
begin
disp_sr_i: disp_sr
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus,
disp_data => disp_data,
disp_sclk => disp_sclk,
disp_lat => disp_lat,
disp_sin => disp_sin
);
clk_100MHZ: clk_gen(10 ns, 50, clk);
reset: rst_n_gen(1 us, rst_n);
process
begin
tsc_1pps <= '0';
run_clk(clk, 1000);
loop
tsc_1pps <= '1';
run_clk(clk, 1);
tsc_1pps <= '0';
run_clk(clk, 1999999);
end loop;
end process;
process
begin
tsc_1ppms <= '0';
run_clk(clk, 1000);
loop
tsc_1ppms <= '1';
run_clk(clk, 1);
tsc_1ppms <= '0';
run_clk(clk, 1999);
end loop;
end process;
process
begin
tsc_1ppus <= '0';
run_clk(clk, 1000);
loop
tsc_1ppus <= '1';
run_clk(clk, 1);
tsc_1ppus <= '0';
run_clk(clk, 1);
end loop;
end process;
process
begin
disp_data <= (others =>'0');
run_clk(clk, 2000);
disp_data <= x"5aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa5";
run_clk(clk, 2000);
disp_data <= x"a55555555555555555555555555555555555555555555555555555555555555a";
run_clk(clk, 2000);
disp_data <= x"a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5";
run_clk(clk, 2000);
disp_data <= x"5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a5a";
run_clk(clk, 2000);
wait;
end process;
end STRUCTURE;
| gpl-3.0 | 5a18cdd48e4cfbe670a5b66ea1c61e1d | 0.44171 | 3.522767 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128.vhd | 1 | 10,331 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_sfifo_15x128.vhd when simulating
-- the core, k7_sfifo_15x128. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_sfifo_15x128 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END k7_sfifo_15x128;
ARCHITECTURE k7_sfifo_15x128_a OF k7_sfifo_15x128 IS
-- synthesis translate_off
COMPONENT wrapped_k7_sfifo_15x128
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(127 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(127 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_sfifo_15x128 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 4,
c_default_value => "BlankString",
c_din_width => 128,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 128,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 1,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 3,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 1,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 12,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 11,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 4,
c_rd_depth => 16,
c_rd_freq => 1,
c_rd_pntr_width => 4,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 4,
c_wr_depth => 16,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 4,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_sfifo_15x128
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full,
prog_empty => prog_empty
);
-- synthesis translate_on
END k7_sfifo_15x128_a;
| gpl-2.0 | 233135a8141b3a319152fdcb9e328885 | 0.53867 | 3.308037 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/spwpkg.vhd | 1 | 16,279 | --
-- SpaceWire VHDL package
--
library ieee;
use ieee.std_logic_1164.all;
package spwpkg is
-- Indicates a platform-specific implementation.
type spw_implementation_type is ( impl_generic, impl_fast );
-- Input signals to spwlink.
type spw_link_in_type is record
-- Enables automatic link start on receipt of a NULL character.
autostart: std_logic;
-- Enables link start once the Ready state is reached.
-- Without either "autostart" or "linkstart", the link remains in
-- state Ready.
linkstart: std_logic;
-- Do not start link (overrides "linkstart" and "autostart") and/or
-- disconnect the currently running link.
linkdis: std_logic;
-- Number of bytes available in the receive buffer. Used to for
-- flow-control operation. At least 8 bytes must be available
-- initially, otherwise the link can not start. Values larger than 63
-- are irrelevant and may be presented as 63. The available room may
-- decrease by one byte due to the reception of an N-Char; in that case
-- the "rxroom" signal must be updated on the clock following the clock
-- on which "rxchar" is high. Under no other circumstances may "rxroom"
-- be decreased.
rxroom: std_logic_vector(5 downto 0);
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside spwxmit until it can be processed.
tick_in: std_logic;
-- Control bits of the TimeCode to be sent.
-- Must be valid while tick_in is high.
ctrl_in: std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent.
-- Must be valid while tick_in is high.
time_in: std_logic_vector(5 downto 0);
-- Requests transmission of an N-Char.
-- Keep this signal high until confirmed by "txack".
txwrite: std_logic;
-- Control flag to be sent with the next N-Char.
-- Must be valid while "txwrite" is high.
txflag: std_logic;
-- Byte to be sent, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while "txwrite" is high.
txdata: std_logic_vector(7 downto 0);
end record;
-- Output signals from spwlink.
type spw_link_out_type is record
-- High if the link state machine is currently in state Started.
started: std_logic;
-- High if the link state machine is currently in state Connecting.
connecting: std_logic;
-- High if the link state machine is currently in state Run.
running: std_logic;
-- Disconnect detected in state Run. Triggers a reset and reconnect.
-- This indication is auto-clearing.
errdisc: std_logic;
-- Parity error detected in state Run. Triggers a reset and reconnect.
-- This indication is auto-clearing.
errpar: std_logic;
-- Invalid escape sequence detected in state Run.
-- Triggers a reset and reconnect; auto-clearing.
erresc: std_logic;
-- Credit error detected. Triggers a reset and reconnect.
-- This indication is auto-clearing.
errcred: std_logic;
-- High to confirm the transmission of an N-Char.
-- This is a Wishbone-style handshake signal. It has a combinatorial
-- dependency on "txwrite".
txack: std_logic;
-- High for one clock cycle if a TimeCode was just received.
-- Verification of the TimeCode as described in 8.12.2 of ECSS-E-50
-- is not implemented; all received timecodes are reported.
tick_out: std_logic;
-- Control bits of last received TimeCode.
ctrl_out: std_logic_vector(1 downto 0);
-- Counter value of last received TimeCode.
time_out: std_logic_vector(5 downto 0);
-- High for one clock cycle if an N-Char (data byte or EOP or EEP) was
-- just received. The data bits must be accepted immediately from
-- "rxflag" and "rxdata".
rxchar: std_logic;
-- High if the received character is EOP or EEP, low if it is a data
-- byte. Valid when "rxchar" is high.
rxflag: std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid when "rxchar" is high.
rxdata: std_logic_vector(7 downto 0);
end record;
-- Output signals from spwrecv to spwlink.
type spw_recv_out_type is record
-- High if at least one signal change was seen since enable.
-- Resets to low when rxen is low.
gotbit: std_logic;
-- High if at least one valid NULL pattern was detected since enable.
-- Resets to low when rxen is low.
gotnull: std_logic;
-- High for one clock cycle if an FCT token was just received.
gotfct: std_logic;
-- High for one clock cycle if a TimeCode was just received.
tick_out: std_logic;
-- Control bits of last received TimeCode.
ctrl_out: std_logic_vector(1 downto 0);
-- Counter value of last received TimeCode.
time_out: std_logic_vector(5 downto 0);
-- High for one clock cycle if an N-Char (data byte or EOP/EEP) was just received.
rxchar: std_logic;
-- High if rxchar is high and the received character is EOP or EEP.
-- Low if rxchar is high and the received character is a data byte.
rxflag: std_logic;
-- Received byte, or "00000000" for EOP or "00000001" for EEP.
-- Valid when "rxchar" is high.
rxdata: std_logic_vector(7 downto 0);
-- Disconnect detected (after a signal change was seen).
-- Resets to low when rxen is low or when a signal change is seen.
errdisc: std_logic;
-- Parity error detected (after a valid NULL pattern was seen).
-- Sticky; resets to low when rxen is low.
errpar: std_logic;
-- Escape sequence error detected (after a valid NULL pattern was seen).
-- Sticky; resets to low when rxen is low.
erresc: std_logic;
end record;
-- Input signals to spwxmit from spwlink.
type spw_xmit_in_type is record
-- High to enable transmitter; low to disable and reset transmitter.
txen: std_logic;
-- Indicates that only NULL characters may be transmitted.
stnull: std_logic;
-- Indicates that only NULL and/or FCT characters may be transmitted.
stfct: std_logic;
-- Requests transmission of an FCT character.
-- Keep this signal high until confirmed by "fctack".
fct_in: std_logic;
-- High for one clock cycle to request transmission of a TimeCode.
-- The request is registered inside spwxmit until it can be processed.
tick_in: std_logic;
-- Control bits of the TimeCode to be sent.
-- Must be valid while "tick_in" is high.
ctrl_in: std_logic_vector(1 downto 0);
-- Counter value of the TimeCode to be sent.
-- Must be valid while "tick_in" is high.
time_in: std_logic_vector(5 downto 0);
-- Request transmission of an N-Char.
-- Keep this signal high until confirmed by "txack".
txwrite: std_logic;
-- Control flag to be sent with the next N-Char.
-- Must be valid while "txwrite" is high.
txflag: std_logic;
-- Byte to send, or "00000000" for EOP or "00000001" for EEP.
-- Must be valid while "txwrite" is high.
txdata: std_logic_vector(7 downto 0);
end record;
-- Output signals from spwxmit to spwlink.
type spw_xmit_out_type is record
-- High to confirm transmission on an FCT character.
-- This is a Wishbone-style handshaking signal; it is combinatorially
-- dependent on "fct_in".
fctack: std_logic;
-- High to confirm transmission of an N-Char.
-- This is a Wishbone-style handshaking signal; it is combinatorially
-- dependent on both "fct_in" and "txwrite".
txack: std_logic;
end record;
-- Character-stream interface
component spwstream is
generic (
sysfreq: integer; -- clk freq in Hz
txclkfreq: integer := 0; -- txclk freq in Hz
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1; -- max bits per clk
tximpl: spw_implementation_type := impl_generic;
rxfifosize_bits: integer range 6 to 14 := 11; -- rx fifo size
txfifosize_bits: integer range 2 to 14 := 11 -- tx fifo size
);
port (
clk: in std_logic; -- system clock
rxclk: in std_logic; -- receiver sample clock
txclk: in std_logic; -- transmit clock
rst: in std_logic; -- synchronous reset
autostart: in std_logic; -- automatic link start
linkstart: in std_logic; -- forced link start
linkdis: in std_logic; -- stop link
txdivcnt: in std_logic_vector(7 downto 0); -- tx scale factor
tick_in: in std_logic; -- request timecode xmit
ctrl_in: in std_logic_vector(1 downto 0);
time_in: in std_logic_vector(5 downto 0);
txwrite: in std_logic; -- request character xmit
txflag: in std_logic; -- control flag of tx char
txdata: in std_logic_vector(7 downto 0);
txrdy: out std_logic; -- room in tx fifo
txhalff: out std_logic; -- tx fifo half full
tick_out: out std_logic; -- timecode received
ctrl_out: out std_logic_vector(1 downto 0);
time_out: out std_logic_vector(5 downto 0);
rxvalid: out std_logic; -- rx fifo not empty
rxhalff: out std_logic; -- rx fifo half full
rxflag: out std_logic; -- control flag of rx char
rxdata: out std_logic_vector(7 downto 0);
rxread: in std_logic; -- accept rx character
started: out std_logic; -- link in Started state
connecting: out std_logic; -- link in Connecting state
running: out std_logic; -- link in Run state
errdisc: out std_logic; -- disconnect error
errpar: out std_logic; -- parity error
erresc: out std_logic; -- escape error
errcred: out std_logic; -- credit error
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic
);
end component spwstream;
-- Link Level Interface
component spwlink is
generic (
reset_time: integer -- reset time in clocks (6.4 us)
);
port (
clk: in std_logic; -- system clock
rst: in std_logic; -- synchronous reset (active-high)
linki: in spw_link_in_type;
linko: out spw_link_out_type;
rxen: out std_logic;
recvo: in spw_recv_out_type;
xmiti: out spw_xmit_in_type;
xmito: in spw_xmit_out_type
);
end component spwlink;
-- Receiver
component spwrecv is
generic (
disconnect_time: integer range 1 to 255; -- disconnect period in system clock cycles
rxchunk: integer range 1 to 4 -- nr of bits per system clock
);
port (
clk: in std_logic; -- system clock
rxen: in std_logic; -- receiver enabled
recvo: out spw_recv_out_type;
inact: in std_logic;
inbvalid: in std_logic;
inbits: in std_logic_vector(rxchunk-1 downto 0)
);
end component spwrecv;
-- Transmitter (generic implementation)
component spwxmit is
port (
clk: in std_logic; -- system clock
rst: in std_logic; -- synchronous reset (active-high)
divcnt: in std_logic_vector(7 downto 0);
xmiti: in spw_xmit_in_type;
xmito: out spw_xmit_out_type;
spw_do: out std_logic; -- tx data to SPW bus
spw_so: out std_logic -- tx strobe to SPW bus
);
end component spwxmit;
-- Transmitter (separate tx clock domain)
component spwxmit_fast is
port (
clk: in std_logic; -- system clock
txclk: in std_logic; -- transmit clock
rst: in std_logic; -- synchronous reset (active-high)
divcnt: in std_logic_vector(7 downto 0);
xmiti: in spw_xmit_in_type;
xmito: out spw_xmit_out_type;
spw_do: out std_logic; -- tx data to SPW bus
spw_so: out std_logic -- tx strobe to SPW bus
);
end component spwxmit_fast;
-- Front-end for SpaceWire Receiver (generic implementation)
component spwrecvfront_generic is
port (
clk: in std_logic; -- system clock
rxen: in std_logic; -- high to enable receiver
inact: out std_logic; -- high if activity on input
inbvalid: out std_logic; -- high if inbits contains a valid received bit
inbits: out std_logic_vector(0 downto 0); -- received bit
spw_di: in std_logic; -- Data In signal from SpaceWire bus
spw_si: in std_logic -- Strobe In signal from SpaceWire bus
);
end component spwrecvfront_generic;
-- Front-end for SpaceWire Receiver (separate rx clock domain)
component spwrecvfront_fast is
generic (
rxchunk: integer range 1 to 4 -- max number of bits per system clock
);
port (
clk: in std_logic; -- system clock
rxclk: in std_logic; -- sample clock (DDR)
rxen: in std_logic; -- high to enable receiver
inact: out std_logic; -- high if activity on input
inbvalid: out std_logic; -- high if inbits contains a valid group of received bits
inbits: out std_logic_vector(rxchunk-1 downto 0); -- received bits
spw_di: in std_logic; -- Data In signal from SpaceWire bus
spw_si: in std_logic -- Strobe In signal from SpaceWire bus
);
end component spwrecvfront_fast;
-- Synchronous two-port memory.
component spwram is
generic (
abits: integer;
dbits: integer );
port (
rclk: in std_logic;
wclk: in std_logic;
ren: in std_logic;
raddr: in std_logic_vector(abits-1 downto 0);
rdata: out std_logic_vector(dbits-1 downto 0);
wen: in std_logic;
waddr: in std_logic_vector(abits-1 downto 0);
wdata: in std_logic_vector(dbits-1 downto 0) );
end component spwram;
-- Double flip-flop synchronizer.
component syncdff is
port (
clk: in std_logic; -- clock (destination domain)
rst: in std_logic; -- asynchronous reset, active-high
di: in std_logic; -- input data
do: out std_logic ); -- output data
end component syncdff;
end package;
| mit | 76bd587196f59cd8cd4f92ec2c38249c | 0.556177 | 4.195619 | false | false | false | false |
peteut/nvc | test/regress/binary_files.vhd | 1 | 862 | entity binary_files is
end entity;
architecture a of binary_files is
begin
main : process
constant file_name : string := "output.raw";
type binary_file is file of character;
file fptr : binary_file;
variable fstatus : file_open_status;
variable tmp, tmp2 : character;
begin
assert character'pos(character'low) = 0;
assert character'pos(character'high) = 255;
file_open(fstatus, fptr, file_name, write_mode);
assert fstatus = open_ok;
for i in 0 to 255 loop
write(fptr, character'val(i));
end loop;
file_close(fptr);
file_open(fstatus, fptr, file_name, read_mode);
assert fstatus = open_ok;
for i in 0 to 255 loop
read(fptr, tmp);
assert character'pos(tmp) = i;
end loop;
assert endfile(fptr);
file_close(fptr);
report "Success";
wait;
end process;
end;
| gpl-3.0 | df2ffcc854cdcad82e453024541ffca6 | 0.647332 | 3.532787 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/upcnt_n.vhd | 2 | 7,159 | -------------------------------------------------------------------------------
-- upcnt_n.vhd entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v1.01.b
--
-- Description:
-- This file contains a parameterizable N-bit up counter
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Data width of counter
--
-- Definition of Ports:
-- Clk -- System clock
-- Clr -- Active low clear
-- Data -- Serial data in
-- Cnt_en -- Count enable
-- Load -- Load line enable
-- Qout -- Shift register shift enable
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : integer :=9
);
port(
Clr : in std_logic;
Clk : in std_logic;
Data : in std_logic_vector (0 to C_SIZE-1);
Cnt_en : in std_logic;
Load : in std_logic;
Qout : inout std_logic_vector (0 to C_SIZE-1)
);
end upcnt_n;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of upcnt_n is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant enable_n : std_logic := '0';
signal q_int : unsigned (0 to C_SIZE-1);
begin
----------------------------------------------------------------------------
-- PROCESS: UP_COUNT_GEN
-- purpose: Up counter
----------------------------------------------------------------------------
UP_COUNT_GEN : process(Clk)
begin
if (Clk'event) and Clk = '1' then
if (Clr = enable_n) then -- Clear output register
q_int <= (others => '0');
elsif (Load = '1') then -- Load in start value
q_int <= unsigned(Data);
elsif Cnt_en = '1' then -- If count enable is high
q_int <= q_int + 1;
else
q_int <= q_int;
end if;
end if;
end process UP_COUNT_GEN;
Qout <= std_logic_vector(q_int);
end architecture RTL;
| gpl-3.0 | 288f1562f44ec666810d7429614f8f61 | 0.381198 | 5.283395 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/example_design/ram_16x1k_dp_exdes.vhd | 1 | 5,650 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_dp_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_dp_exdes IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END ram_16x1k_dp_exdes;
ARCHITECTURE xilinx OF ram_16x1k_dp_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT ram_16x1k_dp IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : ram_16x1k_dp
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| bsd-3-clause | 827562d14b831804db3c58511f808c57 | 0.544956 | 4.4279 | false | false | false | false |
peteut/nvc | test/regress/real1.vhd | 2 | 805 | entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0;
r := 2.0;
r := r * 3.0;
assert r > 5.99999;
assert r < 6.00001;
assert integer(r) = 6;
r := real(5);
report real'image(r);
r := real(-5.262e2);
report real'image(r);
r := real(1.23456);
report real'image(r);
r := real(2.0);
report real'image(r ** (-1));
report real'image(real'low);
report real'image(real'high);
wait;
end process;
end architecture;
| gpl-3.0 | 19977f8df5030755233d6602ffb0b1ee | 0.470807 | 3.382353 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_hid/example_design/weight_hid_exdes.vhd | 1 | 4,629 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_hid_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_hid_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weight_hid_exdes;
ARCHITECTURE xilinx OF weight_hid_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weight_hid IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weight_hid
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| bsd-2-clause | c1d533d206315bd1bd41683fa9106edf | 0.568157 | 4.737973 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/tsc.vhd | 1 | 16,311 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : tsc.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-04-29
-- Last update: 2017-06-08
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Time Stamp Counter
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-29 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity tsc is
port (
rst_n : in std_logic;
clk : in std_logic;
gps_1pps : in std_logic;
gps_3dfix_d : in std_logic;
tsc_read : in std_logic;
tsc_sync : in std_logic;
pfd_resync : in std_logic;
gps_1pps_d : out std_logic;
tsc_1pps_d : out std_logic;
pll_trig : out std_logic;
pfd_status : out std_logic;
pdiff_1pps : out std_logic_vector(31 downto 0);
fdiff_1pps : out std_logic_vector(31 downto 0);
tsc_cnt : out std_logic_vector(63 downto 0);
tsc_cnt1 : out std_logic_vector(63 downto 0);
tsc_1pps : out std_logic;
tsc_1ppms : out std_logic;
tsc_1ppus : out std_logic
);
end tsc;
architecture rtl of tsc is
signal counter : std_logic_vector(63 downto 0);
signal pps_cnt : std_logic_vector(27 downto 0);
signal pps_cnt_term : std_logic;
signal ppms_cnt : std_logic_vector(16 downto 0);
signal ppms_cnt_term : std_logic;
signal ppus_cnt : std_logic_vector(6 downto 0);
signal ppus_cnt_term : std_logic;
signal gps_1pps_dly : std_logic_vector(2 downto 0);
signal gps_1pps_pulse : std_logic;
signal pps_rst : std_logic;
signal tsc_1pps_dly : std_logic_vector(2 downto 0);
signal tsc_1pps_pulse : std_logic;
type pfd_t is (pfd_idle,
pfd_lead,
pfd_lag,
pfd_trig,
pfd_sync,
pfd_tsc,
pfd_gps,
pfd_det_gps,
pfd_det_tsc,
pfd_wait_gps,
pfd_wait_tsc
);
signal curr_state : pfd_t;
signal next_state : pfd_t;
constant CLKS_PER_SEC : natural := 100000000;
constant CLKS_PER_MS : natural := CLKS_PER_SEC / 1000;
constant CLKS_PER_US : natural := CLKS_PER_MS / 1000;
constant CLKS_PER_SEC_2 : natural := CLKS_PER_SEC / 2;
constant CLKS_PER_SEC_2N : integer := -CLKS_PER_SEC_2;
signal lead : std_logic;
signal lag : std_logic;
signal trig : std_logic;
signal gt_half : std_logic;
signal clr_diff : std_logic;
signal clr_status : std_logic;
signal set_status : std_logic;
signal diff_cnt : std_logic_vector(31 downto 0);
signal pdiff : std_logic_vector(31 downto 0);
signal fdiff : std_logic_vector(31 downto 0);
begin
-- The TSC counter 64 bit running at 100MHz
tsc_counter:
process (rst_n, clk) is
begin
if (rst_n = '0') then
counter <= (others => '0');
elsif (clk'event and clk = '1') then
counter <= counter + 1;
end if;
end process;
-- Output read sample register
-- Output count at one second
tsc_oreg:
process (rst_n, clk) is
begin
if (rst_n = '0') then
tsc_cnt <= (others => '0');
tsc_cnt1 <= (others => '0');
elsif (clk'event and clk = '1') then
if (tsc_read = '1') then
tsc_cnt <= counter;
end if;
if (pps_cnt_term = '1') then
tsc_cnt1 <= counter;
end if;
end if;
end process;
-- ----------------------------------------------------------------------
-- Reset signal register for pulse per s, ms, us counters and PFD
tsc_1pps_rst:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pps_rst <= '0';
elsif (clk'event and clk = '1') then
pps_rst <= tsc_sync and gps_1pps_pulse;
end if;
end process;
-- One pulse pulse per second
tsc_1pps_ctr:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pps_cnt <= (others => '0');
pps_cnt_term <= '0';
elsif (clk'event and clk = '1') then
if (pps_cnt_term = '1' or pps_rst = '1') then
pps_cnt <= (others => '0');
else
pps_cnt <= pps_cnt + 1;
end if;
if (pps_rst = '1') then
pps_cnt_term <= '0';
elsif (pps_cnt = (CLKS_PER_SEC - 2)) then
pps_cnt_term <= '1';
else
pps_cnt_term <= '0';
end if;
end if;
end process;
tsc_1pps <= pps_cnt_term;
-- Millisecond pulse generator synchronized to pps
tsc_1ppms_ctr:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ppms_cnt <= (others => '0');
ppms_cnt_term <= '0';
elsif (clk'event and clk = '1') then
if (ppms_cnt_term = '1' or pps_cnt_term = '1' or pps_rst = '1') then
ppms_cnt <= (others => '0');
else
ppms_cnt <= ppms_cnt + 1;
end if;
if (pps_cnt_term = '1' or pps_rst = '1') then
ppms_cnt_term <= '0';
elsif (ppms_cnt = (CLKS_PER_MS - 2)) then
ppms_cnt_term <= '1';
else
ppms_cnt_term <= '0';
end if;
end if;
end process;
tsc_1ppms <= ppms_cnt_term;
-- Microsecond pulse generator synchronized to pps
tsc_1ppus_ctr:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ppus_cnt <= (others => '0');
ppus_cnt_term <= '0';
elsif (clk'event and clk = '1') then
if (ppus_cnt_term = '1' or pps_cnt_term = '1' or pps_rst = '1') then
ppus_cnt <= (others => '0');
else
ppus_cnt <= ppus_cnt + 1;
end if;
if (pps_cnt_term = '1' or pps_rst = '1') then
ppus_cnt_term <= '0';
elsif (ppus_cnt = (CLKS_PER_US - 2)) then
ppus_cnt_term <= '1';
else
ppus_cnt_term <= '0';
end if;
end if;
end process;
tsc_1ppus <= ppus_cnt_term;
-- ----------------------------------------------------------------------
-- GPS 1 pulse per second input register
-- Delay the ocxo 1pps pulse approximately the same amount as the gps 1pps
tsc_pps_delay:
process (rst_n, clk) is
begin
if (rst_n = '0') then
gps_1pps_dly <= (others => '0');
gps_1pps_pulse <= '0';
tsc_1pps_dly <= (others => '0');
tsc_1pps_pulse <= '0';
elsif (clk'event and clk = '1') then
gps_1pps_dly(0) <= gps_1pps;
gps_1pps_dly(1) <= gps_1pps_dly(0);
gps_1pps_dly(2) <= gps_1pps_dly(1);
gps_1pps_pulse <= not gps_1pps_dly(2) and gps_1pps_dly(1);
if (pps_rst = '1') then
tsc_1pps_dly <= (others => '0');
tsc_1pps_pulse <= '0';
else
tsc_1pps_dly(0) <= pps_cnt_term;
tsc_1pps_dly(1) <= tsc_1pps_dly(0);
tsc_1pps_dly(2) <= tsc_1pps_dly(1);
tsc_1pps_pulse <= tsc_1pps_dly(1);
end if;
end if;
end process;
gps_1pps_d <= gps_1pps_pulse;
tsc_1pps_d <= tsc_1pps_pulse;
-- Phase detector state machine register
tsc_pfd_st:
process (rst_n, clk) is
begin
if (rst_n = '0') then
curr_state <= pfd_idle;
elsif (clk'event and clk = '1') then
curr_state <= next_state;
end if;
end process;
-- Phase detector State diagram
-- Set difference to zero for missing pps
-- Automatically set the lead/lag phasing
tsc_pfd_next:
process (curr_state, tsc_1pps_pulse, gps_1pps_pulse, pfd_resync, gt_half) is
begin
-- outputs
lead <= '0';
lag <= '0';
trig <= '0';
clr_diff <= '0';
clr_status <= '0';
set_status <= '0';
case curr_state is
-- ------------------------------------------------------------
-- ------------------------------------------------------------
-- Phase detector
-- Referenced to GPS PPS
-- Negative phase if TSC is before GPS
when pfd_idle =>
-- Idle state
clr_status <= '1';
if (tsc_1pps_pulse = '1' and gps_1pps_pulse = '1') then
next_state <= pfd_trig;
elsif (tsc_1pps_pulse = '1') then
next_state <= pfd_lead;
elsif (gps_1pps_pulse = '1' ) then
next_state <= pfd_lag;
elsif (pfd_resync = '1') then
next_state <= pfd_sync;
else
next_state <= pfd_idle;
end if;
when pfd_lead =>
-- Got tsc pps before gps
lead <= '1'; -- Count down
if (tsc_1pps_pulse = '1' or gt_half = '1') then
-- Missing gps pps
next_state <= pfd_sync;
elsif (gps_1pps_pulse = '1' ) then
next_state <= pfd_trig;
else
next_state <= pfd_lead;
end if;
when pfd_lag =>
-- Got gps pps before tsc
lag <= '1'; -- Count up
if (gps_1pps_pulse = '1' or gt_half = '1') then
-- Missing tsc pps
next_state <= pfd_sync;
elsif (tsc_1pps_pulse = '1') then
next_state <= pfd_trig;
else
next_state <= pfd_lag;
end if;
when pfd_trig =>
-- Set the holding register
trig <= '1';
next_state <= pfd_idle;
-- ------------------------------------------------------------
-- ------------------------------------------------------------
-- Resync the phase detector
when pfd_sync =>
-- Resync the phase detector due to lost pulse or sw resync
clr_diff <= '1';
set_status <= '1';
if (tsc_1pps_pulse = '1' and gps_1pps_pulse = '1') then
next_state <= pfd_idle;
elsif (tsc_1pps_pulse = '1') then
next_state <= pfd_tsc;
elsif (gps_1pps_pulse = '1' ) then
next_state <= pfd_gps;
else
next_state <= pfd_sync;
end if;
-- ------------------------------------------------------------
-- tsc pulse detected first
when pfd_tsc =>
-- tsc pulse detected, measure time to gps pulse
lag <= '1'; -- Count up
if (tsc_1pps_pulse = '1') then
next_state <= pfd_sync;
elsif (gps_1pps_pulse = '1' ) then
next_state <= pfd_det_gps;
else
next_state <= pfd_tsc;
end if;
when pfd_det_gps =>
-- gps pulse detected, check tsc->gps time measurement
if (gt_half = '1' ) then
next_state <= pfd_wait_gps;
else
next_state <= pfd_idle;
end if;
when pfd_wait_gps =>
-- Wait for next gps pulse to restart measurement
if (tsc_1pps_pulse = '1' and gps_1pps_pulse = '1') then
next_state <= pfd_idle;
elsif (gps_1pps_pulse = '1' ) then
next_state <= pfd_gps;
else
next_state <= pfd_wait_gps;
end if;
-- ------------------------------------------------------------
-- gps pulse detected first
when pfd_gps =>
-- gps pulse detected, measure time to tsc pulse
lag <= '1'; -- Count up
if (gps_1pps_pulse = '1') then
next_state <= pfd_sync;
elsif (tsc_1pps_pulse = '1' ) then
next_state <= pfd_det_tsc;
else
next_state <= pfd_gps;
end if;
when pfd_det_tsc =>
-- gps pulse detected, check gps->tsc time measurement
if (gt_half = '1' ) then
next_state <= pfd_wait_tsc;
else
next_state <= pfd_idle;
end if;
when pfd_wait_tsc =>
-- Wait for next tsc pulse to restart measurement
if (tsc_1pps_pulse = '1' and gps_1pps_pulse = '1') then
next_state <= pfd_idle;
elsif (tsc_1pps_pulse = '1' ) then
next_state <= pfd_tsc;
else
next_state <= pfd_wait_tsc;
end if;
-- ------------------------------------------------------------
-- ------------------------------------------------------------
when others =>
next_state <= pfd_idle;
end case;
end process;
pll_trig <= trig;
-- Difference measurement between GPS and OCXO
tsc_ctrs:
process (rst_n, clk) is
begin
if (rst_n = '0') then
diff_cnt <= (others => '0');
gt_half <= '0';
elsif (clk'event and clk = '1') then
if (lead = '0' and lag = '0') then
diff_cnt <= (others => '0');
gt_half <= '0';
else
if (lag = '1') then
diff_cnt <= diff_cnt + 1;
elsif (lead = '1') then
diff_cnt <= diff_cnt - 1;
end if;
if (diff_cnt = CLKS_PER_SEC_2 or
diff_cnt = conv_std_logic_vector(CLKS_PER_SEC_2N, diff_cnt'length)) then
gt_half <= '1';
end if;
end if;
end if;
end process;
-- Count output for micro registers
-- PFD sync state status register
tsc_pfd_status:
process (rst_n, clk) is
begin
if (rst_n = '0') then
pdiff <= (others => '0');
fdiff <= (others => '0');
pfd_status <= '0';
elsif (clk'event and clk = '1') then
if (clr_diff = '1') then
pdiff <= (others => '0');
fdiff <= (others => '0');
elsif (trig = '1') then
pdiff <= diff_cnt;
fdiff <= diff_cnt - pdiff;
end if;
if (clr_status = '1') then
pfd_status <= '0';
elsif (set_status = '1') then
pfd_status <= '1';
end if;
end if;
end process;
pdiff_1pps <= pdiff;
fdiff_1pps <= fdiff;
end rtl;
| gpl-3.0 | 935239809bb94d363d1c9f6f703766d4 | 0.406535 | 3.937953 | false | false | false | false |
peteut/nvc | test/sem/wait.vhd | 4 | 1,416 | entity a is
end entity;
architecture b of a is
signal x, y : bit;
signal z : bit_vector(3 downto 0);
alias xa is x;
alias za : bit is z(2);
begin
-- wait for
process is
begin
wait for ps;
wait for 5 ns;
wait for 2 * 4 hr;
wait for 523; -- Not TIME type
end process;
-- wait on
process is
variable v : bit;
begin
wait on x;
wait on x, y;
wait on v; -- Not signal
end process;
-- process sensitivity
process (x, y) is
begin
x <= y;
end process;
process (x, a) is -- Bad name a
begin
x <= '1';
end process;
process (x) is
begin
x <= y;
wait for 1 ns; -- Not allowed wait
end process;
-- wait until
process is
begin
wait until true;
wait until x = '1';
wait until x; -- Not boolean
wait until y = x for 1 ns;
wait until y = x for x; -- Not time
end process;
-- Alias in sensitivity list
process (xa, za) is
begin
end process;
-- Wait on scalar sub-elements and slices
process is
variable i : integer;
begin
wait on z(1), za, z(2 downto 1);
wait on z(i); -- Not static
end process;
end architecture;
| gpl-3.0 | 880bbbed3afb00402d6120c8ee3be223 | 0.478107 | 4.104348 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/util_pkg.vhd | 1 | 9,110 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : util_pkg.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-04-26
-- Last update: 2018-01-20
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Utility components
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-26 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
package util_pkg is
component delay_sig
generic (
cycles : in natural := 0;
init : in std_logic := '0'
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic
);
end component delay_sig;
component delay_vec
generic (
cycles : in natural := 0
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic_vector;
signal q : out std_logic_vector
);
end component delay_vec;
component delay_pulse
generic (
cycles : in natural := 0
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic
);
end component delay_pulse;
component pulse_stretch
generic (
cycles : in natural := 0
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic
);
end component pulse_stretch;
function log2(i : in natural) return natural;
end package util_pkg;
package body util_pkg is
function log2(i : in natural) return natural is
variable mask : natural;
variable count : natural;
begin
mask := 1;
for count in 0 to 31 loop
if (mask >= i) then
return (count);
end if;
mask := mask * 2;
end loop;
return (count);
end function;
end package body util_pkg;
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity delay_sig is
generic (
cycles : in natural := 0;
init : in std_logic := '0'
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic
);
end delay_sig;
architecture rtl of delay_sig is
begin
zero:
if (cycles = 0) generate
q <= d;
end generate zero;
one:
if (cycles = 1) generate
process (rst_n, clk)
begin
if (rst_n = '0') then
q <= init;
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end generate;
gt_one:
if (cycles > 1) generate
signal dly : std_logic_vector(cycles - 1 downto 0);
begin
process (rst_n, clk)
begin
if (rst_n = '0') then
dly <= (others => init);
elsif (clk'event and clk = '1') then
dly(0) <= d;
for i in 1 to cycles - 1 loop
dly(i) <= dly(i - 1);
end loop;
end if;
end process;
q <= dly(cycles - 1);
end generate;
end rtl;
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity delay_vec is
generic (
cycles : in natural := 0
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic_vector;
signal q : out std_logic_vector
);
end delay_vec;
architecture rtl of delay_vec is
begin
zero:
if (cycles = 0) generate
q <= d;
end generate zero;
one:
if (cycles = 1) generate
process (rst_n, clk)
begin
if (rst_n = '0') then
q <= (others => '0');
elsif (clk'event and clk = '1') then
q <= d;
end if;
end process;
end generate;
gt_one:
if (cycles > 1) generate
type dly_arr is array(natural range <>) of std_logic_vector(d'range);
signal dly : dly_arr(cycles - 1 downto 0);
begin
process (rst_n, clk)
begin
if (rst_n = '0') then
for i in 0 to cycles - 1 loop
dly(i) <= (others => '0');
end loop;
elsif (clk'event and clk = '1') then
dly(0) <= d;
for i in 1 to cycles - 1 loop
dly(i) <= dly(i - 1);
end loop;
end if;
end process;
q <= dly(cycles - 1);
end generate;
end rtl;
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.util_pkg.all;
entity delay_pulse is
generic (
cycles : in natural := 0
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic
);
end delay_pulse;
architecture rtl of delay_pulse is
begin
le_3:
if (cycles <= 3) generate
begin
d_s: delay_sig generic map (cycles) port map (rst_n, clk, d, q);
end generate;
gt_3:
if (cycles > 3) generate
signal dly : std_logic_vector(log2(cycles) - 1 downto 0);
begin
process (rst_n, clk)
begin
if (rst_n = '0') then
dly <= (others => '0');
q <= '0';
elsif (clk'event and clk = '1') then
if (d = '1') then
dly <= conv_std_logic_vector(cycles - 1, dly'length);
elsif (dly /= 0) then
dly <= dly - 1;
else
dly <= dly;
end if;
if (dly = 1 and d = '0') then
q <= '1';
else
q <= '0';
end if;
end if;
end process;
end generate;
end rtl;
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.util_pkg.all;
entity pulse_stretch is
generic (
cycles : in natural := 0
);
port (
signal rst_n : in std_logic;
signal clk : in std_logic;
signal d : in std_logic;
signal q : out std_logic
);
end pulse_stretch;
architecture rtl of pulse_stretch is
begin
lt_1:
if (cycles < 1) generate
begin
d_s: delay_sig generic map (1) port map (rst_n, clk, d, q);
end generate;
ge_1:
if (cycles >= 1) generate
signal clear : std_logic;
begin
d_s: delay_pulse generic map (cycles + 1) port map (rst_n, clk, d, clear);
process (rst_n, clk)
begin
if (rst_n = '0') then
q <= '0';
elsif (clk'event and clk = '1') then
if (d = '1') then
q <= '1';
elsif (clear = '1') then
q <= '0';
end if;
end if;
end process;
end generate;
end rtl;
| gpl-3.0 | 5091e42f17587f40330ece1ad23dc80e | 0.401537 | 4.400966 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/soft_reset.vhd | 2 | 13,703 | --soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
| gpl-3.0 | 55d1692cb1fcab04fada8249c878d9a5 | 0.404729 | 4.864395 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/dynamic_master.vhd | 2 | 16,342 | -------------------------------------------------------------------------------
-- dynamic_master.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: dynamic_master.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the control logic for the dynamic master.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Definition of Ports:
-- Clk -- System clock
-- Rst -- System reset
-- Dynamic_MSMS -- Dynamic master slave mode select
-- Cr -- Control register
-- Tx_fifo_rd_i -- Transmit FIFO read
-- Tx_data_exists -- Trnasmit FIFO exists
-- AckDataState -- Data ack acknowledge signal
-- Tx_fifo_data -- Transmit FIFO read input
-- EarlyAckHdr -- Ack_header state strobe signal
-- EarlyAckDataState -- Data ack early acknowledge signal
-- Bb -- Bus busy indicator
-- Msms_rst_r -- MSMS reset indicator
-- DynMsmsSet -- Dynamic MSMS set signal
-- DynRstaSet -- Dynamic repeated start set signal
-- Msms_rst -- MSMS reset signal
-- TxFifoRd -- Transmit FIFO read output signal
-- Txak -- Transmit ack signal
-- Cr_txModeSelect_set -- Sets transmit mode select
-- Cr_txModeSelect_clr -- Clears transmit mode select
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity dynamic_master is
port(
Clk : in std_logic;
Rst : in std_logic;
Dynamic_MSMS : in std_logic_vector(0 to 1);
Cr : in std_logic_vector(0 to 7);
Tx_fifo_rd_i : in std_logic;
Tx_data_exists : in std_logic;
AckDataState : in std_logic;
Tx_fifo_data : in std_logic_vector(0 to 7);
EarlyAckHdr : in std_logic;
EarlyAckDataState : in std_logic;
Bb : in std_logic;
Msms_rst_r : in std_logic;
DynMsmsSet : out std_logic;
DynRstaSet : out std_logic;
Msms_rst : out std_logic;
TxFifoRd : out std_logic;
Txak : out std_logic;
Cr_txModeSelect_set : out std_logic;
Cr_txModeSelect_clr : out std_logic
);
end dynamic_master;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of dynamic_master is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal firstDynStartSeen : std_logic; -- used to detect re-start during
-- dynamic start generation
signal dynamic_MSMS_d : std_logic_vector(0 to 1);
signal rxCntDone : std_logic;
signal forceTxakHigh : std_logic;
signal earlyAckDataState_d1: std_logic;
signal ackDataState_d1 : std_logic;
signal rdByteCntr : unsigned(0 to 7);
signal rdCntrFrmTxFifo : std_logic;
signal callingReadAccess : std_logic;
signal dynamic_start : std_logic;
signal dynamic_stop : std_logic;
-------------------------------------------------------------------------------
begin
-- In the case where the tx fifo only contains a single byte (the address)
-- which contains both start and stop bits set the controller has to rely on
-- the tx fifo data exists flag to qualify the fifo output. Otherwise the
-- controller emits a continous stream of bytes. This fixes CR439857
dynamic_start <= Dynamic_MSMS(1) and Tx_data_exists;
dynamic_stop <= Dynamic_MSMS(0) and Tx_data_exists;
DynMsmsSet <= dynamic_start -- issue dynamic start by setting MSMS
and not(Cr(5)) -- when MSMS is not already set and
and not(Bb); -- bus isn't busy
DynRstaSet <= dynamic_start -- issue repeated start when
and Tx_fifo_rd_i
and firstDynStartSeen; -- MSMS is already set
Msms_rst <= (dynamic_stop and Tx_fifo_rd_i)
or Msms_rst_r
or rxCntDone;
TxFifoRd <= Tx_fifo_rd_i or rdCntrFrmTxFifo;
forceTxakHigh <= '1' when (EarlyAckDataState='1' and callingReadAccess='1'
and rdByteCntr = 0) else
'0';
Txak <= Cr(3) or forceTxakHigh;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MSMS_DLY_PROCESS
-- purpose: Dynamic Master MSMS registering
-----------------------------------------------------------------------------
DYN_MSMS_DLY_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
dynamic_MSMS_d <= (others => '0');
else
dynamic_MSMS_d <= Dynamic_MSMS;
end if;
end if;
end process DYN_MSMS_DLY_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_START_PROCESS
-- purpose: reset firstDynStartSeen if CR(5) MSMS is cleared
-----------------------------------------------------------------------------
DYN_START_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
firstDynStartSeen <= '0';
else
if(Cr(5) = '0') then
firstDynStartSeen <= '0';
elsif(firstDynStartSeen = '0' and Tx_fifo_rd_i = '1'
and dynamic_start = '1') then
firstDynStartSeen <= '1';
end if;
end if;
end if;
end process DYN_START_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_ACCESS_PROCESS
-- purpose: capture access direction initiated via dynamic Start
-----------------------------------------------------------------------------
DYN_RD_ACCESS_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
callingReadAccess <= '0';
else
if(Tx_fifo_rd_i = '1' and dynamic_start = '1') then
callingReadAccess <= Tx_fifo_data(7);
end if;
end if;
end if;
end process DYN_RD_ACCESS_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MODE_SELECT_SET_PROCESS
-- purpose: Set the tx Mode Select bit in the CR register at the begining of
-- each ack_header state
-----------------------------------------------------------------------------
DYN_MODE_SELECT_SET_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Cr_txModeSelect_set <= '0';
elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then
Cr_txModeSelect_set <= not callingReadAccess;
else
Cr_txModeSelect_set <= '0';
end if;
end if;
end process DYN_MODE_SELECT_SET_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_MODE_SELECT_CLR_PROCESS
-- purpose: Clear the tx Mode Select bit in the CR register at the begining of
-- each ack_header state
-----------------------------------------------------------------------------
DYN_MODE_SELECT_CLR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
Cr_txModeSelect_clr <= '0';
elsif(EarlyAckHdr='1' and firstDynStartSeen='1') then
Cr_txModeSelect_clr <= callingReadAccess;
else
Cr_txModeSelect_clr <= '0';
end if;
end if;
end process DYN_MODE_SELECT_CLR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_CNTR_PROCESS
-- purpose: If this iic cycle is generating a read access, create a read
-- of the tx fifo to get the number of tx to process
-----------------------------------------------------------------------------
DYN_RD_CNTR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rdCntrFrmTxFifo <= '0';
else
if(EarlyAckHdr='1' and Tx_data_exists='1'
and callingReadAccess='1') then
rdCntrFrmTxFifo <= '1';
else
rdCntrFrmTxFifo <= '0';
end if;
end if;
end if;
end process DYN_RD_CNTR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_BYTE_CNTR_PROCESS
-- purpose: If this iic cycle is generating a read access, create a read
-- of the tx fifo to get the number of rx bytes to process
-----------------------------------------------------------------------------
DYN_RD_BYTE_CNTR_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rdByteCntr <= (others => '0');
else
if(rdCntrFrmTxFifo='1') then
rdByteCntr <= unsigned(Tx_fifo_data);
elsif(EarlyAckDataState='1' and earlyAckDataState_d1='0'
and rdByteCntr /= 0) then
rdByteCntr <= rdByteCntr - 1;
end if;
end if;
end if;
end process DYN_RD_BYTE_CNTR_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_RD_BYTE_CNTR_PROCESS
-- purpose: Initialize read byte counter in order to control master
-- generation of ack to slave.
-----------------------------------------------------------------------------
DYN_EARLY_DATA_ACK_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
earlyAckDataState_d1 <= '0';
else
earlyAckDataState_d1 <= EarlyAckDataState;
end if;
end if;
end process DYN_EARLY_DATA_ACK_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_STATE_DATA_ACK_PROCESS
-- purpose: Register ackdatastate
-----------------------------------------------------------------------------
DYN_STATE_DATA_ACK_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
ackDataState_d1 <= '0';
else
ackDataState_d1 <= AckDataState;
end if;
end if;
end process DYN_STATE_DATA_ACK_PROCESS;
-----------------------------------------------------------------------------
-- PROCESS: DYN_STATE_DATA_ACK_PROCESS
-- purpose: Generation of receive count done to generate stop
-----------------------------------------------------------------------------
DYN_RX_CNT_PROCESS:process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxCntDone <= '0';
else
if(AckDataState='1' and ackDataState_d1='0' and callingReadAccess='1'
and rdByteCntr = 0) then
rxCntDone <= '1';
else
rxCntDone <= '0';
end if;
end if;
end if;
end process DYN_RX_CNT_PROCESS;
end architecture RTL;
| gpl-3.0 | 7c252379bd035969f45c018c03c32231 | 0.434463 | 5.102092 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/user_logic.vhd | 1 | 31,508 | ------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Tue May 5 20:44:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_NUM_REG -- Number of software accessible registers
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Resetn -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_NUM_REG : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH / 8 - 1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG - 1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG - 1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Resetn : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg1 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg2 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg3 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg4 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg5 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg6 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg7 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg8 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg9 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg10 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg11 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg12 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg13 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg14 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg15 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg16 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg17 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg18 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg19 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg20 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg21 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg22 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg23 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg24 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg25 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg26 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg27 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg28 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg29 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg30 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg31 : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg_write_sel : std_logic_vector(31 downto 0);
signal slv_reg_read_sel : std_logic_vector(31 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal slv_reg26_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg28_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_reg29_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
--signal slv_reg30_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
--signal slv_reg31_internal : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
component superip_internal is
port(
-- Outputs
Mux3_BalanceORMux2_Left_out : out std_logic_vector(23 downto 0);
Mux3_BalanceORMux2_Right_out : out std_logic_vector(23 downto 0);
slv_reg26 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg28 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg29 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg30 : out STD_LOGIC_VECTOR(31 downto 0);
slv_reg31 : out STD_LOGIC_VECTOR(31 downto 0);
-- Inputs
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic;
Audio_Left_in : in std_logic_vector(23 downto 0);
Audio_Right_in : in std_logic_vector(23 downto 0);
SAMPLE_TRIG : in std_logic;
-- REGISTERS
slv_reg0 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg1 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg2 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg3 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg4 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg5 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg6 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg7 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg8 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg9 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg10 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg11 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg12 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg13 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg14 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg15 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg16 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg17 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg18 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg19 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg20 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg21 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg22 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg23 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg24 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg25 : in STD_LOGIC_VECTOR(31 downto 0);
slv_reg27 : in STD_LOGIC_VECTOR(31 downto 0)
);
end component;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(31 downto 0);
slv_reg_read_sel <= Bus2IP_RdCE(31 downto 0);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6) or Bus2IP_WrCE(7) or Bus2IP_WrCE(8) or Bus2IP_WrCE(9) or Bus2IP_WrCE(10) or Bus2IP_WrCE(11) or Bus2IP_WrCE(12) or Bus2IP_WrCE(13)
or Bus2IP_WrCE(14) or Bus2IP_WrCE(15) or Bus2IP_WrCE(16) or Bus2IP_WrCE(17) or Bus2IP_WrCE(18) or Bus2IP_WrCE(19) or Bus2IP_WrCE(20) or Bus2IP_WrCE(21) or Bus2IP_WrCE(22) or Bus2IP_WrCE(23) or Bus2IP_WrCE(24) or Bus2IP_WrCE(25) or Bus2IP_WrCE(26) or Bus2IP_WrCE(27) or
Bus2IP_WrCE(28) or Bus2IP_WrCE(29) or Bus2IP_WrCE(30) or Bus2IP_WrCE(31);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6) or Bus2IP_RdCE(7) or Bus2IP_RdCE(8) or Bus2IP_RdCE(9) or Bus2IP_RdCE(10) or Bus2IP_RdCE(11) or Bus2IP_RdCE(12) or Bus2IP_RdCE(13)
or Bus2IP_RdCE(14) or Bus2IP_RdCE(15) or Bus2IP_RdCE(16) or Bus2IP_RdCE(17) or Bus2IP_RdCE(18) or Bus2IP_RdCE(19) or Bus2IP_RdCE(20) or Bus2IP_RdCE(21) or Bus2IP_RdCE(22) or Bus2IP_RdCE(23) or Bus2IP_RdCE(24) or Bus2IP_RdCE(25) or Bus2IP_RdCE(26) or Bus2IP_RdCE(27) or
Bus2IP_RdCE(28) or Bus2IP_RdCE(29) or Bus2IP_RdCE(30) or Bus2IP_RdCE(31);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process(Bus2IP_Clk) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
slv_reg7 <= (others => '0');
slv_reg8 <= (others => '0');
slv_reg9 <= (others => '0');
slv_reg10 <= (others => '0');
slv_reg11 <= (others => '0');
slv_reg12 <= (others => '0');
slv_reg13 <= (others => '0');
slv_reg14 <= (others => '0');
slv_reg15 <= (others => '0');
slv_reg16 <= (others => '0');
slv_reg17 <= (others => '0');
slv_reg18 <= (others => '0');
slv_reg19 <= (others => '0');
slv_reg20 <= (others => '0');
slv_reg21 <= (others => '0');
slv_reg22 <= (others => '0');
slv_reg23 <= (others => '0');
slv_reg24 <= (others => '0');
slv_reg25 <= (others => '0');
slv_reg26 <= (others => '0');
slv_reg27 <= (others => '0');
slv_reg28 <= (others => '0');
slv_reg29 <= (others => '0');
slv_reg30 <= (others => '0');
slv_reg31 <= (others => '0');
else
case slv_reg_write_sel is
when "10000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg0(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "01000000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg1(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00100000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg2(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00010000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg3(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00001000000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg4(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000100000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg5(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000010000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg6(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000001000000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg7(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000100000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg8(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000010000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg9(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000001000000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg10(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000100000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg11(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000010000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg12(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000001000000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg13(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000100000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg14(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000010000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg15(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000001000000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg16(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000100000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg17(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000010000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg18(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000001000000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg19(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000100000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg20(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000010000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg21(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000001000000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg22(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000000100000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg23(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000000010000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg24(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
when "00000000000000000000000001000000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg25(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
-- when "00000000000000000000000000100000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
-- if (Bus2IP_BE(byte_index) = '1') then
-- slv_reg26(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
-- end if;
-- end loop;
when "00000000000000000000000000010000" =>
for byte_index in 0 to (C_SLV_DWIDTH / 8) - 1 loop
if (Bus2IP_BE(byte_index) = '1') then
slv_reg27(byte_index * 8 + 7 downto byte_index * 8) <= Bus2IP_Data(byte_index * 8 + 7 downto byte_index * 8);
end if;
end loop;
-- when "00000000000000000000000000001000" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
-- when "00000000000000000000000000000100" =>
-- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
-- if ( Bus2IP_BE(byte_index) = '1' ) then
-- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
-- end if;
-- end loop;
when "00000000000000000000000000000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when "00000000000000000000000000000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg31(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8);
end if;
end loop;
when others => null;
end case;
slv_reg26 <= slv_reg26_internal;
slv_reg28 <= slv_reg28_internal;
slv_reg29 <= slv_reg29_internal;
--slv_reg30 <= slv_reg30_internal;
--slv_reg31 <= slv_reg31_internal;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6, slv_reg7, slv_reg8, slv_reg9, slv_reg10, slv_reg11, slv_reg12, slv_reg13, slv_reg14, slv_reg15, slv_reg16, slv_reg17, slv_reg18, slv_reg19, slv_reg20, slv_reg21, slv_reg22, slv_reg23, slv_reg24, slv_reg25, slv_reg26, slv_reg27, slv_reg28, slv_reg29, slv_reg30, slv_reg31)
is
begin
case slv_reg_read_sel is
when "10000000000000000000000000000000" => slv_ip2bus_data <= slv_reg0;
when "01000000000000000000000000000000" => slv_ip2bus_data <= slv_reg1;
when "00100000000000000000000000000000" => slv_ip2bus_data <= slv_reg2;
when "00010000000000000000000000000000" => slv_ip2bus_data <= slv_reg3;
when "00001000000000000000000000000000" => slv_ip2bus_data <= slv_reg4;
when "00000100000000000000000000000000" => slv_ip2bus_data <= slv_reg5;
when "00000010000000000000000000000000" => slv_ip2bus_data <= slv_reg6;
when "00000001000000000000000000000000" => slv_ip2bus_data <= slv_reg7;
when "00000000100000000000000000000000" => slv_ip2bus_data <= slv_reg8;
when "00000000010000000000000000000000" => slv_ip2bus_data <= slv_reg9;
when "00000000001000000000000000000000" => slv_ip2bus_data <= slv_reg10;
when "00000000000100000000000000000000" => slv_ip2bus_data <= slv_reg11;
when "00000000000010000000000000000000" => slv_ip2bus_data <= slv_reg12;
when "00000000000001000000000000000000" => slv_ip2bus_data <= slv_reg13;
when "00000000000000100000000000000000" => slv_ip2bus_data <= slv_reg14;
when "00000000000000010000000000000000" => slv_ip2bus_data <= slv_reg15;
when "00000000000000001000000000000000" => slv_ip2bus_data <= slv_reg16;
when "00000000000000000100000000000000" => slv_ip2bus_data <= slv_reg17;
when "00000000000000000010000000000000" => slv_ip2bus_data <= slv_reg18;
when "00000000000000000001000000000000" => slv_ip2bus_data <= slv_reg19;
when "00000000000000000000100000000000" => slv_ip2bus_data <= slv_reg20;
when "00000000000000000000010000000000" => slv_ip2bus_data <= slv_reg21;
when "00000000000000000000001000000000" => slv_ip2bus_data <= slv_reg22;
when "00000000000000000000000100000000" => slv_ip2bus_data <= slv_reg23;
when "00000000000000000000000010000000" => slv_ip2bus_data <= slv_reg24;
when "00000000000000000000000001000000" => slv_ip2bus_data <= slv_reg25;
when "00000000000000000000000000100000" => slv_ip2bus_data <= slv_reg26;
when "00000000000000000000000000010000" => slv_ip2bus_data <= slv_reg27;
when "00000000000000000000000000001000" => slv_ip2bus_data <= slv_reg28;
when "00000000000000000000000000000100" => slv_ip2bus_data <= slv_reg29;
when "00000000000000000000000000000010" => slv_ip2bus_data <= slv_reg30;
when "00000000000000000000000000000001" => slv_ip2bus_data <= slv_reg31;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
SIP : superip_internal port map(
Mux3_BalanceORMux2_Left_out => Mux3_BalanceORMux2_Left_out,
Mux3_BalanceORMux2_Right_out => Mux3_BalanceORMux2_Right_out,
slv_reg26 => slv_reg26_internal,
slv_reg28 => slv_reg28_internal,
slv_reg29 => slv_reg29_internal,
slv_reg30 => slv_reg30,
slv_reg31 => slv_reg31,
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
Audio_Left_in => Audio_Left_in,
Audio_Right_in => Audio_Right_in,
SAMPLE_TRIG => SAMPLE_TRIG,
slv_reg0 => slv_reg0,
slv_reg1 => slv_reg1,
slv_reg2 => slv_reg2,
slv_reg3 => slv_reg3,
slv_reg4 => slv_reg4,
slv_reg5 => slv_reg5,
slv_reg6 => slv_reg6,
slv_reg7 => slv_reg7,
slv_reg8 => slv_reg8,
slv_reg9 => slv_reg9,
slv_reg10 => slv_reg10,
slv_reg11 => slv_reg11,
slv_reg12 => slv_reg12,
slv_reg13 => slv_reg13,
slv_reg14 => slv_reg14,
slv_reg15 => slv_reg15,
slv_reg16 => slv_reg16,
slv_reg17 => slv_reg17,
slv_reg18 => slv_reg18,
slv_reg19 => slv_reg19,
slv_reg20 => slv_reg20,
slv_reg21 => slv_reg21,
slv_reg22 => slv_reg22,
slv_reg23 => slv_reg23,
slv_reg24 => slv_reg24,
slv_reg25 => slv_reg25,
slv_reg27 => slv_reg27
);
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
| mit | 68c5644ed7ef0498cbda448254bffa8b | 0.553542 | 3.313841 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_pkg.vhd | 1 | 11,634 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE rd_fifo_256to64_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT rd_fifo_256to64_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rd_fifo_256to64_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rd_fifo_256to64_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT rd_fifo_256to64_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rd_fifo_256to64_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT rd_fifo_256to64_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(12-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END rd_fifo_256to64_pkg;
PACKAGE BODY rd_fifo_256to64_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END rd_fifo_256to64_pkg;
| gpl-2.0 | 43785c5ce38a53d9fd48f3bf1e3fce73 | 0.506704 | 3.902717 | false | false | false | false |
peteut/nvc | test/regress/issue340.vhd | 2 | 1,113 | entity submodule is
port (
sig : in bit);
end entity;
architecture a of submodule is
begin
main : process
begin
wait for 1 ns;
assert sig = '1';
report "Success";
wait;
end process;
end;
entity issue340 is
end entity;
architecture a of issue340 is
signal sig_vector : bit_vector(0 to 1) := "00";
alias sig_bit_alias : bit is sig_vector(0);
signal sig : bit := '0';
alias sig_alias : bit is sig;
procedure drive(signal value : out bit) is
begin
value <= '1';
end;
begin
main : process
begin
drive(sig_alias);
drive(sig_bit_alias);
wait for 1 ns;
assert sig_vector(0) = '1';
assert sig = '1';
assert sig_alias = '1';
assert sig_bit_alias = '1';
report "Success";
wait;
end process;
submodule0_inst : entity work.submodule
port map (
sig => sig_alias);
submodule1_inst : entity work.submodule
port map (
sig => sig_bit_alias);
submodule2_inst : entity work.submodule
port map (
sig => sig);
submodule3_inst : entity work.submodule
port map (
sig => sig_vector(0));
end;
| gpl-3.0 | 7c962ac10a68764bada75e7e5f86cdbe | 0.61186 | 3.44582 | false | false | false | false |
peteut/nvc | test/regress/signal14.vhd | 2 | 672 | package pack is
signal reset : bit := '1';
end package;
-------------------------------------------------------------------------------
entity buf is
port (
i : in bit;
o : out bit );
end entity;
architecture behav of buf is
begin
o <= i after 1 ns;
end architecture;
entity signal14 is
end entity;
use work.pack.all;
architecture test of signal14 is
signal reset_o : bit;
begin
u1: entity work.buf
port map (
i => reset,
o => reset_o );
process is
begin
assert reset_o = '0';
wait for 2 ns;
assert reset_o = '1';
wait;
end process;
end architecture;
| gpl-3.0 | 99902a0f1842a5871eebe13ae6bd68f2 | 0.491071 | 4.023952 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/ip/ocxo_clk_pll/ocxo_clk_pll_clk_wiz.vhd | 1 | 7,297 | -- file: ocxo_clk_pll_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___100.000______0.000______50.0______597.520____892.144
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary__________10.000___________0.00100
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity ocxo_clk_pll_clk_wiz is
port
(-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end ocxo_clk_pll_clk_wiz;
architecture xilinx of ocxo_clk_pll_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_in1_ocxo_clk_pll : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_ocxo_clk_pll : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_out1_ocxo_clk_pll : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
signal reset_high : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_ibufg : IBUF
port map
(O => clk_in1_ocxo_clk_pll,
I => clk_in1);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 63.750,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 6.375,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 100.0)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_ocxo_clk_pll,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_out1_ocxo_clk_pll,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_ocxo_clk_pll,
CLKIN1 => clk_in1_ocxo_clk_pll,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => reset_high);
reset_high <= not resetn;
locked <= locked_int;
-- Output buffering
-------------------------------------
clk_out1 <= clk_out1_ocxo_clk_pll;
end xilinx;
| gpl-3.0 | de574e819d54ee3210dae4fc509dc528 | 0.571331 | 4.230145 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/prediction.vhd | 1 | 853 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.custom_pkg.all;
entity prediction is
port (clk : in std_logic;
enable : in std_logic;
output_hid : in eight_bit(num_neurons-1 downto 0);
predict : out std_logic_vector(7 downto 0)
);
end prediction;
architecture Behavioral of prediction is
begin
process (clk, enable, output_hid)
variable biggest : std_logic_vector(7 downto 0);
variable count : Integer;
begin
if enable = '0' then
biggest := (others=>'0');
count := 0;
else
if rising_edge(clk) then
if count < num_neurons then
if signed(output_hid(count)) > signed(biggest) then
biggest := output_hid(count);
end if;
count := count + 1;
end if;
end if;
end if;
predict <= biggest;
end process;
end Behavioral;
| bsd-2-clause | 4105776563afba95b509dabbc93dcf6b | 0.661196 | 3.057348 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/rx_usDMA_Channel.vhd | 1 | 26,155 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity usDMA_Transact is
port (
-- Around the Channel Buffer
usTlp_Req : OUT std_logic;
usTlp_RE : IN std_logic;
usTlp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : IN std_logic;
us_Last_sof : IN std_logic;
us_Last_eof : IN std_logic;
FIFO_Data_Count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
FIFO_Reading : IN std_logic;
-- Upstream reset from MWr channel
usDMA_Channel_Rst : IN std_logic;
-- Upstream Registers from MWr Channel
DMA_us_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : IN std_logic;
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
-- Calculation in advance, for better timing
usHA_is_64b : IN std_logic;
usBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : IN std_logic;
usLeng_Lo7b_True : IN std_logic;
-- from Cpl/D channel
usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Upstream Control Signals from MWr Channel
usDMA_Start : IN std_logic; -- out of 1st dex
usDMA_Stop : IN std_logic; -- out of 1st dex
-- Upstream Control Signals from CplD Channel
usDMA_Start2 : IN std_logic; -- out of consecutive dex
usDMA_Stop2 : IN std_logic; -- out of consecutive dex
-- Upstream DMA Acknowledge to the start command
DMA_Cmd_Ack : OUT std_logic;
-- To Interrupt module
DMA_Done : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
-- To Registers' Group
DMA_us_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- Common ports
trn_clk : IN std_logic
);
end entity usDMA_Transact;
architecture Behavioral of usDMA_Transact is
-- Upstream DMA channel
signal Local_Reset_i : std_logic;
signal DMA_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal cfg_MPS : std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
signal usDMA_MWr_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- DMA calculation
COMPONENT DMA_Calculate
PORT(
-- Downstream Registers from MWr Channel
DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : IN std_logic;
BDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : IN std_logic;
Leng_Lo7b_True : IN std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : OUT std_logic;
-- Only for downstream channel
DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : OUT std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
--
DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Engine control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : OUT std_logic;
ThereIs_Snout : OUT std_logic;
ThereIs_Body : OUT std_logic;
ThereIs_Tail : OUT std_logic;
ThereIs_Dex : OUT std_logic;
HA64bit : OUT std_logic;
Addr_Inc : OUT std_logic;
-- FSM indicators
State_Is_LoadParam : IN std_logic;
State_Is_Snout : IN std_logic;
State_Is_Body : IN std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : IN std_logic_vector(2 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
END COMPONENT;
signal usDMA_PA_Loaded : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_PA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_HA_Var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_BDA_fsm : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usBDA_is_64b_fsm : std_logic;
signal usDMA_PA_snout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_BAR_Number : std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
signal usDMA_Snout_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal usDMA_Body_Length : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal usDMA_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal usNo_More_Bodies : std_logic;
signal usThereIs_Snout : std_logic;
signal usThereIs_Body : std_logic;
signal usThereIs_Tail : std_logic;
signal usThereIs_Dex : std_logic;
signal usHA64bit : std_logic;
signal us_AInc : std_logic;
-- DMA state machine
COMPONENT DMA_FSM
PORT(
-- Fixed information for 1st header of TLP: MRd/MWr
TLP_Has_Payload : IN std_logic;
TLP_Hdr_is_4DW : IN std_logic;
DMA_Addr_Inc : IN std_logic;
DMA_BAR_Number : IN std_logic_vector(C_TAGBAR_BIT_TOP-C_TAGBAR_BIT_BOT downto 0);
-- FSM control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic;
DMA_Stop : IN std_logic;
DMA_Stop2 : IN std_logic;
No_More_Bodies : IN std_logic;
ThereIs_Snout : IN std_logic;
ThereIs_Body : IN std_logic;
ThereIs_Tail : IN std_logic;
ThereIs_Dex : IN std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : IN std_logic;
DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : IN std_logic;
Done_Condition_2 : IN std_logic;
Done_Condition_3 : IN std_logic;
Done_Condition_4 : IN std_logic;
Done_Condition_5 : IN std_logic;
-- Channel buffer write
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
ChBuf_aFull : IN std_logic;
ChBuf_WrEn : OUT std_logic;
ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : OUT std_logic;
State_Is_Snout : OUT std_logic;
State_Is_Body : OUT std_logic;
State_Is_Tail : OUT std_logic;
DMA_Cmd_Ack : OUT std_logic;
-- To Tx Port
ChBuf_ValidRd : IN std_logic;
BDA_nAligned : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
DMA_Done : OUT std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
END COMPONENT;
-- FSM state indicators
signal usState_Is_LoadParam : std_logic;
signal usState_Is_Snout : std_logic;
signal usState_Is_Body : std_logic;
signal usState_Is_Tail : std_logic;
signal usChBuf_ValidRd : std_logic;
signal usBDA_nAligned : std_logic;
signal usDMA_TimeOut_i : std_logic;
signal usDMA_Busy_i : std_logic;
signal usDMA_Done_i : std_logic;
-- Built-in single-port fifo as downstream DMA channel buffer
-- 128-bit wide, for 64-bit address
component k7_sfifo_15x128
port (
clk : IN std_logic;
rst : IN std_logic;
prog_full : OUT std_logic;
-- wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : OUT std_logic;
-- rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic
);
end component;
-- Signal with DMA_upstream channel abstract buffer
signal usTlp_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal usTlp_RE_i : std_logic;
signal usTlp_RE_i_r1 : std_logic;
signal usTlp_we : std_logic;
signal usTlp_empty_i : std_logic;
signal usTlp_full : std_logic;
signal usTlp_prog_Full : std_logic;
signal usTlp_pempty : std_logic;
signal usTlp_Npempty_r1 : std_logic;
signal usTlp_Nempty_r1 : std_logic;
signal usTlp_empty_r1 : std_logic;
signal usTlp_empty_r2 : std_logic;
signal usTlp_empty_r3 : std_logic;
signal usTlp_empty_r4 : std_logic;
signal usTlp_prog_Full_r1 : std_logic;
-- Request for output arbitration
signal usTlp_Req_i : std_logic;
signal usTlp_nReq_r1 : std_logic;
signal FIFO_Reading_r1 : std_logic;
signal FIFO_Reading_r2 : std_logic;
signal FIFO_Reading_r3p : std_logic;
signal usTlp_MWr_Leng : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
-- Busy/Done state bits generation
type FSM_Request is (
REQST_Idle
, REQST_1Read
, REQST_Decision
, REQST_nFIFO_Req
, REQST_Quantity
, REQST_FIFO_Req
);
signal FSM_REQ_us : FSM_Request;
begin
-- DMA done signal
DMA_Done <= usDMA_Done_i;
DMA_TimeOut <= usDMA_TimeOut_i;
DMA_Busy <= usDMA_Busy_i;
-- connecting FIFO's signals
usTlp_Qout <= usTlp_Qout_i;
usTlp_Req <= usTlp_Req_i and not FIFO_Reading_r3p;
-- positive local reset
Local_Reset_i <= usDMA_Channel_Rst;
-- Max Payload Size bits
cfg_MPS <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
-- Kernel Engine
us_DMA_Calculation:
DMA_Calculate
PORT MAP(
DMA_PA => DMA_us_PA ,
DMA_HA => DMA_us_HA ,
DMA_BDA => DMA_us_BDA ,
DMA_Length => DMA_us_Length ,
DMA_Control => DMA_us_Control ,
HA_is_64b => usHA_is_64b ,
BDA_is_64b => usBDA_is_64b ,
Leng_Hi19b_True => usLeng_Hi19b_True ,
Leng_Lo7b_True => usLeng_Lo7b_True ,
DMA_PA_Loaded => usDMA_PA_Loaded ,
DMA_PA_Var => usDMA_PA_Var ,
DMA_HA_Var => usDMA_HA_Var ,
DMA_BDA_fsm => usDMA_BDA_fsm ,
BDA_is_64b_fsm => usBDA_is_64b_fsm ,
-- Only for downstream channel
DMA_PA_Snout => usDMA_PA_snout ,
DMA_BAR_Number => usDMA_BAR_Number ,
-- Lengths
DMA_Snout_Length => usDMA_Snout_Length ,
DMA_Body_Length => usDMA_Body_Length ,
DMA_Tail_Length => usDMA_Tail_Length ,
-- Control signals to FSM
No_More_Bodies => usNo_More_Bodies ,
ThereIs_Snout => usThereIs_Snout ,
ThereIs_Body => usThereIs_Body ,
ThereIs_Tail => usThereIs_Tail ,
ThereIs_Dex => usThereIs_Dex ,
HA64bit => usHA64bit ,
Addr_Inc => us_AInc ,
DMA_Start => usDMA_Start ,
DMA_Start2 => usDMA_Start2 ,
State_Is_LoadParam => usState_Is_LoadParam ,
State_Is_Snout => usState_Is_Snout ,
State_Is_Body => usState_Is_Body ,
-- State_Is_Tail => usState_Is_Tail ,
Param_Max_Cfg => cfg_MPS ,
dma_clk => trn_clk ,
dma_reset => Local_Reset_i
);
-- Kernel FSM
us_DMA_StateMachine:
DMA_FSM
PORT MAP(
TLP_Has_Payload => '1' ,
TLP_Hdr_is_4DW => usHA64bit ,
DMA_Addr_Inc => us_AInc ,
DMA_BAR_Number => usDMA_BAR_Number ,
DMA_Start => usDMA_Start ,
DMA_Start2 => usDMA_Start2 ,
DMA_Stop => usDMA_Stop ,
DMA_Stop2 => usDMA_Stop2 ,
-- Control signals to FSM
No_More_Bodies => usNo_More_Bodies ,
ThereIs_Snout => usThereIs_Snout ,
ThereIs_Body => usThereIs_Body ,
ThereIs_Tail => usThereIs_Tail ,
ThereIs_Dex => usThereIs_Dex ,
DMA_PA_Loaded => usDMA_PA_Loaded ,
DMA_PA_Var => usDMA_PA_Var ,
DMA_HA_Var => usDMA_HA_Var ,
DMA_BDA_fsm => usDMA_BDA_fsm ,
BDA_is_64b_fsm => usBDA_is_64b_fsm ,
DMA_Snout_Length => usDMA_Snout_Length ,
DMA_Body_Length => usDMA_Body_Length ,
DMA_Tail_Length => usDMA_Tail_Length ,
ChBuf_ValidRd => usChBuf_ValidRd ,
BDA_nAligned => usBDA_nAligned ,
DMA_TimeOut => usDMA_TimeOut_i ,
DMA_Busy => usDMA_Busy_i ,
DMA_Done => usDMA_Done_i ,
-- DMA_Done_Rise => open ,
Pkt_Tag => usDMA_MWr_Tag ,
Dex_Tag => usDMA_dex_Tag ,
Done_Condition_1 => '1' ,
Done_Condition_2 => usTlp_empty_r3 ,
Done_Condition_3 => usTlp_nReq_r1 ,
Done_Condition_4 => us_Last_sof ,
Done_Condition_5 => us_Last_eof ,
us_MWr_Param_Vec => us_MWr_Param_Vec ,
ChBuf_aFull => usTlp_Npempty_r1 , -- usTlp_prog_Full_r1 ,
ChBuf_WrEn => usTlp_we ,
ChBuf_WrDin => usTlp_din ,
State_Is_LoadParam => usState_Is_LoadParam ,
State_Is_Snout => usState_Is_Snout ,
State_Is_Body => usState_Is_Body ,
State_Is_Tail => usState_Is_Tail ,
DMA_Cmd_Ack => DMA_Cmd_Ack ,
dma_clk => trn_clk ,
dma_reset => Local_Reset_i
);
usChBuf_ValidRd <= usTlp_RE; -- usTlp_RE_i and not usTlp_empty_i;
-- -------------------------------------------------
--
DMA_us_Status <= DMA_Status_i;
--
-- Synchronous output: DMA_Status_i
--
US_DMA_Status_Concat:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DMA_Status_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
DMA_Status_i <= (
CINT_BIT_DMA_STAT_NALIGN => usBDA_nAligned,
CINT_BIT_DMA_STAT_TIMEOUT => usDMA_TimeOut_i,
CINT_BIT_DMA_STAT_BDANULL => usDMA_BDA_eq_Null,
CINT_BIT_DMA_STAT_BUSY => usDMA_Busy_i,
CINT_BIT_DMA_STAT_DONE => usDMA_Done_i,
Others => '0'
);
end if;
end process;
-- -----------------------------------
-- Synchronous Register: usDMA_MWr_Tag
FSM_usDMA_usDMA_MWr_Tag:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
usDMA_MWr_Tag <= C_TAG0_DMA_US_MWR;
elsif trn_clk'event and trn_clk = '1' then
if usState_Is_Snout='1'
or usState_Is_Body='1'
or usState_Is_Tail='1'
then
-- Only 4 lower bits increment, higher 4 stay
usDMA_MWr_Tag(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)
<= usDMA_MWr_Tag(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0)
+ CONV_STD_LOGIC_VECTOR(1, C_TAG_WIDTH-C_TAG_DECODE_BITS);
else
usDMA_MWr_Tag <= usDMA_MWr_Tag;
end if;
end if;
end process;
-- -------------------------------------------------
-- us MWr/MRd TLP Buffer
-- -------------------------------------------------
US_TLP_Buffer:
k7_sfifo_15x128
port map (
clk => trn_clk,
rst => Local_Reset_i,
prog_full => usTlp_prog_Full ,
-- wr_clk => trn_clk,
wr_en => usTlp_we,
din => usTlp_din,
full => usTlp_full,
-- rd_clk => trn_clk,
rd_en => usTlp_RE_i,
dout => usTlp_Qout_wire,
prog_empty => usTlp_pempty,
empty => usTlp_empty_i
);
-- ---------------------------------------------
-- Synchronous delay
--
Synch_Delay_ren_Qout:
process (Local_Reset_i, trn_clk )
begin
if Local_Reset_i = '1' then
FIFO_Reading_r1 <= '0';
FIFO_Reading_r2 <= '0';
FIFO_Reading_r3p<= '0';
usTlp_RE_i_r1 <= '0';
usTlp_nReq_r1 <= '0';
usTlp_Qout_reg <= (OTHERS=>'0');
usTlp_MWr_Leng <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
FIFO_Reading_r1 <= FIFO_Reading;
FIFO_Reading_r2 <= FIFO_Reading_r1;
FIFO_Reading_r3p<= FIFO_Reading_r1 or FIFO_Reading_r2;
usTlp_RE_i_r1 <= usTlp_RE_i;
usTlp_nReq_r1 <= not usTlp_Req_i;
if usTlp_RE_i_r1='1' then
usTlp_Qout_reg <= usTlp_Qout_wire;
usTlp_MWr_Leng <= usTlp_Qout_wire(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
else
usTlp_Qout_reg <= usTlp_Qout_reg;
usTlp_MWr_Leng <= usTlp_MWr_Leng;
end if;
end if;
end process;
-- ---------------------------------------------
-- Request for arbitration
--
Synch_Req_Proc:
process (Local_Reset_i, trn_clk )
begin
if Local_Reset_i = '1' then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
elsif trn_clk'event and trn_clk = '1' then
case FSM_REQ_us is
when REQST_IDLE =>
if usTlp_empty_i = '0' then
usTlp_RE_i <= '1';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_1Read;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
end if;
when REQST_1Read =>
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Decision;
when REQST_Decision =>
if usTlp_Qout_wire(C_CHBUF_FMT_BIT_TOP) = '1' -- Has Payload
and usTlp_Qout_wire(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT)
=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_nFIFO_Req;
end if;
when REQST_nFIFO_Req =>
if usTlp_RE = '1' then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_nFIFO_Req;
end if;
when REQST_Quantity =>
if usTlp_RE = '1' then
usTlp_RE_i <= '1';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
elsif FIFO_Data_Count(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)=C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)
and FIFO_Data_Count(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) < usTlp_MWr_Leng(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_FIFO_Req;
end if;
when REQST_FIFO_Req =>
if FIFO_Data_Count(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)=C_ALL_ZEROS(C_FIFO_DC_WIDTH downto C_TLP_FLD_WIDTH_OF_LENG)
and FIFO_Data_Count(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) < usTlp_MWr_Leng(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)
then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_Quantity;
elsif usTlp_RE = '1' then
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
else
usTlp_RE_i <= '0';
usTlp_Req_i <= not usDMA_Stop
and not usDMA_Stop2
and not us_FC_stop;
FSM_REQ_us <= REQST_FIFO_Req;
end if;
when OTHERS =>
usTlp_RE_i <= '0';
usTlp_Req_i <= '0';
FSM_REQ_us <= REQST_IDLE;
end case;
end if;
end process;
-- ---------------------------------------------
-- Sending usTlp_Qout
--
Synch_usTlp_Qout:
process (Local_Reset_i, trn_clk )
begin
if Local_Reset_i = '1' then
usTlp_Qout_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if usTlp_RE = '1' then
usTlp_Qout_i <= usTlp_Qout_reg;
else
usTlp_Qout_i <= usTlp_Qout_i;
end if;
end if;
end process;
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
usTlp_Npempty_r1 <= not usTlp_pempty;
usTlp_Nempty_r1 <= not usTlp_empty_i;
usTlp_empty_r1 <= usTlp_empty_i;
usTlp_empty_r2 <= usTlp_empty_r1;
usTlp_empty_r3 <= usTlp_empty_r2;
usTlp_empty_r4 <= usTlp_empty_r3;
usTlp_prog_Full_r1 <= usTlp_prog_Full;
-- usTlp_Req_i <= not usTlp_empty_i
-- and not usDMA_Stop
-- and not usDMA_Stop2
-- and not us_FC_stop
-- ;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | 5610709f736b1488ddd481fcd12ddba5 | 0.491799 | 3.531596 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/axi_i2s_adi.vhd | 3 | 18,754 | ------------------------------------------------------------------------------
-- axi_i2s_adi.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: axi_i2s_adi.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Thu Apr 26 17:49:16 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library axi_i2s_adi_v1_00_a;
use axi_i2s_adi_v1_00_a.user_logic;
Library UNISIM;
use UNISIM.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH --
-- C_S_AXI_ADDR_WIDTH --
-- C_S_AXI_MIN_SIZE --
-- C_USE_WSTRB --
-- C_DPHASE_TIMEOUT --
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY --
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK --
-- S_AXI_ARESETN --
-- S_AXI_AWADDR --
-- S_AXI_AWVALID --
-- S_AXI_WDATA --
-- S_AXI_WSTRB --
-- S_AXI_WVALID --
-- S_AXI_BREADY --
-- S_AXI_ARADDR --
-- S_AXI_ARVALID --
-- S_AXI_RREADY --
-- S_AXI_ARREADY --
-- S_AXI_RDATA --
-- S_AXI_RRESP --
-- S_AXI_RVALID --
-- S_AXI_WREADY --
-- S_AXI_BRESP --
-- S_AXI_BVALID --
-- S_AXI_AWREADY --
------------------------------------------------------------------------------
entity axi_i2s_adi is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
C_DATA_WIDTH : integer := 24;
C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first)
C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode)
C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge)
C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge)
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
BCLK_O : out std_logic;
LRCLK_O : out std_logic;
SDATA_I : in std_logic;
SDATA_O : out std_logic;
-- MEM_RD_O for debugging
MEM_RD_O : out std_logic;
--
ACLK : in std_logic;
ARESETN : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TDATA : in std_logic_vector(31 downto 0);
S_AXIS_TLAST : in std_logic;
S_AXIS_TVALID : in std_logic;
M_AXIS_ACLK : in std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TDATA : out std_logic_vector(31 downto 0);
M_AXIS_TLAST : out std_logic;
M_AXIS_TVALID : out std_logic;
M_AXIS_TKEEP : out std_logic_vector(3 downto 0);
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of ACLK : signal is "CLK";
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity axi_i2s_adi;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of axi_i2s_adi is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 12;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
-- bufg
signal LRCLK_BUFG_I : std_logic;
signal BCLK_BUFG_I : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity axi_i2s_adi_v1_00_a.user_logic
generic map
(
C_MSB_POS => C_MSB_POS,
C_FRM_SYNC => C_FRM_SYNC,
C_LRCLK_POL => C_LRCLK_POL,
C_BCLK_POL => C_BCLK_POL,
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => C_DATA_WIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
BCLK_O => BCLK_BUFG_I,
LRCLK_O => LRCLK_BUFG_I,
SDATA_I => SDATA_I,
SDATA_O => SDATA_O,
-- debug only
MEM_RD_O => MEM_RD_O,
--
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
S_AXIS_ACLK => ACLK,
S_AXIS_TREADY => S_AXIS_TREADY,
S_AXIS_TDATA => S_AXIS_TDATA,
S_AXIS_TLAST => S_AXIS_TLAST,
S_AXIS_TVALID => S_AXIS_TVALID,
M_AXIS_ACLK => M_AXIS_ACLK,
M_AXIS_TREADY => M_AXIS_TREADY,
M_AXIS_TDATA => M_AXIS_TDATA,
M_AXIS_TLAST => M_AXIS_TLAST,
M_AXIS_TVALID => M_AXIS_TVALID,
M_AXIS_TKEEP => M_AXIS_TKEEP
);
----- bufg
BUFG_inst_BCLK : BUFG
port map (
O => LRCLK_O, -- 1-bit Clock buffer output
I => LRCLK_BUFG_I -- 1-bit Clock buffer input
);
BUFG_inst_LRCLK : BUFG
port map (
O => BCLK_O, -- 1-bit Clock buffer output
I => BCLK_BUFG_I -- 1-bit Clock buffer input
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 308c525363a39de9c0d9b64d7426ed90 | 0.433774 | 3.952371 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/test_image.vhd | 1 | 5,604 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file test_image.vhd when simulating
-- the core, test_image. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY test_image IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END test_image;
ARCHITECTURE test_image_a OF test_image IS
-- synthesis translate_off
COMPONENT wrapped_test_image
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_test_image USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "artix7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "test_image.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 230,
c_read_depth_b => 230,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 230,
c_write_depth_b => 230,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_test_image
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END test_image_a;
| bsd-2-clause | 961ba654e91d1b2d6a167c4483945bc6 | 0.531585 | 3.946479 | false | true | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/filter_v1_00_a/hdl/vhdl/IIR_Biquad_II.vhd | 3 | 22,254 | --////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II is
Generic(
Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"
);
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (15 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end IIR_Biquad_II;
architecture arch of IIR_Biquad_II is
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients --WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1101_1101_1011_0000_1001"; -- b0 ~ +0.999869117
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0000_0101_0100_1100_1000_1010"; -- b1 ~ -1.999676575
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1101_1101_1011_0000_1001"; -- b2 ~ +0.999869117
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0000_0101_0100_1100_1000_1010"; -- a1 ~ -1.999676575
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1011_1011_0110_0001_0011"; -- a2 ~ +0.999738235
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- band pass 2nd order elliptical fl= 7200Hz, fu = 7400Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b0 ~ +0.9944543
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- b1 ~ -1.1479874
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b2 ~ +0.9944543
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- a1 ~ -1.1479874
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_0100_1010_0100_0111_0100_1011"; -- a2 ~ +0.9889086
-- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients -- WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
--
-- -- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk, rst, Y_out_double, sample_trig)
begin
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk)) then
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(15) & X_in(15) & X_in(15) & X_in(15) & X_in & B"0000_0000_0000"; -- X_in(17) & X_in(17) & X_in & B"0000_0000_0000";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk, rst)
begin
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk)) then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk) then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(61 downto 30);
pgZFF_X2 <= pgZFF_X2_quad(61 downto 30);
pgZFF_X1 <= pgZFF_X1_quad(61 downto 30);
pgZFF_Y1 <= pgZFF_Y1_quad(61 downto 30);
pgZFF_Y2 <= pgZFF_Y2_quad(61 downto 30);
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk, sum_stg_a)
begin
if(rising_edge(clk)) then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end process;
-- output truncation block
process(clk, trunc_out)
begin
if rising_edge(clk) then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 15);
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- band pass 2nd order elliptical fl= 7200Hz, fu = 7400Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b0 ~ +0.9944543
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- b1 ~ -1.1479874
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b2 ~ +0.9944543
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- a1 ~ -1.1479874
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_0100_1010_0100_0111_0100_1011"; -- a2 ~ +0.9889086
-- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
--
-- -- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272 | mit | 416b3655da0dc23690dcd27e7d75aa1b | 0.509122 | 2.771012 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_10/lab10_1/lpm_rom0.vhd | 1 | 6,380 | -- megafunction wizard: %LPM_ROM%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_rom0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_rom0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
inclock : IN STD_LOGIC := '1';
outclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END lpm_rom0;
ARCHITECTURE SYN OF lpm_rom0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (9 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
address_aclr_a : STRING;
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
clock0 : IN STD_LOGIC ;
clock1 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (5 DOWNTO 0);
q_a : OUT STD_LOGIC_VECTOR (9 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(9 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_aclr_a => "NONE",
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "lab10_1.mif",
intended_device_family => "Cyclone III",
lpm_type => "altsyncram",
numwords_a => 64,
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK1",
widthad_a => 6,
width_a => 10,
width_byteena_a => 1
)
PORT MAP (
clock0 => inclock,
clock1 => outclock,
address_a => address,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "lab10_1.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "64"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "0"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "6"
-- Retrieval info: PRIVATE: WidthData NUMERIC "10"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "lab10_1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "64"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK1"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "6"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 6 0 INPUT NODEFVAL address[5..0]
-- Retrieval info: USED_PORT: inclock 0 0 0 0 INPUT VCC inclock
-- Retrieval info: USED_PORT: outclock 0 0 0 0 INPUT NODEFVAL outclock
-- Retrieval info: USED_PORT: q 0 0 10 0 OUTPUT NODEFVAL q[9..0]
-- Retrieval info: CONNECT: @address_a 0 0 6 0 address 0 0 6 0
-- Retrieval info: CONNECT: q 0 0 10 0 @q_a 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 inclock 0 0 0 0
-- Retrieval info: CONNECT: @clock1 0 0 0 0 outclock 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_rom0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 46fe666b55354c9f02ef965189e1720e | 0.670846 | 3.522916 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_pctrl.vhd | 1 | 18,582 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.wr_fifo32to256_pkg.ALL;
ENTITY wr_fifo32to256_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF wr_fifo32to256_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:wr_fifo32to256_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:wr_fifo32to256_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | 506fce6b389cfd380ceb695feccc8d1a | 0.509687 | 3.237282 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain.vhd | 1 | 10,367 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_prime_fifo_plain.vhd when simulating
-- the core, k7_prime_fifo_plain. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_prime_fifo_plain IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END k7_prime_fifo_plain;
ARCHITECTURE k7_prime_fifo_plain_a OF k7_prime_fifo_plain IS
-- synthesis translate_off
COMPONENT wrapped_k7_prime_fifo_plain
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_prime_fifo_plain USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 6,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 4,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 5,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 6,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 496,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 495,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 9,
c_rd_depth => 512,
c_rd_freq => 125,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 9,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 125,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_prime_fifo_plain
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
END k7_prime_fifo_plain_a;
| gpl-2.0 | ad8a7e2fb6b9b0a80d5b70ae333b0bcb | 0.538922 | 3.311083 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | tb/memory_tb.vhd | 1 | 875 | library IEEE;
use IEEE.std_logic_1164.all;
entity MEMORY_TB is
end entity;
architecture MEMORY_TB_ARCH of MEMORY_TB is
signal clock : std_logic := '0';
signal we : std_logic;
signal datain, dataout : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0);
component MEMORY is
port (
clock : in std_logic;
we : in std_logic;
address : in std_logic_vector(7 downto 0);
datain : in std_logic_vector(15 downto 0);
dataout : out std_logic_vector(15 downto 0)
);
end component;
begin
memoryIns : MEMORY port map(clock, we, address, datain, dataout);
clock <= not clock after 100 ns;
we <= '0', '1' after 90 ns, '0' after 600 ns;
address <= (OTHERS => '0');
datain <= (OTHERS => '0'), "0000000000000001" after 300 ns, (OTHERS => '0') after 450 ns;
end architecture; | gpl-3.0 | d585bd61e55d9bb7d0882ea93c519be3 | 0.626286 | 3.431373 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_out/simulation/weight_out_synth.vhd | 1 | 7,904 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_out_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY weight_out_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE weight_out_synth_ARCH OF weight_out_synth IS
COMPONENT weight_out_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(319 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 320,
READ_WIDTH => 320 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: weight_out_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| bsd-2-clause | 2c87b44038a56a3784a62c83aea24dc3 | 0.565789 | 3.778203 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_pkg.vhd | 1 | 11,363 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fifo8to32_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fifo8to32_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo8to32_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo8to32_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fifo8to32_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo8to32_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fifo8to32_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(16-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fifo8to32_pkg;
PACKAGE BODY fifo8to32_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fifo8to32_pkg;
| gpl-2.0 | 40691851d07c5efd5bfc1176c2ddc690 | 0.506468 | 3.925043 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/ram_16x1k_sp_tb.vhd | 1 | 4,240 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ram_16x1k_sp_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ram_16x1k_sp_tb IS
END ENTITY;
ARCHITECTURE ram_16x1k_sp_tb_ARCH OF ram_16x1k_sp_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ram_16x1k_sp_synth_inst:ENTITY work.ram_16x1k_sp_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-3-clause | 356093d0ff5dcd32f67d264b26f398e5 | 0.619104 | 4.520256 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/bram_DDRs_Control_Loopback.vhd | 1 | 44,671 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bram_DDRs_Control_loopback is
Generic (
C_ASYNFIFO_WIDTH : integer := 72 ;
P_SIMULATION : boolean := TRUE
);
Port (
-- -- Pins
-- DDR_CLKn : OUT std_logic;
-- DDR_CLK : OUT std_logic;
-- DDR_CKE : OUT std_logic;
-- DDR_CSn : OUT std_logic;
-- DDR_RASn : OUT std_logic;
-- DDR_CASn : OUT std_logic;
-- DDR_WEn : OUT std_logic;
-- DDR_BankAddr : OUT std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
-- DDR_Addr : OUT std_logic_vector(C_DDR_AWIDTH-1 downto 0);
-- DDR_DM : OUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DDR_DQ : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
-- DDR_DQS : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DMA interface
DDR_wr_sof : IN std_logic;
DDR_wr_eof : IN std_logic;
DDR_wr_v : IN std_logic;
DDR_wr_FA : IN std_logic;
DDR_wr_Shift : IN std_logic;
DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : OUT std_logic;
DDR_rdc_sof : IN std_logic;
DDR_rdc_eof : IN std_logic;
DDR_rdc_v : IN std_logic;
DDR_rdc_FA : IN std_logic;
DDR_rdc_Shift : IN std_logic;
DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : OUT std_logic;
-- DDR_rdD_sof : OUT std_logic;
-- DDR_rdD_eof : OUT std_logic;
-- DDR_rdDout_V : OUT std_logic;
-- DDR_rdDout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : IN std_logic;
DDR_FIFO_Empty : OUT std_logic;
DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : OUT std_logic;
DDR_blinker : OUT std_logic;
Sim_Zeichen : OUT std_logic;
mem_clk : IN std_logic;
trn_clk : IN std_logic;
trn_reset_n : IN std_logic
);
end entity bram_DDRs_Control_loopback;
architecture Behavioral of bram_DDRs_Control_loopback is
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
COMPONENT DDR_ClkGen
PORT(
ddr_Clock : OUT std_logic;
ddr_Clock_n : OUT std_logic;
ddr_Clock90 : OUT std_logic;
ddr_Clock90_n : OUT std_logic;
Clk_ddr_rddata : OUT std_logic;
Clk_ddr_rddata_n : OUT std_logic;
ddr_DCM_locked : OUT std_logic;
clk_in : IN std_logic;
trn_reset_n : IN std_logic
);
END COMPONENT;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
COMPONENT asyn_rw_FIFO72
-- GENERIC (
-- OUTPUT_REGISTERED : BOOLEAN
-- );
PORT(
wClk : IN std_logic;
wEn : IN std_logic;
Din : IN std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aFull : OUT std_logic;
Full : OUT std_logic;
rClk : IN std_logic;
rEn : IN std_logic;
Qout : OUT std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aEmpty : OUT std_logic;
Empty : OUT std_logic;
Rst : IN std_logic
);
END COMPONENT;
component k7_prime_FIFO_plain
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
full : OUT std_logic;
prog_full: OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
empty : OUT std_logic;
rst : IN std_logic
);
end component;
-- component fifo_512x36_v4_2
-- port (
-- wr_clk : IN std_logic;
-- wr_en : IN std_logic;
-- din : IN std_logic_VECTOR(35 downto 0);
-- prog_full : OUT std_logic;
-- full : OUT std_logic;
--
-- rd_clk : IN std_logic;
-- rd_en : IN std_logic;
-- dout : OUT std_logic_VECTOR(35 downto 0);
-- prog_empty : OUT std_logic;
-- empty : OUT std_logic;
--
-- rst : IN std_logic
-- );
-- end component;
component fifo_512x72_v4_4
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
-- prog_empty : OUT std_logic;
empty : OUT std_logic;
rst : IN std_logic
);
end component;
---- Dual-port block RAM for packets
--- Core output registered
--
-- component v5bram4096x32
-- port (
-- clka : IN std_logic;
-- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- wea : IN std_logic_vector(0 downto 0);
-- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
-- clkb : IN std_logic;
-- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- web : IN std_logic_vector(0 downto 0);
-- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- );
-- end component;
component k7_bram4096x64
port (
clka : IN std_logic;
addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
wea : IN std_logic_vector(7 downto 0);
dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
clkb : IN std_logic;
addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
web : IN std_logic_vector(7 downto 0);
dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- Blinking -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
COMPONENT DDR_Blink
PORT(
DDR_Blinker : OUT std_logic;
DDR_Write : IN std_logic;
DDR_Read : IN std_logic;
DDR_Both : IN std_logic;
ddr_Clock : IN std_logic;
DDr_Rst_n : IN std_logic
);
END COMPONENT;
-- ---------------------------------------------------------------------
signal ddr_DCM_locked : std_logic;
-- -- ---------------------------------------------------------------------
signal Rst_i : std_logic;
-- -- ---------------------------------------------------------------------
signal DDR_Ready_i : std_logic;
-- -- ---------------------------------------------------------------------
signal ddr_Clock : std_logic;
signal ddr_Clock_n : std_logic;
signal ddr_Clock90 : std_logic;
signal ddr_Clock90_n : std_logic;
signal Clk_ddr_rddata : std_logic;
signal Clk_ddr_rddata_n : std_logic;
-- -- -- Write Pipe Channel
signal wpipe_wEn : std_logic;
signal wpipe_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal wpipe_aFull : std_logic;
signal wpipe_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_wr_Cross_Row : std_logic;
signal DDR_wr_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_write_ALC : std_logic_vector(11-1 downto 0);
signal wpipe_rEn : std_logic;
signal wpipe_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal wpipe_aEmpty : std_logic;
signal wpipe_Empty : std_logic;
signal wpipe_Qout_latch : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- -- -- Read Pipe Command Channel
signal rpipec_wEn : std_logic;
signal rpipec_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpipec_aFull : std_logic;
signal rpipec_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_rd_Cross_Row : std_logic;
signal DDR_rdc_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_read_ALC : std_logic_vector(11-1 downto 0);
signal rpipec_rEn : std_logic;
signal rpipec_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpipec_aEmpty : std_logic;
signal rpipec_Empty : std_logic;
-- -- -- Read Pipe Data Channel
signal rpiped_wEn : std_logic;
signal rpiped_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpiped_aFull : std_logic;
signal rpiped_Full : std_logic;
-- signal rpiped_rEn : std_logic;
signal rpiped_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpiped_aEmpty : std_logic;
-- signal rpiped_Empty : std_logic;
-- write State machine
type bram_wrStates is ( wrST_bram_RESET
, wrST_bram_IDLE
-- , wrST_bram_Address
, wrST_bram_1st_Data
, wrST_bram_1st_Data_b2b
, wrST_bram_more_Data
, wrST_bram_last_DW
);
-- State variables
signal pseudo_DDR_wr_State : bram_wrStates;
-- Block RAM
signal pRAM_weA : std_logic_vector(7 downto 0);
signal pRAM_addrA : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_weB : std_logic_vector(7 downto 0);
signal pRAM_addrB : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_shifted : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wpipe_qout_lo32b : std_logic_vector(33-1 downto 0);
signal wpipe_QW_Aligned : std_logic;
signal pRAM_AddrA_Inc : std_logic;
signal wpipe_read_valid : std_logic;
-- read State machine
type bram_rdStates is ( rdST_bram_RESET
, rdST_bram_IDLE
, rdST_bram_b4_LA
, rdST_bram_LA
-- , rdST_bram_b4_Length
-- , rdST_bram_Length
-- , rdST_bram_b4_Address
-- , rdST_bram_Address
, rdST_bram_Data
-- , rdST_bram_Data_shift
);
-- State variables
signal pseudo_DDR_rd_State : bram_rdStates;
signal rpiped_rd_counter : std_logic_vector(10-1 downto 0);
signal rpiped_wEn_b3 : std_logic;
signal rpiped_wEn_b2 : std_logic;
signal rpiped_wEn_b1 : std_logic;
signal rpiped_wr_EOF : std_logic;
signal rpipec_read_valid : std_logic;
signal rpiped_wr_skew : std_logic;
signal rpiped_wr_postpone : std_logic;
signal simone_debug : std_logic;
begin
Rst_i <= not trn_reset_n;
DDR_Ready <= DDR_Ready_i;
pRAM_doutB_shifted <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
-- Delay
Syn_Shifting_pRAM_doutB:
process ( trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
pRAM_doutB_r1 <= pRAM_doutB;
end if;
end process;
-- -----------------------------------------------
--
Syn_DDR_CKE:
process (trn_clk, Rst_i)
begin
if Rst_i = '1' then
DDR_Ready_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
DDR_Ready_i <= '1'; -- ddr_DCM_locked;
end if;
end process;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_Clock_Generator:
-- DDR_ClkGen
-- PORT MAP(
-- ddr_Clock => ddr_Clock , -- OUT std_logic;
-- ddr_Clock_n => ddr_Clock_n , -- OUT std_logic;
-- ddr_Clock90 => ddr_Clock90 , -- OUT std_logic;
-- ddr_Clock90_n => ddr_Clock90_n , -- OUT std_logic;
-- Clk_ddr_rddata => Clk_ddr_rddata , -- OUT std_logic;
-- Clk_ddr_rddata_n => Clk_ddr_rddata_n , -- OUT std_logic;
-- ddr_DCM_locked => ddr_DCM_locked , -- OUT std_logic;
--
-- clk_in => mem_clk , -- IN std_logic;
-- trn_reset_n => trn_reset_n -- IN std_logic
-- );
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => wpipe_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => wpipe_aEmpty ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => open ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_write_fifo:
k7_prime_fifo_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => wpipe_wEn , -- IN std_logic;
din => wpipe_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => wpipe_aFull , -- OUT std_logic;
full => wpipe_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => wpipe_rEn , -- IN std_logic;
dout => wpipe_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => wpipe_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
wpipe_wEn <= DDR_wr_v;
wpipe_Din <= DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
DDR_wr_full <= wpipe_aFull;
Sim_Zeichen <= simone_debug; --S wpipe_Empty;
Syn_DDR_wrD_Cross_Row:
process (trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
DDR_wr_din_r1(64-1 downto 10) <= (OTHERS=>'0');
DDR_wr_din_r1( 9 downto 0) <= DDR_wr_din(9 downto 0) - "100";
end if;
end process;
DDR_write_ALC <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
DDR_wr_Cross_Row <= '0'; -- DDR_write_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => rpipec_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => rpipec_aEmpty ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
--
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => open ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_C_fifo:
k7_prime_fifo_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => rpipec_wEn , -- IN std_logic;
din => rpipec_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpipec_aFull , -- OUT std_logic;
full => open, --rpipec_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => rpipec_rEn , -- IN std_logic;
dout => rpipec_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => rpipec_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
rpipec_wEn <= DDR_rdc_v;
rpipec_Din <= "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
DDR_rdc_full <= rpipec_aFull;
Syn_DDR_rdC_Cross_Row:
process (trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
DDR_rdc_din_r1(64-1 downto 10) <= (OTHERS=>'0');
DDR_rdc_din_r1( 9 downto 0) <= DDR_rdc_din(9 downto 0) - "100";
end if;
end process;
DDR_read_ALC <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
DDR_rd_Cross_Row <= '0'; -- DDR_read_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => ddr_Clock, -- Clk_ddr_rddata , -- ddr_Clock , -- ddr_Clock_n ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => rpiped_Full ,
--
-- rClk => trn_clk ,
-- rEn => DDR_FIFO_RdEn , -- rpiped_rEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open , -- rpiped_aEmpty ,
-- Empty => DDR_FIFO_Empty , -- rpiped_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => ddr_Clock ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => open ,
--
-- rClk => trn_clk ,
-- rEn => DDR_FIFO_RdEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open ,
-- Empty => DDR_FIFO_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_D_fifo:
k7_prime_fifo_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => rpiped_wEn , -- IN std_logic;
din => rpiped_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpiped_aFull , -- OUT std_logic;
full => open, -- rpiped_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => DDR_FIFO_RdEn , -- IN std_logic;
dout => rpiped_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => DDR_FIFO_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
DDR_FIFO_RdQout <= rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
-- -------------------------------------------------
-- pkt_RAM instantiate
--
pkt_RAM:
k7_bram4096x64
port map (
clka => trn_clk ,
addra => pRAM_addrA ,
wea => pRAM_weA ,
dina => pRAM_dinA ,
douta => pRAM_doutA ,
clkb => trn_clk ,
addrb => pRAM_addrB ,
web => pRAM_weB ,
dinb => pRAM_dinB ,
doutb => pRAM_doutB
);
pRAM_weB <= X"00";
pRAM_dinB <= (Others =>'0');
-- ------------------------------------------------
-- write States synchronous
--
Syn_Pseudo_DDR_wr_States:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (OTHERS=>'1');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
wpipe_qout_lo32b <= (OTHERS=>'0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
elsif trn_clk'event and trn_clk = '1' then
case pseudo_DDR_wr_State is
when wrST_bram_RESET =>
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_addrA <= (OTHERS=>'1');
wpipe_QW_Aligned <= '1';
wpipe_qout_lo32b <= (OTHERS=>'0');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
pRAM_AddrA_Inc <= '1';
when wrST_bram_IDLE =>
pRAM_addrA <= wpipe_Qout(14 downto 3);
pRAM_AddrA_Inc <= wpipe_Qout(2);
wpipe_QW_Aligned <= not wpipe_Qout(69);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= pRAM_dinA;
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data; -- wrST_bram_Address;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
end if;
when wrST_bram_1st_Data =>
pRAM_addrA <= pRAM_addrA;
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
elsif wpipe_Qout(71)='1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif pRAM_AddrA_Inc='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_more_Data =>
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_more_Data; -- wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_addrA <= pRAM_addrA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_last_DW =>
-- pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data_b2b; -- wrST_bram_Address;
wpipe_Qout_latch <= wpipe_Qout;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
wpipe_Qout_latch <= wpipe_Qout;
end if;
when wrST_bram_1st_Data_b2b =>
pRAM_addrA <= wpipe_Qout_latch(14 downto 3);
wpipe_QW_Aligned <= not wpipe_Qout_latch(69);
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(71)='1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout_latch(2)='1' then -- pRAM_AddrA_Inc
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when OTHERS =>
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (OTHERS=>'1');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
wpipe_qout_lo32b <= (OTHERS=>'0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
end case;
end if;
end process;
--
Syn_wPipe_read:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
wpipe_rEn <= '0';
wpipe_read_valid <= '0';
elsif trn_clk'event and trn_clk = '1' then
wpipe_rEn <= '1';
wpipe_read_valid <= wpipe_rEn and not wpipe_Empty;
end if;
end process;
--
Syn_rPipeC_read:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpipec_read_valid <= '0';
rpiped_wr_postpone <= '0';
rpiped_wr_skew <= '0';
elsif trn_clk'event and trn_clk = '1' then
rpipec_read_valid <= rpipec_rEn and not rpipec_Empty;
if rpipec_read_valid='1' then
rpiped_wr_postpone <= rpipec_Qout(2) and not rpipec_Qout(69);
rpiped_wr_skew <= rpipec_Qout(69) xor rpipec_Qout(2);
else
rpiped_wr_postpone <= rpiped_wr_postpone;
rpiped_wr_skew <= rpiped_wr_skew;
end if;
end if;
end process;
-- ------------------------------------------------
-- Read States synchronous
--
Syn_Pseudo_DDR_rd_States:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
pseudo_DDR_rd_State <= rdST_bram_RESET;
rpipec_rEn <= '0';
pRAM_addrB <= (OTHERS=>'1');
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
elsif trn_clk'event and trn_clk = '1' then
case pseudo_DDR_rd_State is
when rdST_bram_RESET =>
pseudo_DDR_rd_State <= rdST_bram_IDLE;
rpipec_rEn <= '0';
pRAM_addrB <= (OTHERS=>'1');
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
when rdST_bram_IDLE =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
if rpipec_Empty = '0' then
rpipec_rEn <= '1';
pseudo_DDR_rd_State <= rdST_bram_b4_LA; --rdST_bram_b4_Length;
else
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
end if;
when rdST_bram_b4_LA =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_LA;
when rdST_bram_LA =>
rpipec_rEn <= '0';
pRAM_addrB <= rpipec_Qout(14 downto 3);
rpiped_wr_EOF <= '0';
rpiped_wEn_b3 <= '0';
if rpipec_Qout(2+32)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + '1';
elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
else
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
end if;
-- elsif rpipec_Qout(2)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- elsif rpipec_Qout(69)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- else
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
-- end if;
pseudo_DDR_rd_State <= rdST_bram_Data;
when rdST_bram_Data =>
rpipec_rEn <= '0';
if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '1';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
elsif rpiped_aFull = '1' then
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
else
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter - "10";
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
end if;
when OTHERS =>
rpipec_rEn <= '0';
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_RESET;
end case;
end if;
end process;
Syn_Pseudo_DDR_rdd_write:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpiped_wEn_b1 <= '0';
rpiped_wEn_b2 <= '0';
rpiped_wEn <= '0';
rpiped_Din <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
rpiped_wEn_b2 <= rpiped_wEn_b3;
rpiped_wEn_b1 <= rpiped_wEn_b2;
if rpiped_wr_skew='1' then
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
else
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
end if;
end if;
end process;
--
DDR_Blinker_Module:
DDR_Blink
PORT MAP(
DDR_Blinker => DDR_Blinker ,
DDR_Write => wpipe_rEn ,
DDR_Read => rpiped_wEn ,
DDR_Both => '0' ,
ddr_Clock => trn_clk ,
DDr_Rst_n => DDR_Ready_i -- DDR_CKE_i
);
end architecture Behavioral;
| gpl-2.0 | 59cad922612a9acac877e6f7c2412627 | 0.41387 | 3.702835 | false | false | false | false |
peteut/nvc | test/lower/tounsigned.vhd | 1 | 558 | package p is
type UNSIGNED is array (NATURAL range <>) of bit;
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED;
end package;
package body p is
function TO_UNSIGNED (ARG, SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED(SIZE-1 downto 0);
variable I_VAL: NATURAL := ARG;
begin
mainloop: for I in 0 to RESULT'LEFT loop
if (I_VAL mod 2) = 0 then
RESULT(I) := '0';
else RESULT(I) := '1';
end if;
I_VAL := I_VAL/2;
end loop;
return RESULT;
end TO_UNSIGNED;
end package body;
| gpl-3.0 | 3547c359481b8cbf5d277ce2523c7a4d | 0.629032 | 3.531646 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_rng.vhd | 1 | 3,908 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY rd_fifo_256to64_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF rd_fifo_256to64_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 66077bc21e0fcee15a449653ce73eaec | 0.638434 | 4.318232 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xlconcat_0_0/synth/cpu_xlconcat_0_0.vhd | 1 | 8,839 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlconcat:2.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlconcat;
ENTITY cpu_xlconcat_0_0 IS
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END cpu_xlconcat_0_0;
ARCHITECTURE cpu_xlconcat_0_0_arch OF cpu_xlconcat_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_xlconcat_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlconcat IS
GENERIC (
IN0_WIDTH : INTEGER;
IN1_WIDTH : INTEGER;
IN2_WIDTH : INTEGER;
IN3_WIDTH : INTEGER;
IN4_WIDTH : INTEGER;
IN5_WIDTH : INTEGER;
IN6_WIDTH : INTEGER;
IN7_WIDTH : INTEGER;
IN8_WIDTH : INTEGER;
IN9_WIDTH : INTEGER;
IN10_WIDTH : INTEGER;
IN11_WIDTH : INTEGER;
IN12_WIDTH : INTEGER;
IN13_WIDTH : INTEGER;
IN14_WIDTH : INTEGER;
IN15_WIDTH : INTEGER;
IN16_WIDTH : INTEGER;
IN17_WIDTH : INTEGER;
IN18_WIDTH : INTEGER;
IN19_WIDTH : INTEGER;
IN20_WIDTH : INTEGER;
IN21_WIDTH : INTEGER;
IN22_WIDTH : INTEGER;
IN23_WIDTH : INTEGER;
IN24_WIDTH : INTEGER;
IN25_WIDTH : INTEGER;
IN26_WIDTH : INTEGER;
IN27_WIDTH : INTEGER;
IN28_WIDTH : INTEGER;
IN29_WIDTH : INTEGER;
IN30_WIDTH : INTEGER;
IN31_WIDTH : INTEGER;
dout_width : INTEGER;
NUM_PORTS : INTEGER
);
PORT (
In0 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In1 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In2 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In3 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In4 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In5 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In6 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In7 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In8 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In9 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In10 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In11 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In12 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In13 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In14 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In15 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In16 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In17 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In18 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In19 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In20 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In21 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In22 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In23 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In24 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In25 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In26 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In27 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In28 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In29 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In30 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
In31 : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
);
END COMPONENT xlconcat;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_xlconcat_0_0_arch: ARCHITECTURE IS "xlconcat,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_xlconcat_0_0_arch : ARCHITECTURE IS "cpu_xlconcat_0_0,xlconcat,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_xlconcat_0_0_arch: ARCHITECTURE IS "cpu_xlconcat_0_0,xlconcat,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlconcat,x_ipVersion=2.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,IN0_WIDTH=1,IN1_WIDTH=1,IN2_WIDTH=1,IN3_WIDTH=1,IN4_WIDTH=1,IN5_WIDTH=1,IN6_WIDTH=1,IN7_WIDTH=1,IN8_WIDTH=1,IN9_WIDTH=1,IN10_WIDTH=1,IN11_WIDTH=1,IN12_WIDTH=1,IN13_WIDTH=1,IN14_WIDTH=1,IN15_WIDTH=1,IN16_WIDTH=1,IN17_WIDTH=1,IN18_WIDTH=1,IN19_WIDTH=1,IN20_WIDTH=1,IN21_WIDTH=1,IN22_WIDTH=1,IN23_WIDTH=1,IN24_WIDTH=1,IN25_WIDTH=1,IN26_WIDTH=1,IN27_WIDTH=1,IN28_WIDTH=1,IN29_WIDTH=1,IN30_WIDTH=1,IN31_WIDTH=1,dout_width=6,NUM_PORTS=6}";
BEGIN
U0 : xlconcat
GENERIC MAP (
IN0_WIDTH => 1,
IN1_WIDTH => 1,
IN2_WIDTH => 1,
IN3_WIDTH => 1,
IN4_WIDTH => 1,
IN5_WIDTH => 1,
IN6_WIDTH => 1,
IN7_WIDTH => 1,
IN8_WIDTH => 1,
IN9_WIDTH => 1,
IN10_WIDTH => 1,
IN11_WIDTH => 1,
IN12_WIDTH => 1,
IN13_WIDTH => 1,
IN14_WIDTH => 1,
IN15_WIDTH => 1,
IN16_WIDTH => 1,
IN17_WIDTH => 1,
IN18_WIDTH => 1,
IN19_WIDTH => 1,
IN20_WIDTH => 1,
IN21_WIDTH => 1,
IN22_WIDTH => 1,
IN23_WIDTH => 1,
IN24_WIDTH => 1,
IN25_WIDTH => 1,
IN26_WIDTH => 1,
IN27_WIDTH => 1,
IN28_WIDTH => 1,
IN29_WIDTH => 1,
IN30_WIDTH => 1,
IN31_WIDTH => 1,
dout_width => 6,
NUM_PORTS => 6
)
PORT MAP (
In0 => In0,
In1 => In1,
In2 => In2,
In3 => In3,
In4 => In4,
In5 => In5,
In6 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In7 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In8 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In9 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In10 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In11 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In12 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In13 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In14 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In15 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In16 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In17 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In18 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In19 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In20 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In21 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In22 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In23 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In24 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In25 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In26 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In27 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In28 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In29 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In30 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
In31 => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
dout => dout
);
END cpu_xlconcat_0_0_arch;
| gpl-3.0 | 5a1b374e1af004f10f2f5cda388cb9fd | 0.644643 | 3.230629 | false | false | false | false |
esar/hdmilight-v1 | fpga/avr/data_mem.vhd | 3 | 5,363 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: data_mem - Behavioral
-- Create Date: 14:09:04 10/30/2009
-- Description: the data mempry of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
entity data_mem is
port ( I_CLK : in std_logic;
I_ADR : in std_logic_vector(10 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_WE : in std_logic_vector( 1 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end data_mem;
architecture Behavioral of data_mem is
constant zero_256 : bit_vector := X"00000000000000000000000000000000"
& X"00000000000000000000000000000000";
constant nine_256 : bit_vector := X"99999999999999999999999999999999"
& X"99999999999999999999999999999999";
signal L_ADR_0 : std_logic;
signal L_ADR_E : std_logic_vector(11 downto 1);
signal L_ADR_O : std_logic_vector(11 downto 1);
signal L_DIN_E : std_logic_vector( 7 downto 0);
signal L_DIN_O : std_logic_vector( 7 downto 0);
signal L_DOUT_E : std_logic_vector( 7 downto 0);
signal L_DOUT_O : std_logic_vector( 7 downto 0);
signal L_WE_E : std_logic;
signal L_WE_O : std_logic;
begin
sr : RAMB16_S9_S9
generic map (
INIT_00 => nine_256, INIT_01 => nine_256, INIT_02 => nine_256,
INIT_03 => nine_256, INIT_04 => nine_256, INIT_05 => nine_256,
INIT_06 => nine_256, INIT_07 => nine_256, INIT_08 => nine_256,
INIT_09 => nine_256, INIT_0A => nine_256, INIT_0B => nine_256,
INIT_0C => nine_256, INIT_0D => nine_256, INIT_0E => nine_256,
INIT_0F => nine_256,
INIT_10 => nine_256, INIT_11 => nine_256, INIT_12 => nine_256,
INIT_13 => nine_256, INIT_14 => nine_256, INIT_15 => nine_256,
INIT_16 => nine_256, INIT_17 => nine_256, INIT_18 => nine_256,
INIT_19 => nine_256, INIT_1A => nine_256, INIT_1B => nine_256,
INIT_1C => nine_256, INIT_1D => nine_256, INIT_1E => nine_256,
INIT_1F => nine_256,
INIT_20 => nine_256, INIT_21 => nine_256, INIT_22 => nine_256,
INIT_23 => nine_256, INIT_24 => nine_256, INIT_25 => nine_256,
INIT_26 => nine_256, INIT_27 => nine_256, INIT_28 => nine_256,
INIT_29 => nine_256, INIT_2A => nine_256, INIT_2B => nine_256,
INIT_2C => nine_256, INIT_2D => nine_256, INIT_2E => nine_256,
INIT_2F => nine_256,
INIT_30 => nine_256, INIT_31 => nine_256, INIT_32 => nine_256,
INIT_33 => nine_256, INIT_34 => nine_256, INIT_35 => nine_256,
INIT_36 => nine_256, INIT_37 => nine_256, INIT_38 => nine_256,
INIT_39 => nine_256, INIT_3A => nine_256, INIT_3B => nine_256,
INIT_3C => nine_256, INIT_3D => nine_256, INIT_3E => nine_256,
INIT_3F => nine_256)
port map ( ADDRA => L_ADR_E, ADDRB => L_ADR_O,
CLKA => I_CLK, CLKB => I_CLK,
DIA => L_DIN_E, DIB => L_DIN_O,
ENA => '1', ENB => '1',
SSRA => '0', SSRB => '0',
WEA => L_WE_E, WEB => L_WE_O,
DOA => L_DOUT_E, DOB => L_DOUT_O,
DOPA => open, DOPB => open,
DIPA => "0", DIPB => "0");
-- remember ADR(0)
--
adr0: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
L_ADR_0 <= I_ADR(0);
end if;
end process;
-- we use two memory blocks _E and _O (even and odd).
-- This gives us a memory with ADR and ADR + 1 at th same time.
-- The second port is currently unused, but may be used later,
-- e.g. for DMA.
--
L_ADR_O <= "0" & I_ADR(10 downto 1);
L_ADR_E <= "1" & (I_ADR(10 downto 1) + ("000000000" & I_ADR(0)));
L_DIN_E <= I_DIN( 7 downto 0) when (I_ADR(0) = '0') else I_DIN(15 downto 8);
L_DIN_O <= I_DIN( 7 downto 0) when (I_ADR(0) = '1') else I_DIN(15 downto 8);
L_WE_E <= I_WE(1) or (I_WE(0) and not I_ADR(0));
L_WE_O <= I_WE(1) or (I_WE(0) and I_ADR(0));
Q_DOUT( 7 downto 0) <= L_DOUT_E when (L_ADR_0 = '0') else L_DOUT_O;
Q_DOUT(15 downto 8) <= L_DOUT_E when (L_ADR_0 = '1') else L_DOUT_O;
end Behavioral;
| gpl-2.0 | 116b3cd342300001cb7cb1621fc96083 | 0.53086 | 3.143611 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_tb.vhd | 1 | 5,776 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
ENTITY k7_sfifo_15x128_tb IS
END ENTITY;
ARCHITECTURE k7_sfifo_15x128_arch OF k7_sfifo_15x128_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from k7_sfifo_15x128_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of k7_sfifo_15x128_synth
k7_sfifo_15x128_synth_inst:k7_sfifo_15x128_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 19
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | a4c997aea12d3fbe15ba7890744473b9 | 0.621018 | 4.108108 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_15/lab15_2/lab15_2.vhd | 1 | 848 | library ieee;
use ieee.std_logic_1164. all ;
use ieee.std_logic_unsigned. all ;
use ieee.numeric_std. all ;
entity mem is
port (clk : in std_logic ;
Wn_R : in std_logic ;
CSn : in std_logic ;
Addr : in std_logic_vector ( 4 downto 0 );
Di : in std_logic_vector ( 3 downto 0 );
Do : out std_logic_vector( 3 downto 0 ));
end mem;
architecture syn of mem is
type ram_type is array ( 15 downto 0 ) of std_logic_vector ( 3 downto 0 );
signal RAM : ram_type;
begin
process (clk, CSn)
begin
if CSn = '0' then
if (clk 'event and clk = '1' ) then
if (Wn_R = '0' ) then
RAM(to_integer( unsigned (addr))) <= Di;
Do <= "ZZZZ" ;
else Do <= RAM(to_integer( unsigned (addr)));
end if ;
end if ;
else
Do <= "ZZZZ" ;
end if ;
end process ;
end syn; | gpl-2.0 | dff50eb27f0e93351950dedc29a5b17d | 0.561321 | 2.617284 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_hid/simulation/weight_hid_synth.vhd | 1 | 7,904 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_hid_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY weight_hid_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE weight_hid_synth_ARCH OF weight_hid_synth IS
COMPONENT weight_hid_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(319 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 320,
READ_WIDTH => 320 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: weight_hid_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| bsd-2-clause | 131aa5b39e8b4f67e77aabce6d7df8b8 | 0.565789 | 3.778203 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_out/example_design/weight_out_prod.vhd | 1 | 10,098 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: weight_out_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : weight_out.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 320
-- C_READ_WIDTH_A : 320
-- C_WRITE_DEPTH_A : 45
-- C_READ_DEPTH_A : 45
-- C_ADDRA_WIDTH : 6
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 320
-- C_READ_WIDTH_B : 320
-- C_WRITE_DEPTH_B : 45
-- C_READ_DEPTH_B : 45
-- C_ADDRB_WIDTH : 6
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_out_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(5 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END weight_out_prod;
ARCHITECTURE xilinx OF weight_out_prod IS
COMPONENT weight_out_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : weight_out_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| bsd-2-clause | 002094071d6ad00a46b7c3f6726a95cd | 0.493563 | 3.832258 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_conv_funs_pkg.vhd | 1 | 15,239 | ----------------------------------------------------------------------------
-- conv_funs_pkg.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
----------------------------------------------------------------------------
-- Filename: conv_funs_pkg.vhd
--
-- Description:
-- Various string conversion functions.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- conv_funs_pkg.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: unknown
-- Revision: $Revision: 1.1.4.1 $
-- Date: $1/1/2002$
--
-- History:
-- XXX 1/1/2002 Initial Version
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package cpu_xadc_wiz_0_0_conv_funs_pkg is
-- hex string to std_logic_vector
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- octal string to std_logic_vector
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- binary string to std_logic_vector
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
-- string to std_logic_vector
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR;
end cpu_xadc_wiz_0_0_conv_funs_pkg;
--
--------------------------------------------------------------------------------
--
package body cpu_xadc_wiz_0_0_conv_funs_pkg is
type basetype is (binary, octal, decimal, hex);
function max(x, y : INTEGER) return INTEGER is
begin
if x > y then return x; else return y; end if;
end max;
function MIN(x, y : INTEGER) return INTEGER is
begin
if x < y then return x; else return y; end if;
end MIN;
function hex_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*4, result will be truncated on the left
-- if instring is other than characters 0 to 9 or a,A to f,F or
-- x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*4, return_length);
variable char_ptr : INTEGER range -3 to max(instring'LENGTH*4, return_length) := max(instring'LENGTH*4, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*4, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-3 to char_ptr) := "0000";
when '1' => return_vector(char_ptr-3 to char_ptr) := "0001";
when '2' => return_vector(char_ptr-3 to char_ptr) := "0010";
when '3' => return_vector(char_ptr-3 to char_ptr) := "0011";
when '4' => return_vector(char_ptr-3 to char_ptr) := "0100";
when '5' => return_vector(char_ptr-3 to char_ptr) := "0101";
when '6' => return_vector(char_ptr-3 to char_ptr) := "0110";
when '7' => return_vector(char_ptr-3 to char_ptr) := "0111";
when '8' => return_vector(char_ptr-3 to char_ptr) := "1000";
when '9' => return_vector(char_ptr-3 to char_ptr) := "1001";
when 'a'|'A' => return_vector(char_ptr-3 to char_ptr) := "1010";
when 'b'|'B' => return_vector(char_ptr-3 to char_ptr) := "1011";
when 'c'|'C' => return_vector(char_ptr-3 to char_ptr) := "1100";
when 'd'|'D' => return_vector(char_ptr-3 to char_ptr) := "1101";
when 'e'|'E' => return_vector(char_ptr-3 to char_ptr) := "1110";
when 'f'|'F' => return_vector(char_ptr-3 to char_ptr) := "1111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-3 to char_ptr) := "UUUU";
-- when 'X' => return_vector(char_ptr-3 to char_ptr) := "XXXX";
-- when 'Z' => return_vector(char_ptr-3 to char_ptr) := "ZZZZ";
-- when 'W' => return_vector(char_ptr-3 to char_ptr) := "WWWW";
-- when 'H' => return_vector(char_ptr-3 to char_ptr) := "HHHH";
-- when 'L' => return_vector(char_ptr-3 to char_ptr) := "LLLL";
-- when '-' => return_vector(char_ptr-3 to char_ptr) := "----";
-- but synplicity does
when '_' => char_ptr := char_ptr + 4;
when others =>
assert FALSE
report lf &
"hex_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '----'"
severity WARNING;
return_vector(char_ptr-3 to char_ptr) := "----";
end case;
char_ptr := char_ptr - 4;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end hex_string_to_slv;
function oct_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length*3, result will be truncated on the left
-- if instring is other than characters 0 to 7 or or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH*3, return_length);
variable char_ptr : INTEGER range -2 to max(instring'LENGTH*3, return_length) := max(instring'LENGTH*3, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH*3, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr-2 to char_ptr) := "000";
when '1' => return_vector(char_ptr-2 to char_ptr) := "001";
when '2' => return_vector(char_ptr-2 to char_ptr) := "010";
when '3' => return_vector(char_ptr-2 to char_ptr) := "011";
when '4' => return_vector(char_ptr-2 to char_ptr) := "100";
when '5' => return_vector(char_ptr-2 to char_ptr) := "101";
when '6' => return_vector(char_ptr-2 to char_ptr) := "110";
when '7' => return_vector(char_ptr-2 to char_ptr) := "111";
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr-2 to char_ptr) := "UUU";
-- when 'X' => return_vector(char_ptr-2 to char_ptr) := "XXX";
-- when 'Z' => return_vector(char_ptr-2 to char_ptr) := "ZZZ";
-- when 'W' => return_vector(char_ptr-2 to char_ptr) := "WWW";
-- when 'H' => return_vector(char_ptr-2 to char_ptr) := "HHH";
-- when 'L' => return_vector(char_ptr-2 to char_ptr) := "LLL";
-- when '-' => return_vector(char_ptr-2 to char_ptr) := "---";
-- but synplicity does
when '_' => char_ptr := char_ptr + 3;
when others =>
assert FALSE
report lf &
"oct_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '---'"
severity WARNING;
return_vector(char_ptr-2 to char_ptr) := "---";
end case;
char_ptr := char_ptr - 3;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end oct_string_to_slv;
function bin_string_to_slv (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
-- if return_length is < than instring'length, result will be truncated on the left
-- if instring is other than characters 0 to 1 or x,X,z,Z,u,U,-,w,W,
-- those result bits will be set to 0
variable temp_string : STRING(1 to instring'LENGTH) := instring;
variable vector_size : POSITIVE := max(instring'LENGTH, return_length);
variable char_ptr : INTEGER range 0 to max(instring'LENGTH, return_length)+1 := max(instring'LENGTH, return_length);
variable return_vector : STD_LOGIC_VECTOR(1 to max(instring'LENGTH, return_length)) := (others => '0');
begin
for i in temp_string'REVERSE_RANGE loop
case temp_string(i) is
when '0' => return_vector(char_ptr) := '0';
when '1' => return_vector(char_ptr) := '1';
-- xst doesn't handle these
-- when 'U' => return_vector(char_ptr) := 'U';
-- when 'X' => return_vector(char_ptr) := 'X';
-- when 'Z' => return_vector(char_ptr) := 'Z';
-- when 'W' => return_vector(char_ptr) := 'W';
-- when 'H' => return_vector(char_ptr) := 'H';
-- when 'L' => return_vector(char_ptr) := 'L';
-- when '-' => return_vector(char_ptr) := '-';
-- but synplicity does
when '_' => char_ptr := char_ptr + 1;
when others =>
assert FALSE
report lf &
"bin_string_to_slv conversion found illegal input character: " &
temp_string(i) & lf & "converting character to '-'"
severity WARNING;
return_vector(char_ptr) := '-';
end case;
char_ptr := char_ptr - 1;
end loop;
return return_vector(vector_size-return_length+1 to vector_size);
end bin_string_to_slv;
function string_to_std_logic_vector (instring : STRING;
return_length : POSITIVE range 1 to 64 := 32)
return STD_LOGIC_VECTOR is
variable instring_length : POSITIVE := instring'LENGTH;
variable temp_string : STRING(1 to instring'LENGTH-2);
begin -- function string_to_std_logic_vector
if instring(1) = '0' and (instring(2) = 'x' or instring(2) = 'X') then
temp_string := instring(3 to instring_length);
return hex_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'o' or instring(2) = 'O') then
temp_string := instring(3 to instring_length);
return oct_string_to_slv(temp_string, return_length);
elsif instring(1) = '0' and (instring(2) = 'b' or instring(2) = 'B') then
temp_string := instring(3 to instring_length);
return bin_string_to_slv(temp_string, return_length);
else
return bin_string_to_slv(instring, return_length);
end if;
end function string_to_std_logic_vector;
end cpu_xadc_wiz_0_0_conv_funs_pkg;
| gpl-3.0 | 906e9b6faacb1b6e84fd1fbb737b9265 | 0.504823 | 4.055082 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/tb/axistream_spw_lite_v1_0_tb.vhd | 1 | 4,333 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.axistream_spw_lite_v1_0_pkg.all;
entity axistream_spw_lite_v1_0_tb is
generic (
sysfreq : real := 100000000.0;
txclkfreq : real := 200000000.0;
--rximpl : spw_implementation_type := impl_generic;
rxchunk_fast : integer range 1 to 4 := 1;
--tximpl : spw_implementation_type := impl_generic;
rxfifosize_bits : integer range 6 to 14 := 11; -- 11 (2 kByte)
txfifosize_bits : integer range 2 to 14 := 11; -- 11 (2 kByte)
txdivcnt : std_logic_vector(7 downto 0) := x"04";
rximpl_fast : boolean := false; -- true to use rx_clk
tximpl_fast : boolean := false -- true to use tx_clk
);
end axistream_spw_lite_v1_0_tb;
architecture arch_imp of axistream_spw_lite_v1_0_tb is
-- control signals
constant aclk_period : time := 10 ns; -- 100 MHz clock
constant txclk_period : time := 5 ns;
constant rxclk_period : time := 12 ns;
signal aclk, txclk, rxclk : std_logic := '0';
signal aresetn : std_logic := '0';
-- data connections
signal s_do : std_logic := '0';
signal s_so : std_logic := '0';
-- slave axis lines
signal s_axis_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal s_axis_tvalid : std_logic := '0';
signal s_axis_tready : std_logic := '0';
signal s_axis_tlast : std_logic := '0';
-- master axis lines
signal m_axis_tdata : std_logic_vector(7 downto 0) := (others => '0');
signal m_axis_tvalid : std_logic := '0';
signal m_axis_tready : std_logic := '0';
signal m_axis_tlast : std_logic := '0';
signal rx_error : std_logic := '0';
-- test data
signal word_in : unsigned(7 downto 0) := (others => '0');
signal word_out : unsigned(7 downto 0) := (others => '0');
signal expected_word : unsigned(7 downto 0) := (others => '0');
signal TLAST_NOT_ASSERTED : std_logic := '0';
signal INVALID_WORD_RECEIVED : std_logic := '0';
begin
aclk_gen : process
begin
aclk <= not aclk;
wait for aclk_period/2;
end process aclk_gen;
txclk_gen : process
begin
txclk <= not txclk;
wait for txclk_period/2;
end process txclk_gen;
rxclk_gen : process
begin
rxclk <= not rxclk;
wait for rxclk_period/2;
end process rxclk_gen;
reset_gen : process
begin
aresetn <= '0';
wait for aclk_period*5;
aresetn <= '1';
wait for 1000 ms;
end process reset_gen;
axistream_spw_lite_v1_0_inst : axistream_spw_lite_v1_0
generic map (
sysfreq => sysfreq,
txclkfreq => txclkfreq,
rximpl_fast => rximpl_fast,
rxchunk_fast => rxchunk_fast,
tximpl_fast => tximpl_fast,
rxfifosize_bits => rxfifosize_bits,
txfifosize_bits => txfifosize_bits,
txdivcnt => txdivcnt
)
port map (
aclk => aclk,
aresetn => aresetn,
rx_clk => rxclk,
tx_clk => txclk,
spw_di => s_do,
spw_si => s_so,
spw_do => s_do,
spw_so => s_so,
s_axis_tdata => s_axis_tdata,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tlast => s_axis_tlast,
m_axis_tdata => m_axis_tdata,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tlast => m_axis_tlast,
rx_error => rx_error
);
s_axis_tvalid <= '1';
m_axis_tready <= '1';
s_axis_tdata <= std_logic_vector(word_in);
s_axis_tlast <= '1' when word_in = to_unsigned(255, 8) else '0';
word_out <= unsigned(m_axis_tdata) when m_axis_tvalid = '1' else word_out;
process(aclk)
begin
if(rising_edge(aclk)) then
if(m_axis_tvalid = '1') then
expected_word <= expected_word + 1;
if(unsigned(m_axis_tdata) /= expected_word) then
report "INVALID WORD RECEIVED" severity warning;
INVALID_WORD_RECEIVED <= '1';
end if;
if(unsigned(m_axis_tdata) = 255 and m_axis_tlast = '0' and m_axis_tvalid = '1') then
report "TLAST NOT ASSERTED" severity warning;
TLAST_NOT_ASSERTED <= '1';
end if;
end if;
end if;
end process;
process(aclk)
begin
if(rising_edge(aclk)) then
if(s_axis_tready = '1') then
word_in <= word_in + 1;
end if;
end if;
end process;
end arch_imp;
| mit | eec3ed7b3de72b9d731f3fc5c61dee1c | 0.589661 | 3.051408 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp_lut.vhd | 1 | 19,135 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_lut.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-17
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controller look up table
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-17 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--library work;
--use work.util_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;
entity disp_lut is
port (
rst_n : in std_logic;
clk : in std_logic;
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
lut_addr : in std_logic_vector(11 downto 0);
lut_data : out std_logic_vector(7 downto 0)
);
end disp_lut;
architecture structure of disp_lut is
SIGNAL rst : std_logic;
begin
rst <= not rst_n;
-- BRAM_TDP_MACRO: True Dual Port RAM
-- 7 Series
-- Xilinx HDL Libraries Guide, version 2014.4
-- Note - This Unimacro model assumes the port directions to be "downto".
-- Simulation of this model with "to" in the port directions could lead to erroneous results.
--------------------------------------------------------------------------
-- DATA_WIDTH_A/B | BRAM_SIZE | RAM Depth | ADDRA/B Width | WEA/B Width --
-- ===============|===========|===========|===============|=============--
-- 19-36 | "36Kb" | 1024 | 10-bit | 4-bit --
-- 10-18 | "36Kb" | 2048 | 11-bit | 2-bit --
-- 10-18 | "18Kb" | 1024 | 10-bit | 2-bit --
-- 5-9 | "36Kb" | 4096 | 12-bit | 1-bit --
-- 5-9 | "18Kb" | 2048 | 11-bit | 1-bit --
-- 3-4 | "36Kb" | 8192 | 13-bit | 1-bit --
-- 3-4 | "18Kb" | 4096 | 12-bit | 1-bit --
-- 2 | "36Kb" | 16384 | 14-bit | 1-bit --
-- 2 | "18Kb" | 8192 | 13-bit | 1-bit --
-- 1 | "36Kb" | 32768 | 15-bit | 1-bit --
-- 1 | "18Kb" | 16384 | 14-bit | 1-bit --
--------------------------------------------------------------------------
BRAM_TDP_MACRO_inst : BRAM_TDP_MACRO
generic map (
BRAM_SIZE => "36Kb", -- Target BRAM, "18Kb" or "36Kb"
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "VIRTEX6", "7SERIES", "SPARTAN6"
DOA_REG => 0, -- Optional port A output register (0 or 1)
DOB_REG => 0, -- Optional port B output register (0 or 1)
INIT_A => X"000000000", -- Initial values on A output port
INIT_B => X"000000000", -- Initial values on B output port
INIT_FILE => "NONE",
READ_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
READ_WIDTH_B => 8, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
-- "GENERATE_X_ONLY" or "NONE"
SRVAL_A => X"000000000", -- Set/Reset value for A port output
SRVAL_B => X"000000000", -- Set/Reset value for B port output
WRITE_MODE_A => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
WRITE_MODE_B => "WRITE_FIRST", -- "WRITE_FIRST", "READ_FIRST" or "NO_CHANGE"
WRITE_WIDTH_A => 32, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
WRITE_WIDTH_B => 8, -- Valid values are 1-36 (19-36 only valid when BRAM_SIZE="36Kb")
-- The following INIT_xx declarations specify the initial contents of the RAM
INIT_00 => X"000000000000000000000064006300530075006e00380038002000470050004c",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"00220023002400250026002700280029002a002b002c002d002e002f00300031",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000200021",
INIT_04 => X"003400350036003700380039003a003b003c003d003e003f0040004100420043",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000320033",
INIT_06 => X"0046004700480049004a004b004c004d004e004f005000510052005300540055",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000440045",
INIT_08 => X"00580059005a005b005c005d005e005f00600061006200630064006500660067",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000560057",
INIT_0A => X"006a006b006c006d006e006f0070007100720073007400750076007700780079",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000680069",
INIT_0C => X"007c007d007e007f002000200020002000200020002000200020002000200020",
INIT_0D => X"00000000000000000000000000000000000000000000000000000000007a007b",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0020002000200020002000880087002000860085002000840183008200810080",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_12 => X"0020002000200020008800870020008600850020008401830082008100800020",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_14 => X"0020002000200088008700200086008500200084018300820081008000200020",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_16 => X"0020002000880087002000860085002000840183008200810080002000200020",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_18 => X"0020008800870020008600850020008401830082008100800020002000200020",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_1A => X"0088008700200086008500200084018300820081008000200020002000200020",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000200020",
INIT_1C => X"0087002000860085002000840183008200810080002000200020002000200020",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000200088",
INIT_1E => X"0020008600850020008401830082008100800020002000200020002000200020",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000880087",
INIT_20 => X"0086008500200084018300820081008000200020002000200020002000200088",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000870020",
INIT_22 => X"0085002000840183008200810080002000200020002000200020002000880087",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000200086",
INIT_24 => X"0020008401830082008100800020002000200020002000200020008800870020",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000860085",
INIT_26 => X"0084018300820081008000200020002000200020002000200088008700200086",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000850020",
INIT_28 => X"0183008200810080002000200020002000200020002000880087002000860085",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000200084",
INIT_2A => X"0082008100800020002000200020002000200020008800870020008600850020",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000840183",
INIT_2C => X"0081008000200020002000200020002000200088008700200086008500200084",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000001830082",
INIT_2E => X"0080002000200020002000200020002000880087002000860085002000840183",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000820081",
INIT_30 => X"0020002000200020002000200020008800870020008600850020008401830082",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000810080",
INIT_32 => X"0020002000200020002000200088008700200086008500200084018300820081",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000800020",
INIT_34 => X"002000470050004c002000470050004c002000470050004c002000470050004c",
INIT_35 => X"002000470050004c002000470050004c002000470050004c002000470050004c",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"000000000000000000000064006300530075006e00380038002000470050004c",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0020008800870020008600850020008401830082008100800020002000200020",
INIT_3D => X"0020002000200020002000200020002000200020002000200020002000200020",
INIT_3E => X"0138013801380138013801380138013801380138013801380138013801380138",
INIT_3F => X"0138013801380138013801380138013801380138013801380138013801380138",
-- The next set of INIT_xx are valid when configured as 36Kb
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"ca0012000000f6fee0beb666f2da60fc00010200000000000400000000440000",
INIT_42 => X"1000000000da766e547c7c1eb6ccd6cefceca81cae780c6ebc8e9e7a9cfeee00",
INIT_43 => X"0080000000da766e4438381eb60ae6ce3a2a280cae30082ef68ede7a1a3efa40",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INITP_xx are for the parity bits
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
-- The next set of INIT_xx are valid when configured as 36Kb
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
port map (
DOA => sram_datai, -- Output port-A data, width defined by READ_WIDTH_A parameter
DOB => lut_data, -- Output port-B data, width defined by READ_WIDTH_B parameter
ADDRA => sram_addr, -- Input port-A address, width defined by Port A depth
ADDRB => lut_addr, -- Input port-B address, width defined by Port B depth
CLKA => clk, -- 1-bit input port-A clock
CLKB => clk, -- 1-bit input port-B clock
DIA => sram_datao, -- Input port-A data, width defined by WRITE_WIDTH_A parameter
DIB => x"00", -- Input port-B data, width defined by WRITE_WIDTH_B parameter
ENA => '1', -- 1-bit input port-A enable
ENB => '1', -- 1-bit input port-B enable
REGCEA => '1', -- 1-bit input port-A output register enable
REGCEB => '1', -- 1-bit input port-B output register enable
RSTA => rst, -- 1-bit input port-A reset
RSTB => rst, -- 1-bit input port-B reset
WEA(0) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEA(1) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEA(2) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEA(3) => sram_we, -- Input port-A write enable, width defined by Port A depth
WEB => "0" -- Input port-B write enable, width defined by Port B depth
);
-- End of BRAM_TDP_MACRO_inst instantiation
end structure;
| gpl-3.0 | 722f7384e7ae270a9528edd0895fdec3 | 0.695009 | 5.182828 | false | false | false | false |
esar/hdmilight-v1 | fpga/top.vhd | 2 | 10,366 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HdmilightTop is
Port
(
ADV_P : in STD_LOGIC_VECTOR(23 downto 0);
ADV_LLC : in STD_LOGIC;
ADV_AP : in STD_LOGIC;
ADV_SCLK : in STD_LOGIC;
ADV_LRCLK : in STD_LOGIC;
ADV_MCLK : in STD_LOGIC;
ADV_SCL : inout STD_LOGIC;
ADV_SDA : inout STD_LOGIC;
ADV_INT1 : in STD_LOGIC;
ADV_RST : out STD_LOGIC;
ADV_HS : in STD_LOGIC;
ADV_VS : in STD_LOGIC;
ADV_DE : in STD_LOGIC;
OUTPUT : out STD_LOGIC_VECTOR(7 downto 0);
RX : in STD_LOGIC;
TX : inout STD_LOGIC;
CLK : in STD_LOGIC
);
end HdmilightTop;
architecture Behavioral of HdmilightTop is
-----------------------------------------------
-- Component Definitions
-----------------------------------------------
COMPONENT DCM32to16
PORT(
CLKIN_IN : IN std_logic;
CLKFX_OUT : OUT std_logic;
CLKIN_IBUFG_OUT : OUT std_logic;
CLK0_OUT : OUT std_logic
);
END COMPONENT;
component cpu_core
port ( I_CLK : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_DIN : in std_logic_vector( 7 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector( 7 downto 0);
Q_ADR_IO : out std_logic_vector( 7 downto 0);
Q_RD_IO : out std_logic;
Q_WE_IO : out std_logic);
end component;
component uart
generic (
divisor : integer := 139 );
port (
clk : in std_logic;
reset : in std_logic;
--
txdata : in std_logic_vector(7 downto 0);
rxdata : out std_logic_vector(7 downto 0);
wr : in std_logic;
rd : in std_logic;
tx_avail : out std_logic;
tx_busy : out std_logic;
rx_avail : out std_logic;
rx_full : out std_logic;
rx_error : out std_logic;
--
uart_rxd : in std_logic;
uart_txd : out std_logic
);
end component;
-----------------------------------------------
-- Signals
-----------------------------------------------
signal RST: std_logic:= '1';
signal RST_COUNT: std_logic_vector(1 downto 0):="00";
signal CLK16: std_logic;
-- UART
signal UART_TX_DATA : std_logic_vector(7 downto 0):=X"00";
signal UART_RX_DATA : std_logic_vector(7 downto 0):=X"00";
signal UART_WR : std_logic := '0';
signal UART_RD : std_logic := '0';
signal UART_TX_AVAIL : std_logic := '0';
signal UART_TX_BUSY : std_logic := '0';
signal UART_RX_AVAIL : std_logic := '0';
signal UART_RX_FULL : std_logic := '0';
signal UART_RX_ERROR : std_logic := '0';
-- MCU
signal MCU_RST: std_logic:= '1';
signal MCU_RUN: std_logic:= '0';
signal MCU_CLK: std_logic:= '0';
signal MCU_INST : std_logic_vector(16-1 downto 0):=(others=>'0');
signal MCU_PC : std_logic_vector(16-1 downto 0):=(others=>'0');
-- MCU IO bus control
signal MCU_IO_RD: std_logic:= '0';
signal MCU_IO_WR: std_logic:= '0';
signal MCU_IO_ADDR : std_logic_vector(8-1 downto 0):=(others=>'0');
signal MCU_IO_DATA_READ : std_logic_vector(8-1 downto 0):=(others=>'0');
signal MCU_IO_DATA_WRITE : std_logic_vector(8-1 downto 0):=(others=>'0');
-- MCU TMR
signal MCU_TIMER_VAL : std_logic_vector(32-1 downto 0):=(others=>'0');
signal MCU_TIMER_CNT : std_logic_vector(32-1 downto 0):=(others=>'0');
signal MCU_TIMER_LATCHED : std_logic_vector(32-1 downto 0):=(others=>'0');
signal DDRD : std_logic_vector(7 downto 0);
signal PIND : std_logic_vector(7 downto 0);
signal PORTD : std_logic_vector(7 downto 0);
signal vidclk : std_logic;
signal viddata_r : std_logic_vector(7 downto 0);
signal viddata_g : std_logic_vector(7 downto 0);
signal viddata_b : std_logic_vector(7 downto 0);
signal hblank : std_logic;
signal vblank : std_logic;
signal ambilightCfgWe : std_logic;
signal ambilightCfgLight : std_logic_vector(7 downto 0);
signal ambilightCfgComponent : std_logic_vector(3 downto 0);
signal ambilightCfgDataIn : std_logic_vector(7 downto 0);
signal ambilightCfgDataOut : std_logic_vector(7 downto 0);
signal driverOutput : std_logic_vector(7 downto 0);
begin
-----------------------------------------------
-- Instantiation
-----------------------------------------------
ambilight : entity ambilight port map(vidclk, viddata_r, viddata_g, viddata_b, hblank, vblank,
CLK16,
ambilightCfgWe,
ambilightCfgLight,
ambilightCfgComponent,
ambilightCfgDataIn,
ambilightCfgDataOut,
driverOutput);
Inst_DCM32to16: DCM32to16 PORT MAP(
CLKIN_IN => CLK,
CLKFX_OUT => CLK16,
CLKIN_IBUFG_OUT => open,
CLK0_OUT => open
);
-- Simple fixed baud UART
U2_UART: uart port map ( CLK16, RST, UART_TX_DATA, UART_RX_DATA, UART_WR, UART_RD,
UART_TX_AVAIL, UART_TX_BUSY, UART_RX_AVAIL, UART_RX_FULL, UART_RX_ERROR,
rx, tx);
-- AVR Core
U3_AVR_MCU: cpu_core port map (
I_CLK => MCU_CLK,
I_CLR => MCU_RST,
I_DIN => MCU_IO_DATA_READ,
I_INTVEC => "000000",
Q_ADR_IO => MCU_IO_ADDR,
Q_DOUT => MCU_IO_DATA_WRITE,
Q_OPC => MCU_INST,
Q_PC => MCU_PC,
Q_RD_IO => MCU_IO_RD,
Q_WE_IO => MCU_IO_WR);
-----------------------------------------------
-- Implementation
-----------------------------------------------
-- Reset Generator
process (CLK16)
begin
if (rising_edge(CLK16)) then
if (RST_COUNT = X"3") then
RST <= '0';
else
RST_COUNT <= RST_COUNT + 1;
end if;
end if;
end process;
-- IO memory space handler
process (RST,CLK16)
begin
if (RST = '1') then
UART_TX_DATA <= X"00";
UART_WR <= '0';
UART_RD <= '0';
MCU_TIMER_LATCHED <= (others=>'0');
elsif (rising_edge(CLK16)) then
UART_WR <= '0';
UART_RD <= '0';
ambilightCfgWe <= '0';
-- IO Read Cycle
if (MCU_IO_RD = '1') then
case MCU_IO_ADDR is
-- 0x21 -> Uart - UDR - TX BUF
when X"41" =>
UART_RD <= '1';
when others =>
end case;
end if;
-- IO Write Cycle
if (MCU_IO_WR = '1') then
case MCU_IO_ADDR is
-- 0x21 -> Uart - UDR - TX BUF
when X"41" =>
UART_TX_DATA <= MCU_IO_DATA_WRITE;
UART_WR <= '1';
-- 0x22 -> 32-bit Timer Control
when X"42" =>
-- Take snapshot of current timer value
MCU_TIMER_LATCHED <= MCU_TIMER_VAL;
when X"46" =>
ambilightCfgLight <= MCU_IO_DATA_WRITE;
when X"47" =>
ambilightCfgComponent <= MCU_IO_DATA_WRITE(3 downto 0);
when X"48" =>
ambilightCfgDataIn <= MCU_IO_DATA_WRITE;
ambilightCfgWe <= '1';
when X"49" =>
DDRD <= MCU_IO_DATA_WRITE;
when X"4b" =>
PORTD <= MCU_IO_DATA_WRITE;
when others =>
end case;
end if;
end if;
end process;
-- Asynchronous IO Read Process
process (MCU_IO_RD, MCU_IO_ADDR, UART_RX_ERROR, UART_TX_BUSY, UART_RX_FULL, UART_TX_AVAIL, UART_RX_AVAIL, UART_RX_DATA, MCU_TIMER_LATCHED,
ambilightCfgDataOut, DDRD, PIND, PORTD)
begin
-- Read cycle?
if (MCU_IO_RD = '1') then
case MCU_IO_ADDR is
-- 0x20 -> Uart - USR - Status Reg
when X"40" =>
MCU_IO_DATA_READ <= "000" & UART_RX_ERROR & UART_TX_BUSY & UART_RX_FULL & UART_TX_AVAIL & UART_RX_AVAIL;
-- 0x21 -> Uart - UDR - RX BUF
when X"41" =>
MCU_IO_DATA_READ <= UART_RX_DATA;
-- 0x22,23,24,25 -> 32-bit Timer
when X"42" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(7 downto 0);
when X"43" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(15 downto 8);
when X"44" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(23 downto 16);
when X"45" =>
MCU_IO_DATA_READ <= MCU_TIMER_LATCHED(31 downto 24);
when X"48" =>
MCU_IO_DATA_READ <= ambilightCfgDataOut;
when X"49" =>
MCU_IO_DATA_READ <= DDRD;
when X"4a" =>
MCU_IO_DATA_READ <= PIND;
when X"4b" =>
MCU_IO_DATA_READ <= PORTD;
when others =>
MCU_IO_DATA_READ <= X"00";
end case;
else
MCU_IO_DATA_READ <= X"00";
end if;
end process;
-- Timer (1 ms resolution)
process (RST,CLK16)
begin
if (RST = '1') then
MCU_TIMER_VAL <= (others=>'0');
MCU_TIMER_CNT <= (others=>'0');
elsif (rising_edge(CLK16)) then
-- 16000/0x3E80 = 1ms @ 16MHz
if (MCU_TIMER_CNT = X"3E80") then
MCU_TIMER_VAL <= MCU_TIMER_VAL + 1;
MCU_TIMER_CNT <= (others=>'0');
else
MCU_TIMER_CNT <= MCU_TIMER_CNT + 1;
end if;
end if;
end process;
-----------------------------------------------
-- Combinatorial
-----------------------------------------------
MCU_CLK <= CLK16;
MCU_RST <= RST;
MCU_RUN <= '1';
ADV_RST <= '1';
OUTPUT <= driverOutput;
ADV_SCL <= PORTD(7) when DDRD(7) = '1' else 'Z';
ADV_SDA <= PORTD(6) when DDRD(6) = '1' else 'Z';
PIND <= ADV_SCL & ADV_SDA & "000000";
vidclk <= ADV_LLC;
viddata_g <= ADV_P(23 downto 16);
viddata_b <= ADV_P(15 downto 8);
viddata_r <= ADV_P(7 downto 0);
hblank <= not ADV_HS;
vblank <= not ADV_VS;
end Behavioral;
| gpl-2.0 | 7e70bdbc381d9f893fd47d225bfc172b | 0.543411 | 3.160366 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/dac_tb.vhd | 1 | 3,643 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : dac_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-05
-- Last update: 2016-08-26
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Testbench for DAC driver
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-05 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity dac_tb is
end dac_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.tb_pkg.all;
architecture STRUCTURE of dac_tb is
component dac
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
dac_ena : in std_logic;
dac_tri : in std_logic;
dac_val : in std_logic_vector(15 downto 0);
dac_sclk : OUT std_logic;
dac_cs_n : OUT std_logic;
dac_sin : OUT std_logic
);
end component;
SIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL tsc_1pps : std_logic;
SIGNAL tsc_1ppms : std_logic;
SIGNAL dac_ena : std_logic;
SIGNAL dac_tri : std_logic;
SIGNAL dac_val : std_logic_vector(15 downto 0);
SIGNAL dac_sclk : std_logic;
SIGNAL dac_cs_n : std_logic;
SIGNAL dac_sin : std_logic;
begin
dac_i: dac
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
dac_ena => dac_ena,
dac_tri => dac_tri,
dac_val => dac_val,
dac_sclk => dac_sclk,
dac_cs_n => dac_cs_n,
dac_sin => dac_sin
);
clk_100MHZ: clk_gen(10 ns, 50, clk);
reset: rst_n_gen(1 us, rst_n);
dac_ena <= '1';
dac_tri <= '0';
process
begin
tsc_1pps <= '0';
run_clk(clk, 1000);
loop
tsc_1pps <= '1';
run_clk(clk, 1);
tsc_1pps <= '0';
run_clk(clk, 1999);
end loop;
end process;
process
begin
tsc_1ppms <= '0';
run_clk(clk, 1000);
loop
tsc_1ppms <= '1';
run_clk(clk, 1);
tsc_1ppms <= '0';
run_clk(clk, 1);
end loop;
end process;
process
begin
dac_val <= (others =>'0');
run_clk(clk, 2000);
dac_val <= x"aaaa";
run_clk(clk, 2000);
dac_val <= x"5555";
run_clk(clk, 2000);
dac_val <= x"a5a5";
run_clk(clk, 2000);
dac_val <= x"5a5a";
run_clk(clk, 2000);
wait;
end process;
end STRUCTURE;
| gpl-3.0 | af61fe3f13e141410a1e092b64a6b393 | 0.393632 | 3.81466 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_out/simulation/bmg_stim_gen.vhd | 1 | 7,572 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(320,320);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(5 DOWNTO 0) <= WRITE_ADDR(5 DOWNTO 0);
READ_ADDR_INT(5 DOWNTO 0) <= READ_ADDR(5 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 45
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 45 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 320,
DOUT_WIDTH => 320,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| bsd-2-clause | a803782eeba341d8ead18a4baa9772b9 | 0.558241 | 3.776559 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/example_design/k7_bram4096x64_exdes.vhd | 1 | 5,437 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_bram4096x64_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_bram4096x64_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END k7_bram4096x64_exdes;
ARCHITECTURE xilinx OF k7_bram4096x64_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT k7_bram4096x64 IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : k7_bram4096x64
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
| gpl-2.0 | 025c3e077b99c1b07a1bff83223b1604 | 0.55343 | 4.500828 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_8/lpm_add_sub0.vhd | 1 | 5,715 | -- megafunction wizard: %LPM_ADD_SUB%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_add_sub
-- ============================================================
-- File Name: lpm_add_sub0.vhd
-- Megafunction Name(s):
-- lpm_add_sub
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_add_sub0 IS
PORT
(
add_sub : IN STD_LOGIC ;
cin : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
cout : OUT STD_LOGIC ;
overflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_add_sub0;
ARCHITECTURE SYN OF lpm_add_sub0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC (
lpm_direction : STRING;
lpm_hint : STRING;
lpm_representation : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
dataa : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
add_sub : IN STD_LOGIC ;
datab : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
overflow : OUT STD_LOGIC ;
cin : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
overflow <= sub_wire0;
cout <= sub_wire1;
result <= sub_wire2(3 DOWNTO 0);
lpm_add_sub_component : lpm_add_sub
GENERIC MAP (
lpm_direction => "UNUSED",
lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES",
lpm_representation => "UNSIGNED",
lpm_type => "LPM_ADD_SUB",
lpm_width => 4
)
PORT MAP (
dataa => dataa,
add_sub => add_sub,
datab => datab,
cin => cin,
overflow => sub_wire0,
cout => sub_wire1,
result => sub_wire2
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: CarryIn NUMERIC "1"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: ConstantA NUMERIC "0"
-- Retrieval info: PRIVATE: ConstantB NUMERIC "0"
-- Retrieval info: PRIVATE: Function NUMERIC "2"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
-- Retrieval info: PRIVATE: Latency NUMERIC "0"
-- Retrieval info: PRIVATE: Overflow NUMERIC "1"
-- Retrieval info: PRIVATE: RadixA NUMERIC "10"
-- Retrieval info: PRIVATE: RadixB NUMERIC "10"
-- Retrieval info: PRIVATE: Representation NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
-- Retrieval info: PRIVATE: aclr NUMERIC "0"
-- Retrieval info: PRIVATE: clken NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: add_sub 0 0 0 0 INPUT NODEFVAL add_sub
-- Retrieval info: USED_PORT: cin 0 0 0 0 INPUT NODEFVAL cin
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: dataa 0 0 4 0 INPUT NODEFVAL dataa[3..0]
-- Retrieval info: USED_PORT: datab 0 0 4 0 INPUT NODEFVAL datab[3..0]
-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT NODEFVAL overflow
-- Retrieval info: USED_PORT: result 0 0 4 0 OUTPUT NODEFVAL result[3..0]
-- Retrieval info: CONNECT: @add_sub 0 0 0 0 add_sub 0 0 0 0
-- Retrieval info: CONNECT: result 0 0 4 0 @result 0 0 4 0
-- Retrieval info: CONNECT: @dataa 0 0 4 0 dataa 0 0 4 0
-- Retrieval info: CONNECT: @datab 0 0 4 0 datab 0 0 4 0
-- Retrieval info: CONNECT: @cin 0 0 0 0 cin 0 0 0 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_add_sub0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 | 6f6ef0a901c9555bfc63fdea2a553e2a | 0.659668 | 3.472053 | false | false | false | false |
peteut/nvc | test/regress/issue354.vhd | 2 | 491 | entity issue354 is
end issue354;
architecture behav of issue354 is
signal byte : bit_vector(7 downto 0);
signal byte_too : bit_vector(7 downto 0);
begin
-- nvc doesn't like the byte_too(1) in the next line
byte(1 downto 0) <= (1 => byte_too(1), 0 => '0') when true else (others => '0');
process
begin
byte_too(0) <= '0';
byte_too(1) <= '1';
wait for 100ns;
assert byte(0) = '0';
assert byte(1) = '1';
assert false report "end of test" severity note;
wait;
end process;
end behav;
| gpl-3.0 | 7b1c481ccec196bd3dc07814ec57a00a | 0.657841 | 2.758427 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_tb.vhd | 1 | 6,119 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
ENTITY rd_fifo_256to64_tb IS
END ENTITY;
ARCHITECTURE rd_fifo_256to64_arch OF rd_fifo_256to64_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from rd_fifo_256to64_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of rd_fifo_256to64_synth
rd_fifo_256to64_synth_inst:rd_fifo_256to64_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 68
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | 60bafffb73f15afd96d7caf50711cd61 | 0.616604 | 4.060385 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/adder_subtractor_component_for_multiplier.vhd | 1 | 1,724 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 09-04-2017
-- Package Name: alu/components
-- Module Name: ADDER_SUBTRACTOR_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ADDER_SUBTRACTOR_COMPONENT_MULTIPLIER is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(8 - 1 downto 0);
INPUT2 : in std_logic_vector(8 - 1 downto 0);
IS_SUB : in std_logic; -- 0 for add and 1 for subtraction
SUM : out std_logic_vector(8 - 1 downto 0);
CARRY : out std_logic
);
end entity;
architecture ADDER_SUBTRACTOR_COMPONENT_MULTIPLIER_ARCH of ADDER_SUBTRACTOR_COMPONENT_MULTIPLIER is
component FULL_ADDER is
port(
CIN : in std_logic;
A : in std_logic;
B : in std_logic;
SUM : out std_logic;
CARRY : out std_logic
);
end component;
signal CARRIES : std_logic_vector(16 downto 0);
signal B_MUXED : std_logic_vector(16 - 1 downto 0);
begin
CARRIES(0) <= IS_SUB xor CARRY_IN;
GENERATING_B:
for I in INPUT2'range generate
with IS_SUB select B_MUXED(I) <=
INPUT2(I) when '0',
not INPUT2(I) when '1',
INPUT2(I) when others;
end generate;
ADDERS_CONNECTING:
for I in INPUT1'range generate
ADDER_X: FULL_ADDER
port map(
CIN => CARRIES(I),
A => INPUT1(I),
B => B_MUXED(I),
SUM => SUM(I),
CARRY => CARRIES(I + 1)
);
end generate;
CARRY <= CARRIES(8 - 1) xor CARRIES(8);
end architecture; | gpl-3.0 | cbe758c9e8574d32d4864ded95cb8afc | 0.527262 | 3.180812 | false | false | false | false |
peteut/nvc | test/regress/issue106.vhd | 2 | 3,450 | -- sliced_array.vhdl
use std.textio.all;
package foo_const is
constant foo1_c : integer := 0;
constant foo2_c : integer := 7;
constant addr1_c : bit_vector(foo2_c downto foo1_c) := x"02";
constant addr2_c : bit_vector(foo2_c downto foo1_c) := x"03";
constant addr3_c : bit_vector(foo2_c downto foo1_c) := x"04";
end foo_const;
use std.textio.all;
use work.foo_const.all;
entity SLICED_ARRAY is
port( IN1 : in bit_vector(7 downto 0);
OUT1 : out bit_vector(7 downto 0) );
end SLICED_ARRAY;
architecture BEHAVIOUR of SLICED_ARRAY is
begin
PR1:
process( IN1 )
variable l : line;
begin
case IN1 is
-- when addr1_c => write(l, string'("OK")); writeline(output, l); -- OK
when addr2_c(7 downto 0) => write(l, string'("OK addr2_c")); writeline(output, l); -- fails
when addr3_c(foo2_c downto foo1_c) => write(l, string'("OK addr3_c")); writeline(output, l); -- fails
when others => write(l, string'("other")); writeline(output, l);
end case;
end process;
end BEHAVIOUR;
-------------------------------------------------------------------------------
-- sliced_array_test.vhdl
use std.textio.all;
entity issue106 is
begin
end entity issue106 ;
architecture BEHAVIOUR of issue106 is
component SLICED_ARRAY is
port( IN1 : in bit_vector(7 downto 0);
OUT1 : out bit_vector(7 downto 0) );
end component SLICED_ARRAY;
signal S1 : bit_vector(7 downto 0);
signal S2 : bit_vector(7 downto 0);
begin
SLICED_ARRAY_INST : SLICED_ARRAY
port map ( IN1 => S1,
OUT1 => S2 );
process
variable l : line;
begin
S1 <= x"10";
wait for 1 ns;
S1 <= x"03";
wait for 1 ns;
S1 <= x"04";
wait;
end process;
other: process is
constant c1 : bit_vector(7 downto 0) := "11110000";
constant c2 : bit_vector(0 to 7) := "11001100";
constant c3 : bit_vector(15 downto 8) := "11110000";
variable v1, v2, v3 : bit_vector(3 downto 0);
begin
v1 := "1100";
case v1 is
when c1(5 downto 2) => report "ok1";
when others => assert false;
end case;
v1 := "1111";
case v1 is
when c1(7 downto 4) => report "ok2";
when others => assert false;
end case;
v2 := "1100";
case v2 is
when c2(4 to 7) => report "ok3";
when others => assert false;
end case;
v2 := "0110";
case v2 is
when c2(3 to 6) => report "ok4";
when others => assert false;
end case;
v3 := "1100";
case v3 is
when c3(13 downto 10) => report "ok5";
when others => assert false;
end case;
v3 := "1111";
case v3 is
when c3(15 downto 12) => report "ok6";
when others => assert false;
end case;
wait;
end process;
end architecture BEHAVIOUR;
| gpl-3.0 | 5b6c30de32d0bc6e23fe3282a718ca81 | 0.467246 | 3.916005 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_pctrl.vhd | 1 | 18,552 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo8to32_pkg.ALL;
ENTITY fifo8to32_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fifo8to32_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fifo8to32_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fifo8to32_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | 973c72af50bc115b6f23eb6cb2a980d7 | 0.509217 | 3.238827 | false | false | false | false |
peteut/nvc | test/regress/issue376.vhd | 2 | 1,950 | entity decoder is
port(
i_bcd : in bit_vector(3 downto 0); -- bcd input
o_display : out bit_vector(6 downto 0) -- display output
);
end entity;
library ieee;
use ieee.numeric_bit.all;
architecture rtl of decoder is
constant D_ZERO : bit_vector(6 downto 0) := "1111110";
constant D_ONE : bit_vector(6 downto 0) := "0110000";
constant D_TWO : bit_vector(6 downto 0) := "1101101";
constant D_THREE : bit_vector(6 downto 0) := "1111001";
constant D_FOUR : bit_vector(6 downto 0) := "0110011";
constant D_FIVE : bit_vector(6 downto 0) := "1011011";
constant D_SIX : bit_vector(6 downto 0) := "1011111";
constant D_SEVEN : bit_vector(6 downto 0) := "1110000";
constant D_EIGHT : bit_vector(6 downto 0) := "1111111";
constant D_NINE : bit_vector(6 downto 0) := "1111011";
constant D_E : bit_vector(6 downto 0) := "1111001";
type t_decoder_arr is array (0 to 15) of bit_vector(6 downto 0);
constant decoder_arr : t_decoder_arr := (D_ZERO, D_ONE, D_TWO, D_THREE, D_FOUR, D_FIVE,
D_SIX, D_SEVEN, D_EIGHT, D_NINE, D_E, D_E, D_E, D_E, D_E, D_E);
begin -- architecture
with to_integer(unsigned(i_bcd)) select
o_display <=
decoder_arr(to_integer(unsigned(i_bcd))) when 0 to 15,
D_E when others;
end architecture;
-------------------------------------------------------------------------------
entity issue376 is
end entity;
architecture test of issue376 is
signal i_bcd : bit_vector(3 downto 0);
signal o_display : bit_vector(6 downto 0);
begin
decoder_1: entity work.decoder
port map (
i_bcd => i_bcd,
o_display => o_display);
process is
begin
i_bcd <= "0000";
wait for 1 ns;
assert o_display = "1111110";
i_bcd <= "0001";
wait for 1 ns;
assert o_display = "0110000";
wait;
end process;
end architecture;
| gpl-3.0 | a1913015e973d2ec5c09a2f242d88493 | 0.571282 | 3.244592 | false | false | false | false |
esar/hdmilight-v1 | fpga/avr/alu.vhd | 3 | 19,226 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: alu - Behavioral
-- Create Date: 13:51:24 11/07/2009
-- Description: arithmetic logic unit of a CPU
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
use work.common.ALL;
entity alu is
port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_D : in std_logic_vector(15 downto 0);
I_D0 : in std_logic;
I_DIN : in std_logic_vector( 7 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector( 7 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_R : in std_logic_vector(15 downto 0);
I_R0 : in std_logic;
I_RSEL : in std_logic_vector( 1 downto 0);
Q_FLAGS : out std_logic_vector( 9 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end alu;
architecture Behavioral of alu is
function ze(A: std_logic_vector(7 downto 0)) return std_logic is
begin
return not (A(0) or A(1) or A(2) or A(3) or
A(4) or A(5) or A(6) or A(7));
end;
function cy_add(Rd, Rr, R: std_logic) return std_logic is
begin
return (Rd and Rr) or (Rd and (not R)) or ((not R) and Rr);
end;
function ov_add(Rd, Rr, R: std_logic) return std_logic is
begin
return (Rd and Rr and (not R)) or ((not Rd) and (not Rr) and R);
end;
function si_add(Rd, Rr, R: std_logic) return std_logic is
begin
return R xor ov_add(Rd, Rr, R);
end;
function cy_sub(Rd, Rr, R: std_logic) return std_logic is
begin
return ((not Rd) and Rr) or (Rr and R) or (R and (not Rd));
end;
function ov_sub(Rd, Rr, R: std_logic) return std_logic is
begin
return (Rd and (not Rr) and (not R)) or ((not Rd) and Rr and R);
end;
function si_sub(Rd, Rr, R: std_logic) return std_logic is
begin
return R xor ov_sub(Rd, Rr, R);
end;
signal L_ADC_DR : std_logic_vector( 7 downto 0); -- D + R + Carry
signal L_ADD_DR : std_logic_vector( 7 downto 0); -- D + R
signal L_ADIW_D : std_logic_vector(15 downto 0); -- D + IMM
signal L_AND_DR : std_logic_vector( 7 downto 0); -- D and R
signal L_ASR_D : std_logic_vector( 7 downto 0); -- (signed D) >> 1
signal L_D8 : std_logic_vector( 7 downto 0); -- D(7 downto 0)
signal L_DEC_D : std_logic_vector( 7 downto 0); -- D - 1
signal L_DOUT : std_logic_vector(15 downto 0);
signal L_INC_D : std_logic_vector( 7 downto 0); -- D + 1
signal L_LSR_D : std_logic_vector( 7 downto 0); -- (unsigned) D >> 1
signal L_MASK_I : std_logic_vector( 7 downto 0); -- 1 << IMM
signal L_NEG_D : std_logic_vector( 7 downto 0); -- 0 - D
signal L_NOT_D : std_logic_vector( 7 downto 0); -- 0 not D
signal L_OR_DR : std_logic_vector( 7 downto 0); -- D or R
signal L_PROD : std_logic_vector(17 downto 0); -- D * R
signal L_R8 : std_logic_vector( 7 downto 0); -- odd or even R
signal L_RI8 : std_logic_vector( 7 downto 0); -- R8 or IMM
signal L_RBIT : std_logic;
signal L_SBIW_D : std_logic_vector(15 downto 0); -- D - IMM
signal L_ROR_D : std_logic_vector( 7 downto 0); -- D rotated right
signal L_SBC_DR : std_logic_vector( 7 downto 0); -- D - R - Carry
signal L_SIGN_D : std_logic;
signal L_SIGN_R : std_logic;
signal L_SUB_DR : std_logic_vector( 7 downto 0); -- D - R
signal L_SWAP_D : std_logic_vector( 7 downto 0); -- D swapped
signal L_XOR_DR : std_logic_vector( 7 downto 0); -- D xor R
begin
dinbit: process(I_DIN, I_BIT(2 downto 0))
begin
case I_BIT(2 downto 0) is
when "000" => L_RBIT <= I_DIN(0); L_MASK_I <= "00000001";
when "001" => L_RBIT <= I_DIN(1); L_MASK_I <= "00000010";
when "010" => L_RBIT <= I_DIN(2); L_MASK_I <= "00000100";
when "011" => L_RBIT <= I_DIN(3); L_MASK_I <= "00001000";
when "100" => L_RBIT <= I_DIN(4); L_MASK_I <= "00010000";
when "101" => L_RBIT <= I_DIN(5); L_MASK_I <= "00100000";
when "110" => L_RBIT <= I_DIN(6); L_MASK_I <= "01000000";
when others => L_RBIT <= I_DIN(7); L_MASK_I <= "10000000";
end case;
end process;
process(L_ADC_DR, L_ADD_DR, L_ADIW_D, I_ALU_OP, L_AND_DR, L_ASR_D,
I_BIT, I_D, L_D8, L_DEC_D, I_DIN, I_FLAGS, I_IMM, L_MASK_I,
L_INC_D, L_LSR_D, L_NEG_D, L_NOT_D, L_OR_DR, I_PC, L_PROD,
I_R, L_RI8, L_RBIT, L_ROR_D, L_SBIW_D, L_SUB_DR, L_SBC_DR,
L_SIGN_D, L_SIGN_R, L_SWAP_D, L_XOR_DR)
begin
Q_FLAGS(9) <= L_RBIT xor not I_BIT(3); -- DIN[BIT] = BIT[3]
Q_FLAGS(8) <= ze(L_SUB_DR); -- D == R for CPSE
Q_FLAGS(7 downto 0) <= I_FLAGS;
L_DOUT <= X"0000";
case I_ALU_OP is
when ALU_ADC =>
L_DOUT <= L_ADC_DR & L_ADC_DR;
Q_FLAGS(0) <= cy_add(L_D8(7), L_RI8(7), L_ADC_DR(7));-- Carry
Q_FLAGS(1) <= ze(L_ADC_DR); -- Zero
Q_FLAGS(2) <= L_ADC_DR(7); -- Negative
Q_FLAGS(3) <= ov_add(L_D8(7), L_RI8(7), L_ADC_DR(7));-- Overflow
Q_FLAGS(4) <= si_add(L_D8(7), L_RI8(7), L_ADC_DR(7));-- Signed
Q_FLAGS(5) <= cy_add(L_D8(3), L_RI8(3), L_ADC_DR(3));-- Halfcarry
when ALU_ADD =>
L_DOUT <= L_ADD_DR & L_ADD_DR;
Q_FLAGS(0) <= cy_add(L_D8(7), L_RI8(7), L_ADD_DR(7));-- Carry
Q_FLAGS(1) <= ze(L_ADD_DR); -- Zero
Q_FLAGS(2) <= L_ADD_DR(7); -- Negative
Q_FLAGS(3) <= ov_add(L_D8(7), L_RI8(7), L_ADD_DR(7));-- Overflow
Q_FLAGS(4) <= si_add(L_D8(7), L_RI8(7), L_ADD_DR(7));-- Signed
Q_FLAGS(5) <= cy_add(L_D8(3), L_RI8(3), L_ADD_DR(3));-- Halfcarry
when ALU_ADIW =>
L_DOUT <= L_ADIW_D;
Q_FLAGS(0) <= L_ADIW_D(15) and not I_D(15); -- Carry
Q_FLAGS(1) <= ze(L_ADIW_D(15 downto 8)) and
ze(L_ADIW_D(7 downto 0)); -- Zero
Q_FLAGS(2) <= L_ADIW_D(15); -- Negative
Q_FLAGS(3) <= I_D(15) and not L_ADIW_D(15); -- Overflow
Q_FLAGS(4) <= (L_ADIW_D(15) and not I_D(15))
xor (I_D(15) and not L_ADIW_D(15)); -- Signed
when ALU_AND =>
L_DOUT <= L_AND_DR & L_AND_DR;
Q_FLAGS(1) <= ze(L_AND_DR); -- Zero
Q_FLAGS(2) <= L_AND_DR(7); -- Negative
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= L_AND_DR(7); -- Signed
when ALU_ASR =>
L_DOUT <= L_ASR_D & L_ASR_D;
Q_FLAGS(0) <= L_D8(0); -- Carry
Q_FLAGS(1) <= ze(L_ASR_D); -- Zero
Q_FLAGS(2) <= L_D8(7); -- Negative
Q_FLAGS(3) <= L_D8(0) xor L_D8(7); -- Overflow
Q_FLAGS(4) <= L_D8(0); -- Signed
when ALU_BLD => -- copy T flag to DOUT
case I_BIT(2 downto 0) is
when "000" => L_DOUT( 0) <= I_FLAGS(6);
L_DOUT( 8) <= I_FLAGS(6);
when "001" => L_DOUT( 1) <= I_FLAGS(6);
L_DOUT( 9) <= I_FLAGS(6);
when "010" => L_DOUT( 2) <= I_FLAGS(6);
L_DOUT(10) <= I_FLAGS(6);
when "011" => L_DOUT( 3) <= I_FLAGS(6);
L_DOUT(11) <= I_FLAGS(6);
when "100" => L_DOUT( 4) <= I_FLAGS(6);
L_DOUT(12) <= I_FLAGS(6);
when "101" => L_DOUT( 5) <= I_FLAGS(6);
L_DOUT(13) <= I_FLAGS(6);
when "110" => L_DOUT( 6) <= I_FLAGS(6);
L_DOUT(14) <= I_FLAGS(6);
when others => L_DOUT( 7) <= I_FLAGS(6);
L_DOUT(15) <= I_FLAGS(6);
end case;
when ALU_BIT_CS => -- copy I_DIN to T flag
Q_FLAGS(6) <= L_RBIT xor not I_BIT(3);
if (I_BIT(3) = '0') then -- clear
L_DOUT(15 downto 8) <= I_DIN and not L_MASK_I;
L_DOUT( 7 downto 0) <= I_DIN and not L_MASK_I;
else -- set
L_DOUT(15 downto 8) <= I_DIN or L_MASK_I;
L_DOUT( 7 downto 0) <= I_DIN or L_MASK_I;
end if;
when ALU_COM =>
L_DOUT <= L_NOT_D & L_NOT_D;
Q_FLAGS(0) <= '1'; -- Carry
Q_FLAGS(1) <= ze(not L_D8); -- Zero
Q_FLAGS(2) <= not L_D8(7); -- Negative
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= not L_D8(7); -- Signed
when ALU_DEC =>
L_DOUT <= L_DEC_D & L_DEC_D;
Q_FLAGS(1) <= ze(L_DEC_D); -- Zero
Q_FLAGS(2) <= L_DEC_D(7); -- Negative
if (L_D8 = X"80") then
Q_FLAGS(3) <= '1'; -- Overflow
Q_FLAGS(4) <= not L_DEC_D(7); -- Signed
else
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= L_DEC_D(7); -- Signed
end if;
when ALU_EOR =>
L_DOUT <= L_XOR_DR & L_XOR_DR;
Q_FLAGS(1) <= ze(L_XOR_DR); -- Zero
Q_FLAGS(2) <= L_XOR_DR(7); -- Negative
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= L_XOR_DR(7); -- Signed
when ALU_INC =>
L_DOUT <= L_INC_D & L_INC_D;
Q_FLAGS(1) <= ze(L_INC_D); -- Zero
Q_FLAGS(2) <= L_INC_D(7); -- Negative
if (L_D8 = X"7F") then
Q_FLAGS(3) <= '1'; -- Overflow
Q_FLAGS(4) <= not L_INC_D(7); -- Signed
else
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= L_INC_D(7); -- Signed
end if;
when ALU_INTR =>
L_DOUT <= I_PC;
Q_FLAGS(7) <= I_IMM(6); -- ena/disable interrupts
when ALU_LSR =>
L_DOUT <= L_LSR_D & L_LSR_D;
Q_FLAGS(0) <= L_D8(0); -- Carry
Q_FLAGS(1) <= ze(L_LSR_D); -- Zero
Q_FLAGS(2) <= '0'; -- Negative
Q_FLAGS(3) <= L_D8(0); -- Overflow
Q_FLAGS(4) <= L_D8(0); -- Signed
when ALU_D_MV_Q =>
L_DOUT <= L_D8 & L_D8;
when ALU_R_MV_Q =>
L_DOUT <= L_RI8 & L_RI8;
when ALU_MV_16 =>
L_DOUT <= I_R(15 downto 8) & L_RI8;
when ALU_MULT =>
Q_FLAGS(0) <= L_PROD(15); -- Carry
if I_IMM(7) = '0' then -- MUL
L_DOUT <= L_PROD(15 downto 0);
Q_FLAGS(1) <= ze(L_PROD(15 downto 8)) -- Zero
and ze(L_PROD( 7 downto 0));
else -- FMUL
L_DOUT <= L_PROD(14 downto 0) & "0";
Q_FLAGS(1) <= ze(L_PROD(14 downto 7)) -- Zero
and ze(L_PROD( 6 downto 0) & "0");
end if;
when ALU_NEG =>
L_DOUT <= L_NEG_D & L_NEG_D;
Q_FLAGS(0) <= not ze(L_D8); -- Carry
Q_FLAGS(1) <= ze(L_NEG_D); -- Zero
Q_FLAGS(2) <= L_NEG_D(7); -- Negative
if (L_D8 = X"80") then
Q_FLAGS(3) <= '1'; -- Overflow
Q_FLAGS(4) <= not L_NEG_D(7); -- Signed
else
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= L_NEG_D(7); -- Signed
end if;
Q_FLAGS(5) <= L_D8(3) or L_NEG_D(3); -- Halfcarry
when ALU_OR =>
L_DOUT <= L_OR_DR & L_OR_DR;
Q_FLAGS(1) <= ze(L_OR_DR); -- Zero
Q_FLAGS(2) <= L_OR_DR(7); -- Negative
Q_FLAGS(3) <= '0'; -- Overflow
Q_FLAGS(4) <= L_OR_DR(7); -- Signed
when ALU_PC_1 => -- ICALL, RCALL
L_DOUT <= I_PC + X"0001";
when ALU_PC_2 => -- CALL
L_DOUT <= I_PC + X"0002";
when ALU_ROR =>
L_DOUT <= L_ROR_D & L_ROR_D;
Q_FLAGS(0) <= L_D8(0); -- Carry
Q_FLAGS(1) <= ze(L_ROR_D); -- Zero
Q_FLAGS(2) <= I_FLAGS(0); -- Negative
Q_FLAGS(3) <= I_FLAGS(0) xor L_D8(0); -- Overflow
Q_FLAGS(4) <= I_FLAGS(0); -- Signed
when ALU_SBC =>
L_DOUT <= L_SBC_DR & L_SBC_DR;
Q_FLAGS(0) <= cy_sub(L_D8(7), L_RI8(7), L_SBC_DR(7));-- Carry
Q_FLAGS(1) <= ze(L_SBC_DR) and I_FLAGS(1); -- Zero
Q_FLAGS(2) <= L_SBC_DR(7); -- Negative
Q_FLAGS(3) <= ov_sub(L_D8(7), L_RI8(7), L_SBC_DR(7));-- Overflow
Q_FLAGS(4) <= si_sub(L_D8(7), L_RI8(7), L_SBC_DR(7));-- Signed
Q_FLAGS(5) <= cy_sub(L_D8(3), L_RI8(3), L_SBC_DR(3));-- Halfcarry
when ALU_SBIW =>
L_DOUT <= L_SBIW_D;
Q_FLAGS(0) <= L_SBIW_D(15) and not I_D(15); -- Carry
Q_FLAGS(1) <= ze(L_SBIW_D(15 downto 8)) and
ze(L_SBIW_D(7 downto 0)); -- Zero
Q_FLAGS(2) <= L_SBIW_D(15); -- Negative
Q_FLAGS(3) <= I_D(15) and not L_SBIW_D(15); -- Overflow
Q_FLAGS(4) <= (L_SBIW_D(15) and not I_D(15))
xor (I_D(15) and not L_SBIW_D(15)); -- Signed
when ALU_SREG =>
case I_BIT(2 downto 0) is
when "000" => Q_FLAGS(0) <= not I_BIT(3);
when "001" => Q_FLAGS(1) <= not I_BIT(3);
when "010" => Q_FLAGS(2) <= not I_BIT(3);
when "011" => Q_FLAGS(3) <= not I_BIT(3);
when "100" => Q_FLAGS(4) <= not I_BIT(3);
when "101" => Q_FLAGS(5) <= not I_BIT(3);
when "110" => Q_FLAGS(6) <= not I_BIT(3);
when others => Q_FLAGS(7) <= not I_BIT(3);
end case;
when ALU_SUB =>
L_DOUT <= L_SUB_DR & L_SUB_DR;
Q_FLAGS(0) <= cy_sub(L_D8(7), L_RI8(7), L_SUB_DR(7));-- Carry
Q_FLAGS(1) <= ze(L_SUB_DR); -- Zero
Q_FLAGS(2) <= L_SUB_DR(7); -- Negative
Q_FLAGS(3) <= ov_sub(L_D8(7), L_RI8(7), L_SUB_DR(7));-- Overflow
Q_FLAGS(4) <= si_sub(L_D8(7), L_RI8(7), L_SUB_DR(7));-- Signed
Q_FLAGS(5) <= cy_sub(L_D8(3), L_RI8(3), L_SUB_DR(3));-- Halfcarry
when ALU_SWAP =>
L_DOUT <= L_SWAP_D & L_SWAP_D;
when others =>
end case;
end process;
L_D8 <= I_D(15 downto 8) when (I_D0 = '1') else I_D(7 downto 0);
L_R8 <= I_R(15 downto 8) when (I_R0 = '1') else I_R(7 downto 0);
L_RI8 <= I_IMM when (I_RSEL = RS_IMM) else L_R8;
L_ADIW_D <= I_D + ("0000000000" & I_IMM(5 downto 0));
L_SBIW_D <= I_D - ("0000000000" & I_IMM(5 downto 0));
L_ADD_DR <= L_D8 + L_RI8;
L_ADC_DR <= L_ADD_DR + ("0000000" & I_FLAGS(0));
L_ASR_D <= L_D8(7) & L_D8(7 downto 1);
L_AND_DR <= L_D8 and L_RI8;
L_DEC_D <= L_D8 - X"01";
L_INC_D <= L_D8 + X"01";
L_LSR_D <= '0' & L_D8(7 downto 1);
L_NEG_D <= X"00" - L_D8;
L_NOT_D <= not L_D8;
L_OR_DR <= L_D8 or L_RI8;
L_PROD <= (L_SIGN_D & L_D8) * (L_SIGN_R & L_R8);
L_ROR_D <= I_FLAGS(0) & L_D8(7 downto 1);
L_SUB_DR <= L_D8 - L_RI8;
L_SBC_DR <= L_SUB_DR - ("0000000" & I_FLAGS(0));
L_SIGN_D <= L_D8(7) and I_IMM(6);
L_SIGN_R <= L_R8(7) and I_IMM(5);
L_SWAP_D <= L_D8(3 downto 0) & L_D8(7 downto 4);
L_XOR_DR <= L_D8 xor L_R8;
Q_DOUT <= (I_DIN & I_DIN) when (I_RSEL = RS_DIN) else L_DOUT;
end Behavioral;
| gpl-2.0 | 4b8c51d2c794acca83a1db011b07c925 | 0.389108 | 3.222595 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/simulation/bmg_stim_gen.vhd | 1 | 16,116 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENB : OUT STD_LOGIC :='0';
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(16,16);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(8192,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEB_VCC: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEB_GND: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(12 DOWNTO 0) <= WRITE_ADDR_A(12 DOWNTO 0);
READ_ADDR_INT_A(12 DOWNTO 0) <= READ_ADDR_A(12 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(12 DOWNTO 0) <= WRITE_ADDR_B(12 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(12 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(12 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>8192 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 8192 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH => 16,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH =>16 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
ENA <= DO_READ_A OR DO_WRITE_A ;
ENB <= DO_READ_B OR DO_WRITE_B ;
WEA <= IF_THEN_ELSE(DO_WRITE_A='1', WEA_VCC,WEA_GND) ;
WEB <= IF_THEN_ELSE(DO_WRITE_B='1', WEB_VCC,WEB_GND) ;
END ARCHITECTURE;
| bsd-3-clause | a1e89ccb7fe48c23e9f126b161e69f12 | 0.576136 | 3.204613 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/hidden_layer_tb.vhd | 1 | 2,431 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.custom_pkg.all;
ENTITY hidden_layer_tb IS
END hidden_layer_tb;
ARCHITECTURE behavior OF hidden_layer_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT hidden_layer
PORT(
clk : IN std_logic;
num_operations : IN std_logic_vector(7 downto 0);
layer : IN layer_type;
rst : IN std_logic;
input : IN std_logic_vector(7 downto 0);
weight : IN eight_bit(2 downto 0);
shift_over_flag : out std_logic;
active_activation: out std_logic;
output_hid : OUT eight_bit(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal num_operations : std_logic_vector(7 downto 0) := (others => '0');
signal layer : layer_type := idle;
signal rst : std_logic := '0';
signal input : std_logic_vector(7 downto 0) := (others => '0');
signal weight : eight_bit(2 downto 0) := ((others=> (others=>'0')));
--Outputs
signal output_hid : eight_bit(2 downto 0);
signal active_activation : std_logic;
signal shift_over_flag : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: hidden_layer PORT MAP (
clk => clk,
num_operations => num_operations,
layer => layer,
rst => rst,
input => input,
weight => weight,
active_activation => active_activation,
shift_over_flag => shift_over_flag,
output_hid => output_hid
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
wait for 5 ns;
num_operations <= "00000100";
layer <= weighted_sum_layer1;
input <= "00001010";
weight(0) <= "00001010";
weight(1) <= "00001110";
weight(2) <= "00001111";
wait for clk_period;
input <= "00011010";
wait for clk_period;
input <= "00101010";
wait for clk_period;
input <= "00101110";
wait for clk_period;
input <= "00000000";
wait for clk_period;
-- wait for 5 ns;
layer <= idle;
wait;
end process;
END;
| bsd-2-clause | edec4adee8f60e2079d1fea6c5ef8307 | 0.582888 | 3.580265 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_tb.vhd | 1 | 5,767 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
ENTITY k7_mBuf_128x72_tb IS
END ENTITY;
ARCHITECTURE k7_mBuf_128x72_arch OF k7_mBuf_128x72_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 2100 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from k7_mBuf_128x72_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of k7_mBuf_128x72_synth
k7_mBuf_128x72_synth_inst:k7_mBuf_128x72_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 75
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | f0febc26e1e2ea46037fd53de2d95c14 | 0.620427 | 4.075618 | false | false | false | false |
peteut/nvc | test/regress/func8.vhd | 2 | 627 | entity func8 is
end entity;
architecture test of func8 is
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
end function;
begin
process is
variable x : integer;
begin
x := 0;
wait for 0 ns;
assert lookup(x) = 0.62; -- Avoid constant folding
x := 2;
wait for 0 ns;
assert lookup(x) = 71.7;
wait;
end process;
end architecture;
| gpl-3.0 | 98a2061efe1ec3e28a4d881621a5e697 | 0.555024 | 3.645349 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/dac.vhd | 1 | 6,773 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : dac.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-05
-- Last update: 2018-04-26
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: DAC driver
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-05 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity dac is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
dac_ena : in std_logic;
dac_tri : in std_logic;
dac_val : in std_logic_vector(15 downto 0);
dac_sclk : OUT std_logic;
dac_cs_n : OUT std_logic;
dac_sin : OUT std_logic
);
end dac;
architecture rtl of dac is
signal trig : std_logic;
SIGNAL bit_sr : std_logic_vector(15 downto 0);
SIGNAL bit_cnt : std_logic_vector(4 downto 0);
signal finish : std_logic;
signal cs : std_logic;
signal sclk : std_logic;
signal sin : std_logic;
signal iob_rst_n : std_logic;
SIGNAL dac_sclk_o : std_logic;
SIGNAL dac_cs_n_o : std_logic;
SIGNAL dac_sin_o : std_logic;
SIGNAL dac_sclk_t : std_logic;
SIGNAL dac_cs_n_t : std_logic;
SIGNAL dac_sin_t : std_logic;
attribute keep : string;
attribute keep of iob_rst_n : signal is "true";
attribute IOB : string;
attribute IOB of dac_sclk_t : signal is "true";
attribute IOB of dac_cs_n_t : signal is "true";
attribute IOB of dac_sin_t : signal is "true";
attribute IOB of dac_sclk_o : signal is "true";
attribute IOB of dac_cs_n_o : signal is "true";
attribute IOB of dac_sin_o : signal is "true";
begin
-- 16-Bit DAC DAC8830ICD (Updates on dac_cs_n rising edge)
-- _______ ______
-- dac_cs_n |_____________ ______________|
-- _______ _____ _____ _ __ _____ _____ _______
-- dac_sin _______X_____X_____X_ __X_____X_____X_______
-- __ __ __ __ __
-- dac_sclk __________| |__| |_ |__| |__| |_______
--
-- Bit 15 14 .. 1 0
--
-- Start triggering, update DAC once per second
dac_trig:
process (rst_n, clk) is
begin
if (rst_n = '0') then
trig <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
if (dac_ena = '0') then
trig <= '0';
elsif (tsc_1pps = '1') then
trig <= '1';
elsif (finish = '1') then
trig <= '0';
end if;
end if;
end if;
end process;
-- bit counter
dac_cnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_cnt <= (others => '0');
finish <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
if (dac_ena = '0') then
bit_cnt <= (others => '0');
finish <= '0';
else
if (trig = '0') then
bit_cnt <= (others => '0');
else
bit_cnt <= bit_cnt + 1;
end if;
if (trig = '0') then
finish <= '0';
elsif (bit_cnt = 30) then
finish <= '1';
else
finish <= '0';
end if;
end if;
end if;
end if;
end process;
-- Generate DAC control signals
dac_sr:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_sr <= (others => '0');
cs <= '1';
sclk <= '0';
sin <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
if (dac_ena = '0') then
bit_sr <= (others => '0');
elsif (tsc_1pps = '1') then
bit_sr <= dac_val;
elsif (bit_cnt(0) = '1') then
bit_sr <= bit_sr(bit_sr'left - 1 downto 0) & '0';
end if;
cs <= not trig;
sclk <= bit_cnt(0);
sin <= bit_sr(bit_sr'left);
end if;
end if;
end process;
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- Written to allow for attributes for force the use of IOB registers.
-- The control signals (preset) can not be on a separate fanout.
-- The IOB attribute also seems to force the synthesizer to keep the
-- duplicate tri-state control registers.
iob_rst_n <= rst_n;
-- Final output register
-- Tristate IOB register for dac output
dac_tri_oreg:
process (iob_rst_n, clk) is
begin
if (iob_rst_n = '0') then
dac_sclk_t <= '1';
dac_cs_n_t <= '1';
dac_sin_t <= '1';
dac_sclk_o <= '1';
dac_cs_n_o <= '1';
dac_sin_o <= '1';
elsif (clk'event and clk = '1') then
dac_sclk_t <= dac_tri;
dac_cs_n_t <= dac_tri;
dac_sin_t <= dac_tri;
dac_sclk_o <= sclk;
dac_cs_n_o <= cs;
dac_sin_o <= sin;
end if;
end process;
dac_cs_n <= dac_cs_n_o when dac_cs_n_t = '0' else 'Z';
dac_sclk <= dac_sclk_o when dac_sclk_t = '0' else 'Z';
dac_sin <= dac_sin_o when dac_sin_t = '0' else 'Z';
-- ----------------------------------------------------------------------
-- ----------------------------------------------------------------------
end rtl;
| gpl-3.0 | bbd02704b8b3d7c7a8d65be423210eda | 0.37369 | 4.019585 | false | false | false | false |
UnofficialRepos/OSVVM | ScoreboardPkg_int.vhd | 2 | 1,903 | --
-- File Name: ScoreBoardPkg_int.vhd
-- Design Unit Name: ScoreBoardPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Instance of Generic Package ScoreboardGenericPkg for integer
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 08/2012 2012.08 Generic Instance of ScoreboardGenericPkg
-- 08/2014 2013.08 Updated interface for Match and to_string
-- 11/2016 2016.11 Released as part of OSVVM library
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package ScoreBoardPkg_int is new work.ScoreboardGenericPkg
generic map (
ExpectedType => integer,
ActualType => integer,
Match => "=",
expected_to_string => to_string,
actual_to_string => to_string
) ;
| artistic-2.0 | fa8390de0594d5bcf8d72abbcdb0e333 | 0.64372 | 3.753452 | false | false | false | false |
peteut/nvc | test/regress/issue367.vhd | 2 | 705 | package r is
function r1(a:bit_vector) return bit_vector;
end package;
package body r is
function r1(a:bit_vector) return bit_vector is
variable ret : bit_vector(a'range);
variable i : integer range a'range; -- Error here
begin
loop
report integer'image(i);
ret(i) := not a(i);
exit when i = i'right;
i := i + 1;
end loop;
return ret;
end r1;
end r;
entity issue367 is
end entity;
use work.r.r1;
architecture test of issue367 is
begin
process is
variable b : bit_vector(1 to 3) := "101";
begin
assert r1(b) = "010";
wait;
end process;
end architecture;
| gpl-3.0 | b817b04563832622bd3417038c32a8b6 | 0.561702 | 3.455882 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_dgen.vhd | 1 | 4,560 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
ENTITY k7_sfifo_15x128_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF k7_sfifo_15x128_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:k7_sfifo_15x128_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 41f955cf4a8653021831364b1ed53506 | 0.601535 | 4.160584 | false | false | false | false |
peteut/nvc | test/sem/real.vhd | 1 | 921 | entity e is
end entity;
architecture a of e is
signal x : real := 1.234; -- OK
type my_real is range 0.0 to 1.0; -- OK
begin
process is
variable v : my_real;
begin
x <= x + 6.1215; -- OK
x <= v; -- Error
end process;
process is
variable i : integer;
begin
i := integer(x); -- OK
x <= real(i); -- OK
x <= real(5); -- OK
x <= real(bit'('1')); -- Error
end process;
process is
variable x : real;
begin
x := real'left; -- OK
x := real'right; -- OK
end process;
process is
constant i : integer := 5;
constant r : real := 252.4;
type t is range i to r; -- Error
begin
end process;
end architecture;
| gpl-3.0 | f3a6a2bedfea5c8b43871294b96d64dc | 0.404995 | 4.148649 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/test_image/example_design/test_image_exdes.vhd | 1 | 4,621 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: test_image_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY test_image_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END test_image_exdes;
ARCHITECTURE xilinx OF test_image_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT test_image IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : test_image
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| bsd-2-clause | 4b9de37211135f8208c8a1dfb8a71cde | 0.56741 | 4.729785 | false | false | false | false |
peteut/nvc | test/regress/issue338b.vhd | 2 | 672 | entity issue338b is
end entity;
architecture a of issue338b is
begin
main : process
procedure proc(s : string; variable value : out integer) is
begin
if s = "" then
value := 0;
else
value := 1;
end if;
end;
function func(s : string) return integer is
begin
if s = "" then
return 0;
end if;
return 1;
end;
constant s1 : string := "foobar";
constant s0 : string := "";
variable value : integer;
begin
assert func(s1) = 1;
assert func(s0) = 0;
proc(s1, value);
assert value = 1;
proc(s0, value);
assert value = 0;
wait;
end process;
end;
| gpl-3.0 | 2c538e051b579297f944ca8e9a77685a | 0.549107 | 3.632432 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/adau1761_audio.vhd | 2 | 18,133 | ------------------------------------------------------------------------------
-- adau1761_audio.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: adau1761_audio.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue May 20 11:28:03 2014 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library adau1761_audio_v1_00_a;
use adau1761_audio_v1_00_a.user_logic;
library unisim;
use unisim.vcomponents.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity adau1761_audio is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
clk_100 : IN std_logic;
clk_48_o : OUT std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
--AC_SDA : INOUT std_logic;
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
AUDIO_OUT_L : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : OUT STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : IN STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : IN STD_LOGIC_VECTOR(23 downto 0);
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
new_sample : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity adau1761_audio;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of adau1761_audio is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 2;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal AC_SDA_tmp : std_logic;
signal clk_48_s : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity adau1761_audio_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
clk_100 => clk_100,
clk_48_o => clk_48_s,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
new_sample => new_sample,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
AUDIO_OUT_L => AUDIO_OUT_L,
AUDIO_OUT_R => AUDIO_OUT_R,
AUDIO_IN_L => AUDIO_IN_L,
AUDIO_IN_R => AUDIO_IN_R,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
clk_48_o <= clk_48_s;
--AC_SDA_tmp <= AC_SDA_I when AC_SDA_T = '0' else 'Z';
--AC_SDA_O <= AC_SDA_tmp;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
| mit | 48fc9fc2044bc4d58898a83dc05356d7 | 0.466387 | 3.97131 | false | false | false | false |
UnofficialRepos/OSVVM | MemoryPkg.vhd | 1 | 58,483 | --
-- File Name: MemoryPkg.vhd
-- Design Unit Name: MemoryPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Description
-- Package defines a protected type, MemoryPType, and methods
-- for efficiently implementing memory data structures
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated NewID with ReportMode, Search, PrintParent. Supports searching for Memory models.
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Refinement to MemRead to return value, X (if X), U (if not initialized)
-- 01/2016 2016.01 Update for buf.all(buf'left)
-- 06/2015 2015.06 Updated for Alerts, ...
-- ... ... Numerous revisions for VHDL Testbenches and Verification
-- 05/2005 0.1 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.numeric_std.all ;
use IEEE.numeric_std_unsigned.all ;
use IEEE.math_real.all ;
use work.TextUtilPkg.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package MemoryPkg is
type MemoryIDType is record
ID : integer_max ;
end record MemoryIDType ;
type MemoryIDArrayType is array (integer range <>) of MemoryIDType ;
constant OSVVM_MEMORY_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
------------------------------------------------------------
impure function NewID (
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return MemoryIDType ;
------------------------------------------------------------
procedure MemWrite (
ID : MemoryIDType ;
Addr : std_logic_vector ;
Data : std_logic_vector
) ;
procedure MemRead (
ID : in MemoryIDType ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead (
ID : MemoryIDType ;
Addr : std_logic_vector
) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase (ID : in MemoryIDType);
------------------------------------------------------------
impure function GetAlertLogID (ID : in MemoryIDType) return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string
) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string
) ;
type MemoryPType is protected
------------------------------------------------------------
impure function NewID (
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return integer ;
------------------------------------------------------------
procedure MemWrite (
ID : integer ;
Addr : std_logic_vector ;
Data : std_logic_vector
) ;
procedure MemRead (
ID : in integer ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead (
ID : integer ;
Addr : std_logic_vector
) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase (ID : integer) ;
impure function GetAlertLogID (ID : integer) return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadH (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileReadB (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteH (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) ;
procedure FileWriteB (
ID : integer ;
FileName : string
) ;
------------------------------------------------------------
-- Destroys the entire data structure
-- Usage: At the end of the simulation to remove all
-- memory used by data structure.
-- Note, a normal simulator does this for you.
-- You only need this if the simulator is broken.
procedure deallocate ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Historical Interface
-- In the new implementation, these use index 1.
-- These are for backward compatibility support
--
-- /////////////////////////////////////////
------------------------------------------------------------
procedure MemInit ( AddrWidth, DataWidth : in integer ) ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) ;
------------------------------------------------------------
procedure MemRead (
Addr : in std_logic_vector ;
Data : out std_logic_vector
) ;
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector ;
------------------------------------------------------------
procedure MemErase ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) ;
procedure SetAlertLogID (Name : string ; ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadH (FileName : string) ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileReadB (FileName : string) ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteH (FileName : string) ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) ;
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) ;
procedure FileWriteB (FileName : string) ;
end protected MemoryPType ;
end MemoryPkg ;
package body MemoryPkg is
constant BLOCK_WIDTH : integer := 10 ;
type MemoryPType is protected body
type MemBlockType is array (integer range <>) of integer ;
type MemBlockPtrType is access MemBlockType ;
type MemArrayType is array (integer range <>) of MemBlockPtrType ;
type MemArrayPtrType is access MemArrayType ;
type FileFormatType is (BINARY, HEX) ;
type MemStructType is record
MemArrayPtr : MemArrayPtrType ;
AddrWidth : integer ;
DataWidth : natural ;
BlockWidth : natural ;
AlertLogID : AlertLogIDType ;
--! removed Name : Line ; -- only in NameStorePType
end record MemStructType ;
-- New Structure
type ItemArrayType is array (integer range <>) of MemStructType ;
type ItemArrayPtrType is access ItemArrayType ;
variable Template : ItemArrayType(1 to 1) := (1 => (NULL, -1, 1, 0, OSVVM_MEMORY_ALERTLOG_ID)) ; -- Work around for QS 2020.04 and 2021.02
constant MEM_STRUCT_PTR_LEFT : integer := Template'left ;
variable MemStructPtr : ItemArrayPtrType := new ItemArrayType'(Template) ;
variable NumItems : integer := 0 ;
-- constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable ItemArrayPtr : InOut ItemArrayPtrType ;
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
-- constant NewNumItems : in integer ;
-- constant CurNumItems : in integer ;
constant MinNumItems : in integer
) is
variable oldItemArrayPtr : ItemArrayPtrType ;
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
-- Array Allocated in declaration to have a single item, but no items (historical mode)
-- if ItemArrayPtr = NULL then
-- ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
-- elsif NewNumItems > ItemArrayPtr'length then
if NewNumItems > ItemArrayPtr'length then
oldItemArrayPtr := ItemArrayPtr ;
ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
ItemArrayPtr.all(1 to NumItems) := oldItemArrayPtr.all(1 to NumItems) ;
deallocate(oldItemArrayPtr) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- PT Local
procedure MemInit (ID : integer ; AddrWidth, DataWidth : integer ) is
------------------------------------------------------------
constant ADJ_BLOCK_WIDTH : integer := minimum(BLOCK_WIDTH, AddrWidth) ;
begin
if AddrWidth <= 0 then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemInit/NewID. AddrWidth = " & to_string(AddrWidth) & " must be > 0.", FAILURE) ;
return ;
end if ;
if DataWidth <= 0 or DataWidth > 31 then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemInit/NewID. DataWidth = " & to_string(DataWidth) & " must be > 0 and <= 31.", FAILURE) ;
return ;
end if ;
MemStructPtr(ID).AddrWidth := AddrWidth ;
MemStructPtr(ID).DataWidth := DataWidth ;
MemStructPtr(ID).BlockWidth := ADJ_BLOCK_WIDTH ;
MemStructPtr(ID).MemArrayPtr := new MemArrayType(0 to 2**(AddrWidth-ADJ_BLOCK_WIDTH)-1) ;
end procedure MemInit ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return integer is
variable NameID : integer ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_MEMORY_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_MEMORY_ALERTLOG_ID, PrintParent) ;
NameID := LocalNameStore.find(Name, ParentID, ResolvedSearch) ;
-- Share the memory if they match
if NameID /= ID_NOT_FOUND.ID then
if MemStructPtr(NumItems).MemArrayPtr /= NULL then
-- Found ID and structure exists, does structure match?
AlertIf(MemStructPtr(NumItems).AlertLogID, AddrWidth /= MemStructPtr(NameID).AddrWidth,
"NewID: AddrWidth: " & to_string(AddrWidth) & " /= Existing AddrWidth: " & to_string(MemStructPtr(NameID).AddrWidth), FAILURE);
AlertIf(MemStructPtr(NumItems).AlertLogID, DataWidth /= MemStructPtr(NameID).DataWidth,
"NewID: DataWidth: " & to_string(DataWidth) & " /= Existing DataWidth: " & to_string(MemStructPtr(NameID).DataWidth), FAILURE);
-- NameStore IDs are issued sequentially and match MemoryID
else
-- Found ID and structure does not exist, Reconstruct Memory
MemInit(NameID, AddrWidth, DataWidth) ;
end if ;
return NameID ;
else
-- Add New Memory to Structure
GrowNumberItems(MemStructPtr, NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
MemStructPtr(NumItems).AlertLogID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
-- Construct Memory, Reports agains AlertLogID
MemInit(NumItems, AddrWidth, DataWidth) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, ResolvedSearch) ;
-- Check NameStore Index vs MemoryIndex
AlertIfNotEqual(MemStructPtr(NumItems).AlertLogID, NameID, NumItems, "MemoryStore, Check Index of LocalNameStore matches MemoryID") ;
return NumItems ;
end if ;
end function NewID ;
------------------------------------------------------------
-- PT Local
impure function IdOutOfRange(
------------------------------------------------------------
constant ID : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_MEMORY_ALERTLOG_ID, ID < MemStructPtr'Low or ID > MemStructPtr'High,
"MemoryPkg." & Name & " ID: " & to_string(ID) &
"is not in the range (" & to_string(MemStructPtr'Low) &
" to " & to_string(MemStructPtr'High) & ")",
FAILURE ) ;
end function IdOutOfRange ;
------------------------------------------------------------
procedure MemWrite (
------------------------------------------------------------
ID : integer ;
Addr : std_logic_vector ;
Data : std_logic_vector
) is
variable BlockWidth : integer ;
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
if IdOutOfRange(ID, "MemWrite") then
return ;
end if ;
BlockWidth := MemStructPtr(ID).BlockWidth ;
-- Check Bounds of Address and if memory is initialized
if Addr'length /= MemStructPtr(ID).AddrWidth then
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Memory not initialized, Write Ignored.", FAILURE) ;
else
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(MemStructPtr(ID).AddrWidth), FAILURE) ;
end if ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= MemStructPtr(ID).DataWidth then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(MemStructPtr(ID).DataWidth), FAILURE) ;
return ;
end if ;
if is_X( Addr ) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemWrite: Address X, Write Ignored.") ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockWidth then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockWidth)) ;
else
BlockAddr := 0 ;
end if ;
-- If empty, allocate a memory block
if (MemStructPtr(ID).MemArrayPtr(BlockAddr) = NULL) then
MemStructPtr(ID).MemArrayPtr(BlockAddr) := new MemBlockType(0 to 2**BlockWidth-1) ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockWidth -1 downto 0)) ;
-- Write to BlockAddr, WordAddr
if (Is_X(Data)) then
MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) := -1 ;
else
MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) := to_integer( Data ) ;
end if ;
end procedure MemWrite ;
------------------------------------------------------------
procedure MemRead (
------------------------------------------------------------
ID : in integer ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) is
variable BlockWidth : integer ;
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
begin
if IdOutOfRange(ID, "MemRead") then
return ;
end if ;
BlockWidth := MemStructPtr(ID).BlockWidth ;
-- Check Bounds of Address and if memory is initialized
if Addr'length /= MemStructPtr(ID).AddrWidth then
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemRead: Memory not initialized. Returning U", FAILURE) ;
else
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemRead: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(MemStructPtr(ID).AddrWidth), FAILURE) ;
end if ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- Check Bounds on Data
if Data'length /= MemStructPtr(ID).DataWidth then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.MemRead: Data'length: " & to_string(Data'length) & " /= Memory Data Width: " & to_string(MemStructPtr(ID).DataWidth), FAILURE) ;
Data := (Data'range => 'U') ;
return ;
end if ;
-- If Addr X, data = X
if is_X( aAddr ) then
Data := (Data'range => 'X') ;
return ;
end if ;
-- Slice out upper address to form block address
if aAddr'high >= BlockWidth then
BlockAddr := to_integer(aAddr(aAddr'high downto BlockWidth)) ;
else
BlockAddr := 0 ;
end if ;
-- Empty Block, return all U
if (MemStructPtr(ID).MemArrayPtr(BlockAddr) = NULL) then
Data := (Data'range => 'U') ;
return ;
end if ;
-- Address of a word within a block
WordAddr := to_integer(aAddr(BlockWidth -1 downto 0)) ;
if MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) >= 0 then
-- Get the Word from the Array
Data := to_slv(MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr), Data'length) ;
elsif MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) = -1 then
-- X in Word, return all X
Data := (Data'range => 'X') ;
else
-- Location Uninitialized, return all X
Data := (Data'range => 'U') ;
end if ;
end procedure MemRead ;
------------------------------------------------------------
impure function MemRead (
ID : integer ;
Addr : std_logic_vector
) return std_logic_vector is
------------------------------------------------------------
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "MemRead function") ;
variable BlockAddr, WordAddr : integer ;
alias aAddr : std_logic_vector (Addr'length-1 downto 0) is Addr ;
--!!Cadence variable Data : std_logic_vector(MemStructPtr(ID).DataWidth-1 downto 0) ;
constant DATA_WIDTH : integer := MemStructPtr(ID).DataWidth ;
variable Data : std_logic_vector(DATA_WIDTH-1 downto 0) ;
begin
MemRead(ID, Addr, Data) ;
return Data ;
end function MemRead ;
------------------------------------------------------------
procedure MemErase(ID : integer) is
-- Erase the memory, but not the array of pointers
------------------------------------------------------------
begin
if IdOutOfRange(ID, "MemErase") then
return ;
end if ;
for BlockAddr in MemStructPtr(ID).MemArrayPtr'range loop
if (MemStructPtr(ID).MemArrayPtr(BlockAddr) /= NULL) then
deallocate (MemStructPtr(ID).MemArrayPtr(BlockAddr)) ;
end if ;
end loop ;
end procedure ;
------------------------------------------------------------
impure function GetAlertLogID (ID : integer) return AlertLogIDType is
------------------------------------------------------------
begin
if IdOutOfRange(ID, "MemErase") then
return ALERTLOG_ID_NOT_FOUND ;
else
return MemStructPtr(ID).AlertLogID ;
end if ;
end function GetAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure FileReadX (
-- Hexadecimal or Binary File Read
------------------------------------------------------------
ID : integer ;
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant DATA_WIDTH : integer := MemStructPtr(ID).DataWidth ;
-- constant TemplateRange : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '0') ;
-- Format:
-- @hh..h -- Address in hex
-- hhh_XX_ZZ -- data values in hex - space delimited
-- "--" or "//" -- comments
file MemFile : text open READ_MODE is FileName ;
variable Addr : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable SmallAddr : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable BigAddr : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable Data : std_logic_vector(DATA_WIDTH - 1 downto 0) ;
variable LineNum : natural ;
variable ItemNum : natural ;
variable AddrInc : std_logic_vector(ADDR_WIDTH - 1 downto 0) ;
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean ;
variable NextChar : character ;
variable StrLen : integer ;
begin
MultiLineComment := FALSE ;
if StartAddr'length /= ADDR_WIDTH and EndAddr'length /= ADDR_WIDTH then
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: Addr'length: " & to_string(Addr'length) & " /= Memory Address Width: " & to_string(ADDR_WIDTH), FAILURE) ;
end if ;
return ;
end if ;
Addr := StartAddr ;
LineNum := 0 ;
if StartAddr <= EndAddr then
SmallAddr := StartAddr ;
BigAddr := EndAddr ;
AddrInc := (ADDR_WIDTH -1 downto 0 => '0') + 1 ;
else
SmallAddr := EndAddr ;
BigAddr := StartAddr ;
AddrInc := (others => '1') ; -- -1
end if;
ReadLineLoop : while not EndFile(MemFile) loop
ReadLine(MemFile, buf) ;
LineNum := LineNum + 1 ;
ItemNum := 0 ;
ItemLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ItemLoop when Empty ;
ItemNum := ItemNum + 1 ;
NextChar := buf.all(buf'left) ;
if (NextChar = '@') then
-- Get Address
read(buf, NextChar) ;
ReadHexToken(buf, Addr, StrLen) ;
exit ReadLineLoop when AlertIf(MemStructPtr(ID).AlertLogID, StrLen = 0, "MemoryPkg.FileReadX: Address length 0 on line: " & to_string(LineNum), FAILURE) ;
exit ItemLoop when AlertIf(MemStructPtr(ID).AlertLogID, Addr < SmallAddr,
"MemoryPkg.FileReadX: Address in file: " & to_hxstring(Addr) &
" < StartAddr: " & to_hxstring(StartAddr) & " on line: " & to_string(LineNum)) ;
exit ItemLoop when AlertIf(MemStructPtr(ID).AlertLogID, Addr > BigAddr,
"MemoryPkg.FileReadX: Address in file: " & to_hxstring(Addr) &
" > EndAddr: " & to_hxstring(BigAddr) & " on line: " & to_string(LineNum)) ;
elsif DataFormat = HEX and ishex(NextChar) then
-- Get Hex Data
ReadHexToken(buf, data, StrLen) ;
exit ReadLineLoop when AlertIfNot(MemStructPtr(ID).AlertLogID, StrLen > 0,
"MemoryPkg.FileReadH: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: MemWrite(Addr => " & to_hxstring(Addr) & ", Data => " & to_hxstring(Data) & ")", DEBUG) ;
MemWrite(ID, Addr, data) ;
Addr := Addr + AddrInc ;
elsif DataFormat = BINARY and isstd_logic(NextChar) then
-- Get Binary Data
-- read(buf, data, ReadValid) ;
ReadBinaryToken(buf, data, StrLen) ;
-- exit ReadLineLoop when AlertIfNot(MemStructPtr(ID).AlertLogID, ReadValid,
exit ReadLineLoop when AlertIfNot(MemStructPtr(ID).AlertLogID, StrLen > 0,
"MemoryPkg.FileReadB: Error while reading data on line: " & to_string(LineNum) &
" Item number: " & to_string(ItemNum), FAILURE) ;
log(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileReadX: MemWrite(Addr => " & to_hxstring(Addr) & ", Data => " & to_string(Data) & ")", DEBUG) ;
MemWrite(ID, Addr, data) ;
Addr := Addr + AddrInc ;
else
if NextChar = LF or NextChar = CR then
-- If LF or CR, silently skip the character (DOS file in Unix)
read(buf, NextChar) ;
else
-- invalid Text, issue warning and skip rest of line
Alert(MemStructPtr(ID).AlertLogID,
"MemoryPkg.FileReadX: Invalid text on line: " & to_string(LineNum) &
" Item: " & to_string(ItemNum) & ". Skipping text: " & buf.all) ;
exit ItemLoop ;
end if ;
end if ;
end loop ItemLoop ;
end loop ReadLineLoop ;
-- -- must read EndAddr-StartAddr number of words if both start and end specified
-- if (StartAddr /= 0 or (not EndAddr) /= 0) and (Addr /= EndAddr) then
-- Alert("MemoryPkg.FileReadH: insufficient data values", WARNING) ;
-- end if ;
file_close(MemFile) ;
end FileReadX ;
------------------------------------------------------------
procedure FileReadH (
-- Hexadecimal File Read
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadH") ;
begin
FileReadX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
-- Hexadecimal File Read
procedure FileReadH (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
-- Hexadecimal File Read
procedure FileReadH (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
-- Binary File Read
procedure FileReadB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadB") ;
begin
FileReadX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- Binary File Read
procedure FileReadB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- Binary File Read
procedure FileReadB (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileReadB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH - 1 downto 0 => '1') ;
begin
FileReadX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
-- PT Local
-- Hexadecimal or Binary File Write
procedure FileWriteX (
------------------------------------------------------------
ID : integer ;
FileName : string ;
DataFormat : FileFormatType ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant DATA_WIDTH : integer := MemStructPtr(ID).DataWidth ;
constant BLOCK_WIDTH : integer := MemStructPtr(ID).BlockWidth ;
-- Format:
-- @hh..h -- Address in hex
-- hhhhh -- data one per line in either hex or binary as specified
file MemFile : text open WRITE_MODE is FileName ;
alias normStartAddr : std_logic_vector(StartAddr'length-1 downto 0) is StartAddr ;
alias normEndAddr : std_logic_vector(EndAddr'length-1 downto 0) is EndAddr ;
variable StartBlockAddr : natural ;
variable EndBlockAddr : natural ;
variable StartWordAddr : natural ;
variable EndWordAddr : natural ;
variable Data : std_logic_vector(DATA_WIDTH-1 downto 0) ;
variable FoundData : boolean ;
variable buf : line ;
begin
if StartAddr'length /= ADDR_WIDTH and EndAddr'length /= ADDR_WIDTH then
-- Check StartAddr and EndAddr Widths and Memory not initialized
if (MemStructPtr(ID).MemArrayPtr = NULL) then
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileWriteX: Memory not initialized, FileRead Ignored.", FAILURE) ;
else
AlertIf(MemStructPtr(ID).AlertLogID, StartAddr'length /= ADDR_WIDTH, "MemoryPkg.FileWriteX: StartAddr'length: "
& to_string(StartAddr'length) &
" /= Memory Address Width: " & to_string(ADDR_WIDTH), FAILURE) ;
AlertIf(MemStructPtr(ID).AlertLogID, EndAddr'length /= ADDR_WIDTH, "MemoryPkg.FileWriteX: EndAddr'length: "
& to_string(EndAddr'length) &
" /= Memory Address Width: " & to_string(ADDR_WIDTH), FAILURE) ;
end if ;
return ;
end if ;
if StartAddr > EndAddr then
-- Only support ascending addresses
Alert(MemStructPtr(ID).AlertLogID, "MemoryPkg.FileWriteX: StartAddr: " & to_hxstring(StartAddr) &
" > EndAddr: " & to_hxstring(EndAddr), FAILURE) ;
return ;
end if ;
-- Slice out upper address to form block address
if ADDR_WIDTH >= BLOCK_WIDTH then
StartBlockAddr := to_integer(normStartAddr(ADDR_WIDTH-1 downto BLOCK_WIDTH)) ;
EndBlockAddr := to_integer( normEndAddr(ADDR_WIDTH-1 downto BLOCK_WIDTH)) ;
else
StartBlockAddr := 0 ;
EndBlockAddr := 0 ;
end if ;
BlockAddrLoop : for BlockAddr in StartBlockAddr to EndBlockAddr loop
next BlockAddrLoop when MemStructPtr(ID).MemArrayPtr(BlockAddr) = NULL ;
if BlockAddr = StartBlockAddr then
StartWordAddr := to_integer(normStartAddr(BLOCK_WIDTH-1 downto 0)) ;
else
StartWordAddr := 0 ;
end if ;
if BlockAddr = EndBlockAddr then
EndWordAddr := to_integer(normEndAddr(BLOCK_WIDTH-1 downto 0)) ;
else
EndWordAddr := 2**BLOCK_WIDTH-1 ;
end if ;
FoundData := FALSE ;
WordAddrLoop : for WordAddr in StartWordAddr to EndWordAddr loop
if (MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr) < 0) then
-- X in Word, return all X
Data := (Data'range => 'X') ;
FoundData := FALSE ;
else
-- Get the Word from the Array
Data := to_slv(MemStructPtr(ID).MemArrayPtr(BlockAddr)(WordAddr), Data'length) ;
if not FoundData then
-- Write Address
write(buf, '@') ;
hwrite(buf, to_slv(BlockAddr, ADDR_WIDTH-BLOCK_WIDTH) & to_slv(WordAddr, BLOCK_WIDTH)) ;
writeline(MemFile, buf) ;
end if ;
FoundData := TRUE ;
end if ;
if FoundData then -- Write Data
if DataFormat = HEX then
hwrite(buf, Data) ;
writeline(MemFile, buf) ;
else
write(buf, Data) ;
writeline(MemFile, buf) ;
end if;
end if ;
end loop WordAddrLoop ;
end loop BlockAddrLoop ;
file_close(MemFile) ;
end FileWriteX ;
------------------------------------------------------------
-- Hexadecimal File Write
procedure FileWriteH (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteH") ;
begin
FileWriteX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
-- Hexadecimal File Write
procedure FileWriteH (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
begin
FileWriteX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
-- Hexadecimal File Write
procedure FileWriteH (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteH") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
-- fails constant StartAddr : std_logic_vector(MemStructPtr(ID).AddrWidth - 1 downto 0) := (others => '0') ;
-- fails constant EndAddr : std_logic_vector(MemStructPtr(ID).AddrWidth - 1 downto 0) := (others => '1') ;
begin
FileWriteX(ID, FileName, HEX, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
-- Binary File Write
procedure FileWriteB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteB") ;
begin
FileWriteX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
-- Binary File Write
procedure FileWriteB (
------------------------------------------------------------
ID : integer ;
FileName : string ;
StartAddr : std_logic_vector
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
begin
FileWriteX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
-- Binary File Write
procedure FileWriteB (
------------------------------------------------------------
ID : integer ;
FileName : string
) is
constant ID_CHECK_OK : boolean := IdOutOfRange(ID, "FileWriteB") ;
constant ADDR_WIDTH : integer := MemStructPtr(ID).AddrWidth ;
constant StartAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '0') ;
constant EndAddr : std_logic_vector := (ADDR_WIDTH-1 downto 0 => '1') ;
begin
FileWriteX(ID, FileName, BINARY, StartAddr, EndAddr) ;
end FileWriteB ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Structure Wide Methods
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
-- Erase the memory
-- Used between independent pieces of a test
-- to erase the all memory model contents, but
-- keeps the memory size and infrastructure
procedure MemErase is
------------------------------------------------------------
begin
for ID in MemStructPtr'range loop
MemErase(ID) ;
end loop ;
end procedure ;
------------------------------------------------------------
-- Destroys the entire data structure
-- Usage: At the end of the simulation to remove all
-- memory used by data structure.
-- Note, a normal simulator does this for you.
-- You only need this if the simulator is broken.
------------------------------------------------------------
-- PT Local
procedure deallocate (ID : integer) is
------------------------------------------------------------
begin
MemErase(ID) ;
deallocate(MemStructPtr(ID).MemArrayPtr) ;
MemStructPtr(ID).AddrWidth := -1 ;
MemStructPtr(ID).DataWidth := 1 ;
MemStructPtr(ID).BlockWidth := 0 ;
--! removed -- deallocate(MemStructPtr(ID).Name) ;
end procedure ;
procedure deallocate is
begin
for ID in MemStructPtr'range loop
deallocate(ID) ;
end loop ;
--! Deallocate not able to be called on MemoryStore - no accessor procedure
--! if make directly visible, then do this, but otherwise no.
-- deallocate(MemStructPtr) ;
-- NumItems := 0 ;
end procedure deallocate ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Compatibility Methods
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
procedure MemInit ( AddrWidth, DataWidth : in integer ) is
------------------------------------------------------------
begin
MemInit(MEM_STRUCT_PTR_LEFT, AddrWidth, DataWidth) ;
end procedure MemInit ;
------------------------------------------------------------
procedure MemWrite ( Addr, Data : in std_logic_vector ) is
------------------------------------------------------------
begin
MemWrite(MEM_STRUCT_PTR_LEFT, Addr, Data) ;
end procedure MemWrite ;
------------------------------------------------------------
procedure MemRead (
------------------------------------------------------------
Addr : In std_logic_vector ;
Data : Out std_logic_vector
) is
begin
MemRead(MEM_STRUCT_PTR_LEFT, Addr, Data) ;
end procedure MemRead ;
------------------------------------------------------------
impure function MemRead ( Addr : std_logic_vector ) return std_logic_vector is
------------------------------------------------------------
constant DATA_WIDTH : integer := MemStructPtr(MEM_STRUCT_PTR_LEFT).DataWidth ;
variable Data : std_logic_vector(DATA_WIDTH-1 downto 0) ;
begin
MemRead(MEM_STRUCT_PTR_LEFT, Addr, Data) ;
return Data ;
end function MemRead ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
MemStructPtr(MEM_STRUCT_PTR_LEFT).AlertLogID := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
MemStructPtr(MEM_STRUCT_PTR_LEFT).AlertLogID := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return MemStructPtr(MEM_STRUCT_PTR_LEFT).AlertLogID ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure FileReadH (
-- Hexadecimal File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Read
------------------------------------------------------------
begin
FileReadH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadH (FileName : string) is
-- Hexadecimal File Read
------------------------------------------------------------
begin
FileReadH(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileReadH ;
------------------------------------------------------------
procedure FileReadB (
-- Binary File Read
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileReadB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Read
------------------------------------------------------------
begin
FileReadB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileReadB ;
------------------------------------------------------------
procedure FileReadB (FileName : string) is
-- Binary File Read
------------------------------------------------------------
begin
FileReadB(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileReadB ;
------------------------------------------------------------
procedure FileWriteH (
-- Hexadecimal File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string ; StartAddr : std_logic_vector) is
-- Hexadecimal File Write
------------------------------------------------------------
begin
FileWriteH(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteH (FileName : string) is
-- Hexadecimal File Write
------------------------------------------------------------
begin
FileWriteH(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileWriteH ;
------------------------------------------------------------
procedure FileWriteB (
-- Binary File Write
------------------------------------------------------------
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
FileWriteB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr, EndAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string ; StartAddr : std_logic_vector) is
-- Binary File Write
------------------------------------------------------------
begin
FileWriteB(MEM_STRUCT_PTR_LEFT, FileName, StartAddr) ;
end FileWriteB ;
------------------------------------------------------------
procedure FileWriteB (FileName : string) is
-- Binary File Write
------------------------------------------------------------
begin
FileWriteB(MEM_STRUCT_PTR_LEFT, FileName) ;
end FileWriteB ;
end protected body MemoryPType ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Singleton Data Structure
-- /////////////////////////////////////////
-- /////////////////////////////////////////
shared variable MemoryStore : MemoryPType ;
------------------------------------------------------------
impure function NewID (
Name : String ;
AddrWidth : integer ;
DataWidth : integer ;
ParentID : AlertLogIDType := OSVVM_MEMORY_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return MemoryIDType is
variable Result : MemoryIDType ;
begin
Result.ID := MemoryStore.NewID(Name, AddrWidth, DataWidth, ParentID, ReportMode, Search, PrintParent) ;
return Result ;
end function NewID ;
------------------------------------------------------------
procedure MemWrite (
ID : MemoryIDType ;
Addr : std_logic_vector ;
Data : std_logic_vector
) is
begin
MemoryStore.MemWrite(ID.ID, Addr, Data) ;
end procedure MemWrite ;
procedure MemRead (
ID : in MemoryIDType ;
Addr : in std_logic_vector ;
Data : out std_logic_vector
) is
begin
MemoryStore.MemRead(ID.ID, Addr, Data) ;
end procedure MemRead ;
impure function MemRead (
ID : MemoryIDType ;
Addr : std_logic_vector
) return std_logic_vector is
begin
return MemoryStore.MemRead(ID.ID, Addr) ;
end function MemRead ;
------------------------------------------------------------
procedure MemErase (ID : in MemoryIDType) is
begin
MemoryStore.MemErase(ID.ID) ;
end procedure MemErase ;
------------------------------------------------------------
impure function GetAlertLogID (
ID : in MemoryIDType
) return AlertLogIDType is
begin
return MemoryStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure FileReadH ( -- Hexadecimal File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileReadH(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileReadH ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileReadH(ID.ID, FileName, StartAddr) ;
end procedure FileReadH ;
procedure FileReadH (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileReadH(ID.ID, FileName) ;
end procedure FileReadH ;
------------------------------------------------------------
procedure FileReadB ( -- Binary File Read
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileReadB(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileReadB ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileReadB(ID.ID, FileName, StartAddr) ;
end procedure FileReadB ;
procedure FileReadB (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileReadB(ID.ID, FileName) ;
end procedure FileReadB ;
------------------------------------------------------------
procedure FileWriteH ( -- Hexadecimal File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteH(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileWriteH ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteH(ID.ID, FileName, StartAddr) ;
end procedure FileWriteH ;
procedure FileWriteH (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileWriteH(ID.ID, FileName) ;
end procedure FileWriteH ;
------------------------------------------------------------
procedure FileWriteB ( -- Binary File Write
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector ;
EndAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteB(ID.ID, FileName, StartAddr, EndAddr) ;
end procedure FileWriteB ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string ;
StartAddr : std_logic_vector
) is
begin
MemoryStore.FileWriteB(ID.ID, FileName, StartAddr) ;
end procedure FileWriteB ;
procedure FileWriteB (
ID : MemoryIDType ;
FileName : string
) is
begin
MemoryStore.FileWriteB(ID.ID, FileName) ;
end procedure FileWriteB ;
end MemoryPkg ; | artistic-2.0 | 2bc5e49d6770c8f41e95808f2c77e7de | 0.506711 | 4.675648 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/interrupt_control_v2_01_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_interrupt_control.vhd | 1 | 56,950 | -------------------------------------------------------------------------------
--cpu_xadc_wiz_0_0_interrupt_control.vhd version v2.01.a
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright(C) 2005 by Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This text contains proprietary, confidential **
-- ** information of Xilinx, Inc. , is distributed by **
-- ** under license from Xilinx, Inc., and may be used, **
-- ** copied and/or disclosed only pursuant to the terms **
-- ** of a valid license agreement with Xilinx, Inc. **
-- ** **
-- ** Unmodified source code is guaranteed to place and route, **
-- ** function and run at speed according to the datasheet **
-- ** specification. Source code is provided "as-is", with no **
-- ** obligation on the part of Xilinx to provide support. **
-- ** **
-- ** Xilinx Hotline support of source code IP shall only include **
-- ** standard level Xilinx Hotline support, and will only address **
-- ** issues and questions related to the standard released Netlist **
-- ** version of the core (and thus indirectly, the original core source). **
-- ** **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Support Hotline will only be able **
-- ** to confirm the problem in the Netlist version of the core. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_interrupt_control.vhd
--
-- Description: This VHDL design file is the parameterized interrupt control
-- module for the ipif which permits parameterizing 1 or 2 levels
-- of interrupt registers. This module has been optimized
-- for the 64 bit wide PLB bus.
--
--
--
-------------------------------------------------------------------------------
-- Structure:
--
-- cpu_xadc_wiz_0_0_interrupt_control.vhd
--
--
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_I_SP2
--
-- Initial Release
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_K_SP3
--
-- Updated to use work library
--
-- @END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: Doug Thorpe
--
-- History:
-- Doug Thorpe Aug 16, 2001 -- V1.00a (initial release)
-- Mike Lovejoy Oct 9, 2001 -- V1.01a
-- Added parameter C_INCLUDE_DEV_ISC to remove Device ISC.
-- When one source of interrupts Device ISC is redundant and
-- can be eliminated to reduce LUT count. When 7 interrupts
-- are included, the LUT count is reduced from 49 to 17.
-- Also removed the "wrapper" which required redefining
-- ports and generics herein.
--
-- det Feb-19-02
-- - Added additional selections of input processing on the IP
-- interrupt inputs. This was done by replacing the
-- C_IP_IRPT_NUM Generic with an unconstrained input array
-- of integers selecting the type of input processing for each
-- bit.
--
-- det Mar-22-02
-- - Corrected a reset problem with pos edge detect interrupt
-- input processing (a high on the input when recovering from
-- reset caused an eroneous interrupt to be latched in the IP_
-- ISR reg.
--
-- blt Nov-18-02 -- V1.01b
-- - Updated library and use statements to use ipif_common_v1_00_b
--
-- DET 11/5/2003 v1_00_e
-- ~~~~~~
-- - Revamped register topology to take advantage of 64 bit wide data bus
-- interface. This required adding the Bus2IP_BE_sa input port to
-- provide byte lane qualifiers for write operations.
-- ^^^^^^
--
--
-- DET 3/25/2004 ipif to v1_00_f
-- ~~~~~~
-- - Changed proc_common library reference to v2_00_a
-- - Removed ipif_common library reference
-- ^^^^^^
-- GAB 06/29/2005 v2_00_a
-- ~~~~~~
-- - Modified plb_cpu_xadc_wiz_0_0_interrupt_control of plb_ipif_v1_00_f to make
-- a common version that supports 32,64, and 128-Bit Data Bus Widths.
-- - Changed to use ieee.numeric_std library and removed
-- ieee.std_logic_arith.all
-- ^^^^^^
-- GAB 09/01/2006 v2_00_a
-- ~~~~~~
-- - Modified wrack and strobe for toggling set interrupt bits to reduce LUTs
-- - Removed strobe from interrupt enable registers where it was not needed
-- ^^^^^^
-- GAB 07/02/2008 v2_01_a
-- ~~~~~~
-- - Modified to used proc_common_v3_00_a library
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--
--
-------------------------------------------------------------------------------
-- Special information
--
-- The input Generic C_IP_INTR_MODE_ARRAY is an unconstrained array
-- of integers. The number of entries specifies how many IP interrupts
-- are to be processed. Each entry in the array specifies the type of input
-- processing for each IP interrupt input. The following table
-- lists the defined values for entries in the array:
--
-- 1 = Level Pass through (non-inverted input)
-- 2 = Level Pass through (invert input)
-- 3 = Registered Level (non-inverted input)
-- 4 = Registered Level (inverted input)
-- 5 = Rising Edge Detect (non-inverted input)
-- 6 = Falling Edge Detect (non-inverted input)
--
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all;
library work;
Use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
----------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_interrupt_control is
Generic(
C_NUM_CE : integer range 4 to 16 := 4;
-- Number of register chip enables required
-- For C_IPIF_DWIDTH=32 Set C_NUM_CE = 16
-- For C_IPIF_DWIDTH=64 Set C_NUM_CE = 8
-- For C_IPIF_DWIDTH=128 Set C_NUM_CE = 4
C_NUM_IPIF_IRPT_SRC : integer range 1 to 29 := 4;
C_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- pass through (non-inverting)
2 -- pass through (inverting)
);
-- Interrupt Modes
--1, -- pass through (non-inverting)
--2, -- pass through (inverting)
--3, -- registered level (non-inverting)
--4, -- registered level (inverting)
--5, -- positive edge detect
--6 -- negative edge detect
C_INCLUDE_DEV_PENCODER : boolean := false;
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_ISC : boolean := false;
-- Specifies device ISC hierarchy
-- Exclusion of Device ISC requires
-- exclusion of Priority encoder
C_IPIF_DWIDTH : integer range 32 to 128 := 128
);
port(
-- Inputs From the IPIF Bus
Bus2IP_Clk : In std_logic;
Bus2IP_Reset : In std_logic;
Bus2IP_Data : In std_logic_vector(0 to C_IPIF_DWIDTH-1);
Bus2IP_BE : In std_logic_vector(0 to (C_IPIF_DWIDTH/8)-1);
Interrupt_RdCE : In std_logic_vector(0 to C_NUM_CE-1);
Interrupt_WrCE : In std_logic_vector(0 to C_NUM_CE-1);
-- Interrupt inputs from the IPIF sources that will
-- get registered in this design
IPIF_Reg_Interrupts : In std_logic_vector(0 to 1);
-- Level Interrupt inputs from the IPIF sources
IPIF_Lvl_Interrupts : In std_logic_vector
(0 to C_NUM_IPIF_IRPT_SRC-1);
-- Inputs from the IP Interface
IP2Bus_IntrEvent : In std_logic_vector
(0 to C_IP_INTR_MODE_ARRAY'length-1);
-- Final Device Interrupt Output
Intr2Bus_DevIntr : Out std_logic;
-- Status Reply Outputs to the Bus
Intr2Bus_DBus : Out std_logic_vector(0 to C_IPIF_DWIDTH-1);
Intr2Bus_WrAck : Out std_logic;
Intr2Bus_RdAck : Out std_logic;
Intr2Bus_Error : Out std_logic;
Intr2Bus_Retry : Out std_logic;
Intr2Bus_ToutSup : Out std_logic
);
end cpu_xadc_wiz_0_0_interrupt_control;
-------------------------------------------------------------------------------
architecture implementation of cpu_xadc_wiz_0_0_interrupt_control is
-------------------------------------------------------------------------------
-- Function declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_max_allowed_irpt_width
--
-- Function Description:
-- This function determines the maximum number of interrupts that
-- can be processed from the User IP based on the IPIF data bus width
-- and the number of interrupt entries desired.
--
-------------------------------------------------------------------
function get_max_allowed_irpt_width(data_bus_width : integer;
num_intrpts_entered : integer)
return integer is
Variable temp_max : Integer;
begin
If (data_bus_width >= num_intrpts_entered) Then
temp_max := num_intrpts_entered;
else
temp_max := data_bus_width;
End if;
return(temp_max);
end function get_max_allowed_irpt_width;
-------------------------------------------------------------------------------
-- Function data_port_map
-- This function will return an index within a 'reg_width' divided port
-- having a width of 'port_width' based on an address 'offset'.
-- For instance if the port_width is 128-bits and the register width
-- reg_width = 32 bits and the register address offset=16 (0x10), this
-- function will return a index of 0.
--
-- Address Offset Returned Index Return Index Returned Index
-- (128 Bit Bus) (64 Bit Bus) (32 Bit Bus)
-- 0x00 0 0 0
-- 0x04 1 1 0
-- 0x08 2 0 0
-- 0x0C 3 1 0
-- 0x10 0 0 0
-- 0x14 1 1 0
-- 0x18 2 0 0
-- 0x1C 3 1 0
-------------------------------------------------------------------------------
function data_port_map(offset : integer;
reg_width : integer;
port_width : integer)
return integer is
variable upper_index : integer;
variable vector_range : integer;
variable reg_offset : std_logic_vector(0 to 7);
variable word_offset_i : integer;
begin
-- Calculate index position to start decoding the address offset
upper_index := log2(port_width/8);
-- Calculate the number of bits to look at in decoding
-- the address offset
vector_range := max2(1,log2(port_width/reg_width));
-- Convert address offset into a std_logic_vector in order to
-- strip out a set of bits for decoding
reg_offset := std_logic_vector(to_unsigned(offset,8));
-- Calculate an index representing the word position of
-- a register with respect to the port width.
word_offset_i := to_integer(unsigned(reg_offset(reg_offset'length
- upper_index to (reg_offset'length
- upper_index) + vector_range - 1)));
return word_offset_i;
end data_port_map;
-------------------------------------------------------------------------------
-- Type declarations
-------------------------------------------------------------------------------
-- no Types
-------------------------------------------------------------------------------
-- Constant declarations
-------------------------------------------------------------------------------
-- general use constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
-- figure out if 32 bits wide or 64 bits wide
Constant LSB_BYTLE_LANE_COL_OFFSET : integer := (C_IPIF_DWIDTH/32)-1;
Constant CHIP_SEL_SCALE_FACTOR : integer := (C_IPIF_DWIDTH/32);
constant BITS_PER_REG : integer := 32;
constant BYTES_PER_REG : integer := BITS_PER_REG/8;
-- Register Index
Constant DEVICE_ISR_INDEX : integer := 0;
Constant DEVICE_IPR_INDEX : integer := 1;
Constant DEVICE_IER_INDEX : integer := 2;
Constant DEVICE_IAR_INDEX : integer := 3; --NOT USED RSVD
Constant DEVICE_SIE_INDEX : integer := 4; --NOT USED RSVD
Constant DEVICE_CIE_INDEX : integer := 5; --NOT USED RSVD
Constant DEVICE_IIR_INDEX : integer := 6;
Constant DEVICE_GIE_INDEX : integer := 7;
Constant IP_ISR_INDEX : integer := 8;
Constant IP_IPR_INDEX : integer := 9; --NOT USED RSVD
Constant IP_IER_INDEX : integer := 10;
Constant IP_IAR_INDEX : integer := 11; --NOT USED RSVD
Constant IP_SIE_INDEX : integer := 12; --NOT USED RSVD
Constant IP_CIE_INDEX : integer := 13; --NOT USED RSVD
Constant IP_IIR_INDEX : integer := 14; --NOT USED RSVD
Constant IP_GIE_INDEX : integer := 15; --NOT USED RSVD
-- Chip Enable Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR : integer := DEVICE_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IPR : integer := DEVICE_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 0 if 64-bit dwidth;
Constant DEVICE_IER : integer := DEVICE_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_IAR : integer := DEVICE_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 1 if 64-bit dwidth;
Constant DEVICE_SIE : integer := DEVICE_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_CIE : integer := DEVICE_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 2 if 64-bit dwidth;
Constant DEVICE_IIR : integer := DEVICE_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant DEVICE_GIE : integer := DEVICE_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 3 if 64-bit dwidth;
Constant IP_ISR : integer := IP_ISR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IPR : integer := IP_IPR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 4 if 64-bit dwidth;
Constant IP_IER : integer := IP_IER_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_IAR : integer := IP_IAR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 5 if 64-bit dwidth;
Constant IP_SIE : integer := IP_SIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_CIE : integer := IP_CIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 6 if 64-bit dwidth;
Constant IP_IIR : integer := IP_IIR_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
Constant IP_GIE : integer := IP_GIE_INDEX/CHIP_SEL_SCALE_FACTOR; -- 7 if 64-bit dwidth;
-- Register Address Offset
Constant DEVICE_ISR_OFFSET : integer := DEVICE_ISR_INDEX * BYTES_PER_REG;
Constant DEVICE_IPR_OFFSET : integer := DEVICE_IPR_INDEX * BYTES_PER_REG;
Constant DEVICE_IER_OFFSET : integer := DEVICE_IER_INDEX * BYTES_PER_REG;
Constant DEVICE_IAR_OFFSET : integer := DEVICE_IAR_INDEX * BYTES_PER_REG;
Constant DEVICE_SIE_OFFSET : integer := DEVICE_SIE_INDEX * BYTES_PER_REG;
Constant DEVICE_CIE_OFFSET : integer := DEVICE_CIE_INDEX * BYTES_PER_REG;
Constant DEVICE_IIR_OFFSET : integer := DEVICE_IIR_INDEX * BYTES_PER_REG;
Constant DEVICE_GIE_OFFSET : integer := DEVICE_GIE_INDEX * BYTES_PER_REG;
Constant IP_ISR_OFFSET : integer := IP_ISR_INDEX * BYTES_PER_REG;
Constant IP_IPR_OFFSET : integer := IP_IPR_INDEX * BYTES_PER_REG;
Constant IP_IER_OFFSET : integer := IP_IER_INDEX * BYTES_PER_REG;
Constant IP_IAR_OFFSET : integer := IP_IAR_INDEX * BYTES_PER_REG;
Constant IP_SIE_OFFSET : integer := IP_SIE_INDEX * BYTES_PER_REG;
Constant IP_CIE_OFFSET : integer := IP_CIE_INDEX * BYTES_PER_REG;
Constant IP_IIR_OFFSET : integer := IP_IIR_INDEX * BYTES_PER_REG;
Constant IP_GIE_OFFSET : integer := IP_GIE_INDEX * BYTES_PER_REG;
-- Column Selection mapping (applies to RdCE and WrCE inputs)
Constant DEVICE_ISR_COL : integer := data_port_map(DEVICE_ISR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IPR_COL : integer := data_port_map(DEVICE_IPR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IER_COL : integer := data_port_map(DEVICE_IER_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IAR_COL : integer := data_port_map(DEVICE_IAR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_SIE_COL : integer := data_port_map(DEVICE_SIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_CIE_COL : integer := data_port_map(DEVICE_CIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_IIR_COL : integer := data_port_map(DEVICE_IIR_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant DEVICE_GIE_COL : integer := data_port_map(DEVICE_GIE_OFFSET,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_ISR_COL : integer := data_port_map(IP_ISR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IPR_COL : integer := data_port_map(IP_IPR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IER_COL : integer := data_port_map(IP_IER_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IAR_COL : integer := data_port_map(IP_IAR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_SIE_COL : integer := data_port_map(IP_SIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_CIE_COL : integer := data_port_map(IP_CIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_IIR_COL : integer := data_port_map(IP_IIR_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
Constant IP_GIE_COL : integer := data_port_map(IP_GIE_OFFSET ,BITS_PER_REG,C_IPIF_DWIDTH);
-- Generic to constant mapping
Constant DBUS_WIDTH_MINUS1 : Integer := C_IPIF_DWIDTH - 1;
Constant NUM_USER_DESIRED_IRPTS : Integer := C_IP_INTR_MODE_ARRAY'length;
-- Constant IP_IRPT_HIGH_INDEX : Integer := C_IP_INTR_MODE_ARRAY'length - 1;
Constant IP_IRPT_HIGH_INDEX : Integer :=
get_max_allowed_irpt_width(C_IPIF_DWIDTH,
NUM_USER_DESIRED_IRPTS)
-1;
Constant IPIF_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC + 2;
-- (2 level + 1 IP + Number of latched inputs) - 1
Constant IPIF_LVL_IRPT_HIGH_INDEX : Integer := C_NUM_IPIF_IRPT_SRC - 1;
-- Priority encoder support constants
Constant PRIORITY_ENC_WIDTH : Integer := 8; -- bits
Constant NO_INTR_VALUE : Integer := 128;
-- no interrupt pending code = "10000000"
-------------------------------------------------------------------------------
-- Signal declarations
-------------------------------------------------------------------------------
Signal trans_reg_irpts : std_logic_vector(1 downto 0);
Signal trans_lvl_irpts : std_logic_vector
(IPIF_LVL_IRPT_HIGH_INDEX downto 0);
Signal trans_ip_irpts : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal edgedtct_ip_irpts : std_logic_vector
(0 to IP_IRPT_HIGH_INDEX);
signal irpt_read_data : std_logic_vector
(DBUS_WIDTH_MINUS1 downto 0);
Signal irpt_rdack : std_logic;
Signal irpt_wrack : std_logic;
signal ip_irpt_status_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_enable_reg : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
signal ip_irpt_pending_value : std_logic_vector
(IP_IRPT_HIGH_INDEX downto 0);
Signal ip_interrupt_or : std_logic;
signal ipif_irpt_status_reg : std_logic_vector(1 downto 0);
signal ipif_irpt_status_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_enable_reg : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
signal ipif_irpt_pending_value : std_logic_vector
(IPIF_IRPT_HIGH_INDEX downto 0);
Signal ipif_glbl_irpt_enable_reg : std_logic;
Signal ipif_interrupt : std_logic;
Signal ipif_interrupt_or : std_logic;
Signal ipif_pri_encode_present : std_logic;
Signal ipif_priority_encode_value : std_logic_vector
(PRIORITY_ENC_WIDTH-1 downto 0);
Signal column_sel : std_logic_vector
(0 to LSB_BYTLE_LANE_COL_OFFSET);
signal interrupt_wrce_strb : std_logic;
signal irpt_wrack_d1 : std_logic;
signal irpt_rdack_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc I/O and Signal assignments
Intr2Bus_DevIntr <= ipif_interrupt;
Intr2Bus_Error <= LOGIC_LOW;
Intr2Bus_Retry <= LOGIC_LOW;
Intr2Bus_ToutSup <= LOGIC_LOW;
REG_WRACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_wrack_d1 <= '0';
Intr2Bus_WrAck <= '0';
else
irpt_wrack_d1 <= irpt_wrack;
Intr2Bus_WrAck <= interrupt_wrce_strb;
end if;
end if;
end process REG_WRACK_PROCESS;
interrupt_wrce_strb <= irpt_wrack and not irpt_wrack_d1;
REG_RDACK_PROCESS : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
if(Bus2IP_Reset = '1')then
irpt_rdack_d1 <= '0';
Intr2Bus_RdAck <= '0';
else
irpt_rdack_d1 <= irpt_rdack;
Intr2Bus_RdAck <= irpt_rdack and not irpt_rdack_d1;
end if;
end if;
end process REG_RDACK_PROCESS;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: ASSIGN_COL
--
-- Process Description:
--
--
-------------------------------------------------------------
ASSIGN_COL : process (Bus2IP_BE)
begin
-- Assign the 32-bit column selects from BE inputs
for i in 0 to LSB_BYTLE_LANE_COL_OFFSET loop
column_sel(i) <= Bus2IP_BE(i*4);
end loop;
end process ASSIGN_COL;
----------------------------------------------------------------------------------------------------------------
--- IP Interrupt processing start
------------------------------------------------------------------------------------------
-- Convert Little endian register to big endian data bus
------------------------------------------------------------------------------------------
LITTLE_TO_BIG : process (irpt_read_data)
Begin
for k in 0 to DBUS_WIDTH_MINUS1 loop
Intr2Bus_DBus(DBUS_WIDTH_MINUS1-k) <= irpt_read_data(k); -- Convert to Big-Endian Data Bus
End loop;
End process; -- LITTLE_TO_BIG
------------------------------------------------------------------------------------------
-- Convert big endian interrupt inputs to Little endian registers
------------------------------------------------------------------------------------------
BIG_TO_LITTLE : process (IPIF_Reg_Interrupts, IPIF_Lvl_Interrupts, edgedtct_ip_irpts)
Begin
for i in 0 to 1 loop
trans_reg_irpts(i) <= IPIF_Reg_Interrupts(i); -- Convert to Little-Endian format
End loop;
for j in 0 to IPIF_LVL_IRPT_HIGH_INDEX loop
trans_lvl_irpts(j) <= IPIF_Lvl_Interrupts(j); -- Convert to Little-Endian format
End loop;
for k in 0 to IP_IRPT_HIGH_INDEX loop
trans_ip_irpts(k) <= edgedtct_ip_irpts(k); -- Convert to Little-Endian format
End loop;
End process; -- BIG_TO_LITTLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Input Processing
------------------------------------------------------------------------------------------
DO_IRPT_INPUT: for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_NON_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 3) generate
edgedtct_ip_irpts(irpt_index) <= IP2Bus_IntrEvent(irpt_index);
end generate GEN_NON_INVERT_PASS_THROUGH;
GEN_INVERT_PASS_THROUGH : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 2 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 4) generate
edgedtct_ip_irpts(irpt_index) <= not(IP2Bus_IntrEvent(irpt_index));
end generate GEN_INVERT_PASS_THROUGH;
GEN_POS_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 5) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '1'; -- setting to '1' protects reset transition
irpt_dly2 <= '1'; -- where interrupt inputs are preset high
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
-- now detect rising edge
edgedtct_ip_irpts(irpt_index) <= irpt_dly1 and not(irpt_dly2);
end generate GEN_POS_EDGE_DETECT;
GEN_NEG_EDGE_DETECT : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 6) generate
Signal irpt_dly1 : std_logic;
Signal irpt_dly2 : std_logic;
begin
REG_THE_IRPTS : process (Bus2IP_Clk)
begin
If (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
irpt_dly1 <= '0';
irpt_dly2 <= '0';
Else
irpt_dly1 <= IP2Bus_IntrEvent(irpt_index);
irpt_dly2 <= irpt_dly1;
End if;
else
null;
End if;
End process; -- REG_THE_IRPTS
edgedtct_ip_irpts(irpt_index) <= not(irpt_dly1) and irpt_dly2;
end generate GEN_NEG_EDGE_DETECT;
GEN_INVALID_TYPE : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 6 ) generate
edgedtct_ip_irpts(irpt_index) <= '0'; -- Don't use input
end generate GEN_INVALID_TYPE;
End generate DO_IRPT_INPUT;
-- Generate the IP Interrupt Status register
GEN_IP_IRPT_STATUS_REG : for irpt_index in 0 to IP_IRPT_HIGH_INDEX generate
GEN_REG_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) > 2) generate
DO_STATUS_BIT : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_status_reg(irpt_index) <= '0';
elsif (Interrupt_WrCE(IP_ISR) = '1' and
column_sel(IP_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then -- toggle selected ISR bits from the DBus inputs
-- (GAB)
ip_irpt_status_reg(irpt_index) <=
(Bus2IP_Data((BITS_PER_REG * IP_ISR_COL)
+(BITS_PER_REG - 1)
- irpt_index) xor -- toggle bits on write of '1'
ip_irpt_status_reg(irpt_index)) or -- but don't miss interrupts coming
trans_ip_irpts(irpt_index); -- in on non-cleared interrupt bits
else
ip_irpt_status_reg(irpt_index) <=
ip_irpt_status_reg(irpt_index) or
trans_ip_irpts(irpt_index); -- latch and hold input interrupt bits
End if;
Else
null;
End if;
End process; -- DO_STATUS_BIT
End generate GEN_REG_STATUS;
GEN_PASS_THROUGH_STATUS : if (C_IP_INTR_MODE_ARRAY(irpt_index) = 1 or
C_IP_INTR_MODE_ARRAY(irpt_index) = 2) generate
ip_irpt_status_reg(irpt_index) <= trans_ip_irpts(irpt_index);
End generate GEN_PASS_THROUGH_STATUS;
End generate GEN_IP_IRPT_STATUS_REG;
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IP_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ip_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(IP_IER) = '1' and
column_sel(IP_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ip_irpt_enable_reg <= Bus2IP_Data
( (BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
- IP_IRPT_HIGH_INDEX to
(BITS_PER_REG * IP_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IP_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IP_INTR_ENABLE : process (ip_irpt_status_reg, ip_irpt_enable_reg)
Begin
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_irpt_pending_value(i) <= ip_irpt_status_reg(i) and
ip_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IP_INTR_ENABLE
------------------------------------------------------------------------------------------
-- Implement the IP Interrupt 'OR' Functions
------------------------------------------------------------------------------------------
DO_IP_INTR_OR : process (ip_irpt_pending_value)
Variable ip_loop_or : std_logic;
Begin
ip_loop_or := '0';
for i in 0 to IP_IRPT_HIGH_INDEX loop
ip_loop_or := ip_loop_or or ip_irpt_pending_value(i);
End loop;
ip_interrupt_or <= ip_loop_or;
End process; -- DO_IP_INTR_OR
--------------------------------------------------------------------------------------------
--- IP Interrupt processing end
--------------------------------------------------------------------------------------------
--==========================================================================================
Include_Device_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
--------------------------------------------------------------------------------------------
--- IPIF Interrupt processing Start
--------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Status Register Write and Clear Functions
-- This is only 2 bits wide (the only inputs latched at this level...the others just flow
-- through)
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_STATUS_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_status_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_ISR) = '1' and
column_sel(DEVICE_ISR_COL) = '1' and
interrupt_wrce_strb = '1') Then
for i in 0 to 1 loop
-- (GAB)
ipif_irpt_status_reg(i) <= (Bus2IP_Data
( (BITS_PER_REG * DEVICE_ISR_COL)
+(BITS_PER_REG - 1)
- i) xor -- toggle bits on write of '1'
ipif_irpt_status_reg(i)) or -- but don't miss interrupts coming
trans_reg_irpts(i); -- in on non-cleared interrupt bits
End loop;
else
for i in 0 to 1 loop
ipif_irpt_status_reg(i) <= ipif_irpt_status_reg(i) or trans_reg_irpts(i);
-- latch and hold asserted interrupts
End loop;
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_STATUS_REG
DO_IPIF_IRPT_STATUS_VALUE : process (ipif_irpt_status_reg, trans_lvl_irpts, ip_interrupt_or)
Begin
ipif_irpt_status_value(1 downto 0) <= ipif_irpt_status_reg;
ipif_irpt_status_value(2) <= ip_interrupt_or;
for i in 3 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_status_value(i) <= trans_lvl_irpts(i-3);
End loop;
End process; -- DO_IPIF_IRPT_STATUS_VALUE
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_ENABLE_REG : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_irpt_enable_reg <= (others => '0');
elsif (Interrupt_WrCE(DEVICE_IER) = '1' and
column_sel(DEVICE_IER_COL) = '1') then
-- interrupt_wrce_strb = '1') Then
-- (GAB)
ipif_irpt_enable_reg <= Bus2IP_Data
(
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
- IPIF_IRPT_HIGH_INDEX to
(BITS_PER_REG * DEVICE_IER_COL)
+(BITS_PER_REG - 1)
);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_ENABLE_REG
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Enable/Masking function
------------------------------------------------------------------------------------------
DO_IPIF_INTR_ENABLE : process (ipif_irpt_status_value, ipif_irpt_enable_reg)
Begin
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_irpt_pending_value(i) <= ipif_irpt_status_value(i) and ipif_irpt_enable_reg(i); -- enable/mask interrupt bits
End loop;
End process; -- DO_IPIF_INTR_ENABLE
end generate Include_Device_ISC_generate;
Initialize_when_not_include_Device_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_irpt_status_reg <= (others => '0');
ipif_irpt_status_value <= (others => '0');
ipif_irpt_enable_reg <= (others => '0');
ipif_irpt_pending_value <= (others => '0');
end generate Initialize_when_not_include_Device_ISC_generate;
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Master Enable Register Write and Clear Functions
------------------------------------------------------------------------------------------
DO_IPIF_IRPT_MASTER_ENABLE : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') Then
If (Bus2IP_Reset = '1') Then
ipif_glbl_irpt_enable_reg <= '0';
elsif (Interrupt_WrCE(DEVICE_GIE) = '1' and
column_sel(DEVICE_GIE_COL) = '1' )then
--interrupt_wrce_strb = '1') Then -- load input data from the DBus inputs
-- (GAB)
ipif_glbl_irpt_enable_reg <= Bus2IP_Data(BITS_PER_REG * DEVICE_GIE_COL);
else
null; -- no change
End if;
Else
null;
End if;
End process; -- DO_IPIF_IRPT_MASTER_ENABLE
INCLUDE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = True) generate
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt Priority Encoder Function on the Interrupt Pending Value
-- Loop from Interrupt LSB to MSB, retaining the position of the last interrupt detected.
-- This method implies a positional priority of MSB to LSB.
------------------------------------------------------------------------------------------
ipif_pri_encode_present <= '1';
DO_PRIORITY_ENCODER : process (ipif_irpt_pending_value)
Variable irpt_position : Integer;
Variable irpt_detected : Boolean;
Variable loop_count : integer;
Begin
loop_count := IPIF_IRPT_HIGH_INDEX + 1;
irpt_position := 0;
irpt_detected := FALSE;
-- Search through the pending interrupt values starting with the MSB
while (loop_count > 0) loop
If (ipif_irpt_pending_value(loop_count-1) = '1') Then
irpt_detected := TRUE;
irpt_position := loop_count-1;
else
null; -- do nothing
End if;
loop_count := loop_count - 1;
End loop;
-- now assign the encoder output value to the bit position of the last interrupt encountered
If (irpt_detected) Then
ipif_priority_encode_value <= std_logic_vector(to_unsigned(irpt_position, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '1'; -- piggy-back off of this function for the "OR" function
else
ipif_priority_encode_value <= std_logic_vector(to_unsigned(NO_INTR_VALUE, PRIORITY_ENC_WIDTH));
ipif_interrupt_or <= '0';
End if;
End process; -- DO_PRIORITY_ENCODER
end generate INCLUDE_DEV_PRIORITY_ENCODER;
DELETE_DEV_PRIORITY_ENCODER : if (C_INCLUDE_DEV_PENCODER = False) generate
ipif_pri_encode_present <= '0';
ipif_priority_encode_value <= (others => '0');
------------------------------------------------------------------------------------------
-- Implement the IPIF Interrupt 'OR' Functions (used if priority encoder removed)
------------------------------------------------------------------------------------------
DO_IPIF_INTR_OR : process (ipif_irpt_pending_value)
Variable ipif_loop_or : std_logic;
Begin
ipif_loop_or := '0';
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
ipif_loop_or := ipif_loop_or or ipif_irpt_pending_value(i);
End loop;
ipif_interrupt_or <= ipif_loop_or;
End process; -- DO_IPIF_INTR_OR
end generate DELETE_DEV_PRIORITY_ENCODER;
-------------------------------------------------------------------------------------------
-- Perform the final Master enable function on the 'ORed' interrupts
OR_operation_with_Dev_ISC_generate: if(C_INCLUDE_DEV_ISC) generate
begin
ipif_interrupt_PROCESS: process(ipif_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ipif_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_with_Dev_ISC_generate;
OR_operation_withOUT_Dev_ISC_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
ipif_interrupt_PROCESS: process(ip_interrupt_or, ipif_glbl_irpt_enable_reg)
begin
ipif_interrupt <= ip_interrupt_or and ipif_glbl_irpt_enable_reg;
end process ipif_interrupt_PROCESS;
end generate OR_operation_withOUT_Dev_ISC_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Interrupt processing end
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_WrAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <= (
Interrupt_WrCE(DEVICE_ISR) and
column_sel(DEVICE_ISR_COL)
)
or
(
Interrupt_WrCE(DEVICE_IER) and
column_sel(DEVICE_IER_COL)
)
or
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Include_Dev_ISC_WrAck_OR_generate;
Exclude_Dev_ISC_WrAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GEN_WRITE_ACKNOWLEGDGE : process (Interrupt_WrCE,
column_sel
)
Begin
irpt_wrack <=
(
Interrupt_WrCE(DEVICE_GIE) and
column_sel(DEVICE_GIE_COL)
)
or
(
Interrupt_WrCE(IP_ISR) and
column_sel(IP_ISR_COL)
)
or
(
Interrupt_WrCE(IP_IER) and
column_sel(IP_IER_COL)
);
End process; -- GEN_WRITE_ACKNOWLEGDGE
end generate Exclude_Dev_ISC_WrAck_OR_generate;
-----------------------------------------------------------------------------------------------------------
--- IPIF Bus Data Read Mux and Read Acknowledge generation
----------------------------------------------------------------------------------------------------------------
Include_Dev_ISC_RdAck_OR_generate: if(C_INCLUDE_DEV_ISC) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, column_sel,
ip_irpt_status_reg,
ip_irpt_enable_reg,
ipif_irpt_pending_value,
ipif_irpt_enable_reg,
ipif_pri_encode_present,
ipif_priority_encode_value,
ipif_irpt_status_value,
ipif_glbl_irpt_enable_reg)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_ISR) = '1'
and column_sel(DEVICE_ISR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_ISR_COL)
- BITS_PER_REG)) <= ipif_irpt_status_value(i); -- output IPIF status interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IPR) = '1'
and column_sel(DEVICE_IPR_COL) = '1')then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_pending_value(i+32); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IPR_COL)
- BITS_PER_REG)) <= ipif_irpt_pending_value(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IER) = '1'
and column_sel(DEVICE_IER_COL) = '1') Then
for i in 0 to IPIF_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IER_COL)
- BITS_PER_REG)) <= ipif_irpt_enable_reg(i); -- output IPIF pending interrupt values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_IIR) = '1'
and column_sel(DEVICE_IIR_COL) = '1') Then
-- irpt_read_data(32+PRIORITY_ENC_WIDTH-1 downto 32) <= ipif_priority_encode_value; -- output IPIF pending interrupt values
irpt_read_data( (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG) + PRIORITY_ENC_WIDTH-1
downto (C_IPIF_DWIDTH
- (BITS_PER_REG*DEVICE_IIR_COL)
- BITS_PER_REG)) <= ipif_priority_encode_value;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(DBUS_WIDTH_MINUS1) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Include_Dev_ISC_RdAck_OR_generate;
Exclude_Dev_ISC_RdAck_OR_generate: if(not(C_INCLUDE_DEV_ISC)) generate
begin
GET_READ_DATA : process (Interrupt_RdCE, ip_irpt_status_reg, ip_irpt_enable_reg,
ipif_glbl_irpt_enable_reg,column_sel)
Begin
irpt_read_data <= (others => '0'); -- default to driving zeroes
If (Interrupt_RdCE(IP_ISR) = '1'
and column_sel(IP_ISR_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_ISR_COL)
- BITS_PER_REG)) <= ip_irpt_status_reg(i); -- output IP interrupt status register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(IP_IER) = '1'
and column_sel(IP_IER_COL) = '1') Then
for i in 0 to IP_IRPT_HIGH_INDEX loop
-- irpt_read_data(i+32) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
irpt_read_data
(i+(C_IPIF_DWIDTH
- (BITS_PER_REG*IP_IER_COL)
- BITS_PER_REG)) <= ip_irpt_enable_reg(i); -- output IP interrupt enable register values
End loop;
irpt_rdack <= '1'; -- set the acknowledge handshake
Elsif (Interrupt_RdCE(DEVICE_GIE) = '1'
and column_sel(DEVICE_GIE_COL) = '1') Then
-- irpt_read_data(31) <= ipif_glbl_irpt_enable_reg; -- output Global Enable Register value
irpt_read_data(C_IPIF_DWIDTH
- (BITS_PER_REG * DEVICE_GIE_COL) - 1) <= ipif_glbl_irpt_enable_reg;
irpt_rdack <= '1'; -- set the acknowledge handshake
else
irpt_rdack <= '0'; -- don't set the acknowledge handshake
End if;
End process; -- GET_READ_DATA
end generate Exclude_Dev_ISC_RdAck_OR_generate;
end implementation;
| gpl-3.0 | 65c02e3e0e1be345fe865cd94a122413 | 0.451308 | 4.581289 | false | false | false | false |
peteut/nvc | test/parse/literal.vhd | 1 | 931 | -- -*- coding: latin-1 -*-
ARCHITECTURE a OF e IS
SIGNAL pos : INTEGER := 64;
SIGNAL neg : INTEGER := -265;
CONSTANT c : INTEGER := 523;
CONSTANT a : STRING := "hel""lo";
CONSTANT b : STRING := """quote""";
CONSTANT d : INTEGER := 1E3; -- Integer not real
CONSTANT e : REAL := 1.234;
CONSTANT f : REAL := 0.21712;
CONSTANT g : REAL := 1.4e6;
CONSTANT h : REAL := 235.1e-2;
CONSTANT i : INTEGER := 1_2_3_4;
CONSTANT j : REAL := 5_6_7.12_3;
CONSTANT k : ptr := NULL;
CONSTANT l : STRING := "Setup time is too short";
CONSTANT m : STRING := "";
CONSTANT n : STRING := " ";
CONSTANT o : STRING := "A";
CONSTANT p : STRING := """";
CONSTANT q : STRING := %Setup time is too short%;
CONSTANT r : STRING := %%;
CONSTANT s : STRING := % %;
CONSTANT t : STRING := %A%;
CONSTANT u : STRING := %%%%;
constant v : string := "©";
BEGIN
END ARCHITECTURE;
| gpl-3.0 | c8a677b3495e348e7d5e3b4ef353b124 | 0.548872 | 3.232639 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/example_design/k7_mBuf_128x72_exdes.vhd | 1 | 4,990 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity k7_mBuf_128x72_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end k7_mBuf_128x72_exdes;
architecture xilinx of k7_mBuf_128x72_exdes is
signal clk_i : std_logic;
component k7_mBuf_128x72 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(72-1 DOWNTO 0);
DOUT : OUT std_logic_vector(72-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : k7_mBuf_128x72
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | 4a69dce496fae80219dda1b329c59f9c | 0.522645 | 4.84466 | false | false | false | false |
gutelfuldead/zynq_ip_repo | IP_LIBRARY/axistream_spw_lite_1.0/src/streamtest_tb.vhd | 1 | 7,840 | --
-- Test bench for spwstream.
--
-- Tests:
-- * one spwstream instance with SpaceWire signals looped back to itself
-- * sending of bytes, packets and time codes through the SpaceWire link
-- * handling of link disabling and link disconnection
--
-- This test bench is intended to test the buffering logic in spwstream.
-- It does not thoroughly verify behaviour of the receiver, transmitter,
-- signal patterns etc. Please use spwlink_tb.vhd to test those aspects.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.spwpkg.all;
entity streamtest_tb is
end entity;
architecture tb_arch of streamtest_tb is
-- Parameters.
constant sys_clock_freq: real := 20.0e6;
component streamtest is
generic (
sysfreq: real;
txclkfreq: real;
tickdiv: integer range 12 to 24 := 20;
rximpl: spw_implementation_type := impl_generic;
rxchunk: integer range 1 to 4 := 1;
tximpl: spw_implementation_type := impl_generic;
rxfifosize_bits: integer range 6 to 14 := 11;
txfifosize_bits: integer range 2 to 14 := 11 );
port (
clk: in std_logic;
rxclk: in std_logic;
txclk: in std_logic;
rst: in std_logic;
linkstart: in std_logic;
autostart: in std_logic;
linkdisable: in std_logic;
senddata: in std_logic;
sendtick: in std_logic;
txdivcnt: in std_logic_vector(7 downto 0);
linkstarted: out std_logic;
linkconnecting: out std_logic;
linkrun: out std_logic;
linkerror: out std_logic;
gotdata: out std_logic;
dataerror: out std_logic;
tickerror: out std_logic;
spw_di: in std_logic;
spw_si: in std_logic;
spw_do: out std_logic;
spw_so: out std_logic );
end component;
signal sys_clock_enable: std_logic := '0';
signal sysclk: std_logic := '0';
signal s_loopback: std_logic := '0';
signal s_nreceived: integer := 0;
signal s_rst: std_logic := '1';
signal s_linkstart: std_logic;
signal s_autostart: std_logic;
signal s_linkdisable: std_logic;
signal s_divcnt: std_logic_vector(7 downto 0);
signal s_linkrun: std_logic;
signal s_linkerror: std_logic;
signal s_gotdata: std_logic;
signal s_dataerror: std_logic;
signal s_tickerror: std_logic;
signal s_spwdi: std_logic;
signal s_spwsi: std_logic;
signal s_spwdo: std_logic;
signal s_spwso: std_logic;
begin
-- streamtest instance
streamtest_inst: streamtest
generic map (
sysfreq => sys_clock_freq,
txclkfreq => sys_clock_freq,
tickdiv => 16,
rximpl => impl_generic,
rxchunk => 1,
tximpl => impl_generic,
rxfifosize_bits => 9,
txfifosize_bits => 8 )
port map (
clk => sysclk,
rxclk => sysclk,
txclk => sysclk,
rst => s_rst,
linkstart => s_linkstart,
autostart => s_autostart,
linkdisable => s_linkdisable,
senddata => '1',
sendtick => '1',
txdivcnt => s_divcnt,
linkstarted => open,
linkconnecting => open,
linkrun => s_linkrun,
linkerror => s_linkerror,
gotdata => s_gotdata,
dataerror => s_dataerror,
tickerror => s_tickerror,
spw_di => s_spwdi,
spw_si => s_spwsi,
spw_do => s_spwdo,
spw_so => s_spwso );
-- Conditional loopback of SpaceWire signals.
s_spwdi <= s_spwdo when (s_loopback = '1') else '0';
s_spwsi <= s_spwso when (s_loopback = '1') else '0';
-- Generate system clock.
process is
begin
if sys_clock_enable /= '1' then
wait until sys_clock_enable = '1';
end if;
sysclk <= '1';
wait for (0.5 sec) / sys_clock_freq;
sysclk <= '0';
wait for (0.5 sec) / sys_clock_freq;
end process;
-- Verify that error indications remain off.
process is
begin
wait on s_linkerror, s_dataerror, s_tickerror;
assert s_dataerror = '0' report "Detected data error";
assert s_tickerror = '0' report "Detected time code error";
if s_loopback = '1' then
assert s_linkerror /= '1' report "Unexpected link error";
end if;
end process;
-- Verify that data is received regularly when the link is up.
process is
begin
if s_linkrun = '0' or s_gotdata = '1' then
wait until s_linkrun = '1' and s_gotdata = '0';
end if;
wait until s_gotdata = '1' or s_linkrun = '0' for 3 ms;
if s_linkrun = '1' then
assert s_gotdata = '1' report "Link running but no data received";
end if;
end process;
-- Count number of received characters.
process is
begin
wait until rising_edge(sysclk);
if s_gotdata = '1' then
s_nreceived <= s_nreceived + 1;
end if;
end process;
-- Main process.
process is
variable vline: LINE;
begin
report "Starting streamtest test bench";
-- Initialize.
s_loopback <= '1';
s_rst <= '1';
s_linkstart <= '0';
s_autostart <= '0';
s_linkdisable <= '0';
s_divcnt <= "00000001";
sys_clock_enable <= '1';
wait for 1 us;
-- Test link and data transmission.
report "Testing txdivcnt = 1";
s_rst <= '0';
s_linkstart <= '1';
wait for 100 us;
assert s_linkrun = '1' report "Link failed to start";
wait for 50 ms;
-- Check number of received characters.
write(vline, string'("Received "));
write(vline, s_nreceived);
write(vline, string'(" characters in 50 ms."));
writeline(output, vline);
assert s_nreceived > 24000 report "Too few characters received";
-- Test switching to different transmission rate.
report "Testing txdivcnt = 2";
s_divcnt <= "00000010";
wait for 10 ms;
report "Testing txdivcnt = 3";
s_divcnt <= "00000011";
wait for 10 ms;
-- Disable and re-enable link.
report "Testing link disable/re-enable";
s_linkdisable <= '1';
s_divcnt <= "00000001";
wait for 2 ms;
s_linkdisable <= '0';
wait for 100 us;
assert s_linkrun = '1' report "Link failed to start after re-enable";
wait for 10 ms;
-- Cut and reconnect loopback wiring.
report "Testing physical disconnect/reconnect";
s_loopback <= '0';
wait for 2 ms;
s_loopback <= '1';
wait for 100 us;
assert s_linkrun = '1' report "Link failed to start after reconnect";
wait for 10 ms;
s_loopback <= '0';
wait for 2 ms;
s_loopback <= '1';
wait for 100 us;
assert s_linkrun = '1' report "Link failed to start after reconnect (2)";
wait for 10 ms;
-- Shut down.
s_rst <= '1';
wait for 1 us;
sys_clock_enable <= '0';
write(vline, string'("Received "));
write(vline, s_nreceived);
write(vline, string'(" characters."));
writeline(output, vline);
report "Done";
wait;
end process;
end architecture tb_arch;
| mit | c07507a8cfb69a29287563d1d1ec94f1 | 0.534821 | 3.81323 | false | true | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/register/reg_16bit.vhd | 1 | 514 | library IEEE;
use IEEE.std_logic_1164.all;
entity reg16b is
port(clk, load, reset : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"
);
end entity;
architecture reg16b_ARCH of reg16b is
begin
process(clk)
begin
if(clk = '1') then
if(reset = '1') then
output <= "0000000000000000";
elsif(load = '1') then
output <= input;
end if;
end if;
end process;
end architecture;
| gpl-3.0 | 81be0fabbcec60687139418968813da5 | 0.614786 | 3.403974 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/sim/cpu_axi_iic_0_0.vhd | 1 | 9,228 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_iic_v2_0;
USE axi_iic_v2_0.axi_iic;
ENTITY cpu_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_axi_iic_0_0;
ARCHITECTURE cpu_axi_iic_0_0_arch OF cpu_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END cpu_axi_iic_0_0_arch;
| gpl-3.0 | 833eb0f013eb9acfaea4f1eef7379f73 | 0.677287 | 3.219819 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/acticv_mul.vhd | 1 | 5,122 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file acticv_mul.vhd when simulating
-- the core, acticv_mul. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY acticv_mul IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END acticv_mul;
ARCHITECTURE acticv_mul_a OF acticv_mul IS
-- synthesis translate_off
COMPONENT wrapped_acticv_mul
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_acticv_mul USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
GENERIC MAP (
c_a_width => 16,
c_b_width => 16,
c_c_width => 48,
c_concat_width => 48,
c_constant_1 => 1,
c_d_width => 16,
c_has_a => 1,
c_has_acin => 0,
c_has_acout => 0,
c_has_b => 1,
c_has_bcin => 0,
c_has_bcout => 0,
c_has_c => 0,
c_has_carrycascin => 0,
c_has_carrycascout => 0,
c_has_carryin => 0,
c_has_carryout => 0,
c_has_ce => 1,
c_has_cea => 0,
c_has_ceb => 0,
c_has_cec => 0,
c_has_ceconcat => 0,
c_has_ced => 0,
c_has_cem => 0,
c_has_cep => 0,
c_has_cesel => 0,
c_has_concat => 0,
c_has_d => 1,
c_has_indep_ce => 0,
c_has_indep_sclr => 0,
c_has_pcin => 0,
c_has_pcout => 0,
c_has_sclr => 0,
c_has_sclra => 0,
c_has_sclrb => 0,
c_has_sclrc => 0,
c_has_sclrconcat => 0,
c_has_sclrd => 0,
c_has_sclrm => 0,
c_has_sclrp => 0,
c_has_sclrsel => 0,
c_latency => 128,
c_model_type => 0,
c_opmodes => "0000000001010001000",
c_p_lsb => 0,
c_p_msb => 31,
c_reg_config => "00000000000010010011000000000000",
c_sel_width => 0,
c_test_core => 0,
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_acticv_mul
PORT MAP (
clk => clk,
ce => ce,
a => a,
b => b,
d => d,
p => p
);
-- synthesis translate_on
END acticv_mul_a;
| bsd-2-clause | 275437a86fb4f211737db34165e452f0 | 0.522062 | 4.004691 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized.vhd | 1 | 10,904 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_eb_fifo_counted_resized.vhd when simulating
-- the core, k7_eb_fifo_counted_resized. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_eb_fifo_counted_resized IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END k7_eb_fifo_counted_resized;
ARCHITECTURE k7_eb_fifo_counted_resized_a OF k7_eb_fifo_counted_resized IS
-- synthesis translate_off
COMPONENT wrapped_k7_eb_fifo_counted_resized
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC;
rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_eb_fifo_counted_resized USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 13,
c_default_value => "BlankString",
c_din_width => 64,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 64,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 1,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 1,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "8kx4",
c_prog_empty_thresh_assert_val => 512,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 513,
c_prog_empty_type => 1,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 6144,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 6143,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 12,
c_rd_depth => 8192,
c_rd_freq => 1,
c_rd_pntr_width => 13,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 12,
c_wr_depth => 8192,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 13,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_eb_fifo_counted_resized
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid,
rd_data_count => rd_data_count,
wr_data_count => wr_data_count,
prog_full => prog_full,
prog_empty => prog_empty
);
-- synthesis translate_on
END k7_eb_fifo_counted_resized_a;
| gpl-2.0 | 65c0c28effe7599180c545b5e5d746ad | 0.545304 | 3.304242 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/simulation/bmg_stim_gen.vhd | 1 | 15,975 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(64,64);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(64,64);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(4096,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEB_VCC: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEB_GND: STD_LOGIC_VECTOR(7 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(11 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(11 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_REG_B(0);
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH => 64,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>64,
DOUT_WIDTH =>64 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA <= IF_THEN_ELSE(DO_WRITE_A='1', WEA_VCC,WEA_GND) ;
WEB <= IF_THEN_ELSE(DO_WRITE_B='1', WEB_VCC,WEB_GND) ;
END ARCHITECTURE;
| gpl-2.0 | fe52435fa53db4f443217bf8e241797a | 0.577089 | 3.208476 | false | false | false | false |
peteut/nvc | test/simp/ffold.vhd | 1 | 7,804 | package pack is
function add4(x : in integer) return integer;
function add1(x : in integer) return integer;
function log2(x : in integer) return integer;
function case1(x : in integer) return integer;
function adddef(x, y : in integer := 5) return integer;
function chain1(x : string) return boolean;
function chain2(x, y : string) return boolean;
function flip(x : bit_vector(3 downto 0)) return bit_vector;
type real_vector is array (natural range <>) of real;
function lookup(index : integer) return real;
function get_bitvec(x, y : integer) return bit_vector;
function approx(x, y : real; t : real := 0.001) return boolean;
function get_string(x : integer) return string;
function get_string(x : real) return string;
function get_string(x : character) return string;
function get_string(x : time) return string;
function needs_heap(x : integer) return integer;
function sum_left_right(x : bit_vector) return integer;
procedure p5(x : in integer; y : out integer);
function call_proc(x : in integer) return integer;
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec;
function min(x, y : integer) return integer;
function get_left(x : bit_vector) return bit;
function test_alloc_proc(a, b, c : string) return boolean;
end package;
package body pack is
function add4(x : in integer) return integer is
begin
return x + 4;
end function;
function add1(x : in integer) return integer is
begin
return x + 1;
end function;
function log2(x : in integer) return integer is
variable r : integer := 0;
variable c : integer := 1;
begin
--while true loop
--end loop;
if x <= 1 then
r := 1;
else
while c < x loop
r := r + 1;
c := c * 2;
end loop;
end if;
return r;
end function;
function case1(x : in integer) return integer is
begin
case x is
when 1 =>
return 2;
when 2 =>
return 3;
when others =>
return 5;
end case;
end function;
function adddef(x, y : in integer := 5) return integer is
begin
return x + y;
end function;
function chain1(x : string) return boolean is
variable r : boolean := false;
begin
if x = "hello" then
r := true;
end if;
return r;
end function;
function chain2(x, y : string) return boolean is
variable r : boolean := false;
begin
if chain1(x) or chain1(y) then
r := true;
end if;
return r;
end function;
function flip(x : bit_vector(3 downto 0)) return bit_vector is
variable r : bit_vector(3 downto 0);
begin
r(0) := x(3);
r(1) := x(2);
r(2) := x(1);
r(3) := x(0);
return r;
end function;
function lookup(index : integer) return real is
constant table : real_vector := (
0.62, 61.62, 71.7, 17.25, 26.15, 651.6, 0.45, 5.761 );
begin
return table(index);
end function;
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
function get_string(x : integer) return string is
begin
return integer'image(x);
end function;
function get_string(x : real) return string is
begin
return real'image(x);
end function;
function get_string(x : character) return string is
begin
return character'image(x);
end function;
function get_string(x : time) return string is
begin
return time'image(x);
end function;
function needs_heap(x : integer) return integer is
begin
if integer'image(x)'length = 2 then
return x * 2;
else
return x / 2;
end if;
end function;
function sum_left_right(x : bit_vector) return integer is
begin
return x'left + x'right;
end function;
procedure p5(x : in integer; y : out integer) is
variable k : integer := x + 1;
begin
y := k;
end procedure;
function call_proc(x : in integer) return integer is
variable y : integer;
begin
p5(x, y);
return y;
end function;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
function min(x, y : integer) return integer is
begin
if x > y then
return y;
else
return x;
end if;
end function;
function get_left(x : bit_vector) return bit is
constant l : integer := x'left;
variable v : bit_vector(1 to x'right);
constant m : integer := min(x'length, v'length) + 1;
begin
return x(l);
end function;
type line is access string;
procedure cat_str(x : inout line; s : in string) is
variable tmp : line := x;
variable len : integer := 0;
begin
if x /= null then
len := x.all'length;
end if;
x := new string(1 to s'length + len);
if tmp /= null then
x.all(1 to len) := tmp.all;
end if;
x.all(1 + len to s'length + len) := s;
if tmp /= null then
deallocate(tmp);
end if;
end procedure;
function test_alloc_proc(a, b, c : string) return boolean is
variable l : line;
variable r : boolean;
begin
cat_str(l, a);
cat_str(l, b);
r := l.all = c;
deallocate(l);
return r;
end function;
end package body;
-------------------------------------------------------------------------------
entity ffold is
end entity;
use work.pack.all;
architecture a of ffold is
begin
b1: block is
signal s0 : integer := add1(5);
signal s1 : integer := add4(1);
signal s2 : integer := log2(11);
signal s3 : integer := log2(integer(real'(5.5)));
signal s4 : integer := case1(1);
signal s5 : integer := case1(7);
signal s6 : integer := adddef;
signal s7 : boolean := chain2("foo", "hello");
signal s8 : boolean := flip("1010") = "0101";
signal s9 : boolean := flip("1010") = "0111";
signal s10 : real := lookup(0); -- 0.62;
signal s11 : real := lookup(2); -- 71.7;
signal s12 : boolean := get_bitvec(1, 2) = "00";
signal s13 : boolean := approx(1.0000, 1.0001);
signal s14 : boolean := approx(1.0000, 1.01);
signal s15 : boolean := get_string(5) = "5";
signal s16 : boolean := get_string(2.5) = "2.5";
signal s17 : boolean := get_string('F') = "'F'";
signal s18 : boolean := get_string(1 fs) = "1 FS";
signal s19 : integer := needs_heap(40);
signal s20 : integer := sum_left_right("101010");
signal s21 : integer := call_proc(1);
signal s22 : boolean := make_rec("010", 20).y = 20;
signal s23 : boolean := get_left("1010") = '1';
signal s24 : boolean := make_rec("010", 4).x = "010";
signal s25 : boolean := test_alloc_proc("hello", "world", "helloworld");
signal s26 : boolean := test_alloc_proc("hello", "moo", "hellomoowee");
begin
end block;
end architecture;
| gpl-3.0 | 8e35744e163f515e0d9991cc6b6d2750 | 0.544593 | 3.735759 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/tlpControl.vhd | 1 | 88,243 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
--use work.busmacro_xc4v_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tlpControl is
port (
-- Test pin, emulating DDR data flow discontinuity
mbuf_UserFull : IN std_logic;
trn_Blinker : OUT std_logic;
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- Interrupter triggers
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
Sys_Int_Enable : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: PC-->FPGA
reg01_tv : OUT std_logic;
reg01_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_tv : OUT std_logic;
reg02_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_tv : OUT std_logic;
reg03_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_tv : OUT std_logic;
reg04_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_tv : OUT std_logic;
reg05_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_tv : OUT std_logic;
reg06_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_tv : OUT std_logic;
reg07_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_tv : OUT std_logic;
reg08_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_tv : OUT std_logic;
reg09_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_tv : OUT std_logic;
reg10_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_tv : OUT std_logic;
reg11_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_tv : OUT std_logic;
reg12_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_tv : OUT std_logic;
reg13_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_tv : OUT std_logic;
reg14_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg15_tv : OUT std_logic;
reg15_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg16_tv : OUT std_logic;
reg16_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg17_tv : OUT std_logic;
reg17_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg18_tv : OUT std_logic;
reg18_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg19_tv : OUT std_logic;
reg19_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg20_tv : OUT std_logic;
reg20_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg21_tv : OUT std_logic;
reg21_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg22_tv : OUT std_logic;
reg22_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg23_tv : OUT std_logic;
reg23_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg24_tv : OUT std_logic;
reg24_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg25_tv : OUT std_logic;
reg25_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: FPGA-->PC
reg01_rv : IN std_logic;
reg01_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_rv : IN std_logic;
reg02_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_rv : IN std_logic;
reg03_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_rv : IN std_logic;
reg04_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_rv : IN std_logic;
reg05_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_rv : IN std_logic;
reg06_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_rv : IN std_logic;
reg07_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_rv : IN std_logic;
reg08_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_rv : IN std_logic;
reg09_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_rv : IN std_logic;
reg10_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_rv : IN std_logic;
reg11_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_rv : IN std_logic;
reg12_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_rv : IN std_logic;
reg13_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_rv : IN std_logic;
reg14_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg15_rv : IN std_logic;
reg15_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg16_rv : IN std_logic;
reg16_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg17_rv : IN std_logic;
reg17_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg18_rv : IN std_logic;
reg18_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg19_rv : IN std_logic;
reg19_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg20_rv : IN std_logic;
reg20_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg21_rv : IN std_logic;
reg21_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg22_rv : IN std_logic;
reg22_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg23_rv : IN std_logic;
reg23_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg24_rv : IN std_logic;
reg24_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg25_rv : IN std_logic;
reg25_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE debug signals
debug_in_1i : OUT std_logic_vector(31 downto 0);
debug_in_2i : OUT std_logic_vector(31 downto 0);
debug_in_3i : OUT std_logic_vector(31 downto 0);
debug_in_4i : OUT std_logic_vector(31 downto 0);
-- Event Buffer FIFO interface
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_re : OUT std_logic;
eb_FIFO_empty : IN std_logic;
eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_ow : IN std_logic;
eb_FIFO_data_count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
pio_reading_status : OUT std_logic;
eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst : OUT std_logic;
H2B_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
B2H_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
Link_Buf_full : IN std_logic;
-- Debugging signals
DMA_us_Done : OUT std_logic;
DMA_us_Busy : OUT std_logic;
DMA_us_Busy_LED : OUT std_logic;
DMA_ds_Done : OUT std_logic;
DMA_ds_Busy : OUT std_logic;
DMA_ds_Busy_LED : OUT std_logic;
-- DDR control interface
DDR_Ready : IN std_logic;
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
DDR_rdc_sof : OUT std_logic;
DDR_rdc_eof : OUT std_logic;
DDR_rdc_v : OUT std_logic;
DDR_rdc_FA : OUT std_logic;
DDR_rdc_Shift : OUT std_logic;
DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : IN std_logic;
-- DDR_rdD_sof : IN std_logic;
-- DDR_rdD_eof : IN std_logic;
-- DDR_rdDout_V : IN std_logic;
-- DDR_rdDout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : OUT std_logic;
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
-- Common interface
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rdst_rdy_n : OUT std_logic;
trn_rnp_ok_n : OUT std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- Transaction transmit interface
trn_tsof_n : OUT std_logic;
trn_teof_n : OUT std_logic;
trn_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_trem_n : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_terrfwd_n : OUT std_logic;
trn_tsrc_rdy_n : OUT std_logic;
trn_tdst_rdy_n : IN std_logic;
trn_tsrc_dsc_n : OUT std_logic;
trn_tdst_dsc_n : IN std_logic;
trn_tbuf_av : IN std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
Format_Shower : OUT std_logic;
-- Interrupt Interface
cfg_interrupt_n : OUT std_logic;
cfg_interrupt_rdy_n : IN std_logic;
cfg_interrupt_mmenable : IN std_logic_VECTOR(2 downto 0);
cfg_interrupt_msienable : IN std_logic;
cfg_interrupt_di : OUT std_logic_VECTOR(7 downto 0);
cfg_interrupt_do : IN std_logic_VECTOR(7 downto 0);
cfg_interrupt_assert_n : OUT std_logic;
Irpt_Req : OUT std_logic;
Irpt_RE : OUT std_logic;
IrptStatesOut : OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed : OUT std_logic;
-- Local signals
pcie_link_width : IN std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : IN std_logic_vector(16-1 downto 0);
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0);
--for debug-------------------------------------------------
dsDMA_Start : OUT std_logic;
dsDMA_Stop : OUT std_logic;
dsDMA_Start2 : OUT std_logic;
dsDMA_Stop2 : OUT std_logic;
dsDMA_Channel_Rst : OUT std_logic;
usDMA_Start : OUT std_logic;
usDMA_Stop : OUT std_logic;
usDMA_Start2 : OUT std_logic;
usDMA_Stop2 : OUT std_logic;
usDMA_Channel_Rst : OUT std_logic;
DMA_us_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn0 : OUT std_logic;
Regs_WrMask0 : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr0 : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin0 : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEn1 : OUT std_logic;
Regs_WrMask1 : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr1 : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin1 : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end entity tlpControl;
architecture Behavioral of tlpControl is
signal trn_lnk_up_i : std_logic;
---- Rx transaction control
component rx_Transact
port (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rdst_rdy_n : OUT std_logic;
trn_rnp_ok_n : OUT std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- MRd Channel
pioCplD_Req : OUT std_logic;
pioCplD_RE : IN std_logic;
pioCplD_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
pio_FC_stop : IN std_logic;
-- MRd-downstream packet Channel
dsMRd_Req : OUT std_logic;
dsMRd_RE : IN std_logic;
dsMRd_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Upstream MWr/MRd Channel
usTlp_Req : OUT std_logic;
usTlp_RE : IN std_logic;
usTlp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : IN std_logic;
us_Last_sof : IN std_logic;
us_Last_eof : IN std_logic;
-- Irpt Channel
Irpt_Req : OUT std_logic;
Irpt_RE : IN std_logic;
Irpt_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
IrptStatesOut : OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed : OUT std_logic;
-- Interrupt Interface
cfg_interrupt_n : OUT std_logic;
cfg_interrupt_rdy_n : IN std_logic;
cfg_interrupt_mmenable : IN std_logic_VECTOR(2 downto 0);
cfg_interrupt_msienable : IN std_logic;
cfg_interrupt_di : OUT std_logic_VECTOR(7 downto 0);
cfg_interrupt_do : IN std_logic_VECTOR(7 downto 0);
cfg_interrupt_assert_n : OUT std_logic;
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_data_count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
eb_FIFO_Empty : IN std_logic;
eb_FIFO_Reading : IN std_logic;
pio_reading_status : OUT std_logic;
-- Registers Write Port
Regs_WrEn0 : OUT std_logic;
Regs_WrMask0 : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr0 : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin0 : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEn1 : OUT std_logic;
Regs_WrMask1 : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr1 : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin1 : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : OUT std_logic;
ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- --------------------------
-- Registers
DMA_ds_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : IN std_logic;
DMA_ds_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : OUT std_logic;
DMA_ds_Busy : OUT std_logic;
DMA_ds_Tout : OUT std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : IN std_logic;
dsBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : IN std_logic;
dsLeng_Lo7b_True : IN std_logic;
dsDMA_Start : IN std_logic;
dsDMA_Stop : IN std_logic;
dsDMA_Start2 : IN std_logic;
dsDMA_Stop2 : IN std_logic;
dsDMA_Channel_Rst : IN std_logic;
dsDMA_Cmd_Ack : OUT std_logic;
DMA_us_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : IN std_logic;
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
DMA_us_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : OUT std_logic;
DMA_us_Busy : OUT std_logic;
DMA_us_Tout : OUT std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : IN std_logic;
usBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : IN std_logic;
usLeng_Lo7b_True : IN std_logic;
usDMA_Start : IN std_logic;
usDMA_Stop : IN std_logic;
usDMA_Start2 : IN std_logic;
usDMA_Stop2 : IN std_logic;
usDMA_Channel_Rst : IN std_logic;
usDMA_Cmd_Ack : OUT std_logic;
MRd_Channel_Rst : IN std_logic;
Sys_IRQ : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof_A : OUT std_logic;
DDR_wr_eof_A : OUT std_logic;
DDR_wr_v_A : OUT std_logic;
DDR_wr_FA_A : OUT std_logic;
DDR_wr_Shift_A : OUT std_logic;
DDR_wr_Mask_A : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_A : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_sof_B : OUT std_logic;
DDR_wr_eof_B : OUT std_logic;
DDR_wr_v_B : OUT std_logic;
DDR_wr_FA_B : OUT std_logic;
DDR_wr_Shift_B : OUT std_logic;
DDR_wr_Mask_B : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_B : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
Link_Buf_full : IN std_logic;
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt generator signals
IG_Reset : IN std_logic;
IG_Host_Clear : IN std_logic;
IG_Latency : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : OUT std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
-- Additional
cfg_dcommand : IN std_logic_vector(16-1 downto 0);
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end component rx_Transact;
-- Downstream DMA transferred bytes count up
signal ds_DMA_Bytes_Add : std_logic;
signal ds_DMA_Bytes : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
---- Tx transaction control
component tx_Transact
port (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction
trn_tsof_n : OUT std_logic;
trn_teof_n : OUT std_logic;
trn_td : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_trem_n : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_terrfwd_n : OUT std_logic;
trn_tsrc_rdy_n : OUT std_logic;
trn_tdst_rdy_n : IN std_logic;
trn_tsrc_dsc_n : OUT std_logic;
trn_tdst_dsc_n : IN std_logic;
trn_tbuf_av : IN std_logic_vector(C_TBUF_AWIDTH-1 downto 0);
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : OUT std_logic;
us_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- MRd Channel
pioCplD_Req : IN std_logic;
pioCplD_RE : OUT std_logic;
pioCplD_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
pio_FC_stop : OUT std_logic;
-- MRd-downstream packet Channel
dsMRd_Req : IN std_logic;
dsMRd_RE : OUT std_logic;
dsMRd_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Upstream MWr Channel
usTlp_Req : IN std_logic;
usTlp_RE : OUT std_logic;
usTlp_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : OUT std_logic;
us_Last_sof : OUT std_logic;
us_Last_eof : OUT std_logic;
-- Irpt Channel
Irpt_Req : IN std_logic;
Irpt_RE : OUT std_logic;
Irpt_Qout : IN std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Event Buffer FIFO read port
eb_FIFO_re : OUT std_logic;
eb_FIFO_empty : IN std_logic;
eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- With Rx port
Regs_RdAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Message routing method
Msg_Routing : IN std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- DDR read port
DDR_rdc_sof : OUT std_logic;
DDR_rdc_eof : OUT std_logic;
DDR_rdc_v : OUT std_logic;
DDR_rdc_FA : OUT std_logic;
DDR_rdc_Shift : OUT std_logic;
DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : IN std_logic;
-- DDR_rdD_sof : IN std_logic;
-- DDR_rdD_eof : IN std_logic;
-- DDR_rdDout_V : IN std_logic;
-- DDR_rdDout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : OUT std_logic;
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut : OUT std_logic;
Tx_eb_TimeOut : OUT std_logic;
Format_Shower : OUT std_logic;
Tx_Reset : IN std_logic;
mbuf_UserFull : IN std_logic;
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end component tx_Transact;
-- Upstream DMA transferred bytes count up
signal us_DMA_Bytes_Add : std_logic;
signal us_DMA_Bytes : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- ------------------------------------------------
-- United memory space consisting of registers.
--
component Regs_Group
port (
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Event Buffer status
eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst : OUT std_logic;
H2B_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
B2H_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
-- Register Write
Regs_WrEnA : IN std_logic;
Regs_WrMaskA : IN std_logic_vector(2-1 downto 0);
Regs_WrAddrA : IN std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEnB : IN std_logic;
Regs_WrMaskB : IN std_logic_vector(2-1 downto 0);
Regs_WrAddrB : IN std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinB : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_RdAddr : IN std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : IN std_logic;
ds_DMA_Bytes : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Register Values
DMA_ds_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : OUT std_logic;
DMA_ds_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : IN std_logic;
-- DMA_ds_Busy : IN std_logic;
DMA_ds_Tout : IN std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : OUT std_logic;
dsBDA_is_64b : OUT std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : OUT std_logic;
dsLeng_Lo7b_True : OUT std_logic;
dsDMA_Start : OUT std_logic;
dsDMA_Stop : OUT std_logic;
dsDMA_Start2 : OUT std_logic;
dsDMA_Stop2 : OUT std_logic;
dsDMA_Channel_Rst : OUT std_logic;
dsDMA_Cmd_Ack : IN std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : IN std_logic;
us_DMA_Bytes : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
DMA_us_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : OUT std_logic;
us_MWr_Param_Vec : OUT std_logic_vector(6-1 downto 0);
DMA_us_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : IN std_logic;
-- DMA_us_Busy : IN std_logic;
DMA_us_Tout : IN std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : OUT std_logic;
usBDA_is_64b : OUT std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : OUT std_logic;
usLeng_Lo7b_True : OUT std_logic;
usDMA_Start : OUT std_logic;
usDMA_Stop : OUT std_logic;
usDMA_Start2 : OUT std_logic;
usDMA_Stop2 : OUT std_logic;
usDMA_Channel_Rst : OUT std_logic;
usDMA_Cmd_Ack : IN std_logic;
-- Reset signals
MRd_Channel_Rst : OUT std_logic;
Tx_Reset : OUT std_logic;
-- to Interrupt module
Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
Sys_Int_Enable : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System error and info
eb_FIFO_ow : IN std_logic;
Tx_TimeOut : IN std_logic;
Tx_eb_TimeOut : IN std_logic;
Msg_Routing : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
pcie_link_width : IN std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : IN std_logic_vector(16-1 downto 0);
-- Interrupt Generation Signals
IG_Reset : OUT std_logic;
IG_Host_Clear : OUT std_logic;
IG_Latency : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : IN std_logic;
-- Data generator control
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
-- SIMONE Register: PC-->FPGA
reg01_tv : OUT std_logic;
reg01_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_tv : OUT std_logic;
reg02_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_tv : OUT std_logic;
reg03_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_tv : OUT std_logic;
reg04_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_tv : OUT std_logic;
reg05_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_tv : OUT std_logic;
reg06_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_tv : OUT std_logic;
reg07_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_tv : OUT std_logic;
reg08_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_tv : OUT std_logic;
reg09_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_tv : OUT std_logic;
reg10_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_tv : OUT std_logic;
reg11_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_tv : OUT std_logic;
reg12_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_tv : OUT std_logic;
reg13_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_tv : OUT std_logic;
reg14_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg15_tv : OUT std_logic;
reg15_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg16_tv : OUT std_logic;
reg16_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg17_tv : OUT std_logic;
reg17_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg18_tv : OUT std_logic;
reg18_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg19_tv : OUT std_logic;
reg19_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg20_tv : OUT std_logic;
reg20_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg21_tv : OUT std_logic;
reg21_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg22_tv : OUT std_logic;
reg22_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg23_tv : OUT std_logic;
reg23_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg24_tv : OUT std_logic;
reg24_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg25_tv : OUT std_logic;
reg25_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: FPGA-->PC
reg01_rv : IN std_logic;
reg01_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_rv : IN std_logic;
reg02_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_rv : IN std_logic;
reg03_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_rv : IN std_logic;
reg04_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_rv : IN std_logic;
reg05_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_rv : IN std_logic;
reg06_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_rv : IN std_logic;
reg07_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_rv : IN std_logic;
reg08_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_rv : IN std_logic;
reg09_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_rv : IN std_logic;
reg10_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_rv : IN std_logic;
reg11_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_rv : IN std_logic;
reg12_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_rv : IN std_logic;
reg13_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_rv : IN std_logic;
reg14_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg15_rv : IN std_logic;
reg15_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg16_rv : IN std_logic;
reg16_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg17_rv : IN std_logic;
reg17_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg18_rv : IN std_logic;
reg18_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg19_rv : IN std_logic;
reg19_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg20_rv : IN std_logic;
reg20_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg21_rv : IN std_logic;
reg21_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg22_rv : IN std_logic;
reg22_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg23_rv : IN std_logic;
reg23_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg24_rv : IN std_logic;
reg24_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg25_rv : IN std_logic;
reg25_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--SIMONE debug signals
debug_in_1i : OUT std_logic_vector(31 downto 0);
debug_in_2i : OUT std_logic_vector(31 downto 0);
debug_in_3i : OUT std_logic_vector(31 downto 0);
debug_in_4i : OUT std_logic_vector(31 downto 0);
-- Common interface
trn_clk : IN std_logic;
trn_lnk_up_n : IN std_logic;
trn_reset_n : IN std_logic
);
end component Regs_Group;
-- DDR write port
signal DDR_wr_sof_A : std_logic;
signal DDR_wr_eof_A : std_logic;
signal DDR_wr_v_A : std_logic;
signal DDR_wr_FA_A : std_logic;
signal DDR_wr_Shift_A : std_logic;
signal DDR_wr_Mask_A : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_B : std_logic;
signal DDR_wr_eof_B : std_logic;
signal DDR_wr_v_B : std_logic;
signal DDR_wr_FA_B : std_logic;
signal DDR_wr_Shift_B : std_logic;
signal DDR_wr_Mask_B : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_B : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_FA_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
:= (OTHERS=>'0');
signal DDR_wr_sof_A_r1 : std_logic;
signal DDR_wr_eof_A_r1 : std_logic;
signal DDR_wr_v_A_r1 : std_logic;
signal DDR_wr_FA_A_r1 : std_logic;
signal DDR_wr_Shift_A_r1 : std_logic;
signal DDR_wr_Mask_A_r1 : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_A_r2 : std_logic;
signal DDR_wr_eof_A_r2 : std_logic;
signal DDR_wr_v_A_r2 : std_logic;
signal DDR_wr_FA_A_r2 : std_logic;
signal DDR_wr_Shift_A_r2 : std_logic;
signal DDR_wr_Mask_A_r2 : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A_r2 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_sof_A_r3 : std_logic;
signal DDR_wr_eof_A_r3 : std_logic;
signal DDR_wr_v_A_r3 : std_logic;
signal DDR_wr_FA_A_r3 : std_logic;
signal DDR_wr_Shift_A_r3 : std_logic;
signal DDR_wr_Mask_A_r3 : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_A_r3 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eb FIFO read enable
signal eb_FIFO_RdEn_i : std_logic;
-- Flow control signals
signal pio_FC_stop : std_logic;
signal us_FC_stop : std_logic;
signal us_Last_sof : std_logic;
signal us_Last_eof : std_logic;
-- Signals between Tx_Transact and Rx_Transact
signal pioCplD_Req : std_logic;
signal pioCplD_RE : std_logic;
signal pioCplD_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- MRd-downstream packet Channel
signal dsMRd_Req : std_logic;
signal dsMRd_RE : std_logic;
signal dsMRd_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Upstream MWr Channel
signal usTlp_Req : std_logic;
signal usTlp_RE : std_logic;
signal usTlp_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Irpt Channel
signal Irpt_Req_i : std_logic;
signal Irpt_RE_i : std_logic;
signal Irpt_Qout : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Registers Write Port
signal Regs_WrEnA : std_logic;
signal Regs_WrMaskA : std_logic_vector(2-1 downto 0);
signal Regs_WrAddrA : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrEnB : std_logic;
signal Regs_WrMaskB : std_logic_vector(2-1 downto 0);
signal Regs_WrAddrB : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Dex parameters to downstream DMA
-- signal DMA_ds_PA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal DMA_ds_HA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal DMA_ds_BDA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal DMA_ds_Length : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- signal DMA_ds_Control : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal dsDMA_BDA_eq_Null : std_logic;
signal DMA_ds_Status : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Done_i : std_logic;
signal DMA_ds_Busy_i : std_logic;
signal DMA_ds_Busy_led_i : std_logic;
signal cnt_ds_Busy : std_logic_vector(20-1 downto 0);
signal DMA_ds_Tout : std_logic;
-- Calculation in advance, for better timing
signal dsHA_is_64b : std_logic;
signal dsBDA_is_64b : std_logic;
-- Calculation in advance, for better timing
signal dsLeng_Hi19b_True : std_logic;
signal dsLeng_Lo7b_True : std_logic;
-- Downstream Control Signals
signal dsDMA_Start_i : std_logic;
signal dsDMA_Stop_i : std_logic;
signal dsDMA_Start2_i : std_logic;
signal dsDMA_Stop2_i : std_logic;
signal dsDMA_Cmd_Ack : std_logic;
signal dsDMA_Channel_Rst_i : std_logic;
signal DMA_ds_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Dex parameters to upstream DMA
signal DMA_us_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_BDA_eq_Null : std_logic;
signal us_MWr_Param_Vec : std_logic_vector(6-1 downto 0);
signal DMA_us_Status : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Done_i : std_logic;
signal DMA_us_Busy_i : std_logic;
signal DMA_us_Busy_led_i : std_logic;
signal cnt_us_Busy : std_logic_vector(20-1 downto 0);
signal DMA_us_Tout : std_logic;
-- Calculation in advance, for better timing
signal usHA_is_64b : std_logic;
signal usBDA_is_64b : std_logic;
-- Calculation in advance, for better timing
signal usLeng_Hi19b_True : std_logic;
signal usLeng_Lo7b_True : std_logic;
-- Upstream Control Signals
signal usDMA_Start_i : std_logic;
signal usDMA_Stop_i : std_logic;
signal usDMA_Start2_i : std_logic;
signal usDMA_Stop2_i : std_logic;
signal usDMA_Cmd_Ack : std_logic;
signal usDMA_Channel_Rst_i : std_logic;
-- MRd Channel Reset
signal MRd_Channel_Rst : std_logic;
-- Tx module Reset
signal Tx_Reset : std_logic;
-- Tx time out
signal Tx_TimeOut : std_logic;
signal Tx_eb_TimeOut : std_logic;
-- Registers read port
signal Regs_RdAddr : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdQout : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register to Interrupt module
signal Sys_IRQ : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Message routing method
signal Msg_Routing : std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
-- Interrupt Generation Signals
signal IG_Reset : std_logic;
signal IG_Host_Clear : std_logic;
signal IG_Latency : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Asserting : std_logic;
-- Test blinker
signal trn_Blinker_cnt : std_logic_vector(31 downto 0) := (OTHERS=>'0');
begin
DDR_wr_v <= DDR_wr_v_i ;
DDR_wr_sof <= DDR_wr_sof_i ;
DDR_wr_eof <= DDR_wr_eof_i ;
DDR_wr_FA <= DDR_wr_FA_i ;
DDR_wr_Shift <= DDR_wr_Shift_i ;
DDR_wr_Mask <= DDR_wr_Mask_i ;
DDR_wr_din <= DDR_wr_din_i ;
trn_Blinker <= trn_Blinker_cnt(26) ;
DMA_us_Busy <= DMA_us_Busy_i ;
DMA_us_Busy_LED <= DMA_us_Busy_led_i ;
DMA_ds_Busy <= DMA_ds_Busy_i ;
DMA_ds_Busy_LED <= DMA_ds_Busy_led_i ;
--for debug-------------------------------------------------
dsDMA_Start <= dsDMA_Start_i ;
dsDMA_Stop <= dsDMA_Stop_i ;
dsDMA_Start2 <= dsDMA_Start2_i ;
dsDMA_Stop2 <= dsDMA_Stop2_i ;
dsDMA_Channel_Rst <= dsDMA_Channel_Rst_i;
DMA_ds_PA <= DMA_ds_PA_i;
DMA_ds_HA <= DMA_ds_HA_i;
DMA_ds_BDA <= DMA_ds_BDA_i;
DMA_ds_Length <= DMA_ds_Length_i;
DMA_ds_Control <= DMA_ds_Control_i;
eb_FIFO_re <= eb_FIFO_RdEn_i ;
DMA_ds_Done <= DMA_ds_Done_i ;
DMA_us_Done <= DMA_us_Done_i ;
trn_lnk_up_i <= not trn_lnk_up_n;
usDMA_Start <= usDMA_Start_i;
usDMA_Stop <= usDMA_Stop_i;
usDMA_Start2 <= usDMA_Start2_i;
usDMA_Stop2 <= usDMA_Stop2_i;
usDMA_Channel_Rst <= usDMA_Channel_Rst_i;
DMA_us_PA <= DMA_us_PA_i;
DMA_us_HA <= DMA_us_HA_i;
DMA_us_BDA <= DMA_us_BDA_i;
DMA_us_Length <= DMA_us_Length_i;
DMA_us_Control <= DMA_us_Control_i;
Irpt_Req <= Irpt_Req_i; -- OUT std_logic;
Irpt_RE <= Irpt_RE_i; -- OUT std_logic;
-- Register Write
Regs_WrEn0 <= Regs_WrEnA ; -- OUT std_logic;
Regs_WrMask0 <= Regs_WrMaskA ; -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr0 <= Regs_WrAddrA ; -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin0 <= Regs_WrDinA ; -- OUT std_logic_vector(32-1 downto 0);
Regs_WrEn1 <= Regs_WrEnB ; -- OUT std_logic;
Regs_WrMask1 <= Regs_WrMaskB ; -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr1 <= Regs_WrAddrB ; -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin1 <= Regs_WrDinB ; -- OUT std_logic_vector(32-1 downto 0);
-- -------------------------------------------------------
-- Delay DDR write port A for 2 cycles
--
SynDelay_DDR_write_PIO:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
DDR_wr_v_A_r1 <= DDR_wr_v_A;
DDR_wr_sof_A_r1 <= DDR_wr_sof_A;
DDR_wr_eof_A_r1 <= DDR_wr_eof_A;
DDR_wr_FA_A_r1 <= DDR_wr_FA_A;
DDR_wr_Shift_A_r1 <= DDR_wr_Shift_A;
DDR_wr_Mask_A_r1 <= DDR_wr_Mask_A;
DDR_wr_din_A_r1 <= DDR_wr_din_A;
DDR_wr_v_A_r2 <= DDR_wr_v_A_r1;
DDR_wr_sof_A_r2 <= DDR_wr_sof_A_r1;
DDR_wr_eof_A_r2 <= DDR_wr_eof_A_r1;
DDR_wr_FA_A_r2 <= DDR_wr_FA_A_r1;
DDR_wr_Shift_A_r2 <= DDR_wr_Shift_A_r1;
DDR_wr_Mask_A_r2 <= DDR_wr_Mask_A_r1;
DDR_wr_din_A_r2 <= DDR_wr_din_A_r1;
DDR_wr_v_A_r3 <= DDR_wr_v_A_r2;
DDR_wr_sof_A_r3 <= DDR_wr_sof_A_r2;
DDR_wr_eof_A_r3 <= DDR_wr_eof_A_r2;
DDR_wr_FA_A_r3 <= DDR_wr_FA_A_r2;
DDR_wr_Shift_A_r3 <= DDR_wr_Shift_A_r2;
DDR_wr_Mask_A_r3 <= DDR_wr_Mask_A_r2;
DDR_wr_din_A_r3 <= DDR_wr_din_A_r2;
end if;
end process;
-- -------------------------------------------------------
-- DDR writes: DDR Writes
--
SynProc_DDR_write:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
DDR_wr_v_i <= DDR_wr_v_A_r3 or DDR_wr_v_B;
if DDR_wr_v_A_r3 = '1' then
DDR_wr_sof_i <= DDR_wr_sof_A_r3;
DDR_wr_eof_i <= DDR_wr_eof_A_r3;
DDR_wr_FA_i <= DDR_wr_FA_A_r3;
DDR_wr_Shift_i <= DDR_wr_Shift_A_r3;
DDR_wr_Mask_i <= DDR_wr_Mask_A_r3;
DDR_wr_din_i <= DDR_wr_din_A_r3;
elsif DDR_wr_v_B = '1' then
DDR_wr_sof_i <= DDR_wr_sof_B;
DDR_wr_eof_i <= DDR_wr_eof_B;
DDR_wr_FA_i <= DDR_wr_FA_B ;
DDR_wr_Shift_i <= DDR_wr_Shift_B ;
DDR_wr_Mask_i <= DDR_wr_Mask_B;
DDR_wr_din_i <= DDR_wr_din_B;
else
DDR_wr_sof_i <= DDR_wr_sof_i;
DDR_wr_eof_i <= DDR_wr_eof_i;
DDR_wr_FA_i <= DDR_wr_FA_i ;
DDR_wr_Shift_i <= DDR_wr_Shift_i ;
DDR_wr_Mask_i <= DDR_wr_Mask_i;
DDR_wr_din_i <= DDR_wr_din_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- trn blink
--
SynProc_trn_blinker:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_Blinker_cnt <= trn_Blinker_cnt + '1';
end if;
end process;
-- -------------------------------------------------------
-- DMA upstream Busy display
--
SynProc_DMA_us_Busy_LED:
process ( trn_clk, DMA_us_Busy_i)
begin
if DMA_us_Busy_i='1' then
DMA_us_Busy_led_i <= '1';
cnt_us_Busy <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if cnt_us_Busy=X"80000" then
DMA_us_Busy_led_i <= '0';
cnt_us_Busy <= cnt_us_Busy;
else
DMA_us_Busy_led_i <= DMA_us_Busy_led_i;
cnt_us_Busy <= cnt_us_Busy + '1';
end if;
end if;
end process;
-- -------------------------------------------------------
-- DMA downstream Busy display
--
SynProc_DMA_ds_Busy_LED:
process ( trn_clk, DMA_ds_Busy_i)
begin
if DMA_ds_Busy_i='1' then
DMA_ds_Busy_led_i <= '1';
cnt_ds_Busy <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if cnt_ds_Busy=X"FFFFF" then
DMA_ds_Busy_led_i <= '0';
cnt_ds_Busy <= cnt_ds_Busy;
else
DMA_ds_Busy_led_i <= DMA_ds_Busy_led_i;
cnt_ds_Busy <= cnt_ds_Busy + '1';
end if;
end if;
end process;
-- DDR_wr_v <= DDR_wr_v_A or DDR_wr_v_B;
-- DDR_wr_sof <= DDR_wr_sof_A when DDR_wr_v_A='1' else DDR_wr_sof_B;
-- DDR_wr_eof <= DDR_wr_eof_A when DDR_wr_v_A='1' else DDR_wr_eof_B;
-- DDR_wr_FA <= DDR_wr_FA_A when DDR_wr_v_A='1' else DDR_wr_FA_B;
-- DDR_wr_din <= DDR_wr_din_A when DDR_wr_v_A='1' else DDR_wr_din_B;
-- Rx TLP interface
rx_Itf:
rx_Transact
port map(
-- Common ports
trn_clk => trn_clk, -- IN std_logic,
trn_reset_n => trn_lnk_up_i , -- trn_reset_n, -- IN std_logic,
trn_lnk_up_n => trn_lnk_up_n, -- IN std_logic,
-- Transaction receive interface
trn_rsof_n => trn_rsof_n, -- IN std_logic,
trn_reof_n => trn_reof_n, -- IN std_logic,
trn_rd => trn_rd, -- IN std_logic_vector(31 downto 0),
trn_rrem_n => trn_rrem_n, -- IN STD_LOGIC_VECTOR ( 7 downto 0 );
trn_rerrfwd_n => trn_rerrfwd_n, -- IN std_logic,
trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- IN std_logic,
trn_rdst_rdy_n => trn_rdst_rdy_n, -- OUT std_logic,
trn_rnp_ok_n => trn_rnp_ok_n, -- OUT std_logic,
trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- IN std_logic,
trn_rbar_hit_n => trn_rbar_hit_n, -- IN std_logic_vector(6 downto 0),
-- trn_rfc_ph_av => trn_rfc_ph_av, -- IN std_logic_vector(7 downto 0),
-- trn_rfc_pd_av => trn_rfc_pd_av, -- IN std_logic_vector(11 downto 0),
-- trn_rfc_nph_av => trn_rfc_nph_av, -- IN std_logic_vector(7 downto 0),
-- trn_rfc_npd_av => trn_rfc_npd_av, -- IN std_logic_vector(11 downto 0),
-- trn_rfc_cplh_av => trn_rfc_cplh_av, -- IN std_logic_vector(7 downto 0),
-- trn_rfc_cpld_av => trn_rfc_cpld_av, -- IN std_logic_vector(11 downto 0),
-- MRd Channel
pioCplD_Req => pioCplD_Req, -- OUT std_logic;
pioCplD_RE => pioCplD_RE, -- IN std_logic;
pioCplD_Qout => pioCplD_Qout, -- OUT std_logic_vector(96 downto 0);
pio_FC_stop => pio_FC_stop, -- IN std_logic;
-- downstream MRd Channel
dsMRd_Req => dsMRd_Req, -- OUT std_logic;
dsMRd_RE => dsMRd_RE, -- IN std_logic;
dsMRd_Qout => dsMRd_Qout, -- OUT std_logic_vector(96 downto 0);
-- Upstream MWr/MRd Channel
usTlp_Req => usTlp_Req, -- OUT std_logic;
usTlp_RE => usTlp_RE, -- IN std_logic;
usTlp_Qout => usTlp_Qout, -- OUT std_logic_vector(96 downto 0);
us_FC_stop => us_FC_stop, -- IN std_logic;
us_Last_sof => us_Last_sof, -- IN std_logic;
us_Last_eof => us_Last_eof, -- IN std_logic;
-- Irpt Channel
Irpt_Req => Irpt_Req_i, -- OUT std_logic;
Irpt_RE => Irpt_RE_i, -- IN std_logic;
Irpt_Qout => Irpt_Qout, -- OUT std_logic_vector(96 downto 0);
IrptStatesOut => IrptStatesOut, --OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed => Interrupts_ORed, -- OUT std_logic;
-- Interrupt Interface
cfg_interrupt_n => cfg_interrupt_n , -- OUT std_logic;
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n , -- IN std_logic;
cfg_interrupt_mmenable => cfg_interrupt_mmenable , -- IN std_logic_VECTOR(2 downto 0);
cfg_interrupt_msienable => cfg_interrupt_msienable , -- IN std_logic;
cfg_interrupt_di => cfg_interrupt_di , -- OUT std_logic_VECTOR(7 downto 0);
cfg_interrupt_do => cfg_interrupt_do , -- IN std_logic_VECTOR(7 downto 0);
cfg_interrupt_assert_n => cfg_interrupt_assert_n , -- OUT std_logic;
-- Event Buffer write port
eb_FIFO_we => eb_FIFO_we , -- OUT std_logic;
eb_FIFO_wsof => eb_FIFO_wsof , -- OUT std_logic;
eb_FIFO_weof => eb_FIFO_weof , -- OUT std_logic;
eb_FIFO_din => eb_FIFO_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_data_count => eb_FIFO_data_count, -- IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
eb_FIFO_Empty => eb_FIFO_Empty , -- IN std_logic;
eb_FIFO_Reading => eb_FIFO_RdEn_i , -- IN std_logic;
pio_reading_status => pio_reading_status , -- OUT std_logic;
-- Register Write
Regs_WrEn0 => Regs_WrEnA , -- OUT std_logic;
Regs_WrMask0 => Regs_WrMaskA , -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr0 => Regs_WrAddrA , -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin0 => Regs_WrDinA , -- OUT std_logic_vector(32-1 downto 0);
Regs_WrEn1 => Regs_WrEnB , -- OUT std_logic;
Regs_WrMask1 => Regs_WrMaskB , -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr1 => Regs_WrAddrB , -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin1 => Regs_WrDinB , -- OUT std_logic_vector(32-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add => ds_DMA_Bytes_Add , -- OUT std_logic;
ds_DMA_Bytes => ds_DMA_Bytes , -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers
DMA_ds_PA => DMA_ds_PA_i , -- IN std_logic_vector(63 downto 0);
DMA_ds_HA => DMA_ds_HA_i , -- IN std_logic_vector(63 downto 0);
DMA_ds_BDA => DMA_ds_BDA_i , -- IN std_logic_vector(63 downto 0);
DMA_ds_Length => DMA_ds_Length_i , -- IN std_logic_vector(31 downto 0);
DMA_ds_Control => DMA_ds_Control_i , -- IN std_logic_vector(31 downto 0);
dsDMA_BDA_eq_Null => dsDMA_BDA_eq_Null , -- IN std_logic;
DMA_ds_Status => DMA_ds_Status , -- OUT std_logic_vector(31 downto 0);
DMA_ds_Done => DMA_ds_Done_i , -- OUT std_logic;
DMA_ds_Busy => DMA_ds_Busy_i , -- OUT std_logic;
DMA_ds_Tout => DMA_ds_Tout , -- OUT std_logic;
dsHA_is_64b => dsHA_is_64b , -- IN std_logic;
dsBDA_is_64b => dsBDA_is_64b , -- IN std_logic;
dsLeng_Hi19b_True => dsLeng_Hi19b_True , -- IN std_logic;
dsLeng_Lo7b_True => dsLeng_Lo7b_True , -- IN std_logic;
dsDMA_Start => dsDMA_Start_i , -- IN std_logic;
dsDMA_Stop => dsDMA_Stop_i , -- IN std_logic;
dsDMA_Start2 => dsDMA_Start2_i , -- IN std_logic;
dsDMA_Stop2 => dsDMA_Stop2_i , -- IN std_logic;
dsDMA_Channel_Rst => dsDMA_Channel_Rst_i , -- IN std_logic;
dsDMA_Cmd_Ack => dsDMA_Cmd_Ack , -- OUT std_logic;
DMA_us_PA => DMA_us_PA_i , -- IN std_logic_vector(63 downto 0);
DMA_us_HA => DMA_us_HA_i , -- IN std_logic_vector(63 downto 0);
DMA_us_BDA => DMA_us_BDA_i , -- IN std_logic_vector(63 downto 0);
DMA_us_Length => DMA_us_Length_i , -- IN std_logic_vector(31 downto 0);
DMA_us_Control => DMA_us_Control_i , -- IN std_logic_vector(31 downto 0);
usDMA_BDA_eq_Null => usDMA_BDA_eq_Null , -- IN std_logic;
us_MWr_Param_Vec => us_MWr_Param_Vec , -- IN std_logic_vector(6-1 downto 0);
DMA_us_Status => DMA_us_Status , -- OUT std_logic_vector(31 downto 0);
DMA_us_Done => DMA_us_Done_i , -- OUT std_logic;
DMA_us_Busy => DMA_us_Busy_i , -- OUT std_logic;
DMA_us_Tout => DMA_us_Tout , -- OUT std_logic;
usHA_is_64b => usHA_is_64b , -- IN std_logic;
usBDA_is_64b => usBDA_is_64b , -- IN std_logic;
usLeng_Hi19b_True => usLeng_Hi19b_True , -- IN std_logic;
usLeng_Lo7b_True => usLeng_Lo7b_True , -- IN std_logic;
usDMA_Start => usDMA_Start_i , -- IN std_logic;
usDMA_Stop => usDMA_Stop_i , -- IN std_logic;
usDMA_Start2 => usDMA_Start2_i , -- IN std_logic;
usDMA_Stop2 => usDMA_Stop2_i , -- IN std_logic;
usDMA_Channel_Rst => usDMA_Channel_Rst_i , -- IN std_logic;
usDMA_Cmd_Ack => usDMA_Cmd_Ack , -- OUT std_logic;
-- Reset signals
MRd_Channel_Rst => MRd_Channel_Rst , -- IN std_logic;
-- to Interrupt module
Sys_IRQ => Sys_IRQ , -- IN std_logic_vector(31 downto 0);
IG_Reset => IG_Reset ,
IG_Host_Clear => IG_Host_Clear ,
IG_Latency => IG_Latency ,
IG_Num_Assert => IG_Num_Assert ,
IG_Num_Deassert => IG_Num_Deassert ,
IG_Asserting => IG_Asserting ,
DAQ_irq => DAQ_irq , -- IN std_logic;
CTL_irq => CTL_irq , -- IN std_logic;
DLM_irq => DLM_irq , -- IN std_logic;
DAQTOUT_irq => DAQTOUT_irq , -- IN std_logic;
CTLTOUT_irq => CTLTOUT_irq , -- IN std_logic;
DLMTOUT_irq => DLMTOUT_irq , -- IN std_logic;
-- DDR write port
DDR_wr_sof_A => DDR_wr_sof_A , -- OUT std_logic;
DDR_wr_eof_A => DDR_wr_eof_A , -- OUT std_logic;
DDR_wr_v_A => DDR_wr_v_A , -- OUT std_logic;
DDR_wr_FA_A => DDR_wr_FA_A , -- OUT std_logic;
DDR_wr_Shift_A => DDR_wr_Shift_A , -- OUT std_logic;
DDR_wr_Mask_A => DDR_wr_Mask_A , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_A => DDR_wr_din_A , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_sof_B => DDR_wr_sof_B , -- OUT std_logic;
DDR_wr_eof_B => DDR_wr_eof_B , -- OUT std_logic;
DDR_wr_v_B => DDR_wr_v_B , -- OUT std_logic;
DDR_wr_FA_B => DDR_wr_FA_B , -- OUT std_logic;
DDR_wr_Shift_B => DDR_wr_Shift_B , -- OUT std_logic;
DDR_wr_Mask_B => DDR_wr_Mask_B , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_B => DDR_wr_din_B , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
Link_Buf_full => Link_Buf_full , -- IN std_logic;
-- Data generator table write
tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(15 downto 0)
localID => localID -- IN std_logic_vector(15 downto 0)
);
-- Tx TLP interface
tx_Itf:
tx_Transact
port map(
-- Common ports
trn_clk => trn_clk, -- IN std_logic,
trn_reset_n => trn_lnk_up_i , -- trn_reset_n, -- IN std_logic,
trn_lnk_up_n => trn_lnk_up_n, -- IN std_logic,
-- Transaction
trn_tsof_n => trn_tsof_n, -- OUT std_logic,
trn_teof_n => trn_teof_n, -- OUT std_logic,
trn_td => trn_td, -- OUT std_logic_vector(31 downto 0),
trn_trem_n => trn_trem_n, -- OUT STD_LOGIC_VECTOR ( 7 downto 0 );
trn_terrfwd_n => trn_terrfwd_n, -- OUT std_logic,
trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- OUT std_logic,
trn_tdst_rdy_n => trn_tdst_rdy_n, -- IN std_logic,
trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- OUT std_logic,
trn_tdst_dsc_n => trn_tdst_dsc_n, -- IN std_logic,
trn_tbuf_av => trn_tbuf_av, -- IN std_logic_vector(6 downto 0),
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add => us_DMA_Bytes_Add, -- OUT std_logic;
us_DMA_Bytes => us_DMA_Bytes, -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- MRd Channel
pioCplD_Req => pioCplD_Req, -- IN std_logic;
pioCplD_RE => pioCplD_RE, -- OUT std_logic;
pioCplD_Qout => pioCplD_Qout, -- IN std_logic_vector(96 downto 0);
pio_FC_stop => pio_FC_stop, -- OUT std_logic;
-- downstream MRd Channel
dsMRd_Req => dsMRd_Req, -- IN std_logic;
dsMRd_RE => dsMRd_RE, -- OUT std_logic;
dsMRd_Qout => dsMRd_Qout, -- IN std_logic_vector(96 downto 0);
-- Upstream MWr/MRd Channel
usTlp_Req => usTlp_Req, -- IN std_logic;
usTlp_RE => usTlp_RE, -- OUT std_logic;
usTlp_Qout => usTlp_Qout, -- IN std_logic_vector(96 downto 0);
us_FC_stop => us_FC_stop, -- OUT std_logic;
us_Last_sof => us_Last_sof, -- OUT std_logic;
us_Last_eof => us_Last_eof, -- OUT std_logic;
-- Irpt Channel
Irpt_Req => Irpt_Req_i, -- IN std_logic;
Irpt_RE => Irpt_RE_i, -- OUT std_logic;
Irpt_Qout => Irpt_Qout, -- IN std_logic_vector(96 downto 0);
-- Event Buffer FIFO read port
eb_FIFO_re => eb_FIFO_RdEn_i, -- OUT std_logic;
eb_FIFO_empty => eb_FIFO_empty , -- IN std_logic;
eb_FIFO_qout => eb_FIFO_qout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers read
Regs_RdAddr => Regs_RdAddr, -- OUT std_logic_vector(15 downto 0);
Regs_RdQout => Regs_RdQout, -- IN std_logic_vector(31 downto 0);
-- Message routing method
Msg_Routing => Msg_Routing,
-- DDR read port
DDR_rdc_sof => DDR_rdc_sof , -- OUT std_logic;
DDR_rdc_eof => DDR_rdc_eof , -- OUT std_logic;
DDR_rdc_v => DDR_rdc_v , -- OUT std_logic;
DDR_rdc_FA => DDR_rdc_FA , -- OUT std_logic;
DDR_rdc_Shift => DDR_rdc_Shift , -- OUT std_logic;
DDR_rdc_din => DDR_rdc_din , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full => DDR_rdc_full , -- IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn => DDR_FIFO_RdEn , -- OUT std_logic;
DDR_FIFO_Empty => DDR_FIFO_Empty , -- IN std_logic;
DDR_FIFO_RdQout => DDR_FIFO_RdQout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR_rdD_sof => DDR_rdD_sof , -- IN std_logic;
-- DDR_rdD_eof => DDR_rdD_eof , -- IN std_logic;
-- DDR_rdDout_V => DDR_rdDout_V , -- IN std_logic;
-- DDR_rdDout => DDR_rdDout , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
Tx_TimeOut => Tx_TimeOut, -- OUT std_logic;
Tx_eb_TimeOut => Tx_eb_TimeOut, -- OUT std_logic;
Format_Shower => Format_Shower, -- OUT std_logic;
Tx_Reset => Tx_Reset, -- IN std_logic;
mbuf_UserFull => mbuf_UserFull, -- IN std_logic;
localID => localID -- IN std_logic_vector(15 downto 0)
);
-- ------------------------------------------------
-- Unified memory space
-- ------------------------------------------------
Memory_Space:
Regs_Group
PORT MAP(
-- DCB protocol interface
protocol_link_act => protocol_link_act , -- IN std_logic_vector(2-1 downto 0);
protocol_rst => protocol_rst , -- OUT std_logic;
-- Fabric side: CTL Rx
ctl_rv => ctl_rv , -- OUT std_logic;
ctl_rd => ctl_rd , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: CTL Tx
ctl_ttake => ctl_ttake , -- OUT std_logic;
ctl_tv => ctl_tv , -- IN std_logic;
ctl_td => ctl_td , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop => ctl_tstop , -- OUT std_logic;
ctl_reset => ctl_reset , -- OUT std_logic;
ctl_status => ctl_status , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_tv => dlm_tv , -- OUT std_logic;
dlm_td => dlm_td , -- OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_rv => dlm_rv , -- IN std_logic;
dlm_rd => dlm_rd , -- IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Event Buffer status + reset
eb_FIFO_Status => eb_FIFO_Status , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst => eb_FIFO_Rst , -- OUT std_logic;
H2B_FIFO_Status => H2B_FIFO_Status ,
B2H_FIFO_Status => B2H_FIFO_Status ,
-- Registers
Regs_WrEnA => Regs_WrEnA , -- IN std_logic;
Regs_WrMaskA => Regs_WrMaskA , -- IN std_logic_vector(2-1 downto 0);
Regs_WrAddrA => Regs_WrAddrA , -- IN std_logic_vector(16-1 downto 0);
Regs_WrDinA => Regs_WrDinA , -- IN std_logic_vector(32-1 downto 0);
Regs_WrEnB => Regs_WrEnB , -- IN std_logic;
Regs_WrMaskB => Regs_WrMaskB , -- IN std_logic_vector(2-1 downto 0);
Regs_WrAddrB => Regs_WrAddrB , -- IN std_logic_vector(16-1 downto 0);
Regs_WrDinB => Regs_WrDinB , -- IN std_logic_vector(32-1 downto 0);
Regs_RdAddr => Regs_RdAddr , -- IN std_logic_vector(15 downto 0);
Regs_RdQout => Regs_RdQout , -- OUT std_logic_vector(31 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add => ds_DMA_Bytes_Add , -- IN std_logic;
ds_DMA_Bytes => ds_DMA_Bytes , -- IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Register values
DMA_ds_PA => DMA_ds_PA_i , -- OUT std_logic_vector(63 downto 0);
DMA_ds_HA => DMA_ds_HA_i , -- OUT std_logic_vector(63 downto 0);
DMA_ds_BDA => DMA_ds_BDA_i , -- OUT std_logic_vector(63 downto 0);
DMA_ds_Length => DMA_ds_Length_i , -- OUT std_logic_vector(31 downto 0);
DMA_ds_Control => DMA_ds_Control_i , -- OUT std_logic_vector(31 downto 0);
dsDMA_BDA_eq_Null => dsDMA_BDA_eq_Null , -- OUT std_logic;
DMA_ds_Status => DMA_ds_Status , -- IN std_logic_vector(31 downto 0);
DMA_ds_Done => DMA_ds_Done_i , -- IN std_logic;
DMA_ds_Tout => DMA_ds_Tout , -- IN std_logic;
dsHA_is_64b => dsHA_is_64b , -- OUT std_logic;
dsBDA_is_64b => dsBDA_is_64b , -- OUT std_logic;
dsLeng_Hi19b_True => dsLeng_Hi19b_True , -- OUT std_logic;
dsLeng_Lo7b_True => dsLeng_Lo7b_True , -- OUT std_logic;
dsDMA_Start => dsDMA_Start_i , -- OUT std_logic;
dsDMA_Stop => dsDMA_Stop_i , -- OUT std_logic;
dsDMA_Start2 => dsDMA_Start2_i , -- OUT std_logic;
dsDMA_Stop2 => dsDMA_Stop2_i , -- OUT std_logic;
dsDMA_Channel_Rst => dsDMA_Channel_Rst_i , -- OUT std_logic;
dsDMA_Cmd_Ack => dsDMA_Cmd_Ack , -- IN std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add => us_DMA_Bytes_Add , -- IN std_logic;
us_DMA_Bytes => us_DMA_Bytes , -- IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
DMA_us_PA => DMA_us_PA_i , -- OUT std_logic_vector(63 downto 0);
DMA_us_HA => DMA_us_HA_i , -- OUT std_logic_vector(63 downto 0);
DMA_us_BDA => DMA_us_BDA_i , -- OUT std_logic_vector(63 downto 0);
DMA_us_Length => DMA_us_Length_i , -- OUT std_logic_vector(31 downto 0);
DMA_us_Control => DMA_us_Control_i , -- OUT std_logic_vector(31 downto 0);
usDMA_BDA_eq_Null => usDMA_BDA_eq_Null , -- OUT std_logic;
us_MWr_Param_Vec => us_MWr_Param_Vec , -- OUT std_logic_vector(6-1 downto 0);
DMA_us_Status => DMA_us_Status , -- IN std_logic_vector(31 downto 0);
DMA_us_Done => DMA_us_Done_i , -- IN std_logic;
DMA_us_Tout => DMA_us_Tout , -- IN std_logic;
usHA_is_64b => usHA_is_64b , -- OUT std_logic;
usBDA_is_64b => usBDA_is_64b , -- OUT std_logic;
usLeng_Hi19b_True => usLeng_Hi19b_True , -- OUT std_logic;
usLeng_Lo7b_True => usLeng_Lo7b_True , -- OUT std_logic;
usDMA_Start => usDMA_Start_i , -- OUT std_logic;
usDMA_Stop => usDMA_Stop_i , -- OUT std_logic;
usDMA_Start2 => usDMA_Start2_i , -- OUT std_logic;
usDMA_Stop2 => usDMA_Stop2_i , -- OUT std_logic;
usDMA_Channel_Rst => usDMA_Channel_Rst_i , -- OUT std_logic;
usDMA_Cmd_Ack => usDMA_Cmd_Ack , -- IN std_logic;
-- Reset signals
MRd_Channel_Rst => MRd_Channel_Rst , -- OUT std_logic;
Tx_Reset => Tx_Reset , -- OUT std_logic;
-- to Interrupt module
Sys_IRQ => Sys_IRQ , -- OUT std_logic_vector(31 downto 0);
DAQ_irq => DAQ_irq , -- IN std_logic;
CTL_irq => CTL_irq , -- IN std_logic;
DLM_irq => DLM_irq , -- IN std_logic;
DAQTOUT_irq => DAQTOUT_irq , -- IN std_logic;
CTLTOUT_irq => CTLTOUT_irq , -- IN std_logic;
DLMTOUT_irq => DLMTOUT_irq , -- IN std_logic;
Sys_Int_Enable => Sys_Int_Enable ,
-- System error and info
eb_FIFO_ow => eb_FIFO_ow ,
Tx_TimeOut => Tx_TimeOut ,
Tx_eb_TimeOut => Tx_eb_TimeOut ,
Msg_Routing => Msg_Routing ,
pcie_link_width => pcie_link_width ,
cfg_dcommand => cfg_dcommand ,
-- Interrupt Generation Signals
IG_Reset => IG_Reset ,
IG_Host_Clear => IG_Host_Clear ,
IG_Latency => IG_Latency ,
IG_Num_Assert => IG_Num_Assert ,
IG_Num_Deassert => IG_Num_Deassert ,
IG_Asserting => IG_Asserting ,
-- Data generator control
DG_is_Running => DG_is_Running ,
DG_Reset => DG_Reset ,
DG_Mask => DG_Mask ,
-- SIMONE Register: PC-->FPGA
reg01_tv => reg01_tv,
reg01_td => reg01_td,
reg02_tv => reg02_tv,
reg02_td => reg02_td,
reg03_tv => reg03_tv,
reg03_td => reg03_td,
reg04_tv => reg04_tv,
reg04_td => reg04_td,
reg05_tv => reg05_tv,
reg05_td => reg05_td,
reg06_tv => reg06_tv,
reg06_td => reg06_td,
reg07_tv => reg07_tv,
reg07_td => reg07_td,
reg08_tv => reg08_tv,
reg08_td => reg08_td,
reg09_tv => reg09_tv,
reg09_td => reg09_td,
reg10_tv => reg10_tv,
reg10_td => reg10_td,
reg11_tv => reg11_tv,
reg11_td => reg11_td,
reg12_tv => reg12_tv,
reg12_td => reg12_td,
reg13_tv => reg13_tv,
reg13_td => reg13_td,
reg14_tv => reg14_tv,
reg14_td => reg14_td,
reg15_tv => reg15_tv,
reg15_td => reg15_td,
reg16_tv => reg16_tv,
reg16_td => reg16_td,
reg17_tv => reg17_tv,
reg17_td => reg17_td,
reg18_tv => reg18_tv,
reg18_td => reg18_td,
reg19_tv => reg19_tv,
reg19_td => reg19_td,
reg20_tv => reg20_tv,
reg20_td => reg20_td,
reg21_tv => reg21_tv,
reg21_td => reg21_td,
reg22_tv => reg22_tv,
reg22_td => reg22_td,
reg23_tv => reg23_tv,
reg23_td => reg23_td,
reg24_tv => reg24_tv,
reg24_td => reg24_td,
reg25_tv => reg25_tv,
reg25_td => reg25_td,
-- SIMONE Register: FPGA-->PC
reg01_rv => reg01_rv,
reg01_rd => reg01_rd,
reg02_rv => reg02_rv,
reg02_rd => reg02_rd,
reg03_rv => reg03_rv,
reg03_rd => reg03_rd,
reg04_rv => reg04_rv,
reg04_rd => reg04_rd,
reg05_rv => reg05_rv,
reg05_rd => reg05_rd,
reg06_rv => reg06_rv,
reg06_rd => reg06_rd,
reg07_rv => reg07_rv,
reg07_rd => reg07_rd,
reg08_rv => reg08_rv,
reg08_rd => reg08_rd,
reg09_rv => reg09_rv,
reg09_rd => reg09_rd,
reg10_rv => reg10_rv,
reg10_rd => reg10_rd,
reg11_rv => reg11_rv,
reg11_rd => reg11_rd,
reg12_rv => reg12_rv,
reg12_rd => reg12_rd,
reg13_rv => reg13_rv,
reg13_rd => reg13_rd,
reg14_rv => reg14_rv,
reg14_rd => reg14_rd,
reg15_rv => reg15_rv,
reg15_rd => reg15_rd,
reg16_rv => reg16_rv,
reg16_rd => reg16_rd,
reg17_rv => reg17_rv,
reg17_rd => reg17_rd,
reg18_rv => reg18_rv,
reg18_rd => reg18_rd,
reg19_rv => reg19_rv,
reg19_rd => reg19_rd,
reg20_rv => reg20_rv,
reg20_rd => reg20_rd,
reg21_rv => reg21_rv,
reg21_rd => reg21_rd,
reg22_rv => reg22_rv,
reg22_rd => reg22_rd,
reg23_rv => reg23_rv,
reg23_rd => reg23_rd,
reg24_rv => reg24_rv,
reg24_rd => reg24_rd,
reg25_rv => reg25_rv,
reg25_rd => reg25_rd,
-- SIMONE debug signals
debug_in_1i => debug_in_1i,
debug_in_2i => debug_in_2i,
debug_in_3i => debug_in_3i,
debug_in_4i => debug_in_4i,
-- Common
trn_clk => trn_clk , -- IN std_logic;
trn_lnk_up_n => trn_lnk_up_n , -- IN std_logic,
trn_reset_n => trn_reset_n -- IN std_logic;
);
end architecture Behavioral;
| gpl-2.0 | 6c665b7ffa4870c53c2c6175ba4d1188 | 0.476729 | 3.248408 | false | false | false | false |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.