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MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/register/status_register.vhd | 1 | 949 | library IEEE;
use IEEE.std_logic_1164.all;
ENTITY STATUS_REGISTER IS
PORT (
carryIn, overflowIn : IN std_logic;
data : IN std_logic_vector (15 DOWNTO 0);
carry, zero, sign, parity, borrow, overflow : OUT std_logic
);
END STATUS_REGISTER;
ARCHITECTURE STATUS_REGISTER_ARCH OF STATUS_REGISTER IS BEGIN
sign <= data(15);
carry <= carryIn;
zero <= not (data(0) or data(1) or data(2) or data(3) or data(4) or data(5) or
data(6) or data(7) or data(8) or data(9) or data(10) or
data(11) or data(12) or data(13) or data(14) or data(15));
borrow <= data(15);
parity <= data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor
data(6) xor data(7) xor data(8) xor data(9) xor data(10) xor
data(11) xor data(12) xor data(13) xor data(14) xor data(15);
overflow <= overflowIn;
END STATUS_REGISTER_ARCH;
| gpl-3.0 | 6eda48b9631071402d455bdcec753830 | 0.592202 | 3.227891 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/mips.vhd | 1 | 6,011 | library IEEE;
use IEEE.std_logic_1164.all;
entity SEMI_MIPS is
port (
clk : in std_logic;
external_reset : in std_logic;
we : out std_logic;
re : out std_logic;
address : out std_logic_vector(7 downto 0);
memory_in : in std_logic_vector(15 downto 0);
memory_out : out std_logic_vector(15 downto 0)
);
end entity;
architecture DATA_PATH of SEMI_MIPS is
component ALU is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OPERATION : in std_logic_vector(3 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
ZERO_OUT : out std_logic
);
end component;
component STATUS_REGISTER is
PORT (
carryIn, overflowIn : IN std_logic;
data : IN std_logic_vector (15 DOWNTO 0);
carry, zero, sign, parity, borrow, overflow : OUT std_logic
);
end component;
component registerFile is
port (
CLK : in std_logic;
W_EN : in std_logic;
INPUT : in std_logic_vector(15 downto 0);
IN_ADR : in std_logic_vector(3 downto 0);
OUT1_ADR: in std_logic_vector(3 downto 0);
OUT2_ADR: in std_logic_vector(3 downto 0);
OUTPUT1 : out std_logic_vector(15 downto 0);
OUTPUT2 : out std_logic_vector(15 downto 0);
REG0_OUT: out std_logic_vector(15 downto 0)
);
end component;
component ADDRESS_UNIT is
PORT (
Iside : IN std_logic_vector (7 DOWNTO 0);
Address : OUT std_logic_vector (7 DOWNTO 0);
clk, ResetPC, Im, PCplus1 : IN std_logic;
EnablePC : IN std_logic
);
end component;
component reg16b is
port(clk, load, reset : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (15 downto 0);
output : out STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000"
);
end component;
component CU is
port (
clk, ExternalReset,
carry, zero, sign, parity, borrow, overflow -- status register
: in STD_LOGIC;
IRout : in STD_LOGIC_VECTOR(15 downto 0); -- IR
reg0 : in STD_LOGIC_VECTOR(15 downto 0); -- Register(0)
ALUout_on_Databus, -- Data Bus
IRload, -- IR
ResetPC, Im, PCplus1, EnablePC, -- Address Unit
W_EN, -- register file
we, re, -- memory
itype
: out STD_LOGIC;
-- ALU's bits
alu_operation : out std_logic_vector(3 downto 0);
databus : inout std_logic_vector(15 downto 0)
);
end component;
signal DATABUS : std_logic_vector(15 downto 0);
signal S1 , S2 , reg2 , d : std_logic_vector(2 downto 0);
signal REG_IN_ADR, REG_OUT1_ADR, REG_OUT2_ADR : std_logic_vector(3 downto 0);
signal ALU_OP : std_logic_vector(3 downto 0);
signal ALUoutput, ALU_INPUT2 : std_logic_vector(15 downto 0);
signal ALU_Zero : std_logic;
signal ALUout_on_Databus : std_logic;
signal ResetPC : std_logic;
signal carryIn, overflowIn, carry, zero, sign, parity, borrow, overflow : std_logic;
signal REG0_OUT ,REG_FILE_SRC1 , REG_FILE_SRC2 , IRout : std_logic_vector (15 downto 0);
signal W_EN : std_logic;
signal itype : std_logic;
signal IRLoad, IRReset : std_logic;
signal Im : std_logic;
signal PCplus1, EnablePC : std_logic;
constant STORE_INSTRUCTION_CODE : std_logic_vector(3 downto 0) := "1101";
begin
DATABUS <= memory_in;
memory_out <= DATABUS;
IR : component reg16b
port map(
clk => clk,
load => IRLoad,
reset => IRReset,
input => DATABUS,
output => IRout
);
ADDRESS_UNIT_inst : component ADDRESS_UNIT
port map(
Iside => IRout(7 downto 0),
Address => Address,
clk => clk,
ResetPC => external_reset,
Im => Im,
PCplus1 => PCplus1,
EnablePC => EnablePC
);
ALU_inst : component ALU
port map(
CARRY_IN => carry,
INPUT1 => REG_FILE_SRC1,
INPUT2 => ALU_INPUT2,
OPERATION => ALU_OP,
OUTPUT => ALUoutput,
CARRY_OUT => carryIn,
ZERO_OUT => ALU_Zero
);
STATUS_REGISTER_inst : component STATUS_REGISTER
port map(
carryIn => carryIn,
overflowIn => overflowIn,
data => ALUoutput,
carry => carry,
zero => zero,
sign => sign,
parity => parity,
borrow => borrow,
overflow => overflow
);
REGFILE_INPUT_ADDRESS : with IRout(15 downto 12) select
REG_IN_ADR <=
IRout(11 downto 8) when STORE_INSTRUCTION_CODE,
IRout(7 downto 4) when others;
registerFile_inst : component registerFile
port map(
CLK => CLK,
W_EN => W_EN,
INPUT => DATABUS,
IN_ADR => REG_IN_ADR,
OUT1_ADR => REG_OUT1_ADR,
OUT2_ADR => REG_OUT2_ADR,
OUTPUT1 => REG_FILE_SRC1,
OUTPUT2 => REG_FILE_SRC2,
REG0_OUT => REG0_OUT
);
CU_inst : component CU
port map(
clk => clk,
ExternalReset => external_reset,
carry => carry,
zero => zero,
sign => sign,
parity => parity,
borrow => borrow,
overflow => overflow,
IRout => IRout,
reg0 => REG0_OUT,
ALUout_on_Databus => ALUout_on_Databus,
IRload => IRload,
ResetPC => ResetPC,
Im => Im,
PCplus1 => PCplus1,
EnablePC => EnablePC,
W_EN => W_EN,
we => we,
re => re,
itype => itype,
alu_operation => ALU_OP,
databus => DATABUS
);
ALU_INPUT2_MUX : with itype select
ALU_INPUT2 <=
REG_FILE_SRC2 when '0',
"00000000" & Im when '1',
REG_FILE_SRC2 when others;
ALU_OUT_MUX : with ALUout_on_Databus select
DATABUS <=
ALUoutput when '1',
"ZZZZZZZZZZZZZZZZ" when others;
end architecture; | gpl-3.0 | f288131b07cc2949fbad50f7f61005ed | 0.563301 | 3.112895 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_family_support.vhd | 1 | 404,634 | --------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
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-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
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-- ** code, or information as one possible implementation of **
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-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
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-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.cpu_xadc_wiz_0_0_family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.cpu_xadc_wiz_0_0_family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package cpu_xadc_wiz_0_0_family_support is
type families_type is
(
nofamily
, virtex
, spartan2
, spartan2e
, virtexe
, virtex2
, qvirtex2 -- Taken to be identical to the virtex2 primitive set.
, qrvirtex2 -- Taken to be identical to the virtex2 primitive set.
, virtex2p
, spartan3
, aspartan3
, virtex4
, virtex4lx
, virtex4fx
, virtex4sx
, spartan3e
, virtex5
, spartan3a
, spartan3an
, spartan3adsp
, aspartan3e
, aspartan3a
, aspartan3adsp
, qvirtex4
, qrvirtex4
, spartan6
, virtex6
, spartan6l
, qspartan6
, aspartan6
, virtex6l
, qspartan6l
, qvirtex5
, qvirtex6
, qrvirtex5
, virtex5tx
, virtex5fx
, virtex6cx
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix7
, aartix7
, artix7l
, qartix7
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 798;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package cpu_xadc_wiz_0_0_family_support;
package body cpu_xadc_wiz_0_0_family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2 => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2e => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexe => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2p => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4lx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4fx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4sx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3an => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5tx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
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virtex5fx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6cx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintex7l => (
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qkintex7 => (
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qvirtex7l => (
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artix7 => (
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aartix7 => (
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artix7l => (
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n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex => return "virtex" ;
when spartan2 => return "spartan2" ;
when spartan2e => return "spartan2e" ;
when virtexe => return "virtexe" ;
when virtex2 => return "virtex2" ;
when qvirtex2 => return "qvirtex2" ;
when qrvirtex2 => return "qrvirtex2" ;
when virtex2p => return "virtex2p" ;
when spartan3 => return "spartan3" ;
when aspartan3 => return "aspartan3" ;
when spartan3e => return "spartan3e" ;
when virtex4 => return "virtex4" ;
when virtex4lx => return "virtex4lx" ;
when virtex4fx => return "virtex4fx" ;
when virtex4sx => return "virtex4sx" ;
when virtex5 => return "virtex5" ;
when spartan3a => return "spartan3a" ;
when spartan3an => return "spartan3an" ;
when spartan3adsp => return "spartan3adsp" ;
when aspartan3e => return "aspartan3e" ;
when aspartan3a => return "aspartan3a" ;
when aspartan3adsp => return "aspartan3adsp";
when qvirtex4 => return "qvirtex4" ;
when qrvirtex4 => return "qrvirtex4" ;
when spartan6 => return "spartan6" ;
when virtex6 => return "virtex6" ;
when spartan6l => return "spartan6l" ;
when qspartan6 => return "qspartan6" ;
when aspartan6 => return "aspartan6" ;
when virtex6l => return "virtex6l" ;
when qspartan6l => return "qspartan6l" ;
when qvirtex5 => return "qvirtex5" ;
when qvirtex6 => return "qvirtex6" ;
when qrvirtex5 => return "qrvirtex5" ;
when virtex5tx => return "virtex5tx" ;
when virtex5fx => return "virtex5fx" ;
when virtex6cx => return "virtex6cx" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- spartan3 Root family
if (equalIgnoringCase(family_in, "spartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3an" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3e" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3e" )) Then return "spartan3" ;
-- virtex4 Root family
Elsif (equalIgnoringCase(family_in, "virtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4lx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4fx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4sx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qvirtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex4" )) Then return "virtex4" ;
-- virtex5 Root family
Elsif (equalIgnoringCase(family_in, "virtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5tx" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5fx" )) Then return "virtex5" ;
-- virtex6 Root family
Elsif (equalIgnoringCase(family_in, "virtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6l" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "qvirtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6cx" )) Then return "virtex6" ;
-- spartan6 Root family
Elsif (equalIgnoringCase(family_in, "spartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "spartan6l" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "aspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6l" )) Then return "spartan6" ;
-- Virtex7 Root family
Elsif (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package cpu_xadc_wiz_0_0_family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body cpu_xadc_wiz_0_0_family_support;
| gpl-3.0 | 1d6a8cb854e4497c583f6012effa5daa | 0.32268 | 2.59312 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_rng.vhd | 1 | 3,905 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY wr_fifo32to256_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF wr_fifo32to256_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 30804bbacced71b8d36d50e447407210 | 0.638924 | 4.329268 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_dverif.vhd | 1 | 5,531 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.wr_fifo32to256_pkg.ALL;
ENTITY wr_fifo32to256_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF wr_fifo32to256_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:wr_fifo32to256_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 8e15a8c587d2e8f654c55549c6477782 | 0.577111 | 4.078909 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/DMA_FSM.vhd | 1 | 32,619 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_FSM is
port (
-- Fixed word for 1st header of TLP: MRd/MWr
TLP_Has_Payload : IN std_logic;
TLP_Hdr_is_4DW : IN std_logic;
DMA_Addr_Inc : IN std_logic;
DMA_BAR_Number : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- FSM control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic;
DMA_Stop : IN std_logic;
DMA_Stop2 : IN std_logic;
No_More_Bodies : IN std_logic;
ThereIs_Snout : IN std_logic;
ThereIs_Body : IN std_logic;
ThereIs_Tail : IN std_logic;
ThereIs_Dex : IN std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : IN std_logic;
DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : IN std_logic;
Done_Condition_2 : IN std_logic;
Done_Condition_3 : IN std_logic;
Done_Condition_4 : IN std_logic;
Done_Condition_5 : IN std_logic;
-- Channel buffer write
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
ChBuf_aFull : IN std_logic;
ChBuf_WrEn : OUT std_logic;
ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : OUT std_logic;
State_Is_Snout : OUT std_logic;
State_Is_Body : OUT std_logic;
State_Is_Tail : OUT std_logic;
DMA_Cmd_Ack : OUT std_logic;
-- To Tx Port
ChBuf_ValidRd : IN std_logic;
BDA_nAligned : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
DMA_Done : OUT std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
end entity DMA_FSM;
architecture Behavioral of DMA_FSM is
-- DMA operation control FSM
type DMAStates is (
-- dmaST_Init: Initial state at reset.
dmaST_Init
-- dmaST_Load_Param: Load DMA parameters (PA, HA, BDA and Leng).
, dmaST_Load_Param
-- dmaST_Snout: 1st TLP might be non-integeral of MAX_SIZE.
, dmaST_Snout
-- dmaST_Stomp: after every ChBuf write, pause a clock before taking
-- next write. This state checks the availability of
-- the ChBuf (channel buffer) for write.
, dmaST_Stomp
-- dmaST_Body: TLP's in the middle, always integeral of MAX_SIZE.
, dmaST_Body
-- dmaST_Tail: the last TLP, similar with the 1st one, whose size
-- should be specially calculated.
, dmaST_Tail
-- -- dmaST_Before_Dex: before writing the MRd TLP (for next descriptor)
-- -- information for the next descriptor (if any),
-- -- a pause is needed to wait for the ChBuf available.
-- , dmaST_Before_Dex
-- dmaST_NextDex: writing the descriptor MRd TLP information to
-- the ChBuf.
, dmaST_NextDex
-- dmaST_Await_Dex: after MRd(descriptor) info is written in the ChBuf,
-- the state machine waits for the descriptor's
-- arrival.
, dmaST_Await_Dex
);
signal DMA_NextState : DMAStates;
signal DMA_State : DMAStates;
-- Busy/Done state bits generation
type FSM_BusyDone is (
FSM_Idle
, FSM_Busy1
, FSM_Busy2
, FSM_Busy3
, FSM_Busy4
, FSM_Busy5
, FSM_Done
);
signal BusyDone_NextState : FSM_BusyDone;
signal BusyDone_State : FSM_BusyDone;
-- Time-out state
type FSM_Time_Out is (
toutSt_Idle
, toutSt_CountUp
, toutSt_Pause
);
signal DMA_TimeOut_State : FSM_Time_Out;
-- DMA Start command from MWr channel
signal DMA_Start_r1 : std_logic;
-- DMA Start command from CplD channel
signal DMA_Start2_r1 : std_logic;
-- Registered Dex indicator
signal ThereIs_Dex_reg : std_logic;
signal ThereIs_Snout_reg : std_logic;
signal ThereIs_Body_reg : std_logic;
signal ThereIs_Tail_reg : std_logic;
-- DMA Stutus monitor
signal BDA_nAligned_i : std_logic;
signal DMA_Busy_i : std_logic;
signal DMA_Done_i : std_logic;
-- FSM state indicators
signal State_Is_LoadParam_i : std_logic;
signal State_Is_Snout_i : std_logic;
signal State_Is_Body_i : std_logic;
signal State_Is_Tail_i : std_logic;
signal State_Is_AwaitDex_i : std_logic;
-- Acknowledge for DMA_Start command
signal DMA_Cmd_Ack_i : std_logic;
-- channel FIFO Write control
signal ChBuf_WrDin_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal ChBuf_WrEn_i : std_logic;
signal ChBuf_aFull_i : std_logic;
-- ---------------------------------------------------------------------------------
-- Time-out calculation : invisible to the user, so moved out of the abbPackage
-- ---------------------------------------------------------------------------------
signal cnt_DMA_TO : std_logic_vector(C_TOUT_WIDTH-1 downto 0);
signal Tout_Lo_Carry : std_logic;
signal DMA_TimeOut_i : std_logic;
-- Carry bit, only for better timing
Constant CBIT_TOUT_CARRY : integer := C_TOUT_WIDTH/2;
begin
-- As DMA Statuses
BDA_nAligned <= BDA_nAligned_i ;
DMA_Busy <= DMA_Busy_i ;
DMA_Done <= DMA_Done_i ;
-- DMA_Done_Rise <= DMA_Done_Rise_i;
DMA_TimeOut <= DMA_TimeOut_i ;
-- Abstract buffer write control
ChBuf_WrEn <= ChBuf_WrEn_i;
ChBuf_WrDin <= ChBuf_WrDin_i;
ChBuf_aFull_i <= ChBuf_aFull;
-- FSM State indicators
State_Is_LoadParam <= State_Is_LoadParam_i;
State_Is_Snout <= State_Is_Snout_i;
State_Is_Body <= State_Is_Body_i;
State_Is_Tail <= State_Is_Tail_i;
DMA_Cmd_Ack <= DMA_Cmd_Ack_i;
-- -----------------------------------------
-- Syn_Delay: DMA_Start
-- DMA_Start2
--
Syn_Delay_DMA_Starts:
process ( dma_clk)
begin
if dma_clk'event and dma_clk = '1' then
DMA_Start_r1 <= DMA_Start;
DMA_Start2_r1 <= DMA_Start2;
end if;
end process;
---- -----------------------------------------
---- -----------------------------------------
----
-- States synchronous: DMA
----
Syn_DMA_States:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_State <= dmaST_Init;
elsif dma_clk'event and dma_clk = '1' then
DMA_State <= DMA_NextState;
end if;
end process;
-- Next States: DMA
Comb_DMA_NextState:
process (
DMA_State
, DMA_Start_r1
, DMA_Start2_r1
, ChBuf_aFull_i
, No_More_Bodies
, ThereIs_Snout --_reg
-- , ThereIs_Body
, ThereIs_Tail_reg
, ThereIs_Dex_reg
)
begin
case DMA_State is
when dmaST_Init =>
if DMA_Start_r1 = '1' then
DMA_NextState <= dmaST_Load_Param;
else
DMA_NextState <= dmaST_Init;
end if;
when dmaST_Load_Param =>
if ChBuf_aFull_i = '1' then
DMA_NextState <= dmaST_Load_Param;
elsif ThereIs_Dex_reg = '1' then
DMA_NextState <= dmaST_NextDex;
elsif ThereIs_Snout = '1' then
DMA_NextState <= dmaST_Snout;
-- elsif ThereIs_Body = '1' then
-- DMA_NextState <= dmaST_Stomp;
else
DMA_NextState <= dmaST_Stomp;
end if;
when dmaST_NextDex =>
if ThereIs_Snout = '1' then
DMA_NextState <= dmaST_Snout;
elsif No_More_Bodies = '0' then
DMA_NextState <= dmaST_Body;
else
DMA_NextState <= dmaST_Await_Dex;
end if;
when dmaST_Snout =>
DMA_NextState <= dmaST_Stomp;
when dmaST_Stomp =>
if ChBuf_aFull_i = '1' then
DMA_NextState <= dmaST_Stomp;
elsif No_More_Bodies= '0' then
DMA_NextState <= dmaST_Body;
elsif ThereIs_Tail_reg= '1' then
DMA_NextState <= dmaST_Tail;
elsif ThereIs_Dex_reg= '1' then
DMA_NextState <= dmaST_Await_Dex;
else
DMA_NextState <= dmaST_Init;
end if;
when dmaST_Body =>
DMA_NextState <= dmaST_Stomp;
when dmaST_Tail =>
if ThereIs_Dex_reg = '1' then
DMA_NextState <= dmaST_Await_Dex;
else
DMA_NextState <= dmaST_Init;
end if;
when dmaST_Await_Dex =>
if DMA_Start2_r1 = '1' then
DMA_NextState <= dmaST_Load_Param;
else
DMA_NextState <= dmaST_Await_Dex;
end if;
when Others =>
DMA_NextState <= dmaST_Init;
end case; -- DMA_State
end process;
-- ----------------------------------------------------
-- States synchronous: DMA_Cmd_Ack
-- equivalent to State_Is_LoadParam
--
Syn_DMA_Cmd_Ack:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Cmd_Ack_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_NextState = dmaST_Load_Param then
DMA_Cmd_Ack_i <= '1';
else
DMA_Cmd_Ack_i <= '0';
end if;
end if;
end process;
-- ----------------------------------------------------
-- States synchronous: ThereIs_Dex_reg
--
Syn_ThereIs_Dex_reg:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Dex_reg <= '0';
ThereIs_Snout_reg <= '0';
ThereIs_Body_reg <= '0';
ThereIs_Tail_reg <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1'
or State_Is_LoadParam_i = '1'
or State_Is_AwaitDex_i ='1'
then
ThereIs_Dex_reg <= ThereIs_Dex;
ThereIs_Snout_reg <= ThereIs_Snout;
ThereIs_Body_reg <= ThereIs_Body;
ThereIs_Tail_reg <= ThereIs_Tail;
else
ThereIs_Dex_reg <= ThereIs_Dex_reg;
ThereIs_Snout_reg <= ThereIs_Snout_reg;
ThereIs_Body_reg <= ThereIs_Body_reg;
ThereIs_Tail_reg <= ThereIs_Tail_reg;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- State_Is_LoadParam
-- State_Is_Snout
-- State_Is_Body
-- State_Is_Tail
-- State_Is_AwaitDex
--
FSM_State_Is_i:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
State_Is_LoadParam_i <= '0';
State_Is_Snout_i <= '0';
State_Is_Body_i <= '0';
State_Is_Tail_i <= '0';
State_Is_AwaitDex_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_NextState= dmaST_Load_Param then
State_Is_LoadParam_i <= '1';
else
State_Is_LoadParam_i <= '0';
end if;
if DMA_NextState= dmaST_Snout then
State_Is_Snout_i <= '1';
else
State_Is_Snout_i <= '0';
end if;
if DMA_NextState= dmaST_Body then
State_Is_Body_i <= '1';
else
State_Is_Body_i <= '0';
end if;
if DMA_NextState= dmaST_Tail then
State_Is_Tail_i <= '1';
else
State_Is_Tail_i <= '0';
end if;
if DMA_NextState= dmaST_Await_Dex then
State_Is_AwaitDex_i <= '1';
else
State_Is_AwaitDex_i <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Synchronous Output: DMA_Abstract_Buffer_Write
--
-- DMA Channel (downstream and upstream) Buffers (128-bit) definition:
-- Note: Type not shows in this buffer
--
-- 127 ~ xxx : Peripheral address
-- xxy ~ 96 : reserved
-- 95 : Address increments
-- 94 : Valid
-- 93 ~ 30 : Host Address
-- 29 ~ 27 : BAR number
-- 26 ~ 19 : Tag
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
FSM_DMA_Abstract_Buffer_Write:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ChBuf_WrEn_i <= '0';
ChBuf_WrDin_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
case DMA_State is
when dmaST_NextDex =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_BDA_fsm;
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- any value
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Dex_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= C_TLP_HAS_NO_DATA; --C_MRD_HEAD0_WORD(C_TLP_FMT_BIT_TOP);
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= BDA_is_64b_fsm;
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_NEXT_BD_LENGTH(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; -- any value
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= C_RELAXED_ORDERING & C_NO_SNOOP;
when dmaST_Snout =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Loaded(C_EP_AWIDTH-1 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Loaded(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Loaded(C_DDR_IAWIDTH-1 downto 0);
else
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
end if;
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
when dmaST_Body =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0);
else
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
end if;
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
when dmaST_Tail =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0);
else
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
end if;
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
when OTHERS =>
ChBuf_WrEn_i <= '0';
ChBuf_WrDin_i <= ChBuf_WrDin_i;
end case;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Latch: BDA_nAligned_i
-- : Capture design defect
--
Latch_BDA_nAligned:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
BDA_nAligned_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
-- If the lowest 2 bits are not zero, error bit set accordingly,
-- because the logic can not deal with this situation.
-- can be removed.
if DMA_BDA_fsm(1) ='1' or DMA_BDA_fsm(0) ='1' then
BDA_nAligned_i <= '1';
else
BDA_nAligned_i <= BDA_nAligned_i;
end if;
end if;
end process;
-- States synchronous: BusyDone_States
Syn_BusyDone_States:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
BusyDone_State <= FSM_Idle;
elsif dma_clk'event and dma_clk = '1' then
BusyDone_State <= BusyDone_NextState;
end if;
end process;
-- Next States: BusyDone_State
Comb_BusyDone_State:
process (
BusyDone_State
, DMA_State
-- , Done_Condition_1
, Done_Condition_2
, Done_Condition_3
, Done_Condition_4
, Done_Condition_5
)
begin
case BusyDone_State is
when FSM_Idle =>
if DMA_State = dmaST_Load_Param then
BusyDone_NextState <= FSM_Busy1;
else
BusyDone_NextState <= FSM_Idle;
end if;
when FSM_Busy1 =>
if DMA_State = dmaST_Init --- Done_Condition_1='1'
then
BusyDone_NextState <= FSM_Busy2;
else
BusyDone_NextState <= FSM_Busy1;
end if;
when FSM_Busy2 =>
if Done_Condition_2='1'
then
BusyDone_NextState <= FSM_Busy3;
else
BusyDone_NextState <= FSM_Busy2;
end if;
when FSM_Busy3 =>
if Done_Condition_3='1'
then
BusyDone_NextState <= FSM_Busy4;
else
BusyDone_NextState <= FSM_Busy3;
end if;
when FSM_Busy4 =>
if Done_Condition_4='1'
then
BusyDone_NextState <= FSM_Busy5;
else
BusyDone_NextState <= FSM_Busy4;
end if;
when FSM_Busy5 =>
if Done_Condition_5='1'
then
BusyDone_NextState <= FSM_Done;
else
BusyDone_NextState <= FSM_Busy5;
end if;
when FSM_Done =>
if DMA_State = dmaST_Init then
BusyDone_NextState <= FSM_Idle;
else
BusyDone_NextState <= FSM_Done;
end if;
when Others =>
BusyDone_NextState <= FSM_Idle;
end case; -- BusyDone_State
end process;
-- Synchronous Output: DMA_Busy_i
FSM_Output_DMA_Busy:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Busy_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
case BusyDone_State is
when FSM_Idle =>
DMA_Busy_i <= '0';
when FSM_Busy1 =>
DMA_Busy_i <= '1';
when FSM_Busy2 =>
DMA_Busy_i <= '1';
when FSM_Busy3 =>
DMA_Busy_i <= '1';
when FSM_Busy4 =>
DMA_Busy_i <= '1';
when FSM_Busy5 =>
DMA_Busy_i <= '1';
when FSM_Done =>
DMA_Busy_i <= '0';
when Others =>
DMA_Busy_i <= '0';
end case; -- BusyDone_State
end if;
end process;
-- Synchronous Output: DMA_Done_i
FSM_Output_DMA_Done:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Done_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
case BusyDone_State is
-- when FSM_Busy1 =>
-- DMA_Done_i <= '0';
--
-- when FSM_Busy2 =>
-- DMA_Done_i <= '0';
--
-- when FSM_Busy3 =>
-- DMA_Done_i <= '0';
--
when FSM_Done =>
DMA_Done_i <= '1';
when Others =>
DMA_Done_i <= DMA_Done_i;
end case; -- BusyDone_State
end if;
end process;
-- ----------------------------------------------
-- Time out counter
-- Synchronous Output: Counter_DMA_TimeOut_i
FSM_Counter_DMA_TimeOut_i:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
DMA_TimeOut_State <= toutSt_Idle;
elsif dma_clk'event and dma_clk = '1' then
case DMA_TimeOut_State is
when toutSt_Idle =>
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
if DMA_Start='1' then
DMA_TimeOut_State <= toutSt_CountUp;
else
DMA_TimeOut_State <= toutSt_Idle;
end if;
when toutSt_CountUp =>
if DMA_Done_i='1' or DMA_Start='1' then
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
DMA_TimeOut_State <= toutSt_Idle;
elsif DMA_Stop='1' then
cnt_DMA_TO <= cnt_DMA_TO;
Tout_Lo_Carry <= Tout_Lo_Carry;
DMA_TimeOut_State <= toutSt_Pause;
elsif ChBuf_ValidRd='1' then
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
DMA_TimeOut_State <= toutSt_CountUp;
else
cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) + '1';
if cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_TOUT_CARRY-1 downto 0) then
Tout_Lo_Carry <= '1';
else
Tout_Lo_Carry <= '0';
end if;
if Tout_Lo_Carry='1' then
cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) + '1';
else
cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY);
end if;
DMA_TimeOut_State <= toutSt_CountUp;
end if;
when toutSt_Pause =>
cnt_DMA_TO <= cnt_DMA_TO;
Tout_Lo_Carry <= Tout_Lo_Carry;
if DMA_Start='1' then
DMA_TimeOut_State <= toutSt_CountUp;
elsif DMA_Done_i='1' then
DMA_TimeOut_State <= toutSt_Idle;
else
DMA_TimeOut_State <= toutSt_Pause;
end if;
when Others =>
cnt_DMA_TO <= cnt_DMA_TO;
Tout_Lo_Carry <= Tout_Lo_Carry;
DMA_TimeOut_State <= toutSt_Idle;
end case;
-- case DMA_State is
--
-- when dmaST_Init =>
-- cnt_DMA_TO <= (Others=>'0');
-- Tout_Lo_Carry <= '0';
--
-- when dmaST_Snout =>
-- cnt_DMA_TO <= (Others=>'0');
-- Tout_Lo_Carry <= '0';
--
--
-- when Others =>
-- cnt_DMA_TO(CBIT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_CARRY-1 downto 0) + '1';
--
-- if cnt_DMA_TO(CBIT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_CARRY-1 downto 0) then
-- Tout_Lo_Carry <= '1';
-- else
-- Tout_Lo_Carry <= '0';
-- end if;
--
-- if Tout_Lo_Carry='1' then
-- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) + '1';
-- else
-- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY);
-- end if;
--
-- end case;
end if;
end process;
-- ----------------------------------------------
-- Time out state bit
-- Synchronous Output: DMA_TimeOut_i
FSM_DMA_TimeOut:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_TimeOut_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
-- Capture the time-out trigger
-- if cnt_DMA_TO(CBIT_TOUT_BOT downto 0) = C_TIME_OUT_VALUE then
if cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT) = C_TIME_OUT_VALUE then
DMA_TimeOut_i <= '1';
else
DMA_TimeOut_i <= DMA_TimeOut_i;
end if;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | a12f21b78a55c58d54d38937f047a3aa | 0.485453 | 3.623931 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/simulation/k7_eb_fifo_counted_resized_rng.vhd | 1 | 3,941 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY k7_eb_fifo_counted_resized_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF k7_eb_fifo_counted_resized_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 43cf16ee6c292906836ace3e89e14163 | 0.639939 | 4.311816 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/axi_epc.vhd | 1 | 48,147 | -------------------------------------------------------------------------------
-- axi_epc.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- File : axi_epc.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI bus
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on axi_epc_v2_0
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_lite_ipif_v3_0.ipif_pkg.SLV64_ARRAY_TYPE;
use axi_lite_ipif_v3_0.ipif_pkg.calc_num_ce;
library axi_epc_v2_0;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BASEADDR -- User logic base address
-- C_HIGHADDR -- User logic high address
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Default family
-- C_INSTANCE -- Instance name of the axi_apb_bridge in the
-- -- system
------------------------------------------------------
-- C_S_AXI_CLK_PERIOD_PS - The clock period of AXI Clock in picoseconds
-- C_PRH_CLK_PERIOD_PS - The clock period of peripheral clock in
-- picoseconds
------------------------------------------------------
-- C_NUM_PERIPHERALS - Number of external devices connected to AXI EPC
-- C_PRH_MAX_AWIDTH - Maximum of address bus width of all peripherals
-- C_PRH_MAX_DWIDTH - Maximum of data bus width of all peripherals
-- C_PRH_MAX_ADWIDTH - Maximum of data bus width of all peripherals
-- and address bus width of peripherals employing
-- multiplexed address/data bus
-- C_PRH_CLK_SUPPORT - Indication of whether the synchronous interface
-- operates on peripheral clock or on AXI clock
-- C_PRH_BURST_SUPPORT - Indicates if the AXI EPC supports burst
-- C_PRH(0:3)_BASEADDR - External peripheral (0:3) base address
-- C_PRH(0:3)_HIGHADDR - External peripheral (0:3) high address
-- C_PRH(0:3)_FIFO_ACCESS - Indicates if the support for accessing FIFO
-- like structure within external device is
-- required
-- C_PRH(0:3)_FIFO_OFFSET - Byte offset of FIFO from the base address
-- assigned to peripheral
-- C_PRH(0:3)_AWIDTH - External peripheral (0:3) address bus width
-- C_PRH(0:3)_DWIDTH - External peripheral (0:3) data bus width
-- C_PRH(0:3)_DWIDTH_MATCH - Indication of whether external peripheral (0:3)
-- supports multiple access cycle on the
-- peripheral interface for a single AXI cycle
-- when the peripheral data bus width is less than
-- that of AXI bus data width
-- C_PRH(0:3)_SYNC - Indicates if the external device (0:3) uses
-- synchronous or asynchronous interface
-- C_PRH(0:3)_BUS_MULTIPLEX - Indicates if the external device (0:3) uses a
-- multiplexed or non-multiplexed device
-- C_PRH(0:3)_ADDR_TSU - External device (0:3) address setup time with
-- respect to rising edge of address strobe
-- (multiplexed address and data bus) or falling
-- edge of read/write signal (non-multiplexed
-- address/data bus)
-- C_PRH(0:3)_ADDR_TH - External device (0:3) address hold time with
-- respect to rising edge of address strobe
-- (multiplexed address and data bus) or rising
-- edge of read/write signal (non-multiplexed
-- address/data bus)
-- C_PRH(0:3)_ADS_WIDTH - Minimum pulse width of address strobe
-- C_PRH(0:3)_CSN_TSU - External device (0:3) chip select setup time
-- with respect to falling edge of read/write
-- signal
-- C_PRH(0:3)_CSN_TH - External device (0:3) chip select hold time with
-- respect to rising edge of read/write signal
-- C_PRH(0:3)_WRN_WIDTH - External device (0:3) write signal minimum
-- pulse width
-- C_PRH(0:3)_WR_CYCLE - External device (0:3) write cycle time
-- C_PRH(0:3)_DATA_TSU - External device (0:3) data bus setup with
-- respect to rising edge of write signal
-- C_PRH(0:3)_DATA_TH - External device (0:3) data bus hold with
-- respect to rising edge of write signal
-- C_PRH(0:3)_RDN_WIDTH - External device (0:3) read signal minimum
-- pulse width
-- C_PRH(0:3)_RD_CYCLE - External device (0:3) read cycle time
-- C_PRH(0:3)_DATA_TOUT - External device (0:3) data bus validity with
-- respect to falling edge of read signal
-- C_PRH(0:3)_DATA_TINV - External device (0:3) data bus high impedence
-- with respect to rising edge of read signal
-- C_PRH(0:3)_RDY_TOUT - External device (0:3) device ready validity from
-- falling edge of read/write signal
-- C_PRH(0:3)_RDY_WIDTH - Maximum wait period for external device (0:3)
-- ready signal assertion
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-----------------------------------------------------
-- PERIPHERAL INTERFACE
-----------------------------------------------------
-- PRH_Clk -- Peripheral interface clock
-- PRH_Rst -- Peripheral interface reset
-- PRH_CS_n -- Peripheral interface chip select
-- PRH_Addr -- Peripheral interface address bus
-- PRH_ADS -- Peripheral interface address strobe
-- PRH_BE -- Peripheral interface byte enables
-- PRH_RNW -- Peripheral interface read/write control for
-- -- synchronous interface
-- PRH_Rd_n -- Peripheral interface read strobe for asynchronous
-- -- interface
-- PRH_Wr_n -- Peripheral interface write strobe for asynchronous
-- -- interface
-- PRH_Burst -- Peripheral interface burst indication signal
-- PRH_Rdy -- Peripheral interface device ready signal
-- PRH_Data_I -- Peripheral interface input data bus
-- PRH_Data_O -- Peripehral interface output data bus
-- PRH_Data_T -- 3-state control for peripheral interface output data
-- -- bus
-------------------------------------------------------------------------------
entity axi_epc is
generic
(
C_S_AXI_CLK_PERIOD_PS : integer := 10000;
C_PRH_CLK_PERIOD_PS : integer := 20000;
-----------------------------------------
C_FAMILY : string := "virtex7";
C_INSTANCE : string := "axi_epc_inst";
C_S_AXI_ADDR_WIDTH : integer range 32 to 32 := 32;
--C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-----------------------------------------
C_NUM_PERIPHERALS : integer range 1 to 4 := 1;
C_PRH_MAX_AWIDTH : integer range 3 to 32:= 32;
C_PRH_MAX_DWIDTH : integer range 8 to 32:= 32;
C_PRH_MAX_ADWIDTH : integer range 8 to 32:= 32;
C_PRH_CLK_SUPPORT : integer range 0 to 1 := 0;
C_PRH_BURST_SUPPORT : integer := 0;
-----------------------------------------
C_PRH0_BASEADDR : std_logic_vector := X"A500_0000";
C_PRH0_HIGHADDR : std_logic_vector := X"A500_FFFF";
C_PRH0_FIFO_ACCESS : integer range 0 to 1:= 0;
C_PRH0_FIFO_OFFSET : integer := 0;
C_PRH0_AWIDTH : integer range 3 to 32:= 32;
C_PRH0_DWIDTH : integer range 8 to 32 := 32;
C_PRH0_DWIDTH_MATCH : integer range 0 to 1:= 0;
C_PRH0_SYNC : integer range 0 to 1:= 1;
C_PRH0_BUS_MULTIPLEX : integer range 0 to 1:= 0;
C_PRH0_ADDR_TSU : integer := 0;
C_PRH0_ADDR_TH : integer := 0;
C_PRH0_ADS_WIDTH : integer := 0;
C_PRH0_CSN_TSU : integer := 0;
C_PRH0_CSN_TH : integer := 0;
C_PRH0_WRN_WIDTH : integer := 0;
C_PRH0_WR_CYCLE : integer := 0;
C_PRH0_DATA_TSU : integer := 0;
C_PRH0_DATA_TH : integer := 0;
C_PRH0_RDN_WIDTH : integer := 0;
C_PRH0_RD_CYCLE : integer := 0;
C_PRH0_DATA_TOUT : integer := 0;
C_PRH0_DATA_TINV : integer := 0;
C_PRH0_RDY_TOUT : integer := 0;
C_PRH0_RDY_WIDTH : integer := 0;
-----------------------------------------
C_PRH1_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_PRH1_HIGHADDR : std_logic_vector := X"0000_0000";
C_PRH1_FIFO_ACCESS : integer range 0 to 1:= 0;
C_PRH1_FIFO_OFFSET : integer := 0;
C_PRH1_AWIDTH : integer range 3 to 32:= 32;
C_PRH1_DWIDTH : integer range 8 to 32 := 32;
C_PRH1_DWIDTH_MATCH : integer range 0 to 1:= 0;
C_PRH1_SYNC : integer range 0 to 1:= 1;
C_PRH1_BUS_MULTIPLEX : integer range 0 to 1:= 0;
C_PRH1_ADDR_TSU : integer := 0;
C_PRH1_ADDR_TH : integer := 0;
C_PRH1_ADS_WIDTH : integer := 0;
C_PRH1_CSN_TSU : integer := 0;
C_PRH1_CSN_TH : integer := 0;
C_PRH1_WRN_WIDTH : integer := 0;
C_PRH1_WR_CYCLE : integer := 0;
C_PRH1_DATA_TSU : integer := 0;
C_PRH1_DATA_TH : integer := 0;
C_PRH1_RDN_WIDTH : integer := 0;
C_PRH1_RD_CYCLE : integer := 0;
C_PRH1_DATA_TOUT : integer := 0;
C_PRH1_DATA_TINV : integer := 0;
C_PRH1_RDY_TOUT : integer := 0;
C_PRH1_RDY_WIDTH : integer := 0;
-----------------------------------------
C_PRH2_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_PRH2_HIGHADDR : std_logic_vector := X"0000_0000";
C_PRH2_FIFO_ACCESS : integer range 0 to 1:= 0;
C_PRH2_FIFO_OFFSET : integer := 0;
C_PRH2_AWIDTH : integer range 3 to 32:= 32;
C_PRH2_DWIDTH : integer range 8 to 32 := 32;
C_PRH2_DWIDTH_MATCH : integer range 0 to 1:= 0;
C_PRH2_SYNC : integer range 0 to 1:= 1;
C_PRH2_BUS_MULTIPLEX : integer range 0 to 1:= 0;
C_PRH2_ADDR_TSU : integer := 0;
C_PRH2_ADDR_TH : integer := 0;
C_PRH2_ADS_WIDTH : integer := 0;
C_PRH2_CSN_TSU : integer := 0;
C_PRH2_CSN_TH : integer := 0;
C_PRH2_WRN_WIDTH : integer := 0;
C_PRH2_WR_CYCLE : integer := 0;
C_PRH2_DATA_TSU : integer := 0;
C_PRH2_DATA_TH : integer := 0;
C_PRH2_RDN_WIDTH : integer := 0;
C_PRH2_RD_CYCLE : integer := 0;
C_PRH2_DATA_TOUT : integer := 0;
C_PRH2_DATA_TINV : integer := 0;
C_PRH2_RDY_TOUT : integer := 0;
C_PRH2_RDY_WIDTH : integer := 0;
-----------------------------------------
C_PRH3_BASEADDR : std_logic_vector := X"FFFF_FFFF";
C_PRH3_HIGHADDR : std_logic_vector := X"0000_0000";
C_PRH3_FIFO_ACCESS : integer range 0 to 1:= 0;
C_PRH3_FIFO_OFFSET : integer := 0;
C_PRH3_AWIDTH : integer range 3 to 32:= 32;
C_PRH3_DWIDTH : integer range 8 to 32 := 32;
C_PRH3_DWIDTH_MATCH : integer range 0 to 1:= 0;
C_PRH3_SYNC : integer range 0 to 1:= 1;
C_PRH3_BUS_MULTIPLEX : integer range 0 to 1:= 0;
C_PRH3_ADDR_TSU : integer := 0;
C_PRH3_ADDR_TH : integer := 0;
C_PRH3_ADS_WIDTH : integer := 0;
C_PRH3_CSN_TSU : integer := 0;
C_PRH3_CSN_TH : integer := 0;
C_PRH3_WRN_WIDTH : integer := 0;
C_PRH3_WR_CYCLE : integer := 0;
C_PRH3_DATA_TSU : integer := 0;
C_PRH3_DATA_TH : integer := 0;
C_PRH3_RDN_WIDTH : integer := 0;
C_PRH3_RD_CYCLE : integer := 0;
C_PRH3_DATA_TOUT : integer := 0;
C_PRH3_DATA_TINV : integer := 0;
C_PRH3_RDY_TOUT : integer := 0;
C_PRH3_RDY_WIDTH : integer := 0
-----------------------------------------
);
port
(
-- system interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- axi write address channel signals
s_axi_awaddr : in std_logic_vector(31 downto 0); --((c_s_axi_addr_width-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- axi write data channel signals
s_axi_wdata : in std_logic_vector(31 downto 0); --((c_s_axi_data_width-1) downto 0);
s_axi_wstrb : in std_logic_vector(3 downto 0); --(((c_s_axi_data_width/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- axi write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- axi read address channel signals
s_axi_araddr : in std_logic_vector(31 downto 0); --((c_s_axi_addr_width-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- axi read address channel signals
s_axi_rdata : out std_logic_vector(31 downto 0); --((c_s_axi_data_width-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- peripheral interface
prh_clk : in std_logic;
prh_rst : in std_logic;
prh_cs_n : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
prh_addr : out std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
prh_ads : out std_logic;
prh_be : out std_logic_vector(0 to C_PRH_MAX_DWIDTH/8-1);
prh_rnw : out std_logic;
prh_rd_n : out std_logic;
prh_wr_n : out std_logic;
prh_burst : out std_logic;
prh_rdy : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
prh_data_i : in std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1);
prh_data_o : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1);
prh_data_t : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1)
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
ATTRIBUTE MAX_FANOUT of prh_clk : signal is "10000";
ATTRIBUTE MAX_FANOUT of prh_rst : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of s_axi_aclk : signal is "Clk";
ATTRIBUTE SIGIS of s_axi_aresetn : signal is "Rst";
ATTRIBUTE SIGIS of prh_clk : signal is "Clk";
ATTRIBUTE SIGIS of prh_rst : signal is "Rst";
ATTRIBUTE XRANGE : string;
ATTRIBUTE XRANGE of C_NUM_PERIPHERALS : constant is "(1:4)";
ATTRIBUTE XRANGE of C_PRH_BURST_SUPPORT : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH_CLK_SUPPORT : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH0_DWIDTH_MATCH : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH1_DWIDTH_MATCH : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH2_DWIDTH_MATCH : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH3_DWIDTH_MATCH : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH0_BUS_MULTIPLEX : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH1_BUS_MULTIPLEX : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH2_BUS_MULTIPLEX : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH3_BUS_MULTIPLEX : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH0_SYNC : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH1_SYNC : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH2_SYNC : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH3_SYNC : constant is "(0,1)";
ATTRIBUTE XRANGE of C_PRH0_DWIDTH : constant is "(8,16,32)";
ATTRIBUTE XRANGE of C_PRH1_DWIDTH : constant is "(8,16,32)";
ATTRIBUTE XRANGE of C_PRH2_DWIDTH : constant is "(8,16,32)";
ATTRIBUTE XRANGE of C_PRH3_DWIDTH : constant is "(8,16,32)";
ATTRIBUTE XRANGE of C_PRH_MAX_AWIDTH : constant is "(3:32)";
ATTRIBUTE XRANGE of C_PRH_MAX_DWIDTH : constant is "(8,16,32)";
ATTRIBUTE XRANGE of C_PRH_MAX_ADWIDTH : constant is "(8:32)";
-----------------------------------------------------------------
-- end of PSFUtil MPD attributes
-----------------------------------------------------------------
end entity axi_epc;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of axi_epc is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-- NAME: get_effective_val
-------------------------------------------------------------------------------
-- Description: Given two possible values that can be taken by an item and a
-- generic setting that affects the actual value taken by the
-- item, this function returns the effective value taken by the
-- item depending on the value of the generic. This function
-- is used to calculate the effective data bus width based on
-- data bus width matching generic (C_PRHx_DWIDTH_MATCH) and
-- effective clock period of peripheral clock based on peripheral
-- clock support generic (C_PRH_CLK_SUPPORT)
-------------------------------------------------------------------------------
function get_effective_val(generic_val : integer;
value_1 : integer;
value_2 : integer)
return integer is
variable effective_val : integer;
begin
if generic_val = 0 then
effective_val := value_1;
else
effective_val := value_2;
end if;
return effective_val;
end function get_effective_val;
-------------------------------------------------------------------------------
-- NAME: get_ard_integer_array
-------------------------------------------------------------------------------
-- Description: Given an integer N, and an unconstrained INTEGER_ARRAY return
-- a constrained array of size N with the first N elements of the
-- input array. This function is used to construct IPIF generic
-- ARD_ID_ARRAY, ARD_DWIDTH_ARRAY, ARD_NUM_CE_ARRAY etc.
-------------------------------------------------------------------------------
function get_ard_integer_array( num_peripherals : integer;
prh_parameter : INTEGER_ARRAY_TYPE )
return INTEGER_ARRAY_TYPE is
variable integer_array : INTEGER_ARRAY_TYPE(0 to num_peripherals-1);
begin
for i in 0 to (num_peripherals - 1) loop
integer_array(i) := prh_parameter(i);
end loop;
return integer_array;
end function get_ard_integer_array;
-------------------------------------------------------------------------------
-- NAME: get_ard_address_range_array
-------------------------------------------------------------------------------
-- Description: Given an integer N, and an unconstrained INTEGER_ARRAY return
-- a constrained array of size N*2 with the first N*2 elements of
-- the input array. This function is used to construct IPIF
-- generic ARD_ADDR_RANGE_ARRAY
-------------------------------------------------------------------------------
function get_ard_addr_range_array ( num_peripherals : integer;
prh_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable addr_range_array : SLV64_ARRAY_TYPE(0 to ((num_peripherals * 2) -1));
begin
for i in 0 to (num_peripherals - 1) loop
addr_range_array(i*2) := prh_addr_range_array(i*2);
addr_range_array((i*2)+1) := prh_addr_range_array((i*2)+1);
end loop;
return addr_range_array;
end function get_ard_addr_range_array;
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant MAX_PERIPHERALS : integer := 4;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_ADDR_WIDTH-1)
:= (others => '0');
constant PRH_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & C_PRH0_BASEADDR,
ZERO_ADDR_PAD & C_PRH0_HIGHADDR,
ZERO_ADDR_PAD & C_PRH1_BASEADDR,
ZERO_ADDR_PAD & C_PRH1_HIGHADDR,
ZERO_ADDR_PAD & C_PRH2_BASEADDR,
ZERO_ADDR_PAD & C_PRH2_HIGHADDR,
ZERO_ADDR_PAD & C_PRH3_BASEADDR,
ZERO_ADDR_PAD & C_PRH3_HIGHADDR
);
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
get_ard_addr_range_array(
C_NUM_PERIPHERALS,
PRH_ADDR_RANGE_ARRAY
);
constant PRH_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
(others => 1);
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
get_ard_integer_array(
C_NUM_PERIPHERALS,
PRH_NUM_CE_ARRAY
);
constant PRH_DWIDTH_ARRAY : INTEGER_ARRAY_TYPE :=
(
C_PRH0_DWIDTH,
C_PRH1_DWIDTH,
C_PRH2_DWIDTH,
C_PRH3_DWIDTH
);
constant NUM_ARD : integer := (ARD_ADDR_RANGE_ARRAY'LENGTH/2);
constant NUM_CE : integer := calc_num_ce(ARD_NUM_CE_ARRAY);
constant PRH0_FIFO_OFFSET : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
conv_std_logic_vector(C_PRH0_FIFO_OFFSET,C_S_AXI_ADDR_WIDTH);
constant PRH1_FIFO_OFFSET : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
conv_std_logic_vector(C_PRH1_FIFO_OFFSET,C_S_AXI_ADDR_WIDTH);
constant PRH2_FIFO_OFFSET : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
conv_std_logic_vector(C_PRH2_FIFO_OFFSET,C_S_AXI_ADDR_WIDTH);
constant PRH3_FIFO_OFFSET : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
conv_std_logic_vector(C_PRH3_FIFO_OFFSET,C_S_AXI_ADDR_WIDTH);
constant PRH0_FIFO_ADDRESS : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
C_PRH0_BASEADDR or PRH0_FIFO_OFFSET;
constant PRH1_FIFO_ADDRESS : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
C_PRH1_BASEADDR or PRH1_FIFO_OFFSET;
constant PRH2_FIFO_ADDRESS : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
C_PRH2_BASEADDR or PRH2_FIFO_OFFSET;
constant PRH3_FIFO_ADDRESS : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH-1) :=
C_PRH3_BASEADDR or PRH3_FIFO_OFFSET;
constant LOCAL_CLK_PERIOD_PS : integer :=
get_effective_val(C_PRH_CLK_SUPPORT,C_S_AXI_CLK_PERIOD_PS,C_PRH_CLK_PERIOD_PS);
-- AXI lite parameters
constant C_S_AXI_EPC_MIN_SIZE : std_logic_vector(31 downto 0):= X"FFFFFFFF";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 0;
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
--bus2ip signals
signal bus2ip_clk : std_logic;
signal bus2ip_reset_active_high : std_logic;
signal bus2ip_reset_active_low : std_logic;
signal bus2ip_cs : std_logic_vector(0 to (ARD_ADDR_RANGE_ARRAY'LENGTH/2)-1);
signal bus2ip_rdce : std_logic_vector(0 to NUM_CE-1);
signal bus2ip_wrce : std_logic_vector(0 to NUM_CE-1);
signal bus2ip_addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal bus2ip_rnw : std_logic;
signal bus2ip_be : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH / 8) - 1);
signal bus2ip_be_int : std_logic_vector((C_S_AXI_DATA_WIDTH / 8) - 1 downto 0);
signal bus2ip_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal bus2ip_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
-- ip2bus signals
signal ip2bus_data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal ip2bus_data_int : std_logic_vector(C_S_AXI_DATA_WIDTH - 1 downto 0);
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
-- local clock and reset signals
signal local_clk : std_logic;
signal local_rst : std_logic;
-- local signals
signal dev_bus2ip_cs : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal dev_bus2ip_rdce : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal dev_bus2ip_wrce : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal dev_bus2ip_addr : std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- NAME: NO_LCLK_LRST_GEN
-------------------------------------------------------------------------------
-- Description: When the C_PRH_CLK_SUPPORT is disabled use AXI clock and
-- AXI reset as the local clock and local reset respectively.
-- The syncrhonous control logic operates on local clock.
-------------------------------------------------------------------------------
NO_LCLK_LRST_GEN: if C_PRH_CLK_SUPPORT = 0 generate
local_clk <= bus2ip_clk;
local_rst <= bus2ip_reset_active_high;
end generate NO_LCLK_LRST_GEN;
-------------------------------------------------------------------------------
-- NAME: LCLK_LRST_GEN
-------------------------------------------------------------------------------
-- Description: When the C_PRH_CLK_SUPPORT is enabled use external peripheral
-- clock and peripheral reset as the local clock and local reset
-- respectively. The syncrhonous control logic operates on local
-- clock.
-------------------------------------------------------------------------------
LCLK_LRST_GEN: if C_PRH_CLK_SUPPORT /= 0 generate
local_clk <= PRH_Clk;
local_rst <= PRH_Rst;
end generate LCLK_LRST_GEN;
-------------------------------------------------------------------------------
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (S_AXI_ACLK) is
begin
if(S_AXI_ACLK'event and S_AXI_ACLK = '1') then
bus2ip_reset_active_high <= not(bus2ip_reset_active_low);
end if;
end process REG_RESET_FROM_IPIF;
----------------------
----------------------------------
-- INSTANTIATE AXI Lite IPIF
----------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0.axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_EPC_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => s_axi_aclk, -- in
S_AXI_ARESETN => s_axi_aresetn, -- in
S_AXI_AWADDR => s_axi_awaddr, -- in
S_AXI_AWVALID => s_axi_awvalid, -- in
S_AXI_AWREADY => s_axi_awready, -- out
S_AXI_WDATA => s_axi_wdata, -- in
S_AXI_WSTRB => s_axi_wstrb, -- in
S_AXI_WVALID => s_axi_wvalid, -- in
S_AXI_WREADY => s_axi_wready, -- out
S_AXI_BRESP => s_axi_bresp, -- out
S_AXI_BVALID => s_axi_bvalid, -- out
S_AXI_BREADY => s_axi_bready, -- in
S_AXI_ARADDR => s_axi_araddr, -- in
S_AXI_ARVALID => s_axi_arvalid, -- in
S_AXI_ARREADY => s_axi_arready, -- out
S_AXI_RDATA => s_axi_rdata, -- out
S_AXI_RRESP => s_axi_rresp, -- out
S_AXI_RVALID => s_axi_rvalid, -- out
S_AXI_RREADY => s_axi_rready, -- in
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_active_low, -- out
Bus2IP_Addr => bus2ip_addr, -- out
Bus2IP_RNW => bus2ip_rnw, -- out
Bus2IP_BE => bus2ip_be_int, -- out
Bus2IP_CS => bus2IP_CS, -- out
Bus2IP_RdCE => bus2ip_rdce, -- out
Bus2IP_WrCE => bus2ip_wrce, -- out
Bus2IP_Data => bus2ip_data_int, -- out
-- Bus2IP_Data => bus2ip_data, -- out
IP2Bus_Data => ip2bus_data_int, -- in
IP2Bus_WrAck => ip2bus_wrack, -- in
IP2Bus_RdAck => ip2bus_rdack, -- in
IP2Bus_Error => ip2bus_error -- in
);
EPC_CORE_I : entity axi_epc_v2_0.epc_core
generic map
(
C_SPLB_CLK_PERIOD_PS => C_S_AXI_CLK_PERIOD_PS,
LOCAL_CLK_PERIOD_PS => LOCAL_CLK_PERIOD_PS,
---------------- -------------------------
C_SPLB_AWIDTH => C_S_AXI_ADDR_WIDTH,
C_SPLB_DWIDTH => C_S_AXI_DATA_WIDTH ,
C_SPLB_NATIVE_DWIDTH => C_S_AXI_DATA_WIDTH ,
C_FAMILY => C_FAMILY,
---------------- -------------------------
C_NUM_PERIPHERALS => C_NUM_PERIPHERALS,
C_PRH_MAX_AWIDTH => C_PRH_MAX_AWIDTH,
C_PRH_MAX_DWIDTH => C_PRH_MAX_DWIDTH,
C_PRH_MAX_ADWIDTH => C_PRH_MAX_ADWIDTH,
C_PRH_CLK_SUPPORT => C_PRH_CLK_SUPPORT,
C_PRH_BURST_SUPPORT => C_PRH_BURST_SUPPORT,
---------------- -------------------------
C_PRH0_FIFO_ACCESS => C_PRH0_FIFO_ACCESS,
C_PRH0_AWIDTH => C_PRH0_AWIDTH,
C_PRH0_DWIDTH => C_PRH0_DWIDTH,
C_PRH0_DWIDTH_MATCH => C_PRH0_DWIDTH_MATCH,
C_PRH0_SYNC => C_PRH0_SYNC,
C_PRH0_BUS_MULTIPLEX => C_PRH0_BUS_MULTIPLEX,
C_PRH0_ADDR_TSU => C_PRH0_ADDR_TSU,
C_PRH0_ADDR_TH => C_PRH0_ADDR_TH,
C_PRH0_ADS_WIDTH => C_PRH0_ADS_WIDTH,
C_PRH0_CSN_TSU => C_PRH0_CSN_TSU,
C_PRH0_CSN_TH => C_PRH0_CSN_TH,
C_PRH0_WRN_WIDTH => C_PRH0_WRN_WIDTH,
C_PRH0_WR_CYCLE => C_PRH0_WR_CYCLE,
C_PRH0_DATA_TSU => C_PRH0_DATA_TSU,
C_PRH0_DATA_TH => C_PRH0_DATA_TH,
C_PRH0_RDN_WIDTH => C_PRH0_RDN_WIDTH,
C_PRH0_RD_CYCLE => C_PRH0_RD_CYCLE,
C_PRH0_DATA_TOUT => C_PRH0_DATA_TOUT,
C_PRH0_DATA_TINV => C_PRH0_DATA_TINV,
C_PRH0_RDY_TOUT => C_PRH0_RDY_TOUT,
C_PRH0_RDY_WIDTH => C_PRH0_RDY_WIDTH,
---------------- -------------------------
C_PRH1_FIFO_ACCESS => C_PRH1_FIFO_ACCESS,
C_PRH1_AWIDTH => C_PRH1_AWIDTH,
C_PRH1_DWIDTH => C_PRH1_DWIDTH,
C_PRH1_DWIDTH_MATCH => C_PRH1_DWIDTH_MATCH,
C_PRH1_SYNC => C_PRH1_SYNC,
C_PRH1_BUS_MULTIPLEX => C_PRH1_BUS_MULTIPLEX,
C_PRH1_ADDR_TSU => C_PRH1_ADDR_TSU,
C_PRH1_ADDR_TH => C_PRH1_ADDR_TH,
C_PRH1_ADS_WIDTH => C_PRH1_ADS_WIDTH,
C_PRH1_CSN_TSU => C_PRH1_CSN_TSU,
C_PRH1_CSN_TH => C_PRH1_CSN_TH,
C_PRH1_WRN_WIDTH => C_PRH1_WRN_WIDTH,
C_PRH1_WR_CYCLE => C_PRH1_WR_CYCLE,
C_PRH1_DATA_TSU => C_PRH1_DATA_TSU,
C_PRH1_DATA_TH => C_PRH1_DATA_TH,
C_PRH1_RDN_WIDTH => C_PRH1_RDN_WIDTH,
C_PRH1_RD_CYCLE => C_PRH1_RD_CYCLE,
C_PRH1_DATA_TOUT => C_PRH1_DATA_TOUT,
C_PRH1_DATA_TINV => C_PRH1_DATA_TINV,
C_PRH1_RDY_TOUT => C_PRH1_RDY_TOUT,
C_PRH1_RDY_WIDTH => C_PRH1_RDY_WIDTH,
---------------- -------------------------
C_PRH2_FIFO_ACCESS => C_PRH2_FIFO_ACCESS,
C_PRH2_AWIDTH => C_PRH2_AWIDTH,
C_PRH2_DWIDTH => C_PRH2_DWIDTH,
C_PRH2_DWIDTH_MATCH => C_PRH2_DWIDTH_MATCH,
C_PRH2_SYNC => C_PRH2_SYNC,
C_PRH2_BUS_MULTIPLEX => C_PRH2_BUS_MULTIPLEX,
C_PRH2_ADDR_TSU => C_PRH2_ADDR_TSU,
C_PRH2_ADDR_TH => C_PRH2_ADDR_TH,
C_PRH2_ADS_WIDTH => C_PRH2_ADS_WIDTH,
C_PRH2_CSN_TSU => C_PRH2_CSN_TSU,
C_PRH2_CSN_TH => C_PRH2_CSN_TH,
C_PRH2_WRN_WIDTH => C_PRH2_WRN_WIDTH,
C_PRH2_WR_CYCLE => C_PRH2_WR_CYCLE,
C_PRH2_DATA_TSU => C_PRH2_DATA_TSU,
C_PRH2_DATA_TH => C_PRH2_DATA_TH,
C_PRH2_RDN_WIDTH => C_PRH2_RDN_WIDTH,
C_PRH2_RD_CYCLE => C_PRH2_RD_CYCLE,
C_PRH2_DATA_TOUT => C_PRH2_DATA_TOUT,
C_PRH2_DATA_TINV => C_PRH2_DATA_TINV,
C_PRH2_RDY_TOUT => C_PRH2_RDY_TOUT,
C_PRH2_RDY_WIDTH => C_PRH2_RDY_WIDTH,
---------------- -------------------------
C_PRH3_FIFO_ACCESS => C_PRH3_FIFO_ACCESS,
C_PRH3_AWIDTH => C_PRH3_AWIDTH,
C_PRH3_DWIDTH => C_PRH3_DWIDTH,
C_PRH3_DWIDTH_MATCH => C_PRH3_DWIDTH_MATCH,
C_PRH3_SYNC => C_PRH3_SYNC,
C_PRH3_BUS_MULTIPLEX => C_PRH3_BUS_MULTIPLEX,
C_PRH3_ADDR_TSU => C_PRH3_ADDR_TSU,
C_PRH3_ADDR_TH => C_PRH3_ADDR_TH,
C_PRH3_ADS_WIDTH => C_PRH3_ADS_WIDTH,
C_PRH3_CSN_TSU => C_PRH3_CSN_TSU,
C_PRH3_CSN_TH => C_PRH3_CSN_TH,
C_PRH3_WRN_WIDTH => C_PRH3_WRN_WIDTH,
C_PRH3_WR_CYCLE => C_PRH3_WR_CYCLE,
C_PRH3_DATA_TSU => C_PRH3_DATA_TSU,
C_PRH3_DATA_TH => C_PRH3_DATA_TH,
C_PRH3_RDN_WIDTH => C_PRH3_RDN_WIDTH,
C_PRH3_RD_CYCLE => C_PRH3_RD_CYCLE,
C_PRH3_DATA_TOUT => C_PRH3_DATA_TOUT,
C_PRH3_DATA_TINV => C_PRH3_DATA_TINV,
C_PRH3_RDY_TOUT => C_PRH3_RDY_TOUT,
C_PRH3_RDY_WIDTH => C_PRH3_RDY_WIDTH,
---------------- -------------------------
MAX_PERIPHERALS => MAX_PERIPHERALS,
PRH0_FIFO_ADDRESS => PRH0_FIFO_ADDRESS,
PRH1_FIFO_ADDRESS => PRH1_FIFO_ADDRESS,
PRH2_FIFO_ADDRESS => PRH2_FIFO_ADDRESS,
PRH3_FIFO_ADDRESS => PRH3_FIFO_ADDRESS
---------------- -------------------------
)
port map (
-- IP Interconnect (IPIC) port signals ----------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Rst => bus2ip_reset_active_high,
Bus2IP_CS => dev_bus2ip_cs,
Bus2IP_RdCE => dev_bus2ip_rdce,
Bus2IP_WrCE => dev_bus2ip_wrce,
Bus2IP_Addr => dev_bus2ip_addr,
Bus2IP_RNW => bus2ip_rnw,
Bus2IP_BE => bus2ip_be,
Bus2IP_Data => bus2ip_data,
-- ip2bus signals ---------------------------------------------------
IP2Bus_Data => ip2bus_data,
IP2Bus_WrAck => ip2bus_wrack,
IP2Bus_RdAck => ip2bus_rdack,
IP2Bus_Error => ip2bus_error,
---------------- -------------------------
Local_Clk => local_clk,
Local_Rst => local_rst,
PRH_CS_n => prh_cs_n,
PRH_Addr => prh_addr,
PRH_ADS => prh_ads,
PRH_BE => prh_be,
PRH_RNW => prh_rnw,
PRH_Rd_n => prh_rd_n,
PRH_Wr_n => prh_wr_n,
PRH_Burst => prh_burst,
PRH_Rdy => prh_rdy,
PRH_Data_I => prh_data_i,
PRH_Data_O => prh_data_o,
PRH_Data_T => prh_data_t
);
dev_bus2ip_cs <= bus2ip_cs((NUM_ARD - C_NUM_PERIPHERALS) to (NUM_ARD -1));
-- Fix the number of CEs per device as one
dev_bus2ip_rdce <= bus2ip_rdce((NUM_CE - C_NUM_PERIPHERALS) to (NUM_CE -1));
dev_bus2ip_wrce <= bus2ip_wrce((NUM_CE - C_NUM_PERIPHERALS) to (NUM_CE -1));
dev_bus2ip_addr <= bus2ip_addr(C_S_AXI_ADDR_WIDTH-C_PRH_MAX_AWIDTH to C_S_AXI_ADDR_WIDTH-1);
-- Little endian to bigendian conversion because the EPC core is in bigendian
PRH_DWIDTH_PROCESS: process (dev_bus2ip_cs, ip2bus_data, bus2ip_data_int, bus2ip_be_int) is
begin
bus2ip_data <= (others => '0');
ip2bus_data_int <= (others => '0');
bus2ip_be <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (dev_bus2ip_cs(i) = '1') then
case PRH_DWIDTH_ARRAY(i) is
when 8 =>
bus2ip_data(0 to 7) <= bus2ip_data_int(7 downto 0);
bus2ip_data(8 to 15) <= bus2ip_data_int(15 downto 8);
bus2ip_data(16 to 23) <= bus2ip_data_int(23 downto 16);
bus2ip_data(24 to 31) <= bus2ip_data_int(31 downto 24);
ip2bus_data_int(7 downto 0) <= ip2bus_data(0 to 7);
ip2bus_data_int(15 downto 8) <= ip2bus_data(8 to 15);
ip2bus_data_int(23 downto 16) <= ip2bus_data(16 to 23);
ip2bus_data_int(31 downto 24) <= ip2bus_data(24 to 31);
bus2ip_be(0) <= bus2ip_be_int(0);
bus2ip_be(1) <= bus2ip_be_int(1);
bus2ip_be(2) <= bus2ip_be_int(2);
bus2ip_be(3) <= bus2ip_be_int(3);
when 16 =>
bus2ip_data(0 to 15) <= bus2ip_data_int(15 downto 0);
bus2ip_data(16 to 31) <= bus2ip_data_int(31 downto 16);
ip2bus_data_int(31 downto 16) <= ip2bus_data(16 to 31);
ip2bus_data_int(15 downto 0) <= ip2bus_data(0 to 15);
bus2ip_be(0 to 1) <= bus2ip_be_int(1 downto 0);
bus2ip_be(2 to 3) <= bus2ip_be_int(3 downto 2);
when 32 =>
bus2ip_data <= bus2ip_data_int;
ip2bus_data_int <= ip2bus_data;
bus2ip_be <= bus2ip_be_int;
-- coverage off
when others =>
bus2ip_data <= bus2ip_data_int;
ip2bus_data_int <= ip2bus_data;
bus2ip_be <= bus2ip_be_int;
-- coverage on
end case;
end if;
end loop;
end process PRH_DWIDTH_PROCESS;
end architecture imp;
--------------------------------end of file------------------------------------
| gpl-3.0 | 0780f1b5d30dc6d2d2cb825668be44ea | 0.461005 | 3.679557 | false | false | false | false |
esar/hdmilight-v1 | fpga/scaler.vhd | 2 | 6,099 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity scaler is
generic (
xdivshift : integer := 5; -- divide X resolution by 32
ydivshift : integer := 5 -- divide Y resolution by 32
);
port (
CLK : in std_logic;
CE2 : in std_logic;
HSYNC_DELAYED : in std_logic;
VSYNC_DELAYED : in std_logic;
RAVG : in std_logic_vector(7 downto 0);
GAVG : in std_logic_vector(7 downto 0);
BAVG : in std_logic_vector(7 downto 0);
LINE_BUF_CLK : in std_logic;
LINE_BUF_ADDR : in std_logic_vector(6 downto 0);
LINE_BUF_DATA : out std_logic_vector(23 downto 0);
LINE_READY : out std_logic;
LINE_ADDR : out std_logic_vector(5 downto 0)
);
end scaler;
architecture Behavioral of scaler is
COMPONENT line_buffer_ram
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
signal HSYNC_LAST : std_logic;
signal END_OF_LINE : std_logic;
signal HSYNC_LAST_LBC : std_logic;
signal END_OF_LINE_LBC : std_logic;
--signal HSYNC_DELAYED : std_logic;
--signal VSYNC_DELAYED : std_logic;
--signal CE2 : std_logic;
--signal CE4 : std_logic;
--signal RAVG : std_logic_vector(7 downto 0);
--signal GAVG : std_logic_vector(7 downto 0);
--signal BAVG : std_logic_vector(7 downto 0);
signal X_COUNT : std_logic_vector(11 downto 0);
signal X_COUNT_RST : std_logic;
signal Y_COUNT : std_logic_vector(10 downto 0);
signal Y_COUNT_CE : std_logic;
signal Y_COUNT_RST : std_logic;
signal Y_COUNT_LAST : std_logic_vector(10 downto 0);
signal Y_COUNT_LAST_CE : std_logic;
signal LINEBUF_RST : std_logic;
signal LINEBUF_WE : std_logic_vector(0 downto 0);
signal LINEBUF_ADDR : std_logic_vector(6 downto 0);
signal LINEBUF_D : std_logic_vector(63 downto 0);
signal LINEBUF_Q : std_logic_vector(63 downto 0);
signal LINEBUF_DB : std_logic_vector(63 downto 0);
begin
line_buffer : line_buffer_ram
PORT MAP (
clka => CLK,
rsta => LINEBUF_RST,
ena => CE2,
wea => LINEBUF_WE,
addra => LINEBUF_ADDR,
dina => LINEBUF_D,
douta => LINEBUF_Q,
clkb => LINE_BUF_CLK,
web => "0",
addrb => LINE_BUF_ADDR,
dinb => (others => '0'),
doutb => LINEBUF_DB
);
--hscale4 : entity work.hscale4 port map(CLK, HSYNC, VSYNC, R, G, B,
-- HSYNC_DELAYED, VSYNC_DELAYED, CE2, CE4, RAVG, GAVG, BAVG);
process(LINE_BUF_CLK)
begin
if(rising_edge(LINE_BUF_CLK)) then
if(CE2 = '1') then
if(HSYNC_DELAYED = '1' and HSYNC_LAST_LBC = '0') then
END_OF_LINE_LBC <= '1';
else
END_OF_LINE_LBC <= '0';
end if;
HSYNC_LAST_LBC <= HSYNC_DELAYED;
end if;
end if;
end process;
process(LINE_BUF_CLK)
begin
if(rising_edge(LINE_BUF_CLK)) then
if(CE2 = '1') then
if(Y_COUNT(4 downto 0) = "11111" and END_OF_LINE_LBC = '1') then
LINE_ADDR <= Y_COUNT_LAST(10 downto 5);
LINE_READY <= '1';
else
LINE_READY <= '0';
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(HSYNC_DELAYED = '1' and HSYNC_LAST = '0') then
END_OF_LINE <= '1';
else
END_OF_LINE <= '0';
end if;
HSYNC_LAST <= HSYNC_DELAYED;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(X_COUNT_RST = '1') then
X_COUNT <= (others => '0');
else
X_COUNT <= std_logic_vector(unsigned(X_COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(Y_COUNT_RST = '1') then
Y_COUNT <= (others => '0');
else
if(Y_COUNT_CE = '1') then
Y_COUNT <= std_logic_vector(unsigned(Y_COUNT) + 1);
end if;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE2 = '1') then
if(Y_COUNT_LAST_CE = '1') then
Y_COUNT_LAST <= Y_COUNT;
end if;
end if;
end if;
end process;
X_COUNT_RST <= HSYNC_DELAYED;
Y_COUNT_RST <= VSYNC_DELAYED;
Y_COUNT_CE <= END_OF_LINE;
Y_COUNT_LAST_CE <= END_OF_LINE;
LINEBUF_ADDR <= Y_COUNT(5) & X_COUNT(9 downto 4);
LINEBUF_RST <= '1' when Y_COUNT(4 downto 0) = "00000" and X_COUNT(3 downto 1) = "000" else '0';
LINEBUF_WE(0) <= X_COUNT(0);
LINEBUF_D(63 downto 48) <= (others => '0');
LINEBUF_D(47 downto 32) <= std_logic_vector(unsigned(LINEBUF_Q(47 downto 32)) + unsigned(RAVG));
LINEBUF_D(31 downto 16) <= std_logic_vector(unsigned(LINEBUF_Q(31 downto 16)) + unsigned(GAVG));
LINEBUF_D(15 downto 0) <= std_logic_vector(unsigned(LINEBUF_Q(15 downto 0)) + unsigned(BAVG));
LINE_BUF_DATA( 7 downto 0) <= LINEBUF_DB(15 downto 8);
LINE_BUF_DATA(15 downto 8) <= LINEBUF_DB(31 downto 24);
LINE_BUF_DATA(23 downto 16) <= LINEBUF_DB(47 downto 40);
end Behavioral;
| gpl-2.0 | ec9530fb1661836a26a7b2cf33ce4a23 | 0.618462 | 2.927988 | false | false | false | false |
ObKo/USBCore | Test/usb_flasher_tb.vhdl | 1 | 7,582 | --
-- USB Full-Speed/Hi-Speed Device Controller core - usb_flasher_tb.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
ENTITY usb_flasher_tb IS
END usb_flasher_tb;
architecture usb_flasher_tb of usb_flasher_tb is
component usb_flasher
port(
clk : in std_logic;
rst : in std_logic;
ctl_xfer_endpoint : in std_logic_vector(3 downto 0);
ctl_xfer_type : in std_logic_vector(7 downto 0);
ctl_xfer_request : in std_logic_vector(7 downto 0);
ctl_xfer_value : in std_logic_vector(15 downto 0);
ctl_xfer_index : in std_logic_vector(15 downto 0);
ctl_xfer_length : in std_logic_vector(15 downto 0);
ctl_xfer_accept : out std_logic;
ctl_xfer : in std_logic;
ctl_xfer_done : out std_logic;
ctl_xfer_data_out : in std_logic_vector(7 downto 0);
ctl_xfer_data_out_valid : in std_logic;
ctl_xfer_data_in : out std_logic_vector(7 downto 0);
ctl_xfer_data_in_valid : out std_logic;
ctl_xfer_data_in_last : out std_logic;
ctl_xfer_data_in_ready : in std_logic;
blk_xfer_endpoint : in std_logic_vector(3 downto 0);
blk_in_xfer : in std_logic;
blk_out_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
blk_xfer_out_ready_read : out std_logic;
blk_xfer_out_data : in std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : in std_logic;
spi_cs : out std_logic;
spi_sck : out std_logic;
spi_mosi : out std_logic;
spi_miso : in std_logic
);
end component;
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal ctl_xfer_endpoint : std_logic_vector(3 downto 0) := (others => '0');
signal ctl_xfer_type : std_logic_vector(7 downto 0) := (others => '0');
signal ctl_xfer_request : std_logic_vector(7 downto 0) := (others => '0');
signal ctl_xfer_value : std_logic_vector(15 downto 0) := (others => '0');
signal ctl_xfer_index : std_logic_vector(15 downto 0) := (others => '0');
signal ctl_xfer_length : std_logic_vector(15 downto 0) := (others => '0');
signal ctl_xfer : std_logic := '0';
signal ctl_xfer_data_out : std_logic_vector(7 downto 0) := (others => '0');
signal ctl_xfer_data_out_valid : std_logic := '0';
signal ctl_xfer_data_in_ready : std_logic := '0';
signal blk_xfer_endpoint : std_logic_vector(3 downto 0) := (others => '0');
signal blk_in_xfer : std_logic := '0';
signal blk_out_xfer : std_logic := '0';
signal blk_xfer_in_data_ready : std_logic := '0';
signal blk_xfer_out_data : std_logic_vector(7 downto 0) := (others => '0');
signal blk_xfer_out_data_valid : std_logic := '0';
signal spi_miso : std_logic := '0';
--Outputs
signal ctl_xfer_accept : std_logic;
signal ctl_xfer_done : std_logic;
signal ctl_xfer_data_in : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid : std_logic;
signal ctl_xfer_data_in_last : std_logic;
signal blk_xfer_in_has_data : std_logic;
signal blk_xfer_in_data : std_logic_vector(7 downto 0);
signal blk_xfer_in_data_valid : std_logic;
signal blk_xfer_in_data_last : std_logic;
signal blk_xfer_out_ready_read : std_logic;
signal spi_cs : std_logic;
signal spi_sck : std_logic;
signal spi_mosi : std_logic;
constant clk_period : time := 10 ns;
BEGIN
FLASHER: usb_flasher
port map (
clk => clk,
rst => rst,
ctl_xfer_endpoint => ctl_xfer_endpoint,
ctl_xfer_type => ctl_xfer_type,
ctl_xfer_request => ctl_xfer_request,
ctl_xfer_value => ctl_xfer_value,
ctl_xfer_index => ctl_xfer_index,
ctl_xfer_length => ctl_xfer_length,
ctl_xfer_accept => ctl_xfer_accept,
ctl_xfer => ctl_xfer,
ctl_xfer_done => ctl_xfer_done,
ctl_xfer_data_out => ctl_xfer_data_out,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid,
ctl_xfer_data_in => ctl_xfer_data_in,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid,
ctl_xfer_data_in_last => ctl_xfer_data_in_last,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready,
blk_xfer_endpoint => blk_xfer_endpoint,
blk_in_xfer => blk_in_xfer,
blk_out_xfer => blk_out_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid,
spi_cs => spi_cs,
spi_sck => spi_sck,
spi_mosi => spi_mosi,
spi_miso => spi_miso
);
ctl_xfer_endpoint <= X"0";
ctl_xfer_type <= X"C0";
ctl_xfer_request <= X"04";
ctl_xfer_value <= X"0085";
ctl_xfer_index <= (others => '0');
ctl_xfer_length <= X"0001";
ctl_xfer_data_in_ready <= '0';
ctl_xfer_data_out <= X"A5";
CLK_GEN: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
STIM: process
begin
wait for 100 ns;
rst <= '1';
wait for clk_period*10;
rst <= '0';
wait for clk_period;
-- blk_out_xfer <= '1';
-- blk_xfer_out_data_valid <= '1';
-- blk_xfer_out_data <= X"A5";
--
-- wait for clk_period;
-- blk_xfer_out_data <= X"88";
--
-- wait for clk_period*255;
-- blk_out_xfer <= '0';
-- blk_xfer_out_data_valid <= '0';
ctl_xfer <= '1';
ctl_xfer_data_out_valid <= '1';
wait for clk_period*100;
ctl_xfer <= '0';
--blk_in_xfer <= '1';
--blk_xfer_in_data_ready <= '1';
--wait for clk_period*256;
--blk_in_xfer <= '0';
--blk_xfer_in_data_ready <= '0';
wait;
end process;
end;
| mit | 45d25e4db75e2d7278174581274fe950 | 0.596149 | 3.148671 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/simulation/ram_16x8k_dp_synth.vhd | 1 | 10,865 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x8k_dp_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ram_16x8k_dp_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ram_16x8k_dp_synth_ARCH OF ram_16x8k_dp_synth IS
COMPONENT ram_16x8k_dp_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ENB: STD_LOGIC := '0';
SIGNAL ENB_R: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
ENB => ENB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ENB_R <= '0' AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
ENB_R <= ENB AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ram_16x8k_dp_exdes PORT MAP (
--Port A
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB_R,
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| bsd-3-clause | 2ca7b06e6f0a4062387894c0dafbf32a | 0.550391 | 3.556465 | false | false | false | false |
esar/hdmilight-v1 | fpga/avr/cpu_core.vhd | 2 | 9,733 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: cpu_core - Behavioral
-- Create Date: 13:51:24 11/07/2009
-- Description: the instruction set implementation of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity cpu_core is
port ( I_CLK : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_DIN : in std_logic_vector( 7 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector( 7 downto 0);
Q_ADR_IO : out std_logic_vector( 7 downto 0);
Q_RD_IO : out std_logic;
Q_WE_IO : out std_logic);
end cpu_core;
architecture Behavioral of cpu_core is
component opc_fetch
port( I_CLK : in std_logic;
I_CLR : in std_logic;
I_INTVEC : in std_logic_vector( 5 downto 0);
I_NEW_PC : in std_logic_vector(15 downto 0);
I_LOAD_PC : in std_logic;
I_PM_ADR : in std_logic_vector(15 downto 0);
I_SKIP : in std_logic;
Q_OPC : out std_logic_vector(31 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PM_DOUT : out std_logic_vector( 7 downto 0);
Q_T0 : out std_logic);
end component;
signal F_PC : std_logic_vector(15 downto 0);
signal F_OPC : std_logic_vector(31 downto 0);
signal F_PM_DOUT : std_logic_vector( 7 downto 0);
signal F_T0 : std_logic;
component opc_deco is
port ( I_CLK : in std_logic;
I_OPC : in std_logic_vector(31 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_T0 : in std_logic;
Q_ALU_OP : out std_logic_vector( 4 downto 0);
Q_AMOD : out std_logic_vector( 5 downto 0);
Q_BIT : out std_logic_vector( 3 downto 0);
Q_DDDDD : out std_logic_vector( 4 downto 0);
Q_IMM : out std_logic_vector(15 downto 0);
Q_JADR : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_PC_OP : out std_logic_vector( 2 downto 0);
Q_PMS : out std_logic; -- program memory select
Q_RD_M : out std_logic;
Q_RRRRR : out std_logic_vector( 4 downto 0);
Q_RSEL : out std_logic_vector( 1 downto 0);
Q_WE_01 : out std_logic;
Q_WE_D : out std_logic_vector( 1 downto 0);
Q_WE_F : out std_logic;
Q_WE_M : out std_logic_vector( 1 downto 0);
Q_WE_XYZS : out std_logic);
end component;
signal D_ALU_OP : std_logic_vector( 4 downto 0);
signal D_AMOD : std_logic_vector( 5 downto 0);
signal D_BIT : std_logic_vector( 3 downto 0);
signal D_DDDDD : std_logic_vector( 4 downto 0);
signal D_IMM : std_logic_vector(15 downto 0);
signal D_JADR : std_logic_vector(15 downto 0);
signal D_OPC : std_logic_vector(15 downto 0);
signal D_PC : std_logic_vector(15 downto 0);
signal D_PC_OP : std_logic_vector(2 downto 0);
signal D_PMS : std_logic;
signal D_RD_M : std_logic;
signal D_RRRRR : std_logic_vector( 4 downto 0);
signal D_RSEL : std_logic_vector( 1 downto 0);
signal D_WE_01 : std_logic;
signal D_WE_D : std_logic_vector( 1 downto 0);
signal D_WE_F : std_logic;
signal D_WE_M : std_logic_vector( 1 downto 0);
signal D_WE_XYZS : std_logic;
component data_path
port( I_CLK : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector( 7 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic);
end component;
signal R_INT_ENA : std_logic;
signal R_NEW_PC : std_logic_vector(15 downto 0);
signal R_LOAD_PC : std_logic;
signal R_SKIP : std_logic;
signal R_ADR : std_logic_vector(15 downto 0);
-- local signals
--
signal L_DIN : std_logic_vector( 7 downto 0);
signal L_INTVEC_5 : std_logic;
begin
opcf : opc_fetch
port map( I_CLK => I_CLK,
I_CLR => I_CLR,
I_INTVEC(5) => L_INTVEC_5,
I_INTVEC(4 downto 0) => I_INTVEC(4 downto 0),
I_LOAD_PC => R_LOAD_PC,
I_NEW_PC => R_NEW_PC,
I_PM_ADR => R_ADR,
I_SKIP => R_SKIP,
Q_PC => F_PC,
Q_OPC => F_OPC,
Q_T0 => F_T0,
Q_PM_DOUT => F_PM_DOUT);
odec : opc_deco
port map( I_CLK => I_CLK,
I_OPC => F_OPC,
I_PC => F_PC,
I_T0 => F_T0,
Q_ALU_OP => D_ALU_OP,
Q_AMOD => D_AMOD,
Q_BIT => D_BIT,
Q_DDDDD => D_DDDDD,
Q_IMM => D_IMM,
Q_JADR => D_JADR,
Q_OPC => D_OPC,
Q_PC => D_PC,
Q_PC_OP => D_PC_OP,
Q_PMS => D_PMS,
Q_RD_M => D_RD_M,
Q_RRRRR => D_RRRRR,
Q_RSEL => D_RSEL,
Q_WE_01 => D_WE_01,
Q_WE_D => D_WE_D,
Q_WE_F => D_WE_F,
Q_WE_M => D_WE_M,
Q_WE_XYZS => D_WE_XYZS);
dpath : data_path
port map( I_CLK => I_CLK,
I_ALU_OP => D_ALU_OP,
I_AMOD => D_AMOD,
I_BIT => D_BIT,
I_DDDDD => D_DDDDD,
I_DIN => L_DIN,
I_IMM => D_IMM,
I_JADR => D_JADR,
I_OPC => D_OPC,
I_PC => D_PC,
I_PC_OP => D_PC_OP,
I_PMS => D_PMS,
I_RD_M => D_RD_M,
I_RRRRR => D_RRRRR,
I_RSEL => D_RSEL,
I_WE_01 => D_WE_01,
I_WE_D => D_WE_D,
I_WE_F => D_WE_F,
I_WE_M => D_WE_M,
I_WE_XYZS => D_WE_XYZS,
Q_ADR => R_ADR,
Q_DOUT => Q_DOUT,
Q_INT_ENA => R_INT_ENA,
Q_NEW_PC => R_NEW_PC,
Q_OPC => Q_OPC,
Q_PC => Q_PC,
Q_LOAD_PC => R_LOAD_PC,
Q_RD_IO => Q_RD_IO,
Q_SKIP => R_SKIP,
Q_WE_IO => Q_WE_IO);
L_DIN <= F_PM_DOUT when (D_PMS = '1') else I_DIN(7 downto 0);
L_INTVEC_5 <= I_INTVEC(5) and R_INT_ENA;
Q_ADR_IO <= R_ADR(7 downto 0);
end Behavioral;
| gpl-2.0 | a1afa8e676408e99eec041cacd4225bb | 0.443029 | 3.40672 | false | false | false | false |
esar/hdmilight-v1 | fpga/avr/status_reg.vhd | 3 | 2,750 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: Register - Behavioral
-- Create Date: 16:15:54 12/26/2009
-- Description: the status register of a CPU.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity status_reg is
port ( I_CLK : in std_logic;
I_COND : in std_logic_vector ( 3 downto 0);
I_DIN : in std_logic_vector ( 7 downto 0);
I_FLAGS : in std_logic_vector ( 7 downto 0);
I_WE_F : in std_logic;
I_WE_SR : in std_logic;
Q : out std_logic_vector ( 7 downto 0);
Q_CC : out std_logic);
end status_reg;
architecture Behavioral of status_reg is
signal L : std_logic_vector ( 7 downto 0);
begin
process(I_CLK)
begin
if (rising_edge(I_CLK)) then
if (I_WE_F = '1') then -- write flags (from ALU)
L <= I_FLAGS;
elsif (I_WE_SR = '1') then -- write I/O
L <= I_DIN;
end if;
end if;
end process;
cond: process(I_COND, L)
begin
case I_COND(2 downto 0) is
when "000" => Q_CC <= L(0) xor I_COND(3);
when "001" => Q_CC <= L(1) xor I_COND(3);
when "010" => Q_CC <= L(2) xor I_COND(3);
when "011" => Q_CC <= L(3) xor I_COND(3);
when "100" => Q_CC <= L(4) xor I_COND(3);
when "101" => Q_CC <= L(5) xor I_COND(3);
when "110" => Q_CC <= L(6) xor I_COND(3);
when others => Q_CC <= L(7) xor I_COND(3);
end case;
end process;
Q <= L;
end Behavioral;
| gpl-2.0 | 68e70817ff2b3305075158ac9afc692c | 0.486182 | 3.701211 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_dverif.vhd | 1 | 5,506 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo8to32_pkg.ALL;
ENTITY fifo8to32_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF fifo8to32_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:fifo8to32_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 5424c2074ebe85e4a935dde497e23e1f | 0.576099 | 4.090639 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/rx_MWr_Channel.vhd | 1 | 36,503 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_MWr_Transact is
port (
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rdst_rdy_n : IN std_logic; -- !!
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- from pre-process module
IOWr_Type : IN std_logic;
MWr_Type : IN std_logic_vector(1 downto 0);
Tlp_straddles_4KB : IN std_logic;
-- Last_DW_of_TLP : IN std_logic;
Tlp_has_4KB : IN std_logic;
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : OUT std_logic;
Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
end entity rx_MWr_Transact;
architecture Behavioral of rx_MWr_Transact is
type RxMWrTrnStates is ( ST_MWr_RESET
, ST_MWr_IDLE
-- , ST_MWr3_HEAD1
-- , ST_MWr4_HEAD1
, ST_MWr3_HEAD2
, ST_MWr4_HEAD2
-- , ST_MWr4_HEAD3
-- , ST_MWr_Last_HEAD
, ST_MWr4_1ST_DATA
, ST_MWr_1ST_DATA
, ST_MWr_1ST_DATA_THROTTLE
, ST_MWr_DATA
, ST_MWr_DATA_THROTTLE
, ST_MWr_LAST_DATA
);
-- State variables
signal RxMWrTrn_NextState : RxMWrTrnStates;
signal RxMWrTrn_State : RxMWrTrnStates;
-- trn_rx stubs
signal trn_rd_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rbar_hit_n_i : std_logic_vector (C_BAR_NUMBER-1 downto 0);
signal trn_rbar_hit_n_r1 : std_logic_vector (C_BAR_NUMBER-1 downto 0);
signal trn_rsrc_rdy_n_i : std_logic;
signal trn_rerrfwd_n_i : std_logic;
signal trn_rsof_n_i : std_logic;
signal trn_reof_n_i : std_logic;
signal trn_rsrc_rdy_n_r1 : std_logic;
signal trn_reof_n_r1 : std_logic;
-- packet RAM and packet FIFOs selection signals
signal FIFO_Space_Sel : std_logic;
signal DDR_Space_Sel : std_logic;
signal REGS_Space_Sel : std_logic;
-- DDR write port
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_FA_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal ddr_wr_1st_mask_hi : std_logic;
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full_i : std_logic;
-- Data generator sequence table write
signal dg_table_Sel : std_logic;
signal tab_wa_odd : std_logic;
signal tab_we_i : std_logic_vector(2-1 downto 0);
signal tab_wa_i : std_logic_vector(12-1 downto 0);
signal tab_wd_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer write port
signal eb_FIFO_we_i : std_logic;
signal eb_FIFO_wsof_i : std_logic;
signal eb_FIFO_weof_i : std_logic;
signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
signal Regs_WrEn_i : std_logic;
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rdst_rdy_n_i : std_logic;
signal trn_rsrc_dsc_n_i : std_logic;
signal trn_rx_throttle : std_logic;
signal trn_rx_throttle_r1 : std_logic;
-- 1st DW BE = "0000" means the TLP is of zero-length.
signal MWr_Has_4DW_Header : std_logic;
signal Tlp_is_Zero_Length : std_logic;
signal MWr_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
begin
-- Event Buffer write
eb_FIFO_we <= eb_FIFO_we_i ;
eb_FIFO_wsof <= eb_FIFO_wsof_i ;
eb_FIFO_weof <= eb_FIFO_weof_i ;
eb_FIFO_din <= eb_FIFO_din_i ;
-- DDR
DDR_wr_sof <= DDR_wr_sof_i ;
DDR_wr_eof <= DDR_wr_eof_i ;
DDR_wr_v <= DDR_wr_v_i ;
DDR_wr_FA <= DDR_wr_FA_i ;
DDR_wr_Shift <= DDR_wr_Shift_i ;
DDR_wr_Mask <= DDR_wr_Mask_i ;
DDR_wr_din <= DDR_wr_din_i ;
DDR_wr_full_i <= DDR_wr_full ;
-- Data generator table
tab_we <= tab_we_i ;
tab_wa <= tab_wa_i ;
tab_wd <= tab_wd_i ;
-- Registers writing
Regs_WrEn <= Regs_WrEn_i;
Regs_WrMask <= Regs_WrMask_i;
Regs_WrAddr <= Regs_WrAddr_i;
Regs_WrDin <= Regs_WrDin_i; -- Mem_WrData;
-- TLP info stubs
trn_rd_i <= trn_rd;
trn_rsof_n_i <= trn_rsof_n;
trn_reof_n_i <= trn_reof_n;
trn_rrem_n_i <= trn_rrem_n;
-- Output to the core as handshaking
trn_rerrfwd_n_i <= trn_rerrfwd_n;
trn_rbar_hit_n_i <= trn_rbar_hit_n;
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
-- Output to the core as handshaking
trn_rsrc_rdy_n_i <= trn_rsrc_rdy_n;
trn_rdst_rdy_n_i <= trn_rdst_rdy_n;
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
trn_rx_throttle <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
-- -----------------------------------------------------
-- Delays: trn_rd_i, trn_rbar_hit_n_i, trn_reof_n_i
-- -----------------------------------------------------
Sync_Delays_trn_rd_rbar_reof:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_rsrc_rdy_n_r1 <= trn_rsrc_rdy_n_i;
trn_reof_n_r1 <= trn_reof_n_i;
trn_rd_r1 <= trn_rd_i;
trn_rrem_n_r1 <= trn_rrem_n_i;
trn_rbar_hit_n_r1 <= trn_rbar_hit_n_i;
trn_rx_throttle_r1 <= trn_rx_throttle;
end if;
end process;
-- -----------------------------------------------------------------------
-- States synchronous
--
Syn_RxTrn_States:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
RxMWrTrn_State <= ST_MWr_RESET;
elsif trn_clk'event and trn_clk = '1' then
RxMWrTrn_State <= RxMWrTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates:
process (
RxMWrTrn_State
, MWr_Type
-- , IOWr_Type
, Tlp_straddles_4KB
, trn_rx_throttle
, trn_reof_n_i
-- , Last_DW_of_TLP
)
begin
case RxMWrTrn_State is
when ST_MWr_RESET =>
RxMWrTrn_NextState <= ST_MWr_IDLE;
when ST_MWr_IDLE =>
if trn_rx_throttle='0' then
case MWr_Type is
when C_TLP_TYPE_IS_MWR_H3 =>
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
when C_TLP_TYPE_IS_MWR_H4 =>
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
when OTHERS =>
-- if IOWr_Type='1' then -- Temp taking IOWr as MWr3
-- RxMWrTrn_NextState <= ST_MWr3_HEAD1;
-- else
RxMWrTrn_NextState <= ST_MWr_IDLE;
-- end if;
end case; -- MWr_Type
else
RxMWrTrn_NextState <= ST_MWr_IDLE;
end if;
-- when ST_MWr3_HEAD1 =>
-- if trn_rx_throttle = '1' then
-- RxMWrTrn_NextState <= ST_MWr3_HEAD1;
-- else
-- RxMWrTrn_NextState <= ST_MWr3_HEAD2;
-- end if;
-- when ST_MWr4_HEAD1 =>
-- if trn_rx_throttle = '1' then
-- RxMWrTrn_NextState <= ST_MWr4_HEAD1;
-- else
-- RxMWrTrn_NextState <= ST_MWr4_HEAD2;
-- end if;
when ST_MWr3_HEAD2 =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
elsif trn_reof_n_i = '0' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_1ST_DATA; -- ST_MWr_Last_HEAD;
end if;
when ST_MWr4_HEAD2 =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
else
RxMWrTrn_NextState <= ST_MWr4_1ST_DATA; -- ST_MWr4_HEAD3;
end if;
-- when ST_MWr4_HEAD3 =>
-- if trn_rx_throttle = '1' then
-- RxMWrTrn_NextState <= ST_MWr4_HEAD3;
-- else
-- RxMWrTrn_NextState <= ST_MWr_Last_HEAD;
-- end if;
-- when ST_MWr_Last_HEAD =>
-- if trn_rx_throttle = '1' then
-- RxMWrTrn_NextState <= ST_MWr_Last_HEAD;
-- elsif Tlp_straddles_4KB = '1' then -- !!
-- RxMWrTrn_NextState <= ST_MWr_IDLE;
---- elsif Last_DW_of_TLP='1' then
---- RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
-- elsif trn_reof_n_i = '0' then
-- RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
-- else
-- RxMWrTrn_NextState <= ST_MWr_1ST_DATA;
-- end if;
when ST_MWr_1ST_DATA =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
elsif trn_reof_n_i = '0' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr4_1ST_DATA =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
elsif trn_reof_n_i = '0' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_1ST_DATA_THROTTLE =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_1ST_DATA_THROTTLE;
elsif trn_reof_n_i = '0' then
RxMWrTrn_NextState <= ST_MWr_IDLE; -- ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_DATA =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_DATA_THROTTLE;
elsif trn_reof_n_i = '0' then
RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_DATA_THROTTLE =>
if trn_rx_throttle = '1' then
RxMWrTrn_NextState <= ST_MWr_DATA_THROTTLE;
elsif trn_reof_n_i = '0' then
RxMWrTrn_NextState <= ST_MWr_LAST_DATA;
else
RxMWrTrn_NextState <= ST_MWr_DATA;
end if;
when ST_MWr_LAST_DATA => -- Same as ST_MWr_IDLE, to support
-- back-to-back transactions
case MWr_Type is
when C_TLP_TYPE_IS_MWR_H3 =>
RxMWrTrn_NextState <= ST_MWr3_HEAD2;
when C_TLP_TYPE_IS_MWR_H4 =>
RxMWrTrn_NextState <= ST_MWr4_HEAD2;
when OTHERS =>
-- if IOWr_Type='1' then
-- RxMWrTrn_NextState <= ST_MWr3_HEAD1;
-- else
RxMWrTrn_NextState <= ST_MWr_IDLE;
-- end if;
end case; -- MWr_Type
when OTHERS =>
RxMWrTrn_NextState <= ST_MWr_RESET;
end case;
end process;
-- ----------------------------------------------
-- registers Write Enable
--
RxFSM_Output_Regs_Write_En:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrMask_i <= "01";
Regs_WrAddr_i <= trn_rd_i(C_EP_AWIDTH-1+32 downto 2+32) & "00";
Regs_WrDin_i <= Endian_Invert_32(trn_rd_i(31 downto 0)) & X"00000000";
-- Regs_WrDin_i <= Endian_Invert_64((trn_rd_r1(31 downto 0)&trn_rd_r1(63 downto 32)));
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
when ST_MWr4_HEAD2 =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= trn_rd_i(C_EP_AWIDTH-1 downto 2) &"00";
Regs_WrDin_i <= Endian_Invert_64(trn_rd_i);
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
when ST_MWr_1ST_DATA =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
if trn_reof_n_i='0' then
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
else
Regs_WrMask_i <= (OTHERS=>'0');
end if;
if MWr_Has_4DW_Header='1' then
Regs_WrAddr_i <= Regs_WrAddr_i;
else
Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
end if;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
when ST_MWr4_1ST_DATA =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
if trn_reof_n_i='0' then
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
else
Regs_WrMask_i <= (OTHERS=>'0');
end if;
-- if MWr_Has_4DW_Header='1' then
Regs_WrAddr_i <= Regs_WrAddr_i;
-- else
-- Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
-- end if;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
when ST_MWr_1ST_DATA_THROTTLE =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= not trn_rx_throttle;
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
if trn_reof_n_i='0' then
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
else
Regs_WrMask_i <= (OTHERS=>'0');
end if;
-- if MWr_Has_4DW_Header='1' then
Regs_WrAddr_i <= Regs_WrAddr_i;
-- else
-- Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(4, C_EP_AWIDTH);
-- end if;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
when ST_MWr_DATA =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= not trn_rx_throttle; -- '1';
if trn_reof_n_i='0' then
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
else
Regs_WrMask_i <= (OTHERS=>'0');
end if;
Regs_WrAddr_i <= Regs_WrAddr_i + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
when ST_MWr_DATA_THROTTLE =>
if REGS_Space_Sel='1' then
Regs_WrEn_i <= not trn_rx_throttle; -- '1';
if trn_reof_n_i='0' then
Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
else
Regs_WrMask_i <= (OTHERS=>'0');
end if;
Regs_WrAddr_i <= Regs_WrAddr_i; -- + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end if;
--------------add for DMA us descriptor-------------
-- when ST_MWr_LAST_DATA =>
-- if REGS_Space_Sel='1' then
-- Regs_WrEn_i <= not trn_rx_throttle; -- '1';
-- if trn_reof_n_i='0' then
-- Regs_WrMask_i <= '0' & (trn_rrem_n_i(3) or trn_rrem_n_i(0));
-- else
-- Regs_WrMask_i <= (OTHERS=>'0');
-- end if;
-- Regs_WrAddr_i <= Regs_WrAddr_i; -- + CONV_STD_LOGIC_VECTOR(8, C_EP_AWIDTH);
-- Regs_WrDin_i <= Endian_Invert_64 (trn_rd_i);
-- else
-- Regs_WrEn_i <= '0';
-- Regs_WrMask_i <= (OTHERS=>'0');
-- Regs_WrAddr_i <= (OTHERS=>'1');
-- Regs_WrDin_i <= (OTHERS=>'0');
-- end if;
--------------add for DMA us descriptor-------------
when OTHERS =>
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrAddr_i <= (OTHERS=>'1');
Regs_WrDin_i <= (OTHERS=>'0');
end case;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: REGS_Space_Sel
--
Syn_Capture_REGS_Space_Sel:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
REGS_Space_Sel <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' then
REGS_Space_Sel <= (trn_rd_i(3) or trn_rd_i(2) or trn_rd_i(1) or trn_rd_i(0))
and not trn_rbar_hit_n_i(CINT_REGS_SPACE_BAR);
else
REGS_Space_Sel <= REGS_Space_Sel;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MWr_Has_4DW_Header
-- : Tlp_is_Zero_Length
--
Syn_Capture_MWr_Has_4DW_Header:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
MWr_Has_4DW_Header <= '0';
Tlp_is_Zero_Length <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' then
MWr_Has_4DW_Header <= trn_rd_i(C_TLP_FMT_BIT_BOT);
Tlp_is_Zero_Length <= not (trn_rd_i(3) or trn_rd_i(2) or trn_rd_i(1) or trn_rd_i(0));
else
MWr_Has_4DW_Header <= MWr_Has_4DW_Header;
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MWr_Leng_in_Bytes
--
Syn_Capture_MWr_Length_in_Bytes:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
MWr_Leng_in_Bytes <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' then
-- Assume no 4KB length for MWr
MWr_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 2)
<= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
else
MWr_Leng_in_Bytes <= MWr_Leng_in_Bytes;
end if;
end if;
end process;
-- ----------------------------------------------
-- Synchronous outputs: DDR Space Select --
-- ----------------------------------------------
RxFSM_Output_DDR_Space_Selected:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
DDR_Space_Sel <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
ddr_wr_1st_mask_hi <= '0';
elsif trn_clk'event and trn_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
and Tlp_is_Zero_Length='0'
then
DDR_Space_Sel <= not trn_rd_i(32+19) and not trn_rd_i(32+18); -- '1';
DDR_wr_sof_i <= not trn_rd_i(32+19) and not trn_rd_i(32+18); -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= not trn_rsrc_rdy_n_i and not trn_rd_i(32+19) and not trn_rd_i(32+18);
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= not trn_rd_i(2+32);
DDR_wr_Mask_i <= (OTHERS=>'0');
ddr_wr_1st_mask_hi <= '1';
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(64-1 downto 32);
else
DDR_Space_Sel <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(64-1 downto 32);
end if;
when ST_MWr4_HEAD2 =>
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
and Tlp_is_Zero_Length='0'
then
DDR_Space_Sel <= not trn_rd_i(19) and not trn_rd_i(18); -- '1';
DDR_wr_sof_i <= not trn_rd_i(19) and not trn_rd_i(18); -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= not trn_rsrc_rdy_n_i and not trn_rd_i(19) and not trn_rd_i(18);
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= trn_rd_i(2);
DDR_wr_Mask_i <= (OTHERS=>'0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(32-1 downto 0);
else
DDR_Space_Sel <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= MWr_Leng_in_Bytes(31 downto 0) & trn_rd_i(32-1 downto 0);
end if;
when ST_MWr4_1ST_DATA =>
DDR_Space_Sel <= DDR_Space_Sel;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
ddr_wr_1st_mask_hi <= '0';
DDR_wr_din_i <= (OTHERS=>'0');
when OTHERS =>
if trn_reof_n_r1='0' then
DDR_Space_Sel <= '0';
else
DDR_Space_Sel <= DDR_Space_Sel;
end if;
if DDR_Space_Sel='1' then
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= not trn_reof_n_r1;
DDR_wr_v_i <= not trn_rx_throttle_r1; -- not trn_rsrc_rdy_n_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= ddr_wr_1st_mask_hi & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
DDR_wr_din_i <= Endian_Invert_64 (trn_rd_r1);
else
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= Endian_Invert_64 (trn_rd_r1);
end if;
if DDR_wr_v_i='1' then
ddr_wr_1st_mask_hi <= '0';
else
ddr_wr_1st_mask_hi <= ddr_wr_1st_mask_hi;
end if;
end case;
end if;
end process;
-- ----------------------------------------------
-- Synchronous outputs: DGen Table write --
-- ----------------------------------------------
RxFSM_Output_DGen_Table_write:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
-- Assume every PIO MWr contains only 1 DW(32 bits) payload
dg_table_Sel <= '0';
tab_we_i <= (OTHERS=>'0');
tab_wa_i <= (OTHERS=>'0');
tab_wd_i <= (OTHERS=>'0');
tab_wa_odd <= '0';
elsif trn_clk'event and trn_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
and Tlp_is_Zero_Length='0'
then
dg_table_Sel <= trn_rd_i(19) and trn_rd_i(18) and not trn_rd_i(17) and not trn_rd_i(16); -- any expression
tab_we_i <= (trn_rd_i(32+19) and trn_rd_i(32+18) and not trn_rd_i(32+17) and not trn_rd_i(32+16) and not trn_rd_i(34))
& (trn_rd_i(32+19) and trn_rd_i(32+18) and not trn_rd_i(32+17) and not trn_rd_i(32+16) and trn_rd_i(34));
tab_wa_i <= trn_rd_i(32+3+11 downto 32+3);
tab_wa_odd <= trn_rd_i(32+2);
tab_wd_i <= Endian_Invert_64 ( (trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)) );
else
dg_table_Sel <= '0';
tab_we_i <= (OTHERS=>'0');
tab_wa_i <= trn_rd_i(32+3+11 downto 32+3);
tab_wa_odd <= trn_rd_i(32+2);
tab_wd_i <= Endian_Invert_64 ( (trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)));
end if;
when ST_MWr4_HEAD2 =>
if trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0'
and Tlp_is_Zero_Length='0'
then
dg_table_Sel <= trn_rd_i(19) and trn_rd_i(18) and not trn_rd_i(17) and not trn_rd_i(16);
tab_we_i <= (OTHERS=>'0');
tab_wa_i <= trn_rd_i(3+11 downto 3);
tab_wa_odd <= trn_rd_i(2);
tab_wd_i <= Endian_Invert_64 ( (trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
else
dg_table_Sel <= '0';
tab_we_i <= (OTHERS=>'0');
tab_wa_i <= trn_rd_i(3+11 downto 3);
tab_wa_odd <= trn_rd_i(2);
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
end if;
when ST_MWr4_1ST_DATA =>
dg_table_Sel <= dg_table_Sel;
tab_we_i <= (dg_table_Sel and not trn_rx_throttle and not tab_wa_odd)
& (dg_table_Sel and not trn_rx_throttle and tab_wa_odd);
tab_wa_i <= tab_wa_i;
tab_wa_odd <= tab_wa_odd;
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
when ST_MWr_1ST_DATA_THROTTLE =>
dg_table_Sel <= dg_table_Sel;
tab_we_i <= (dg_table_Sel and not trn_rx_throttle and not tab_wa_odd)
& (dg_table_Sel and not trn_rx_throttle and tab_wa_odd);
tab_wa_i <= tab_wa_i;
tab_wa_odd <= tab_wa_odd;
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
when OTHERS =>
dg_table_Sel <= '0';
tab_we_i <= (OTHERS=>'0');
tab_wa_i <= tab_wa_i;
tab_wa_odd <= tab_wa_odd;
tab_wd_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
end case;
end if;
end process;
-- ----------------------------------------------
-- Synchronous outputs: EB FIFO Select --
-- ----------------------------------------------
RxFSM_Output_FIFO_Space_Selected:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
FIFO_Space_Sel <= '0';
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
case RxMWrTrn_State is
when ST_MWr3_HEAD2 =>
if trn_rbar_hit_n_r1(CINT_FIFO_SPACE_BAR)='0'
and Tlp_is_Zero_Length='0'
then
FIFO_Space_Sel <= '1';
eb_FIFO_we_i <= not trn_reof_n_i; -- '1';
eb_FIFO_wsof_i <= not trn_reof_n_i; -- '1';
eb_FIFO_weof_i <= not trn_reof_n_i; -- '1';
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)));
else
FIFO_Space_Sel <= '0';
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(32-1 downto 0) & trn_rd_i(32-1 downto 0)));
end if;
when ST_MWr_1ST_DATA =>
FIFO_Space_Sel <= FIFO_Space_Sel;
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
eb_FIFO_din_i <= Endian_Invert_64 (( trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32) ));
when ST_MWr4_HEAD2 =>
if trn_rbar_hit_n_r1(CINT_FIFO_SPACE_BAR)='0'
and Tlp_is_Zero_Length='0'
then
FIFO_Space_Sel <= '1';
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
else
FIFO_Space_Sel <= '0';
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
end if;
when ST_MWr4_1ST_DATA =>
FIFO_Space_Sel <= FIFO_Space_Sel;
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
if trn_rrem_n_i(3)='1' or trn_rrem_n_i(0)='1' then
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
else
eb_FIFO_din_i <= Endian_Invert_64 (trn_rd_i);
end if;
when ST_MWr_1ST_DATA_THROTTLE =>
if MWr_Has_4DW_Header='1' then
FIFO_Space_Sel <= FIFO_Space_Sel;
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- trn_rx_throttle;
if trn_rrem_n_i(3)='1' or trn_rrem_n_i(0)='1' then
eb_FIFO_din_i <= Endian_Invert_64 ((trn_rd_i(64-1 downto 32) & trn_rd_i(64-1 downto 32)));
else
eb_FIFO_din_i <= Endian_Invert_64 (trn_rd_i);
end if;
else
FIFO_Space_Sel <= FIFO_Space_Sel;
eb_FIFO_we_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
eb_FIFO_wsof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
eb_FIFO_weof_i <= FIFO_Space_Sel and not trn_reof_n_i; -- '1';
eb_FIFO_din_i <= Endian_Invert_64 (( trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32) ));
end if;
when OTHERS =>
FIFO_Space_Sel <= '0';
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
end case;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | b33e2342fd13ed34c88da937e7484078 | 0.442292 | 3.255418 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/data_steer.vhd | 1 | 60,260 | -------------------------------------------------------------------------------
-- data_steer.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : data_steer.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI data steering logic
-- Structure : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics --
-------------------------------------------------------------------------------
-- C_SPLB_NATIVE_DWIDTH - Data bus width of PLB bus
-- C_PRH_MAX_DWIDTH - Maximum of data bus width of peripheral devices
-- ALL_PRH_DWIDTH_MATCH - Indication that all devices are employing data width
-- matching
-- NO_PRH_DWIDTH_MATCH - Indication that no device is employing data width
-- matching
-- NO_PRH_SYNC - Indicates all devices are configured for
-- asynchronous interface
-- NO_PRH_ASYNC - Indicates all devices are configured for
-- synchronous interface
-- ADDRCNT_WIDTH - Width of address suffix generated by address
-- generation logic
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Rst - IPIC reset
-- Local_Clk - Operational clock for peripheral interface
-- Local_Rst - Reset for peripheral interface
-- Bus2IP_RNW - IPIC read/write control
-- Bus2IP_BE - Byte enables from IPIC interface
-- Bus2IP_Data - Data bus from IPIC interface
-- Dev_in_access - Indication that peripheral interface is being
-- accessed by the PLB master
-- Dev_sync - Indicates if the current device being accessed
-- is synchronous device
-- Dev_rnw - Read/write control indication from IPIC interface
-- Dev_dwidth_match - Indicates if the current device employs data width
-- - matching
-- Dev_dbus_width - Indicates decoded value for the data bus width
-- Addr_suffix - Least significant address bits
-- Steer_index - Index for data steering
-- Async_en - Indication from asynchronous logic to latch the
-- read data bus
-- Async_ce - Indication of currently read bytes to asynchronous
-- conrol logic
-- Sync_en - Indication from synchronous logic to latch the
-- read data bus
-- Sync_ce - Indication of currently read bytes to synchronous
-- conrol logic
-- PRH_Data_In - Peripheral interface input bus for read access
-- PRH_BE - Byte enables for external peripheral devices
-- Data_Int - Internal peripheral data bus to be driven out
-- to the external peripheral devices
-- IP2Bus_Data - Data bus to the IPIC interface on a read access
-------------------------------------------------------------------------------
entity data_steer is
generic (
C_SPLB_NATIVE_DWIDTH : integer;
C_PRH_MAX_DWIDTH : integer;
ALL_PRH_DWIDTH_MATCH : integer;
NO_PRH_DWIDTH_MATCH : integer;
NO_PRH_SYNC : integer;
NO_PRH_ASYNC : integer;
ADDRCNT_WIDTH : integer
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
Local_Clk : in std_logic;
Local_Rst : in std_logic;
Bus2IP_RNW : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
Bus2IP_Data : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
Dev_bus_multiplex : in std_logic;
--dev_fifo_access : in std_logic;
Dev_in_access : in std_logic;
Dev_sync : in std_logic;
Dev_rnw : in std_logic;
Dev_dwidth_match : in std_logic;
Dev_dbus_width : in std_logic_vector(0 to 2);
Addr_suffix : in std_logic_vector(0 to ADDRCNT_WIDTH-1);
Steer_index : out std_logic_vector(0 to ADDRCNT_WIDTH-1);
Async_en : in std_logic;
Async_ce : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
Sync_en : in std_logic;
Sync_ce : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
PRH_Data_In : in std_logic_vector(0 to C_PRH_MAX_DWIDTH-1);
PRH_BE : out std_logic_vector(0 to C_PRH_MAX_DWIDTH/8-1);
Data_Int : out std_logic_vector(0 to C_PRH_MAX_DWIDTH-1);
IP2Bus_Data : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1)
);
end entity data_steer;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of data_steer is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant BYTE_SIZE : integer := 8;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal steer_index_i : std_logic_vector(0 to ADDRCNT_WIDTH-1) :=
(others => '0');
signal steer_data_in : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) :=
(others => '0');
signal no_steer_data_in : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) :=
(others => '0');
signal data_in : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) :=
(others => '0');
signal async_ip2bus_data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) :=
(others => '0');
signal sync_ip2bus_data : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) :=
(others => '0');
signal ip2bus_data_int : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1) :=
(others => '0');
signal no_steer_async_ce:
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal steer_async_ce :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal async_ce_i :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal no_steer_sync_ce :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal steer_sync_ce :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal sync_ce_i :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal async_rd_ce :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal sync_rd_ce :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal steer_data : std_logic_vector(0 to C_PRH_MAX_DWIDTH-1)
:= (others => '0');
signal steer_be : std_logic_vector(0 to C_PRH_MAX_DWIDTH/8-1)
:= (others => '0');
--
signal prh_be_i : std_logic_vector(0 to C_PRH_MAX_DWIDTH/8-1)
:= (others => '0');
signal data_Int_i : std_logic_vector(0 to C_PRH_MAX_DWIDTH-1)
:= (others => '0');
--
signal sync_rd_ce_d1 :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
signal sync_rd_ce_int :
std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1) := (others => '0');
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
--------------------------------
-- NAME: NO_DEV_DWIDTH_MATCH_GEN
-- Description: If no device employs data width matching, then generate
-- Data_Int, PRH_BE and IP2Bus_Data
----------------------------------------------------------------------
NO_DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 1 generate
Async_ce <= (others => '0');
Sync_ce <= (others => '0');
Steer_index <= (others => '0');
-----------------
-- For write path
-----------------
Data_Int <= Bus2IP_Data(0 to C_PRH_MAX_DWIDTH-1);
prh_be_i <= Bus2IP_BE(0 to C_PRH_MAX_DWIDTH/8-1);
REG_PRH_SIGS2 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
PRH_BE <= prh_be_i;
end if;
end process REG_PRH_SIGS2;
-----------------
-- For read path
-----------------
------------------------------------------
-- NAME: PRH_MAX_DWIDTH_32_RD_NO_STEER_GEN
-- Description: Generate data for PLB interface
------------------------------------------------
PRH_MAX_DWIDTH_32_RD_NO_STEER_GEN: if C_PRH_MAX_DWIDTH = 32 generate
------------------------------
-- NAME: NO_STEER_DATA_PROCESS
-- Description: Generate data for PLB interface
-----------------------------------------------
NO_STEER_DATA_PROCESS: process(Dev_dbus_width, PRH_Data_In) is
begin
no_steer_data_in <= (others => '0');
case Dev_dbus_width is
-- Device width is 8 bits
-- when "001" =>
-- no_steer_data_in(0 to BYTE_SIZE-1) <= PRH_Data_In(0 to BYTE_SIZE-1);
-- Device width is 16 bits
-- when "010" =>
-- no_steer_data_in(0 to 2*BYTE_SIZE-1)<= PRH_Data_In(0 to 2*BYTE_SIZE-1);
-- Device width is 32 bits
when "100" =>
no_steer_data_in(0 to 4*BYTE_SIZE-1)<= PRH_Data_In(0 to 4*BYTE_SIZE-1);
-- coverage off
when others =>
no_steer_data_in <= (others => '0');
-- coverage on
end case;
end process NO_STEER_DATA_PROCESS;
end generate PRH_MAX_DWIDTH_32_RD_NO_STEER_GEN;
---------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_16_RD_NO_STEER_GEN
---------------------------------------------------------------------------
-- Description: Generate data for PLB interface
---------------------------------------------------------------------------
PRH_MAX_DWIDTH_16_RD_NO_STEER_GEN: if C_PRH_MAX_DWIDTH = 16 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_DATA_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data for PLB interface
-------------------------------------------------------------------------
NO_STEER_DATA_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
no_steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_data_in(0 to BYTE_SIZE-1)
<= PRH_Data_In(0 to BYTE_SIZE-1);
when "010" =>
no_steer_data_in(0 to 2*BYTE_SIZE-1)
<= PRH_Data_In(0 to 2*BYTE_SIZE-1);
when others =>
no_steer_data_in <= (others => '0');
end case;
end process NO_STEER_DATA_PROCESS;
end generate PRH_MAX_DWIDTH_16_RD_NO_STEER_GEN;
---------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_8_RD_NO_STEER_GEN
---------------------------------------------------------------------------
-- Description: Generate data for PLB interface
---------------------------------------------------------------------------
PRH_MAX_DWIDTH_8_RD_NO_STEER_GEN: if C_PRH_MAX_DWIDTH = 8 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_DATA_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data for PLB interface
-------------------------------------------------------------------------
NO_STEER_DATA_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
no_steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_data_in(0 to BYTE_SIZE-1)
<= PRH_Data_In(0 to BYTE_SIZE-1);
when others =>
no_steer_data_in <= (others => '0');
end case;
end process NO_STEER_DATA_PROCESS;
end generate PRH_MAX_DWIDTH_8_RD_NO_STEER_GEN;
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as synchronous devices
-----------------------------------------------------------------------------
SOME_DEV_SYNC_GEN: if NO_PRH_SYNC = 0 generate
---------------------------------------------------------------------------
-- NAME: NO_STEER_SYNC_CE_PROCESS
---------------------------------------------------------------------------
-- Description: Generate data enables for PLB interface
---------------------------------------------------------------------------
NO_STEER_SYNC_CE_PROCESS: process(Dev_dbus_width, Sync_en)
begin
no_steer_sync_ce <= (others => '0');
case Dev_dbus_width is
-- coverage off
when "001" =>
no_steer_sync_ce(0) <= Sync_en;
when "010" =>
for i in 0 to 1 loop
no_steer_sync_ce(i) <= Sync_en;
end loop;
-- coverage on
when "100" =>
for i in 0 to 3 loop
no_steer_sync_ce(i) <= Sync_en;
end loop;
when others =>
no_steer_sync_ce <= (others => '0');
end case;
end process NO_STEER_SYNC_CE_PROCESS;
---------------------------------------------------------------------------
-- NAME: SYNC_RDREG_GEN
---------------------------------------------------------------------------
-- Description: Generate input data registers
---------------------------------------------------------------------------
SYNC_RDREG_GEN: for i in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1 generate
-------------------------------------------------------------------------
-- NAME: SYNC_RDREG_BYTE_GEN
-------------------------------------------------------------------------
-- Description: Generate input data registers
-------------------------------------------------------------------------
SYNC_RDREG_BYTE_GEN: for j in 0 to BYTE_SIZE-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SYNC_RDREG_BIT: label is "TRUE";
begin
SYNC_RDREG_BIT: component FDRE
port map (
Q => Sync_ip2bus_data(i*BYTE_SIZE+j),
C => Local_Clk,
CE => no_steer_sync_ce(i),
D => PRH_Data_In(i*BYTE_SIZE+j),
R => Local_Rst
);
end generate SYNC_RDREG_BYTE_GEN;
end generate SYNC_RDREG_GEN;
---------------------------------------------------------------------------
-- NAME: PRH_DWIDTH_LT_PLB_DWIDTH_GEN
---------------------------------------------------------------------------
-- Description: Tie the higher order bits of data to zero
---------------------------------------------------------------------------
PRH_DWIDTH_LT_PLB_DWIDTH_GEN: if C_PRH_MAX_DWIDTH < C_SPLB_NATIVE_DWIDTH
generate
sync_ip2bus_data(C_PRH_MAX_DWIDTH to C_SPLB_NATIVE_DWIDTH-1) <=
(others => '0');
end generate PRH_DWIDTH_LT_PLB_DWIDTH_GEN;
end generate SOME_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as asynchronous devices
-----------------------------------------------------------------------------
SOME_DEV_ASYNC_GEN: if NO_PRH_ASYNC = 0 generate
---------------------------------------------------------------------------
-- NAME: NO_STEER_ASYNC_CE_PROCESS
---------------------------------------------------------------------------
-- Description: Generate data enables for PLB interface
---------------------------------------------------------------------------
NO_STEER_ASYNC_CE_PROCESS: process(Dev_dbus_width, Async_en)
begin
no_steer_async_ce <= (others => '0');
case Dev_dbus_width is
-- coverage off
when "001" =>
no_steer_async_ce(0) <= Async_en;
when "010" =>
for i in 0 to 1 loop
no_steer_async_ce(i) <= Async_en;
end loop;
-- coverage on
when "100" =>
for i in 0 to 3 loop
no_steer_async_ce(i) <= Async_en;
end loop;
-- coverage off
when others =>
no_steer_async_ce <= (others => '0');
-- coverage on
end case;
end process NO_STEER_ASYNC_CE_PROCESS;
---------------------------------------------------------------------------
-- NAME: ASYNC_RDREG_GEN
---------------------------------------------------------------------------
-- Description: Generate input data registers
---------------------------------------------------------------------------
ASYNC_RDREG_GEN: for i in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1 generate
-------------------------------------------------------------------------
-- NAME: ASYNC_RDREG_BYTE_GEN
-------------------------------------------------------------------------
-- Description: Generate input data registers
-------------------------------------------------------------------------
ASYNC_RDREG_BYTE_GEN: for j in 0 to BYTE_SIZE-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of ASYNC_RDREG_BIT: label is "TRUE";
begin
ASYNC_RDREG_BIT: component FDRE
port map (
Q => async_ip2bus_data(i*BYTE_SIZE+j),
C => Bus2IP_Clk,
CE => no_steer_async_ce(i),
D => PRH_Data_In(i*BYTE_SIZE+j),
R => Bus2IP_Rst
);
end generate ASYNC_RDREG_BYTE_GEN;
end generate ASYNC_RDREG_GEN;
---------------------------------------------------------------------------
-- NAME: PRH_DWIDTH_LT_PLB_DWIDTH_GEN
---------------------------------------------------------------------------
-- Description: Tie the higher order bits of data to zero
---------------------------------------------------------------------------
PRH_DWIDTH_LT_PLB_DWIDTH_GEN: if C_PRH_MAX_DWIDTH < C_SPLB_NATIVE_DWIDTH
generate
async_ip2bus_data(C_PRH_MAX_DWIDTH to C_SPLB_NATIVE_DWIDTH-1) <=
(others => '0');
end generate PRH_DWIDTH_LT_PLB_DWIDTH_GEN;
end generate SOME_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as synchronous devices
-----------------------------------------------------------------------------
ALL_DEV_SYNC_GEN: if NO_PRH_ASYNC = 1 generate
async_ip2bus_data <= (others => '0');
ip2bus_data_int <= sync_ip2bus_data;
end generate ALL_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as asynchronous devices
-----------------------------------------------------------------------------
ALL_DEV_ASYNC_GEN: if NO_PRH_SYNC = 1 generate
sync_ip2bus_data <= (others => '0');
ip2bus_data_int <= async_ip2bus_data;
end generate ALL_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: DEV_SYNC_AND_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some devices are configured as synchronous and some
-- asynchronous
-----------------------------------------------------------------------------
DEV_SYNC_AND_ASYNC_GEN: if NO_PRH_SYNC = 0 and NO_PRH_ASYNC = 0 generate
ip2bus_data_int <= async_ip2bus_data when Dev_sync = '0'
else sync_ip2bus_data;
end generate DEV_SYNC_AND_ASYNC_GEN;
IP2Bus_Data <= ip2bus_data_int when (Bus2IP_RNW = '1' and Dev_in_access = '1')
else (others => '0');
end generate NO_DEV_DWIDTH_MATCH_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_DWIDTH_MATCH_GEN
-------------------------------------------------------------------------------
-- Description: If any device employs data width matching, then generate data
-- and byte steering logic for write and read path along with data
-- registering for read path
-------------------------------------------------------------------------------
DEV_DWIDTH_MATCH_GEN: if NO_PRH_DWIDTH_MATCH = 0 generate
---------------------------------------------------------------------------
-- NAME: STEER_INDEX_PROCESS
---------------------------------------------------------------------------
-- Description: Generate index for steering logic from the address suffix
---------------------------------------------------------------------------
STEER_INDEX_PROCESS: process(Dev_dbus_width, Addr_suffix)
begin
steer_index_i <= (others => '0');
case Dev_dbus_width is
when "001" =>
steer_index_i <= Addr_suffix;
when "010" =>
steer_index_i <= '0' & Addr_suffix(0 to ADDRCNT_WIDTH-2);
when "100" =>
steer_index_i <= (others => '0');
when others =>
steer_index_i <= (others => '0');
end case;
end process STEER_INDEX_PROCESS;
Steer_index <= steer_index_i;
-----------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_32_WR_STEER_GEN
-----------------------------------------------------------------------------
-- Description: Generate steering logic for write data path when the
-- peripheral data bus is 32 bit
-----------------------------------------------------------------------------
PRH_MAX_DWIDTH_32_WR_STEER_GEN: if C_PRH_MAX_DWIDTH = 32 generate
---------------------------------------------------------------------------
-- NAME: WR_32_STEER_PROCESS
---------------------------------------------------------------------------
-- Description: Generate steering logic for write path when the peripheral
-- data bus width 32 bits
---------------------------------------------------------------------------
WR_32_STEER_PROCESS: process(Dev_dbus_width, steer_index_i,
Bus2IP_Data, Bus2IP_BE)
begin
steer_data <= (others => '0');
steer_be <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_data(0 to BYTE_SIZE-1) <= Bus2IP_Data(i*BYTE_SIZE to
i*BYTE_SIZE + BYTE_SIZE-1);
steer_be(0) <= Bus2IP_BE(i);
end if;
end loop;
when "010" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/(BYTE_SIZE*2) -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_data(0 to 2*BYTE_SIZE-1) <= Bus2IP_Data(i*BYTE_SIZE*2 to
i*BYTE_SIZE*2 + 2*BYTE_SIZE-1);
steer_be(0 to 1) <= Bus2IP_BE(i*2 to (i*2)+1);
end if;
end loop;
when "100" =>
steer_data <= Bus2IP_Data;
steer_be <= Bus2IP_BE;
when others =>
steer_data <= (others => '0');
steer_be <= (others => '0');
end case;
end process WR_32_STEER_PROCESS;
end generate PRH_MAX_DWIDTH_32_WR_STEER_GEN;
-----------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_16_WR_STEER_GEN
-----------------------------------------------------------------------------
-- Description: Generate steering logic for write data path when the
-- peripheral data bus is 16 bit
-----------------------------------------------------------------------------
PRH_MAX_DWIDTH_16_WR_STEER_GEN: if C_PRH_MAX_DWIDTH = 16 generate
---------------------------------------------------------------------------
-- NAME: WR_16_STEER_PROCESS
---------------------------------------------------------------------------
-- Description: Generate steering logic for write path when the peripheral
-- data bus width is 16 bits
---------------------------------------------------------------------------
WR_16_STEER_PROCESS: process(Dev_dbus_width, steer_index_i,
Bus2IP_Data, Bus2IP_BE)
begin
steer_data <= (others => '0');
steer_be <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_data(0 to BYTE_SIZE-1) <= Bus2IP_Data(i*BYTE_SIZE to
i*BYTE_SIZE + BYTE_SIZE-1);
steer_be(0) <= Bus2IP_BE(i);
end if;
end loop;
when "010" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/(BYTE_SIZE*2) -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_data(0 to 2*BYTE_SIZE-1) <= Bus2IP_Data(i*BYTE_SIZE*2 to
i*BYTE_SIZE*2 + 2*BYTE_SIZE-1);
steer_be(0 to 1) <= Bus2IP_BE(i*2 to (i*2)+1);
end if;
end loop;
when others =>
steer_data <= (others => '0');
steer_be <= (others => '0');
end case;
end process WR_16_STEER_PROCESS;
end generate PRH_MAX_DWIDTH_16_WR_STEER_GEN;
-----------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_8_WR_STEER_GEN
-----------------------------------------------------------------------------
-- Description: Generate steering logic for write data path when the
-- peripheral data bus is 8 bit
-----------------------------------------------------------------------------
PRH_MAX_DWIDTH_8_WR_STEER_GEN: if C_PRH_MAX_DWIDTH = 8 generate
---------------------------------------------------------------------------
-- NAME: WR_8_STEER_PROCESS
---------------------------------------------------------------------------
-- Description: Generate steering logic for write path when the
-- peripheral data bus width is 8 bits
---------------------------------------------------------------------------
WR_8_STEER_PROCESS: process(Dev_dbus_width, steer_index_i,
Bus2IP_Data, Bus2IP_BE)
begin
steer_data <= (others => '0');
steer_be <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_data(0 to BYTE_SIZE-1) <= Bus2IP_Data(i*BYTE_SIZE to
i*BYTE_SIZE + BYTE_SIZE-1);
steer_be(0) <= Bus2IP_BE(i);
end if;
end loop;
when others =>
steer_data <= (others => '0');
steer_be <= (others => '0');
end case;
end process WR_8_STEER_PROCESS;
end generate PRH_MAX_DWIDTH_8_WR_STEER_GEN;
-- Generate data for peripheral interface
Data_Int <= Bus2IP_Data(0 to C_PRH_MAX_DWIDTH-1) when Dev_dwidth_match = '0'
else steer_data;
--for STA only
-- Generate BE for peripheral interface
prh_be_i <= Bus2IP_BE(0 to C_PRH_MAX_DWIDTH/8 -1) when Dev_dwidth_match = '0'
else steer_be;
REG_PRH_SIGS4 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
PRH_BE <= prh_be_i;
end if;
end process REG_PRH_SIGS4;
-----------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_32_RD_STEER_GEN
-----------------------------------------------------------------------------
-- Description: Generate steering logic for read path when the
-- peripheral data bus is 32 bit
-----------------------------------------------------------------------------
PRH_MAX_DWIDTH_32_RD_STEER_GEN: if C_PRH_MAX_DWIDTH = 32 generate
---------------------------------------------------------------------------
-- NAME: RD_32_STEER_PROCESS
---------------------------------------------------------------------------
-- Description: Generate steering logic for read path when peripheral
-- data bus width is 32 bits
---------------------------------------------------------------------------
RD_32_STEER_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1 loop
steer_data_in(i*BYTE_SIZE to i*BYTE_SIZE+BYTE_SIZE-1) <=
PRH_Data_In(0 to BYTE_SIZE-1);
end loop;
when "010" =>
for i in 0 to C_PRH_MAX_DWIDTH/(BYTE_SIZE*2)-1 loop
steer_data_in(i*BYTE_SIZE*2 to i*BYTE_SIZE*2+BYTE_SIZE*2-1) <=
PRH_Data_In(0 to BYTE_SIZE*2-1);
end loop;
when "100" =>
steer_data_in <= PRH_Data_In;
when others =>
steer_data_in <= (others => '0');
end case;
end process RD_32_STEER_PROCESS;
end generate PRH_MAX_DWIDTH_32_RD_STEER_GEN;
-----------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_16_RD_STEER_GEN
-----------------------------------------------------------------------------
-- Description: Generate steering logic for read and write when the
-- peripheral data bus is 16 bit
-----------------------------------------------------------------------------
PRH_MAX_DWIDTH_16_RD_STEER_GEN: if C_PRH_MAX_DWIDTH = 16 generate
---------------------------------------------------------------------------
-- NAME: RD_16_STEER_PROCESS
---------------------------------------------------------------------------
-- Description: Generate steering logic for read path when the peripheral
-- data bus width is 16 bits
---------------------------------------------------------------------------
RD_16_STEER_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1 loop
steer_data_in(i*BYTE_SIZE to i*BYTE_SIZE+BYTE_SIZE-1) <=
PRH_Data_In(0 to BYTE_SIZE-1);
end loop;
when "010" =>
for i in 0 to C_PRH_MAX_DWIDTH/(BYTE_SIZE*2)-1 loop
steer_data_in(i*BYTE_SIZE*2 to i*BYTE_SIZE*2+BYTE_SIZE*2-1) <=
PRH_Data_In(0 to BYTE_SIZE*2-1);
end loop;
when others =>
steer_data_in <= (others => '0');
end case;
end process RD_16_STEER_PROCESS;
end generate PRH_MAX_DWIDTH_16_RD_STEER_GEN;
-----------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_8_RD_STEER_GEN
-----------------------------------------------------------------------------
-- Description: Generate steering logic for read and write when the
-- peripheral data bus is 8 bit
-----------------------------------------------------------------------------
PRH_MAX_DWIDTH_8_RD_STEER_GEN: if C_PRH_MAX_DWIDTH = 8 generate
---------------------------------------------------------------------------
-- NAME: RD_8_STEER_PROCESS
---------------------------------------------------------------------------
-- Description: Generate steering logic for read path when the
-- peripheral data bus width is 8 bits
---------------------------------------------------------------------------
RD_8_STEER_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1 loop
steer_data_in(i*BYTE_SIZE to i*BYTE_SIZE+BYTE_SIZE-1) <=
PRH_Data_In(0 to BYTE_SIZE-1);
end loop;
when others =>
steer_data_in <= (others => '0');
end case;
end process RD_8_STEER_PROCESS;
end generate PRH_MAX_DWIDTH_8_RD_STEER_GEN;
------------------------------------------------------------------------------
-- NAME: ALL_DEV_DWIDTH_MATCH_GEN
------------------------------------------------------------------------------
-- Description: If not all device employs data width matching, then generate
-- data in without steering
------------------------------------------------------------------------------
ALL_DEV_DWIDTH_MATCH_GEN: if ALL_PRH_DWIDTH_MATCH = 0 generate
---------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_32_RD_NO_STEER_GEN
---------------------------------------------------------------------------
-- Description: Generate data for PLB interface without steering
---------------------------------------------------------------------------
PRH_MAX_DWIDTH_32_RD_NO_STEER_GEN: if C_PRH_MAX_DWIDTH = 32 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_DATA_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data for PLB interface without steering
-------------------------------------------------------------------------
NO_STEER_DATA_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
no_steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_data_in(0 to BYTE_SIZE-1)
<= PRH_Data_In(0 to BYTE_SIZE-1);
when "010" =>
no_steer_data_in(0 to 2*BYTE_SIZE-1)
<= PRH_Data_In(0 to 2*BYTE_SIZE-1);
when "100" =>
no_steer_data_in(0 to 4*BYTE_SIZE-1)
<= PRH_Data_In(0 to 4*BYTE_SIZE-1);
when others =>
no_steer_data_in <= (others => '0');
end case;
end process NO_STEER_DATA_PROCESS;
end generate PRH_MAX_DWIDTH_32_RD_NO_STEER_GEN;
---------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_16_RD_NO_STEER_GEN
---------------------------------------------------------------------------
-- Description: Generate data for PLB interface without steering
---------------------------------------------------------------------------
PRH_MAX_DWIDTH_16_RD_NO_STEER_GEN: if C_PRH_MAX_DWIDTH = 16 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_DATA_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data for PLB interface without steering
-------------------------------------------------------------------------
NO_STEER_DATA_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
no_steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_data_in(0 to BYTE_SIZE-1)
<= PRH_Data_In(0 to BYTE_SIZE-1);
when "010" =>
no_steer_data_in(0 to 2*BYTE_SIZE-1)
<= PRH_Data_In(0 to 2*BYTE_SIZE-1);
when others =>
no_steer_data_in <= (others => '0');
end case;
end process NO_STEER_DATA_PROCESS;
end generate PRH_MAX_DWIDTH_16_RD_NO_STEER_GEN;
---------------------------------------------------------------------------
-- NAME: PRH_MAX_DWIDTH_8_RD_NO_STEER_GEN
---------------------------------------------------------------------------
-- Description: Generate data for PLB interface without steering
---------------------------------------------------------------------------
PRH_MAX_DWIDTH_8_RD_NO_STEER_GEN: if C_PRH_MAX_DWIDTH = 8 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_DATA_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data for PLB interface without steering
-------------------------------------------------------------------------
NO_STEER_DATA_PROCESS: process(Dev_dbus_width, PRH_Data_In)
begin
no_steer_data_in <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_data_in(0 to BYTE_SIZE-1)
<= PRH_Data_In(0 to BYTE_SIZE-1);
when others =>
no_steer_data_in <= (others => '0');
end case;
end process NO_STEER_DATA_PROCESS;
end generate PRH_MAX_DWIDTH_8_RD_NO_STEER_GEN;
end generate ALL_DEV_DWIDTH_MATCH_GEN;
------------------------------------------------------------------------------
-- NAME: NOT_ALL_DEV_DWIDTH_MATCH_GEN
------------------------------------------------------------------------------
-- Description: If all device employs data width matching, then
-- non-steered data is not required
------------------------------------------------------------------------------
NOT_ALL_DEV_DWIDTH_MATCH_GEN: if ALL_PRH_DWIDTH_MATCH = 1 generate
no_steer_data_in <= (others => '0');
end generate NOT_ALL_DEV_DWIDTH_MATCH_GEN;
data_in <= no_steer_data_in when Dev_dwidth_match = '0' else steer_data_in;
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as synchronous devices
-----------------------------------------------------------------------------
SOME_DEV_SYNC_GEN: if NO_PRH_SYNC = 0 generate
-------------------------------------------------------------------------
-- NAME: STEER_SYNC_CE_PROCESS
--------------------------------------------------------------------------
-- Description: Generate data enables for synchronous interface
-- after steering to the appropriate byte lane
-------------------------------------------------------------------------
STEER_SYNC_CE_PROCESS: process(Dev_dbus_width, steer_index_i, Sync_en)
begin
steer_sync_ce <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_sync_ce(i) <= Sync_en;
end if;
end loop;
when "010" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/(BYTE_SIZE*2)-1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_sync_ce(i*2) <= Sync_en;
steer_sync_ce(i*2+1) <= Sync_en;
end if;
end loop;
when "100" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1 loop
steer_sync_ce(i) <= Sync_en;
end loop;
when others =>
steer_sync_ce <= (others => '0');
end case;
end process STEER_SYNC_CE_PROCESS;
---------------------------------------------------------------------------
-- NAME: ALL_DEV_DWIDTH_MATCH_GEN
---------------------------------------------------------------------------
-- Description: If not all device employs data width matching, then
-- generate data enables without steering
---------------------------------------------------------------------------
ALL_DEV_DWIDTH_MATCH_GEN: if ALL_PRH_DWIDTH_MATCH = 0 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_SYNC_CE_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data enables without steering for synchronous
-- interface
-------------------------------------------------------------------------
NO_STEER_SYNC_CE_PROCESS: process(Dev_dbus_width, Sync_en)
begin
no_steer_sync_ce <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_sync_ce(0) <= Sync_en;
when "010" =>
for i in 0 to 1 loop
no_steer_sync_ce(i) <= Sync_en;
end loop;
when "100" =>
for i in 0 to 3 loop
no_steer_sync_ce(i) <= Sync_en;
end loop;
when others =>
no_steer_sync_ce <= (others => '0');
end case;
end process NO_STEER_SYNC_CE_PROCESS;
end generate ALL_DEV_DWIDTH_MATCH_GEN;
---------------------------------------------------------------------------
-- NAME: NOT_ALL_DEV_DWIDTH_MATCH_GEN
---------------------------------------------------------------------------
-- Description: If all device employs data width matching, then
-- non-steered data enables are not required
---------------------------------------------------------------------------
NOT_ALL_DEV_DWIDTH_MATCH_GEN: if ALL_PRH_DWIDTH_MATCH = 1 generate
no_steer_sync_ce <= (others => '0');
end generate NOT_ALL_DEV_DWIDTH_MATCH_GEN;
-- Generate data enable for the current device
sync_ce_i <= no_steer_sync_ce when Dev_dwidth_match = '0'
else steer_sync_ce;
Sync_ce <= sync_ce_i;
---------------------------------------------------------------------------
-- NAME: SYNC_RD_CE_GEN
---------------------------------------------------------------------------
-- Description: Qualify the data enable for the current device with the
-- read signal for registering read data from synchronous
-- interface
---------------------------------------------------------------------------
SYNC_RD_CE_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1 generate
sync_rd_ce(i) <= sync_ce_i(i) and Dev_rnw;
end generate SYNC_RD_CE_GEN;
REG_SYNC_RD_CE : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
sync_rd_ce_d1 <= sync_rd_ce;
end if;
end process REG_SYNC_RD_CE;
SYNC_RD_PROCESS: process (Dev_bus_multiplex, sync_rd_ce_d1, sync_rd_ce)
begin
if (Dev_bus_multiplex='0') then
sync_rd_ce_int <= sync_rd_ce_d1;
else
sync_rd_ce_int <= sync_rd_ce;
end if;
end process SYNC_RD_PROCESS;
-- sync_rd_ce_int <= sync_rd_ce_d1 when (Dev_dwidth_match='0') else
-- sync_rd_ce;
---------------------------------------------------------------------------
-- NAME: SYNC_RDREG_PLBWIDTH_GEN
---------------------------------------------------------------------------
-- Description: Generate read registers for synchronous interface
---------------------------------------------------------------------------
SYNC_RDREG_PLBWIDTH_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/C_PRH_MAX_DWIDTH-1
generate
-------------------------------------------------------------------------
-- NAME: SYNC_RDREG_PRHWIDTH_GEN
-------------------------------------------------------------------------
-- Description: Generate read registers for synchronous interface
-------------------------------------------------------------------------
SYNC_RDREG_PRHWIDTH_GEN: for j in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1
generate
-----------------------------------------------------------------------
-- NAME: SYNC_RDREG_BYTE_GEN
-----------------------------------------------------------------------
-- Description: Generate read registers for synchronous interface
-----------------------------------------------------------------------
SYNC_RDREG_BYTE_GEN: for k in 0 to BYTE_SIZE-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SYNC_RDREG_BIT: label is "TRUE";
begin
SYNC_RDREG_BIT: component FDRE
port map (
Q => sync_ip2bus_data(i*C_PRH_MAX_DWIDTH+j*BYTE_SIZE+k),
C => Local_Clk,
CE => sync_rd_ce_int(i*C_PRH_MAX_DWIDTH/BYTE_SIZE+j),
D => data_in(j*BYTE_SIZE+k),
R => Local_Rst
);
end generate SYNC_RDREG_BYTE_GEN;
end generate SYNC_RDREG_PRHWIDTH_GEN;
end generate SYNC_RDREG_PLBWIDTH_GEN;
end generate SOME_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: SOME_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some or all devices are configured as asynchronous devices
-----------------------------------------------------------------------------
SOME_DEV_ASYNC_GEN: if NO_PRH_ASYNC = 0 generate
-------------------------------------------------------------------------
-- NAME: STEER_ASYNC_CE_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data enables for asynchronous interface
-- after steering to the appropriate byte lane
-------------------------------------------------------------------------
STEER_ASYNC_CE_PROCESS: process(Dev_dbus_width, steer_index_i, Async_en)
begin
steer_async_ce <= (others => '0');
case Dev_dbus_width is
when "001" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_async_ce(i) <= Async_en;
end if;
end loop;
when "010" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/(BYTE_SIZE*2) -1 loop
if steer_index_i = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
steer_async_ce(i*2) <= Async_en;
steer_async_ce(i*2+1) <= Async_en;
end if;
end loop;
when "100" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1 loop
steer_async_ce(i) <= Async_en;
end loop;
when others =>
steer_async_ce <= (others => '0');
end case;
end process STEER_ASYNC_CE_PROCESS;
---------------------------------------------------------------------------
-- NAME: ALL_DEV_DWIDTH_MATCH_GEN
---------------------------------------------------------------------------
-- Description: If not all device employs data width matching, then
-- generate data enables without steering
---------------------------------------------------------------------------
ALL_DEV_DWIDTH_MATCH_GEN: if ALL_PRH_DWIDTH_MATCH = 0 generate
-------------------------------------------------------------------------
-- NAME: NO_STEER_ASYNC_CE_PROCESS
-------------------------------------------------------------------------
-- Description: Generate data enables without steering for asynchronous
-- interface
-------------------------------------------------------------------------
NO_STEER_ASYNC_CE_PROCESS: process(Dev_dbus_width, Async_en)
begin
no_steer_async_ce <= (others => '0');
case Dev_dbus_width is
when "001" =>
no_steer_async_ce(0) <= Async_en;
when "010" =>
for i in 0 to 1 loop
no_steer_async_ce(i) <= Async_en;
end loop;
when "100" =>
for i in 0 to 3 loop
no_steer_async_ce(i) <= Async_en;
end loop;
when others =>
no_steer_async_ce <= (others => '0');
end case;
end process NO_STEER_ASYNC_CE_PROCESS;
end generate ALL_DEV_DWIDTH_MATCH_GEN;
---------------------------------------------------------------------------
-- NAME: NOT_ALL_DEV_DWIDTH_MATCH_GEN
-------- ------------------------------------------------------------------
-- Description: If all device employs data width matching, then
-- non-steered data enables are not required
---------------------------------------------------------------------------
NOT_ALL_DEV_DWIDTH_MATCH_GEN: if ALL_PRH_DWIDTH_MATCH = 1 generate
no_steer_async_ce <= (others => '0');
end generate NOT_ALL_DEV_DWIDTH_MATCH_GEN;
-- Generate data enables for the current device
async_ce_i <= no_steer_async_ce when Dev_dwidth_match = '0'
else steer_async_ce;
Async_ce <= async_ce_i;
---------------------------------------------------------------------------
-- NAME: ASYNC_RD_CE_GEN
---------------------------------------------------------------------------
-- Description: Qualify the data enables for the current device with the
-- read signal for registering read data from asynchronous
-- interface
---------------------------------------------------------------------------
ASYNC_RD_CE_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1 generate
async_rd_ce(i) <= async_ce_i(i) and Dev_rnw;
end generate ASYNC_RD_CE_GEN;
---------------------------------------------------------------------------
-- NAME: ASYNC_RDREG_PLBWIDTH_GEN
---------------------------------------------------------------------------
-- Description: Generate read registers for asynchronous interface
---------------------------------------------------------------------------
ASYNC_RDREG_PLBWIDTH_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/C_PRH_MAX_DWIDTH-1
generate
-------------------------------------------------------------------------
-- NAME: ASYNC_RDREG_PRHWIDTH_GEN
-------------------------------------------------------------------------
-- Description: Generate read registers for asynchronous interface
-------------------------------------------------------------------------
ASYNC_RDREG_PRHWIDTH_GEN: for j in 0 to C_PRH_MAX_DWIDTH/BYTE_SIZE-1
generate
-----------------------------------------------------------------------
-- NAME: ASYNC_RDREG_BYTE_GEN
-----------------------------------------------------------------------
-- Description: Generate read registers for asynchronous interface
-----------------------------------------------------------------------
ASYNC_RDREG_BYTE_GEN: for k in 0 to BYTE_SIZE-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of ASYNC_RDREG_BIT: label is "TRUE";
begin
ASYNC_RDREG_BIT: component FDRE
port map (
Q => async_ip2bus_data(i*C_PRH_MAX_DWIDTH+j*BYTE_SIZE+k),
C => Bus2IP_Clk,
CE => async_rd_ce(i*C_PRH_MAX_DWIDTH/BYTE_SIZE+j),
D => data_in(j*BYTE_SIZE+k),
R => Bus2IP_Rst
);
end generate ASYNC_RDREG_BYTE_GEN;
end generate ASYNC_RDREG_PRHWIDTH_GEN;
end generate ASYNC_RDREG_PLBWIDTH_GEN;
end generate SOME_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_SYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as synchronous devices
-----------------------------------------------------------------------------
ALL_DEV_SYNC_GEN: if NO_PRH_ASYNC = 1 generate
ip2bus_data_int <= sync_ip2bus_data;
Async_ce <= (others => '0');
end generate ALL_DEV_SYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: ALL_DEV_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: All devices are configured as asynchronous devices
-----------------------------------------------------------------------------
ALL_DEV_ASYNC_GEN: if NO_PRH_SYNC = 1 generate
ip2bus_data_int <= async_ip2bus_data;
Sync_ce <= (others => '0');
end generate ALL_DEV_ASYNC_GEN;
-----------------------------------------------------------------------------
-- NAME: DEV_SYNC_AND_ASYNC_GEN
-----------------------------------------------------------------------------
-- Description: Some devices are configured as synchronous and some
-- asynchronous
-----------------------------------------------------------------------------
DEV_SYNC_AND_ASYNC_GEN: if NO_PRH_SYNC = 0 and NO_PRH_ASYNC = 0 generate
ip2bus_data_int <= async_ip2bus_data when Dev_sync = '0'
else sync_ip2bus_data;
end generate DEV_SYNC_AND_ASYNC_GEN;
IP2Bus_Data <= ip2bus_data_int when (Bus2IP_RNW = '1' and Dev_in_access = '1')
else (others => '0');
end generate DEV_DWIDTH_MATCH_GEN;
end architecture imp;
--------------------------------end of file------------------------------------
| gpl-3.0 | b2b7694bdefad16159d8157e22ce5478 | 0.404348 | 4.735188 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72.vhd | 1 | 10,225 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_mBuf_128x72.vhd when simulating
-- the core, k7_mBuf_128x72. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_mBuf_128x72 IS
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END k7_mBuf_128x72;
ARCHITECTURE k7_mBuf_128x72_a OF k7_mBuf_128x72 IS
-- synthesis translate_off
COMPONENT wrapped_k7_mBuf_128x72
PORT (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_mBuf_128x72 USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 9,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "kintex7",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 6,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 4,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 128,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 127,
c_prog_full_type => 1,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 9,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 0,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 9,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_mBuf_128x72
PORT MAP (
clk => clk,
rst => rst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
prog_full => prog_full
);
-- synthesis translate_on
END k7_mBuf_128x72_a;
| gpl-2.0 | 25172222eef9188fd0875424e5dc9f3f | 0.537408 | 3.294137 | false | false | false | false |
esar/hdmilight-v1 | fpga/lightAverager.vhd | 2 | 8,934 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity lightAverager is
port (
CLK : in std_logic;
CE : in std_logic;
START : in std_logic;
YPOS : in std_logic_vector(5 downto 0);
LINE_BUF_ADDR : out std_logic_vector(6 downto 0);
LINE_BUF_DATA : in std_logic_vector(23 downto 0);
CONFIG_ADDR : out std_logic_vector(8 downto 0);
CONFIG_DATA : in std_logic_vector(31 downto 0);
RESULT_CLK : in std_logic;
RESULT_ADDR : in std_logic_vector(8 downto 0);
RESULT_DATA : out std_logic_vector(31 downto 0)
);
end lightAverager;
architecture Behavioral of lightAverager is
COMPONENT resultRam
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(71 DOWNTO 0)
);
END COMPONENT;
-- count is overflow (1), xpos (6), light (8), read/write (1) = 16 bits
signal COUNT : std_logic_vector(15 downto 0);
signal FRAME : std_logic := '0';
signal RUNNING : std_logic;
signal WRITE_CYCLE : std_logic;
signal XPOS : std_logic_vector(5 downto 0);
signal LIGHT_ADDR : std_logic_vector(7 downto 0);
signal WRITE_ENABLE : std_logic;
signal WRITE_ADDR : std_logic_vector(7 downto 0);
signal WRITE_DATA : std_logic_vector(71 downto 0);
signal RESULT_RAM_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_WE : std_logic_vector(0 downto 0);
signal RESULT_RAM_D : std_logic_vector(71 downto 0);
signal RESULT_RAM_Q : std_logic_vector(71 downto 0);
signal RESULT_RAM_B_ADDR : std_logic_vector(8 downto 0);
signal RESULT_RAM_B_Q : std_logic_vector(71 downto 0);
signal XMIN_p0 : std_logic_vector(5 downto 0);
signal XMAX_p0 : std_logic_vector(5 downto 0);
signal YMIN_p0 : std_logic_vector(5 downto 0);
signal YMAX_p0 : std_logic_vector(5 downto 0);
signal SHIFT_p0 : std_logic_vector(3 downto 0);
signal OUT_ADDR_p0 : std_logic_vector(2 downto 0);
signal R_TOTAL_p0 : std_logic_vector(20 downto 0);
signal G_TOTAL_p0 : std_logic_vector(20 downto 0);
signal B_TOTAL_p0 : std_logic_vector(20 downto 0);
signal R_p0 : std_logic_vector(7 downto 0);
signal G_p0 : std_logic_vector(7 downto 0);
signal B_p0 : std_logic_vector(7 downto 0);
signal WRITE_ADDR_p0 : std_logic_vector(7 downto 0);
signal XPOS_p0 : std_logic_vector(5 downto 0);
signal YPOS_p0 : std_logic_vector(5 downto 0);
signal RUNNING_p0 : std_logic;
signal SHIFT_p1 : std_logic_vector(3 downto 0);
signal OUT_ADDR_p1 : std_logic_vector(2 downto 0);
signal R_TOTAL_p1 : std_logic_vector(20 downto 0);
signal G_TOTAL_p1 : std_logic_vector(20 downto 0);
signal B_TOTAL_p1 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p1 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p1 : std_logic;
signal OUT_ADDR_p2 : std_logic_vector(2 downto 0);
signal R_TOTAL_p2 : std_logic_vector(20 downto 0);
signal G_TOTAL_p2 : std_logic_vector(20 downto 0);
signal B_TOTAL_p2 : std_logic_vector(20 downto 0);
signal WRITE_ADDR_p2 : std_logic_vector(7 downto 0);
signal WRITE_ENABLE_p2 : std_logic;
begin
resultBuffer : resultRam
PORT MAP (
clka => CLK,
ena => CE,
wea => RESULT_RAM_WE,
addra => RESULT_RAM_ADDR,
dina => RESULT_RAM_D,
douta => RESULT_RAM_Q,
clkb => RESULT_CLK,
web => "0",
addrb => RESULT_RAM_B_ADDR,
dinb => (others=> '0'),
doutb => RESULT_RAM_B_Q
);
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(START = '1') then
COUNT <= (others => '0');
RUNNING <= '1';
if(YPOS = "000000") then
FRAME <= not FRAME;
end if;
elsif(COUNT(15) = '1') then
RUNNING <= '0';
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
-- read address is set when write_cycle = '0'
-- so read data is available when write_cycle = '1'
if(WRITE_CYCLE = '1') then
XMIN_p0 <= CONFIG_DATA(5 downto 0);
XMAX_p0 <= CONFIG_DATA(11 downto 6);
YMIN_p0 <= CONFIG_DATA(17 downto 12);
YMAX_p0 <= CONFIG_DATA(23 downto 18);
SHIFT_p0 <= CONFIG_DATA(27 downto 24);
OUT_ADDR_p0 <= CONFIG_DATA(30 downto 28);
R_TOTAL_p0 <= RESULT_RAM_Q(20 downto 0);
G_TOTAL_p0 <= RESULT_RAM_Q(41 downto 21);
B_TOTAL_p0 <= RESULT_RAM_Q(62 downto 42);
R_p0 <= LINE_BUF_DATA(23 downto 16);
G_p0 <= LINE_BUF_DATA(15 downto 8);
B_p0 <= LINE_BUF_DATA( 7 downto 0);
WRITE_ADDR_p0 <= LIGHT_ADDR;
XPOS_p0 <= XPOS;
YPOS_p0 <= YPOS;
RUNNING_p0 <= RUNNING;
end if;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
if(RUNNING_p0 = '1' and
unsigned(XPOS_p0) >= unsigned(XMIN_p0) and unsigned(XPOS_p0) <= unsigned(XMAX_p0) and
unsigned(YPOS_p0) >= unsigned(YMIN_p0) and unsigned(YPOS_p0) <= unsigned(YMAX_p0)) then
WRITE_ENABLE_p1 <= '1';
else
WRITE_ENABLE_p1 <= '0';
end if;
if(XPOS_p0 = XMIN_p0 and YPOS_p0 = YMIN_p0) then
R_TOTAL_p1 <= "0000000000000" & R_p0;
G_TOTAL_p1 <= "0000000000000" & G_p0;
B_TOTAL_p1 <= "0000000000000" & B_p0;
else
R_TOTAL_p1 <= std_logic_vector(unsigned(R_TOTAL_p0) + unsigned(R_p0));
G_TOTAL_p1 <= std_logic_vector(unsigned(G_TOTAL_p0) + unsigned(G_p0));
B_TOTAL_p1 <= std_logic_vector(unsigned(B_TOTAL_p0) + unsigned(B_p0));
end if;
if(XPOS_p0 = XMAX_p0 and YPOS_p0 = YMAX_p0) then
SHIFT_p1 <= SHIFT_p0;
else
SHIFT_p1 <= (others => '0');
end if;
WRITE_ADDR_p1 <= WRITE_ADDR_p0;
OUT_ADDR_p1 <= OUT_ADDR_p0;
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
if(CE = '1') then
R_TOTAL_p2 <= std_logic_vector(unsigned(R_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
G_TOTAL_p2 <= std_logic_vector(unsigned(G_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
B_TOTAL_p2 <= std_logic_vector(unsigned(B_TOTAL_p1) srl to_integer(unsigned(SHIFT_p1)));
WRITE_ENABLE_p2 <= WRITE_ENABLE_p1;
WRITE_ADDR_p2 <= WRITE_ADDR_p1;
OUT_ADDR_p2 <= OUT_ADDR_p1;
end if;
end if;
end process;
WRITE_ENABLE <= '1' when WRITE_ENABLE_p2 = '1' and WRITE_CYCLE = '1' else '0';
WRITE_ADDR <= WRITE_ADDR_p2;
WRITE_DATA(20 downto 0) <= R_TOTAL_p2;
WRITE_DATA(41 downto 21) <= G_TOTAL_p2;
WRITE_DATA(62 downto 42) <= B_TOTAL_p2;
WRITE_DATA(65 downto 63) <= OUT_ADDR_p2;
WRITE_DATA(71 downto 66) <= (others => '0');
WRITE_CYCLE <= COUNT(0);
LIGHT_ADDR <= COUNT(8 downto 1);
XPOS <= COUNT(14 downto 9);
CONFIG_ADDR <= "0" & LIGHT_ADDR;
LINE_BUF_ADDR <= YPOS(0) & XPOS;
RESULT_RAM_ADDR <= (not FRAME) & LIGHT_ADDR when WRITE_CYCLE = '0' else (not FRAME) & WRITE_ADDR;
RESULT_RAM_WE(0) <= '0' when WRITE_CYCLE = '0' else WRITE_ENABLE;
RESULT_RAM_D <= WRITE_DATA;
RESULT_RAM_B_ADDR <= FRAME & RESULT_ADDR(7 downto 0);
RESULT_DATA( 7 downto 0) <= RESULT_RAM_B_Q( 7 downto 0);
RESULT_DATA(15 downto 8) <= RESULT_RAM_B_Q(28 downto 21);
RESULT_DATA(23 downto 16) <= RESULT_RAM_B_Q(49 downto 42);
RESULT_DATA(26 downto 24) <= RESULT_RAM_B_Q(65 downto 63);
RESULT_DATA(31 downto 27) <= (others => '0');
end Behavioral;
| gpl-2.0 | 105bc91767a9e8b27f717ebf31b8eb1b | 0.62223 | 2.911046 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/simulation/bmg_stim_gen.vhd | 1 | 7,815 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC : STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND : STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(9 DOWNTO 0) <= WRITE_ADDR(9 DOWNTO 0);
READ_ADDR_INT(9 DOWNTO 0) <= READ_ADDR(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 1024 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 16,
DOUT_WIDTH => 16,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
ENA <= DO_READ OR DO_WRITE ;
WEA <= IF_THEN_ELSE(DO_WRITE='1', WEA_VCC,WEA_GND) ;
END ARCHITECTURE;
| bsd-3-clause | 485f6fd5ad4541858fdfe8ad48996f77 | 0.556494 | 3.759019 | false | false | false | false |
peteut/nvc | test/regress/textio4.vhd | 1 | 4,210 | entity textio4 is
end entity;
use std.textio.all;
architecture test of textio4 is
begin
check_int: process is
variable l : line;
variable x : integer;
variable good : boolean;
variable c : character;
begin
l := new string'(" 123,5");
read(l, x, good);
assert good;
assert x = 123;
assert l.all(1) = ',';
read(l, x, good);
assert not good;
assert l.all(1) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(1) = '5';
read(l, x, good);
assert good;
assert x = 5;
assert l.all'length = 0;
report "Negative integers";
l := new string'(" -123,-5");
read(l, x, good);
assert good;
assert x = -123;
assert l.all(1) = ',';
read(l, x, good);
assert not good;
assert l.all(1) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(1) = '-';
read(l, x, good);
assert good;
assert x = -5;
assert l.all'length = 0;
report "Integers min and max";
l := new string'(integer'image(integer'low) & "," & integer'image(integer'high));
read(l, x, good);
assert good;
assert x = integer'low;
read(l, c, good);
assert good;
read(l, x, good);
assert good;
assert x = integer'high;
assert l.all'length = 0;
report "Negative integer not good with single minus";
l := new string'("-,100");
read(l, x, good);
assert not good;
assert l.all(1) = '-';
read(l, c, good);
assert good;
assert c = '-';
read(l, c, good);
assert good;
assert c = ',';
read(l, x, good);
assert good;
assert x = 100;
assert l.all'length = 0;
report "Negative integer with minus in the middle";
l := new string'("10-10");
read(l, x, good);
assert good;
assert x = 10;
read(l, x, good);
assert good;
assert x = -10;
assert l.all'length = 0;
wait;
end process;
check_bool: process is
variable l : line;
variable x : boolean;
variable good : boolean;
variable c : character;
begin
l := new string'(" true,false");
read(l, x, good);
assert good;
assert x = true;
assert l.all(1) = ',';
read(l, x, good);
assert not good;
assert l.all(1) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(1) = 'f';
read(l, x, good);
assert good;
assert x = false;
assert l.all'length = 0;
wait;
end process;
check_real: process is
variable l : line;
variable x : real;
variable good : boolean;
variable c : character;
begin
l := new string'(" 5.152,61.4,5.");
read(l, x, good);
assert good;
assert x > 5.151 and x < 5.153;
assert l.all(1) = ',';
read(l, x, good);
assert not good;
assert l.all(1) = ',';
read(l, c, good);
assert good;
assert c = ',';
assert l.all(1) = '6';
read(l, x, good);
assert good;
assert x > 61.39 and x < 61.41;
read(l, c, good);
assert good;
assert c = ',';
assert l.all(1) = '5';
read(l, x, good);
assert not good;
wait;
end process;
check_bit_vector: process is
variable l : line;
variable x : bit_vector(1 to 4);
variable good : boolean;
variable c : character;
begin
l := new string'(" 1010 110 11111");
read(l, x, good);
assert good;
assert x = "1010";
assert l.all(1) = ' ';
read(l, x, good);
assert not good;
assert l.all(1) = ' ';
read(l, x, good);
assert good;
assert x = "1111";
assert l.all(1) = '1';
wait;
end process;
end architecture;
| gpl-3.0 | c61960c528ee4b9d2f76364bcbad94f4 | 0.462945 | 3.712522 | false | false | false | false |
olgirard/openmsp430 | core/synthesis/xilinx/src/coregen/spartan3adsp_dmem.vhd | 1 | 5,204 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file spartan3adsp_dmem.vhd when simulating
-- the core, spartan3adsp_dmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY spartan3adsp_dmem IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END spartan3adsp_dmem;
ARCHITECTURE spartan3adsp_dmem_a OF spartan3adsp_dmem IS
-- synthesis translate_off
component wrapped_spartan3adsp_dmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_spartan3adsp_dmem use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3adsp",
c_write_depth_b => 1024,
c_write_depth_a => 1024,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 10,
c_addrb_width => 10,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 1024,
c_read_depth_a => 1024,
c_byte_size => 8,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 2,
c_has_enb => 0,
c_web_width => 2,
c_has_ena => 1,
c_use_byte_web => 1,
c_use_byte_wea => 1,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_spartan3adsp_dmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END spartan3adsp_dmem_a;
| bsd-3-clause | 60211410e6fca59d0dc828603fe77f15 | 0.563989 | 3.6934 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/debounce.vhd | 2 | 10,586 | -------------------------------------------------------------------------------
-- debounce.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: debounce.vhd
-- Version: v1.01.b
-- Description:
-- This file implements a simple debounce (inertial delay)
-- filter to remove short glitches from a signal based upon
-- using user definable delay parameters. It accepts a "Stable"
-- signal which allows the filter to dynamically stretch its
-- delay based on whether another signal is Stable or not. If
-- the filter has detected a change on is "Noisy" input then it
-- will signal its output is "unstable". That can be cross
-- coupled into the "Stable" input of another filter if
-- necessary.
-- Notes:
-- 1) A default assignment based on the generic C_DEFAULT is made for the flip
-- flop output of the delay logic when C_INERTIAL_DELAY > 0. Otherwise, the
-- logic is free running and no reset is possible.
-- 2) A C_INERTIAL_DELAY value of 0 eliminates the debounce logic and connects
-- input to output directly.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613486
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_INERTIAL_DELAY -- Filtering delay
-- C_DEFAULT -- User logic high address
-- Definition of Ports:
-- Sysclk -- System clock
-- Stable -- IIC signal is Stable
-- Unstable_n -- IIC signal is unstable
-- Noisy -- IIC signal is Noisy
-- Clean -- IIC signal is Clean
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity debounce is
generic (
C_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_DEFAULT : std_logic := '1'
);
port (
Sysclk : in std_logic;
Rst : in std_logic;
Stable : in std_logic;
Unstable_n : out std_logic;
Noisy : in std_logic;
Clean : out std_logic);
end entity debounce;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of debounce is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- XST proceses default assignments for configuration purposes
signal clean_cs : std_logic := C_DEFAULT;
signal stable_cs : std_logic := '1';
signal debounce_ct : integer range 0 to 255;
signal Noisy_d1 : std_logic := '1';
signal Noisy_d2 : std_logic := '1';
begin
----------------------------------------------------------------------------
-- Input Registers Process
-- This process samples the incoming SDA and SCL with the system clock
----------------------------------------------------------------------------
-- INPUT_DOUBLE_REGS : process(Sysclk)
-- begin
-- if Sysclk'event and Sysclk = '1' then
-- Noisy_d1 <= Noisy;
-- Noisy_d2 <= Noisy_d1; -- double buffer async input
-- end if;
-- end process INPUT_DOUBLE_REGS;
INPUT_DOUBLE_REGS : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 4
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Noisy,
prmry_vect_in => (others => '0'),
scndry_aclk => Sysclk,
scndry_resetn => '0',
scndry_out => Noisy_d2,
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- GEN_INERTIAL : Generate when C_INERTIAL_DELAY > 0
----------------------------------------------------------------------------
GEN_INERTIAL : if (C_INERTIAL_DELAY > 0) generate
----------------------------------------------------------------------------
-- GEN_INERTIAL : C_INERTIAL_DELAY > 0
-- Inertial delay filters out pulses that are smaller in width then the
-- specified delay. If the C_INERTIAL_DELAY is 0 then the input is passed
-- directly to the "Clean" output signal.
----------------------------------------------------------------------------
INRTL_PROCESS : process (Sysclk) is
begin
if ((rising_edge(Sysclk))) then
if Rst = '1' then
clean_cs <= C_DEFAULT;
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
elsif (clean_cs = Noisy_d2) then
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
else
if (debounce_ct > 0) then
debounce_ct <= debounce_ct - 1;
Unstable_n <= '0';
else
if Stable = '1' then
clean_cs <= Noisy_d2;
debounce_ct <= C_INERTIAL_DELAY ;
Unstable_n <= '1';
end if;
end if;
end if;
end if;
end process INRTL_PROCESS;
s0 : Clean <= clean_cs;
end generate GEN_INERTIAL;
----------------------------------------------------------------------------
-- NO_INERTIAL : C_INERTIAL_DELAY = 0
-- No inertial delay means output is always Stable
----------------------------------------------------------------------------
NO_INERTIAL : if (C_INERTIAL_DELAY = 0) generate
s0 : Clean <= Noisy_d2;
s1 : Unstable_n <= '1';
end generate NO_INERTIAL;
end architecture RTL;
| gpl-3.0 | 3abb0c712c5a21a5fe105c78d0113e28 | 0.41895 | 5.106609 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_rng.vhd | 1 | 3,920 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY k7_prime_fifo_plain_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF k7_prime_fifo_plain_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | f10516c29b5ef7e59d40a633e7ce9f86 | 0.638776 | 4.317181 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/v6abb64Package_efifo_elink.vhd | 1 | 43,647 | -- -------------------------------------------------------------
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- Nov 2008 --> 64-bit
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
package abb64Package is
-- Implemet a design with only one FIFO and only one BRAM Module: For Loopback Test!!
constant USE_LOOPBACK_TEST : boolean := false;
-- Declare constants
-- ----------------------------------------------------------------------
-- Address definitions
-- The 2 MSB's are for Addressing, i.e.
--
-- 0x0000 : Design ID
-- 0x0008 : Interrupt status
-- 0x0010 : Interrupt enable
-- 0x0018 : General error
-- 0x0020 : General status
-- 0x0028 : General control
-- 0x002C ~ 0x004C: DMA upstream registers
-- 0x0050 ~ 0x0070: DMA upstream registers
-- 0x0074 : MRd channel control
-- 0x0078 : CplD channel control
-- 0x007C : ICAP input/output
-- 0x0080 ~ 0x008C: Interrupt Generator (IG) registers
-- 0x4010 : TxFIFO write port
-- 0x4018 : W - TxFIFO Reset
-- : R - TxFIFO Vacancy status
-- 0x4020 : RxFIFO read port
-- 0x4028 : W - RxFIFO Reset
-- : R - RxFIFO Occupancy status
-- 0x8000 ~ 0xBFFF: BRAM space (BAR1)
-- Others : Reserved
------------------------------------------------------------------------
-- Global Constants
--
--- Number of Lanes for PCIe, 1, 4 or 8
Constant C_NUM_PCIE_LANES : integer := 1;
--- Data bus width
Constant C_DBUS_WIDTH : integer := 64;
--- Event Buffer: FIFO Data Count width
Constant C_FIFO_DC_WIDTH : integer := 26;
--- Small BRAM FIFO for emulation
Constant C_EMU_FIFO_DC_WIDTH : integer := 15; --S 14 x fifo originale ; 15 x fifo grande!!
--- Address width for endpoint device/peripheral
--
Constant C_EP_AWIDTH : integer range 10 to 30
:= 16;
--- Buffer width from the PCIe Core
Constant C_TBUF_AWIDTH : integer := 6; -- 4; -- 5;
--- Width for Tx output Arbitration
Constant C_ARBITRATE_WIDTH : integer := 4;
--- Number of BAR spaces
Constant CINT_BAR_SPACES : integer := 4;
--- Max BAR number, 7
Constant C_BAR_NUMBER : integer := 7;
--- Encoded BAR number takes 3 bits to represent 0~6. 7 means invalid or don't care
Constant C_ENCODE_BAR_NUMBER : integer := 3;
--- Number of Channels, currently 4: Interrupt, PIO MRd, upstream DMA, downstream DMA
Constant C_CHANNEL_NUMBER : integer := 4;
--- Data width of the channel buffers (FIFOs)
Constant C_CHANNEL_BUF_WIDTH : integer := 128;
--- Higher 4 bits are for tag decoding
Constant C_TAG_DECODE_BITS : integer := 4;
--- DDR SDRAM bank address pin number
Constant C_DDR_BANK_AWIDTH : integer := 2;
--- DDR SDRAM address pin number
Constant C_DDR_AWIDTH : integer := 13;
--- DDR SDRAM data pin number
Constant C_DDR_DWIDTH : integer := 16;
--- DDR SDRAM module address width, dependent on total DDR memory capacity.
-- 128 Mb= 16MB : 24
-- 256 Mb= 32MB : 25
-- 512 Mb= 64MB : 26
-- 1024 Mb= 128MB : 27
-- 2048 Mb= 256MB : 28
Constant C_DDR_IAWIDTH : integer range 24 to 28
:= 26;
--- Block RAM address bus width. Variation requires BRAM core regeneration.
Constant C_PRAM_AWIDTH : integer range 8 to 28
:= 12;
--- Width for Interrupt generation counter
Constant C_CNT_GINT_WIDTH : integer := 30;
-- --- Emulation FIFOs' address width
-- Constant C_FIFO_AWIDTH : integer := 5;
--- Tag RAM data bus width, 1 bit for AInc information and 3 bits for BAR number
Constant C_TAGRAM_DWIDTH : integer := 36;
--- Configuration command width, e.g. cfg_dcommand, cfg_lcommand.
Constant C_CFG_COMMAND_DWIDTH : integer := 16;
--- Tag RAM address bus width, only 6 bits (of 8) are used for MRd from DMA Write Channel
Constant C_TAGRAM_AWIDTH : integer := 6;
Constant C_TAG_MAP_WIDTH : integer := 64; -- 2^C_TAGRAM_AWIDTH
-- TAG map are partitioned into sub-parts
Constant C_SUB_TAG_MAP_WIDTH : integer := 8;
--- Address_Increment bit is put in tag RAM
Constant CBIT_AINC_IN_TAGRAM : integer := C_TAGRAM_DWIDTH-1;
-- Bit range of BAR field in TAG ram
Constant C_TAGBAR_BIT_TOP : integer := CBIT_AINC_IN_TAGRAM-1;
Constant C_TAGBAR_BIT_BOT : integer := C_TAGBAR_BIT_TOP-C_ENCODE_BAR_NUMBER+1;
--- Number of bits for Last DW BE and 1st DW BE in the header of a TLP
Constant C_BE_WIDTH : integer := 4;
--- ICAP width: 8 or 32.
Constant C_ICAP_WIDTH : integer := 32;
--- Feature Bits width
Constant C_FEAT_BITS_WIDTH : integer := 8;
--- Channel lables
Constant C_CHAN_INDEX_IRPT : integer := 3;
Constant C_CHAN_INDEX_MRD : integer := 2;
Constant C_CHAN_INDEX_DMA_DS : integer := 1;
Constant C_CHAN_INDEX_DMA_US : integer := 0;
------------------------------------------------------------------------
-- Bit ranges
-- Bits range for Max_Read_Request_Size in cfg_dcommand
Constant C_CFG_MRS_BIT_TOP : integer := 14;
Constant C_CFG_MRS_BIT_BOT : integer := 12;
-- Bits range for Max_Payload_Size in cfg_dcommand
Constant C_CFG_MPS_BIT_TOP : integer := 7;
Constant C_CFG_MPS_BIT_BOT : integer := 5;
-- The bit in minimum Max_Read_Request_Size/Max_Payload_Size that is one
-- i.e. 0x80 Bytes = 0x20 DW = "000000100000"
Constant CBIT_SENSE_OF_MAXSIZE : integer := 5;
-- ------------------------------------------------------------------------
--
-- Section for TLP headers' bit definition
-- ( not shown in user header file)
--
-- ------------------------------------------------------------------------
-- -- The bit in TLP header #0 that means whether the TLP comes with data
-- Constant CBIT_TLP_HAS_PAYLOAD : integer := 30;
-- -- The bit in TLP header #0 that means whether the TLP has 4-DW header
-- Constant CBIT_TLP_HAS_4DW_HEAD : integer := 29;
-- -- The bit in TLP header #0 that means Cpl/CplD
-- Constant C_TLP_CPLD_BIT : integer := 27;
-- The bit in TLP header #0 that means TLP Digest
Constant C_TLP_TD_BIT : integer := 15 +32;
-- The bit in TLP header #0 that means Error Poison
Constant C_TLP_EP_BIT : integer := 14 +32;
-- Bit range of Format field in TLP header #0
Constant C_TLP_FMT_BIT_TOP : integer := 30 +32; -- TLP has payload
Constant C_TLP_FMT_BIT_BOT : integer := 29 +32; -- TLP header has 4 DW
-- Bit range of Type field in TLP header #0
Constant C_TLP_TYPE_BIT_TOP : integer := 28 +32;
Constant C_TLP_TYPE_BIT_BOT : integer := 24 +32;
-- Bit range of TC field in TLP header #0
Constant C_TLP_TC_BIT_TOP : integer := 22 +32;
Constant C_TLP_TC_BIT_BOT : integer := 20 +32;
-- Bit range of Attribute field in TLP header #0
Constant C_TLP_ATTR_BIT_TOP : integer := 13 +32;
Constant C_TLP_ATTR_BIT_BOT : integer := 12 +32;
-- Bit range of Length field in TLP header #0
Constant C_TLP_LENG_BIT_TOP : integer := 9 +32;
Constant C_TLP_LENG_BIT_BOT : integer := 0 +32;
-- Bit range of Requester ID field in header #1 of non-Cpl/D TLP
Constant C_TLP_REQID_BIT_TOP : integer := 31;
Constant C_TLP_REQID_BIT_BOT : integer := 16;
-- Bit range of Tag field in header #1 of non-Cpl/D TLP
Constant C_TLP_TAG_BIT_TOP : integer := 15;
Constant C_TLP_TAG_BIT_BOT : integer := 8;
-- Bit range of Last BE field in TLP header #1
Constant C_TLP_LAST_BE_BIT_TOP : integer := 7;
Constant C_TLP_LAST_BE_BIT_BOT : integer := 4;
-- Bit range of 1st BE field in TLP header #1
Constant C_TLP_1ST_BE_BIT_TOP : integer := 3;
Constant C_TLP_1ST_BE_BIT_BOT : integer := 0;
-- Bit range of Completion Status field in Cpl/D TLP header #1
Constant C_CPLD_CS_BIT_TOP : integer := 15;
Constant C_CPLD_CS_BIT_BOT : integer := 13;
-- Bit range of Completion Byte Count field in Cpl/D TLP header #1
Constant C_CPLD_BC_BIT_TOP : integer := 11;
Constant C_CPLD_BC_BIT_BOT : integer := 0;
-- Bit range of Completer ID field in header#1 of Cpl/D TLP
Constant C_CPLD_CPLT_ID_BIT_TOP : integer := C_TLP_REQID_BIT_TOP;
Constant C_CPLD_CPLT_ID_BIT_BOT : integer := C_TLP_REQID_BIT_BOT;
-- Bit range of Requester ID field in header#2 of Cpl/D TLP
Constant C_CPLD_REQID_BIT_TOP : integer := 31 +32;
Constant C_CPLD_REQID_BIT_BOT : integer := 16 +32;
-- Bit range of Completion Tag field in Cpl/D TLP 3rd header
Constant C_CPLD_TAG_BIT_TOP : integer := C_TLP_TAG_BIT_TOP +32;
Constant C_CPLD_TAG_BIT_BOT : integer := C_TLP_TAG_BIT_BOT +32;
-- Bit range of Completion Lower Address field in Cpl/D TLP 3rd header
Constant C_CPLD_LA_BIT_TOP : integer := 6 +32;
Constant C_CPLD_LA_BIT_BOT : integer := 0 +32;
-- Bit range of Message Code field in Msg 2nd header
Constant C_MSG_CODE_BIT_TOP : integer := 7;
Constant C_MSG_CODE_BIT_BOT : integer := 0;
-- ----------------------------------------------------------------------
-- TLP field widths
-- For PCIe, the length field is 10 bits wide.
Constant C_TLP_FLD_WIDTH_OF_LENG : integer
:= C_TLP_LENG_BIT_TOP-C_TLP_LENG_BIT_BOT+1;
------------------------------------------------------------------------
--- Tag width in TLP
Constant C_TAG_WIDTH : integer
:= C_TLP_TAG_BIT_TOP-C_TLP_TAG_BIT_BOT+1;
------------------------------------------------------------------------
--- Width for Local ID
Constant C_ID_WIDTH : integer
:= C_TLP_REQID_BIT_TOP-C_TLP_REQID_BIT_BOT+1;
------------------------------------------------------------------------
--- Width for Requester ID
Constant C_REQID_WIDTH : integer
:= C_TLP_REQID_BIT_TOP-C_TLP_REQID_BIT_BOT+1;
-- ------------------------------------------------------------------------
-- Section for Channel Buffer bit definition, referenced to TLP header definition
-- ( not shown in user header file)
--
-- ------------------------------------------------------------------------
-- Bit range of Length field in Channel Buffer word
Constant C_CHBUF_LENG_BIT_BOT : integer := 0;
Constant C_CHBUF_LENG_BIT_TOP : integer := C_CHBUF_LENG_BIT_BOT+C_TLP_FLD_WIDTH_OF_LENG-1; -- 9
-- Bit range of Attribute field in Channel Buffer word
Constant C_CHBUF_ATTR_BIT_BOT : integer := C_CHBUF_LENG_BIT_TOP+1; --10;
Constant C_CHBUF_ATTR_BIT_TOP : integer := C_CHBUF_ATTR_BIT_BOT+C_TLP_ATTR_BIT_TOP-C_TLP_ATTR_BIT_BOT; --11;
-- The bit in Channel Buffer word that means Error Poison
Constant C_CHBUF_EP_BIT : integer := C_CHBUF_ATTR_BIT_TOP+1; --12;
-- The bit in Channel Buffer word that means TLP Digest
Constant C_CHBUF_TD_BIT : integer := C_CHBUF_EP_BIT+1; --13;
-- Bit range of TC field in Channel Buffer word
Constant C_CHBUF_TC_BIT_BOT : integer := C_CHBUF_TD_BIT+1; --14;
Constant C_CHBUF_TC_BIT_TOP : integer := C_CHBUF_TC_BIT_BOT+C_TLP_TC_BIT_TOP-C_TLP_TC_BIT_BOT; --16;
-- Bit range of Format field in Channel Buffer word
Constant C_CHBUF_FMT_BIT_BOT : integer := C_CHBUF_TC_BIT_TOP+1; --17;
Constant C_CHBUF_FMT_BIT_TOP : integer := C_CHBUF_FMT_BIT_BOT+C_TLP_FMT_BIT_TOP-C_TLP_FMT_BIT_BOT; --18;
-- Bit range of Tag field in Channel Buffer word except Cpl/D
Constant C_CHBUF_TAG_BIT_BOT : integer := C_CHBUF_FMT_BIT_TOP+1; --19;
Constant C_CHBUF_TAG_BIT_TOP : integer := C_CHBUF_TAG_BIT_BOT+C_TLP_TAG_BIT_TOP-C_TLP_TAG_BIT_BOT; --26;
-- Bit range of BAR Index field in upstream DMA Channel Buffer word
Constant C_CHBUF_DMA_BAR_BIT_BOT : integer := C_CHBUF_TAG_BIT_TOP+1; --27;
Constant C_CHBUF_DMA_BAR_BIT_TOP : integer := C_CHBUF_DMA_BAR_BIT_BOT+C_ENCODE_BAR_NUMBER-1; --29;
-- Bit range of Message Code field in Channel Buffer word for Msg
Constant C_CHBUF_MSG_CODE_BIT_BOT : integer := C_CHBUF_TAG_BIT_TOP+1; --27;
Constant C_CHBUF_MSG_CODE_BIT_TOP : integer := C_CHBUF_MSG_CODE_BIT_BOT+C_MSG_CODE_BIT_TOP-C_MSG_CODE_BIT_BOT; --34;
-- Bit range of remaining Byte Count field in Cpl/D Channel Buffer word
Constant C_CHBUF_CPLD_BC_BIT_BOT : integer := C_CHBUF_FMT_BIT_TOP+1; --19;
Constant C_CHBUF_CPLD_BC_BIT_TOP : integer := C_CHBUF_CPLD_BC_BIT_BOT+C_TLP_FLD_WIDTH_OF_LENG-1+2; --30;
-- Bit range of Completion Status field in Cpl/D Channel Buffer word
Constant C_CHBUF_CPLD_CS_BIT_BOT : integer := C_CHBUF_CPLD_BC_BIT_TOP+1; --31;
Constant C_CHBUF_CPLD_CS_BIT_TOP : integer := C_CHBUF_CPLD_CS_BIT_BOT+C_CPLD_CS_BIT_TOP-C_CPLD_CS_BIT_BOT; --33;
-- Bit range of Lower Address field in Cpl/D Channel Buffer word
Constant C_CHBUF_CPLD_LA_BIT_BOT : integer := C_CHBUF_CPLD_CS_BIT_TOP+1; --34;
Constant C_CHBUF_CPLD_LA_BIT_TOP : integer := C_CHBUF_CPLD_LA_BIT_BOT+C_CPLD_LA_BIT_TOP-C_CPLD_LA_BIT_BOT; --40;
-- Bit range of Tag field in Cpl/D Channel Buffer word
Constant C_CHBUF_CPLD_TAG_BIT_BOT : integer := C_CHBUF_CPLD_LA_BIT_TOP+1; --41;
Constant C_CHBUF_CPLD_TAG_BIT_TOP : integer := C_CHBUF_CPLD_TAG_BIT_BOT+C_CPLD_TAG_BIT_TOP-C_CPLD_TAG_BIT_BOT; --48;
-- Bit range of Requester ID field in Cpl/D Channel Buffer word
Constant C_CHBUF_CPLD_REQID_BIT_BOT : integer := C_CHBUF_CPLD_TAG_BIT_TOP+1; --49;
Constant C_CHBUF_CPLD_REQID_BIT_TOP : integer := C_CHBUF_CPLD_REQID_BIT_BOT+C_CPLD_REQID_BIT_TOP-C_CPLD_REQID_BIT_BOT; --64;
-- Bit range of BAR Index field in Cpl/D Channel Buffer word
Constant C_CHBUF_CPLD_BAR_BIT_BOT : integer := C_CHBUF_CPLD_REQID_BIT_TOP+1; --65;
Constant C_CHBUF_CPLD_BAR_BIT_TOP : integer := C_CHBUF_CPLD_BAR_BIT_BOT+C_ENCODE_BAR_NUMBER-1; --67;
-- Bit range of host address in Channel Buffer word
Constant C_CHBUF_HA_BIT_BOT : integer := C_CHBUF_DMA_BAR_BIT_TOP+1; --30;
-- Constant C_CHBUF_HA_BIT_TOP : integer := C_CHBUF_HA_BIT_BOT+2*C_DBUS_WIDTH-1; --93;
Constant C_CHBUF_HA_BIT_TOP : integer := C_CHBUF_HA_BIT_BOT+C_DBUS_WIDTH-1; --93;
-- The bit in Channel Buffer word that means whether this TLP is valid for output arbitration
-- (against channel buffer reset during arbitration)
Constant C_CHBUF_QVALID_BIT : integer := C_CHBUF_HA_BIT_TOP+1; --94;
-- The bit in Channel Buffer word that means address increment
Constant C_CHBUF_AINC_BIT : integer := C_CHBUF_QVALID_BIT+1; --95;
-- The bit in Channel Buffer word that means zero-length
Constant C_CHBUF_0LENG_BIT : integer := C_CHBUF_AINC_BIT+1; --96;
-- Bit range of peripheral address in Channel Buffer word
Constant C_CHBUF_PA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_EP_AWIDTH; --112;
Constant C_CHBUF_PA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of BRAM address in Channel Buffer word
Constant C_CHBUF_MA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_PRAM_AWIDTH-2; --114;
Constant C_CHBUF_MA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
-- Bit range of DDR address in Channel Buffer word
Constant C_CHBUF_DDA_BIT_BOT : integer := C_CHANNEL_BUF_WIDTH-C_DDR_IAWIDTH; --102;
Constant C_CHBUF_DDA_BIT_TOP : integer := C_CHANNEL_BUF_WIDTH-1; --127;
------------------------------------------------------------------------
-- The Relaxed Ordering bit constant in TLP
Constant C_RELAXED_ORDERING : std_logic
:= '0';
-- The NO SNOOP bit constant in TLP
Constant C_NO_SNOOP : std_logic
:= '0'; -- '1';
-- AK, 2007-11-07: SNOOP-bit corrupts DMA, if set on INTEL platform. Seems to be don't care on AMD
------------------------------------------------------------------------
-- TLP resolution concerning Format
Constant C_FMT3_NO_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
:= "00";
Constant C_FMT3_WITH_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
:= "10";
Constant C_FMT4_NO_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
:= "01";
Constant C_FMT4_WITH_DATA : std_logic_vector(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT)
:= "11";
-- TLP resolution concerning Type
Constant C_TYPE_MEM_REQ : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "00000";
Constant C_TYPE_IO_REQ : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "00010";
Constant C_TYPE_MEM_REQ_LK : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "00001";
Constant C_TYPE_COMPLETION : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "01010";
Constant C_TYPE_COMPLETION_LK : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "01011";
Constant C_TYPE_MSG_TO_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "10000";
Constant C_TYPE_MSG_BY_ADDRESS : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "10001";
Constant C_TYPE_MSG_BY_ID : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "10010";
Constant C_TYPE_MSG_FROM_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "10011";
Constant C_TYPE_MSG_LOCAL : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "10100";
Constant C_TYPE_MSG_GATHER_TO_ROOT : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= "10101";
-- Select this constant to test system response
Constant C_TYPE_OF_MSG : std_logic_vector(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT)
:= C_TYPE_MSG_LOCAL; -- C_TYPE_MSG_TO_ROOT;
------------------------------------------------------------------------
-- Lowest priority for Tx_Output_Arbitration module
Constant C_LOWEST_PRIORITY : std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0)
:= (0=>'1', OTHERS=>'0');
------------------------------------------------------------------------
Constant C_DECODE_BIT_TOP : integer := C_EP_AWIDTH-1; -- 15;
Constant C_DECODE_BIT_BOT : integer := C_DECODE_BIT_TOP-1; -- 14;
------------------------------------------------------------------------
-- Current buffer descriptor length is 8 DW.
Constant C_NEXT_BD_LENGTH : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
:= CONV_STD_LOGIC_VECTOR(8*4, C_TLP_FLD_WIDTH_OF_LENG+2);
-- Maximum 8 DW for the CplD carrying next BDA
Constant C_NEXT_BD_LENG_MSB : integer := 3;
------------------------------------------------------------------------
-- To determine the max.size parameters, 6 bits are used.
Constant C_MAXSIZE_FLD_BIT_TOP : integer := C_TLP_FLD_WIDTH_OF_LENG +2;
Constant C_MAXSIZE_FLD_BIT_BOT : integer := 7;
-- DDR commands: RASn-CASn-WEn
Constant CMD_NOP : std_logic_vector(2 downto 0) := "111";
Constant CMD_LMR : std_logic_vector(2 downto 0) := "000";
Constant CMD_ACT : std_logic_vector(2 downto 0) := "011";
Constant CMD_READ : std_logic_vector(2 downto 0) := "101";
Constant CMD_WRITE : std_logic_vector(2 downto 0) := "100";
Constant CMD_PRECH : std_logic_vector(2 downto 0) := "010";
Constant CMD_BTERM : std_logic_vector(2 downto 0) := "110";
Constant CMD_AREF : std_logic_vector(2 downto 0) := "001";
------------------------------------------------------------------------
-- Time-out counter width
Constant C_TOUT_WIDTH : integer := 32;
-- Bottom bit for determining time-out
Constant CBIT_TOUT_BOT : integer := 16;
-- Time-out value
Constant C_TIME_OUT_VALUE : std_logic_vector(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT)
-- := (OTHERS=>'1' ); -- Maximum value (-1)
:= (24=>'1', OTHERS=>'0' );
----------------------------------------------------------------------------------
Constant C_REGS_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0)
:= (C_DECODE_BIT_TOP => '0'
, C_DECODE_BIT_BOT => '0'
, OTHERS => '0' );
Constant C_BRAM_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0)
:= (C_DECODE_BIT_TOP => '1'
, C_DECODE_BIT_BOT => '0'
, OTHERS => '0' );
Constant C_FIFO_BASE_ADDR : std_logic_vector(C_EP_AWIDTH-1 downto 0)
:= (C_DECODE_BIT_TOP => '0'
, C_DECODE_BIT_BOT => '0'
, OTHERS => '0' );
----------------------------------------------------------------------------------
-- Constant CINT_ADDR_TXFIFO_DATA : integer := 4;
-- Constant CINT_ADDR_TXFIFO_CTRL : integer := 6;
-- Constant CINT_ADDR_TXFIFO_STA : integer := 6;
--
-- Constant CINT_ADDR_RXFIFO_DATA : integer := 8;
-- Constant CINT_ADDR_RXFIFO_CTRL : integer := 10;
-- Constant CINT_ADDR_RXFIFO_STA : integer := 10;
Constant CINT_REGS_SPACE_BAR : integer := 0;
Constant CINT_FIFO_SPACE_BAR : integer := 2;
Constant CINT_BRAM_SPACE_BAR : integer := 3;
Constant CINT_DDR_SPACE_BAR : integer := 1;
------------------------------------------------------------------------
-- -- Default channel buffer word for CplD
-- Constant C_DEF_CPLD_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- :=X"CA000000";
----------------------------------------------------------------------------------
-- 1st word of MRd, for requesting the next descriptor
-- Constant C_MRD_HEAD0_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- := X"80000000";
Constant C_TLP_HAS_DATA : std_logic
:= '1';
Constant C_TLP_HAS_NO_DATA : std_logic
:= '0';
Constant C_TLP_3DW_HEADER : std_logic
:= '0';
Constant C_TLP_4DW_HEADER : std_logic
:= '1';
------------------------------------------------------------------------
Constant C_TLP_TYPE_IS_MRD_H3 : std_logic_vector(3 downto 0)
:= "1000";
Constant C_TLP_TYPE_IS_MRDLK_H3 : std_logic_vector(3 downto 0)
:= "0100";
Constant C_TLP_TYPE_IS_MRD_H4 : std_logic_vector(3 downto 0)
:= "0010";
Constant C_TLP_TYPE_IS_MRDLK_H4 : std_logic_vector(3 downto 0)
:= "0001";
Constant C_TLP_TYPE_IS_MWR_H3 : std_logic_vector(1 downto 0)
:= "10";
Constant C_TLP_TYPE_IS_MWR_H4 : std_logic_vector(1 downto 0)
:= "01";
Constant C_TLP_TYPE_IS_CPLD : std_logic_vector(3 downto 0)
:= "1000";
Constant C_TLP_TYPE_IS_CPL : std_logic_vector(3 downto 0)
:= "0100";
Constant C_TLP_TYPE_IS_CPLDLK : std_logic_vector(3 downto 0)
:= "0010";
Constant C_TLP_TYPE_IS_CPLLK : std_logic_vector(3 downto 0)
:= "0001";
------------------------------------------------------------------------
-- Maximal number of Interrupts
Constant C_NUM_OF_INTERRUPTS : integer := 16;
------------------------------------------------------------------------
-- Minimal register set
Constant CINT_ADDR_VERSION : integer := 0;
Constant CINT_ADDR_IRQ_STAT : integer := 2;
-- IRQ Enable. Write '1' turns on the interrupt, '0' masks.
Constant CINT_ADDR_IRQ_EN : integer := 4;
Constant CINT_ADDR_ERROR : integer := 6; -- unused
Constant CINT_ADDR_STATUS : integer := 8;
Constant CINT_ADDR_CONTROL : integer := 10;
-- Upstream DMA channel Constants
Constant CINT_ADDR_DMA_US_PAH : integer := 11;
Constant CINT_ADDR_DMA_US_PAL : integer := 12;
Constant CINT_ADDR_DMA_US_HAH : integer := 13;
Constant CINT_ADDR_DMA_US_HAL : integer := 14;
Constant CINT_ADDR_DMA_US_BDAH : integer := 15;
Constant CINT_ADDR_DMA_US_BDAL : integer := 16;
Constant CINT_ADDR_DMA_US_LENG : integer := 17;
Constant CINT_ADDR_DMA_US_CTRL : integer := 18;
Constant CINT_ADDR_DMA_US_STA : integer := 19;
-- Downstream DMA channel Constants
Constant CINT_ADDR_DMA_DS_PAH : integer := 20;
Constant CINT_ADDR_DMA_DS_PAL : integer := 21;
Constant CINT_ADDR_DMA_DS_HAH : integer := 22;
Constant CINT_ADDR_DMA_DS_HAL : integer := 23;
Constant CINT_ADDR_DMA_DS_BDAH : integer := 24;
Constant CINT_ADDR_DMA_DS_BDAL : integer := 25;
Constant CINT_ADDR_DMA_DS_LENG : integer := 26;
Constant CINT_ADDR_DMA_DS_CTRL : integer := 27;
Constant CINT_ADDR_DMA_DS_STA : integer := 28;
-------- Address for MRd channel control
Constant CINT_ADDR_MRD_CTRL : integer := 29;
-------- Address for Tx module control
Constant CINT_ADDR_TX_CTRL : integer := 30;
-------- Address for ICAP access
Constant CINT_ADDR_ICAP : integer := 31;
-------- Address of Interrupt Generator Control (W)
Constant CINT_ADDR_IG_CONTROL : integer := 32;
-------- Address of Interrupt Generator Latency (W+R)
Constant CINT_ADDR_IG_LATENCY : integer := 33;
-------- Address of Interrupt Generator Assert Number (R)
Constant CINT_ADDR_IG_NUM_ASSERT : integer := 34;
-------- Address of Interrupt Generator Deassert Number (R)
Constant CINT_ADDR_IG_NUM_DEASSERT : integer := 35;
-------- Event Buffer FIFO status (R) + control (W)
Constant CINT_ADDR_EB_STACON : integer := 36;
-------- Upstream DMA transferred byte count (R)
Constant CINT_ADDR_US_TRANSF_BC : integer := 37;
-------- Downstream DMA transferred byte count (R)
Constant CINT_ADDR_DS_TRANSF_BC : integer := 38;
-------- DCB protocol link status (R) + control (W)
Constant CINT_ADDR_PROTOCOL_STACON : integer := 39;
-------- CTL class register rx(R) + tx (W)
Constant CINT_ADDR_CTL_CLASS : integer := 40;
-------- DLM class register rx(R) + tx (W)
Constant CINT_ADDR_DLM_CLASS : integer := 41;
-------- Data generator control register (W)
Constant CINT_ADDR_DG_CTRL : integer := 42;
-------- Traffice classes status (R)
Constant CINT_ADDR_TC_STATUS : integer := 43;
-------- SIMONE USER REGISTER 01 rx(R) + tx (W)
Constant CINT_ADDR_REG01 : integer := 44;
-------- SIMONE USER REGISTER 02 rx(R) + tx (W)
Constant CINT_ADDR_REG02 : integer := 45;
-------- SIMONE USER REGISTER 03 rx(R) + tx (W)
Constant CINT_ADDR_REG03 : integer := 46;
-------- SIMONE USER REGISTER 04 rx(R) + tx (W)
Constant CINT_ADDR_REG04 : integer := 47;
-------- SIMONE USER REGISTER 05 rx(R) + tx (W)
Constant CINT_ADDR_REG05 : integer := 48;
-------- SIMONE USER REGISTER 06 rx(R) + tx (W)
Constant CINT_ADDR_REG06 : integer := 49;
-------- SIMONE USER REGISTER 07 rx(R) + tx (W)
Constant CINT_ADDR_REG07 : integer := 50;
-------- SIMONE USER REGISTER 08 rx(R) + tx (W)
Constant CINT_ADDR_REG08 : integer := 51;
-------- SIMONE USER REGISTER 09 rx(R) + tx (W)
Constant CINT_ADDR_REG09 : integer := 52;
-------- SIMONE USER REGISTER 10 rx(R) + tx (W)
Constant CINT_ADDR_REG10 : integer := 53;
-------- Host2Board FIFO status (R)
Constant CINT_ADDR_H2B_STACON : integer := 54;
-------- Board2Host FIFO status (R)
Constant CINT_ADDR_B2H_STACON : integer := 55;
-------- SIMONE USER REGISTER 11 rx(R) + tx (W)
Constant CINT_ADDR_REG11 : integer := 56;
-------- SIMONE USER REGISTER 12 rx(R) + tx (W)
Constant CINT_ADDR_REG12 : integer := 57;
-------- SIMONE USER REGISTER 13 rx(R) + tx (W)
Constant CINT_ADDR_REG13 : integer := 58;
-------- SIMONE USER REGISTER 14 rx(R) + tx (W)
Constant CINT_ADDR_REG14 : integer := 59;
-------- WHW USER REGISTER 15 rx(R) + tx (W)
Constant CINT_ADDR_REG15 : integer := 60;
-------- WHW USER REGISTER 16 rx(R) + tx (W)
Constant CINT_ADDR_REG16 : integer := 61;
-------- WHW USER REGISTER 17 rx(R) + tx (W)
Constant CINT_ADDR_REG17 : integer := 62;
-------- WHW USER REGISTER 18 rx(R) + tx (W)
Constant CINT_ADDR_REG18 : integer := 63;
-------- WHW USER REGISTER 19 rx(R) + tx (W)
Constant CINT_ADDR_REG19 : integer := 64;
-------- WHW USER REGISTER 20 rx(R) + tx (W)
Constant CINT_ADDR_REG20 : integer := 65;
-------- WHW USER REGISTER 20 rx(R) + tx (W)
Constant CINT_ADDR_REG21 : integer := 66;
-------- WHW USER REGISTER 20 rx(R) + tx (W)
Constant CINT_ADDR_REG22 : integer := 67;
-------- WHW USER REGISTER 20 rx(R) + tx (W)
Constant CINT_ADDR_REG23 : integer := 68;
-------- WHW USER REGISTER 20 rx(R) + tx (W)
Constant CINT_ADDR_REG24 : integer := 69;
-------- WHW USER REGISTER 20 rx(R) + tx (W)
Constant CINT_ADDR_REG25 : integer := 70;
------------------------------------------------------------------------
-- Number of registers
Constant C_NUM_OF_ADDRESSES : integer := 71;
--
------------------------------------------------------------------------
-- ----------------------------------------------------------------------
-- Bit definitions of the Control register for DMA channels
--
Constant CINT_BIT_DMA_CTRL_VALID : integer := 25;
Constant CINT_BIT_DMA_CTRL_LAST : integer := 24;
Constant CINT_BIT_DMA_CTRL_UPA : integer := 20;
Constant CINT_BIT_DMA_CTRL_AINC : integer := 15;
Constant CINT_BIT_DMA_CTRL_END : integer := 08;
-- Bit range of BAR field in DMA Control register
Constant CINT_BIT_DMA_CTRL_BAR_TOP : integer := 18;
Constant CINT_BIT_DMA_CTRL_BAR_BOT : integer := 16;
-- Default DMA Control register value
-- Constant C_DEF_DMA_CTRL_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
Constant C_DEF_DMA_CTRL_WORD : std_logic_vector(C_DBUS_WIDTH-1 downto 0)
:= (CINT_BIT_DMA_CTRL_VALID => '1' ,
CINT_BIT_DMA_CTRL_END => '1' ,
OTHERS => '0'
);
------------------------------------------------------------------------
Constant C_CHANNEL_RST_BITS : std_logic_vector(C_FEAT_BITS_WIDTH-1 downto 0)
:= X"0A";
------------------------------------------------------------------------
Constant C_HOST_ICLR_BITS : std_logic_vector(C_FEAT_BITS_WIDTH-1 downto 0)
:= X"F0";
----------------------------------------------------------------------------------
-- Initial MWr Tag for upstream DMA
Constant C_TAG0_DMA_US_MWR : std_logic_vector(C_TAG_WIDTH-1 downto 0)
:= X"D0";
-- Initial MRd Tag for upstream DMA descriptor
Constant C_TAG0_DMA_USB : std_logic_vector(C_TAG_WIDTH-1 downto 0)
:= X"E0";
-- Initial MRd Tag for downstream DMA descriptor
Constant C_TAG0_DMA_DSB : std_logic_vector(C_TAG_WIDTH-1 downto 0)
:= X"C0";
-- Initial Msg Tag Hihger 4 bits for interrupt
Constant C_MSG_TAG_HI : std_logic_vector( 3 downto 0)
:= X"F";
-- Msg code for IntA (fixed by PCIe)
Constant C_MSGCODE_INTA : std_logic_vector( 7 downto 0)
:= X"20";
-- Msg code for #IntA (fixed by PCIe)
Constant C_MSGCODE_INTA_N : std_logic_vector( 7 downto 0)
:= X"24";
----------------------------------------------------------------------------------
-- DMA status bit definition
Constant CINT_BIT_DMA_STAT_NALIGN : integer := 7;
Constant CINT_BIT_DMA_STAT_TIMEOUT : integer := 4;
Constant CINT_BIT_DMA_STAT_BDANULL : integer := 3;
Constant CINT_BIT_DMA_STAT_BUSY : integer := 1;
Constant CINT_BIT_DMA_STAT_DONE : integer := 0;
-- Bit definition in interrup status register (ISR) For Interrupt
Constant CINT_BIT_US_DONE_IN_ISR : integer := 0;
Constant CINT_BIT_DS_DONE_IN_ISR : integer := 1;
Constant CINT_BIT_INTGEN_IN_ISR : integer := 2;
Constant CINT_BIT_DGEN_IN_ISR : integer := 3;
Constant CINT_BIT_USTOUT_IN_ISR : integer := 4;
Constant CINT_BIT_DSTOUT_IN_ISR : integer := 5;
-- Bit definition in interrup status register (ISR) For Polling Statue
Constant CPOLL_BIT_US_DONE_IN_ISR : integer := 0 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DS_DONE_IN_ISR : integer := 1 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_INTGEN_IN_ISR : integer := 2 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DGEN_IN_ISR : integer := 3 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_USTOUT_IN_ISR : integer := 4 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DSTOUT_IN_ISR : integer := 5 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DAQ_IN_ISR : integer := 6 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_CTL_IN_ISR : integer := 7 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DLM_IN_ISR : integer := 8 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DAQTOUT_IN_ISR : integer := 10 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_CTLTOUT_IN_ISR : integer := 11 + C_NUM_OF_INTERRUPTS;
Constant CPOLL_BIT_DLMTOUT_IN_ISR : integer := 12 + C_NUM_OF_INTERRUPTS;
-- The Time-out bits in System Error Register (SER)
Constant CINT_BIT_TX_TOUT_IN_SER : integer := 18;
Constant CINT_BIT_EB_TOUT_IN_SER : integer := 19;
Constant CINT_BIT_EB_OVERWRITTEN : integer := 20;
-- The separate RST bit in DG_CTRL register
Constant CINT_BIT_DG_RST : integer := 12;
-- The MASK bit in DG_CTRL register
Constant CINT_BIT_DG_MASK : integer := 8;
-- The BUSY bit in DG_CTRL register
Constant CINT_BIT_DG_BUSY : integer := 1;
-- The AVAIL bit in DG_CTRL register
Constant CINT_BIT_DG_AVAIL : integer := 0;
-- Bit definition of msg routing method in General Control Register (GCR)
Constant C_GCR_MSG_ROUT_BIT_BOT : integer := 0;
Constant C_GCR_MSG_ROUT_BIT_TOP : integer := 2;
-- Bit definition of ICAP Busy in global status register (GSR)
Constant CINT_BIT_ICAP_BUSY_IN_GSR : integer := 4;
-- Bit definition of Data Generator available in global status register (GSR)
Constant CINT_BIT_DG_AVAIL_IN_GSR : integer := 5;
-- Bit definition of DCB link_active in global status register (GSR)
Constant CINT_BIT_LINK_ACT_IN_GSR : integer := 6;
-- Bit range of link width in GSR
Constant CINT_BIT_LWIDTH_IN_GSR_BOT : integer := 10; -- 16;
Constant CINT_BIT_LWIDTH_IN_GSR_TOP : integer := 15; -- 21;
----------------------------------------------------------------------------------
-- Carry bit, only for better timing, used to divide 32-bit add into 2 stages
Constant CBIT_CARRY : integer := 16;
----------------------------------------------------------------------------------
-- Zero and -1 constants for different dimensions
--
Constant C_ALL_ZEROS : std_logic_vector(255 downto 0)
:= (OTHERS=>'0');
Constant C_ALL_ONES : std_logic_vector(255 downto 0)
:= (OTHERS=>'1');
----------------------------------------------------------------------------------
-- Implement date generator (DG)
constant IMP_DATA_GENERATOR : boolean := FALSE;
-- DDR2 SODIMM module as the event buffer kernel
-- !! remember to replace the UCF accordingly
constant USE_DDR2_MODULE : boolean := FALSE;
-- For simplified verification, emulated loop-backed links be used if FALSE
constant USE_OPTO_LINKS : boolean := FALSE;
-- Implement interrupt generator (IG)
constant IMP_INT_GENERATOR : boolean := TRUE;
-- interrupt type: cfg(aka legacy) or MSI
constant USE_CFG_INTERRUPT : boolean := FALSE;
-- Busmacro insertion for partial reconfigurability
constant INSERT_BUSMACRO : boolean := FALSE;
------------------------------------------------------------------------------------
---- ------------ Author ID
constant AUTHOR_UNKNOWN : std_logic_vector(4-1 downto 0) := X"0";
constant AUTHOR_AKUGEL : std_logic_vector(4-1 downto 0) := X"1";
constant AUTHOR_WGAO : std_logic_vector(4-1 downto 0) := X"2";
----------------------------------------------------------------------------------
---- ------------ design ID ---------------------
---- design id now contains a version: upper 8 bits, a major revision: next 8 bits,
---- and author code: next 4 bits and a minor revision: lower 12 bits
---- keep the autor file seperate and don't submit to CVS
----
constant DESIGN_VERSION : std_logic_vector( 8-1 downto 0) := X"01";
constant DESIGN_MAJOR_REVISION : std_logic_vector( 8-1 downto 0) := X"04";
constant DESIGN_MINOR_REVISION : std_logic_vector(12-1 downto 0) := X"001";
constant C_DESIGN_ID : std_logic_vector(64-1 downto 0)
:= X"00000000"
& DESIGN_VERSION
& DESIGN_MAJOR_REVISION
& AUTHOR_WGAO
& DESIGN_MINOR_REVISION
;
----------------------------------------------------------------------------------
-- Function to invert endian for 32-bit data
--
function Endian_Invert_32 (Word_in: std_logic_vector) return std_logic_vector;
function Endian_Invert_64 (Word_in: std_logic_vector(64-1 downto 0)) return std_logic_vector;
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
-- revision log
-- 2007-05-30: AK - abbPackage added, address map changed
-- 2007-06-12: WGao - C_DEF_DMA_CTRL_WORD added,
-- DMA Control word bit definition added,
-- Function Endian_Invert_32 added.
-- CINT_ADDR_MRD_CTRL and CINT_ADDR_CPLD_CTRL changed,
-- CINT_ADDR_US_SAH and CINT_ADDR_DS_SAH removed.
-- 2007-07-16: AK - dma status bits added
end abb64Package;
package body abb64Package is
-- ------------------------------------------------------------------------------------------
-- Function to invert bytewise endian for 32-bit data
-- ------------------------------------------------------------------------------------------
function Endian_Invert_32 (Word_in: std_logic_vector) return std_logic_vector is
begin
return Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
end Endian_Invert_32;
-- ------------------------------------------------------------------------------------------
-- Function to invert bytewise endian for 64-bit data
-- ------------------------------------------------------------------------------------------
function Endian_Invert_64 (Word_in: std_logic_vector(64-1 downto 0)) return std_logic_vector is
begin
return Word_in(39 downto 32)&Word_in(47 downto 40)&Word_in(55 downto 48)&Word_in(63 downto 56)
& Word_in(7 downto 0)&Word_in(15 downto 8)&Word_in(23 downto 16)&Word_in(31 downto 24);
end Endian_Invert_64;
end abb64Package;
| gpl-2.0 | b1fff89f8a3302856fabfb04c0d74455 | 0.50409 | 3.706122 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/async_cntl.vhd | 1 | 66,887 | ------------------------------------------------------------------------------
-- async_cntl.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
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-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
------------------------------------------------------------------------------
-- Filename: async_cntl.vhd
-- Version: v1.00.a
-- Description: This is the top level file for "EPC asynch control logic",
-- includes the logic of generation of asynch logic signals
-- VHDL-Standard: VHDL'93
------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals:"*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_misc.and_reduce;
use IEEE.std_logic_misc.or_reduce;
library axi_lite_ipif_v3_0;
library lib_pkg_v1_0;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use lib_pkg_v1_0.lib_pkg.max2;
use lib_pkg_v1_0.lib_pkg.log2;
library unisim;
use unisim.vcomponents.FDRE;
library axi_epc_v2_0;
use axi_epc_v2_0.async_statemachine;
use axi_epc_v2_0.async_counters;
------------------------------------------------------------------------------
-- Definition of Generics:
-----------------------------------------------------------------------------
--PRH_SYNC -- To check the sync/async type of devices
--NO_PRH_SYNC -- when = 1 : All the devices are asynchronous
-- -- when = 0 : All the devices are synchronous
--C_SPLB_NATIVE_DWIDTH -- PLB Bus Data Width
--C_NUM_PERIPHERALS -- Number of peripherals present for particular case
--Note: consider x as 0 to C_NUM_PERIPHERALS-1
--C_PRHx_ADDR_TSU -- Peripherl Device address set up time
--C_PRHx_ADDR_TH -- Peripherl Device address hold time
--C_PRHx_WRN_WIDTH -- Peripherl Device write control signal active width
--C_PRHx_DATA_TSU -- Peripherl Device data set up time
--C_PRHx_RDN_WIDTH -- Peripherl Device read control signal active width
--C_PRHx_DATA_TOUT -- Peripherl Device data Data bus(PRH_Data) validity
-- -- from falling edge of read signal(PRH_Rd_n)
--C_PRHx_DATA_TH -- Device data bus(PRH_Data) hold with respect to
-- -- rising edge of write signal(PRH_Wr_n)
--C_PRHx_DATA_TINV -- Device data bus(PRH_Data) high impedance from
-- -- rising edge of read (PRH_Rd_n)
--C_PRHx_RDY_TOUT -- Device ready(PRH_Rdy)validity from the falling
-- -- edge of read or write (PRH_Rd_n/PRH_Wr_n)
--C_PRHx_RDY_WIDTH -- Maximum pulse width of device ready (PRH_Rdy)
-- -- signal
--C_PRHx_ADS_WIDTH -- Peripherl Device address strobe pulse width time
--C_PRHx_CSN_TSU -- Peripherl Device chip select set up time
--C_PRHx_CSN_TH -- Peripherl Device chip select hold time
--C_PRHx_WR_CYCLE -- Peripherl Device cycle time for consecutive writes
--C_PRHx_RD_CYCLE -- Peripherl Device cycle time for consecutive reads
--C_BUS_CLOCK_PERIOD_PS -- PLB clock period
--C_MAX_DWIDTH -- Maximum of data bus width of all peripherals
--C_MAX_PERIPHERALS -- Number of devices that can be connected
-----------------------------------------------------------------------------
-- Definition of Ports:
------------------------------------------------------------------------------
-- Definition of Input:
--Bus2IP_BE -- Bus to IP byte enable
--Bus2IP_CS -- Bus to IP chip select
--Bus2IP_RdCE -- Bus to IP Read control enable
--Bus2IP_WrCE -- Bus to IP Write control enable
--IPIC_Asynch_req -- IPIC Asynch transaction request
--Dev_FIFO_access -- Device FIFO Accress
--Dev_in_access -- Device in access cycle
--Asynch_prh_rdy -- Asynch Mode of Operation of external device
--Dev_dwidth_match -- Peripherl Device Dwidth Match
--Dev_dbus_width -- Peripherl Device Data Width
--Dev_bus_multiplexed -- Peripherl Device address & data bus multiplexed
--Asynch_ce -- Asynch chip enable
--Clk -- Input clock
--Rst -- Input Reset signal
-----------------------------------------------------------------------------
-- Definition of Output Ports:
-----------------------------------------------------------------------------
--Asynch_Wrack -- asynchronous write acknowledge
--Asynch_Rdack -- asynchronous read acknowledge
--Asynch_error -- error acknowledge
--Asynch_Wr -- Asynch write control signal
--Asynch_Rd -- Asynch read control signal
--Asynch_en -- Asynch enable to latch the read/write cycle data
--Asynch_addr_strobe -- Asynch address latch(when bus is muxed)
--Asynch_addr_data_sel -- Asynch address/data select(when bus is muxed)
--Asynch_chip_select -- Asynchronous chip select
--Asynch_addr_cnt_ld -- Asynch counter reset at the start/load for mux access
--Asynch_addr_cnt_en -- Asynch address counter enable to increment next
-----------------------------------------------------------------------------
entity async_cntl is
generic (
PRH_SYNC : std_logic_vector;
NO_PRH_ASYNC : integer;
C_SPLB_NATIVE_DWIDTH: integer;
------------------------------------------
C_PRH0_ADDR_TSU : integer;
C_PRH0_ADDR_TH : integer;
C_PRH0_WRN_WIDTH : integer;
C_PRH0_DATA_TSU : integer;
C_PRH0_RDN_WIDTH : integer;
C_PRH0_DATA_TOUT : integer;
C_PRH0_DATA_TH : integer;
C_PRH0_DATA_TINV : integer;
C_PRH0_RDY_TOUT : integer;
C_PRH0_RDY_WIDTH : integer;
C_PRH0_ADS_WIDTH : integer;
C_PRH0_CSN_TSU : integer;
C_PRH0_CSN_TH : integer ;
C_PRH0_WR_CYCLE : integer ;
C_PRH0_RD_CYCLE : integer ;
------------------------------------------
C_PRH1_ADDR_TSU : integer ;
C_PRH1_ADDR_TH : integer ;
C_PRH1_WRN_WIDTH : integer ;
C_PRH1_DATA_TSU : integer ;
C_PRH1_RDN_WIDTH : integer ;
C_PRH1_DATA_TOUT : integer ;
C_PRH1_DATA_TH : integer ;
C_PRH1_DATA_TINV : integer ;
C_PRH1_RDY_TOUT : integer ;
C_PRH1_RDY_WIDTH : integer ;
C_PRH1_ADS_WIDTH : integer ;
C_PRH1_CSN_TSU : integer ;
C_PRH1_CSN_TH : integer ;
C_PRH1_WR_CYCLE : integer ;
C_PRH1_RD_CYCLE : integer ;
------------------------------------------
C_PRH2_ADDR_TSU : integer ;
C_PRH2_ADDR_TH : integer ;
C_PRH2_WRN_WIDTH : integer ;
C_PRH2_DATA_TSU : integer ;
C_PRH2_RDN_WIDTH : integer ;
C_PRH2_DATA_TOUT : integer ;
C_PRH2_DATA_TH : integer ;
C_PRH2_DATA_TINV : integer ;
C_PRH2_RDY_TOUT : integer ;
C_PRH2_RDY_WIDTH : integer ;
C_PRH2_ADS_WIDTH : integer ;
C_PRH2_CSN_TSU : integer ;
C_PRH2_CSN_TH : integer ;
C_PRH2_WR_CYCLE : integer ;
C_PRH2_RD_CYCLE : integer ;
------------------------------------------
C_PRH3_ADDR_TSU : integer ;
C_PRH3_ADDR_TH : integer ;
C_PRH3_WRN_WIDTH : integer ;
C_PRH3_DATA_TSU : integer ;
C_PRH3_RDN_WIDTH : integer ;
C_PRH3_DATA_TOUT : integer ;
C_PRH3_DATA_TH : integer ;
C_PRH3_DATA_TINV : integer ;
C_PRH3_RDY_TOUT : integer ;
C_PRH3_RDY_WIDTH : integer ;
C_PRH3_ADS_WIDTH : integer ;
C_PRH3_CSN_TSU : integer ;
C_PRH3_CSN_TH : integer ;
C_PRH3_WR_CYCLE : integer ;
C_PRH3_RD_CYCLE : integer ;
------------------------------------------
C_BUS_CLOCK_PERIOD_PS : integer;
--C_MAX_DWIDTH : integer;
C_NUM_PERIPHERALS : integer;
C_MAX_PERIPHERALS : integer
------------------------------------------
);
port (
Bus2IP_CS : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_BE : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 -1);
Bus2IP_RNW : in std_logic;
IPIC_Asynch_req : in std_logic;
Dev_FIFO_access : in std_logic;
Dev_in_access : in std_logic;
Asynch_prh_rdy : in std_logic;
Dev_dwidth_match : in std_logic;
--Dev_dbus_width : in std_logic_vector(0 to 2);
Dev_bus_multiplexed : in std_logic;
Asynch_ce : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 -1);
Asynch_Wrack : out std_logic;
Asynch_Rdack : out std_logic;
Asynch_error : out std_logic;
Asynch_Wr : out std_logic;
Asynch_Rd : out std_logic;
Asynch_en : out std_logic;
Asynch_addr_strobe : out std_logic;
Asynch_addr_data_sel: out std_logic;
Asynch_data_sel : out std_logic;
Asynch_chip_select : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Asynch_addr_cnt_ld : out std_logic;
Asynch_addr_cnt_en : out std_logic;
-- Clocks and reset
Clk : in std_logic;
Rst : in std_logic
);
end entity async_cntl;
------------------------------------------------------------------------------
architecture imp of async_cntl is
attribute ASYNC_REG : string;
------------------------------------------------------------------------------
-- Function : FindMaxWidth
-- This function is used by all calculations.
-- The main logic behind this function is, the max width of respective
-- parameters will be calculated, based upon whether the device is asynch
-- device or not.If the device is asynch device then only the parameter
-- of the respective array will be taken into consideration for further
-- calculation. The SYNC_ARRAY will give the clear idea about the
-- type of devices (asynch/sync)
function FindMaxWidth( no_of_devices : integer;
prh_wait_width : INTEGER_ARRAY_TYPE;
sync_vector : std_logic_vector
)
return integer is
variable temp_max : integer := 1;
begin
for i in 0 to (no_of_devices-1) loop
if sync_vector(i) = '0' then
temp_max := max2(temp_max,prh_wait_width(i));
end if;
end loop;
return temp_max;
end function FindMaxWidth;
------------------------------------------------------------------------------
-- Declaration of Constants
------------------------------------------------------------------------------
--ADDRESS HOLD TIME
--This calculation is applicable for devices with MUXed buses
--get the address hold up generics for all the peripherals
--the calculation is done by comparing 1 or C_PRHx_ADDR_TH/C_BUS_CLOCK_PERIOD_PS
--value. this gives precise values of the ADDRx_TH.
constant ADDR_TH0 : integer:= (C_PRH0_ADDR_TH/C_BUS_CLOCK_PERIOD_PS)+1;
constant ADDR_TH1 : integer:= (C_PRH1_ADDR_TH/C_BUS_CLOCK_PERIOD_PS)+1;
constant ADDR_TH2 : integer:= (C_PRH2_ADDR_TH/C_BUS_CLOCK_PERIOD_PS)+1;
constant ADDR_TH3 : integer:= (C_PRH3_ADDR_TH/C_BUS_CLOCK_PERIOD_PS)+1;
-- convert the generics into the integer to define the width of the counter
constant ADDR_TH0_WIDTH : integer := max2(1,log2(ADDR_TH0+1));
constant ADDR_TH1_WIDTH : integer := max2(1,log2(ADDR_TH1+1));
constant ADDR_TH2_WIDTH : integer := max2(1,log2(ADDR_TH2+1));
constant ADDR_TH3_WIDTH : integer := max2(1,log2(ADDR_TH3+1));
-- to make the width of counter independent of manual calculation
constant ADDR_TH_ARRAY : INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
ADDR_TH0_WIDTH,
ADDR_TH1_WIDTH,
ADDR_TH2_WIDTH,
ADDR_TH3_WIDTH
);
constant MAX_ADDR_TH_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,ADDR_TH_ARRAY,PRH_SYNC);
constant ADDR_HOLD_CNTR0:std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_TH0, MAX_ADDR_TH_CNT_WIDTH);
constant ADDR_HOLD_CNTR1:std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_TH1, MAX_ADDR_TH_CNT_WIDTH);
constant ADDR_HOLD_CNTR2:std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_TH2, MAX_ADDR_TH_CNT_WIDTH);
constant ADDR_HOLD_CNTR3:std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_TH3, MAX_ADDR_TH_CNT_WIDTH);
-- this array stores the values for the adress hold up time for devices
type ADDR_HOLDCNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1);
constant ADDR_HOLDCNTR_ARRAY : ADDR_HOLDCNT_ARRAY_TYPE :=
(
ADDR_HOLD_CNTR0,
ADDR_HOLD_CNTR1,
ADDR_HOLD_CNTR2,
ADDR_HOLD_CNTR3
);
------------------------------------------------------------------------------
-- CHIP SELECT/DATA HOLD/ADDR HOLD calculation
-- ADDRESS HOLD TIME/DATA HOLD TIME/CHIP SELECT HOLD TIME
-- This calculation is applicable for NON-MUXed Asynch devices
-- This constant is applicable for DATA Hold and Chip Select and Address Hold
-- Time. It is a max of Chip select hold and Data Hold and Address Hold period
-- the calculation is done by comparing 1 or max of C_PRH0_DATA_TH,C_PRH0_CSN_TH
-- and C_PRH0_ADDR_TH divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the ADDRx_TH.
constant ADDR_DATA_CS_TH0 : integer :=
(max2(1,
(max2
(max2(C_PRH0_DATA_TH,C_PRH0_CSN_TH),C_PRH0_ADDR_TH)/C_BUS_CLOCK_PERIOD_PS)+1));
constant ADDR_DATA_CS_TH1 : integer :=
(max2(1,
(max2
(max2(C_PRH1_DATA_TH,C_PRH1_CSN_TH),C_PRH1_ADDR_TH)/C_BUS_CLOCK_PERIOD_PS)+1));
constant ADDR_DATA_CS_TH2 : integer :=
(max2(1,
(max2
(max2(C_PRH2_DATA_TH,C_PRH2_CSN_TH),C_PRH2_ADDR_TH)/C_BUS_CLOCK_PERIOD_PS)+1));
constant ADDR_DATA_CS_TH3 : integer :=
(max2(1,
(max2
(max2(C_PRH3_DATA_TH,C_PRH3_CSN_TH),C_PRH3_ADDR_TH)/C_BUS_CLOCK_PERIOD_PS)+1));
-- convert the generics into the integer to define the width of the counter
constant ADDR_DATA_CS_TH0_WIDTH : integer := max2(1,log2(ADDR_DATA_CS_TH0+1));
constant ADDR_DATA_CS_TH1_WIDTH : integer := max2(1,log2(ADDR_DATA_CS_TH1+1));
constant ADDR_DATA_CS_TH2_WIDTH : integer := max2(1,log2(ADDR_DATA_CS_TH2+1));
constant ADDR_DATA_CS_TH3_WIDTH : integer := max2(1,log2(ADDR_DATA_CS_TH3+1));
-- to make the width of counter independent of manual calculation
-- Pass this array to FindMaxWidth function
constant ADDR_DATA_CS_TH_ARRAY :
INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
ADDR_DATA_CS_TH0_WIDTH,
ADDR_DATA_CS_TH1_WIDTH,
ADDR_DATA_CS_TH2_WIDTH,
ADDR_DATA_CS_TH3_WIDTH
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_ADDR_DATA_CS_TH_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,ADDR_DATA_CS_TH_ARRAY,PRH_SYNC);
constant ADDR_DATA_CS_HOLD_CNTR0:
std_logic_vector(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_DATA_CS_TH0, MAX_ADDR_DATA_CS_TH_CNT_WIDTH);
constant ADDR_DATA_CS_HOLD_CNTR1:
std_logic_vector(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_DATA_CS_TH1, MAX_ADDR_DATA_CS_TH_CNT_WIDTH);
constant ADDR_DATA_CS_HOLD_CNTR2:
std_logic_vector(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_DATA_CS_TH2, MAX_ADDR_DATA_CS_TH_CNT_WIDTH);
constant ADDR_DATA_CS_HOLD_CNTR3:
std_logic_vector(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1)
:= conv_std_logic_vector(ADDR_DATA_CS_TH3, MAX_ADDR_DATA_CS_TH_CNT_WIDTH);
-- this array stores the values for the data hold up time for devices
type ADDR_DATA_HOLD_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1);
constant ADDR_DATA_HOLD_CNTR_ARRAY : ADDR_DATA_HOLD_CNT_ARRAY_TYPE :=
(
ADDR_DATA_CS_HOLD_CNTR0,
ADDR_DATA_CS_HOLD_CNTR1,
ADDR_DATA_CS_HOLD_CNTR2,
ADDR_DATA_CS_HOLD_CNTR3
);
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- READ CONTROL SIGNAL
-- Read signal (PRH_RDn) low time is the maximum of C_PRHx_RDN_WIDTH and
-- C_PRHx_DATA_TOUT
-- the calculation is done by comparing 1 or max of C_PRH0_RDN_WIDTH
-- and C_PRH0_DATA_TOUT divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the RDN_MAXx.
constant RDN_MAX0 : integer :=
(max2(1,
(max2(C_PRH0_RDN_WIDTH,C_PRH0_DATA_TOUT)/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDN_MAX1 : integer :=
(max2(1,
(max2(C_PRH1_RDN_WIDTH,C_PRH1_DATA_TOUT)/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDN_MAX2 : integer :=
(max2(1,
(max2(C_PRH2_RDN_WIDTH,C_PRH2_DATA_TOUT)/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDN_MAX3 : integer :=
(max2(1,
(max2(C_PRH3_RDN_WIDTH,C_PRH3_DATA_TOUT)/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDN_CNT_WIDTH0: integer := max2(1,log2(RDN_MAX0+1));
constant RDN_CNT_WIDTH1: integer := max2(1,log2(RDN_MAX1+1));
constant RDN_CNT_WIDTH2: integer := max2(1,log2(RDN_MAX2+1));
constant RDN_CNT_WIDTH3: integer := max2(1,log2(RDN_MAX3+1));
constant RD_CNT_ARRAY : INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
RDN_CNT_WIDTH0,
RDN_CNT_WIDTH1,
RDN_CNT_WIDTH2,
RDN_CNT_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_RDN_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,RD_CNT_ARRAY,PRH_SYNC);
------------------------------------------------------------------------------
-- WRITE CONTROL SIGNAL
-- Write signal (PRH_WRn) low time is the maximum of C_PRHx_WRN_WIDTH and
-- C_PRHx_DATA_TSU
-- the calculation is done by comparing 1 or max of C_PRH0_WRN_WIDTH
-- and C_PRH0_DATA_TSU divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the WRN_MAXx.
constant WRN_MAX0 : integer
:=(max2(1,
(max2(C_PRH0_WRN_WIDTH,C_PRH0_DATA_TSU)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WRN_MAX1 : integer
:=(max2(1,
(max2(C_PRH1_WRN_WIDTH,C_PRH1_DATA_TSU)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WRN_MAX2 : integer
:=(max2(1,
(max2(C_PRH2_WRN_WIDTH,C_PRH2_DATA_TSU)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WRN_MAX3 : integer
:=(max2(1,
(max2(C_PRH3_WRN_WIDTH,C_PRH3_DATA_TSU)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WRN_CNT_WIDTH0 : integer := max2(1,log2(WRN_MAX0+1));
constant WRN_CNT_WIDTH1 : integer := max2(1,log2(WRN_MAX1+1));
constant WRN_CNT_WIDTH2 : integer := max2(1,log2(WRN_MAX2+1));
constant WRN_CNT_WIDTH3 : integer := max2(1,log2(WRN_MAX3+1));
constant WR_CNT_ARRAY : INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
WRN_CNT_WIDTH0,
WRN_CNT_WIDTH1,
WRN_CNT_WIDTH2,
WRN_CNT_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_WRN_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,WR_CNT_ARRAY,PRH_SYNC);
------------------------------------------------------------------------------
--calculate the max width of Read and Write calculation
constant MAX_CONTROL_CNT_WIDTH : integer :=
max2(MAX_WRN_CNT_WIDTH,MAX_RDN_CNT_WIDTH);
------------------------------------------------------------------------------
constant TRDCNT_0 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(RDN_MAX0, MAX_CONTROL_CNT_WIDTH);
constant TRDCNT_1 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(RDN_MAX1, MAX_CONTROL_CNT_WIDTH);
constant TRDCNT_2 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(RDN_MAX2, MAX_CONTROL_CNT_WIDTH);
constant TRDCNT_3 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(RDN_MAX3, MAX_CONTROL_CNT_WIDTH);
--this array stores the values for read control signal activated period value
type RDCNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1);
constant TRD_CNTR_ARRAY : RDCNT_ARRAY_TYPE :=
(
TRDCNT_0,
TRDCNT_1,
TRDCNT_2,
TRDCNT_3
);
-----------------------------------------------------------------------------
-- convert the constants into std_logic_vector
constant TWRCNT_0 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(WRN_MAX0, MAX_CONTROL_CNT_WIDTH);
constant TWRCNT_1 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(WRN_MAX1, MAX_CONTROL_CNT_WIDTH);
constant TWRCNT_2 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(WRN_MAX2, MAX_CONTROL_CNT_WIDTH);
constant TWRCNT_3 :
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1)
:= conv_std_logic_vector(WRN_MAX3, MAX_CONTROL_CNT_WIDTH);
-- define the array of the std_logic_vector. It should be 2 dimentional array
-- whose height is determined by the C_MAX_PERIPHERALS and the depth is -- --
-- defined by max of the width of the WR counters.
type WRCNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1);
constant TWR_CNTR_ARRAY : WRCNT_ARRAY_TYPE :=
( TWRCNT_0,
TWRCNT_1,
TWRCNT_2,
TWRCNT_3
);
------------------------------------------------------------------------------
--ADDRESS STROBE
--This signal is used to define address strobe width, when the device is in
-- multiplexed mode
-- the calculation is done by comparing 1 or max of C_PRH0_ADDR_TSU
-- and C_PRH0_ADS_WIDTH,C_PRH0_CSN_TSU divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the ADS_WDTHx.
constant ADS_WDTH0: integer :=
(max2(1,
(max2
(max2(C_PRH0_ADDR_TSU,C_PRH0_ADS_WIDTH),C_PRH0_CSN_TSU)/C_BUS_CLOCK_PERIOD_PS)
+1));
constant ADS_WDTH1: integer :=
(max2(1,
(max2
(max2(C_PRH1_ADDR_TSU,C_PRH1_ADS_WIDTH),C_PRH1_CSN_TSU)/C_BUS_CLOCK_PERIOD_PS)
+1));
constant ADS_WDTH2: integer :=
(max2(1,
(max2
(max2(C_PRH2_ADDR_TSU,C_PRH2_ADS_WIDTH),C_PRH2_CSN_TSU)/C_BUS_CLOCK_PERIOD_PS)
+1));
constant ADS_WDTH3: integer :=
(max2(1,
(max2
(max2(C_PRH3_ADDR_TSU,C_PRH3_ADS_WIDTH),C_PRH3_CSN_TSU)/C_BUS_CLOCK_PERIOD_PS)
+1));
constant ADS_CNT_WIDTH0: integer := max2(1,log2(ADS_WDTH0+1));
constant ADS_CNT_WIDTH1: integer := max2(1,log2(ADS_WDTH1+1));
constant ADS_CNT_WIDTH2: integer := max2(1,log2(ADS_WDTH2+1));
constant ADS_CNT_WIDTH3: integer := max2(1,log2(ADS_WDTH3+1));
constant ADS_CNT_ARRAY : INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
ADS_CNT_WIDTH0,
ADS_CNT_WIDTH1,
ADS_CNT_WIDTH2,
ADS_CNT_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_ADS_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,ADS_CNT_ARRAY,PRH_SYNC);
constant TADS_CNT_0: std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1)
:=conv_std_logic_vector(ADS_WDTH0,MAX_ADS_CNT_WIDTH);
constant TADS_CNT_1: std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1)
:=conv_std_logic_vector(ADS_WDTH1,MAX_ADS_CNT_WIDTH);
constant TADS_CNT_2: std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1)
:=conv_std_logic_vector(ADS_WDTH2,MAX_ADS_CNT_WIDTH);
constant TADS_CNT_3: std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1)
:=conv_std_logic_vector(ADS_WDTH3,MAX_ADS_CNT_WIDTH);
-- this array stores the values for the address strobe time for devices
type TADS_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1);
constant TADS_CNT_ARRAY : TADS_CNT_ARRAY_TYPE :=
(
TADS_CNT_0,
TADS_CNT_1,
TADS_CNT_2,
TADS_CNT_3
);
-------------------------------------------------------------------------------
-- RECOVERY
-- bus muxed (types) -- write recovery time
-- -- read recovery time
-- bus non-muxed (types) -- write recovery time
-- -- read recovery time
-- In parameter declaration, the Read and Write Cycle period should be always
-- more than Read and Write control width period
-------------------------------------------------------------------------------
-- common calculation for write and read recovery
constant PRH_Wr_n0 : integer :=
(C_PRH0_WR_CYCLE-C_PRH0_WRN_WIDTH);
constant PRH_Wr_n1 : integer :=
(C_PRH1_WR_CYCLE-C_PRH1_WRN_WIDTH);
constant PRH_Wr_n2 : integer :=
(C_PRH2_WR_CYCLE-C_PRH2_WRN_WIDTH);
constant PRH_Wr_n3 : integer :=
(C_PRH3_WR_CYCLE-C_PRH3_WRN_WIDTH);
constant PRH_Rd_n0 : integer:=
(C_PRH0_Rd_CYCLE-C_PRH0_RDN_WIDTH);
constant PRH_Rd_n1 : integer :=
(C_PRH1_Rd_CYCLE-C_PRH1_RDN_WIDTH);
constant PRH_Rd_n2 : integer :=
(C_PRH2_Rd_CYCLE-C_PRH2_RDN_WIDTH);
constant PRH_Rd_n3 : integer :=
(C_PRH3_Rd_CYCLE-C_PRH3_RDN_WIDTH);
--------------------------------------------------------------------------------
-- RECOVERY + BUS MUXED + WRITE
-- The recovery time is maximum
-- of C_PRHx_CSN_TH and C_PRHx_DATA_TH and
-- [(C_PRHx_WR_CYCLE)-(C_PRHx_WRN_WIDTH)]
-- (ADDRESS HOLD & DATA HOLD & PRH_Wr_n)
-- the calculation is done by comparing 1 or max of C_PRH0_CSN_TH
-- and C_PRH0_DATA_TH,PRH_Wr_n0 divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the WR_REC_MUXEDx.
constant WR_REC_MUXED0 : integer :=
(max2(1,
(max2(max2(C_PRH0_CSN_TH,C_PRH0_DATA_TH),PRH_Wr_n0)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_MUXED1 : integer :=
(max2(1,
(max2(max2(C_PRH1_CSN_TH,C_PRH1_DATA_TH),PRH_Wr_n1)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_MUXED2 : integer :=
(max2(1,
(max2(max2(C_PRH2_CSN_TH,C_PRH2_DATA_TH),PRH_Wr_n2)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_MUXED3 : integer :=
(max2(1,
(max2(max2(C_PRH3_CSN_TH,C_PRH3_DATA_TH),PRH_Wr_n3)/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_MUXED_WIDTH0 : integer := max2(1,log2(WR_REC_MUXED0+1));
constant WR_REC_MUXED_WIDTH1 : integer := max2(1,log2(WR_REC_MUXED1+1));
constant WR_REC_MUXED_WIDTH2 : integer := max2(1,log2(WR_REC_MUXED2+1));
constant WR_REC_MUXED_WIDTH3 : integer := max2(1,log2(WR_REC_MUXED3+1));
constant WR_REC_CNT_MUXED_ARRAY :
INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
WR_REC_MUXED_WIDTH0,
WR_REC_MUXED_WIDTH1,
WR_REC_MUXED_WIDTH2,
WR_REC_MUXED_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_WR_REC_MUXED_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,WR_REC_CNT_MUXED_ARRAY,PRH_SYNC);
constant WR_REC_MUXED_CNT0:
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_MUXED0, MAX_WR_REC_MUXED_CNT_WIDTH);
constant WR_REC_MUXED_CNT1:
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_MUXED1, MAX_WR_REC_MUXED_CNT_WIDTH);
constant WR_REC_MUXED_CNT2:
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_MUXED2, MAX_WR_REC_MUXED_CNT_WIDTH);
constant WR_REC_MUXED_CNT3:
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_MUXED3, MAX_WR_REC_MUXED_CNT_WIDTH);
type WR_REC_MUXED_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1);
constant WR_REC_MUXED_CNTR_ARRAY : WR_REC_MUXED_CNT_ARRAY_TYPE :=
(
WR_REC_MUXED_CNT0,
WR_REC_MUXED_CNT1,
WR_REC_MUXED_CNT2,
WR_REC_MUXED_CNT3
);
-------------------------------------------------------------------------------
-- RECOVERY + BUS MUXED + READ
-- The recovery time is maximum
-- of C_PRHx_CSN_TH and C_PRHx_DATA_TINV and
-- [(C_PRHx_RD_CYCLE)-(C_PRHx_RDN_WIDTH)]
-- (ADDRESS HOLD & DATA HOLD & PRH_Rd_n)
-- the calculation is done by comparing 1 or max of C_PRH0_CSN_TH
-- and C_PRH0_DATA_TINV,PRH_Rd_n0 divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the RD_REC_MUXEDx.
constant RD_REC_MUXED0 : integer :=
(max2(1,
(max2(max2(C_PRH0_CSN_TH,C_PRH0_DATA_TINV),PRH_Rd_n0)/C_BUS_CLOCK_PERIOD_PS)+1
));
constant RD_REC_MUXED1 : integer :=
(max2(1,
(max2(max2(C_PRH1_CSN_TH,C_PRH1_DATA_TINV),PRH_Rd_n1)/C_BUS_CLOCK_PERIOD_PS)+1
));
constant RD_REC_MUXED2 : integer :=
(max2(1,
(max2(max2(C_PRH2_CSN_TH,C_PRH2_DATA_TINV),PRH_Rd_n2)/C_BUS_CLOCK_PERIOD_PS)+1
));
constant RD_REC_MUXED3 : integer :=
(max2(1,
(max2(max2(C_PRH3_CSN_TH,C_PRH3_DATA_TINV),PRH_Rd_n3)/C_BUS_CLOCK_PERIOD_PS)+1
));
constant RD_REC_MUXED_WIDTH0 : integer := max2(1,log2(RD_REC_MUXED0+1));
constant RD_REC_MUXED_WIDTH1 : integer := max2(1,log2(RD_REC_MUXED1+1));
constant RD_REC_MUXED_WIDTH2 : integer := max2(1,log2(RD_REC_MUXED2+1));
constant RD_REC_MUXED_WIDTH3 : integer := max2(1,log2(RD_REC_MUXED3+1));
constant RD_REC_CNT_MUXED_ARRAY :
INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
RD_REC_MUXED_WIDTH0,
RD_REC_MUXED_WIDTH1,
RD_REC_MUXED_WIDTH2,
RD_REC_MUXED_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_RD_REC_MUXED_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,RD_REC_CNT_MUXED_ARRAY,PRH_SYNC);
constant RD_REC_MUXED_CNT0:
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_MUXED0, MAX_RD_REC_MUXED_CNT_WIDTH);
constant RD_REC_MUXED_CNT1:
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_MUXED1, MAX_RD_REC_MUXED_CNT_WIDTH);
constant RD_REC_MUXED_CNT2:
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_MUXED2, MAX_RD_REC_MUXED_CNT_WIDTH);
constant RD_REC_MUXED_CNT3:
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_MUXED3, MAX_RD_REC_MUXED_CNT_WIDTH);
type RD_REC_MUXED_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1);
constant RD_REC_MUXED_CNTR_ARRAY : RD_REC_MUXED_CNT_ARRAY_TYPE :=
(
RD_REC_MUXED_CNT0,
RD_REC_MUXED_CNT1,
RD_REC_MUXED_CNT2,
RD_REC_MUXED_CNT3
);
-------------------------------------------------------------------------------
-- RECOVERY + BUS NON-MUXED + WRITE
-- The recovery time is maximum
-- of C_PRHx_ADDR and C_PRHx_CSN_TH and C_PRHx_DATA_TH and
-- [(C_PRHx_WR_CYCLE)-(C_PRHx_WRN_WIDTH)]
-- (ADDRESS HOLD & DATA HOLD & PRH_Wr_n)
-- the calculation is done by comparing 1 or max of C_PRH0_CSN_TH
-- and C_PRH0_DATA_TH,C_PRH0_ADDR_TH, PRH_Wr_n0 divided by C_BUS_CLOCK_PERIOD_PS
-- value. this gives precise values of the WR_REC_NON_MUXEDx.
constant WR_REC_NON_MUXED0 : integer :=
(max2(1,
(max2(max2(C_PRH0_CSN_TH,C_PRH0_DATA_TH),
max2(C_PRH0_ADDR_TH,PRH_Wr_n0))/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_NON_MUXED1 : integer :=
(max2(1,
(max2(max2(C_PRH1_CSN_TH,C_PRH1_DATA_TH),
max2(C_PRH1_ADDR_TH,PRH_Wr_n1))/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_NON_MUXED2 : integer :=
(max2(1,
(max2(max2(C_PRH2_CSN_TH,C_PRH2_DATA_TH),
max2(C_PRH1_ADDR_TH,PRH_Wr_n2))/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_NON_MUXED3 : integer :=
(max2(1,
(max2(max2(C_PRH3_CSN_TH,C_PRH3_DATA_TH),
max2(C_PRH3_ADDR_TH,PRH_Wr_n3))/C_BUS_CLOCK_PERIOD_PS)+1));
constant WR_REC_NON_MUXED_WIDTH0 : integer:= max2(1,log2(WR_REC_NON_MUXED0+1));
constant WR_REC_NON_MUXED_WIDTH1 : integer:= max2(1,log2(WR_REC_NON_MUXED1+1));
constant WR_REC_NON_MUXED_WIDTH2 : integer:= max2(1,log2(WR_REC_NON_MUXED2+1));
constant WR_REC_NON_MUXED_WIDTH3 : integer:= max2(1,log2(WR_REC_NON_MUXED3+1));
constant WR_REC_CNT_NON_MUXED_ARRAY :
INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
WR_REC_NON_MUXED_WIDTH0,
WR_REC_NON_MUXED_WIDTH1,
WR_REC_NON_MUXED_WIDTH2,
WR_REC_NON_MUXED_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_WR_REC_NON_MUXED_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,WR_REC_CNT_NON_MUXED_ARRAY,PRH_SYNC);
constant WR_REC_NON_MUXED_CNT0:
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_NON_MUXED0, MAX_WR_REC_NON_MUXED_CNT_WIDTH);
constant WR_REC_NON_MUXED_CNT1:
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_NON_MUXED1, MAX_WR_REC_NON_MUXED_CNT_WIDTH);
constant WR_REC_NON_MUXED_CNT2:
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_NON_MUXED2, MAX_WR_REC_NON_MUXED_CNT_WIDTH);
constant WR_REC_NON_MUXED_CNT3:
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(WR_REC_NON_MUXED3, MAX_WR_REC_NON_MUXED_CNT_WIDTH);
type WR_REC_NON_MUXED_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1);
constant WR_REC_NON_MUXED_CNTR_ARRAY : WR_REC_NON_MUXED_CNT_ARRAY_TYPE :=
(
WR_REC_NON_MUXED_CNT0,
WR_REC_NON_MUXED_CNT1,
WR_REC_NON_MUXED_CNT2,
WR_REC_NON_MUXED_CNT3
);
-------------------------------------------------------------------------------
-- RECOVERY + BUS NON-MUXED + READ
-- The recovery time is maximum
-- of C_PRHx_CSN_TH and C_PRHx_DATA_TINV and
-- [(C_PRHx_RD_CYCLE)-(C_PRHx_RDN_WIDTH)]
-- (ADDRESS HOLD & DATA HOLD & PRH_Rd_n)
-- the calculation is done by comparing 1 or max of C_PRH0_CSN_TH
-- and C_PRH0_DATA_TINV,C_PRH0_ADDR_TH,PRH_Rd_n0 divided by C_BUS_CLOCK_PERIOD_PS
-- value. this gives precise values of the RD_REC_NON_MUXEDx.
constant RD_REC_NON_MUXED0 : integer :=
(max2(1,
(max2(max2(C_PRH0_CSN_TH,C_PRH0_DATA_TINV),
max2(C_PRH0_ADDR_TH,PRH_Rd_n0))/C_BUS_CLOCK_PERIOD_PS)+1));
constant RD_REC_NON_MUXED1 : integer :=
(max2(1,
(max2(max2(C_PRH1_CSN_TH,C_PRH1_DATA_TINV),
max2(C_PRH1_ADDR_TH,PRH_Rd_n1))/C_BUS_CLOCK_PERIOD_PS)+1));
constant RD_REC_NON_MUXED2 : integer :=
(max2(1,
(max2(max2(C_PRH2_CSN_TH,C_PRH2_DATA_TINV),
max2(C_PRH2_ADDR_TH,PRH_Rd_n2))/C_BUS_CLOCK_PERIOD_PS)+1));
constant RD_REC_NON_MUXED3 : integer :=
(max2(1,
(max2(max2(C_PRH3_CSN_TH,C_PRH3_DATA_TINV),
max2(C_PRH3_ADDR_TH,PRH_Rd_n3))/C_BUS_CLOCK_PERIOD_PS)+1));
constant RD_REC_NON_MUXED_WIDTH0 : integer:= max2(1,log2(RD_REC_NON_MUXED0+1));
constant RD_REC_NON_MUXED_WIDTH1 : integer:= max2(1,log2(RD_REC_NON_MUXED1+1));
constant RD_REC_NON_MUXED_WIDTH2 : integer:= max2(1,log2(RD_REC_NON_MUXED2+1));
constant RD_REC_NON_MUXED_WIDTH3 : integer:= max2(1,log2(RD_REC_NON_MUXED3+1));
constant RD_REC_CNT_NON_MUXED_ARRAY :
INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
RD_REC_NON_MUXED_WIDTH0,
RD_REC_NON_MUXED_WIDTH1,
RD_REC_NON_MUXED_WIDTH2,
RD_REC_NON_MUXED_WIDTH3
);
-- the max value is calculated for those devices, which are asynch type
-- PRH_SYNC will be directly taken from the epc_core.vhd file
constant MAX_RD_REC_NON_MUXED_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,RD_REC_CNT_NON_MUXED_ARRAY,PRH_SYNC);
constant RD_REC_NON_MUXED_CNT0:
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_NON_MUXED0, MAX_RD_REC_NON_MUXED_CNT_WIDTH);
constant RD_REC_NON_MUXED_CNT1:
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_NON_MUXED1, MAX_RD_REC_NON_MUXED_CNT_WIDTH);
constant RD_REC_NON_MUXED_CNT2:
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_NON_MUXED2, MAX_RD_REC_NON_MUXED_CNT_WIDTH);
constant RD_REC_NON_MUXED_CNT3:
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1)
:= conv_std_logic_vector(RD_REC_NON_MUXED3, MAX_RD_REC_NON_MUXED_CNT_WIDTH);
type RD_REC_NON_MUXED_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1);
constant RD_REC_NON_MUXED_CNTR_ARRAY : RD_REC_NON_MUXED_CNT_ARRAY_TYPE :=
(
RD_REC_NON_MUXED_CNT0,
RD_REC_NON_MUXED_CNT1,
RD_REC_NON_MUXED_CNT2,
RD_REC_NON_MUXED_CNT3
);
------------------------------------------------------------------------------
--constant MAX_WR_M_NM_WIDTH: integer
--:= max2(MAX_WR_REC_MUXED_CNT_WIDTH,MAX_WR_REC_NON_MUXED_CNT_WIDTH);
--constant MAX_RD_M_NM_WIDTH: integer
--:= max2(MAX_RD_REC_MUXED_CNT_WIDTH,MAX_RD_REC_NON_MUXED_CNT_WIDTH);
-------------------------------------------------------------------------------
-- This calulation is for the Device Ready Validity from the activation
-- edge of the control signals
-- The control signals are activated and then it is required to check the
-- readyness of the device.The device ready validity time is the time
-- determined by C_PRHx_RDY_TOUT generics
-- the calculation is done by comparing 1 or max of C_PRH0_RDY_TOUT
-- divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the RD_REC_NON_MUXEDx.
constant RDY_TOUT0 : integer :=
(max2(1,
(C_PRH0_RDY_TOUT/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_TOUT1 : integer :=
(max2(1,
(C_PRH1_RDY_TOUT/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_TOUT2 : integer :=
(max2(1,
(C_PRH2_RDY_TOUT/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_TOUT3 : integer :=
(max2(1,
(C_PRH3_RDY_TOUT/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_TOUT_CNT_WIDTH0 : integer := max2(1,log2(RDY_TOUT0+1));
constant RDY_TOUT_CNT_WIDTH1 : integer := max2(1,log2(RDY_TOUT1+1));
constant RDY_TOUT_CNT_WIDTH2 : integer := max2(1,log2(RDY_TOUT2+1));
constant RDY_TOUT_CNT_WIDTH3 : integer := max2(1,log2(RDY_TOUT3+1));
--for optimisation purpose the max width is calculated only for asynch devices
constant RDY_TOUT_CNT_ARRAY : INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
RDY_TOUT_CNT_WIDTH0,
RDY_TOUT_CNT_WIDTH1,
RDY_TOUT_CNT_WIDTH2,
RDY_TOUT_CNT_WIDTH3
);
constant MAX_RDY_TOUT_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,RDY_TOUT_CNT_ARRAY,PRH_SYNC);
constant RDY_TOUT_CNT_0 :
std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_TOUT0, MAX_RDY_TOUT_CNT_WIDTH);
constant RDY_TOUT_CNT_1 :
std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_TOUT1, MAX_RDY_TOUT_CNT_WIDTH);
constant RDY_TOUT_CNT_2 :
std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_TOUT2, MAX_RDY_TOUT_CNT_WIDTH);
constant RDY_TOUT_CNT_3 :
std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_TOUT3, MAX_RDY_TOUT_CNT_WIDTH);
--RDY_TOUT_CNT_ARRAY_TYPE array stores the values for the device ready
--validity time with respect to assertion of control signals
type RDY_TOUT_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1);
constant TRDY_TOUT_CNTR_ARRAY : RDY_TOUT_CNT_ARRAY_TYPE :=
(
RDY_TOUT_CNT_0,
RDY_TOUT_CNT_1,
RDY_TOUT_CNT_2,
RDY_TOUT_CNT_3
);
------------------------------------------------------------------------------
-- This calulation is for the device ready period for communication with host,
-- which starts from the activation of the control signals
-- The device ready time is the time determined by C_PRHx_RDY_WIDTH generics
-- The constant is of integer type and not integer range 1 to 31
-- This is by assumption: the device ready period may be much longer
-- the calculation is done by comparing 1 or max of C_PRH0_RDY_WIDTH
-- divided by C_BUS_CLOCK_PERIOD_PS value.
-- this gives precise values of the RDY_WIDTHx.
constant RDY_WIDTH0 : integer :=
(max2(1,
(C_PRH0_RDY_WIDTH/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_WIDTH1 : integer :=
(max2(1,
(C_PRH1_RDY_WIDTH/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_WIDTH2 : integer :=
(max2(1,
(C_PRH2_RDY_WIDTH/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_WIDTH3 : integer :=
(max2(1,
(C_PRH3_RDY_WIDTH/C_BUS_CLOCK_PERIOD_PS)+1));
constant RDY_WIDTH_CNT_WIDTH0 : integer := max2(1,log2(RDY_WIDTH0+1));
constant RDY_WIDTH_CNT_WIDTH1 : integer := max2(1,log2(RDY_WIDTH1+1));
constant RDY_WIDTH_CNT_WIDTH2 : integer := max2(1,log2(RDY_WIDTH2+1));
constant RDY_WIDTH_CNT_WIDTH3 : integer := max2(1,log2(RDY_WIDTH3+1));
constant PRH_WIDTH_ARRAY : INTEGER_ARRAY_TYPE(0 to C_MAX_PERIPHERALS-1) :=
(
RDY_WIDTH_CNT_WIDTH0,
RDY_WIDTH_CNT_WIDTH1,
RDY_WIDTH_CNT_WIDTH2,
RDY_WIDTH_CNT_WIDTH3
);
constant MAX_RDY_WIDTH_CNT_WIDTH: integer :=
FindMaxWidth(C_NUM_PERIPHERALS,PRH_WIDTH_ARRAY,PRH_SYNC);
constant RDY_WIDTH_CNT_0 :
std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_WIDTH0, MAX_RDY_WIDTH_CNT_WIDTH);
constant RDY_WIDTH_CNT_1 :
std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_WIDTH1, MAX_RDY_WIDTH_CNT_WIDTH);
constant RDY_WIDTH_CNT_2 :
std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_WIDTH2, MAX_RDY_WIDTH_CNT_WIDTH);
constant RDY_WIDTH_CNT_3 :
std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1)
:= conv_std_logic_vector(RDY_WIDTH3, MAX_RDY_WIDTH_CNT_WIDTH);
-- RDY_WIDTH_CNT_ARRAY_TYPE array stores the values for the device ready
-- validity time with respect to assertion of control signals
type RDY_WIDTH_CNT_ARRAY_TYPE is array (0 to C_MAX_PERIPHERALS-1) of
std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1);
constant TRDY_WIDTH_CNTR_ARRAY : RDY_WIDTH_CNT_ARRAY_TYPE :=
(
RDY_WIDTH_CNT_0,
RDY_WIDTH_CNT_1,
RDY_WIDTH_CNT_2,
RDY_WIDTH_CNT_3
);
------------------------------------------------------------------------------
-- signal declaration
------------------------------------------------------------------------------
-- temporary output signals
signal taddr_hold_data_i:
std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1);
-- address strobe signal when the bus is multipelxed
signal tads_data_i:
std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1);
-- control signal data
-- control width is the actual read or write signal counter width assigned
-- depedning upon the type of control activation
signal tcontrol_width_data_i:
std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1);
-- device validation and max time taken by the device to be ready for the
-- communication std logic vector data
signal tdev_valid_data_i:
std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1);
signal tdevrdy_width_data_i:
std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1);
signal taddr_data_cs_hold_count_i :
std_logic_vector(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1);
-- recovery signal data
signal trd_recovery_muxed_data_i :
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1);
signal twr_recovery_muxed_data_i :
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1);
signal trd_recovery_non_muxed_data_i :
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1);
signal twr_recovery_non_muxed_data_i :
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1);
------------------------------------------------------------------------------
signal asynch_rd_req_i : std_logic;
signal asynch_wr_req_i : std_logic;
signal taddr_hold_ld_i : std_logic;
signal tdata_hold_ld_i : std_logic;
signal tdev_rdy_ld_i : std_logic;
signal tcontrol_ld_i : std_logic;
signal tdev_valid_ld_i : std_logic;
signal tads_ld_i : std_logic;
signal twr_recovery_ld_i : std_logic;
signal trd_recovery_ld_i : std_logic;
signal taddr_hold_ld_ce_i : std_logic;
signal tdata_hold_ld_ce_i : std_logic;
signal tcontrol_ld_ce_i : std_logic;
signal tdev_valid_ld_ce_i : std_logic;
signal tdev_rdy_ld_ce_i : std_logic;
signal tads_ld_ce_i : std_logic;
signal twr_muxed_recovery_load_ce_i : std_logic;
signal trd_muxed_recovery_load_ce_i : std_logic;
signal twr_non_muxed_recovery_load_ce_i : std_logic;
signal trd_non_muxed_recovery_load_ce_i : std_logic;
signal asynch_prh_rdy_d1 : std_logic;
signal asynch_prh_rdy_d2 : std_logic;
signal asynch_prh_rdy_i : std_logic;
signal async_cycle_bit_rst : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
signal async_cycle_bit : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
signal asynch_start_i : std_logic;
signal asynch_cycle_i : std_logic;
signal taddr_hold_cnt : std_logic_vector(0 to MAX_ADDR_TH_CNT_WIDTH-1);
signal tcontrol_wdth_cnt : std_logic_vector(0 to MAX_CONTROL_CNT_WIDTH-1);
signal tdevrdy_wdth_cnt : std_logic_vector(0 to MAX_RDY_WIDTH_CNT_WIDTH-1);
signal tdev_valid_cnt : std_logic_vector(0 to MAX_RDY_TOUT_CNT_WIDTH-1);
signal tads_cnt : std_logic_vector(0 to MAX_ADS_CNT_WIDTH-1);
signal taddr_data_cs_hold_cnt: std_logic_vector
(0 to MAX_ADDR_DATA_CS_TH_CNT_WIDTH-1);
signal twr_muxed_rec_cnt :
std_logic_vector(0 to MAX_WR_REC_MUXED_CNT_WIDTH-1);
signal trd_muxed_rec_cnt :
std_logic_vector(0 to MAX_RD_REC_MUXED_CNT_WIDTH-1);
signal twr_non_muxed_rec_cnt :
std_logic_vector(0 to MAX_WR_REC_NON_MUXED_CNT_WIDTH-1);
signal trd_non_muxed_rec_cnt :
std_logic_vector(0 to MAX_RD_REC_NON_MUXED_CNT_WIDTH-1);
--signal Asynch_Wrack_i, Asynch_rdack_i : std_logic;
------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- NAME: SOME_DEV_ASYNC_GEN
-------------------------------------------------------------------------------
-- Description: Some devices are configured as asynchronous devices
-------------------------------------------------------------------------------
SOME_DEV_ASYNC_GEN: if NO_PRH_ASYNC = 0 generate
attribute ASYNC_REG of REG_PRH_RDY: label is "TRUE";
begin
ASYNC_CYCLE_BIT_RST_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/8-1 generate
async_cycle_bit_rst(i) <= Rst or Asynch_ce(i);-- or Asynch_Wrack_i
--or Asynch_Rdack_i;
end generate ASYNC_CYCLE_BIT_RST_GEN;
--Asynch_Wrack <= Asynch_Wrack_i;
--Asynch_Rdack <= Asynch_Rdack_i;
ASYNC_CYCLE_BIT_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/8-1 generate
---------------------------------------------------------------------------
-- NAME: ASYNC_CYCLE_BIT_PROCESS
---------------------------------------------------------------------------
-- Description: Generate an indication for the byte lanes to be read during
-- a single transaction or during the last transfer of a burst
-- transaction
-- Assumes that the burst transfers are of same size
---------------------------------------------------------------------------
ASYNC_CYCLE_BIT_PROCESS: process (async_cycle_bit_rst, Clk)
begin
if (async_cycle_bit_rst(i) = '1' ) then
async_cycle_bit(i) <= '0';
elsif (Clk'event and Clk = '1') then
if (asynch_start_i = '1') then
async_cycle_bit(i) <= Bus2IP_BE(i);
end if;
end if;
end process ASYNC_CYCLE_BIT_PROCESS;
end generate ASYNC_CYCLE_BIT_GEN;
asynch_cycle_i <= or_reduce(async_cycle_bit);
----------------------------------------------------
-- DEV_RDY_PROCESS : PROCESS
----------------------------------------------------
-- This process is used to double synch the incoming
-- peripheral ready (PRH_RDY) signal
----------------------------------------------------
REG_PRH_RDY: component FDRE
port map (
Q => asynch_prh_rdy_d1,
C => Clk,
CE => '1',
D => Asynch_prh_rdy,
R => Rst
);
-- DEV_RDY_PROCESS:process(Clk)
-- begin
-- if (Clk'event and Clk = '1') then
-- if (Rst = '1') then
-- asynch_prh_rdy_d2 <= '0';
-- else
-- asynch_prh_rdy_d2 <= asynch_prh_rdy_d1;
-- end if;
-- end if;
-- end process DEV_RDY_PROCESS;
asynch_prh_rdy_i <= asynch_prh_rdy_d1;
----------------------------------------------------
ADDR_TH_PROCESS:process (Bus2IP_CS)
begin
taddr_hold_data_i <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
taddr_hold_data_i <= ADDR_HOLDCNTR_ARRAY(i);
end if;
end loop;
end process ADDR_TH_PROCESS;
----------------------------------------------------
DATA_TH_PROCESS:process (Bus2IP_CS)
begin
taddr_data_cs_hold_count_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
taddr_data_cs_hold_count_i<= ADDR_DATA_HOLD_CNTR_ARRAY(i);
end if;
end loop;
end process DATA_TH_PROCESS;
----------------------------------------------------
ADS_DATA_PROCESS:process (Bus2IP_CS)
begin
tads_data_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
tads_data_i<= TADS_CNT_ARRAY(i);
end if;
end loop;
end process ADS_DATA_PROCESS;
----------------------------------------------------
DEV_VALID_DATA_PROCESS:process (Bus2IP_CS)
begin
tdev_valid_data_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
tdev_valid_data_i<= TRDY_TOUT_CNTR_ARRAY(i);
end if;
end loop;
end process DEV_VALID_DATA_PROCESS;
----------------------------------------------------
DEV_RDY_DATA_PROCESS:process (Bus2IP_CS)
begin
tdevrdy_width_data_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
tdevrdy_width_data_i<= TRDY_WIDTH_CNTR_ARRAY(i);
end if;
end loop;
end process DEV_RDY_DATA_PROCESS;
-------------------------------------------------------------------------------
RD_REC_DATA_PROCESS:process (Bus2IP_CS,Dev_bus_multiplexed)
begin
trd_recovery_muxed_data_i<= (others => '0');
trd_recovery_non_muxed_data_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
if(Dev_bus_multiplexed='1') then
trd_recovery_muxed_data_i<= RD_REC_MUXED_CNTR_ARRAY(i);
else
trd_recovery_non_muxed_data_i<= RD_REC_NON_MUXED_CNTR_ARRAY(i);
end if;
end if;
end loop;
end process RD_REC_DATA_PROCESS;
-------------------------------------------------------------------------------
WR_REC_DATA_PROCESS:process (Bus2IP_CS,Dev_bus_multiplexed)
begin
twr_recovery_muxed_data_i<= (others => '0');
twr_recovery_non_muxed_data_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
if(Dev_bus_multiplexed='1') then
twr_recovery_muxed_data_i<= WR_REC_MUXED_CNTR_ARRAY(i);
else
twr_recovery_non_muxed_data_i<= WR_REC_NON_MUXED_CNTR_ARRAY(i);
end if;
end if;
end loop;
end process WR_REC_DATA_PROCESS;
-------------------------------------------------------------------------------
CONTROL_DATA_PROCESS:process (Bus2IP_CS,
Bus2IP_RdCE,
Bus2IP_WrCE)
begin
tcontrol_width_data_i<= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1')then
if(Bus2IP_RdCE(i) = '1')then
tcontrol_width_data_i<= TRD_CNTR_ARRAY(i);
elsif(Bus2IP_WrCE(i) = '1')then
tcontrol_width_data_i<= TWR_CNTR_ARRAY(i);
end if;
end if;
end loop;
end process CONTROL_DATA_PROCESS;
----------------------------------------------------
RD_REQ_GEN_PROCESS:process(Dev_in_access,
Bus2IP_RdCE,
IPIC_Asynch_req,
Bus2IP_CS
)
begin
asynch_rd_req_i <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1' and Bus2IP_RdCE(i)='1')then
asynch_rd_req_i <= Dev_in_access and IPIC_Asynch_req;
end if;
end loop;
end process RD_REQ_GEN_PROCESS;
----------------------------------------------------
WR_REQ_GEN_PROCESS:process(Dev_in_access,
Bus2IP_WrCE,
IPIC_Asynch_req,
Bus2IP_CS
)
begin
asynch_wr_req_i <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if(Bus2IP_CS(i)='1' and Bus2IP_WrCE(i)='1')then
asynch_wr_req_i <= Dev_in_access and IPIC_Asynch_req;
end if;
end loop;
end process WR_REQ_GEN_PROCESS;
-------------------------------------------------------------------------------
-- component instantiation
-------------------------------------------------------------------------------
-- epc_asynch_statemachine
-------------------------------------------------------------------------------
ASYNC_STATEMACHINE_I: entity axi_epc_v2_0.async_statemachine
generic map
(
C_ADDR_TH_CNT_WIDTH => MAX_ADDR_TH_CNT_WIDTH,
C_ADDR_DATA_CS_TH_CNT_WIDTH => MAX_ADDR_DATA_CS_TH_CNT_WIDTH,
C_CONTROL_CNT_WIDTH => MAX_CONTROL_CNT_WIDTH,
C_DEV_VALID_CNT_WIDTH => MAX_RDY_TOUT_CNT_WIDTH,
C_DEV_RDY_CNT_WIDTH => MAX_RDY_WIDTH_CNT_WIDTH,
C_ADS_CNT_WIDTH => MAX_ADS_CNT_WIDTH,
C_WR_REC_NM_CNT_WIDTH => MAX_WR_REC_NON_MUXED_CNT_WIDTH,
C_RD_REC_NM_CNT_WIDTH => MAX_RD_REC_NON_MUXED_CNT_WIDTH,
C_WR_REC_M_CNT_WIDTH => MAX_WR_REC_MUXED_CNT_WIDTH,
C_RD_REC_M_CNT_WIDTH => MAX_RD_REC_MUXED_CNT_WIDTH,
C_NUM_PERIPHERALS => C_NUM_PERIPHERALS
)
port map(
-- inputs form async_cntl
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RNW => Bus2IP_RNW,
Asynch_rd_req => asynch_rd_req_i,
Asynch_wr_req => asynch_wr_req_i,
Dev_in_access => Dev_in_access,
Dev_FIFO_access => Dev_FIFO_access,
Asynch_prh_rdy => asynch_prh_rdy_i,
-- inputs from top_level_file
Dev_dwidth_match => Dev_dwidth_match,
Dev_bus_multiplexed => Dev_bus_multiplexed,
-- input from data steering logic
Asynch_cycle => asynch_cycle_i,
-- outputs to IPIF
Asynch_Wrack => Asynch_Wrack,
Asynch_Rdack => Asynch_Rdack,
Asynch_error => Asynch_error,
Asynch_start => asynch_start_i,
-- outputs to counters
Taddr_hold_load => taddr_hold_ld_i,
Tdata_hold_load => tdata_hold_ld_i,
Tcontrol_load => tcontrol_ld_i,
Tdev_valid_load => tdev_valid_ld_i,
Tdev_rdy_load => tdev_rdy_ld_i,
Tads_load => tads_ld_i,
Twr_recovery_load => twr_recovery_ld_i,
Trd_recovery_load => trd_recovery_ld_i,
Taddr_hold_load_ce => taddr_hold_ld_ce_i,
Tdata_hold_load_ce => tdata_hold_ld_ce_i,
Tcontrol_load_ce => tcontrol_ld_ce_i,
Tdev_valid_load_ce => tdev_valid_ld_ce_i,
Tdev_rdy_load_ce => tdev_rdy_ld_ce_i,
Tads_load_ce => tads_ld_ce_i,
Twr_muxed_recovery_load_ce => twr_muxed_recovery_load_ce_i,
Trd_muxed_recovery_load_ce => trd_muxed_recovery_load_ce_i,
Twr_non_muxed_recovery_load_ce=> twr_non_muxed_recovery_load_ce_i,
Trd_non_muxed_recovery_load_ce=> trd_non_muxed_recovery_load_ce_i,
-- output to data_steering_logic file
Asynch_Rd => Asynch_Rd,
Asynch_en => Asynch_en,
Asynch_Wr => Asynch_Wr,
Asynch_addr_strobe => Asynch_addr_strobe,
Asynch_addr_data_sel => Asynch_addr_data_sel,
Asynch_data_sel => Asynch_data_sel,
Asynch_chip_select => Asynch_chip_select,
Asynch_addr_cnt_ld => Asynch_addr_cnt_ld,
Asynch_addr_cnt_en => Asynch_addr_cnt_en,
Taddr_hold_cnt => taddr_hold_cnt,
Tcontrol_wdth_cnt => tcontrol_wdth_cnt,
Tdevrdy_wdth_cnt => tdevrdy_wdth_cnt,
Tdev_valid_cnt => tdev_valid_cnt,
Tads_cnt => tads_cnt,
Twr_muxed_rec_cnt => twr_muxed_rec_cnt,
Trd_muxed_rec_cnt => trd_muxed_rec_cnt,
Twr_non_muxed_rec_cnt => twr_non_muxed_rec_cnt,
Trd_non_muxed_rec_cnt => trd_non_muxed_rec_cnt,
Taddr_data_cs_hold_cnt => taddr_data_cs_hold_cnt,
-- Clocks and reset
Clk => Clk,
Rst => Rst
);
-------------------------------------------------------------------------------
-- component instantiation
-------------------------------------------------------------------------------
-- epc_counters
-------------------------------------------------------------------------------
ASYNC_CNTR_I: entity axi_epc_v2_0.async_counters
generic map
(
C_ADDR_TH_CNT_WIDTH => MAX_ADDR_TH_CNT_WIDTH,
C_ADDR_DATA_CS_TH_CNT_WIDTH => MAX_ADDR_DATA_CS_TH_CNT_WIDTH,
C_CONTROL_CNT_WIDTH => MAX_CONTROL_CNT_WIDTH,
C_DEV_VALID_CNT_WIDTH => MAX_RDY_TOUT_CNT_WIDTH,
C_DEV_RDY_CNT_WIDTH => MAX_RDY_WIDTH_CNT_WIDTH,
C_ADS_CNT_WIDTH => MAX_ADS_CNT_WIDTH,
C_WR_REC_NM_CNT_WIDTH => MAX_WR_REC_NON_MUXED_CNT_WIDTH,
C_RD_REC_NM_CNT_WIDTH => MAX_RD_REC_NON_MUXED_CNT_WIDTH,
C_WR_REC_M_CNT_WIDTH => MAX_WR_REC_MUXED_CNT_WIDTH,
C_RD_REC_M_CNT_WIDTH => MAX_RD_REC_MUXED_CNT_WIDTH
)
port map
(
Taddr_hold_count => taddr_hold_data_i,
Taddr_data_cs_hold_count => taddr_data_cs_hold_count_i,
Tcontrol_width_data => tcontrol_width_data_i,
Tdev_valid_data => tdev_valid_data_i,
Tdevrdy_width_data => tdevrdy_width_data_i,
Tads_data => tads_data_i,
Twr_recovery_muxed_data => twr_recovery_muxed_data_i,
Twr_recovery_non_muxed_data => twr_recovery_non_muxed_data_i,
Trd_recovery_muxed_data => trd_recovery_muxed_data_i,
Trd_recovery_non_muxed_data => trd_recovery_non_muxed_data_i,
Taddr_hold_cnt => taddr_hold_cnt,
Tcontrol_wdth_cnt => tcontrol_wdth_cnt,
Tdevrdy_wdth_cnt => tdevrdy_wdth_cnt,
Twr_muxed_rec_cnt => twr_muxed_rec_cnt,
Trd_muxed_rec_cnt => trd_muxed_rec_cnt,
Twr_non_muxed_rec_cnt => twr_non_muxed_rec_cnt,
Trd_non_muxed_rec_cnt => trd_non_muxed_rec_cnt,
Tdev_valid_cnt => tdev_valid_cnt,
Tads_cnt => tads_cnt,
Taddr_data_cs_hold_cnt => taddr_data_cs_hold_cnt,
Taddr_hold_load => taddr_hold_ld_i,
Tdata_hold_load => tdata_hold_ld_i,
Tcontrol_load => tcontrol_ld_i,
Tdev_valid_load => tdev_valid_ld_i,
Tdev_rdy_load => tdev_rdy_ld_i,
Tads_load => tads_ld_i,
Twr_recovery_load => twr_recovery_ld_i,
Trd_recovery_load => trd_recovery_ld_i,
Taddr_hold_load_ce => taddr_hold_ld_ce_i,
Tdata_hold_load_ce => tdata_hold_ld_ce_i,
Tcontrol_load_ce => tcontrol_ld_ce_i,
Tdev_valid_load_ce => tdev_valid_ld_ce_i,
Tdev_rdy_load_ce => tdev_rdy_ld_ce_i,
Tads_load_ce => tads_ld_ce_i,
Twr_muxed_recovery_load_ce => twr_muxed_recovery_load_ce_i,
Trd_muxed_recovery_load_ce => trd_muxed_recovery_load_ce_i,
Twr_non_muxed_recovery_load_ce => twr_non_muxed_recovery_load_ce_i,
Trd_non_muxed_recovery_load_ce => trd_non_muxed_recovery_load_ce_i,
Clk => Clk,
Rst => rst
);
end generate SOME_DEV_ASYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: NO_DEV_ASYNC_GEN
-------------------------------------------------------------------------------
-- Description: All devices are configured as synchronous devices
-------------------------------------------------------------------------------
NO_DEV_ASYNC_GEN: if NO_PRH_ASYNC = 1 generate
Asynch_Wrack <= '0';
Asynch_Rdack <= '0';
Asynch_error <= '0';
Asynch_Wr <= '1';
Asynch_Rd <= '1';
Asynch_en <= '0';
Asynch_addr_strobe <= '0';
Asynch_addr_data_sel<= '0';
Asynch_data_sel <= '0';
Asynch_chip_select <= (others => '1');
Asynch_addr_cnt_ld <= '0';
Asynch_addr_cnt_en <= '0';
end generate NO_DEV_ASYNC_GEN;
end imp;
------------------------------------------------------------------------------
-- End of async_cntl.vhd file
------------------------------------------------------------------------------
| gpl-3.0 | dfbb0353ea221a103c6154c2af15bb36 | 0.564818 | 3.107988 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rom_8192x32/example_design/rom_8192x32_exdes.vhd | 1 | 4,354 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
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-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rom_8192x32_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_8192x32_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END rom_8192x32_exdes;
ARCHITECTURE xilinx OF rom_8192x32_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT rom_8192x32 IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : rom_8192x32
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| gpl-2.0 | b2b8d430d877ea5fe5489739a2dfab0c | 0.576022 | 4.748092 | false | false | false | false |
esar/hdmilight-v1 | fpga/avg4.vhd | 2 | 5,471 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hscale4 is
Port ( CLK : in STD_LOGIC;
D_HSYNC : in STD_LOGIC;
D_VSYNC : in STD_LOGIC;
D_R : in STD_LOGIC_VECTOR (7 downto 0);
D_G : in STD_LOGIC_VECTOR (7 downto 0);
D_B : in STD_LOGIC_VECTOR (7 downto 0);
Q_HSYNC : out STD_LOGIC;
Q_VSYNC : out STD_LOGIC;
CE2 : out STD_LOGIC;
CE4 : out STD_LOGIC;
Q_R : out STD_LOGIC_VECTOR (7 downto 0);
Q_G : out STD_LOGIC_VECTOR (7 downto 0);
Q_B : out STD_LOGIC_VECTOR (7 downto 0));
end hscale4;
architecture Behavioral of hscale4 is
signal COUNT : std_logic_vector(1 downto 0);
signal HSYNC_LAST : std_logic;
signal R1 : std_logic_vector(7 downto 0);
signal R2 : std_logic_vector(7 downto 0);
signal R3 : std_logic_vector(7 downto 0);
signal RSUM1 : std_logic_vector(8 downto 0);
signal RSUM2 : std_logic_vector(8 downto 0);
signal RSUM3 : std_logic_vector(8 downto 0);
signal RAVG : std_logic_vector(7 downto 0);
signal G1 : std_logic_vector(7 downto 0);
signal G2 : std_logic_vector(7 downto 0);
signal G3 : std_logic_vector(7 downto 0);
signal GSUM1 : std_logic_vector(8 downto 0);
signal GSUM2 : std_logic_vector(8 downto 0);
signal GSUM3 : std_logic_vector(8 downto 0);
signal GAVG : std_logic_vector(7 downto 0);
signal B1 : std_logic_vector(7 downto 0);
signal B2 : std_logic_vector(7 downto 0);
signal B3 : std_logic_vector(7 downto 0);
signal BSUM1 : std_logic_vector(8 downto 0);
signal BSUM2 : std_logic_vector(8 downto 0);
signal BSUM3 : std_logic_vector(8 downto 0);
signal BAVG : std_logic_vector(7 downto 0);
signal HSYNC1 : std_logic;
signal HSYNC2 : std_logic;
signal HSYNC3 : std_logic;
signal HSYNC4 : std_logic;
signal HSYNC5 : std_logic;
signal HSYNC6 : std_logic;
signal HSYNC7 : std_logic;
signal VSYNC1 : std_logic;
signal VSYNC2 : std_logic;
signal VSYNC3 : std_logic;
signal VSYNC4 : std_logic;
signal VSYNC5 : std_logic;
signal VSYNC6 : std_logic;
signal VSYNC7 : std_logic;
begin
process(CLK)
begin
if(rising_edge(CLK)) then
if(D_HSYNC = '0' and HSYNC_LAST = '1') then
COUNT <= (others => '0');
else
COUNT <= std_logic_vector(unsigned(COUNT) + 1);
end if;
HSYNC_LAST <= D_HSYNC;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
R3 <= R2;
R2 <= R1;
R1 <= D_R;
RSUM1 <= std_logic_vector(unsigned('0' & D_R) + unsigned('0' & R1));
RSUM2 <= std_logic_vector(unsigned('0' & R2) + unsigned('0' & R3));
RSUM3 <= std_logic_vector(unsigned('0' & RSUM1(8 downto 1)) + unsigned('0' & RSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "01") then
RAVG <= RSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
G3 <= G2;
G2 <= G1;
G1 <= D_G;
GSUM1 <= std_logic_vector(unsigned('0' & D_G) + unsigned('0' & G1));
GSUM2 <= std_logic_vector(unsigned('0' & G2) + unsigned('0' & G3));
GSUM3 <= std_logic_vector(unsigned('0' & GSUM1(8 downto 1)) + unsigned('0' & GSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "11") then
GAVG <= GSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
B3 <= B2;
B2 <= B1;
B1 <= D_B;
BSUM1 <= std_logic_vector(unsigned('0' & D_B) + unsigned('0' & B1));
BSUM2 <= std_logic_vector(unsigned('0' & B2) + unsigned('0' & B3));
BSUM3 <= std_logic_vector(unsigned('0' & BSUM1(8 downto 1)) + unsigned('0' & BSUM2(8 downto 1)));
if(COUNT(1 downto 0) = "11") then
BAVG <= BSUM3(8 downto 1);
end if;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
HSYNC7 <= HSYNC6;
HSYNC6 <= HSYNC5;
HSYNC5 <= HSYNC4;
HSYNC4 <= HSYNC3;
HSYNC3 <= HSYNC2;
HSYNC2 <= HSYNC1;
HSYNC1 <= D_HSYNC;
end if;
end process;
process(CLK)
begin
if(rising_edge(CLK)) then
VSYNC7 <= VSYNC6;
VSYNC6 <= VSYNC5;
VSYNC5 <= VSYNC4;
VSYNC4 <= VSYNC3;
VSYNC3 <= VSYNC2;
VSYNC2 <= VSYNC1;
VSYNC1 <= D_VSYNC;
end if;
end process;
Q_HSYNC <= HSYNC7;
Q_VSYNC <= VSYNC7;
Q_R <= RAVG;
Q_G <= GAVG;
Q_B <= BAVG;
CE2 <= COUNT(0);
CE4 <= COUNT(1);
end Behavioral;
| gpl-2.0 | d17f506df170f50c3ec085428b05b194 | 0.621276 | 2.927234 | false | false | false | false |
peteut/nvc | test/regress/bitvec.vhd | 2 | 748 | entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
variable n : integer;
begin
b := "1101";
n := 2;
wait for 1 ns;
assert not b = "0010";
assert (b and "1010") = "1000";
assert (b or "0110") = "1111";
assert (b xor "0111") = "1010";
assert (b xnor "0111") = "0101";
assert (b nand "1010") = "0111";
assert (b nor "0110") = "0000";
assert get_bitvec(1, n) = "00";
wait;
end process;
end architecture;
| gpl-3.0 | 135661ae59f04618b0250c5061b45eb7 | 0.518717 | 3.545024 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_pkg.vhd | 1 | 11,396 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE counter_fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT counter_fifo_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT counter_fifo_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT counter_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT counter_fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT counter_fifo_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT counter_fifo_exdes IS
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END counter_fifo_pkg;
PACKAGE BODY counter_fifo_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END counter_fifo_pkg;
| gpl-2.0 | 7f9726ce15b539485d91ca97881a9879 | 0.506932 | 3.951456 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_family.vhd | 1 | 23,012 | -------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_family.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_family.vhd
--
-- Description:
-- This HDL file provides various functions for determining features (such
-- as BRAM types) in the various device families in Xilinx products.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- cpu_xadc_wiz_0_0_family.vhd
--
-------------------------------------------------------------------------------
-- Revision history
--
-- ??? ?????????? Initial version
-- jam 03/31/2003 added spartan3 to constants and derived function. Added
-- comments to try and explain how the function is used
-- jam 04/01/2003 removed VIRTEX from the derived list for BYZANTIUM,
-- VIRTEX2P, and SPARTAN3. This changes VIRTEX2 to be a
-- base family type, similar to X4K and VIRTEX
-- jam 04/02/2003 add VIRTEX back into the hierarchy of VIRTEX2P, BYZANTIUM
-- and SPARTAN3; add additional comments showing use in
-- VHDL
-- lss 03/24/2004 Added QVIRTEX2, QRVIRTEX2, VIRTEX4
-- flo 03/22/2005 Added SPARTAN3E
-- als 02/23/2006 Added VIRTEX5
-- flo 09/13/2006 Added SPARTAN3A and SPARTAN3A. This may allow
-- legacy designs to support spartan3a and spartan3an in
-- terms of BRAMs. For new work (and maintenence where
-- possible) this package, family, should be dropped in favor
-- of the package, family_support.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- @BEGIN_CHANGELOG EDK_H_SP1
-- Added spartan3e
-- @END_CHANGELOG
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
package cpu_xadc_wiz_0_0_family is
-- constant declarations
constant ANY : string := "any";
constant X4K : string := "x4k";
constant X4KE : string := "x4ke";
constant X4KL : string := "x4kl";
constant X4KEX : string := "x4kex";
constant X4KXL : string := "x4kxl";
constant X4KXV : string := "x4kxv";
constant X4KXLA : string := "x4kxla";
constant SPARTAN : string := "spartan";
constant SPARTANXL : string := "spartanxl";
constant SPARTAN2 : string := "spartan2";
constant SPARTAN2E : string := "spartan2e";
constant VIRTEX : string := "virtex";
constant VIRTEXE : string := "virtexe";
constant VIRTEX2 : string := "virtex2";
constant VIRTEX2P : string := "virtex2p";
constant BYZANTIUM : string := "byzantium";
constant SPARTAN3 : string := "spartan3";
constant QRVIRTEX2 : string := "qrvirtex2";
constant QVIRTEX2 : string := "qvirtex2";
constant VIRTEX4 : string := "virtex4";
constant VIRTEX5 : string := "virtex5";
constant SPARTAN3E : string := "spartan3e";
constant SPARTAN3A : string := "spartan3a";
constant SPARTAN3AN: string := "spartan3an";
-- function declarations
-- derived - provides a means to determine if a family specified in child is
-- the same as, or is a super set of, the family specified in
-- ancestor.
--
-- Typically, child is set to the generic specifying the family type
-- the user wishes to implement the design into (C_FAMILY), and the
-- designer hard codes ancestor to the family type supported by the
-- design. If the design supports multiple family types, then each
-- of those family types would need to be tested against C_FAMILY
-- using this function. An example for the VIRTEX2P hierarchy
-- is shown below:
--
-- VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2P)
-- generate
-- -- logic specific to Virtex2P family
-- end generate VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2P_SPECIFIC_LOGIC_GEN:
-- if not derived(C_FAMILY,VIRTEX2P)
-- generate
--
-- VIRTEX2_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX2)
-- generate
-- -- logic specific to Virtex2 family
-- end generate VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX2_SPECIFIC_LOGIC_GEN
-- if not derived(C_FAMILY,VIRTEX2)
-- generate
--
-- VIRTEX_SPECIFIC_LOGIC_GEN:
-- if derived(C_FAMILY,VIRTEX)
-- generate
-- -- logic specific to Virtex family
-- end generate VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- NON_VIRTEX_SPECIFIC_LOGIC_GEN;
-- if not derived(C_FAMILY,VIRTEX)
-- generate
--
-- ANY_FAMILY_TYPE_LOGIC_GEN:
-- if derived(C_FAMILY,ANY)
-- generate
-- -- logic not specific to any family
-- end generate ANY_FAMILY_TYPE_LOGIC_GEN;
--
-- end generate NON_VIRTEX_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2_SPECIFIC_LOGIC_GEN;
--
-- end generate NON_VIRTEX2P_SPECIFIC_LOGIC_GEN;
--
-- This function will return TRUE if the family type specified in
-- child is equal to, or a super set of, the family type specified in
-- ancestor, otherwise it returns FALSE.
--
-- The current super sets are defined by the following list, where
-- all family types listed to the right of an item are contained in
-- the super set of that item, for all lines containing that item.
--
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
--
-- For exampel, all other family types are contained in the super set
-- for ANY. Stated another way, if the designer specifies ANY
-- for the family type the design supports, then the function will
-- return TRUE for any family type the user wishes to implement the
-- design into.
--
-- if derived(C_FAMILY,ANY) generate ... end generate;
--
-- If the designer specifies VIRTEX2 as the family type supported by
-- the design, then the function will only return TRUE if the user
-- intends to implement the design in VIRTEX2, VIRTEX2P, BYZANTIUM,
-- or SPARTAN3.
--
-- if derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses VIRTEX2 BRAMs
-- end generate;
--
-- if not derived(C_FAMILY,VIRTEX2) generate
-- -- logic that uses non VIRTEX2 BRAMs
-- end generate;
--
-- Note:
-- The last three lines of the list above were modified from the
-- original to remove VIRTEX from those lines because, from our point
-- of view, VIRTEX2 is different enough from VIRTEX to conclude that
-- it should be its own base family type.
--
-- **************************************************************************
-- WARNING
-- **************************************************************************
-- DO NOT RELY ON THE DERIVED FUNCTION TO PROVIDE DIFFERENTIATION BETWEEN
-- FAMILY TYPES FOR ANYTHING OTHER THAN BRAMS
--
-- Use of the derived function assumes that the designer is not using
-- RLOCs (RLOC'd FIFO's from Coregen, etc.) and that the BRAMs in the
-- derived families are similar. If the designer is using specific
-- elements of a family type, they are responsible for ensuring that
-- those same elements are available in all family types supported by
-- their design, and that the elements function exactly the same in all
-- "similar" families.
--
-- **************************************************************************
--
function derived ( child, ancestor : string ) return boolean;
-- equalIgnoreCase - Returns TRUE if case insensitive string comparison
-- determines that str1 and str2 are equal, otherwise FALSE
function equalIgnoreCase( str1, str2 : string ) return boolean;
-- toLowerCaseChar - Returns the lower case form of char if char is an upper
-- case letter. Otherwise char is returned.
function toLowerCaseChar( char : character ) return character;
end cpu_xadc_wiz_0_0_family;
package body cpu_xadc_wiz_0_0_family is
-- True if architecture "child" is derived from, or equal to,
-- the architecture "ancestor".
-- ANY, X4K, SPARTAN, SPARTANXL
-- ANY, X4K, X4KE, X4KL
-- ANY, X4K, X4KEX, X4KXL, X4KXV, X4KXLA
-- ANY, VIRTEX, SPARTAN2, SPARTAN2E
-- ANY, VIRTEX, VIRTEXE
-- ANY, VIRTEX, VIRTEX2, BYZANTIUM
-- ANY, VIRTEX, VIRTEX2, VIRTEX2P
-- ANY, VIRTEX, VIRTEX2, SPARTAN3
function derived ( child, ancestor : string ) return boolean is
variable is_derived : boolean := FALSE;
begin
if equalIgnoreCase( child, VIRTEX ) then -- base family type
if ( equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2 ) then
if ( equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QRVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QRVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, QVIRTEX2 ) then
if ( equalIgnoreCase(ancestor,QVIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX5 ) then
if ( equalIgnoreCase(ancestor,VIRTEX5) OR
equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX4 ) then
if ( equalIgnoreCase(ancestor,VIRTEX4) OR
equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEX2P ) then
if ( equalIgnoreCase(ancestor,VIRTEX2P) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, BYZANTIUM ) then
if ( equalIgnoreCase(ancestor,BYZANTIUM) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, VIRTEXE ) then
if ( equalIgnoreCase(ancestor,VIRTEXE) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2 ) then
if ( equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN2E ) then
if ( equalIgnoreCase(ancestor,SPARTAN2E) OR
equalIgnoreCase(ancestor,SPARTAN2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3 ) then
if ( equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3E ) then
if ( equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3A ) then
if ( equalIgnoreCase(ancestor,SPARTAN3A) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN3AN ) then
if ( equalIgnoreCase(ancestor,SPARTAN3AN) OR
equalIgnoreCase(ancestor,SPARTAN3E) OR
equalIgnoreCase(ancestor,SPARTAN3) OR
equalIgnoreCase(ancestor,VIRTEX2) OR
equalIgnoreCase(ancestor,VIRTEX) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4K ) then -- base family type
if ( equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KEX ) then
if ( equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXL ) then
if ( equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXV ) then
if ( equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KXLA ) then
if ( equalIgnoreCase(ancestor,X4KXLA) OR
equalIgnoreCase(ancestor,X4KXV) OR
equalIgnoreCase(ancestor,X4KXL) OR
equalIgnoreCase(ancestor,X4KEX) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KE ) then
if ( equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, X4KL ) then
if ( equalIgnoreCase(ancestor,X4KL) OR
equalIgnoreCase(ancestor,X4KE) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTAN ) then
if ( equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, SPARTANXL ) then
if ( equalIgnoreCase(ancestor,SPARTANXL) OR
equalIgnoreCase(ancestor,SPARTAN) OR
equalIgnoreCase(ancestor,X4K) OR
equalIgnoreCase(ancestor,ANY)
) then is_derived := TRUE;
end if;
elsif equalIgnoreCase( child, ANY ) then
if equalIgnoreCase( ancestor, any ) then is_derived := TRUE;
end if;
end if;
return is_derived;
end derived;
-- Returns the lower case form of char if char is an upper case letter.
-- Otherwise char is returned.
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
-- Returns true if case insensitive string comparison determines that
-- str1 and str2 are equal
function equalIgnoreCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoreCase;
end cpu_xadc_wiz_0_0_family;
| gpl-3.0 | e54085ddefaaa39dcec26ecc5150296f | 0.548105 | 4.680089 | false | false | false | false |
peteut/nvc | test/regress/issue349.vhd | 2 | 652 | entity issue349 is
end issue349;
architecture RTL of issue349 is
type WORD_TYPE is record
DATA : bit_vector(7 downto 0);
VAL : boolean;
end record;
constant WORD_NULL : WORD_TYPE := (DATA => (others => '0'),
VAL => TRUE);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
signal curr_queue : WORD_VECTOR(0 to 1);
begin
curr_queue <= (others => WORD_NULL);
process is
begin
wait for 1 ns;
assert curr_queue = (0 to 1 => WORD_NULL);
wait;
end process;
end RTL;
| gpl-3.0 | fe40ad4a007630abedf7813f4d0b485e | 0.501534 | 3.904192 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_synth.vhd | 1 | 9,261 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_mBuf_128x72_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF k7_mBuf_128x72_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(72-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
rst_s_wr3 <= '0';
rst_s_rd <= '0';
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: k7_mBuf_128x72_dgen
GENERIC MAP (
C_DIN_WIDTH => 72,
C_DOUT_WIDTH => 72,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: k7_mBuf_128x72_dverif
GENERIC MAP (
C_DOUT_WIDTH => 72,
C_DIN_WIDTH => 72,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: k7_mBuf_128x72_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 72,
C_DIN_WIDTH => 72,
C_WR_PNTR_WIDTH => 9,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
k7_mBuf_128x72_inst : k7_mBuf_128x72_exdes
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | 680edb200c1b44842f5b87c9e8958937 | 0.455458 | 4.145479 | false | false | false | false |
UnofficialRepos/OSVVM | CoveragePkg.vhd | 1 | 432,269 | --
-- File Name: CoveragePkg.vhd
-- Design Unit Name: CoveragePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
-- Matthias Alles Creonic. Inspired GetMinBinVal, GetMinPoint, GetCov
-- Jerry Kaczynski Aldec. Inspired GetBin function
-- Sebastian Dunst Inspired GetBinName function
-- ... Aldec Worked on VendorCov functional coverage interface
--
-- Package Defines
-- Functional coverage modeling utilities and data structure
--
-- Developed by/for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated NewID with ParentID, ReportMode, Search, PrintParent.
-- Supports searching for coverage models.
-- 01/2022 2022.01 Added DeallocateBins and TCover
-- Updated AddBins and AddCross s.t. can set AtLeast and Weight to 0
-- GenBin defaults AtLeast and Weight to 0. AddBins and AddCross to 1.
-- 12/2021 2021.12 Added ReadCovYaml
-- 11/2021 2021.11 Updated WriteCovYaml to write CovWeight first.
-- Updated GetCov calculation with PercentCov.
-- 10/2021 2021.10 Added WriteCovYaml to write out coverage as a YAML file
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- Moved SetName, SetMessage to deprecated
-- Moved AddBins, AddCross, GenBin, and GenCross with weight parameter to deprecated
-- 07/2021 2021.07 Updated for new data structure
-- 07/2020 2020.07 Adjusted NextPointModeType: Changed MIN to MODE_MINIMUM.
-- The preferred MINIMUM will not work in some tools
-- Added GetNext{Index, BinVal, Point}[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})]
-- Added NextPointModeType = (RANDOM, INCREMENT, MODE_MINIMUM)
-- Added SetNextPointMode[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})
-- 05/2020 2020.05 Updated LastIndex to also be set during ICover.
-- Updated deallocate to set all variables to their initial value
-- Added GetInc{Index, BinVal, Point}
-- Added GetNext{Index, BinVal, Point}[(Mode => {RANDOM|INCREMENT|MIN})]
-- Added NextPointModeType = (RANDOM, INCREMENT, MODE_MINIMUM)
-- Added SetNextPointMode[(Mode => {RANDOM|INCREMENT|MODE_MINIMUM})
-- Added to_std_logic(integer), to_boolean(integer) + vector forms
-- RandCov{Point|BinVal} is deprecated, renamed to GetRand{Point|BinVal}
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Updated PercentCov calculation so AtLeast of <= 0 is correct
-- String' Fix for GHDL
-- Removed Deprecated procedure Increment - see TbUtilPkg as it moved there
-- 05/2017 2017.05 Updated WriteBin name printing
-- ClearCov (deprecates SetCovZero)
-- 11/2016 2016.11 Added VendorCovApiPkg and calls to bind it in.
-- 03/2016 2016.03 Added GetBinName(Index) to retrieve a bin's name
-- 01/2016 2016.01 Fixes for pure functions. Added bounds checking on ICover
-- 06/2015 2015.06 AddCross[CovMatrix?Type], Mirroring for WriteBin
-- 01/2015 2015.01 Use AlertLogPkg to count assertions and filter log messages
-- 12/2014 2014.07a Fix memory leak in deallocate. Removed initialied pointers which can lead to leaks.
-- 7/2014 2014.07 Bin Naming (for requirements tracking), WriteBin with Pass/Fail, GenBin[integer_vector]
-- 1/2014 2014.01 Merging of Cov Models, LastIndex
-- 5/2013 2013.05 Release with updated RandomPkg. Minimal changes.
-- 04/2013: 2013.04 Thresholding, CovTarget, Merging off by default,
-- 01/2012: 2.4 Added Merging of bins
-- 01/2012: 2.3 Added Function GetBin from Jerry K. Made write for RangeArrayType visible
-- 12/2011: 2.2b Fixed minor inconsistencies on interface declarations.
-- 11/2011: 2.2a Changed constants ALL_RANGE, ZERO_BIN, and ONE_BIN to have a 1 index
-- 07/2011: 2.2 Added randomization with coverage goals (AtLeast), weight, and percentage thresholds
-- 06/2011: 2.1 Removed signal based coverage modeling
-- 04/2011: 2.0 Added protected type based data structure: CovPType
-- 02/2011: 1.1 Added GetMinCov, GetMaxCov, CountCovHoles, GetCovHole
-- 02/2011: 1.0 Changed CoverBinType to facilitage long term support of cross coverage
-- 09/2010 Release in SynthWorks' VHDL Testbenches and Verification classes
-- 06/2010: 0.1 Initial revision
--
--
-- Development Notes:
-- The coverage procedures are named ICover to avoid conflicts with
-- future language changes which may add cover as a keyword
-- Procedure WriteBin writes each CovBin on a separate line, as such
-- it was inappropriate to overload either textio write or to_string
-- In the notes VHDL-2008 notes refers to
-- composites with unconstrained elements
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2010 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.math_real.all ;
use std.textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
use work.TextUtilPkg.all ;
use work.TranscriptPkg.all ;
use work.AlertLogPkg.all ;
use work.RandomBasePkg.all ;
use work.RandomProcedurePkg.all ;
use work.RandomPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.MessageListPkg.all ;
use work.OsvvmGlobalPkg.all ;
use work.VendorCovApiPkg.all ;
package CoveragePkg is
type CoverageIDType is record
ID : integer ;
end record CoverageIDType ;
type CoverageIDArrayType is array (integer range <>) of CoverageIDType ;
constant OSVVM_COVERAGE_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- CovPType allocates bins that are multiples of MIN_NUM_BINS
constant MIN_NUM_BINS : integer := 2**7 ; -- power of 2
type RangeType is record
min : integer ;
max : integer ;
end record ;
type RangeArrayType is array (integer range <>) of RangeType ;
constant ALL_RANGE : RangeArrayType := (1=>(Integer'left, Integer'right)) ;
procedure write ( file f : text ; BinVal : RangeArrayType ) ;
procedure write ( variable buf : inout line ; constant BinVal : in RangeArrayType) ;
-- CovBinBaseType.action values.
-- Note that coverage counting depends on these values
constant COV_COUNT : integer := 1 ;
constant COV_IGNORE : integer := 0 ;
constant COV_ILLEGAL : integer := -1 ;
-- -- type OsvvmOptionsType is (OPT_DEFAULT, FALSE, TRUE) ;
-- alias OsvvmOptionsType is work.OsvvmGlobalPkg.OsvvmOptionsType ;
constant COV_OPT_INIT_PARM_DETECT : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
-- -- For backward compatibility. Don't add to other packages.
-- alias DISABLED is work.OsvvmGlobalPkg.DISABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ];
-- alias ENABLED is work.OsvvmGlobalPkg.ENABLED [return work.OsvvmGlobalPkg.OsvvmOptionsType ];
-- Deprecated
-- Used for easy manual entry. Order: min, max, action
-- Intentionally did not use a record to allow other input
-- formats in the future with VHDL-2008 unconstrained arrays
-- of unconstrained elements
-- type CovBinManualType is array (natural range <>) of integer_vector(0 to 2) ;
type CovBinBaseType is record
BinVal : RangeArrayType(1 to 1) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovBinType is array (natural range <>) of CovBinBaseType ;
constant ALL_BIN : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ALL_COUNT : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ALL_ILLEGAL : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_ILLEGAL, Count => 0, AtLeast => 0, Weight => 0 )) ;
constant ALL_IGNORE : CovBinType := (0 => ( BinVal => ALL_RANGE, Action => COV_IGNORE, Count => 0, AtLeast => 0, Weight => 0 )) ;
constant ZERO_BIN : CovBinType := (0 => ( BinVal => (1=>(0,0)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant ONE_BIN : CovBinType := (0 => ( BinVal => (1=>(1,1)), Action => COV_COUNT, Count => 0, AtLeast => 1, Weight => 1 )) ;
constant NULL_BIN : CovBinType(work.RandomBasePkg.NULL_RANGE_TYPE) := (others => ( BinVal => ALL_RANGE, Action => integer'high, Count => 0, AtLeast => integer'high, Weight => integer'high )) ;
type NextPointModeType is (RANDOM, INCREMENT, MODE_MINIMUM) ;
type CountModeType is (COUNT_FIRST, COUNT_ALL) ;
type IllegalModeType is (ILLEGAL_ON, ILLEGAL_FAILURE, ILLEGAL_OFF) ;
-- WeightModeType other than AT_LEAST or REMAIN is deprecated
type WeightModeType is (AT_LEAST, REMAIN, WEIGHT, REMAIN_EXP, REMAIN_SCALED, REMAIN_WEIGHT ) ;
-- In VHDL-2008 CovMatrix?BaseType and CovMatrix?Type will be subsumed
-- by CovBinBaseType and CovBinType with RangeArrayType as an unconstrained array.
type CovMatrix2BaseType is record
BinVal : RangeArrayType(1 to 2) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix2Type is array (natural range <>) of CovMatrix2BaseType ;
type CovMatrix3BaseType is record
BinVal : RangeArrayType(1 to 3) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix3Type is array (natural range <>) of CovMatrix3BaseType ;
type CovMatrix4BaseType is record
BinVal : RangeArrayType(1 to 4) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix4Type is array (natural range <>) of CovMatrix4BaseType ;
type CovMatrix5BaseType is record
BinVal : RangeArrayType(1 to 5) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix5Type is array (natural range <>) of CovMatrix5BaseType ;
type CovMatrix6BaseType is record
BinVal : RangeArrayType(1 to 6) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix6Type is array (natural range <>) of CovMatrix6BaseType ;
type CovMatrix7BaseType is record
BinVal : RangeArrayType(1 to 7) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix7Type is array (natural range <>) of CovMatrix7BaseType ;
type CovMatrix8BaseType is record
BinVal : RangeArrayType(1 to 8) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix8Type is array (natural range <>) of CovMatrix8BaseType ;
type CovMatrix9BaseType is record
BinVal : RangeArrayType(1 to 9) ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
end record ;
type CovMatrix9Type is array (natural range <>) of CovMatrix9BaseType ;
------------------------------------------------------------ VendorCov
-- VendorCov Conversion for Vendor supported functional coverage modeling
function ToVendorCovBinVal (BinVal : RangeArrayType) return VendorCovRangeArrayType ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer ;
function ToMinPoint (A : RangeArrayType) return integer_vector ;
-- BinVal to Minimum Point
------------------------------------------------------------
procedure ToRandPoint(
-- BinVal to Random Point
-- better as a function, however, inout not supported on functions
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer
) ;
------------------------------------------------------------
procedure ToRandPoint(
-- BinVal to Random Point
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer_vector
) ;
------------------------------------------------------------
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) ;
procedure FileCloseWriteBin ;
-- procedure WriteToCovFile (variable buf : inout line) ;
procedure PrintToCovFile(S : string) ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
-- AlertLogID set by NewID
-- procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) ;
-- procedure SetAlertLogID (ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID (ID : CoverageIDType) return AlertLogIDType ;
------------------------------------------------------------
-- Name set by NewID
impure function GetName (ID : CoverageIDType) return String ;
impure function GetCovModelName (ID : CoverageIDType) return String ;
impure function GetNamePlus (ID : CoverageIDType; prefix, suffix : string) return String ;
procedure SetItemBinNames (
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) ;
alias SetFieldName is SetItemBinNames [CoverageIDType,
string, string, string, string, string, string, string, string, string, string,
string, string, string, string, string, string, string, string, string, string] ;
procedure SetCovTarget (ID : CoverageIDType; Percent : real) ;
impure function GetCovTarget (ID : CoverageIDType) return real ;
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) ;
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) ;
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) ;
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) ;
--
-- SetWeightMode with a WeightMode other than AT_LEAST or REMAIN is deprecated
-- SetWeightMode with a WeightScale parameter is deprecated
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) ;
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) ;
impure function GetCovWeight (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- Seeds are initialized by NewID.
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) ;
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string ;
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) ;
impure function GetSeed (ID : CoverageIDType) return RandomSeedType ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Item / Cross Bin Creation and Destruction
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) ;
procedure Deallocate (ID : CoverageIDType) ;
procedure DeallocateBins (CoverID : CoverageIDType) ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
CovBin : CovBinType
) ;
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Recording and Clearing Coverage
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer_vector) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer) ;
procedure TCover (CoverID : CoverageIDType; A : integer) ;
procedure ClearCov (ID : CoverageIDType) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Statistics
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean ;
impure function IsCovered (ID : CoverageIDType) return boolean ;
impure function IsInitialized (ID : CoverageIDType) return boolean ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer ;
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real ;
impure function GetCov (ID : CoverageIDType) return real ;
impure function GetTotalCovCount(ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovCount(ID : CoverageIDType) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real ;
impure function GetMinCount (ID : CoverageIDType) return integer ;
impure function GetMaxCov (ID : CoverageIDType) return real ;
impure function GetMaxCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function CountCovHoles (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Generating Coverage Points, BinValues, and Indices
-- /////////////////////////////////////////
------------------------------------------------------------
-- Return Points
------------------------------------------------------------
-- to be replaced in VHDL-2019 by version that uses RandomSeed as an inout
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer ;
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector ;
------------------------------------------------------------
-- Return Points
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer ;
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType) return integer ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetRandPoint (ID : CoverageIDType) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
impure function GetIncPoint (ID : CoverageIDType) return integer ;
impure function GetIncPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMinPoint (ID : CoverageIDType) return integer ;
impure function GetMinPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMaxPoint (ID : CoverageIDType) return integer ;
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType) return integer ;
impure function GetNextPoint (ID : CoverageIDType) return integer_vector ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function RandCovPoint (ID : CoverageIDType) return integer_vector ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- deprecated RandCovBinVal, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins (ID : CoverageIDType) return integer ;
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer ;
impure function GetRandIndex (ID : CoverageIDType) return integer ;
impure function GetLastIndex (ID : CoverageIDType) return integer ;
impure function GetIncIndex (ID : CoverageIDType) return integer ;
impure function GetMinIndex (ID : CoverageIDType) return integer ;
impure function GetMaxIndex (ID : CoverageIDType) return integer ;
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextIndex (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Accessing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer ;
-- ------------------------------------------------------------
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Printing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- To specify the following, see SetReportOptions
-- WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal
-- WritePrefix, PassName, FailName
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) ; -- With LogLevel
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) ;
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Writing Out RAW Coverage Bin Information
-- Note that read supports merging of coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) ;
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
-- procedure WriteCovDb (ID : CoverageIDType) ;
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Operations across all coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure WriteCovYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) ;
impure function GotCoverage return boolean ;
impure function GetCov (PercentCov : real ) return real ;
impure function GetCov return real ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType ;
variable Valid : out Boolean
) ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType
) ;
--
-- Support for AddBins and AddCross
--
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType ;
-- Each item in range in a separate CovBin
function GenBin(Min, Max, NumBin : integer ) return CovBinType ;
function GenBin(Min, Max : integer) return CovBinType ;
function GenBin(A : integer) return CovBinType ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
A : integer_vector
) return CovBinType ;
function GenBin ( A : integer_vector ) return CovBinType ;
------------------------------------------------------------
function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType ;
------------------------------------------------------------
-- All items in range in a single CovBin
function IllegalBin ( Min, Max : integer ) return CovBinType ;
function IllegalBin ( A : integer ) return CovBinType ;
-- IgnoreBin should never have an AtLeast parameter
------------------------------------------------------------
function IgnoreBin (Min, Max, NumBin : integer) return CovBinType ;
------------------------------------------------------------
function IgnoreBin (Min, Max : integer) return CovBinType ; -- All items in range in a single CovBin
function IgnoreBin (A : integer) return CovBinType ;
-- With VHDL-2008, there will be one GenCross that returns CovBinType
-- and has inputs initialized to NULL_BIN - see AddCross
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type ;
function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type ;
function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type ;
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type ;
------------------------------------------------------------
-- Utilities. Remove if added to std.standard
function to_integer ( B : boolean ) return integer ;
function to_boolean ( I : integer ) return boolean ;
function to_integer ( SL : std_logic ) return integer ;
function to_std_logic ( I : integer ) return std_logic ;
function to_integer_vector ( BV : boolean_vector ) return integer_vector ;
function to_boolean_vector ( IV : integer_vector ) return boolean_vector ;
function to_integer_vector ( SLV : std_logic_vector ) return integer_vector ;
function to_std_logic_vector ( IV : integer_vector ) return std_logic_vector ;
alias to_slv is to_std_logic_vector[integer_vector return std_logic_vector] ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
type CovPType is protected
------------------------------------------------------------
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType ;
impure function GetNumIDs return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) ;
procedure FileCloseWriteBin ;
-- procedure WriteToCovFile (variable buf : inout line) ;
procedure PrintToCovFile(S : string) ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetName (ID : CoverageIDType; Name : String) ;
impure function SetName (ID : CoverageIDType; Name : String) return string ;
procedure DeallocateName (ID : CoverageIDType) ;
impure function GetName (ID : CoverageIDType) return String ;
impure function GetCovModelName (ID : CoverageIDType) return String ;
impure function GetNamePlus (ID : CoverageIDType; prefix, suffix : string) return String ;
procedure SetItemBinNames (
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) ;
------------------------------------------------------------
procedure SetMessage (ID : CoverageIDType; Message : String) ;
procedure DeallocateMessage (ID : CoverageIDType) ;
procedure SetCovTarget (ID : CoverageIDType; Percent : real) ;
impure function GetCovTarget (ID : CoverageIDType) return real ;
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) ;
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) ;
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) ;
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) ;
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) ;
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) ;
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) ;
impure function GetCovWeight (ID : CoverageIDType) return integer ;
------------------------------------------------------------
procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) ;
procedure SetAlertLogID (ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID (ID : CoverageIDType) return AlertLogIDType ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) ;
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string ;
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) ;
impure function GetSeed (ID : CoverageIDType) return RandomSeedType ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Item / Cross Bin Creation and Destruction
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) ;
procedure Deallocate (ID : CoverageIDType) ;
procedure DeallocateBins (CoverID : CoverageIDType) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins (ID : CoverageIDType; Name : String ; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ; -- Weight Deprecated
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Recording and Clearing Coverage
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer_vector) ;
procedure ICover (ID : CoverageIDType; CovPoint : integer) ;
procedure TCover (CoverID : CoverageIDType; A : integer) ;
procedure ClearCov (ID : CoverageIDType) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Statistics
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean ;
impure function IsCovered (ID : CoverageIDType) return boolean ;
impure function IsInitialized (ID : CoverageIDType) return boolean ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer ;
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; PercentCov : real; TotalCovCount : out integer; TotalCovGoal : out integer ) ;
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; TotalCovCount : out integer; TotalCovGoal : out integer ) ;
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real ;
impure function GetCov (ID : CoverageIDType) return real ;
impure function GetTotalCovCount(ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovCount(ID : CoverageIDType) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetTotalCovGoal (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real ;
impure function GetMinCount (ID : CoverageIDType) return integer ;
impure function GetMaxCov (ID : CoverageIDType) return real ;
impure function GetMaxCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function CountCovHoles (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Generating Coverage Points, BinValues, and Indices
-- /////////////////////////////////////////
------------------------------------------------------------
-- Return Points
------------------------------------------------------------
-- to be replaced in VHDL-2019 by version that uses RandomSeed as an inout
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer ;
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector ;
------------------------------------------------------------
-- Return Points
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer ;
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType) return integer ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function GetRandPoint (ID : CoverageIDType) return integer_vector ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
impure function GetIncPoint (ID : CoverageIDType) return integer ;
impure function GetIncPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMinPoint (ID : CoverageIDType) return integer ;
impure function GetMinPoint (ID : CoverageIDType) return integer_vector ;
impure function GetMaxPoint (ID : CoverageIDType) return integer ;
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector ;
impure function GetNextPoint (ID : CoverageIDType) return integer ;
impure function GetNextPoint (ID : CoverageIDType) return integer_vector ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer ;
impure function RandCovPoint (ID : CoverageIDType) return integer_vector ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType ;
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- deprecated RandCovBinVal, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType ;
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins (ID : CoverageIDType) return integer ;
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer ;
impure function GetRandIndex (ID : CoverageIDType) return integer ;
impure function GetLastIndex (ID : CoverageIDType) return integer ;
impure function GetIncIndex (ID : CoverageIDType) return integer ;
impure function GetMinIndex (ID : CoverageIDType) return integer ;
impure function GetMaxIndex (ID : CoverageIDType) return integer ;
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer ;
impure function GetNextIndex (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Accessing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer ;
-- ------------------------------------------------------------
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Printing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- To specify the following, see SetReportOptions
-- WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal
-- WritePrefix, PassName, FailName
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) ; -- With LogLevel
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) ;
------------------------------------------------------------
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) ;
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; PercentCov : real ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Writing Out RAW Coverage Bin Information
-- Note that read supports merging of coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) ;
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
-- procedure WriteCovDb (ID : CoverageIDType) ;
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
procedure WriteCovYaml (FileName : string := ""; Coverage : real ; OpenKind : File_Open_Kind := WRITE_MODE) ;
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) ;
impure function GotCoverage return boolean ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Compatibility Methods - Allows CoveragePkg to Work as a PT still
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
procedure DeallocateName ; -- clear name
impure function GetName return String ;
impure function GetCovModelName return String ;
------------------------------------------------------------
procedure SetMessage (Message : String) ;
procedure DeallocateMessage ; -- clear message
procedure SetCovTarget (Percent : real) ; -- 2.5
impure function GetCovTarget return real ; -- 2.5
procedure SetThresholding (A : boolean := TRUE ) ; -- 2.5
procedure SetCovThreshold (Percent : real) ;
procedure SetMerging (A : boolean := TRUE ) ; -- 2.5
procedure SetCountMode (A : CountModeType) ;
procedure SetIllegalMode (A : IllegalModeType) ;
procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) ;
procedure SetNextPointMode (A : NextPointModeType) ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) ;
procedure SetAlertLogID (Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
procedure InitSeed (S : string ) ;
impure function InitSeed (S : string ) return string ;
procedure InitSeed (I : integer ) ;
------------------------------------------------------------
procedure SetSeed (RandomSeedIn : RandomSeedType ) ;
impure function GetSeed return RandomSeedType ;
------------------------------------------------------------
procedure SetBinSize (NewNumBins : integer) ;
procedure Deallocate ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins ( Name : String ; AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins ( Name : String ; CovBin : CovBinType) ;
procedure AddBins ( AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ;
procedure AddBins ( AtLeast : integer ; CovBin : CovBinType ) ;
procedure AddBins ( CovBin : CovBinType ) ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
procedure AddCross(
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
procedure AddCross (CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddCross (CovBin : CovMatrix9Type ; Name : String := "") ;
------------------------------------------------------------
-- Recording and Clearing Coverage
procedure ICoverLast ;
procedure ICover( CovPoint : integer) ;
procedure ICover( CovPoint : integer_vector) ;
procedure TCover( A : integer) ;
procedure ClearCov ;
procedure SetCovZero ; -- Deprecated
------------------------------------------------------------
-- Coverage Information and Statistics
impure function IsCovered return boolean ;
impure function IsCovered ( PercentCov : real ) return boolean ;
impure function IsInitialized return boolean ;
------------------------------------------------------------
impure function GetItemCount return integer ;
impure function GetCov ( PercentCov : real ) return real ;
impure function GetCov return real ; -- PercentCov of entire model/all bins
impure function GetTotalCovCount ( PercentCov : real ) return integer ;
impure function GetTotalCovCount return integer ;
impure function GetTotalCovGoal ( PercentCov : real ) return integer ;
impure function GetTotalCovGoal return integer ;
------------------------------------------------------------
impure function GetMinCov return real ; -- PercentCov
impure function GetMinCount return integer ; -- Count
impure function GetMaxCov return real ; -- PercentCov
impure function GetMaxCount return integer ; -- Count
------------------------------------------------------------
impure function CountCovHoles ( PercentCov : real ) return integer ;
impure function CountCovHoles return integer ;
------------------------------------------------------------
-- Return Points
impure function GetPoint ( BinIndex : integer ) return integer ;
impure function GetPoint ( BinIndex : integer ) return integer_vector ;
impure function GetRandPoint return integer ;
impure function GetRandPoint ( PercentCov : real ) return integer ;
impure function GetRandPoint return integer_vector ;
impure function GetRandPoint ( PercentCov : real ) return integer_vector ;
impure function GetIncPoint return integer ;
impure function GetIncPoint return integer_vector ;
impure function GetMinPoint return integer ;
impure function GetMinPoint return integer_vector ;
impure function GetMaxPoint return integer ;
impure function GetMaxPoint return integer_vector ;
impure function GetNextPoint return integer ;
impure function GetNextPoint return integer_vector ;
impure function GetNextPoint(Mode : NextPointModeType) return integer ;
impure function GetNextPoint(Mode : NextPointModeType) return integer_vector ;
-- RandCovPoint is deprecated, renamed to GetRandPoint
impure function RandCovPoint return integer ;
impure function RandCovPoint ( PercentCov : real ) return integer ;
impure function RandCovPoint return integer_vector ;
impure function RandCovPoint ( PercentCov : real ) return integer_vector ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal ( BinIndex : integer ) return RangeArrayType ;
impure function GetRandBinVal return RangeArrayType ;
impure function GetRandBinVal ( PercentCov : real ) return RangeArrayType ;
impure function GetLastBinVal return RangeArrayType ;
impure function GetIncBinVal return RangeArrayType ;
impure function GetMinBinVal return RangeArrayType ;
impure function GetMaxBinVal return RangeArrayType ;
impure function GetNextBinVal return RangeArrayType ;
impure function GetNextBinVal(Mode : NextPointModeType) return RangeArrayType ;
impure function GetHoleBinVal ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal ( PercentCov : real ) return RangeArrayType ;
impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- RandCovBinVal is deprecated, renamed to GetRandBinVal
impure function RandCovBinVal return RangeArrayType ;
impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType ; -- deprecated, see GetRandBinVal
------------------------------------------------------------
-- Return Index
impure function GetNumBins return integer ;
impure function GetRandIndex return integer ;
impure function GetRandIndex ( CovTargetPercent : real ) return integer ;
impure function GetLastIndex return integer ;
impure function GetIncIndex return integer ;
impure function GetMinIndex return integer ;
impure function GetMaxIndex return integer ;
impure function GetNextIndex return integer ;
impure function GetNextIndex(Mode : NextPointModeType) return integer ;
-- GetBin returns an internal value of the coverage data structure
-- The return value may change as the package evolves
-- Use it only for debugging.
-- GetBinInfo is a for development only.
impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType ;
impure function GetBinValLength return integer ;
impure function GetBin ( BinIndex : integer ) return CovBinBaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType ;
impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType ;
impure function GetBinName ( BinIndex : integer; DefaultName : string := "" ) return string ;
impure function GetErrorCount return integer ;
------------------------------------------------------------
procedure WriteBin (
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
LogLevel : LogType ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
procedure WriteBin (
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
LogLevel : LogType ;
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure DumpBin (LogLevel : LogType := DEBUG) ; -- Development only
procedure WriteCovHoles ( LogLevel : LogType := ALWAYS ) ;
procedure WriteCovHoles ( PercentCov : real ) ;
procedure WriteCovHoles ( LogLevel : LogType; PercentCov : real ) ;
procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles ( LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure ReadCovDb (FileName : string; Merge : boolean := FALSE) ;
procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) ;
------------------------------------------------------------
-- Remaining are Deprecated
--
-- Deprecated/Subsumed by versions with PercentCov Parameter (rather than AtLeast value)
impure function RandCovPoint (AtLeast : integer ) return integer ;
impure function RandCovPoint (AtLeast : integer ) return integer_vector ;
impure function RandCovBinVal (AtLeast : integer ) return RangeArrayType ;
impure function RandCovHole (AtLeast : integer ) return RangeArrayType ;
impure function CountCovHoles (AtLeast : integer ) return integer ;
impure function IsCovered (AtLeast : integer ) return boolean ;
impure function GetHoleBinVal (ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ;
impure function GetCovHole (ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType ;
procedure WriteCovHoles (AtLeast : integer ) ;
procedure WriteCovHoles (LogLevel : LogType; AtLeast : integer ) ;
procedure WriteCovHoles (FileName : string; AtLeast : integer; OpenKind : File_Open_Kind := APPEND_MODE ) ;
procedure WriteCovHoles (LogLevel : LogType; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) ;
-- Deprecated. Replaced by SetMessage
procedure SetItemName (ItemNameIn : String) ; -- Replaced by SetMessage
-- Deprecated. Replaced by GetErrorCount
impure function CovBinErrCnt return integer ; -- Replaced by GetErrorCount
-- Deprecated. Replaced by GetRandBinVal/RandCovBinVal
impure function RandCovHole (PercentCov : real) return RangeArrayType ; -- Deprecated
impure function RandCovHole return RangeArrayType ; -- Deprecated
-- Deprecated. Replaced by GetHoleBinVal
impure function GetCovHole (ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType ;
impure function GetCovHole (PercentCov : real ) return RangeArrayType ;
impure function GetCovHole (ReqHoleNum : integer := 1 ) return RangeArrayType ;
-- Deprecated. Replaced by GetMinCount / GetMaxCount
impure function GetMinCov return integer ; -- Replaced by GetMinCount
impure function GetMaxCov return integer ; -- Replaced by GetMaxCount
-- Deprecated. Replaced by AddCross.
procedure AddBins (CovBin : CovMatrix2Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix3Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix4Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix5Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix6Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix7Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix8Type ; Name : String := "") ;
procedure AddBins (CovBin : CovMatrix9Type ; Name : String := "") ;
end protected CovPType ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType ;
variable ErrorCount : inout integer
) ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType
) ;
------------------------------------------------------------
-- Deprecated items
-- The following will be removed from the package in the future.
--
------------------------------------------------------------
-- SetName is deprecated, see NewID
procedure SetName (ID : CoverageIDType; Name : String) ;
impure function SetName (ID : CoverageIDType; Name : String) return string ;
procedure DeallocateName (ID : CoverageIDType) ;
------------------------------------------------------------
-- SetMessage is deprecated, see PrintToCovFile
procedure SetMessage (ID : CoverageIDType; Message : String) ;
procedure DeallocateMessage (ID : CoverageIDType) ;
------------------------------------------------------------
-- DumpBin is deprecated
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) ; -- Weight Deprecated
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) ;
------------------------------------------------------------
-- Weight Parameter is deprecated
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType ;
------------------------------------------------------------
-- Weight Parameter is deprecated
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
A : integer_vector
) return CovBinType ;
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type ;
end package CoveragePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body CoveragePkg is
------------------------------------------------------------
-- package local
function ActionToName(Action : integer) return string is
------------------------------------------------------------
begin
case Action is
when 1 => return "COUNT" ;
when 0 => return "IGNORE" ;
when others => return "ILLEGAL" ;
end case ;
end function ActionToName ;
------------------------------------------------------------
function inside (
-- package local
------------------------------------------------------------
CovPoint : integer_vector ;
BinVal : RangeArrayType
) return boolean is
alias iCovPoint : integer_vector(BinVal'range) is CovPoint ;
begin
for i in BinVal'range loop
if not (iCovPoint(i) >= BinVal(i).min and iCovPoint(i) <= BinVal(i).max) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function inside ;
------------------------------------------------------------
function inside (
-- package local, used by InsertBin
-- True when BinVal1 is inside BinVal2
------------------------------------------------------------
BinVal1 : RangeArrayType ;
BinVal2 : RangeArrayType
) return boolean is
alias iBinVal2 : RangeArrayType(BinVal1'range) is BinVal2 ;
begin
for i in BinVal1'range loop
if not (BinVal1(i).min >= iBinVal2(i).min and BinVal1(i).max <= iBinVal2(i).max) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function inside ;
------------------------------------------------------------
procedure write (
variable buf : inout line ;
CovPoint : integer_vector
) is
-- package local. called by ICover
------------------------------------------------------------
alias iCovPoint : integer_vector(1 to CovPoint'length) is CovPoint ;
begin
write(buf, "(" & integer'image(iCovPoint(1)) ) ;
for i in 2 to iCovPoint'right loop
write(buf, "," & integer'image(iCovPoint(i)) ) ;
end loop ;
swrite(buf, ")") ;
end procedure write ;
------------------------------------------------------------
procedure write ( file f : text ; BinVal : RangeArrayType ) is
-- called by WriteBin and WriteCovHoles
------------------------------------------------------------
begin
for i in BinVal'range loop
if BinVal(i).min = BinVal(i).max then
write(f, "(" & integer'image(BinVal(i).min) & ") " ) ;
elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then
write(f, "(ALL) " ) ;
else
write(f, "(" & integer'image(BinVal(i).min) & " to " &
integer'image(BinVal(i).max) & ") " ) ;
end if ;
end loop ;
end procedure write ;
------------------------------------------------------------
procedure write (
-- called by WriteBin and WriteCovHoles
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType
) is
------------------------------------------------------------
begin
for i in BinVal'range loop
if BinVal(i).min = BinVal(i).max then
write(buf, "(" & integer'image(BinVal(i).min) & ") " ) ;
elsif (BinVal(i).min = integer'left) and (BinVal(i).max = integer'right) then
swrite(buf, "(ALL) " ) ;
else
write(buf, "(" & integer'image(BinVal(i).min) & " to " &
integer'image(BinVal(i).max) & ") " ) ;
end if ;
end loop ;
end procedure write ;
------------------------------------------------------------
procedure WriteBinVal (
-- package local for now
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType
) is
begin
for i in BinVal'range loop
write(buf, BinVal(i).min) ;
write(buf, ' ') ;
write(buf, BinVal(i).max) ;
write(buf, ' ') ;
end loop ;
end procedure WriteBinVal ;
------------------------------------------------------------
-- package local for now
procedure read (
-- if public, also create one that does not use valid flag
------------------------------------------------------------
variable buf : inout line ;
variable BinVal : out RangeArrayType ;
variable Valid : out boolean
) is
variable ReadValid : boolean ;
begin
for i in BinVal'range loop
read(buf, BinVal(i).min, ReadValid) ;
exit when not ReadValid ;
read(buf, BinVal(i).max, ReadValid) ;
exit when not ReadValid ;
end loop ;
Valid := ReadValid ;
end procedure read ;
------------------------------------------------------------
function CalcPercentCov( Count : integer ; AtLeast : integer ) return real is
-- package local, called by MergeBin, InsertBin, ClearCov, ReadCovDbDatabase
------------------------------------------------------------
variable PercentCov : real ;
begin
if AtLeast > 0 then
return real(Count)*100.0/real(AtLeast) ;
elsif AtLeast = 0 then
return 100.0 ;
else
return real'right ;
end if ;
end function CalcPercentCov ;
-- ------------------------------------------------------------
function BinLengths (
-- package local, used by AddCross, GenCross
-- ------------------------------------------------------------
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) return integer_vector is
variable result : integer_vector(1 to 20) := (others => 0 ) ;
variable i : integer := result'left ;
variable Len : integer ;
begin
loop
case i is
when 1 => Len := Bin1'length ;
when 2 => Len := Bin2'length ;
when 3 => Len := Bin3'length ;
when 4 => Len := Bin4'length ;
when 5 => Len := Bin5'length ;
when 6 => Len := Bin6'length ;
when 7 => Len := Bin7'length ;
when 8 => Len := Bin8'length ;
when 9 => Len := Bin9'length ;
when 10 => Len := Bin10'length ;
when 11 => Len := Bin11'length ;
when 12 => Len := Bin12'length ;
when 13 => Len := Bin13'length ;
when 14 => Len := Bin14'length ;
when 15 => Len := Bin15'length ;
when 16 => Len := Bin16'length ;
when 17 => Len := Bin17'length ;
when 18 => Len := Bin18'length ;
when 19 => Len := Bin19'length ;
when 20 => Len := Bin20'length ;
when others => Len := 0 ;
end case ;
result(i) := Len ;
exit when Len = 0 ;
i := i + 1 ;
exit when i = 21 ;
end loop ;
return result(1 to (i-1)) ;
end function BinLengths ;
-- ------------------------------------------------------------
function CalcNumCrossBins ( BinLens : integer_vector ) return integer is
-- package local, used by AddCross
-- ------------------------------------------------------------
variable result : integer := 1 ;
begin
for i in BinLens'range loop
result := result * BinLens(i) ;
end loop ;
return result ;
end function CalcNumCrossBins ;
-- ------------------------------------------------------------
procedure IncBinIndex (
-- package local, used by AddCross
-- ------------------------------------------------------------
variable BinIndex : inout integer_vector ;
constant BinLens : in integer_vector
) is
alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ;
alias aBinLens : integer_vector(aBinIndex'range) is BinLens ;
begin
-- increment right most one, then if overflow, increment next
-- assumes bins numbered from 1 to N. - assured by ConcatenateBins
for i in aBinIndex'reverse_range loop
aBinIndex(i) := aBinIndex(i) + 1 ;
exit when aBinIndex(i) <= aBinLens(i) ;
aBinIndex(i) := 1 ;
end loop ;
end procedure IncBinIndex ;
-- ------------------------------------------------------------
function ConcatenateBins (
-- package local, used by AddCross and GenCross
-- ------------------------------------------------------------
BinIndex : integer_vector ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) return CovBinType is
alias aBin1 : CovBinType (1 to Bin1'length) is Bin1 ;
alias aBin2 : CovBinType (1 to Bin2'length) is Bin2 ;
alias aBin3 : CovBinType (1 to Bin3'length) is Bin3 ;
alias aBin4 : CovBinType (1 to Bin4'length) is Bin4 ;
alias aBin5 : CovBinType (1 to Bin5'length) is Bin5 ;
alias aBin6 : CovBinType (1 to Bin6'length) is Bin6 ;
alias aBin7 : CovBinType (1 to Bin7'length) is Bin7 ;
alias aBin8 : CovBinType (1 to Bin8'length) is Bin8 ;
alias aBin9 : CovBinType (1 to Bin9'length) is Bin9 ;
alias aBin10 : CovBinType (1 to Bin10'length) is Bin10 ;
alias aBin11 : CovBinType (1 to Bin11'length) is Bin11 ;
alias aBin12 : CovBinType (1 to Bin12'length) is Bin12 ;
alias aBin13 : CovBinType (1 to Bin13'length) is Bin13 ;
alias aBin14 : CovBinType (1 to Bin14'length) is Bin14 ;
alias aBin15 : CovBinType (1 to Bin15'length) is Bin15 ;
alias aBin16 : CovBinType (1 to Bin16'length) is Bin16 ;
alias aBin17 : CovBinType (1 to Bin17'length) is Bin17 ;
alias aBin18 : CovBinType (1 to Bin18'length) is Bin18 ;
alias aBin19 : CovBinType (1 to Bin19'length) is Bin19 ;
alias aBin20 : CovBinType (1 to Bin20'length) is Bin20 ;
alias aBinIndex : integer_vector(1 to BinIndex'length) is BinIndex ;
variable result : CovBinType(aBinIndex'range) ;
begin
for i in aBinIndex'range loop
case i is
when 1 => result(i) := aBin1(aBinIndex(i)) ;
when 2 => result(i) := aBin2(aBinIndex(i)) ;
when 3 => result(i) := aBin3(aBinIndex(i)) ;
when 4 => result(i) := aBin4(aBinIndex(i)) ;
when 5 => result(i) := aBin5(aBinIndex(i)) ;
when 6 => result(i) := aBin6(aBinIndex(i)) ;
when 7 => result(i) := aBin7(aBinIndex(i)) ;
when 8 => result(i) := aBin8(aBinIndex(i)) ;
when 9 => result(i) := aBin9(aBinIndex(i)) ;
when 10 => result(i) := aBin10(aBinIndex(i)) ;
when 11 => result(i) := aBin11(aBinIndex(i)) ;
when 12 => result(i) := aBin12(aBinIndex(i)) ;
when 13 => result(i) := aBin13(aBinIndex(i)) ;
when 14 => result(i) := aBin14(aBinIndex(i)) ;
when 15 => result(i) := aBin15(aBinIndex(i)) ;
when 16 => result(i) := aBin16(aBinIndex(i)) ;
when 17 => result(i) := aBin17(aBinIndex(i)) ;
when 18 => result(i) := aBin18(aBinIndex(i)) ;
when 19 => result(i) := aBin19(aBinIndex(i)) ;
when 20 => result(i) := aBin20(aBinIndex(i)) ;
when others =>
-- pure functions cannot use alert and/or print
report "CoveragePkg.AddCross: More than 20 bins not supported"
severity FAILURE ;
end case ;
end loop ;
return result ;
end function ConcatenateBins ;
------------------------------------------------------------
function MergeState( CrossBins : CovBinType) return integer is
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
variable resultState : integer ;
begin
resultState := COV_COUNT ;
for i in CrossBins'range loop
if CrossBins(i).action = COV_ILLEGAL then
return COV_ILLEGAL ;
end if ;
if CrossBins(i).action = COV_IGNORE then
resultState := COV_IGNORE ;
end if ;
end loop ;
return resultState ;
end function MergeState ;
------------------------------------------------------------
function MergeBinVal( CrossBins : CovBinType) return RangeArrayType is
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
alias aCrossBins : CovBinType(1 to CrossBins'length) is CrossBins ;
variable BinVal : RangeArrayType(aCrossBins'range) ;
begin
for i in aCrossBins'range loop
BinVal(i to i) := aCrossBins(i).BinVal ;
end loop ;
return BinVal ;
end function MergeBinVal ;
------------------------------------------------------------
function MergeAtLeast(
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
Action : in integer ;
AtLeast : in integer ;
CrossBins : in CovBinType
) return integer is
variable Result : integer := AtLeast ;
begin
if Action /= COV_COUNT then
return 0 ;
end if ;
for i in CrossBins'range loop
if CrossBins(i).Action = Action then
Result := maximum (Result, CrossBins(i).AtLeast) ;
end if ;
end loop ;
return result ;
end function MergeAtLeast ;
------------------------------------------------------------
function MergeWeight(
-- package local, Used by AddCross, GenCross
------------------------------------------------------------
Action : in integer ;
Weight : in integer ;
CrossBins : in CovBinType
) return integer is
variable Result : integer := Weight ;
begin
if Action /= COV_COUNT then
return 0 ;
end if ;
for i in CrossBins'range loop
if CrossBins(i).Action = Action then
Result := maximum (Result, CrossBins(i).Weight) ;
end if ;
end loop ;
return result ;
end function MergeWeight ;
------------------------------------------------------------ VendorCov
-- VendorCov Conversion for Vendor supported functional coverage modeling
function ToVendorCovBinVal (BinVal : RangeArrayType) return VendorCovRangeArrayType is
------------------------------------------------------------
variable VendorCovBinVal : VendorCovRangeArrayType(BinVal'range);
begin -- VendorCov
for ArrIdx in BinVal'LEFT to BinVal'RIGHT loop -- VendorCov
VendorCovBinVal(ArrIdx) := (min => BinVal(ArrIdx).min, -- VendorCov
max => BinVal(ArrIdx).max) ; -- VendorCov
end loop; -- VendorCov
return VendorCovBinVal ;
end function ToVendorCovBinVal ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer is
-- Used in testing
------------------------------------------------------------
begin
return A(A'left).min ;
end function ToMinPoint ;
------------------------------------------------------------
function ToMinPoint (A : RangeArrayType) return integer_vector is
-- Used in testing
------------------------------------------------------------
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i).min ;
end loop ;
return result ;
end function ToMinPoint ;
------------------------------------------------------------
procedure ToRandPoint(
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer
) is
begin
result := RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
end procedure ToRandPoint ;
------------------------------------------------------------
procedure ToRandPoint(
------------------------------------------------------------
variable RV : inout RandomPType ;
constant BinVal : in RangeArrayType ;
variable result : out integer_vector
) is
variable VectorVal : integer_vector(BinVal'range) ;
begin
for i in BinVal'range loop
VectorVal(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ;
end loop ;
result := VectorVal ;
end procedure ToRandPoint ;
------------------------------------------------------------
-- Local. Get first word from a string
function GetWord (Message : string) return string is
------------------------------------------------------------
alias aMessage : string( 1 to Message'length) is Message ;
begin
for i in aMessage'range loop
if aMessage(i) = ' ' or aMessage(i) = HT then
return aMessage(1 to i-1) ;
end if ;
end loop ;
return aMessage ;
end function GetWord ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
type CovPType is protected body
constant COV_READ_YAML_ALERT_LEVEL : AlertType := ERROR ;
------------------------------------------------------------
-- Global Settings for Coverage Modeling
-- Local WriteBin and WriteCovHoles formatting settings, defaults determined by CoverageGlobals
variable WritePassFailVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WriteBinInfoVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WriteCountVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WriteAnyIllegalVar : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
variable WritePrefixVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
file WriteBinFile : text ;
variable WriteBinFileInit : boolean := FALSE ;
--!! variable UsingLocalFile : boolean := FALSE ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- CoverageBin Data Structures
-- /////////////////////////////////////////
type RangeArrayPtrType is access RangeArrayType ;
type CovBinInternalBaseType is record
BinVal : RangeArrayPtrType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
PercentCov : real ;
Name : line ;
end record CovBinInternalBaseType ;
type CovBinInternalType is array (natural range <>) of CovBinInternalBaseType ;
type CovBinPtrType is access CovBinInternalType ;
type FieldNameArrayType is array (natural range <>) of Line ;
type FieldNameArrayPtrType is access FieldNameArrayType ;
type IntegerVectorPtrType is access integer_vector ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Settings Structure
-- /////////////////////////////////////////
type CovStructType is record
-- Coverage Bin Structure
CovBinPtr : CovBinPtrType ;
CovName : line ;
NumBins : integer ;
BinValLength : integer ;
FieldName : FieldNameArrayPtrType ;
CovWeight : integer ; -- Set GetCov for entire model
TCoverCount : integer ;
TCoverValuePtr : IntegerVectorPtrType ;
CovMessage : MessageStructPtrType ;
VendorCovHandle : VendorCovHandleType ;
-- Statistics and History
ItemCount : integer ; -- Count of randomizations
LastIndex : integer ; -- Index of last Stimulus Gen or Coverage Collection
LastStimGenIndex : integer ; -- Index of last stimulus gen
-- Internal Modes and Settings
NextPointMode : NextPointModeType ;
IllegalMode : IllegalModeType ;
IllegalModeLevel : AlertType ;
WeightMode : WeightModeType ;
WeightScale : real ;
ThresholdingEnable : boolean ; -- thresholding disabled by default
CovThreshold : real ;
CovTarget : real ;
MergingEnable : boolean ; -- merging disabled by default
CountMode : CountModeType ;
-- Randomization Variable
RV : RandomSeedType ;
RvSeedInit : boolean ;
AlertLogID : AlertLogIDType ;
end record CovStructType ;
variable COV_STRUCT_INIT : CovStructType :=
(
-- Coverage Bin Structure
CovBinPtr => NULL,
CovName => NULL,
NumBins => 0,
BinValLength => 1,
FieldName => NULL,
CovWeight => 1,
TCoverCount => 0,
TCoverValuePtr => NULL,
CovMessage => NULL,
VendorCovHandle => 0,
-- Statistics and History
ItemCount => 0, -- Count of randomizations
LastIndex => 1, -- Index of last Stimulus Gen or Coverage Collection
LastStimGenIndex => 1, -- Index of last stimulus gen
-- Internal Modes and Settings
NextPointMode => RANDOM,
IllegalMode => ILLEGAL_ON,
IllegalModeLevel => ERROR,
WeightMode => AT_LEAST,
WeightScale => 1.0,
ThresholdingEnable => FALSE, -- thresholding disabled by default
CovThreshold => 45.0,
CovTarget => 100.0,
MergingEnable => FALSE, -- merging disabled by default
CountMode => COUNT_FIRST,
-- Randomization Variable
RV => (1, 7),
RvSeedInit => FALSE,
AlertLogID => OSVVM_COVERAGE_ALERTLOG_ID
) ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Adjustable Array Data Structure and Creation
-- /////////////////////////////////////////
type ItemArrayType is array (integer range <>) of CovStructType ;
type ItemArrayPtrType is access ItemArrayType ;
variable Template : ItemArrayType(1 to 1) := (1 => COV_STRUCT_INIT) ;
constant COV_STRUCT_ID_DEFAULT : CoverageIDType := (ID => Template'left) ;
variable CovStructPtr : ItemArrayPtrType := new ItemArrayType'(Template) ;
variable NumItems : integer := 0 ;
-- constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable ItemArrayPtr : InOut ItemArrayPtrType ;
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
-- constant NewNumItems : in integer ;
-- constant CurNumItems : in integer ;
constant MinNumItems : in integer
) is
variable oldItemArrayPtr : ItemArrayPtrType ;
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if ItemArrayPtr = NULL then
ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
elsif NewNumItems > ItemArrayPtr'length then
oldItemArrayPtr := ItemArrayPtr ;
ItemArrayPtr := new ItemArrayType(1 to NormalizeArraySize(NewNumItems, MinNumItems)) ;
ItemArrayPtr(1 to NumItems) := oldItemArrayPtr(1 to NumItems) ;
deallocate(oldItemArrayPtr) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType is
variable NewCoverageID : CoverageIDType ;
variable NameID : integer ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_COVERAGE_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_COVERAGE_ALERTLOG_ID, PrintParent) ;
NameID := LocalNameStore.find(Name, ParentID, ResolvedSearch) ;
if NameID /= ID_NOT_FOUND.ID then
NewCoverageID := (ID => NameID) ;
SetName(NewCoverageID, Name) ; -- redundant - refactor after diverge. Needed if deallocate
return NewCoverageID ;
else
-- Add New Coverage Model to Structure
GrowNumberItems(CovStructPtr, NumItems, 1, MIN_NUM_ITEMS) ;
CovStructPtr(NumItems) := COV_STRUCT_INIT ;
NewCoverageID := (ID => NumItems) ;
-- Create AlertLogID
CovStructPtr(NumItems).AlertLogID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, ResolvedSearch) ;
AlertIfNotEqual(CovStructPtr(NumItems).AlertLogID, NameID, NumItems, "CoveragePkg: Index of LocalNameStore /= CoverageID") ;
InitSeed( NewCoverageID, Name) ;
SetName( NewCoverageID, Name) ; -- redundant - refactor after diverge
return NewCoverageID ;
end if ;
end function NewID ;
------------------------------------------------------------
impure function GetNumIDs return integer is
------------------------------------------------------------
begin
return NumItems ;
end function GetNumIDs ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
WriteBinFileInit := TRUE ;
file_open( WriteBinFile , FileName , OpenKind );
end procedure FileOpenWriteBin ;
------------------------------------------------------------
procedure FileCloseWriteBin is
------------------------------------------------------------
begin
WriteBinFileInit := FALSE ;
file_close( WriteBinFile) ;
end procedure FileCloseWriteBin ;
------------------------------------------------------------
-- PT Local for now as it uses an access type
procedure WriteToCovFile (variable buf : inout line) is
------------------------------------------------------------
begin
if buf /= NULL then
if WriteBinFileInit then
-- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead
writeline(WriteBinFile, buf) ;
elsif IsTranscriptEnabled then
if IsTranscriptMirrored then
-- Write to TranscriptFile and OUTPUT
tee(TranscriptFile, buf) ;
else
-- Write to TranscriptFile
writeline(TranscriptFile, buf) ;
end if ;
else
-- Default Write to OUTPUT
writeline(OUTPUT, buf) ;
end if ;
end if ;
end procedure WriteToCovFile ;
------------------------------------------------------------
procedure PrintToCovFile(S : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, S) ;
WriteToCovFile(buf) ;
end procedure PrintToCovFile ;
-- ------------------------------------------------------------
-- procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
-- ------------------------------------------------------------
-- begin
-- WriteCovDbFileInit := TRUE ;
-- file_open( WriteCovDbFile , FileName , OpenKind );
-- end procedure FileOpenWriteCovDb ;
--
-- ------------------------------------------------------------
-- procedure FileCloseWriteCovDb is
-- ------------------------------------------------------------
-- begin
-- WriteCovDbFileInit := FALSE ;
-- file_close( WriteCovDbFile );
-- end procedure FileCloseWriteCovDb ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= COV_OPT_INIT_PARM_DETECT then
WritePassFailVar := WritePassFail ;
end if ;
if WriteBinInfo /= COV_OPT_INIT_PARM_DETECT then
WriteBinInfoVar := WriteBinInfo ;
end if ;
if WriteCount /= COV_OPT_INIT_PARM_DETECT then
WriteCountVar := WriteCount ;
end if ;
if WriteAnyIllegal /= COV_OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar := WriteAnyIllegal ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
end procedure SetReportOptions ;
------------------------------------------------------------
procedure ResetReportOptions is
------------------------------------------------------------
begin
-- Globals - for all coverage models
WritePassFailVar := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfoVar := COV_OPT_INIT_PARM_DETECT ;
WriteCountVar := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegalVar := COV_OPT_INIT_PARM_DETECT ;
WritePrefixVar.deallocate ;
PassNameVar.deallocate ;
FailNameVar.deallocate ;
end procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
impure function IsInitialized (ID : CoverageIDType) return boolean is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).NumBins > 0 ;
end function IsInitialized ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) is
------------------------------------------------------------
variable ChurnSeed : integer ;
begin
if UseNewSeedMethods then
CovStructPtr(ID.ID).RV := GenRandSeed(S) ;
Uniform(CovStructPtr(ID.ID).RV, ChurnSeed, 0, 1) ;
else
CovStructPtr(ID.ID).RV := OldGenRandSeed(S) ;
end if ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end procedure InitSeed ;
------------------------------------------------------------
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string is
------------------------------------------------------------
begin
InitSeed(ID, S, UseNewSeedMethods) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
return S ;
end function InitSeed ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) is
------------------------------------------------------------
variable ChurnSeed : integer ;
begin
if UseNewSeedMethods then
CovStructPtr(ID.ID).RV := GenRandSeed(I) ;
Uniform(CovStructPtr(ID.ID).RV, ChurnSeed, 0, 1) ;
else
CovStructPtr(ID.ID).RV := OldGenRandSeed(I) ;
end if ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).RV := RandomSeedIn ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end procedure SetSeed ;
------------------------------------------------------------
impure function GetSeed (ID : CoverageIDType) return RandomSeedType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).RV ;
end function GetSeed ;
------------------------------------------------------------
procedure SetName (ID : CoverageIDType; Name : String) is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL then
deallocate (CovStructPtr(ID.ID).CovName) ;
end if;
CovStructPtr(ID.ID).CovName := new string'(Name) ;
-- Update if name updated after model created -- VendorCov
if IsInitialized(ID) then -- VendorCov
VendorCovSetName(CovStructPtr(ID.ID).VendorCovHandle, Name) ; -- VendorCov
end if ; -- VendorCov
-- Init seed if not already initialized
if not CovStructPtr(ID.ID).RvSeedInit then
InitSeed(ID, Name) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end if ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (ID : CoverageIDType; Name : String) return string is
------------------------------------------------------------
begin
SetName(ID, Name) ; -- call procedure above
return Name ;
end function SetName ;
------------------------------------------------------------
procedure DeallocateName (ID : CoverageIDType) is
------------------------------------------------------------
begin
Deallocate (CovStructPtr(ID.ID).CovName) ;
end procedure DeallocateName ;
------------------------------------------------------------
impure function GetName (ID : CoverageIDType) return String is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL then
return CovStructPtr(ID.ID).CovName.all ;
else
return "!!! CovName is NULL !!!" ;
end if ;
end function GetName ;
------------------------------------------------------------
impure function GetCovModelName (ID : CoverageIDType) return String is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL then
-- return Name if set
return CovStructPtr(ID.ID).CovName.all ;
elsif CovStructPtr(ID.ID).AlertLogID /= OSVVM_COVERAGE_ALERTLOG_ID then
-- otherwise return AlertLogName if it is set
return GetAlertLogName(CovStructPtr(ID.ID).AlertLogID) ;
elsif CovStructPtr(ID.ID).CovMessage /= NULL then
-- otherwise Get the first word of the Message if it is set
return GetWord(CovStructPtr(ID.ID).CovMessage.Name.all) ;
else
return "" ;
end if ;
end function GetCovModelName ;
------------------------------------------------------------
-- Called in calls to AlertLogID to add Name to if set different from AlertLogID name
impure function GetNamePlus(ID : CoverageIDType; prefix, suffix : string) return String is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovName /= NULL and (CovStructPtr(ID.ID).CovName.all /= GetAlertLogName(CovStructPtr(ID.ID).AlertLogID)) then
-- return Name if set
return prefix & CovStructPtr(ID.ID).CovName.all & suffix ;
elsif CovStructPtr(ID.ID).AlertLogID = OSVVM_COVERAGE_ALERTLOG_ID and CovStructPtr(ID.ID).CovMessage /= NULL then
-- If AlertLogID not set, then use Message
return prefix & GetWord(CovStructPtr(ID.ID).CovMessage.Name.all) & suffix ;
else
return "" ;
end if ;
end function GetNamePlus ;
------------------------------------------------------------
-- PT Local
impure function NewNamePtr(Name : string) return Line is
------------------------------------------------------------
begin
if Name /= "" then
return new string'(Name) ;
else
return NULL ;
end if;
end function NewNamePtr ;
-- ------------------------------------------------------------
-- -- pt local
-- procedure CheckBinValLength(ID : CoverageIDType; CurBinValLength : integer ; Caller : string ) is
-- ------------------------------------------------------------
-- begin
-- if CovStructPtr(ID.ID).NumBins = 0 then
-- CovStructPtr(ID.ID).BinValLength := CurBinValLength ; -- number of points in cross
-- else
-- AlertIfNotEqual(CovStructPtr(ID.ID).AlertLogID, CovStructPtr(ID.ID).BinValLength, CurBinValLength, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg." & Caller & ":" &
-- " Cross coverage bins of different dimensions prohibited", FAILURE) ;
-- end if;
-- end procedure CheckBinValLength ;
------------------------------------------------------------
-- pt local
impure function BinValLengthNotEqual(CoverID : CoverageIDType; CurBinValLength : integer) return boolean is
------------------------------------------------------------
constant ID : integer := CoverID.ID ;
begin
if CovStructPtr(ID).NumBins = 0 then
CovStructPtr(ID).BinValLength := CurBinValLength ;
CovStructPtr(ID).TCoverValuePtr := new integer_vector(1 to CurBinValLength) ;
return FALSE ;
else
return CurBinValLength /= CovStructPtr(ID).BinValLength ;
end if;
end function BinValLengthNotEqual ;
------------------------------------------------------------
procedure SetItemBinNames (
------------------------------------------------------------
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) is
variable NamePtr : Line ;
variable FieldNameArray : FieldNameArrayType(1 to 20) ;
variable Dimensions : integer := 0 ;
begin
-- Support names for up to a cross of 20
for i in 1 to 20 loop
if CovStructPtr(ID.ID).FieldName /= NULL then
for i in 1 to CovStructPtr(ID.ID).FieldName'length loop
deallocate (CovStructPtr(ID.ID).FieldName(i)) ;
end loop ;
deallocate (CovStructPtr(ID.ID).FieldName) ;
end if;
case i is
when 1 => NamePtr := NewNamePtr(Name1) ;
when 2 => NamePtr := NewNamePtr(Name2) ;
when 3 => NamePtr := NewNamePtr(Name3) ;
when 4 => NamePtr := NewNamePtr(Name4) ;
when 5 => NamePtr := NewNamePtr(Name5) ;
when 6 => NamePtr := NewNamePtr(Name6) ;
when 7 => NamePtr := NewNamePtr(Name7) ;
when 8 => NamePtr := NewNamePtr(Name8) ;
when 9 => NamePtr := NewNamePtr(Name9) ;
when 10 => NamePtr := NewNamePtr(Name10) ;
when 11 => NamePtr := NewNamePtr(Name11) ;
when 12 => NamePtr := NewNamePtr(Name12) ;
when 13 => NamePtr := NewNamePtr(Name13) ;
when 14 => NamePtr := NewNamePtr(Name14) ;
when 15 => NamePtr := NewNamePtr(Name15) ;
when 16 => NamePtr := NewNamePtr(Name16) ;
when 17 => NamePtr := NewNamePtr(Name17) ;
when 18 => NamePtr := NewNamePtr(Name18) ;
when 19 => NamePtr := NewNamePtr(Name19) ;
when 20 => NamePtr := NewNamePtr(Name20) ;
end case ;
exit when NamePtr = NULL ;
FieldNameArray(i) := NamePtr ;
Dimensions := i ;
end loop ;
CovStructPtr(ID.ID).FieldName := new FieldNameArrayType'(FieldNameArray(1 to Dimensions)) ;
-- Check that Dimensions match bin dimensions
if BinValLengthNotEqual(ID, Dimensions) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.SetItemBinNames: Coverage bins of different dimensions prohibited", FAILURE) ;
end if ;
end procedure SetItemBinNames ;
------------------------------------------------------------
procedure SetMessage (ID : CoverageIDType; Message : String) is
------------------------------------------------------------
begin
SetMessage(CovStructPtr(ID.ID).CovMessage, Message) ;
-- VendorCov update if name updated after model created
if IsInitialized(ID) then -- VendorCov
-- Refine this? If CovName or AlertLogID is set, -- VendorCov
-- it may be set to the same name again. -- VendorCov
VendorCovSetName(CovStructPtr(ID.ID).VendorCovHandle, GetCovModelName(ID)) ; -- VendorCov
end if ; -- VendorCov
if not CovStructPtr(ID.ID).RvSeedInit then -- Init seed if not initialized
InitSeed(ID, Message) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end if ;
end procedure SetMessage ;
------------------------------------------------------------
procedure DeallocateMessage (ID : CoverageIDType) is
------------------------------------------------------------
begin
DeallocateMessage(CovStructPtr(ID.ID).CovMessage) ;
end procedure DeallocateMessage ;
------------------------------------------------------------
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).ThresholdingEnable := A ;
end procedure SetThresholding ;
------------------------------------------------------------
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).ThresholdingEnable := TRUE ;
if Percent >= 0.0 then
CovStructPtr(ID.ID).CovThreshold := Percent + 0.0001 ; -- used in less than
else
CovStructPtr(ID.ID).CovThreshold := 0.0001 ; -- used in less than
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetCovThreshold:" &
" Invalid Threshold Value " & real'image(Percent), FAILURE) ;
end if ;
end procedure SetCovThreshold ;
------------------------------------------------------------
procedure SetCovTarget (ID : CoverageIDType; Percent : real) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).CovTarget := Percent ;
end procedure SetCovTarget ;
------------------------------------------------------------
impure function GetCovTarget (ID : CoverageIDType) return real is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovTarget ;
end function GetCovTarget ;
------------------------------------------------------------
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).MergingEnable := A ;
end procedure SetMerging ;
------------------------------------------------------------
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).CountMode := A ;
end procedure SetCountMode ;
------------------------------------------------------------
procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).AlertLogID := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).AlertLogID := GetAlertLogID(Name, ParentID, CreateHierarchy) ;
if not CovStructPtr(ID.ID).RvSeedInit then -- Init seed if not initialized
InitSeed(ID, Name) ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
end if ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(ID : CoverageIDType) return AlertLogIDType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).AlertLogID ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).NextPointMode := A ;
end procedure SetNextPointMode ;
------------------------------------------------------------
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).IllegalMode := A ;
if A = ILLEGAL_FAILURE then
CovStructPtr(ID.ID).IllegalModeLevel := FAILURE ;
else
CovStructPtr(ID.ID).IllegalModeLevel := ERROR ;
end if ;
end procedure SetIllegalMode ;
------------------------------------------------------------
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) is
------------------------------------------------------------
variable buf : line ;
begin
CovStructPtr(ID.ID).WeightMode := WeightMode ;
CovStructPtr(ID.ID).WeightScale := WeightScale ;
if (WeightMode = REMAIN_EXP) and (WeightScale > 2.0) then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" &
" WeightScale > 2.0 and large Counts can cause RandCovPoint to fail due to integer values out of range", WARNING) ;
end if ;
if (WeightScale < 1.0) and (WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED) then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" &
" WeightScale must be > 1.0 when WeightMode = REMAIN_WEIGHT or WeightMode = REMAIN_SCALED", FAILURE) ;
CovStructPtr(ID.ID).WeightScale := 1.0 ;
end if;
if WeightScale <= 0.0 then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.SetWeightMode:" &
" WeightScale must be > 0.0", FAILURE) ;
CovStructPtr(ID.ID).WeightScale := 1.0 ;
end if;
end procedure SetWeightMode ;
------------------------------------------------------------
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) is
------------------------------------------------------------
begin
CovStructPtr(ID.ID).CovWeight := Weight ;
end procedure SetCovWeight ;
------------------------------------------------------------
impure function GetCovWeight (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovWeight ;
end function GetCovWeight ;
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) is
-- Sets a CovBin to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
------------------------------------------------------------
variable oldCovBinPtr : CovBinPtrType ;
begin
if CovStructPtr(ID.ID).CovBinPtr = NULL then
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NewNumBins) ;
elsif NewNumBins > CovStructPtr(ID.ID).CovBinPtr'length then
-- make message bigger
oldCovBinPtr := CovStructPtr(ID.ID).CovBinPtr ;
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NewNumBins) ;
CovStructPtr(ID.ID).CovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) := oldCovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) ;
deallocate(oldCovBinPtr) ;
end if ;
end procedure SetBinSize ;
------------------------------------------------------------
-- pt local
impure function NormalizeNumBins(ID : CoverageIDType; ReqNumBins : integer ) return integer is
variable NormNumBins : integer := MIN_NUM_BINS ;
begin
while NormNumBins < ReqNumBins loop
NormNumBins := NormNumBins + MIN_NUM_BINS ;
end loop ;
return NormNumBins ;
end function NormalizeNumBins ;
------------------------------------------------------------
-- pt local
procedure GrowBins (ID : CoverageIDType; ReqNumBins : integer) is
variable oldCovBinPtr : CovBinPtrType ;
variable NewNumBins : integer ;
begin
NewNumBins := CovStructPtr(ID.ID).NumBins + ReqNumBins ;
if CovStructPtr(ID.ID).CovBinPtr = NULL then
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NormalizeNumBins(ID, NewNumBins)) ;
elsif NewNumBins > CovStructPtr(ID.ID).CovBinPtr'length then
-- make message bigger
oldCovBinPtr := CovStructPtr(ID.ID).CovBinPtr ;
CovStructPtr(ID.ID).CovBinPtr := new CovBinInternalType(1 to NormalizeNumBins(ID, NewNumBins)) ;
CovStructPtr(ID.ID).CovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) := oldCovBinPtr.all(1 to CovStructPtr(ID.ID).NumBins) ;
deallocate(oldCovBinPtr) ;
end if ;
end procedure GrowBins ;
------------------------------------------------------------
-- pt local, called by InsertBin
-- Finds index of bin if it is inside an existing bins
procedure FindBinInside(
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Position : out integer ;
FoundInside : out boolean
) is
begin
Position := CovStructPtr(ID.ID).NumBins + 1 ;
FoundInside := FALSE ;
FindLoop : for i in CovStructPtr(ID.ID).NumBins downto 1 loop
-- skip this CovBin if CovPoint is not in it
next FindLoop when not inside(BinVal, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
Position := i ;
FoundInside := TRUE ;
exit ;
end loop ;
end procedure FindBinInside ;
------------------------------------------------------------
-- pt local
-- Inserts values into a new bin.
-- Called by InsertBin
procedure InsertNewBin(
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string ;
PercentCov : real
) is
begin
if (not IsInitialized(ID)) then -- VendorCov
if (BinVal'length > 1) then -- Cross Bin -- VendorCov
CovStructPtr(ID.ID).VendorCovHandle := VendorCovCrossCreate(GetCovModelName(ID)) ; -- VendorCov
else -- VendorCov
CovStructPtr(ID.ID).VendorCovHandle := VendorCovPointCreate(GetCovModelName(ID)); -- VendorCov
end if; -- VendorCov
end if; -- VendorCov
VendorCovBinAdd(CovStructPtr(ID.ID).VendorCovHandle, ToVendorCovBinVal(BinVal), Action, AtLeast, Name) ; -- VendorCov
CovStructPtr(ID.ID).NumBins := CovStructPtr(ID.ID).NumBins + 1 ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).BinVal := new RangeArrayType'(BinVal) ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Action := Action ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Count := Count ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).AtLeast := AtLeast ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Weight := Weight ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).Name := new String'(Name) ;
CovStructPtr(ID.ID).CovBinPtr.all(CovStructPtr(ID.ID).NumBins).PercentCov := PercentCov ;
end procedure InsertNewBin ;
------------------------------------------------------------
-- pt local
-- Inserts values into a new bin.
-- Called by InsertBin
procedure MergeBin (
ID : CoverageIDType ;
Position : Natural ;
Count : integer ;
AtLeast : integer ;
Weight : integer
) is
begin
CovStructPtr(ID.ID).CovBinPtr.all(Position).Count := CovStructPtr(ID.ID).CovBinPtr.all(Position).Count + Count ;
CovStructPtr(ID.ID).CovBinPtr.all(Position).AtLeast := CovStructPtr(ID.ID).CovBinPtr.all(Position).AtLeast + AtLeast ;
CovStructPtr(ID.ID).CovBinPtr.all(Position).Weight := CovStructPtr(ID.ID).CovBinPtr.all(Position).Weight + Weight ;
CovStructPtr(ID.ID).CovBinPtr.all(Position).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(Position).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(Position).AtLeast ) ;
end procedure MergeBin ;
------------------------------------------------------------
-- pt local
-- All insertion comes here
-- Enforces the general insertion use model:
-- Earlier bins supercede later bins - except with COUNT_ALL
-- Add Illegal and Ignore bins first to remove regions of larger count bins
-- Later ignore bins can be used to miss an illegal catch-all
-- Add Illegal bins last as a catch-all to find things that missed other bins
procedure InsertBin(
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string
) is
variable Position : integer ;
variable FoundInside : boolean ;
variable PercentCov : real ;
begin
PercentCov := CalcPercentCov(Count => Count, AtLeast => AtLeast) ;
if not CovStructPtr(ID.ID).MergingEnable then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
else -- handle merging
-- future optimization, FindBinInside only checks against Ignore and Illegal bins
FindBinInside(ID, BinVal, Position, FoundInside) ;
if not FoundInside then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
elsif Action = COV_COUNT then
-- when check only ignore and illegal bins, only action is to drop
if CovStructPtr(ID.ID).CovBinPtr.all(Position).Action /= COV_COUNT then
null ; -- drop count bin when it is inside a Illegal or Ignore bin
elsif CovStructPtr(ID.ID).CovBinPtr.all(Position).BinVal.all = BinVal and CovStructPtr(ID.ID).CovBinPtr.all(Position).Name.all = Name then
-- Bins match, so merge the count values
MergeBin (ID, Position, Count, AtLeast, Weight) ;
else
-- Bins overlap, but do not match, insert new bin
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
end if;
elsif Action = COV_IGNORE then
-- when check only ignore and illegal bins, only action is to report error
if CovStructPtr(ID.ID).CovBinPtr.all(Position).Action = COV_COUNT then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
else
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.InsertBin (AddBins/AddCross):" &
" ignore bin dropped. It is a subset of prior bin", ERROR) ;
end if;
elsif Action = COV_ILLEGAL then
-- when check only ignore and illegal bins, only action is to report error
if CovStructPtr(ID.ID).CovBinPtr.all(Position).Action = COV_COUNT then
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, Name, PercentCov) ;
else
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.InsertBin (AddBins/AddCross):" &
" illegal bin dropped. It is a subset of prior bin", ERROR) ;
end if;
end if ;
end if ; -- merging enabled
end procedure InsertBin ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
variable vCalcAtLeast : integer ;
variable vCalcWeight : integer ;
begin
if BinValLengthNotEqual(ID, 1) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddBins: Coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
if CovBin(i).Action = COV_COUNT then
vCalcAtLeast := maximum(AtLeast, CovBin(i).AtLeast) ;
vCalcWeight := maximum(Weight, CovBin(i).Weight) ;
else
vCalcAtLeast := 0 ;
vCalcWeight := 0 ;
end if ;
InsertBin(
ID => ID,
BinVal => CovBin(i).BinVal,
Action => CovBin(i).Action,
Count => CovBin(i).Count,
AtLeast => vCalcAtLeast,
Weight => vCalcWeight,
Name => Name
) ;
end loop ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; Name : String ; AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, Name, AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) is
------------------------------------------------------------
begin
AddBins(ID, Name, 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, "", AtLeast, Weight, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, "", AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(ID, "", 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
constant BIN_LENS : integer_vector :=
BinLengths(
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable vCalcAction, vCalcCount, vCalcAtLeast, vCalcWeight : integer ;
variable vCalcBinVal : RangeArrayType(BinIndex'range) ;
begin
if BinValLengthNotEqual(ID, BIN_LENS'length) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, NUM_NEW_BINS) ;
vCalcCount := 0 ;
for MatrixIndex in 1 to NUM_NEW_BINS loop
CrossBins := ConcatenateBins(BinIndex,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
vCalcAction := MergeState (CrossBins) ;
vCalcBinVal := MergeBinVal(CrossBins) ;
vCalcAtLeast := MergeAtLeast( vCalcAction, AtLeast, CrossBins) ;
vCalcWeight := MergeWeight ( vCalcAction, Weight, CrossBins) ;
InsertBin(ID, vCalcBinVal, vCalcAction, vCalcCount, vCalcAtLeast, vCalcWeight, Name) ;
IncBinIndex( BinIndex, BIN_LENS) ; -- increment right most one, then if overflow, increment next
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, Name, AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, Name, 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, "", AtLeast, Weight,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, "", AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(ID, "", 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure DeallocateBins(CoverID : CoverageIDType) is
------------------------------------------------------------
constant Index : integer := CoverID.ID ;
begin
-- Local for a particular CoverageModel
if CovStructPtr(Index).CovBinPtr /= NULL then
for i in 1 to CovStructPtr(Index).NumBins loop
deallocate(CovStructPtr(Index).CovBinPtr(i).BinVal) ;
deallocate(CovStructPtr(Index).CovBinPtr(i).Name) ;
end loop ;
deallocate(CovStructPtr(Index).CovBinPtr) ;
end if ;
CovStructPtr(Index).NumBins := 0 ;
end procedure DeallocateBins ;
------------------------------------------------------------
procedure Deallocate(ID : CoverageIDType) is
------------------------------------------------------------
constant Index : integer := ID.ID ;
begin
--!!?? These are only done when removing all coverage models.
-- -- Globals - for all coverage models
-- WritePassFailVar := COV_OPT_INIT_PARM_DETECT ;
-- WriteBinInfoVar := COV_OPT_INIT_PARM_DETECT ;
-- WriteCountVar := COV_OPT_INIT_PARM_DETECT ;
-- WriteAnyIllegalVar := COV_OPT_INIT_PARM_DETECT ;
-- WritePrefixVar.deallocate ;
-- PassNameVar.deallocate ;
-- FailNameVar.deallocate ;
DeallocateBins(ID) ;
DeallocateName(ID) ;
DeallocateMessage(ID) ;
-- Restore internal variables to their default values
-- CovStructPtr(Index) := COV_STRUCT_INIT ;
CovStructPtr(Index).BinValLength := 1 ;
CovStructPtr(Index).VendorCovHandle := 0 ;
CovStructPtr(Index).ItemCount := 0 ;
CovStructPtr(Index).LastIndex := 1 ;
CovStructPtr(Index).LastStimGenIndex := 1 ;
-- Changing these is beyond what deallocate should do.
CovStructPtr(Index).NextPointMode := RANDOM ;
CovStructPtr(Index).IllegalMode := ILLEGAL_ON ;
CovStructPtr(Index).IllegalModeLevel := ERROR ;
CovStructPtr(Index).WeightMode := AT_LEAST ;
CovStructPtr(Index).WeightScale := 1.0 ;
CovStructPtr(Index).ThresholdingEnable := FALSE ;
CovStructPtr(Index).CovThreshold := 45.0 ;
CovStructPtr(Index).CovTarget := 100.0 ;
CovStructPtr(Index).MergingEnable := FALSE ;
CovStructPtr(Index).CountMode := COUNT_FIRST ;
-- CovStructPtr(Index).RV := (1, 7) ;
-- CovStructPtr(Index).RvSeedInit := FALSE ;
-- CovStructPtr(Index).AlertLogID := OSVVM_COVERAGE_ALERTLOG_ID ;
end procedure deallocate ;
------------------------------------------------------------
-- Local
procedure ICoverIndex(ID : CoverageIDType; Index : integer ; CovPoint : integer_vector ) is
------------------------------------------------------------
variable buf : line ;
begin
-- Update Count, PercentCov
CovStructPtr(ID.ID).CovBinPtr(Index).Count := CovStructPtr(ID.ID).CovBinPtr(Index).Count + CovStructPtr(ID.ID).CovBinPtr(Index).action ;
VendorCovBinInc(CovStructPtr(ID.ID).VendorCovHandle, Index); -- VendorCov
CovStructPtr(ID.ID).CovBinPtr(Index).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(Index).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(Index).AtLeast
) ;
if CovStructPtr(ID.ID).CovBinPtr(Index).action = COV_ILLEGAL then
if CovStructPtr(ID.ID).IllegalMode /= ILLEGAL_OFF then
-- if CovPoint = NULL_INTV then
if CovPoint'length = 0 then
alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.ICoverLast:" &
" Value randomized is in an illegal bin.", CovStructPtr(ID.ID).IllegalModeLevel) ;
else
write(buf, CovPoint) ;
alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.ICover:" &
" Value " & buf.all & " is in an illegal bin.", CovStructPtr(ID.ID).IllegalModeLevel) ;
deallocate(buf) ;
end if ;
else
IncAlertCount(CovStructPtr(ID.ID).AlertLogID, ERROR) ; -- silent alert.
end if ;
end if ;
end procedure ICoverIndex ;
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) is
------------------------------------------------------------
begin
ICoverIndex(ID, CovStructPtr(ID.ID).LastStimGenIndex, NULL_INTV) ;
end procedure ICoverLast ;
------------------------------------------------------------
procedure ICover(ID : CoverageIDType; CovPoint : integer_vector) is
------------------------------------------------------------
begin
if CovPoint'length /= CovStructPtr(ID.ID).BinValLength then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg." &
" ICover: CovPoint length = " & to_string(CovPoint'length) &
" does not match Coverage Bin dimensions = " & to_string(CovStructPtr(ID.ID).BinValLength), FAILURE) ;
-- Search CovStructPtr(ID.ID).LastStimGenIndex first. Important it is not CovStructPtr(ID.ID).LastIndex seen by ICover below.
-- If find an object in a sentinal bin - only looks in sentinal bin after that point
elsif CovStructPtr(ID.ID).CountMode = COUNT_FIRST and inside(CovPoint, CovStructPtr(ID.ID).CovBinPtr(CovStructPtr(ID.ID).LastStimGenIndex).BinVal.all) then
ICoverIndex(ID, CovStructPtr(ID.ID).LastStimGenIndex, CovPoint) ;
else
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- skip this CovBin if CovPoint is not in it
next CovLoop when not inside(CovPoint, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
-- Mark Covered
CovStructPtr(ID.ID).LastIndex := i ; -- Mark found index
ICoverIndex(ID, i, CovPoint) ;
exit CovLoop when CovStructPtr(ID.ID).CountMode = COUNT_FIRST ; -- only find first one
end loop CovLoop ;
end if ;
end procedure ICover ;
------------------------------------------------------------
procedure ICover (ID : CoverageIDType; CovPoint : integer) is
------------------------------------------------------------
begin
ICover(ID, (1=> CovPoint)) ;
end procedure ICover ;
------------------------------------------------------------
procedure TCover (CoverID : CoverageIDType; A : integer) is
------------------------------------------------------------
constant ID : integer := CoverID.ID ;
begin
CovStructPtr(ID).TCoverCount := CovStructPtr(ID).TCoverCount + 1 ;
CovStructPtr(ID).TCoverValuePtr.all := CovStructPtr(ID).TCoverValuePtr.all(2 to CovStructPtr(ID).BinValLength) & A ;
if (CovStructPtr(ID).TCoverCount >= CovStructPtr(ID).BinValLength) then
ICover(CoverID, CovStructPtr(ID).TCoverValuePtr.all) ;
end if ;
end procedure TCover ;
------------------------------------------------------------
procedure ClearCov (ID : CoverageIDType) is
------------------------------------------------------------
begin
for i in 1 to CovStructPtr(ID.ID).NumBins loop
CovStructPtr(ID.ID).CovBinPtr(i).Count := 0 ;
CovStructPtr(ID.ID).CovBinPtr(i).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(i).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(i).AtLeast ) ;
end loop ;
end procedure ClearCov ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real is
------------------------------------------------------------
variable MinCov : real := real'right ; -- big number
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < MinCov then
MinCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
end if ;
end loop CovLoop ;
return MinCov ;
end function GetMinCov ;
------------------------------------------------------------
impure function GetMinCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MinCount : integer := integer'right ; -- big number
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < MinCount then
MinCount := CovStructPtr(ID.ID).CovBinPtr(i).Count ;
end if ;
end loop CovLoop ;
return MinCount ;
end function GetMinCount ;
------------------------------------------------------------
impure function GetMaxCov (ID : CoverageIDType) return real is
------------------------------------------------------------
variable MaxCov : real := 0.0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov > MaxCov then
MaxCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
end if ;
end loop CovLoop ;
return MaxCov ;
end function GetMaxCov ;
------------------------------------------------------------
impure function GetMaxCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MaxCount : integer := 0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count > MaxCount then
MaxCount := CovStructPtr(ID.ID).CovBinPtr(i).Count ;
end if ;
end loop CovLoop ;
return MaxCount ;
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < PercentCov then
HoleCount := HoleCount + 1 ;
end if ;
end loop CovLoop ;
return HoleCount ;
end function CountCovHoles ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CountCovHoles(ID, CovStructPtr(ID.ID).CovTarget) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean is
------------------------------------------------------------
begin
-- AlertIf(CovStructPtr(ID.ID).NumBins < 1, OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.IsCovered: Empty Coverage Model", failure) ;
return CountCovHoles(ID, PercentCov) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType) return boolean is
------------------------------------------------------------
begin
-- AlertIf(CovStructPtr(ID.ID).NumBins < 1, OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.IsCovered: Empty Coverage Model", failure) ;
return CountCovHoles(ID, CovStructPtr(ID.ID).CovTarget) = 0 ;
end function IsCovered ;
------------------------------------------------------------
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; PercentCov : real; TotalCovCount : out integer; TotalCovGoal : out integer ) is
------------------------------------------------------------
variable ScaledCovGoal : integer := 0 ;
begin
TotalCovCount := 0 ;
TotalCovGoal := 0 ;
BinLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT then
ScaledCovGoal := integer(ceil(PercentCov * real(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)/100.0)) ;
TotalCovGoal := TotalCovGoal + ScaledCovGoal ;
if CovStructPtr(ID.ID).CovBinPtr(i).Count <= ScaledCovGoal then
TotalCovCount := TotalCovCount + CovStructPtr(ID.ID).CovBinPtr(i).Count ;
else
-- do not count the extra values that exceed their cov goal
TotalCovCount := TotalCovCount + ScaledCovGoal ;
end if ;
end if ;
end loop BinLoop ;
end procedure GetTotalCovCountAndGoal ;
------------------------------------------------------------
procedure GetTotalCovCountAndGoal (ID : CoverageIDType; TotalCovCount : out integer; TotalCovGoal : out integer ) is
------------------------------------------------------------
begin
GetTotalCovCountAndGoal(ID, CovStructPtr(ID.ID).CovTarget, TotalCovCount, TotalCovGoal) ;
end procedure GetTotalCovCountAndGoal ;
------------------------------------------------------------
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
GetTotalCovCountAndGoal(ID, PercentCov, TotalCovCount, TotalCovGoal) ;
if TotalCovGoal > 0 then
return 100.0 * real(TotalCovCount) / real(TotalCovGoal) ;
else
return 0.0 ;
end if ;
end function GetCov ;
------------------------------------------------------------
impure function GetCov (ID : CoverageIDType) return real is
------------------------------------------------------------
begin
return GetCov(ID, CovStructPtr(ID.ID).CovTarget ) ;
end function GetCov ;
------------------------------------------------------------
impure function GetTotalCovCount (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
GetTotalCovCountAndGoal(ID, PercentCov, TotalCovCount, TotalCovGoal) ;
return TotalCovCount ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetTotalCovCount(ID, CovStructPtr(ID.ID).CovTarget) ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
GetTotalCovCountAndGoal(ID, PercentCov, TotalCovCount, TotalCovGoal) ;
return TotalCovGoal ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetTotalCovGoal (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetTotalCovGoal(ID, CovStructPtr(ID.ID).CovTarget) ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).ItemCount ;
end function GetItemCount ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).NumBins ;
end function GetNumBins ;
------------------------------------------------------------
impure function GetLastIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).LastIndex ;
end function GetLastIndex ;
------------------------------------------------------------
impure function CalcWeight (ID : CoverageIDType; BinIndex : integer ; MaxCovPercent : real ) return integer is
-- pt local
------------------------------------------------------------
begin
case CovStructPtr(ID.ID).WeightMode is
when AT_LEAST => -- AtLeast
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast ;
when WEIGHT => -- Weight
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight ;
when REMAIN => -- (Adjust * AtLeast) - Count
--?? simpler integer( Ceil (MaxCovPercent - CovStructPtr(ID.ID).CovBinPtr(BinIndex).PercentCov)) * CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast
return integer( Ceil( MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_EXP => -- Weight * (REMAIN **WeightScale)
-- Experimental may be removed
-- CAUTION: for large numbers and/or WeightScale > 2.0, result can be > 2**31 (max integer value)
-- both Weight and WeightScale default to 1
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight *
integer( Ceil (
( (MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0) -
real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count) ) ** CovStructPtr(ID.ID).WeightScale ) );
when REMAIN_SCALED => -- (WeightScale * Adjust * AtLeast) - Count
-- Experimental may be removed
-- Biases remainder toward AT_LEAST value.
-- WeightScale must be > 1.0
return integer( Ceil( CovStructPtr(ID.ID).WeightScale * MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_WEIGHT => -- Weight * ((WeightScale * Adjust * AtLeast) - Count)
-- Experimental may be removed
-- WeightScale must be > 1.0
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight * (
integer( Ceil( CovStructPtr(ID.ID).WeightScale * MaxCovPercent * real(CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast)/100.0)) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count) ;
end case ;
end function CalcWeight ;
------------------------------------------------------------
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer is
------------------------------------------------------------
variable WeightVec : integer_vector(0 to CovStructPtr(ID.ID).NumBins-1) ; -- Prep for change to DistInt
variable MaxCovPercent : real ;
variable MinCovPercent : real ;
variable rInt : integer ;
begin
CovStructPtr(ID.ID).ItemCount := CovStructPtr(ID.ID).ItemCount + 1 ;
MinCovPercent := GetMinCov(ID) ;
if CovStructPtr(ID.ID).ThresholdingEnable then
MaxCovPercent := MinCovPercent + CovStructPtr(ID.ID).CovThreshold ;
if MinCovPercent < CovTargetPercent then
-- Clip at CovTargetPercent until reach CovTargetPercent
MaxCovPercent := minimum(MaxCovPercent, CovTargetPercent);
end if ;
else
if MinCovPercent < CovTargetPercent then
MaxCovPercent := CovTargetPercent ;
else
-- Done, Enable all bins
MaxCovPercent := GetMaxCov(ID) + 1.0 ;
-- MaxCovPercent := real'right ; -- weight scale issues
end if ;
end if ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < MaxCovPercent then
-- Calculate Weight based on CovStructPtr(ID.ID).WeightMode
-- Scale to current percentage goal: MaxCov which can be < or > 100.0
WeightVec(i-1) := CalcWeight(ID, i, MaxCovPercent) ;
else
WeightVec(i-1) := 0 ;
end if ;
end loop CovLoop ;
-- DistInt returns integer range 0 to CovStructPtr(ID.ID).NumBins-1
-- Caution: DistInt can fail when sum(WeightVec) > 2**31
-- See notes in CalcWeight for REMAIN_EXP
-- CovStructPtr(ID.ID).LastStimGenIndex := 1 + RV.DistInt( WeightVec ) ; -- return range 1 to CovStructPtr(ID.ID).NumBins
DistInt(CovStructPtr(ID.ID).RV, rInt, WeightVec) ;
CovStructPtr(ID.ID).LastStimGenIndex := 1 + rInt ; -- return range 1 to CovStructPtr(ID.ID).NumBins
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetRandIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetRandIndex(ID, CovStructPtr(ID.ID).CovTarget) ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetIncIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable CurIndex : integer ;
begin
CurIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
CovStructPtr(ID.ID).LastStimGenIndex := (CovStructPtr(ID.ID).LastStimGenIndex mod CovStructPtr(ID.ID).NumBins) + 1 ;
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CurIndex ;
end function GetIncIndex ;
------------------------------------------------------------
impure function GetMinIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MinCov : real := real'right ; -- big number
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < MinCov then
MinCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
CovStructPtr(ID.ID).LastStimGenIndex := i ;
end if ;
end loop CovLoop ;
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetMinIndex ;
------------------------------------------------------------
impure function GetMaxIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable MaxCov : real := -1.0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov > MaxCov then
MaxCov := CovStructPtr(ID.ID).CovBinPtr(i).PercentCov ;
CovStructPtr(ID.ID).LastStimGenIndex := i ;
end if ;
end loop CovLoop ;
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetMaxIndex ;
------------------------------------------------------------
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
case Mode is
when RANDOM => return GetRandIndex(ID) ;
when INCREMENT => return GetIncIndex (ID) ;
when others => return GetMinIndex (ID) ;
end case ;
end function GetNextIndex;
------------------------------------------------------------
impure function GetNextIndex (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode) ;
end function GetNextIndex ;
-- Return BinVals
------------------------------------------------------------
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( BinIndex ).BinVal.all ;
end function GetBinVal ;
------------------------------------------------------------
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( CovStructPtr(ID.ID).LastIndex ).BinVal.all ;
end function GetLastBinVal ;
------------------------------------------------------------
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, PercentCov) ).BinVal.all ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, CovStructPtr(ID.ID).CovTarget ) ).BinVal.all ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(ID, GetIncIndex(ID)) ;
end function GetIncBinVal ;
------------------------------------------------------------
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetBinVal(ID, GetMinIndex(ID) ) ;
end function GetMinBinVal ;
------------------------------------------------------------
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetBinVal(ID, GetMaxIndex(ID) ) ;
end function GetMaxBinVal ;
------------------------------------------------------------
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(ID, GetNextIndex(ID, Mode)) ;
end function GetNextBinVal;
------------------------------------------------------------
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(ID, GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode)) ;
end function GetNextBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, PercentCov) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, CovStructPtr(ID.ID).CovTarget ) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
variable buf : line ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < PercentCov then
HoleCount := HoleCount + 1 ;
if HoleCount = ReqHoleNum then
return CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all ;
end if ;
end if ;
end loop CovLoop ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.GetHoleBinVal:" &
" did not find a coverage hole. HoleCount = " & integer'image(HoleCount) &
" ReqHoleNum = " & integer'image(ReqHoleNum), ERROR
) ;
return CovStructPtr(ID.ID).CovBinPtr(CovStructPtr(ID.ID).NumBins).BinVal.all ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ID, 1, PercentCov) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ID, ReqHoleNum, CovStructPtr(ID.ID).CovTarget) ;
end function GetHoleBinVal ;
-- Return Points
------------------------------------------------------------
impure function ToRandPoint(ID : CoverageIDType; BinVal : RangeArrayType ) return integer is
-- pt local
------------------------------------------------------------
variable rInt : integer ;
begin
-- return RV.RandInt(BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
RandInt(CovStructPtr(ID.ID).RV, rInt, BinVal(BinVal'left).min, BinVal(BinVal'left).max) ;
return rInt ;
end function ToRandPoint ;
------------------------------------------------------------
impure function ToRandPoint(ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector is
-- pt local
------------------------------------------------------------
variable CovPoint : integer_vector(BinVal'range) ;
variable normCovPoint : integer_vector(1 to BinVal'length) ;
begin
for i in BinVal'range loop
-- CovPoint(i) := RV.RandInt(BinVal(i).min, BinVal(i).max) ;
Uniform(CovStructPtr(ID.ID).RV, CovPoint(i), BinVal(i).min, BinVal(i).max) ;
end loop ;
normCovPoint := CovPoint ;
return normCovPoint ;
end function ToRandPoint ;
------------------------------------------------------------
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, BinIndex)) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, BinIndex)) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetIncPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetPoint(ID, GetIncIndex(ID)) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetIncPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(ID, GetIncIndex(ID)) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetMinPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMinIndex(ID) )) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMinPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMinIndex(ID) )) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMaxPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMaxIndex(ID) )) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetBinVal(ID, GetMaxIndex(ID) )) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, Mode)) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, Mode)) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode)) ;
end function GetNextPoint ;
------------------------------------------------------------
impure function GetNextPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(ID, GetNextIndex(ID, CovStructPtr(ID.ID).NextPointMode)) ;
end function GetNextPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, CovStructPtr(ID.ID).CovTarget)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, GetRandBinVal(ID, PercentCov)) ;
end function RandCovPoint ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
variable result : CovBinBaseType ;
begin
result.BinVal := ALL_RANGE;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer is
-- ------------------------------------------------------------
begin
return CovStructPtr(ID.ID).BinValLength ;
end function GetBinValLength ;
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
variable result : CovBinBaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix2BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix3BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix4BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix5BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix6BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix7BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix8BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType is
-- ------------------------------------------------------------
variable result : CovMatrix9BaseType ;
begin
result.BinVal := CovStructPtr(ID.ID).CovBinPtr(BinIndex).BinVal.all;
result.Action := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Action;
result.Count := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count;
result.AtLeast := CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast;
result.Weight := CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight;
return result ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string is
-- ------------------------------------------------------------
begin
if CovStructPtr(ID.ID).CovBinPtr(BinIndex).Name.all /= "" then
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Name.all ;
else
return DefaultName ;
end if;
end function GetBinName;
------------------------------------------------------------
-- pt local for now -- file formal parameter not allowed with a public method
-- procedure WriteBinName (ID : CoverageIDType; file f : text ; S : string ; Prefix : string := "%% " ) is
procedure WriteBinName (ID : CoverageIDType; variable buf : inout line; S : string ; Prefix : string := "%% " ) is
------------------------------------------------------------
variable Message : MessageStructPtrType ;
variable MessageIndex : integer := 1 ;
-- variable buf : line ;
begin
Message := CovStructPtr(ID.ID).CovMessage ;
if Message = NULL then
write(buf, Prefix & S & GetCovModelName(ID)) ; -- Print name when no message
write(buf, "" & LF) ;
-- writeline(f, buf) ;
else
if CovStructPtr(ID.ID).CovName /= NULL then
-- Print Name if set
write(buf, Prefix & S & CovStructPtr(ID.ID).CovName.all) ;
elsif CovStructPtr(ID.ID).AlertLogID /= OSVVM_COVERAGE_ALERTLOG_ID then
-- otherwise Print AlertLogName if it is set
write(buf, Prefix & S & string'(GetAlertLogName(CovStructPtr(ID.ID).AlertLogID)) ) ;
else
-- otherwise print the first line of the message
write(buf, Prefix & S & Message.Name.all) ;
Message := Message.NextPtr ;
end if ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
WriteMessage(buf, Message, Prefix) ;
end if ;
end procedure WriteBinName ;
------------------------------------------------------------
-- pt local for now -- file formal parameter not allowed with method
procedure WriteBin (
ID : CoverageIDType ;
variable buf : inout line ;
-- file f : text ;
WritePassFail : OsvvmOptionsType ;
WriteBinInfo : OsvvmOptionsType ;
WriteCount : OsvvmOptionsType ;
WriteAnyIllegal : OsvvmOptionsType ;
WritePrefix : string ;
PassName : string ;
FailName : string ;
UsingLocalFile : boolean := FALSE
) is
------------------------------------------------------------
begin
if CovStructPtr(ID.ID).NumBins < 1 then
if WriteBinFileInit or UsingLocalFile then
swrite(buf, WritePrefix & " " & FailName & " ") ;
swrite(buf, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteBin: Coverage model is empty. Nothing to print.") ;
-- writeline(f, buf) ;
end if ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteBin:" &
" Coverage model is empty. Nothing to print.", FAILURE) ;
return ;
end if ;
-- Models with Bins
WriteBinName(ID, buf, "WriteBin: ", WritePrefix) ;
for i in 1 to CovStructPtr(ID.ID).NumBins loop -- CovStructPtr(ID.ID).CovBinPtr.all'range
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT or
(CovStructPtr(ID.ID).CovBinPtr(i).action = COV_ILLEGAL and IsEnabled(WriteAnyIllegal)) or
CovStructPtr(ID.ID).CovBinPtr(i).count < 0 -- Illegal bin with errors
then
-- WriteBin Info
swrite(buf, WritePrefix) ;
if CovStructPtr(ID.ID).CovBinPtr(i).Name.all /= "" then
swrite(buf, CovStructPtr(ID.ID).CovBinPtr(i).Name.all & " ") ;
end if ;
if IsEnabled(WritePassFail) then
-- For illegal bins, AtLeast = 0 and count is negative.
if CovStructPtr(ID.ID).CovBinPtr(i).count >= CovStructPtr(ID.ID).CovBinPtr(i).AtLeast then
swrite(buf, PassName & ' ') ;
else
swrite(buf, FailName & ' ') ;
end if ;
end if ;
if IsEnabled(WriteBinInfo) then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT then
swrite(buf, "Bin:") ;
else
swrite(buf, "Illegal Bin:") ;
end if;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
end if ;
if IsEnabled(WriteCount) then
write(buf, " Count = " & integer'image(abs(CovStructPtr(ID.ID).CovBinPtr(i).count))) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
if CovStructPtr(ID.ID).WeightMode = WEIGHT or CovStructPtr(ID.ID).WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
end if ;
end if ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
end if ;
end loop ;
swrite(buf, "") ;
-- writeline(f, buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) is
------------------------------------------------------------
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal(WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailNameVar.GetOpt ) ;
variable buf : line ;
begin
WriteBin (
ID => ID,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailNameVar.GetOpt )
) ;
WriteToCovFile(buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteBin (
ID => ID
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) is
------------------------------------------------------------
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal (WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailNameVar.GetOpt ) ;
file LocalWriteBinFile : text open OpenKind is FileName ;
variable buf : line ;
begin
WriteBin (
ID => ID,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailNameVar.GetOpt ),
UsingLocalFile => TRUE
);
writeline(LocalWriteBinFile, buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
------------------------------------------------------------
ID : CoverageIDType ;
LogLevel : LogType ;
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE
) is
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteBin (
ID => ID,
FileName => FileName,
OpenKind => OpenKind
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
-- Development only
-- pt local for now -- file formal parameter not allowed with method
-- procedure DumpBin (ID : CoverageIDType; file f : text ) is
procedure DumpBin (ID : CoverageIDType; variable buf : inout line ) is
------------------------------------------------------------
-- variable buf : line ;
begin
WriteBinName(ID, buf, "DumpBin: ") ;
-- writeline(f, buf) ;
-- if CovStructPtr(ID.ID).NumBins < 1 then
-- Write(f, "%%FATAL, Coverage Model is empty. Nothing to print." & LF ) ;
-- end if ;
for i in 1 to CovStructPtr(ID.ID).NumBins loop -- CovStructPtr(ID.ID).CovBinPtr.all'range
swrite(buf, "%% ") ;
if CovStructPtr(ID.ID).CovBinPtr(i).Name.all /= "" then
swrite(buf, CovStructPtr(ID.ID).CovBinPtr(i).Name.all & " ") ;
end if ;
swrite(buf, "Bin:") ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
case CovStructPtr(ID.ID).CovBinPtr(i).action is
when COV_COUNT => swrite(buf, " Count = ") ;
when COV_IGNORE => swrite(buf, " Ignore = ") ;
when COV_ILLEGAL => swrite(buf, " Illegal = ") ;
when others => swrite(buf, " BOGUS BOGUS BOGUS = ") ;
end case ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).count) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
end loop ;
swrite(buf, "") ;
-- writeline(f,buf) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) is
------------------------------------------------------------
variable buf : line ;
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
DumpBin(ID, buf) ;
WriteToCovFile(buf) ;
end if ;
end procedure DumpBin ;
------------------------------------------------------------
-- pt local
-- procedure WriteCovHoles (ID : CoverageIDType; file f : text; PercentCov : real := 100.0; UsingLocalFile : boolean := FALSE) is
procedure WriteCovHoles (ID : CoverageIDType; variable buf : inout line; PercentCov : real := 100.0; UsingLocalFile : boolean := FALSE) is
------------------------------------------------------------
-- variable buf : line ;
begin
if CovStructPtr(ID.ID).NumBins < 1 then
if WriteBinFileInit or UsingLocalFile then
-- Duplicate Alert in specified file
swrite(buf, "%% Alert FAILURE " & GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model empty. Nothing to print.") ;
-- writeline(f, buf) ;
end if ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model empty. Nothing to print.", FAILURE) ;
return ;
end if ;
-- Models with Bins
WriteBinName(ID, buf, "WriteCovHoles: ") ;
-- writeline(f, buf) ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).PercentCov < PercentCov then
swrite(buf, "%% ") ;
if CovStructPtr(ID.ID).CovBinPtr(i).Name.all /= "" then
swrite(buf, CovStructPtr(ID.ID).CovBinPtr(i).Name.all & " ") ;
end if ;
swrite(buf, "Bin:") ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
write(buf, " Count = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Count)) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
if CovStructPtr(ID.ID).WeightMode = WEIGHT or CovStructPtr(ID.ID).WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
end if ;
write(buf, "" & LF) ;
-- writeline(f, buf) ;
end if ;
end loop CovLoop ;
swrite(buf, "") ;
-- writeline(f, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) is
------------------------------------------------------------
variable buf : line ;
begin
WriteCovHoles(ID, buf, PercentCov) ;
WriteToCovFile(buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, CovStructPtr(ID.ID).CovTarget) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; PercentCov : real ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, PercentCov) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
variable buf : line ;
begin
-- WriteCovHoles(ID, CovHoleFile, CovStructPtr(ID.ID).CovTarget, TRUE) ;
WriteCovHoles(ID, buf, CovStructPtr(ID.ID).CovTarget, TRUE) ;
writeline(CovHoleFile, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, FileName, OpenKind) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
variable buf : line ;
begin
-- WriteCovHoles(ID, CovHoleFile, PercentCov, TRUE) ;
WriteCovHoles(ID, buf, PercentCov, TRUE) ;
writeline(CovHoleFile, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, FileName, PercentCov, OpenKind) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- pt local
impure function FindExactBin (
-- find an exact match to a bin wrt BinVal, Action, AtLeast, Weight, and Name
------------------------------------------------------------
ID : CoverageIDType ;
Merge : boolean ;
BinVal : RangeArrayType ;
Action : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string
) return integer is
begin
if Merge then
for i in 1 to CovStructPtr(ID.ID).NumBins loop
if (BinVal = CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) and (Action = CovStructPtr(ID.ID).CovBinPtr(i).Action) and
(AtLeast = CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) and (Weight = CovStructPtr(ID.ID).CovBinPtr(i).Weight) and
(Name = CovStructPtr(ID.ID).CovBinPtr(i).Name.all) then
return i ;
end if;
end loop ;
end if ;
return 0 ;
end function FindExactBin ;
------------------------------------------------------------
-- pt local
procedure read (
------------------------------------------------------------
buf : inout line ;
NamePtr : inout line ;
NameLength : in integer ;
ReadValid : out boolean
) is
variable Name : string(1 to NameLength) ;
begin
if NameLength > 0 then
read(buf, Name, ReadValid) ;
NamePtr := new string'(Name) ;
else
ReadValid := TRUE ;
NamePtr := new string'("") ;
end if ;
end procedure read ;
------------------------------------------------------------
-- pt local
procedure ReadCovVars (ID : CoverageIDType; file CovDbFile : text; Good : out boolean ) is
------------------------------------------------------------
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable ReadValid : boolean ;
variable GoodLoop1 : boolean ;
variable iSeed : RandomSeedType ;
variable iIllegalMode : integer ;
variable iWeightMode : integer ;
variable iWeightScale : real ;
variable iCovThreshold : real ;
variable iCountMode : integer ;
variable iNumberOfMessages : integer ;
variable iThresholdingEnable : boolean ;
variable iCovTarget : real ;
variable iMergingEnable : boolean ;
begin
-- ReadLoop0 : while not EndFile(CovDbFile) loop
ReadLoop0 : loop -- allows emulation of "return when"
-- ReadLine to Get Coverage Model Name, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: No Coverage Data to read", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
if buf.all /= "Coverage_Model_Not_Named" then
SetName(ID, buf.all) ;
end if ;
exit ReadLoop0 ;
end loop ReadLoop0 ;
-- ReadLoop1 : while not EndFile(CovDbFile) loop
ReadLoop1 : loop
-- ReadLine to Get Variables, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
read(buf, iSeed, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Seed", FAILURE) ;
-- RV.SetSeed( iSeed ) ;
CovStructPtr(ID.ID).RV := iSeed ;
CovStructPtr(ID.ID).RvSeedInit := TRUE ;
read(buf, iCovThreshold, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading CovThreshold", FAILURE) ;
CovStructPtr(ID.ID).CovThreshold := iCovThreshold ;
read(buf, iIllegalMode, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading IllegalMode", FAILURE) ;
SetIllegalMode(ID, IllegalModeType'val( iIllegalMode )) ;
read(buf, iWeightMode, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading WeightMode", FAILURE) ;
CovStructPtr(ID.ID).WeightMode := WeightModeType'val( iWeightMode ) ;
read(buf, iWeightScale, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading WeightScale", FAILURE) ;
CovStructPtr(ID.ID).WeightScale := iWeightScale ;
read(buf, iCountMode, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading CountMode", FAILURE) ;
CovStructPtr(ID.ID).CountMode := CountModeType'val( iCountMode ) ;
read(buf, iThresholdingEnable, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading ThresholdingEnable", FAILURE) ;
CovStructPtr(ID.ID).ThresholdingEnable := iThresholdingEnable ;
read(buf, iCovTarget, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading CovTarget", FAILURE) ;
CovStructPtr(ID.ID).CovTarget := iCovTarget ;
read(buf, iMergingEnable, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading MergingEnable", FAILURE) ;
CovStructPtr(ID.ID).MergingEnable := iMergingEnable ;
exit ReadLoop1 ;
end loop ReadLoop1 ;
GoodLoop1 := ReadValid ;
-- ReadLoop2 : while not EndFile(CovDbFile) loop
ReadLoop2 : while ReadValid loop
-- ReadLine to Coverage Model Header WriteBin Message, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
read(buf, iNumberOfMessages, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading NumberOfMessages", FAILURE) ;
for i in 1 to iNumberOfMessages loop
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: End of File while reading Messages", FAILURE) ;
ReadLine(CovDbFile, buf) ;
SetMessage(ID, buf.all) ;
end loop ;
exit ReadLoop2 ;
end loop ReadLoop2 ;
Good := ReadValid and GoodLoop1 ;
end procedure ReadCovVars ;
------------------------------------------------------------
-- pt local
procedure ReadCovDbInfo (
------------------------------------------------------------
ID : CoverageIDType ;
File CovDbFile : text ;
variable NumRangeItems : out integer ;
variable NumLines : out integer ;
variable Good : out boolean
) is
variable buf : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
begin
ReadLoop : loop
-- ReadLine to RangeItems NumLines, skip blank and comment lines, fails when file empty
exit when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Coverage DB File Incomplete", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next when Empty ;
read(buf, NumRangeItems, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading NumRangeItems", FAILURE) ;
read(buf, NumLines, ReadValid) ;
exit when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading NumLines", FAILURE) ;
exit ;
end loop ReadLoop ;
Good := ReadValid ;
end procedure ReadCovDbInfo ;
------------------------------------------------------------
-- pt local
procedure ReadCovDbDataBase (
------------------------------------------------------------
ID : CoverageIDType ;
File CovDbFile : text ;
constant NumRangeItems : in integer ;
constant NumLines : in integer ;
constant Merge : in boolean ;
variable Good : out boolean
) is
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable ReadValid : boolean ;
-- Format: Action Count min1 max1 min2 max2 ....
variable Action : integer ;
variable Count : integer ;
variable BinVal : RangeArrayType(1 to NumRangeItems) ;
variable index : integer ;
variable AtLeast : integer ;
variable Weight : integer ;
variable PercentCov : real ;
variable NameLength : integer ;
variable SkipBlank : character ;
variable NamePtr : line ;
begin
GrowBins(ID, NumLines) ;
ReadLoop : for i in 1 to NumLines loop
GetValidLineLoop: loop
exit ReadLoop when AlertIf(CovStructPtr(ID.ID).AlertLogID, EndFile(CovDbFile), GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Did not read specified number of lines", FAILURE) ;
ReadLine(CovDbFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next GetValidLineLoop when Empty ; -- replace with EmptyLine(buf)
exit GetValidLineLoop ;
end loop ;
read(buf, Action, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Action", FAILURE) ;
read(buf, Count, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Count", FAILURE) ;
read(buf, AtLeast, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading AtLeast", FAILURE) ;
read(buf, Weight, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Weight", FAILURE) ;
read(buf, PercentCov, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading PercentCov", FAILURE) ;
read(buf, BinVal, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading BinVal", FAILURE) ;
read(buf, NameLength, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Bin Name Length", FAILURE) ;
read(buf, SkipBlank, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Bin Name Length", FAILURE) ;
read(buf, NamePtr, NameLength, ReadValid) ;
exit ReadLoop when AlertIfNot(CovStructPtr(ID.ID).AlertLogID, ReadValid, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.ReadCovDb: Failed while reading Bin Name", FAILURE) ;
index := FindExactBin(ID, Merge, BinVal, Action, AtLeast, Weight, NamePtr.all) ;
if index > 0 then
-- Bin is an exact match so only merge the count values
CovStructPtr(ID.ID).CovBinPtr(index).Count := CovStructPtr(ID.ID).CovBinPtr(index).Count + Count ;
CovStructPtr(ID.ID).CovBinPtr(index).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID.ID).CovBinPtr.all(index).Count,
AtLeast => CovStructPtr(ID.ID).CovBinPtr.all(index).AtLeast ) ;
else
InsertNewBin(ID, BinVal, Action, Count, AtLeast, Weight, NamePtr.all, PercentCov) ;
end if ;
deallocate(NamePtr) ;
end loop ReadLoop ;
Good := ReadValid ;
end ReadCovDbDataBase ;
------------------------------------------------------------
-- pt local
procedure ReadCovDb (ID : CoverageIDType; File CovDbFile : text; Merge : boolean := FALSE) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
-- file CovDbFile : text open READ_MODE is FileName ;
variable NumRangeItems : integer ;
variable NumLines : integer ;
variable ReadValid : boolean ;
begin
if not Merge then
Deallocate(ID) ; -- remove any old bins
end if ;
ReadLoop : loop
-- Read coverage private variables to the file
ReadCovVars(ID, CovDbFile, ReadValid) ;
exit when not ReadValid ;
-- Get Coverage dimensions and number of items in file.
ReadCovDbInfo(ID, CovDbFile, NumRangeItems, NumLines, ReadValid) ;
exit when not ReadValid ;
-- Read the file
ReadCovDbDataBase(ID, CovDbFile, NumRangeItems, NumLines, Merge, ReadValid) ;
exit ;
end loop ReadLoop ;
end ReadCovDb ;
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file CovDbFile : text open READ_MODE is FileName ;
begin
ReadCovDb(ID, CovDbFile, Merge) ;
end procedure ReadCovDb ;
------------------------------------------------------------
-- pt local
procedure WriteCovDbVars (ID : CoverageIDType; file CovDbFile : text ) is
------------------------------------------------------------
variable buf : line ;
variable CovMessageCount : integer ;
begin
-- write coverage private variables to the file
if CovStructPtr(ID.ID).CovName /= NULL then
swrite(buf, CovStructPtr(ID.ID).CovName.all) ;
else
swrite(buf, "Coverage_Model_Not_Named") ;
end if ;
writeline(CovDbFile, buf) ;
write(buf, CovStructPtr(ID.ID).RV ) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovThreshold, RIGHT, 0, 5) ;
write(buf, ' ') ;
write(buf, IllegalModeType'pos(CovStructPtr(ID.ID).IllegalMode)) ;
write(buf, ' ') ;
write(buf, WeightModeType'pos(CovStructPtr(ID.ID).WeightMode)) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).WeightScale, RIGHT, 0, 6) ;
write(buf, ' ') ;
write(buf, CountModeType'pos(CovStructPtr(ID.ID).CountMode)) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).ThresholdingEnable) ; -- boolean
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovTarget, RIGHT, 0, 6) ; -- Real
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).MergingEnable) ; -- boolean
write(buf, ' ') ;
writeline(CovDbFile, buf) ;
GetMessageCount(CovStructPtr(ID.ID).CovMessage, CovMessageCount) ;
write(buf, CovMessageCount ) ;
writeline(CovDbFile, buf) ;
WriteMessage(CovDbFile, CovStructPtr(ID.ID).CovMessage) ;
end procedure WriteCovDbVars ;
------------------------------------------------------------
-- pt local
procedure WriteCovDb (ID : CoverageIDType; file CovDbFile : text ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
variable buf : line ;
begin
-- write Cover variables to the file
WriteCovDbVars(ID, CovDbFile ) ;
-- write NumRangeItems, NumLines
write(buf, CovStructPtr(ID.ID).CovBinPtr(1).BinVal'length) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).NumBins) ;
write(buf, ' ') ;
writeline(CovDbFile, buf) ;
-- write coverage to a file
writeloop : for LineCount in 1 to CovStructPtr(ID.ID).NumBins loop
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Action) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Count) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).AtLeast) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Weight) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).PercentCov, RIGHT, 0, 4) ;
write(buf, ' ') ;
WriteBinVal(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).BinVal.all) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Name'length) ;
write(buf, ' ') ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(LineCount).Name.all) ;
writeline(CovDbFile, buf) ;
end loop WriteLoop ;
end procedure WriteCovDb ;
------------------------------------------------------------
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file CovDbFile : text open OpenKind is FileName ;
begin
if CovStructPtr(ID.ID).NumBins >= 1 then
WriteCovDb(ID, CovDbFile) ;
else
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.WriteCovDb: no bins defined ", FAILURE) ;
end if ;
file_close(CovDbFile) ;
end procedure WriteCovDb ;
-- ------------------------------------------------------------
-- procedure WriteCovDb (ID : CoverageIDType) is
-- ------------------------------------------------------------
-- begin
-- if WriteCovDbFileInit then
-- WriteCovDb(ID, WriteCovDbFile) ;
-- else
-- report "CoveragePkg: WriteCovDb file not specified" severity failure ;
-- end if ;
-- end procedure WriteCovDb ;
------------------------------------------------------------
-- pt local
procedure WriteCovSettingsYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
variable TotalCovCount, TotalCovGoal : integer ;
begin
-- write bins to YAML file
write(buf, Prefix & "Settings: " & LF) ;
write(buf, Prefix & " CovWeight: " & to_string(CovStructPtr(ID.ID).CovWeight) & LF) ;
write(buf, Prefix & " Goal: " & to_string(CovStructPtr(ID.ID).CovTarget, 1) & LF) ;
write(buf, Prefix & " WeightMode: """ & to_upper(to_string(CovStructPtr(ID.ID).WeightMode)) & '"' & LF) ;
write(buf, Prefix & " Seeds: [" & to_string(CovStructPtr(ID.ID).RV, ", ") & "]" & LF) ;
write(buf, Prefix & " CountMode: """ & to_upper(to_string(CovStructPtr(ID.ID).CountMode)) & '"' & LF) ;
write(buf, Prefix & " IllegalMode: """ & to_upper(to_string(CovStructPtr(ID.ID).IllegalMode)) & '"' & LF) ;
write(buf, Prefix & " Threshold: " & to_string(CovStructPtr(ID.ID).CovThreshold, 1) & LF) ;
write(buf, Prefix & " ThresholdEnable: """ & to_upper(to_string(CovStructPtr(ID.ID).ThresholdingEnable)) & '"' & LF) ;
GetTotalCovCountAndGoal (ID, TotalCovCount, TotalCovGoal) ;
write(buf, Prefix & " TotalCovCount: " & to_string(TotalCovCount) & LF) ;
write(buf, Prefix & " TotalCovGoal: " & to_string(TotalCovGoal) & LF) ;
end procedure WriteCovSettingsYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovFieldNameYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
variable Dimensions : integer ;
variable FieldWidth : integer ;
variable FieldName : FieldNameArrayPtrType ;
begin
FieldName := CovStructPtr(ID.ID).FieldName ;
Dimensions := CovStructPtr(ID.ID).BinValLength ;
if FieldName = NULL then
FieldWidth := 0 ;
else
FieldWidth := FieldName'length;
end if;
write(buf, Prefix & " FieldNames: " & LF) ;
for i in 1 to Dimensions loop
if i > FieldWidth then
write(buf, Prefix & " - ""Bin" & to_string(i) & '"' & LF) ;
else
write(buf, Prefix & " - """ & FieldName(i).all & '"' & LF) ;
end if ;
end loop ;
end procedure WriteCovFieldNameYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovBinInfoYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
begin
-- write bins to YAML file
write(buf, Prefix & "BinInfo: " & LF) ;
write(buf, Prefix & " Dimensions: " & to_string(CovStructPtr(ID.ID).BinValLength) & LF) ;
WriteCovFieldNameYaml(ID, buf, Prefix) ;
write(buf, Prefix & " NumBins: " & to_string(CovStructPtr(ID.ID).NumBins) & LF) ;
end procedure WriteCovBinInfoYaml ;
------------------------------------------------------------
procedure WriteBinValYaml (
-- package local for now
------------------------------------------------------------
variable buf : inout line ;
constant BinVal : in RangeArrayType ;
constant Prefix : in string
) is
begin
for i in BinVal'range loop
write(buf, Prefix &
"- {Min: " & to_string(BinVal(i).min) &
", Max: " & to_string(BinVal(i).max) & "}" & LF) ;
end loop ;
end procedure WriteBinValYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovBinsYaml (ID : CoverageIDType; variable buf : inout LINE; Prefix : string ) is
------------------------------------------------------------
variable Action : integer ;
variable CovBin : CovBinInternalBaseType ;
begin
-- write bins to YAML file
write(buf, Prefix & "Bins: " & LF) ;
writeloop : for EachLine in 1 to CovStructPtr(ID.ID).NumBins loop
CovBin := CovStructPtr(ID.ID).CovBinPtr(EachLine) ;
write(buf, Prefix & " - Name: """ & CovBin.Name.all & '"' & LF) ;
write(buf, Prefix & " Type: """ & ActionToName(CovBin.Action) & '"' & LF ) ;
write(buf, Prefix & " Range: " & LF) ;
WriteBinValYaml(buf, CovBin.BinVal.all, Prefix & " ") ;
write(buf, Prefix & " Count: " & to_string(CovBin.Count) & LF) ;
write(buf, Prefix & " AtLeast: " & to_string(CovBin.AtLeast) & LF) ;
write(buf, Prefix & " PercentCov: " & to_string(CovBin.PercentCov, 4) & LF) ;
end loop writeloop ;
end procedure WriteCovBinsYaml ;
------------------------------------------------------------
-- pt local
procedure WriteCovYaml (ID : CoverageIDType; file CovYamlFile : text; TestCaseName : string ) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
-- If no bins, FAIL and return (if resumed)
if CovStructPtr(ID.ID).NumBins < 1 then
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") &
"CoveragePkg.WriteCovYaml: no bins defined ", FAILURE) ;
return ;
end if ;
write(buf, NAME_PREFIX & "- Name: " & '"' & GetName(ID) & '"' & LF) ;
--!! TODO: Add Writing for ParentName, ReportMode, Search, PrintParent
write(buf, NAME_PREFIX & " TestCases: " & LF) ;
write(buf, NAME_PREFIX & " - " & '"' & TestCaseName & '"' & LF) ;
--!! Add code to list out merged tests
write(buf, NAME_PREFIX & " Coverage: " & to_string(GetCov(ID), 2) & LF) ;
WriteCovSettingsYaml(ID, buf, NAME_PREFIX & " ") ;
WriteCovBinInfoYaml (ID, buf, NAME_PREFIX & " ") ;
WriteCovBinsYaml (ID, buf, NAME_PREFIX & " ") ;
writeline(CovYamlFile, buf) ;
end procedure WriteCovYaml ;
-- ------------------------------------------------------------
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
-- ------------------------------------------------------------
-- file CovYamlFile : text open OpenKind is FileName ;
-- begin
-- WriteCovYaml(ID, CovYamlFile) ;
-- file_close(CovYamlFile) ;
-- end procedure WriteCovYaml ;
------------------------------------------------------------
procedure WriteCovYaml (FileName : string := ""; Coverage : real ; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_cov.yml", FileName) ;
file CovYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "Coverage: " & to_string(Coverage, 2) & LF) ;
swrite(buf, "Models: ") ;
writeline(CovYamlFile, buf) ;
for i in 1 to NumItems loop
if CovStructPtr(i).NumBins >= 1 then
WriteCovYaml(CoverageIDType'(ID => i), CovYamlFile, GetAlertLogName) ;
end if ;
end loop ;
file_close(CovYamlFile) ;
end procedure WriteCovYaml ;
------------------------------------------------------------
-- pt local. Find a specific token potentially split across lines
procedure ReadFindToken (
------------------------------------------------------------
file ReadFile : text ;
constant Token : in string ;
variable buf : inout line ;
variable Found : out boolean
) is
variable Empty, MultiLineComment, ReadValid : boolean ;
variable vToken : string(1 to Token'length) ;
begin
Found := FALSE ;
ReadLoop : loop
if buf = NULL or buf.all'length = 0 then
-- return Good FALSE when file empty
exit ReadLoop when EndFile(ReadFile) ;
-- Get Next Line
ReadLine(ReadFile, buf) ;
end if ;
-- Skip blank and multi-line comment lines
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLoop when Empty;
read(buf, vToken, ReadValid) ;
if not ReadValid then
deallocate(buf) ;
next ReadLoop ;
end if ;
next ReadLoop when vToken /= Token ;
Found := TRUE ;
exit ReadLoop ;
end loop ReadLoop ;
end procedure ReadFindToken ;
------------------------------------------------------------
-- pt local
procedure ReadQuotedString (
------------------------------------------------------------
variable buf : inout line ;
variable Name : inout line
) is
variable char : character ;
variable vString : string(1 to buf'length) ;
variable Index : integer := 1 ;
variable Found, Empty, ReadValid : boolean ;
begin
Found := FALSE ;
if Name /= NULL then
deallocate(Name) ;
end if ;
ReadLoop : loop
SkipWhiteSpace(buf, Empty) ; -- Skips white space at beginning of line
exit ReadLoop when Empty ;
exit ReadLoop when buf.all(buf'left) /= '"' ;
Read(buf, Char, ReadValid) ;
exit ReadLoop when not ReadValid ;
for i in vString'range loop
Read(buf, vString(i), ReadValid) ;
exit ReadLoop when not ReadValid ;
if vString(i) = '"' then
Index := i - 1 ;
Found := TRUE ;
exit ;
end if ;
exit ReadLoop when buf.all'length = 0 ;
end loop ;
end loop ReadLoop ;
if Found then
Name := new string'(vString(1 to Index)) ;
end if ;
end procedure ReadQuotedString ;
------------------------------------------------------------
-- pt local
procedure ReadCovModelNameYaml (
------------------------------------------------------------
variable ID : out CoverageIDType ;
file CovYamlFile : text ;
variable Found : out boolean
) is
variable buf : line ;
variable sName : line ;
begin
Found := FALSE ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "- Name:", buf, Found) ;
exit ReadLoop when not Found ;
-- Get the Name
ReadQuotedString(buf, sName) ;
exit when AlertIf(OSVVM_COV_ALERTLOG_ID, sName = NULL,
"CoveragePkg.ReadCovYaml: Unnamed Coverage Model.", COV_READ_YAML_ALERT_LEVEL);
--!! TODO: Add reading for ParentName, ReportMode, Search, PrintParent
ID := NewID(sName.all, ReportMode => ENABLED, Search => NAME_AND_PARENT, PrintParent => PRINT_NAME_AND_PARENT) ;
deallocate(sName) ;
Found := TRUE ;
exit ;
end loop ReadLoop ;
end procedure ReadCovModelNameYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovSettingsYaml (
------------------------------------------------------------
constant CovID : in CoverageIDType ;
file CovYamlFile : text ;
variable Found : out boolean
) is
variable buf : line ;
variable Name : line ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
variable vInteger : integer ;
variable vReal : real ;
variable Seed1, Seed2 : integer ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "Settings:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Settings:""", COV_READ_YAML_ALERT_LEVEL) ;
-- CovWeight
ReadFindToken (CovYamlFile, "CovWeight:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Settings:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vInteger, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading CovWeight value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).CovWeight := vInteger ;
-- Goal / CovTarget
ReadFindToken (CovYamlFile, "Goal:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Goal:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vReal, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading CovTarget value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).CovTarget := vReal ;
-- WeightMode
ReadFindToken (CovYamlFile, "WeightMode:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""WeightMode:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading WeightMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "REMAIN" then
CovStructPtr(ID).WeightMode := REMAIN ;
else -- at_least
CovStructPtr(ID).WeightMode := AT_LEAST ;
end if ;
-- Seeds
ReadFindToken (CovYamlFile, "Seeds:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Seeds:""", COV_READ_YAML_ALERT_LEVEL) ;
-- [
ReadFindToken (CovYamlFile, "[", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Seeds ""[""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Seed1, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Seed1 value.", COV_READ_YAML_ALERT_LEVEL) ;
-- ,
ReadFindToken (CovYamlFile, ",", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Seed #2 "",""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Seed2, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Seed2 value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).RV := (Seed1, Seed2) ;
-- CountMode
ReadFindToken (CovYamlFile, "CountMode:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""CountMode:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading CountMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "COUNT_ALL" then
CovStructPtr(ID).CountMode := COUNT_ALL ;
else
CovStructPtr(ID).CountMode := COUNT_FIRST ;
end if ;
-- IllegalMode
ReadFindToken (CovYamlFile, "IllegalMode:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""IllegalMode:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading IllegalMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "ILLEGAL_OFF" then
CovStructPtr(ID).IllegalMode := ILLEGAL_OFF ;
elsif Name.all = "ILLEGAL_FAILURE" then
CovStructPtr(ID).IllegalMode := ILLEGAL_FAILURE ;
else
CovStructPtr(ID).IllegalMode := ILLEGAL_ON ;
end if ;
-- Threshold
ReadFindToken (CovYamlFile, "Threshold:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Threshold:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vReal, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Threshold value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).CovThreshold := vReal ;
-- ThresholdEnable
ReadFindToken (CovYamlFile, "ThresholdEnable:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""ThresholdEnable:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading IllegalMode value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "TRUE" then
CovStructPtr(ID).ThresholdingEnable := TRUE ;
else
CovStructPtr(ID).ThresholdingEnable := FALSE ;
end if ;
-- TotalCovCount - read and toss
ReadFindToken (CovYamlFile, "TotalCovCount:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""TotalCovCount:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vInteger, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading TotalCovCount value.", COV_READ_YAML_ALERT_LEVEL) ;
-- Value not used
-- TotalCovGoal - read and toss
ReadFindToken (CovYamlFile, "TotalCovGoal:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""TotalCovGoal:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, vInteger, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading TotalCovGoal value.", COV_READ_YAML_ALERT_LEVEL) ;
-- End
Found := TRUE ;
exit ReadLoop ;
end loop ReadLoop ;
deallocate(Name) ;
end procedure ReadCovSettingsYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovBinInfoYaml (
------------------------------------------------------------
constant CovID : in CoverageIDType ;
file CovYamlFile : text ;
variable Dimensions : out integer ;
variable NumBins : out integer ;
variable Found : out boolean
) is
variable buf : line ;
variable FieldNameArray : FieldNameArrayType(1 to 20) ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
variable ReadValid : boolean ;
variable FoundFieldName : boolean ;
begin
Found := FALSE ;
Dimensions := 0 ;
NumBins := 0 ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "BinInfo:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""BinInfo:""", COV_READ_YAML_ALERT_LEVEL) ;
-- Dimensions
ReadFindToken (CovYamlFile, "Dimensions:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Dimensions:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Dimensions, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Dimensions value.", COV_READ_YAML_ALERT_LEVEL) ;
CovStructPtr(ID).BinValLength := Dimensions ;
-- FieldNames
ReadFindToken (CovYamlFile, "FieldNames:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""FieldNames:""", COV_READ_YAML_ALERT_LEVEL) ;
-- FieldNames Values
FoundFieldName := FALSE ;
for i in 1 to Dimensions loop
ReadFindToken (CovYamlFile, "-", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Field Name deliminter '-'.", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, FieldNameArray(i)) ;
exit ReadLoop when AlertIf(AlertLogID, FieldNameArray(i) = NULL,
"CoveragePkg.ReadCovYaml Error while reading Field Name value # " & to_string(i), COV_READ_YAML_ALERT_LEVEL) ;
if FieldNameArray(i).all /= ("Bin" & to_string(i)) then
FoundFieldName := TRUE ;
end if ;
end loop ;
if FoundFieldName then
CovStructPtr(ID).FieldName := new FieldNameArrayType'(FieldNameArray(1 to Dimensions)) ;
end if ;
-- NumBins
ReadFindToken (CovYamlFile, "NumBins:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""NumBins:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, NumBins, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading NumBins value.", COV_READ_YAML_ALERT_LEVEL) ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
if not Found or not FoundFieldName then
-- clean up pointers
for i in 1 to Dimensions loop
deallocate(FieldNameArray(i)) ;
end loop ;
end if ;
end procedure ReadCovBinInfoYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovBinValYaml (
------------------------------------------------------------
file CovYamlFile : text ;
constant AlertLogID : in AlertLogIDType ;
variable BinVal : out RangeArrayType ;
variable Found : out boolean
) is
variable buf : line ;
variable Min, Max : integer ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop: loop
-- Range:
ReadFindToken (CovYamlFile, "Range:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Range:""", COV_READ_YAML_ALERT_LEVEL) ;
-- RangeArrayType
for i in BinVal'range loop
-- - {Min:
ReadFindToken (CovYamlFile, "- {Min:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Bins ""Min:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Min, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Min value.", COV_READ_YAML_ALERT_LEVEL) ;
-- , Max:
ReadFindToken (CovYamlFile, ", Max:", buf, Found) ;
exit ReadLoop when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Bins ""Max:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Max, ReadValid) ;
exit ReadLoop when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Max value.", COV_READ_YAML_ALERT_LEVEL) ;
BinVal(i) := (Min => Min, Max => Max) ;
end loop ;
Found := TRUE ;
exit ReadLoop ;
end loop ;
end procedure ReadCovBinValYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovOneBinYaml (
------------------------------------------------------------
file CovYamlFile : text ;
constant CovID : in CoverageIDType ;
constant Merge : in boolean ;
constant Dimensions : in integer ;
variable Found : out boolean
) is
variable buf : line ;
variable Name : line ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
variable NamePtr : line ;
variable Action : integer ;
variable BinVal : RangeArrayType(1 to Dimensions) ;
variable Count : integer ;
variable AtLeast : integer ;
variable Weight : integer ;
variable PercentCov : real ;
variable Index : integer ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop: loop
-- - Name:
ReadFindToken (CovYamlFile, "- Name:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find Bins ""Name:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, NamePtr) ;
exit ReadLoop when AlertIf(AlertLogID, NamePtr = NULL,
"CoveragePkg.ReadCovYaml Error while reading Name value.", COV_READ_YAML_ALERT_LEVEL) ;
-- Type:
ReadFindToken (CovYamlFile, "Type:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Type:""", COV_READ_YAML_ALERT_LEVEL) ;
ReadQuotedString(buf, Name) ;
exit ReadLoop when AlertIf(AlertLogID, Name = NULL,
"CoveragePkg.ReadCovYaml Error while reading Type value.", COV_READ_YAML_ALERT_LEVEL) ;
if Name.all = "COUNT" then
Action := 1 ;
elsif Name.all = "IGNORE" then
Action := 0 ;
else -- Illegal
Action := -1 ;
end if ;
deallocate(Name) ;
-- BinVal
ReadCovBinValYaml(CovYamlFile, AlertLogID, BinVal, Found) ;
exit when not Found ;
-- Count:
ReadFindToken (CovYamlFile, "Count:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Count:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, Count, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading Count value.", COV_READ_YAML_ALERT_LEVEL) ;
-- AtLeast:
ReadFindToken (CovYamlFile, "AtLeast:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""AtLeast:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, AtLeast, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading AtLeast value.", COV_READ_YAML_ALERT_LEVEL) ;
Weight := AtLeast ;
-- PercentCov:
ReadFindToken (CovYamlFile, "PercentCov:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""PercentCov:""", COV_READ_YAML_ALERT_LEVEL) ;
Read(buf, PercentCov, ReadValid) ;
exit when AlertIf(AlertLogID, not ReadValid,
"CoveragePkg.ReadCovYaml Error while reading PercentCov value.", COV_READ_YAML_ALERT_LEVEL) ;
-- Insert the Bin
Index := FindExactBin(CovID, Merge, BinVal, Action, AtLeast, Weight, NamePtr.all) ;
if Index > 0 then
-- Bin is an exact match so only merge the count values
CovStructPtr(ID).CovBinPtr(Index).Count := CovStructPtr(ID).CovBinPtr(Index).Count + Count ;
CovStructPtr(ID).CovBinPtr(Index).PercentCov := CalcPercentCov(
Count => CovStructPtr(ID).CovBinPtr.all(Index).Count,
AtLeast => CovStructPtr(ID).CovBinPtr.all(Index).AtLeast ) ;
else
InsertNewBin(CovID, BinVal, Action, Count, AtLeast, Weight, NamePtr.all, PercentCov) ;
end if ;
deallocate(NamePtr) ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
end procedure ReadCovOneBinYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovBinsYaml (
------------------------------------------------------------
constant CovID : in CoverageIDType ;
file CovYamlFile : text ;
constant Dimensions : in integer ;
constant NumBins : in integer ;
variable Found : out boolean ;
constant Merge : in boolean := FALSE
) is
variable buf : line ;
variable FieldNameArray : FieldNameArrayType(1 to 20) ;
constant ID : integer := CovID.ID ;
constant AlertLogID : AlertLogIDType := CovStructPtr(ID).AlertLogID ;
begin
Found := FALSE ;
ReadLoop: loop
ReadFindToken (CovYamlFile, "Bins:", buf, Found) ;
exit when AlertIf(AlertLogID, not Found,
"CoveragePkg.ReadCovYaml did not find ""Bins:""", COV_READ_YAML_ALERT_LEVEL) ;
GrowBins(CovID, NumBins) ;
for i in 1 to NumBins loop
ReadCovOneBinYaml(CovYamlFile, CovID, Merge, Dimensions, Found) ;
exit ReadLoop when not Found ;
end loop ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
end procedure ReadCovBinsYaml ;
------------------------------------------------------------
-- pt local
procedure ReadCovModelYaml (
------------------------------------------------------------
file CovYamlFile : text ;
variable Found : out boolean ;
constant Merge : in boolean := FALSE
) is
variable CovID : CoverageIDType ;
variable Dimensions : integer ;
variable NumBins : integer ;
variable FoundModelName : boolean ;
begin
Found := FALSE ;
FoundModelName := FALSE ;
ReadLoop: loop
ReadCovModelNameYaml(CovID, CovYamlFile, Found) ;
exit when not Found ;
FoundModelName := TRUE ;
if not Merge then -- remove any old bins
DeallocateBins(CovID) ;
end if ;
-- Nothing to do with this for now
-- ReadCovTestCasesYaml(CovID, CovYamlFile, Found) ;
-- exit when not Found ;
-- On merge, new settings apply
ReadCovSettingsYaml(CovID, CovYamlFile, Found) ;
exit when not Found ;
-- On merge, new settings apply
ReadCovBinInfoYaml(CovID, CovYamlFile, Dimensions, NumBins, Found) ;
exit when not Found ;
-- On merge, matching bins are merged
ReadCovBinsYaml(CovID, CovYamlFile, Dimensions, NumBins, Found, Merge) ;
exit when not Found ;
-- End
Found := TRUE ;
exit ;
end loop ReadLoop ;
if FoundModelName and not Found then
-- remove partially constructed model
Deallocate(CovID) ;
end if ;
end procedure ReadCovModelYaml ;
-- ------------------------------------------------------------
-- procedure ReadCovYaml (ModelName : string; FileName : string) is
-- ------------------------------------------------------------
-- file CovYamlFile : text open READ_MODE is FileName ;
-- begin
-- ID := NewID("ModelName"
-- ReadCovYaml(ID, CovYamlFile) ;
-- file_close(CovYamlFile) ;
-- end procedure ReadCovYaml ;
------------------------------------------------------------
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_cov.yml", FileName) ;
file CovYamlFile : text open READ_MODE is RESOLVED_FILE_NAME ;
variable buf : line ;
variable Found : boolean ;
begin
ReadFindToken (CovYamlFile, "Models:", buf, Found) ;
if not Found then
Alert(OSVVM_COV_ALERTLOG_ID,
"No Coverage Models found in " & RESOLVED_FILE_NAME, COV_READ_YAML_ALERT_LEVEL) ;
return ;
end if;
loop
ReadCovModelYaml(CovYamlFile, Found, Merge) ;
exit when not Found ;
end loop ;
file_close(CovYamlFile) ;
end procedure ReadCovYaml ;
------------------------------------------------------------
impure function GotCoverage return boolean is
------------------------------------------------------------
begin
for i in 1 to NumItems loop
if CovStructPtr(i).NumBins >= 1 then
return TRUE ;
end if;
end loop ;
return FALSE ;
end function GotCoverage ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer is
------------------------------------------------------------
variable ErrorCnt : integer := 0 ;
begin
if CovStructPtr(ID.ID).NumBins < 1 then
return 1 ; -- return error if model empty
else
for i in 1 to CovStructPtr(ID.ID).NumBins loop
if CovStructPtr(ID.ID).CovBinPtr(i).count < 0 then -- illegal CovBin
ErrorCnt := ErrorCnt + CovStructPtr(ID.ID).CovBinPtr(i).count ;
end if ;
end loop ;
return - ErrorCnt ;
end if ;
end function GetErrorCount ;
------------------------------------------------------------
-- pt local
-- Adjusted InsertBin
-- Ensures minimum of Count and AtLeast are 1
procedure AdjustedInsertBin (
ID : CoverageIDType ;
BinVal : RangeArrayType ;
Action : integer ;
Count : integer ;
AtLeast : integer ;
Weight : integer ;
Name : string
) is
variable vCalcAtLeast : integer ;
variable vCalcWeight : integer ;
begin
if Action = COV_COUNT then
vCalcAtLeast := maximum(0, AtLeast) ;
vCalcWeight := maximum(0, Weight) ;
else
vCalcAtLeast := 0 ;
vCalcWeight := 0 ;
end if ;
InsertBin(
ID => ID,
BinVal => BinVal,
Action => Action,
Count => Count,
AtLeast => vCalcAtLeast,
Weight => vCalcWeight,
Name => Name
) ;
end procedure AdjustedInsertBin ;
------------------------------------------------------------
-- These support usage of cross coverage constants
-- Also support the older AddCross(GenCross(...)) methodology
-- which has been replaced by AddCross(GenBin, GenBin, ...)
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 2) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
InsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 3) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 4) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 5) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 6) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 7) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 8) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") is
------------------------------------------------------------
begin
if BinValLengthNotEqual(ID, 9) then
Alert(CovStructPtr(ID.ID).AlertLogID, "CoveragePkg.AddCross: Cross coverage bins of different dimensions prohibited", FAILURE) ;
return ;
end if ;
GrowBins(ID, CovBin'length) ;
for i in CovBin'range loop
AdjustedInsertBin(ID,
CovBin(i).BinVal, CovBin(i).Action, CovBin(i).Count,
CovBin(i).AtLeast, CovBin(i).Weight, Name
) ;
end loop ;
end procedure AddCross ;
--!!!! How to handle this - do not support in main interface
--------------------------------------------------------------
--------------------------------------------------------------
-- Deprecated / Subsumed by versions with PercentCov Parameter
-- Maintained for backward compatibility only and
-- may be removed in the future.
-- ------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function CountCovHoles (ID : CoverageIDType; AtLeast : integer ) return integer is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < minimum(AtLeast, CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < AtLeast then
HoleCount := HoleCount + 1 ;
end if ;
end loop CovLoop ;
return HoleCount ;
end function CountCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function IsCovered (ID : CoverageIDType; AtLeast : integer ) return boolean is
------------------------------------------------------------
begin
return CountCovHoles(ID, AtLeast) = 0 ;
end function IsCovered ;
------------------------------------------------------------
impure function CalcWeight (ID : CoverageIDType; BinIndex : integer ; MaxAtLeast : integer ) return integer is
-- pt local
------------------------------------------------------------
begin
case CovStructPtr(ID.ID).WeightMode is
when AT_LEAST =>
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).AtLeast ;
when WEIGHT =>
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight ;
when REMAIN =>
return MaxAtLeast - CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_SCALED =>
-- Experimental may be removed
return integer( Ceil( CovStructPtr(ID.ID).WeightScale * real(MaxAtLeast))) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
when REMAIN_WEIGHT =>
-- Experimental may be removed
return CovStructPtr(ID.ID).CovBinPtr(BinIndex).Weight * (
integer( Ceil( CovStructPtr(ID.ID).WeightScale * real(MaxAtLeast))) -
CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ) ;
when others =>
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.CalcWeight:" &
" Selected Weight Mode not supported with deprecated RandCovPoint(AtLeast), see RandCovPoint(PercentCov)", FAILURE) ;
return MaxAtLeast - CovStructPtr(ID.ID).CovBinPtr(BinIndex).Count ;
end case ;
end function CalcWeight ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
-- If keep this, need to be able to scale AtLeast Value
impure function GetRandIndex (ID : CoverageIDType; AtLeast : integer ) return integer is
-- pt local
------------------------------------------------------------
variable WeightVec : integer_vector(0 to CovStructPtr(ID.ID).NumBins-1) ; -- Prep for change to DistInt
variable MinCount, AdjAtLeast, MaxAtLeast : integer ;
variable rInt : integer ;
begin
CovStructPtr(ID.ID).ItemCount := CovStructPtr(ID.ID).ItemCount + 1 ;
MinCount := GetMinCount(ID) ;
-- iAtLeast := integer(ceil(CovStructPtr(ID.ID).CovTarget * real(AtLeast)/100.0)) ;
if CovStructPtr(ID.ID).ThresholdingEnable then
AdjAtLeast := MinCount + integer(CovStructPtr(ID.ID).CovThreshold) + 1 ;
if MinCount < AtLeast then
-- Clip at AtLeast until reach AtLeast
AdjAtLeast := minimum(AdjAtLeast, AtLeast) ;
end if ;
else
if MinCount < AtLeast then
AdjAtLeast := AtLeast ; -- Valid
else
-- Done, Enable all bins
-- AdjAtLeast := integer'right ; -- Get All
AdjAtLeast := GetMaxCount(ID) + 1 ; -- Get All
end if ;
end if;
MaxAtLeast := AdjAtLeast ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- if not CovStructPtr(ID.ID).ThresholdingEnable then
-- -- When not thresholding, consider bin Bin.AtLeast
-- -- iBinAtLeast := integer(ceil(CovStructPtr(ID.ID).CovTarget * real(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)/100.0)) ;
-- MaxAtLeast := maximum(AdjAtLeast, CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) ;
-- end if ;
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < MaxAtLeast then
WeightVec(i-1) := CalcWeight(ID, i, MaxAtLeast ) ; -- CovStructPtr(ID.ID).CovBinPtr(i).Weight ;
else
WeightVec(i-1) := 0 ;
end if ;
end loop CovLoop ;
-- DistInt returns integer range 0 to CovStructPtr(ID.ID).NumBins-1
-- CovStructPtr(ID.ID).LastStimGenIndex := 1 + RV.DistInt( WeightVec ) ; -- return range 1 to CovStructPtr(ID.ID).NumBins
DistInt(CovStructPtr(ID.ID).RV, rInt, WeightVec) ;
CovStructPtr(ID.ID).LastStimGenIndex := 1 + rInt ; -- return range 1 to CovStructPtr(ID.ID).NumBins
CovStructPtr(ID.ID).LastIndex := CovStructPtr(ID.ID).LastStimGenIndex ;
return CovStructPtr(ID.ID).LastStimGenIndex ;
end function GetRandIndex ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovBinVal (ID : CoverageIDType; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return CovStructPtr(ID.ID).CovBinPtr( GetRandIndex(ID, AtLeast) ).BinVal.all ; -- GetBinVal
end function RandCovBinVal ;
-- Maintained for backward compatibility. Repeated until aliases work for methods
------------------------------------------------------------
-- Deprecated+ New versions use PercentCov. Name change.
impure function RandCovHole (ID : CoverageIDType; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(ID, AtLeast) ; -- GetBinVal
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovPoint (ID : CoverageIDType; AtLeast : integer ) return integer is
------------------------------------------------------------
variable BinVal : RangeArrayType(1 to 1) ;
variable rInt : integer ;
begin
BinVal := RandCovBinVal(ID, AtLeast) ;
-- return RV.RandInt(BinVal(1).min, BinVal(1).max) ;
Uniform(CovStructPtr(ID.ID).RV, rInt, BinVal(1).min, BinVal(1).max) ;
return rInt ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint (ID : CoverageIDType; AtLeast : integer ) return integer_vector is
------------------------------------------------------------
begin
return ToRandPoint(ID, RandCovBinVal(ID, AtLeast)) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
variable HoleCount : integer := 0 ;
variable buf : line ;
begin
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < minimum(AtLeast, CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < AtLeast then
HoleCount := HoleCount + 1 ;
if HoleCount = ReqHoleNum then
return CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all ;
end if ;
end if ;
end loop CovLoop ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.GetHoleBinVal:" &
" did not find hole. HoleCount = " & integer'image(HoleCount) &
"ReqHoleNum = " & integer'image(ReqHoleNum), ERROR
) ;
return CovStructPtr(ID.ID).CovBinPtr(CovStructPtr(ID.ID).NumBins).BinVal.all ;
end function GetHoleBinVal ;
------------------------------------------------------------
-- Deprecated+. New versions use PercentCov. Name Change.
impure function GetCovHole (ID : CoverageIDType; ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(ID, ReqHoleNum, AtLeast) ;
end function GetCovHole ;
------------------------------------------------------------
-- pt local
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; file f : text; AtLeast : integer; UsingLocalFile : boolean := FALSE ) is
------------------------------------------------------------
-- variable minAtLeast : integer ;
variable buf : line ;
begin
WriteBinName(ID, buf, "WriteCovHoles: ") ;
-- writeline(f, buf) ;
if CovStructPtr(ID.ID).NumBins < 1 then
if WriteBinFileInit or UsingLocalFile then
-- Duplicate Alert in specified file
swrite(buf, "%% Alert FAILURE " & GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model is empty. Nothing to print.") ;
writeline(f, buf) ;
end if ;
Alert(CovStructPtr(ID.ID).AlertLogID, GetNamePlus(ID, prefix => "in ", suffix => ", ") & "CoveragePkg.WriteCovHoles:" &
" coverage model is empty. Nothing to print.", FAILURE) ;
end if ;
CovLoop : for i in 1 to CovStructPtr(ID.ID).NumBins loop
-- minAtLeast := minimum(AtLeast,CovStructPtr(ID.ID).CovBinPtr(i).AtLeast) ;
-- if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < minAtLeast then
if CovStructPtr(ID.ID).CovBinPtr(i).action = COV_COUNT and CovStructPtr(ID.ID).CovBinPtr(i).Count < AtLeast then
swrite(buf, "%% Bin:") ;
write(buf, CovStructPtr(ID.ID).CovBinPtr(i).BinVal.all) ;
write(buf, " Count = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Count)) ;
write(buf, " AtLeast = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).AtLeast)) ;
if CovStructPtr(ID.ID).WeightMode = WEIGHT or CovStructPtr(ID.ID).WeightMode = REMAIN_WEIGHT then
-- Print Weight only when it is used
write(buf, " Weight = " & integer'image(CovStructPtr(ID.ID).CovBinPtr(i).Weight)) ;
end if ;
writeline(f, buf) ;
end if ;
end loop CovLoop ;
swrite(buf, "") ;
writeline(f, buf) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; AtLeast : integer ) is
------------------------------------------------------------
begin
if WriteBinFileInit then
-- Write to Local WriteBinFile - Deprecated, recommend use TranscriptFile instead
WriteCovHoles(ID, WriteBinFile, AtLeast) ;
elsif IsTranscriptEnabled then
-- Write to TranscriptFile
WriteCovHoles(ID, TranscriptFile, AtLeast) ;
if IsTranscriptMirrored then
-- Mirrored to OUTPUT
WriteCovHoles(ID, OUTPUT, AtLeast) ;
end if ;
else
-- Default Write to OUTPUT
WriteCovHoles(ID, OUTPUT, AtLeast) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; AtLeast : integer ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, AtLeast) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
file CovHoleFile : text open OpenKind is FileName ;
begin
WriteCovHoles(ID, CovHoleFile, AtLeast, TRUE) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType ; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
if IsLogEnabled(CovStructPtr(ID.ID).AlertLogID, LogLevel) then
WriteCovHoles(ID, FileName, AtLeast, OpenKind) ;
end if;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Compatibility Methods - Allows CoveragePkg to Work as a PT still
-- /////////////////////////////////////////
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
SetAlertLogID(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
------------------------------------------------------------
constant SeedInit : boolean := CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).RvSeedInit ;
begin
SetAlertLogID(COV_STRUCT_ID_DEFAULT, Name, ParentID, CreateHierarchy) ;
if not SeedInit then
InitSeed(COV_STRUCT_ID_DEFAULT, Name, FALSE) ;
end if ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return GetAlertLogID(COV_STRUCT_ID_DEFAULT) ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
constant SeedInit : boolean := CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).RvSeedInit ;
begin
SetName(COV_STRUCT_ID_DEFAULT, Name) ;
if not SeedInit then
InitSeed(COV_STRUCT_ID_DEFAULT, Name, FALSE) ;
end if ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
SetName(Name) ; -- call procedure above
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName return String is
------------------------------------------------------------
begin
return GetName(COV_STRUCT_ID_DEFAULT) ;
end function GetName ;
------------------------------------------------------------
impure function GetCovModelName return String is
------------------------------------------------------------
begin
return GetCovModelName(COV_STRUCT_ID_DEFAULT) ;
end function GetCovModelName ;
------------------------------------------------------------
impure function GetNamePlus(prefix, suffix : string) return String is
------------------------------------------------------------
begin
return GetNamePlus(COV_STRUCT_ID_DEFAULT, prefix, suffix) ;
end function GetNamePlus ;
------------------------------------------------------------
procedure SetMessage (Message : String) is
------------------------------------------------------------
constant SeedInit : boolean := CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).RvSeedInit ;
begin
SetMessage(COV_STRUCT_ID_DEFAULT, Message) ;
if not SeedInit then
InitSeed(COV_STRUCT_ID_DEFAULT, Message, FALSE) ;
end if ;
end procedure SetMessage ;
------------------------------------------------------------
procedure SetNextPointMode (A : NextPointModeType) is
------------------------------------------------------------
begin
SetNextPointMode(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetNextPointMode ;
------------------------------------------------------------
procedure SetIllegalMode (A : IllegalModeType) is
------------------------------------------------------------
begin
SetIllegalMode(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetIllegalMode ;
------------------------------------------------------------
procedure SetWeightMode (A : WeightModeType; Scale : real := 1.0) is
------------------------------------------------------------
begin
SetWeightMode(COV_STRUCT_ID_DEFAULT, A, Scale) ;
end procedure SetWeightMode ;
------------------------------------------------------------
procedure DeallocateMessage is
------------------------------------------------------------
begin
DeallocateMessage(COV_STRUCT_ID_DEFAULT) ;
end procedure DeallocateMessage ;
------------------------------------------------------------
procedure DeallocateName is
------------------------------------------------------------
begin
DeallocateName(COV_STRUCT_ID_DEFAULT) ;
end procedure DeallocateName ;
------------------------------------------------------------
procedure SetThresholding (A : boolean := TRUE ) is
------------------------------------------------------------
begin
SetThresholding(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetThresholding ;
------------------------------------------------------------
procedure SetCovThreshold (Percent : real) is
------------------------------------------------------------
begin
SetCovThreshold(COV_STRUCT_ID_DEFAULT, Percent) ;
end procedure SetCovThreshold ;
------------------------------------------------------------
procedure SetCovTarget (Percent : real) is
------------------------------------------------------------
begin
SetCovTarget(COV_STRUCT_ID_DEFAULT, Percent) ;
end procedure SetCovTarget ;
------------------------------------------------------------
impure function GetCovTarget return real is
------------------------------------------------------------
begin
return GetCovTarget(COV_STRUCT_ID_DEFAULT) ;
end function GetCovTarget ;
------------------------------------------------------------
procedure SetMerging (A : boolean := TRUE ) is
------------------------------------------------------------
begin
SetMerging(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetMerging ;
------------------------------------------------------------
procedure SetCountMode (A : CountModeType) is
------------------------------------------------------------
begin
SetCountMode(COV_STRUCT_ID_DEFAULT, A) ;
end procedure SetCountMode ;
------------------------------------------------------------
procedure InitSeed (S : string ) is
------------------------------------------------------------
begin
InitSeed(COV_STRUCT_ID_DEFAULT, S, FALSE) ;
end procedure InitSeed ;
------------------------------------------------------------
impure function InitSeed (S : string ) return string is
------------------------------------------------------------
begin
return InitSeed(COV_STRUCT_ID_DEFAULT, S, FALSE) ;
end function InitSeed ;
------------------------------------------------------------
procedure InitSeed (I : integer ) is
------------------------------------------------------------
begin
InitSeed(COV_STRUCT_ID_DEFAULT, I, FALSE) ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (RandomSeedIn : RandomSeedType ) is
------------------------------------------------------------
begin
SetSeed(COV_STRUCT_ID_DEFAULT, RandomSeedIn) ;
end procedure SetSeed ;
------------------------------------------------------------
impure function GetSeed return RandomSeedType is
------------------------------------------------------------
begin
return GetSeed(COV_STRUCT_ID_DEFAULT) ;
end function GetSeed ;
------------------------------------------------------------
procedure SetBinSize (NewNumBins : integer) is
-- Sets a CovBin to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy as a CovBin autosizes.
------------------------------------------------------------
begin
SetBinSize(COV_STRUCT_ID_DEFAULT, NewNumBins) ;
end procedure SetBinSize ;
------------------------------------------------------------
procedure AddBins (
------------------------------------------------------------
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
begin
AddBins(COV_STRUCT_ID_DEFAULT, Name, AtLeast, Weight, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( Name : String ; AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins(Name, AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (Name : String ; CovBin : CovBinType) is
------------------------------------------------------------
begin
AddBins(Name, 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins("", AtLeast, Weight, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( AtLeast : integer ; CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins("", AtLeast, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins ( CovBin : CovBinType ) is
------------------------------------------------------------
begin
AddBins("", 1, 1, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(COV_STRUCT_ID_DEFAULT, Name, AtLeast, Weight,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10,
Bin11, Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(Name, AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross(Name, 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross("", AtLeast, Weight,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross("", AtLeast, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
AddCross("", 1, 1,
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11,
Bin12, Bin13, Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
) ;
end procedure AddCross ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
begin
ResetReportOptions ;
Deallocate(COV_STRUCT_ID_DEFAULT) ;
end procedure deallocate ;
------------------------------------------------------------
procedure ICoverLast is
------------------------------------------------------------
begin
ICoverLast(COV_STRUCT_ID_DEFAULT) ;
end procedure ICoverLast ;
------------------------------------------------------------
procedure ICover ( CovPoint : integer) is
------------------------------------------------------------
begin
ICover(COV_STRUCT_ID_DEFAULT, (1=> CovPoint)) ;
end procedure ICover ;
------------------------------------------------------------
procedure ICover( CovPoint : integer_vector) is
------------------------------------------------------------
begin
ICover(COV_STRUCT_ID_DEFAULT, CovPoint) ;
end procedure ICover ;
------------------------------------------------------------
procedure TCover ( A : integer) is
------------------------------------------------------------
begin
TCover(COV_STRUCT_ID_DEFAULT, A) ;
end procedure TCover ;
------------------------------------------------------------
procedure ClearCov is
------------------------------------------------------------
begin
ClearCov(COV_STRUCT_ID_DEFAULT) ;
end procedure ClearCov ;
------------------------------------------------------------
-- deprecated
procedure SetCovZero is
------------------------------------------------------------
begin
ClearCov(COV_STRUCT_ID_DEFAULT) ;
end procedure SetCovZero ;
------------------------------------------------------------
impure function IsInitialized return boolean is
------------------------------------------------------------
begin
return IsInitialized(COV_STRUCT_ID_DEFAULT) ;
end function IsInitialized ;
------------------------------------------------------------
impure function GetMinCov return real is
------------------------------------------------------------
begin
return GetMinCov(COV_STRUCT_ID_DEFAULT) ;
end function GetMinCov ;
------------------------------------------------------------
impure function GetMinCount return integer is
------------------------------------------------------------
begin
return GetMinCount (COV_STRUCT_ID_DEFAULT);
end function GetMinCount ;
------------------------------------------------------------
impure function GetMaxCov return real is
------------------------------------------------------------
begin
return GetMaxCov(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxCov ;
------------------------------------------------------------
impure function GetMaxCount return integer is
------------------------------------------------------------
begin
return GetMaxCount(COV_STRUCT_ID_DEFAULT);
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return CountCovHoles(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function CountCovHoles return integer is
------------------------------------------------------------
begin
return CountCovHoles(COV_STRUCT_ID_DEFAULT) ;
end function CountCovHoles ;
------------------------------------------------------------
impure function IsCovered ( PercentCov : real ) return boolean is
------------------------------------------------------------
begin
return IsCovered(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function IsCovered ;
------------------------------------------------------------
impure function IsCovered return boolean is
------------------------------------------------------------
begin
return IsCovered(COV_STRUCT_ID_DEFAULT) ;
end function IsCovered ;
------------------------------------------------------------
impure function GetCov ( PercentCov : real ) return real is
------------------------------------------------------------
begin
return GetCov(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetCov ;
------------------------------------------------------------
impure function GetCov return real is
------------------------------------------------------------
begin
return GetCov(COV_STRUCT_ID_DEFAULT ) ;
end function GetCov ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return GetItemCount(COV_STRUCT_ID_DEFAULT) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetTotalCovCount ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetTotalCovCount(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovCount return integer is
------------------------------------------------------------
begin
return GetTotalCovCount(COV_STRUCT_ID_DEFAULT) ;
end function GetTotalCovCount ;
------------------------------------------------------------
impure function GetTotalCovGoal ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetTotalCovGoal(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetTotalCovGoal return integer is
------------------------------------------------------------
begin
return GetTotalCovGoal(COV_STRUCT_ID_DEFAULT) ;
end function GetTotalCovGoal ;
-- Return Index Values
------------------------------------------------------------
impure function GetNumBins return integer is
------------------------------------------------------------
begin
return GetNumBins(COV_STRUCT_ID_DEFAULT) ;
end function GetNumBins ;
------------------------------------------------------------
impure function GetLastIndex return integer is
------------------------------------------------------------
begin
return GetLastIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetLastIndex ;
------------------------------------------------------------
impure function GetRandIndex ( CovTargetPercent : real ) return integer is
------------------------------------------------------------
begin
return GetRandIndex(COV_STRUCT_ID_DEFAULT, CovTargetPercent) ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetRandIndex return integer is
------------------------------------------------------------
begin
return GetRandIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetRandIndex ;
------------------------------------------------------------
impure function GetIncIndex return integer is
------------------------------------------------------------
begin
return GetIncIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetIncIndex ;
------------------------------------------------------------
impure function GetMinIndex return integer is
------------------------------------------------------------
begin
return GetMinIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetMinIndex ;
------------------------------------------------------------
impure function GetMaxIndex return integer is
------------------------------------------------------------
begin
return GetMaxIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxIndex ;
------------------------------------------------------------
impure function GetNextIndex (Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
return GetNextIndex(COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextIndex;
------------------------------------------------------------
impure function GetNextIndex return integer is
------------------------------------------------------------
begin
return GetNextIndex(COV_STRUCT_ID_DEFAULT) ;
end function GetNextIndex ;
-- Return BinVals
------------------------------------------------------------
impure function GetBinVal ( BinIndex : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetBinVal(COV_STRUCT_ID_DEFAULT, BinIndex ) ;
end function GetBinVal ;
------------------------------------------------------------
impure function GetLastBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetLastBinVal(COV_STRUCT_ID_DEFAULT) ;
end function GetLastBinVal ;
------------------------------------------------------------
impure function GetRandBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetRandBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetRandBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetRandBinVal(COV_STRUCT_ID_DEFAULT) ; -- GetBinVal
end function GetRandBinVal ;
------------------------------------------------------------
impure function GetIncBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetIncBinVal( COV_STRUCT_ID_DEFAULT ) ;
end function GetIncBinVal ;
------------------------------------------------------------
impure function GetMinBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetMinBinVal( COV_STRUCT_ID_DEFAULT ) ;
end function GetMinBinVal ;
------------------------------------------------------------
impure function GetMaxBinVal return RangeArrayType is
------------------------------------------------------------
begin
-- use global coverage target
return GetMaxBinVal( COV_STRUCT_ID_DEFAULT ) ;
end function GetMaxBinVal ;
------------------------------------------------------------
impure function GetNextBinVal (Mode : NextPointModeType) return RangeArrayType is
------------------------------------------------------------
begin
return GetNextBinVal (COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextBinVal;
------------------------------------------------------------
impure function GetNextBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetNextBinVal (COV_STRUCT_ID_DEFAULT) ;
end function GetNextBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetRandBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
-- deprecated, see GetRandBinVal
impure function RandCovBinVal return RangeArrayType is
------------------------------------------------------------
begin
return GetRandBinVal(COV_STRUCT_ID_DEFAULT) ; -- GetBinVal
end function RandCovBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum, PercentCov) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, 1, PercentCov) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetHoleBinVal ( ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum) ;
end function GetHoleBinVal ;
------------------------------------------------------------
impure function GetPoint ( BinIndex : integer ) return integer is
------------------------------------------------------------
begin
return GetPoint(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetPoint ( BinIndex : integer ) return integer_vector is
------------------------------------------------------------
begin
return GetPoint(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetPoint ;
------------------------------------------------------------
impure function GetRandPoint return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetRandPoint ( PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetRandPoint ;
------------------------------------------------------------
impure function GetIncPoint return integer is
------------------------------------------------------------
begin
return GetIncPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetIncPoint return integer_vector is
------------------------------------------------------------
begin
return GetIncPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetIncPoint ;
------------------------------------------------------------
impure function GetMinPoint return integer is
------------------------------------------------------------
begin
return GetMinPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMinPoint return integer_vector is
------------------------------------------------------------
begin
return GetMinPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMinPoint ;
------------------------------------------------------------
impure function GetMaxPoint return integer is
------------------------------------------------------------
begin
return GetMaxPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetMaxPoint return integer_vector is
------------------------------------------------------------
begin
return GetMaxPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxPoint ;
------------------------------------------------------------
impure function GetNextPoint (Mode : NextPointModeType) return integer is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint (Mode : NextPointModeType) return integer_vector is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT, Mode) ;
end function GetNextPoint;
------------------------------------------------------------
impure function GetNextPoint return integer is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetNextPoint ;
------------------------------------------------------------
impure function GetNextPoint return integer_vector is
------------------------------------------------------------
begin
return GetNextPoint(COV_STRUCT_ID_DEFAULT) ;
end function GetNextPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint ( PercentCov : real ) return integer is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT) ;
end function RandCovPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint ( PercentCov : real ) return integer_vector is
------------------------------------------------------------
begin
return GetRandPoint(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function RandCovPoint ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo ( BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
begin
return GetBinInfo(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength return integer is
-- ------------------------------------------------------------
begin
return GetBinValLength(COV_STRUCT_ID_DEFAULT) ;
end function GetBinValLength ;
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovBinBaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix2BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix3BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix4BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix5BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix6BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix7BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix8BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBin ( BinIndex : integer ) return CovMatrix9BaseType is
-- ------------------------------------------------------------
begin
return GetBin(COV_STRUCT_ID_DEFAULT, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBinName ( BinIndex : integer; DefaultName : string := "" ) return string is
-- ------------------------------------------------------------
begin
return GetBinName(COV_STRUCT_ID_DEFAULT, BinIndex, DefaultName) ;
end function GetBinName;
------------------------------------------------------------
procedure WriteBin (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFail, WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfo, WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCount, WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal(WriteAnyIllegal, WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailName, FailNameVar.GetOpt ) ;
variable buf, buf2 : line ;
begin
WriteBin (
ID => COV_STRUCT_ID_DEFAULT,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailName, FailNameVar.GetOpt )
) ;
WriteToCovFile(buf) ;
end procedure WriteBin ;
------------------------------------------------------------
-- Deprecated
procedure WriteBin ( -- With LogLevel
------------------------------------------------------------
LogLevel : LogType ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if IsLogEnabled(CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).AlertLogID, LogLevel) then
WriteBin (
WritePassFail => WritePassFail,
WriteBinInfo => WriteBinInfo,
WriteCount => WriteCount,
WriteAnyIllegal => WriteAnyIllegal,
WritePrefix => WritePrefix,
PassName => PassName,
FailName => FailName
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
procedure WriteBin (
------------------------------------------------------------
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
file LocalWriteBinFile : text open OpenKind is FileName ;
constant rWritePassFail : OsvvmOptionsType := ResolveCovWritePassFail (WritePassFail, WritePassFailVar) ;
constant rWriteBinInfo : OsvvmOptionsType := ResolveCovWriteBinInfo (WriteBinInfo, WriteBinInfoVar ) ;
constant rWriteCount : OsvvmOptionsType := ResolveCovWriteCount (WriteCount, WriteCountVar ) ;
constant rWriteAnyIllegal : OsvvmOptionsType := ResolveCovWriteAnyIllegal (WriteAnyIllegal, WriteAnyIllegalVar) ;
-- constant rWritePrefix : string := ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt) ;
-- constant rPassName : string := ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ) ;
-- constant rFailName : string := ResolveOsvvmFailName (FailName, FailNameVar.GetOpt ) ;
variable buf : line ;
begin
WriteBin (
ID => COV_STRUCT_ID_DEFAULT,
buf => buf,
WritePassFail => rWritePassFail,
WriteBinInfo => rWriteBinInfo,
WriteCount => rWriteCount,
WriteAnyIllegal => rWriteAnyIllegal,
-- WritePrefix => rWritePrefix,
WritePrefix => ResolveOsvvmWritePrefix (WritePrefix, WritePrefixVar.GetOpt),
-- PassName => rPassName,
PassName => ResolveOsvvmPassName (PassName, PassNameVar.GetOpt ),
-- FailName => rFailName
FailName => ResolveOsvvmFailName (FailName, FailNameVar.GetOpt ),
UsingLocalFile => TRUE
);
writeline(LocalWriteBinFile, buf) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure WriteBin ( -- With LogLevel
------------------------------------------------------------
LogLevel : LogType ;
FileName : string;
OpenKind : File_Open_Kind := APPEND_MODE ;
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if IsLogEnabled(CovStructPtr(COV_STRUCT_ID_DEFAULT.ID).AlertLogID, LogLevel) then
WriteBin (
FileName => FileName,
OpenKind => OpenKind,
WritePassFail => WritePassFail,
WriteBinInfo => WriteBinInfo,
WriteCount => WriteCount,
WriteAnyIllegal => WriteAnyIllegal,
WritePrefix => WritePrefix,
PassName => PassName,
FailName => FailName
) ;
end if ;
end procedure WriteBin ; -- With LogLevel
------------------------------------------------------------
procedure DumpBin (LogLevel : LogType := DEBUG) is
------------------------------------------------------------
begin
DumpBin (COV_STRUCT_ID_DEFAULT, LogLevel) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure WriteCovHoles ( PercentCov : real ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType := ALWAYS ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType ; PercentCov : real ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, PercentCov) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, FileName, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, FileName, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
procedure ReadCovDb (FileName : string; Merge : boolean := FALSE) is
------------------------------------------------------------
begin
ReadCovDb(COV_STRUCT_ID_DEFAULT, FileName, Merge) ;
end procedure ReadCovDb ;
------------------------------------------------------------
procedure WriteCovDb (FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
------------------------------------------------------------
begin
WriteCovDb (COV_STRUCT_ID_DEFAULT, FileName, OpenKind) ;
end procedure WriteCovDb ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
begin
return GetErrorCount(COV_STRUCT_ID_DEFAULT) ;
end function GetErrorCount ;
------------------------------------------------------------
-- These support usage of cross coverage constants
-- Also support the older AddCross(GenCross(...)) methodology
-- which has been replaced by AddCross
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix2Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix3Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix4Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix5Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix6Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix7Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix8Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross (CovBin : CovMatrix9Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddCross ;
-- ------------------------------------------------------------
-- ------------------------------------------------------------
-- Deprecated / Subsumed by versions with PercentCov Parameter
-- Maintained for backward compatibility only and
-- may be removed in the future.
-- ------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function CountCovHoles ( AtLeast : integer ) return integer is
------------------------------------------------------------
begin
return CountCovHoles (COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function CountCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function IsCovered ( AtLeast : integer ) return boolean is
------------------------------------------------------------
begin
return IsCovered(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function IsCovered ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovBinVal (AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovBinVal ;
-- Maintained for backward compatibility. Repeated until aliases work for methods
------------------------------------------------------------
-- Deprecated+ New versions use PercentCov. Name change.
impure function RandCovHole (AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovHole(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function RandCovPoint (AtLeast : integer ) return integer is
------------------------------------------------------------
begin
return RandCovPoint(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovPoint ;
------------------------------------------------------------
impure function RandCovPoint (AtLeast : integer ) return integer_vector is
------------------------------------------------------------
begin
return RandCovPoint(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov
impure function GetHoleBinVal ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal (COV_STRUCT_ID_DEFAULT, ReqHoleNum, AtLeast) ;
end function GetHoleBinVal ;
------------------------------------------------------------
-- Deprecated+. New versions use PercentCov. Name Change.
impure function GetCovHole ( ReqHoleNum : integer ; AtLeast : integer ) return RangeArrayType is
------------------------------------------------------------
begin
return GetCovHole(COV_STRUCT_ID_DEFAULT, ReqHoleNum, AtLeast) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( AtLeast : integer ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, AtLeast) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( LogLevel : LogType ; AtLeast : integer ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, AtLeast) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, FileName, AtLeast, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- Deprecated. New versions use PercentCov.
procedure WriteCovHoles ( LogLevel : LogType ; FileName : string; AtLeast : integer ; OpenKind : File_Open_Kind := APPEND_MODE ) is
------------------------------------------------------------
begin
WriteCovHoles(COV_STRUCT_ID_DEFAULT, LogLevel, FileName, AtLeast, OpenKind) ;
end procedure WriteCovHoles ;
--------------------------------------------------------------
--------------------------------------------------------------
-- Deprecated. Due to name changes to promote greater consistency
-- Maintained for backward compatibility - but only for PT version
-- Not available in Data Structure
-- ------------------------------------------------------------
------------------------------------------------------------
impure function CovBinErrCnt return integer is
-- Deprecated. Name changed to ErrorCount for package to package consistency
------------------------------------------------------------
begin
return GetErrorCount(COV_STRUCT_ID_DEFAULT) ;
end function CovBinErrCnt ;
------------------------------------------------------------
-- Deprecated. Same as RandCovBinVal
impure function RandCovHole ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function RandCovHole ;
------------------------------------------------------------
-- Deprecated. Same as RandCovBinVal
impure function RandCovHole return RangeArrayType is
------------------------------------------------------------
begin
return RandCovBinVal(COV_STRUCT_ID_DEFAULT) ;
end function RandCovHole ;
-- GetCovHole replaced by GetHoleBinVal
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum, PercentCov) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( PercentCov : real ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, PercentCov) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Same as GetHoleBinVal
impure function GetCovHole ( ReqHoleNum : integer := 1 ) return RangeArrayType is
------------------------------------------------------------
begin
return GetHoleBinVal(COV_STRUCT_ID_DEFAULT, ReqHoleNum) ;
end function GetCovHole ;
------------------------------------------------------------
-- Deprecated. Replaced by SetMessage with multi-line support
procedure SetItemName (ItemNameIn : String) is
------------------------------------------------------------
begin
SetMessage(COV_STRUCT_ID_DEFAULT, ItemNameIn) ;
end procedure SetItemName ;
------------------------------------------------------------
-- Deprecated. Same as GetMinCount
impure function GetMinCov return integer is
------------------------------------------------------------
begin
return GetMinCount(COV_STRUCT_ID_DEFAULT) ;
end function GetMinCov ;
------------------------------------------------------------
-- Deprecated. Same as GetMaxCount
impure function GetMaxCov return integer is
------------------------------------------------------------
begin
return GetMaxCount(COV_STRUCT_ID_DEFAULT) ;
end function GetMaxCov ;
------------------------------------------------------------
-- Deprecated. Use AddCross Instead.
procedure AddBins (CovBin : CovMatrix2Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix3Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix4Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix5Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix6Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix7Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix8Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
------------------------------------------------------------
procedure AddBins (CovBin : CovMatrix9Type ; Name : String := "") is
------------------------------------------------------------
begin
AddCross(COV_STRUCT_ID_DEFAULT, CovBin, Name) ;
end procedure AddBins ;
end protected body CovPType ;
------------------------------------------------------------------------------------------
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
-- XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX CovPType XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
------------------------------------------------------------------------------------------
------------------------------------------------------------
-- /////////////////////////////////////////
-- Singleton Data Structure
-- /////////////////////////////////////////
------------------------------------------------------------
shared variable CoverageStore : CovPType ;
------------------------------------------------------------
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_COVERAGE_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return CoverageIDType is
begin
return CoverageStore.NewID (Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Global Settings Common to All Coverage Models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure FileOpenWriteBin (FileName : string; OpenKind : File_Open_Kind ) is
begin
CoverageStore.FileOpenWriteBin (FileName, OpenKind) ;
end procedure FileOpenWriteBin ;
procedure FileCloseWriteBin is
begin
CoverageStore.FileCloseWriteBin ;
end procedure FileCloseWriteBin ;
-- procedure WriteToCovFile (variable buf : inout line) is
-- begin
-- CoverageStore.WriteToCovFile (buf) ;
-- end procedure WriteToCovFile ;
procedure PrintToCovFile(S : string) is
begin
CoverageStore.PrintToCovFile (S) ;
end procedure PrintToCovFile ;
------------------------------------------------------------
procedure SetReportOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := COV_OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
CoverageStore.SetReportOptions (
WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal,
WritePrefix, PassName, FailName
) ;
end procedure SetReportOptions ;
procedure ResetReportOptions is
begin
CoverageStore.ResetReportOptions ;
end procedure ResetReportOptions ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Model Settings
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetName (ID : CoverageIDType; Name : String) is
begin
CoverageStore.SetName (ID, Name) ;
end procedure SetName ;
impure function SetName (ID : CoverageIDType; Name : String) return string is
begin
return CoverageStore.SetName (ID, Name) ;
end function SetName ;
procedure DeallocateName (ID : CoverageIDType) is
begin
CoverageStore.DeallocateName (ID) ;
end procedure DeallocateName ;
impure function GetName (ID : CoverageIDType) return String is
begin
return CoverageStore.GetName(ID => ID) ;
end function GetName ;
impure function GetCovModelName (ID : CoverageIDType) return String is
begin
return CoverageStore.GetCovModelName(ID => ID) ;
end function GetCovModelName ;
impure function GetNamePlus (ID : CoverageIDType; prefix, suffix : string) return String is
begin
return CoverageStore.GetNamePlus (ID, prefix, suffix) ;
end function GetNamePlus ;
procedure SetItemBinNames (
ID : CoverageIDType ;
Name1 : String ;
Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20 : string := ""
) is
begin
CoverageStore.SetItemBinNames (
ID,
Name1, Name2, Name3, Name4, Name5,
Name6, Name7, Name8, Name9, Name10,
Name11, Name12, Name13, Name14, Name15,
Name16, Name17, Name18, Name19, Name20
) ;
end procedure SetItemBinNames ;
------------------------------------------------------------
procedure SetMessage (ID : CoverageIDType; Message : String) is
begin
CoverageStore.SetMessage(ID, Message) ;
end procedure SetMessage ;
procedure DeallocateMessage (ID : CoverageIDType) is
begin
CoverageStore.DeallocateMessage(ID) ;
end procedure DeallocateMessage ;
procedure SetCovTarget (ID : CoverageIDType; Percent : real) is
begin
CoverageStore.SetCovTarget(ID, Percent) ;
end procedure SetCovTarget ;
impure function GetCovTarget (ID : CoverageIDType) return real is
begin
return CoverageStore.GetCovTarget(ID) ;
end function GetCovTarget ;
procedure SetThresholding (ID : CoverageIDType; A : boolean := TRUE ) is
begin
CoverageStore.SetThresholding(ID, A) ;
end procedure SetThresholding ;
procedure SetCovThreshold (ID : CoverageIDType; Percent : real) is
begin
CoverageStore.SetCovThreshold(ID, Percent) ;
end procedure SetCovThreshold ;
procedure SetMerging (ID : CoverageIDType; A : boolean := TRUE ) is
begin
CoverageStore.SetMerging(ID, A) ;
end procedure SetMerging ;
procedure SetCountMode (ID : CoverageIDType; A : CountModeType) is
begin
CoverageStore.SetCountMode(ID, A) ;
end procedure SetCountMode ;
procedure SetIllegalMode (ID : CoverageIDType; A : IllegalModeType) is
begin
CoverageStore.SetIllegalMode(ID, A) ;
end procedure SetIllegalMode ;
procedure SetWeightMode (ID : CoverageIDType; WeightMode : WeightModeType; WeightScale : real := 1.0) is
begin
CoverageStore.SetWeightMode(ID, WeightMode, WeightScale) ;
end procedure SetWeightMode ;
procedure SetCovWeight (ID : CoverageIDType; Weight : integer) is
begin
CoverageStore.SetCovWeight(ID, Weight) ;
end procedure SetCovWeight ;
impure function GetCovWeight (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetCovWeight(ID) ;
end function GetCovWeight ;
procedure SetNextPointMode (ID : CoverageIDType; A : NextPointModeType) is
begin
CoverageStore.SetNextPointMode(ID, A) ;
end procedure SetNextPointMode ;
------------------------------------------------------------
procedure SetAlertLogID (ID : CoverageIDType; A : AlertLogIDType) is
begin
CoverageStore.SetAlertLogID (ID, A) ;
end procedure SetAlertLogID ;
procedure SetAlertLogID (ID : CoverageIDType; Name : string ; ParentID : AlertLogIDType := ALERTLOG_BASE_ID ; CreateHierarchy : Boolean := TRUE) is
begin
CoverageStore.SetAlertLogID (ID, Name, ParentID, CreateHierarchy) ;
end procedure SetAlertLogID ;
impure function GetAlertLogID (ID : CoverageIDType) return AlertLogIDType is
begin
return CoverageStore.GetAlertLogID(ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
procedure InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE) is
begin
CoverageStore.InitSeed(ID, S, UseNewSeedMethods) ;
end procedure InitSeed ;
impure function InitSeed (ID : CoverageIDType; S : string; UseNewSeedMethods : boolean := TRUE ) return string is
begin
return CoverageStore.InitSeed(ID, S, UseNewSeedMethods) ;
end function InitSeed ;
procedure InitSeed (ID : CoverageIDType; I : integer; UseNewSeedMethods : boolean := TRUE ) is
begin
CoverageStore.InitSeed(ID, I, UseNewSeedMethods) ;
end procedure InitSeed ;
------------------------------------------------------------
procedure SetSeed (ID : CoverageIDType; RandomSeedIn : RandomSeedType ) is
begin
CoverageStore.SetSeed (ID, RandomSeedIn) ;
end procedure SetSeed ;
impure function GetSeed (ID : CoverageIDType) return RandomSeedType is
begin
return CoverageStore.GetSeed (ID => ID) ;
end function GetSeed ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Item / Cross Bin Creation and Destruction
-- /////////////////////////////////////////
------------------------------------------------------------
procedure SetBinSize (ID : CoverageIDType; NewNumBins : integer) is
begin
CoverageStore.SetBinSize (ID, NewNumBins) ;
end procedure SetBinSize ;
procedure DeallocateBins (CoverID : CoverageIDType) is
begin
CoverageStore.DeallocateBins (CoverID) ;
end procedure DeallocateBins ;
procedure Deallocate (ID : CoverageIDType) is
begin
CoverageStore.Deallocate (ID) ;
end procedure Deallocate ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddBins (
------------------------------------------------------------
ID : CoverageIDType ;
Name : String ;
AtLeast : integer ;
Weight : integer ;
CovBin : CovBinType
) is
begin
CoverageStore.AddBins (ID, Name, AtLeast, Weight, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; Name : String ; AtLeast : integer ; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, Name, AtLeast, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; Name : String ; CovBin : CovBinType) is
begin
CoverageStore.AddBins (ID, Name, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; Weight : integer ; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, AtLeast, Weight, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; AtLeast : integer ; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, AtLeast, CovBin) ;
end procedure AddBins ;
procedure AddBins (ID : CoverageIDType; CovBin : CovBinType ) is
begin
CoverageStore.AddBins (ID, CovBin) ;
end procedure AddBins ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross (
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Name, AtLeast, Weight, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Name, AtLeast, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Name : string ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Name, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
-- Weight Deprecated
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, AtLeast, Weight, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
AtLeast : integer ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, AtLeast, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
procedure AddCross(
------------------------------------------------------------
ID : CoverageIDType ;
Bin1, Bin2 : CovBinType ;
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20 : CovBinType := NULL_BIN
) is
begin
CoverageStore.AddCross(ID, Bin1, Bin2,
Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9, Bin10, Bin11, Bin12, Bin13,
Bin14, Bin15, Bin16, Bin17, Bin18, Bin19, Bin20
);
end procedure AddCross ;
------------------------------------------------------------
-- AddCross for usage with constants created by GenCross
------------------------------------------------------------
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix2Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix3Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix4Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix5Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix6Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix7Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix8Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
procedure AddCross (ID : CoverageIDType; CovBin : CovMatrix9Type ; Name : String := "") is
begin
CoverageStore.AddCross (ID, CovBin, Name) ;
end procedure AddCross ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Recording and Clearing Coverage
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
procedure ICoverLast (ID : CoverageIDType) is
begin
CoverageStore.ICoverLast (ID) ;
end procedure ICoverLast ;
procedure ICover (ID : CoverageIDType; CovPoint : integer_vector) is
begin
CoverageStore.ICover (ID, CovPoint) ;
end procedure ICover ;
procedure ICover (ID : CoverageIDType; CovPoint : integer) is
begin
CoverageStore.ICover (ID, CovPoint) ;
end procedure ICover ;
procedure TCover (CoverID : CoverageIDType; A : integer) is
begin
CoverageStore.TCover (CoverID, A) ;
end procedure TCover ;
procedure ClearCov (ID : CoverageIDType) is
begin
CoverageStore.ClearCov (ID) ;
end procedure ClearCov ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Coverage Information and Statistics
-- /////////////////////////////////////////
------------------------------------------------------------
------------------------------------------------------------
impure function IsCovered (ID : CoverageIDType; PercentCov : real ) return boolean is
begin
return CoverageStore.IsCovered (ID, PercentCov) ;
end function IsCovered ;
impure function IsCovered (ID : CoverageIDType) return boolean is
begin
return CoverageStore.IsCovered (ID) ;
end function IsCovered ;
impure function IsInitialized (ID : CoverageIDType) return boolean is
begin
return CoverageStore.IsInitialized (ID) ;
end function IsInitialized ;
------------------------------------------------------------
impure function GetItemCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetItemCount (ID) ;
end function GetItemCount ;
impure function GetCov (ID : CoverageIDType; PercentCov : real ) return real is
begin
return CoverageStore.GetCov (ID, PercentCov) ;
end function GetCov ;
impure function GetCov (ID : CoverageIDType) return real is
begin
return CoverageStore.GetCov (ID) ;
end function GetCov ;
impure function GetTotalCovCount (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.GetTotalCovCount (ID, PercentCov) ;
end function GetTotalCovCount ;
impure function GetTotalCovCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetTotalCovCount (ID) ;
end function GetTotalCovCount ;
impure function GetTotalCovGoal (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.GetTotalCovGoal (ID, PercentCov) ;
end function GetTotalCovGoal ;
impure function GetTotalCovGoal (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetTotalCovGoal (ID) ;
end function GetTotalCovGoal ;
------------------------------------------------------------
impure function GetMinCov (ID : CoverageIDType) return real is
begin
return CoverageStore.GetMinCov (ID) ;
end function GetMinCov ;
impure function GetMinCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMinCount (ID) ;
end function GetMinCount ;
impure function GetMaxCov (ID : CoverageIDType) return real is
begin
return CoverageStore.GetMaxCov (ID) ;
end function GetMaxCov ;
impure function GetMaxCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMaxCount (ID) ;
end function GetMaxCount ;
------------------------------------------------------------
impure function CountCovHoles (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.CountCovHoles (ID, PercentCov) ;
end function CountCovHoles ;
impure function CountCovHoles (ID : CoverageIDType) return integer is
begin
return CoverageStore.CountCovHoles (ID) ;
end function CountCovHoles ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Generating Coverage Points, BinValues, and Indices
-- /////////////////////////////////////////
------------------------------------------------------------
-- Return Points
------------------------------------------------------------
-- to be replaced in VHDL-2019 by version that uses RandomSeed as an inout
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer is
begin
return CoverageStore.ToRandPoint (ID, BinVal) ;
end function ToRandPoint ;
impure function ToRandPoint (ID : CoverageIDType; BinVal : RangeArrayType ) return integer_vector is
begin
return CoverageStore.ToRandPoint (ID, BinVal) ;
end function ToRandPoint ;
------------------------------------------------------------
-- Return Points
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer is
begin
return CoverageStore.GetPoint (ID, BinIndex) ;
end function GetPoint ;
impure function GetPoint (ID : CoverageIDType; BinIndex : integer ) return integer_vector is
begin
return CoverageStore.GetPoint (ID, BinIndex) ;
end function GetPoint ;
impure function GetRandPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetRandPoint (ID) ;
end function GetRandPoint ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.GetRandPoint (ID, PercentCov) ;
end function GetRandPoint ;
impure function GetRandPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetRandPoint (ID) ;
end function GetRandPoint ;
impure function GetRandPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
begin
return CoverageStore.GetRandPoint (ID, PercentCov) ;
end function GetRandPoint ;
impure function GetIncPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetIncPoint (ID => ID) ;
end function GetIncPoint ;
impure function GetIncPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetIncPoint (ID => ID) ;
end function GetIncPoint ;
impure function GetMinPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMinPoint (ID => ID) ;
end function GetMinPoint ;
impure function GetMinPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetMinPoint (ID => ID) ;
end function GetMinPoint ;
impure function GetMaxPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMaxPoint (ID => ID) ;
end function GetMaxPoint ;
impure function GetMaxPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetMaxPoint (ID => ID) ;
end function GetMaxPoint ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer is
begin
return CoverageStore.GetNextPoint (ID, Mode) ;
end function GetNextPoint ;
impure function GetNextPoint (ID : CoverageIDType; Mode : NextPointModeType) return integer_vector is
begin
return CoverageStore.GetNextPoint (ID, Mode) ;
end function GetNextPoint ;
impure function GetNextPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetNextPoint (ID) ;
end function GetNextPoint ;
impure function GetNextPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.GetNextPoint (ID) ;
end function GetNextPoint ;
------------------------------------------------------------
-- deprecated, see GetRandPoint
impure function RandCovPoint (ID : CoverageIDType) return integer is
begin
return CoverageStore.RandCovPoint (ID) ;
end function RandCovPoint ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer is
begin
return CoverageStore.RandCovPoint (ID, PercentCov) ;
end function RandCovPoint ;
impure function RandCovPoint (ID : CoverageIDType) return integer_vector is
begin
return CoverageStore.RandCovPoint (ID) ;
end function RandCovPoint ;
impure function RandCovPoint (ID : CoverageIDType; PercentCov : real ) return integer_vector is
begin
return CoverageStore.RandCovPoint (ID, PercentCov) ;
end function RandCovPoint ;
------------------------------------------------------------
-- Return BinVals
impure function GetBinVal (ID : CoverageIDType; BinIndex : integer ) return RangeArrayType is
begin
return CoverageStore.GetBinVal (ID, BinIndex) ;
end function GetBinVal ;
impure function GetRandBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.GetRandBinVal (ID, PercentCov) ;
end function GetRandBinVal ;
impure function GetRandBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetRandBinVal (ID => ID) ;
end function GetRandBinVal ;
impure function GetLastBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetLastBinVal (ID => ID) ;
end function GetLastBinVal ;
impure function GetIncBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetIncBinVal (ID => ID) ;
end function GetIncBinVal ;
impure function GetMinBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetMinBinVal (ID => ID) ;
end function GetMinBinVal ;
impure function GetMaxBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetMaxBinVal (ID => ID) ;
end function GetMaxBinVal ;
impure function GetNextBinVal (ID : CoverageIDType; Mode : NextPointModeType) return RangeArrayType is
begin
return CoverageStore.GetNextBinVal (ID, Mode) ;
end function GetNextBinVal ;
impure function GetNextBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.GetNextBinVal (ID => ID) ;
end function GetNextBinVal ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer ; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.GetHoleBinVal (ID, ReqHoleNum, PercentCov) ;
end function GetHoleBinVal ;
impure function GetHoleBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.GetHoleBinVal (ID, PercentCov) ;
end function GetHoleBinVal ;
impure function GetHoleBinVal (ID : CoverageIDType; ReqHoleNum : integer := 1 ) return RangeArrayType is
begin
return CoverageStore.GetHoleBinVal (ID, ReqHoleNum) ;
end function GetHoleBinVal ;
-- deprecated RandCovBinVal, see GetRandBinVal
impure function RandCovBinVal (ID : CoverageIDType; PercentCov : real ) return RangeArrayType is
begin
return CoverageStore.RandCovBinVal (ID, PercentCov) ;
end function RandCovBinVal ;
impure function RandCovBinVal (ID : CoverageIDType) return RangeArrayType is
begin
return CoverageStore.RandCovBinVal (ID => ID) ;
end function RandCovBinVal ;
------------------------------------------------------------
-- Return Index Values
impure function GetNumBins (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetNumBins (ID => ID) ;
end function GetNumBins ;
impure function GetRandIndex (ID : CoverageIDType; CovTargetPercent : real ) return integer is
begin
return CoverageStore.GetRandIndex (ID, CovTargetPercent) ;
end function GetRandIndex ;
impure function GetRandIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetRandIndex (ID => ID) ;
end function GetRandIndex ;
impure function GetLastIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetLastIndex (ID => ID) ;
end function GetLastIndex ;
impure function GetIncIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetIncIndex (ID => ID) ;
end function GetIncIndex ;
impure function GetMinIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMinIndex (ID => ID) ;
end function GetMinIndex ;
impure function GetMaxIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetMaxIndex (ID => ID) ;
end function GetMaxIndex ;
impure function GetNextIndex (ID : CoverageIDType; Mode : NextPointModeType) return integer is
begin
return CoverageStore.GetNextIndex (ID, Mode) ;
end function GetNextIndex;
impure function GetNextIndex (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetNextIndex (ID => ID) ;
end function GetNextIndex ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Accessing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinInfo (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
begin
return CoverageStore.GetBinInfo(ID, BinIndex) ;
end function GetBinInfo ;
-- ------------------------------------------------------------
-- Intended as a stand in until we get a more general GetBin
impure function GetBinValLength (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetBinValLength(ID => ID);
end function GetBinValLength ;
-- ------------------------------------------------------------
-- Eventually the multiple GetBin functions will be replaced by a
-- a single GetBin that returns CovBinBaseType with BinVal as an
-- unconstrained element
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovBinBaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix2BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix3BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix4BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix5BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix6BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix7BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix8BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
impure function GetBin (ID : CoverageIDType; BinIndex : integer ) return CovMatrix9BaseType is
begin
return CoverageStore.GetBin(ID, BinIndex) ;
end function GetBin ;
-- ------------------------------------------------------------
impure function GetBinName (ID : CoverageIDType; BinIndex : integer; DefaultName : string := "" ) return string is
begin
return CoverageStore.GetBinName (ID, BinIndex, DefaultName) ;
end function GetBinName ;
------------------------------------------------------------
impure function GetErrorCount (ID : CoverageIDType) return integer is
begin
return CoverageStore.GetErrorCount (ID => ID) ;
end function GetErrorCount ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Printing Coverage Bin Information
-- /////////////////////////////////////////
------------------------------------------------------------
-- To specify the following, see SetReportOptions
-- WritePassFail, WriteBinInfo, WriteCount, WriteAnyIllegal
-- WritePrefix, PassName, FailName
------------------------------------------------------------
procedure WriteBin (ID : CoverageIDType) is
begin
CoverageStore.WriteBin (ID => ID) ;
end procedure WriteBin ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType ) is
begin
CoverageStore.WriteBin (ID, LogLevel) ;
end procedure WriteBin ;
procedure WriteBin (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) is
begin
CoverageStore.WriteBin (ID, FileName, OpenKind) ;
end procedure WriteBin ;
procedure WriteBin (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE) is
begin
CoverageStore.WriteBin (ID, LogLevel, FileName, OpenKind) ;
end procedure WriteBin ;
------------------------------------------------------------
procedure DumpBin (ID : CoverageIDType; LogLevel : LogType := DEBUG) is
begin
CoverageStore.DumpBin (ID, LogLevel) ;
end procedure DumpBin ;
------------------------------------------------------------
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType := ALWAYS ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; PercentCov : real ) is
begin
CoverageStore.WriteCovHoles (ID, PercentCov) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; PercentCov : real ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel, PercentCov) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, FileName, OpenKind) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel, FileName, OpenKind) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
procedure WriteCovHoles (ID : CoverageIDType; LogLevel : LogType; FileName : string; PercentCov : real ; OpenKind : File_Open_Kind := APPEND_MODE ) is
begin
CoverageStore.WriteCovHoles (ID, LogLevel, FileName, PercentCov, OpenKind) ;
end procedure WriteCovHoles ;
------------------------------------------------------------
-- /////////////////////////////////////////
-- Writing Out RAW Coverage Bin Information
-- Note that read supports merging of coverage models
-- /////////////////////////////////////////
------------------------------------------------------------
procedure ReadCovDb (ID : CoverageIDType; FileName : string; Merge : boolean := FALSE) is
begin
CoverageStore.ReadCovDb (ID, FileName, Merge) ;
end procedure ReadCovDb ;
procedure WriteCovDb (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
begin
CoverageStore.WriteCovDb (ID, FileName, OpenKind) ;
end procedure WriteCovDb ;
-- procedure WriteCovDb (ID : CoverageIDType) is
-- ------------------------------------------------------------
-- procedure WriteCovYaml (ID : CoverageIDType; FileName : string; OpenKind : File_Open_Kind := WRITE_MODE ) is
-- ------------------------------------------------------------
-- file CovYamlFile : text open OpenKind is FileName ;
-- begin
-- CoverageStore.WriteCovYaml (ID, FileName, OpenKind) ;
-- end procedure WriteCovYaml ;
------------------------------------------------------------
procedure WriteCovYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
begin
CoverageStore.WriteCovYaml(FileName, GetCov, OpenKind) ;
end procedure WriteCovYaml ;
------------------------------------------------------------
procedure ReadCovYaml (FileName : string := ""; Merge : boolean := FALSE) is
------------------------------------------------------------
begin
CoverageStore.ReadCovYaml(FileName, Merge) ;
end procedure ReadCovYaml ;
------------------------------------------------------------
impure function GotCoverage return boolean is
------------------------------------------------------------
begin
return CoverageStore.GotCoverage ;
end function GotCoverage ;
------------------------------------------------------------
impure function GetCov (PercentCov : real ) return real is
------------------------------------------------------------
variable ID : CoverageIDType ;
variable ItemCovCount, ItemCovGoal : integer ;
variable TotalCovCount, TotalCovGoal : integer := 0;
variable CovWeight : integer ;
variable ScaledCovGoal, rTotalCovCount : real ;
begin
for i in 1 to CoverageStore.GetNumIDs loop
ID := (ID => i) ;
CoverageStore.GetTotalCovCountAndGoal(ID, ItemCovCount, ItemCovGoal) ;
CovWeight := GetCovWeight(ID) ;
TotalCovCount := TotalCovCount + (ItemCovCount * CovWeight) ;
TotalCovGoal := TotalCovGoal + (ItemCovGoal * CovWeight) ;
end loop ;
ScaledCovGoal := PercentCov * real(TotalCovGoal) / 100.0 ;
rTotalCovCount := real(TotalCovCount) ;
if rTotalCovCount >= ScaledCovGoal then
return 100.0 ;
elsif ScaledCovGoal > 0.0 then
return (100.0 * rTotalCovCount) / ScaledCovGoal ;
else
return 0.0 ;
end if;
end function GetCov ;
------------------------------------------------------------
impure function GetCov return real is
------------------------------------------------------------
begin
return GetCov (100.0) ;
end function GetCov ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType ;
variable ErrorCount : inout integer
) is
variable NumBins1, NumBins2 : integer ;
variable BinInfo1, BinInfo2 : CovBinBaseType ;
variable BinVal1, BinVal2 : RangeArrayType(1 to Bin1.GetBinValLength) ;
variable buf : line ;
variable iAlertLogID : AlertLogIDType ;
begin
iAlertLogID := Bin1.GetAlertLogID ;
NumBins1 := Bin1.GetNumBins ;
NumBins2 := Bin2.GetNumBins ;
if (NumBins1 /= NumBins2) then
ErrorCount := ErrorCount + 1 ;
print("CoveragePkg.CompareBins: CoverageModels " & Bin1.GetCovModelName & " and " & Bin2.GetCovModelName &
" have different bin lengths") ;
return ;
end if ;
for i in 1 to NumBins1 loop
BinInfo1 := Bin1.GetBinInfo(i) ;
BinInfo2 := Bin2.GetBinInfo(i) ;
BinVal1 := Bin1.GetBinVal (i) ;
BinVal2 := Bin2.GetBinVal (i) ;
if BinInfo1 /= BinInfo2 or BinVal1 /= BinVal2 then
write(buf, "%% Bin:" & to_string(i) & " miscompare." & LF) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin1: ") ;
write(buf, BinVal1) ;
write(buf, " Action = " & to_string(BinInfo1.action)) ;
write(buf, " Count = " & to_string(BinInfo1.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo1.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo1.Weight) & LF ) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin2: ") ;
write(buf, BinVal2) ;
write(buf, " Action = " & to_string(BinInfo2.action)) ;
write(buf, " Count = " & to_string(BinInfo2.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo2.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo2.Weight) & LF ) ;
-- writeline(OUTPUT, buf) ;
ErrorCount := ErrorCount + 1 ;
writeline(buf) ;
-- Alert(iAlertLogID, buf.all, ERROR) ;
-- deallocate(buf) ;
end if ;
end loop ;
end procedure CompareBins ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
variable Bin1 : inout CovPType ;
variable Bin2 : inout CovPType
) is
variable ErrorCount : integer ;
variable iAlertLogID : AlertLogIDType ;
begin
CompareBins(Bin1, Bin2, ErrorCount) ;
iAlertLogID := Bin1.GetAlertLogID ;
AffirmIfEqual(ErrorCount, 0, "CompareBins(Bin1, Bin2, ErrorCount) " & Bin1.GetCovModelName & " and " & Bin2.GetCovModelName & " ErrorCount:") ;
end procedure CompareBins ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType ;
variable Valid : out Boolean
) is
variable NumBins1, NumBins2 : integer ;
variable BinInfo1, BinInfo2 : CovBinBaseType ;
variable BinVal1, BinVal2 : RangeArrayType(1 to GetBinValLength(Bin1)) ;
variable buf : line ;
variable iAlertLogID : AlertLogIDType ;
begin
iAlertLogID := GetAlertLogID(Bin1) ;
NumBins1 := GetNumBins(Bin1) ;
NumBins2 := GetNumBins(Bin2) ;
Valid := TRUE ;
if (NumBins1 /= NumBins2) then
Valid := FALSE ;
print("CoveragePkg.CompareBins: CoverageModels " & GetCovModelName(Bin1) & " and " & GetCovModelName(Bin2) &
" have different bin lengths") ;
return ;
end if ;
for i in 1 to NumBins1 loop
BinInfo1 := GetBinInfo(Bin1, i) ;
BinInfo2 := GetBinInfo(Bin2, i) ;
BinVal1 := GetBinVal (Bin1, i) ;
BinVal2 := GetBinVal (Bin2, i) ;
if BinInfo1 /= BinInfo2 or BinVal1 /= BinVal2 then
write(buf, "%% Bin: " & to_string(i) & " miscompare." & LF) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin1: ") ;
write(buf, BinVal1) ;
write(buf, " Action = " & to_string(BinInfo1.action)) ;
write(buf, " Count = " & to_string(BinInfo1.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo1.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo1.Weight) & LF ) ;
-- writeline(OUTPUT, buf) ;
swrite(buf, "%% Bin2: ") ;
write(buf, BinVal2) ;
write(buf, " Action = " & to_string(BinInfo2.action)) ;
write(buf, " Count = " & to_string(BinInfo2.count)) ;
write(buf, " AtLeast = " & to_string(BinInfo2.AtLeast)) ;
write(buf, " Weight = " & to_string(BinInfo2.Weight) ) ; -- & LF
-- writeline(OUTPUT, buf) ;
Valid := FALSE ;
writeline(buf) ;
-- Alert(iAlertLogID, buf.all, ERROR) ;
-- deallocate(buf) ;
end if ;
end loop ;
end procedure CompareBins ;
------------------------------------------------------------
-- Experimental. Intended primarily for development.
procedure CompareBins (
------------------------------------------------------------
constant Bin1 : in CoverageIDType ;
constant Bin2 : in CoverageIDType
) is
variable Valid : boolean ;
variable iAlertLogID : AlertLogIDType ;
begin
CompareBins(Bin1, Bin2, Valid) ;
iAlertLogID := GetAlertLogID(Bin1) ;
AffirmIf(iAlertLogID, Valid, "CompareBins(Bin1, Bin2) " & GetCovModelName(Bin1) & " and " & GetCovModelName(Bin2)) ;
end procedure CompareBins ;
------------------------------------------------------------
-- package local, Used by GenBin, IllegalBin, and IgnoreBin
function MakeBin(
-- Must be pure to allow initializing coverage models passed as generics.
-- Impure implies the expression is not globally static.
------------------------------------------------------------
Min, Max : integer ;
NumBin : integer ;
AtLeast : integer ;
Weight : integer ;
Action : integer
) return CovBinType is
variable iCovBin : CovBinType(1 to NumBin) ;
variable TotalBins : integer ; -- either real or integer
variable rMax, rCurMin, rNumItemsInBin, rRemainingBins : real ; -- must be real
variable iCurMin, iCurMax : integer ;
begin
if Min > Max then
-- Similar to NULL ranges. Only generate report warning.
report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) MAX > MIN generated NULL_BIN"
severity WARNING ;
-- No Alerts. They make this impure.
-- Alert(OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.MakeBin (called by GenBin, IllegalBin, IgnoreBin): Min must be <= Max", WARNING) ;
return NULL_BIN ;
elsif NumBin <= 0 then
-- Similar to NULL ranges. Only generate report warning.
report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) NumBin <= 0 generated NULL_BIN"
severity WARNING ;
-- Alerts make this impure.
-- Alert(OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.MakeBin (called by GenBin, IllegalBin, IgnoreBin): NumBin must be <= 0", WARNING) ;
return NULL_BIN ;
elsif NumBin = 1 then
iCovBin(1) := (
BinVal => (1 => (Min, Max)),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
return iCovBin ;
else
-- Using type real to work around issues with integer sizing
iCurMin := Min ;
rCurMin := real(iCurMin) ;
rMax := real(Max) ;
rRemainingBins := (minimum( real(NumBin), rMax - rCurMin + 1.0 )) ;
TotalBins := integer(rRemainingBins) ;
for i in iCovBin'range loop
rNumItemsInBin := trunc((rMax - rCurMin + 1.0) / rRemainingBins) ; -- Max - Min can be larger than integer range.
iCurMax := iCurMin - integer(-rNumItemsInBin + 1.0) ; -- Keep: the "minus negative" works around a simulator bounds issue found in 2015.06
iCovBin(i) := (
BinVal => (1 => (iCurMin, iCurMax)),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
rRemainingBins := rRemainingBins - 1.0 ;
exit when rRemainingBins = 0.0 ;
iCurMin := iCurMax + 1 ;
rCurMin := real(iCurMin) ;
end loop ;
return iCovBin(1 to TotalBins) ;
end if ;
end function MakeBin ;
------------------------------------------------------------
-- package local, Used by GenBin, IllegalBin, and IgnoreBin
function MakeBin(
------------------------------------------------------------
A : integer_vector ;
AtLeast : integer ;
Weight : integer ;
Action : integer
) return CovBinType is
alias NewA : integer_vector(1 to A'length) is A ;
variable iCovBin : CovBinType(1 to A'length) ;
begin
if A'length <= 0 then
-- Similar to NULL ranges. Only generate report warning.
report "OSVVM.CoveragePkg.MakeBin (called by GenBin, IllegalBin, or IgnoreBin) integer_vector length <= 0 generated NULL_BIN"
severity WARNING ;
-- Alerts make this impure.
-- Alert(OSVVM_COVERAGE_ALERTLOG_ID, "CoveragePkg.MakeBin (GenBin, IllegalBin, IgnoreBin): integer_vector parameter must have values", WARNING) ;
return NULL_BIN ;
else
for i in NewA'Range loop
iCovBin(i) := (
BinVal => (i => (NewA(i), NewA(i)) ),
Action => Action,
Count => 0,
Weight => Weight,
AtLeast => AtLeast
) ;
end loop ;
return iCovBin ;
end if ;
end function MakeBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType is
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => AtLeast,
Weight => Weight,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Min, Max : integer ;
NumBin : integer
) return CovBinType is
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => AtLeast,
Weight => 1,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin( Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( Min, Max : integer) return CovBinType is
------------------------------------------------------------
begin
-- create a separate CovBin for each value
-- AtLeast and Weight = 1 (must use longer version to specify)
return MakeBin(
Min => Min,
Max => Max,
NumBin => Max - Min + 1,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( A : integer ) return CovBinType is
------------------------------------------------------------
begin
-- create a single CovBin for A.
-- AtLeast and Weight = 1 (must use longer version to specify)
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin(
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
A : integer_vector
) return CovBinType is
begin
return MakeBin(
A => A,
AtLeast => AtLeast,
Weight => Weight,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( AtLeast : integer ; A : integer_vector ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
A => A,
AtLeast => AtLeast,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function GenBin ( A : integer_vector ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
A => A,
AtLeast => 0,
Weight => 0,
Action => COV_COUNT
) ;
end function GenBin ;
------------------------------------------------------------
function IllegalBin ( Min, Max, NumBin : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
------------------------------------------------------------
function IllegalBin ( Min, Max : integer ) return CovBinType is
------------------------------------------------------------
begin
-- default, generate one CovBin with the entire range of values
return MakeBin(
Min => Min,
Max => Max,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
------------------------------------------------------------
function IllegalBin ( A : integer ) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_ILLEGAL
) ;
end function IllegalBin ;
-- IgnoreBin should never have an AtLeast parameter
------------------------------------------------------------
function IgnoreBin (Min, Max, NumBin : integer) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => Min,
Max => Max,
NumBin => NumBin,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (Min, Max : integer) return CovBinType is
------------------------------------------------------------
begin
-- default, generate one CovBin with the entire range of values
return MakeBin(
Min => Min,
Max => Max,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function IgnoreBin (A : integer) return CovBinType is
------------------------------------------------------------
begin
return MakeBin(
Min => A,
Max => A,
NumBin => 1,
AtLeast => 0,
Weight => 0,
Action => COV_IGNORE
) ;
end function IgnoreBin ;
------------------------------------------------------------
function GenCross( -- 2
-- Cross existing bins
-- Use AddCross for adding values directly to coverage database
-- Use GenCross for constants
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2 : CovBinType
) return CovMatrix2Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix2Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross(AtLeast : integer ; Bin1, Bin2 : CovBinType) return CovMatrix2Type is
-- Cross existing bins -- use AddCross instead
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2) ;
end function GenCross ;
------------------------------------------------------------
function GenCross(Bin1, Bin2 : CovBinType) return CovMatrix2Type is
-- Cross existing bins -- use AddCross instead
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 3
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3 : CovBinType
) return CovMatrix3Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix3Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3 : CovBinType ) return CovMatrix3Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 4
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4 : CovBinType
) return CovMatrix4Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix4Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4 : CovBinType ) return CovMatrix4Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 5
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType
) return CovMatrix5Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix5Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5 : CovBinType ) return CovMatrix5Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 6
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType
) return CovMatrix6Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix6Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6 : CovBinType ) return CovMatrix6Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 7
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType
) return CovMatrix7Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix7Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7 : CovBinType ) return CovMatrix7Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 8
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType
) return CovMatrix8Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix8Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8 : CovBinType ) return CovMatrix8Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( -- 9
------------------------------------------------------------
AtLeast : integer ;
Weight : integer ;
Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType
) return CovMatrix9Type is
constant BIN_LENS : integer_vector := BinLengths(Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
constant NUM_NEW_BINS : integer := CalcNumCrossBins(BIN_LENS) ;
variable BinIndex : integer_vector(1 to BIN_LENS'length) := (others => 1) ;
variable CrossBins : CovBinType(BinIndex'range) ;
variable Action : integer ;
variable iCovMatrix : CovMatrix9Type(1 to NUM_NEW_BINS) ;
begin
for MatrixIndex in iCovMatrix'range loop
CrossBins := ConcatenateBins(BinIndex, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
Action := MergeState(CrossBins) ;
iCovMatrix(MatrixIndex).action := Action ;
iCovMatrix(MatrixIndex).count := 0 ;
iCovMatrix(MatrixIndex).BinVal := MergeBinVal(CrossBins) ;
iCovMatrix(MatrixIndex).AtLeast := MergeAtLeast( Action, AtLeast, CrossBins) ;
iCovMatrix(MatrixIndex).Weight := MergeWeight ( Action, Weight, CrossBins) ;
IncBinIndex( BinIndex, BIN_LENS ) ; -- increment right most one, then if overflow, increment next
end loop ;
return iCovMatrix ;
end function GenCross ;
------------------------------------------------------------
function GenCross( AtLeast : integer ; Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is
------------------------------------------------------------
begin
return GenCross(AtLeast, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
end function GenCross ;
------------------------------------------------------------
function GenCross( Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9 : CovBinType ) return CovMatrix9Type is
------------------------------------------------------------
begin
return GenCross(1, 1, Bin1, Bin2, Bin3, Bin4, Bin5, Bin6, Bin7, Bin8, Bin9) ;
end function GenCross ;
------------------------------------------------------------
function to_integer ( B : boolean ) return integer is
------------------------------------------------------------
begin
if B then
return 1 ;
else
return 0 ;
end if ;
end function to_integer ;
------------------------------------------------------------
function CheckInteger_1_0 ( I : integer ) return boolean is
-------------------------------------------------------------
begin
case I is
when 0 | 1 => return TRUE ;
when others => return FALSE ;
end case ;
end function CheckInteger_1_0 ;
------------------------------------------------------------
function local_to_boolean ( I : integer ) return boolean is
------------------------------------------------------------
begin
case I is
when 1 => return TRUE ;
when 0 => return FALSE ;
when others =>
return FALSE ;
end case ;
end function local_to_boolean ;
------------------------------------------------------------
function to_boolean ( I : integer ) return boolean is
------------------------------------------------------------
begin
if not CheckInteger_1_0(I) then
report
"CoveragePkg.to_boolean: invalid integer value: " & to_string(I) &
" returning FALSE" severity WARNING ;
end if ;
return local_to_boolean(I) ;
end function to_boolean ;
------------------------------------------------------------
function to_integer ( SL : std_logic ) return integer is
-------------------------------------------------------------
begin
case SL is
when '1' | 'H' => return 1 ;
when '0' | 'L' => return 0 ;
when others => return -1 ;
end case ;
end function to_integer ;
------------------------------------------------------------
function local_to_std_logic ( I : integer ) return std_logic is
-------------------------------------------------------------
begin
case I is
when 1 => return '1' ;
when 0 => return '0' ;
when others => return 'X' ;
end case ;
end function local_to_std_logic ;
------------------------------------------------------------
function to_std_logic ( I : integer ) return std_logic is
-------------------------------------------------------------
begin
if not CheckInteger_1_0(I) then
report
"CoveragePkg.to_std_logic: invalid integer value: " & to_string(I) &
" returning X" severity WARNING ;
end if ;
return local_to_std_logic(I) ;
end function to_std_logic ;
------------------------------------------------------------
function to_integer_vector ( BV : boolean_vector ) return integer_vector is
------------------------------------------------------------
variable result : integer_vector(BV'range) ;
begin
for i in BV'range loop
result(i) := to_integer(BV(i)) ;
end loop ;
return result ;
end function to_integer_vector ;
------------------------------------------------------------
function to_boolean_vector ( IV : integer_vector ) return boolean_vector is
------------------------------------------------------------
variable result : boolean_vector(IV'range) ;
variable HasError : boolean := FALSE ;
begin
for i in IV'range loop
result(i) := local_to_boolean(IV(i)) ;
if not CheckInteger_1_0(IV(i)) then
HasError := TRUE ;
end if ;
end loop ;
if HasError then
report
"CoveragePkg.to_boolean_vector: invalid integer value" &
" returning FALSE" severity WARNING ;
end if ;
return result ;
end function to_boolean_vector ;
------------------------------------------------------------
function to_integer_vector ( SLV : std_logic_vector ) return integer_vector is
-------------------------------------------------------------
variable result : integer_vector(SLV'range) ;
begin
for i in SLV'range loop
result(i) := to_integer(SLV(i)) ;
end loop ;
return result ;
end function to_integer_vector ;
------------------------------------------------------------
function to_std_logic_vector ( IV : integer_vector ) return std_logic_vector is
-------------------------------------------------------------
variable result : std_logic_vector(IV'range) ;
variable HasError : boolean := FALSE ;
begin
for i in IV'range loop
result(i) := local_to_std_logic(IV(i)) ;
if not CheckInteger_1_0(IV(i)) then
HasError := TRUE ;
end if ;
end loop ;
if HasError then
report
"CoveragePkg.to_std_logic_vector: invalid integer value" &
" returning FALSE" severity WARNING ;
end if ;
return result ;
end function to_std_logic_vector ;
end package body CoveragePkg ; | artistic-2.0 | 085ef304ac497916b4e3a9b4f4ae741f | 0.52409 | 4.438126 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/11KP/Контрольна1 розв'язки/v2z2/lpm_shiftreg0.vhd | 2 | 4,156 | -- megafunction wizard: %LPM_SHIFTREG%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_shiftreg
-- ============================================================
-- File Name: lpm_shiftreg0.vhd
-- Megafunction Name(s):
-- lpm_shiftreg
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 132 02/25/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_shiftreg0 IS
PORT
(
clock : IN STD_LOGIC ;
shiftin : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END lpm_shiftreg0;
ARCHITECTURE SYN OF lpm_shiftreg0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_shiftreg
GENERIC (
lpm_direction : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
shiftin : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(3 DOWNTO 0);
lpm_shiftreg_component : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 4
)
PORT MAP (
clock => clock,
shiftin => shiftin,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX3000A"
-- Retrieval info: PRIVATE: LeftShift NUMERIC "1"
-- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "0"
-- Retrieval info: PRIVATE: Q_OUT NUMERIC "1"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "1"
-- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: shiftin 0 0 0 0 INPUT NODEFVAL shiftin
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: @shiftin 0 0 0 0 shiftin 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 | 2a8beaf6aaf89376a910e4678abe5ad1 | 0.653272 | 3.771325 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_slave_attachment.vhd | 1 | 22,347 | -------------------------------------------------------------------------------
-- Slave Attachment - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --cpu_xadc_wiz_0_0_axi_lite_ipif.vhd
-- --cpu_xadc_wiz_0_0_slave_attachment.vhd
-- --cpu_xadc_wiz_0_0_address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library work;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.max2;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
use work.cpu_xadc_wiz_0_0_family_support.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity cpu_xadc_wiz_0_0_slave_attachment;
-------------------------------------------------------------------------------
architecture imp of cpu_xadc_wiz_0_0_slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= s_axi_aclk;
Bus2IP_Resetn <= s_axi_aresetn;
bus2ip_rnw_i <= '1' when s_axi_arvalid='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= s_axi_wstrb when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= s_axi_wdata;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & s_axi_araddr(C_ADDR_DECODE_BITS downto 0)
when (s_axi_arvalid='1')
else
ZEROS & s_axi_awaddr(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (s_axi_arvalid or (s_axi_awvalid and s_axi_wvalid))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.cpu_xadc_wiz_0_0_address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => s_axi_aclk,
Bus_rst => s_axi_aresetn,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => s_axi_arvalid,
Bus_RNW_Erly => s_axi_arvalid,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
rst <= not s_axi_aresetn;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (s_axi_arvalid = '1') then -- Read precedence over write
state <= SM_READ;
elsif (s_axi_awvalid = '1' and s_axi_wvalid = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and s_axi_bready) or
(s_axi_rvalid_i and s_axi_rready)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
s_axi_rresp <= s_axi_rresp_i;
s_axi_rdata <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (s_axi_rready = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
s_axi_bresp <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (s_axi_aclk) is
begin
if s_axi_aclk'event and s_axi_aclk = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (s_axi_bready = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (s_axi_aclk) is
begin
if (s_axi_aclk'event and s_axi_aclk = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
s_axi_bvalid <= s_axi_bvalid_i;
s_axi_rvalid <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
s_axi_arready <= rd_done;
s_axi_awready <= wr_done;
s_axi_wready <= wr_done;
-------------------------------------------------------------------------------
end imp;
| gpl-3.0 | cdea4b566605e3fefac3e5d93c01ef14 | 0.473307 | 4.083135 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/controller_tb.vhd | 1 | 1,180 |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use work.custom_pkg.all;
ENTITY controller_tb IS
END controller_tb;
ARCHITECTURE behavior OF controller_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT controller
PORT(
clk : IN std_logic;
reset : IN std_logic;
output : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: controller PORT MAP (
clk => clk,
reset => reset,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
-- hold reset state for 100 ns.
wait for 100 ns;
reset <= '0';
wait for clk_period*10;
wait for 5000 ns ;
end process;
END;
| bsd-2-clause | bb44a1d28d4f5091cc2bbf6044270a8f | 0.589831 | 3.69906 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | tb/tb.vhd | 1 | 879 | library IEEE;
use IEEE.std_logic_1164.all;
entity TB is
end entity;
architecture TB_ARCH of TB is
component SEMI_MIPS_MODULE is
port(
CLK : std_logic;
EXTERNAL_RESET : std_logic
);
end component;
signal CLK_COUNTER : integer := 0;
signal CLK_COUNT : integer := 50;
signal CLK : std_logic := '1';
signal EXTERNAL_RESET : std_logic;
begin
CLOCK_GEN : process is
begin
loop
CLK <= not CLK;
wait for 100 ns;
CLK <= not CLK;
wait for 100 ns;
CLK_COUNTER <= CLK_COUNTER + 1;
if(CLK_COUNTER = CLK_COUNT) then
assert false report "Reached end of the clock generation";
wait;
end if;
end loop;
end process CLOCK_GEN;
SEMI_MIPS_MODULE_inst : component SEMI_MIPS_MODULE
port map(
CLK => CLK,
EXTERNAL_RESET => EXTERNAL_RESET
);
EXTERNAL_RESET <= '1', '0' after 200 ns;
end architecture; | gpl-3.0 | b771c7e4ea6ba4a74698b023032017f5 | 0.637088 | 3.073427 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/RxIn_Delays.vhd | 1 | 41,437 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RxIn_Delay is
port (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
trn_rdst_rdy_n : OUT std_logic;
Pool_wrBuf_full : IN std_logic;
Link_Buf_full : IN std_logic;
-- Delay for one clock
trn_rsof_n_dly : OUT std_logic;
trn_reof_n_dly : OUT std_logic;
trn_rd_dly : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n_dly : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n_dly : OUT std_logic;
trn_rsrc_rdy_n_dly : OUT std_logic;
trn_rdst_rdy_n_dly : OUT std_logic;
trn_rsrc_dsc_n_dly : OUT std_logic;
trn_rbar_hit_n_dly : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
IORd_Type : OUT std_logic;
IOWr_Type : OUT std_logic;
MRd_Type : OUT std_logic_vector(3 downto 0);
MWr_Type : OUT std_logic_vector(1 downto 0);
CplD_Type : OUT std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
dsDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB : OUT std_logic;
-- To Cpl/D channel
Tlp_has_4KB : OUT std_logic;
Tlp_has_1DW : OUT std_logic;
CplD_is_the_Last : OUT std_logic;
CplD_on_Pool : OUT std_logic;
CplD_on_EB : OUT std_logic;
Req_ID_Match : OUT std_logic;
usDex_Tag_Matched : OUT std_logic;
dsDex_Tag_Matched : OUT std_logic;
CplD_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end entity RxIn_Delay;
architecture Behavioral of RxIn_Delay is
-- Max Length Checking
signal Tlp_has_0_Length : std_logic;
signal Tlp_has_1DW_Length_i : std_logic;
signal MaxReadReqSize_Exceeded: std_logic;
signal MaxPayloadSize_Exceeded: std_logic;
signal Tlp_straddles_4KB_i : std_logic;
signal CarryIn_ALC : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal Tlp_has_4KB_i : std_logic;
signal cfg_MRS : std_logic_vector(C_CFG_MRS_BIT_TOP-C_CFG_MRS_BIT_BOT downto 0);
signal cfg_MPS : std_logic_vector(C_CFG_MPS_BIT_TOP-C_CFG_MPS_BIT_BOT downto 0);
signal cfg_MRS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
signal cfg_MPS_decoded : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
TYPE CfgThreshold is ARRAY (C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE downto 0)
of std_logic_vector (C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal MaxSize_Thresholds : CfgThreshold;
-- As one clock of delay
signal trn_rsof_n_r1 : std_logic;
signal trn_reof_n_r1 : std_logic;
signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rerrfwd_n_r1 : std_logic;
signal trn_rsrc_rdy_n_r1 : std_logic;
signal trn_rdst_rdy_n_i : std_logic;
signal trn_rdst_rdy_n_r1 : std_logic;
signal trn_rsrc_dsc_n_r1 : std_logic;
signal trn_rbar_hit_n_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP type decision
signal TLP_is_MRd_BAR0_H3DW : std_logic;
signal TLP_is_MRd_BAR1_H3DW : std_logic;
signal TLP_is_MRd_BAR2_H3DW : std_logic;
signal TLP_is_MRd_BAR3_H3DW : std_logic;
signal TLP_is_MRd_BAR0_H4DW : std_logic;
signal TLP_is_MRd_BAR1_H4DW : std_logic;
signal TLP_is_MRd_BAR2_H4DW : std_logic;
signal TLP_is_MRd_BAR3_H4DW : std_logic;
signal TLP_is_MRdLk_BAR0_H3DW : std_logic;
signal TLP_is_MRdLk_BAR1_H3DW : std_logic;
signal TLP_is_MRdLk_BAR2_H3DW : std_logic;
signal TLP_is_MRdLk_BAR3_H3DW : std_logic;
signal TLP_is_MRdLk_BAR0_H4DW : std_logic;
signal TLP_is_MRdLk_BAR1_H4DW : std_logic;
signal TLP_is_MRdLk_BAR2_H4DW : std_logic;
signal TLP_is_MRdLk_BAR3_H4DW : std_logic;
signal TLP_is_MWr_BAR0_H3DW : std_logic;
signal TLP_is_MWr_BAR1_H3DW : std_logic;
signal TLP_is_MWr_BAR2_H3DW : std_logic;
signal TLP_is_MWr_BAR3_H3DW : std_logic;
signal TLP_is_MWr_BAR0_H4DW : std_logic;
signal TLP_is_MWr_BAR1_H4DW : std_logic;
signal TLP_is_MWr_BAR2_H4DW : std_logic;
signal TLP_is_MWr_BAR3_H4DW : std_logic;
signal TLP_is_IORd_BAR0 : std_logic;
signal TLP_is_IORd_BAR1 : std_logic;
signal TLP_is_IORd_BAR2 : std_logic;
signal TLP_is_IORd_BAR3 : std_logic;
signal TLP_is_IOWr_BAR0 : std_logic;
signal TLP_is_IOWr_BAR1 : std_logic;
signal TLP_is_IOWr_BAR2 : std_logic;
signal TLP_is_IOWr_BAR3 : std_logic;
signal TLP_is_IORd : std_logic;
signal TLP_is_IOWr : std_logic;
signal TLP_is_CplD : std_logic;
signal TLP_is_Cpl : std_logic;
signal TLP_is_CplDLk : std_logic;
signal TLP_is_CplLk : std_logic;
signal TLP_is_MRd_H3DW : std_logic;
signal TLP_is_MRd_H4DW : std_logic;
signal TLP_is_MRdLk_H3DW : std_logic;
signal TLP_is_MRdLk_H4DW : std_logic;
signal TLP_is_MWr_H3DW : std_logic;
signal TLP_is_MWr_H4DW : std_logic;
signal IORd_Type_i : std_logic;
signal IOWr_Type_i : std_logic;
signal MRd_Type_i : std_logic_vector(3 downto 0);
signal MWr_Type_i : std_logic_vector(1 downto 0);
signal CplD_Type_i : std_logic_vector(3 downto 0);
signal Req_ID_Match_i : std_logic;
signal usDex_Tag_Matched_i : std_logic;
signal dsDex_Tag_Matched_i : std_logic;
-----------------------------------------------------------------
-- Inbound DW counter
signal TLP_Payload_Address_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal TLP_DW_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal TLP_Address_sig : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal MWr_on_Pool : std_logic;
signal MWr_on_EB : std_logic;
signal CplD_on_Pool_i : std_logic;
signal CplD_on_EB_i : std_logic;
signal CplD_is_the_Last_i : std_logic;
signal CplD_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Counter inside a TLP
type TLPCntStates is ( TK_RST
, TK_Idle
-- , TK_MWr_3Hdr_B
, TK_MWr_3Hdr_C
-- , TK_MWr_4Hdr_B
, TK_MWr_4Hdr_C
-- , TK_MWr_4Hdr_D
-- , TK_CplD_Hdr_B
, TK_CplD_Hdr_C
, TK_Body
);
signal FSM_TLP_Cnt : TLPCntStates;
signal FSM_TLP_Cnt_r1 : TLPCntStates;
-- CplD tag capture FSM (Address at tRAM)
type AddrOnRAM_States is ( AOtSt_RST
, AOtSt_Idle
, AOtSt_HdrA
, AOtSt_HdrB
, AOtSt_Body
);
signal FSM_AOtRAM : AddrOnRAM_States;
begin
trn_rdst_rdy_n <= trn_rdst_rdy_n_i ; -- and trn_rsof_n and trn_rsof_n_r1 ;
-- Delay
trn_rsof_n_dly <= trn_rsof_n_r1 ;
trn_reof_n_dly <= trn_reof_n_r1 ;
trn_rrem_n_dly <= trn_rrem_n_r1 ;
trn_rd_dly <= trn_rd_r1 ;
trn_rerrfwd_n_dly <= trn_rerrfwd_n_r1 ;
trn_rsrc_rdy_n_dly <= trn_rsrc_rdy_n_r1 ;
trn_rdst_rdy_n_dly <= trn_rdst_rdy_n_r1 ; -- trn_rdst_rdy_n_r1 ;
trn_rsrc_dsc_n_dly <= trn_rsrc_dsc_n_r1 ;
trn_rbar_hit_n_dly <= trn_rbar_hit_n_r1 ;
-- TLP resolution
IORd_Type <= '0' ; -- IORd_Type_i ;
IOWr_Type <= '0' ; -- IOWr_Type_i ;
MRd_Type <= MRd_Type_i ;
MWr_Type <= MWr_Type_i ;
CplD_Type <= CplD_Type_i ;
-- To Cpl/D channel
Req_ID_Match <= Req_ID_Match_i ;
usDex_Tag_Matched <= usDex_Tag_Matched_i ;
dsDex_Tag_Matched <= dsDex_Tag_Matched_i ;
CplD_Tag <= CplD_Tag_i ;
CplD_is_the_Last <= CplD_is_the_Last_i ;
CplD_on_Pool <= CplD_on_Pool_i ;
CplD_on_EB <= CplD_on_EB_i ;
Tlp_has_4KB <= Tlp_has_4KB_i ;
Tlp_has_1DW <= Tlp_has_1DW_Length_i ;
Tlp_straddles_4KB <= '0'; --Tlp_straddles_4KB_i ;
-- !! !!
MaxReadReqSize_Exceeded <= '0';
MaxPayloadSize_Exceeded <= '0';
----------------------------------------------
--
-- Synchronous Registered: TLP_DW_Length
-- Tlp_has_4KB
-- Tlp_has_1DW_Length
-- Tlp_has_0_Length
--
FSM_TLP_1ST_DW_Info:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
TLP_DW_Length_i <= (OTHERS => '0');
Tlp_has_4KB_i <= '0';
Tlp_has_1DW_Length_i <= '0';
Tlp_has_0_Length <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n='0' then
TLP_DW_Length_i <= trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
else
TLP_DW_Length_i <= TLP_DW_Length_i;
end if;
if trn_rsof_n ='0' then
if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) then
Tlp_has_4KB_i <= '1' ;
else
Tlp_has_4KB_i <= '0' ;
end if;
else
Tlp_has_4KB_i <= Tlp_has_4KB_i ;
end if;
if trn_rsof_n ='0' then
if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
Tlp_has_1DW_Length_i <= '1';
else
Tlp_has_1DW_Length_i <= '0';
end if;
else
Tlp_has_1DW_Length_i <= Tlp_has_1DW_Length_i;
end if;
if trn_rsof_n ='0' then
if trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
= CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and trn_rd(2)='0' then
Tlp_has_0_Length <= '1';
else
Tlp_has_0_Length <= '0';
end if;
else
Tlp_has_0_Length <= Tlp_has_0_Length;
end if;
end if;
end process;
---- --------------------------------------------------------------------------
-- -- Max Payload Size bits
-- cfg_MPS <= cfg_dcommand(C_CFG_MPS_BIT_TOP downto C_CFG_MPS_BIT_BOT);
--
-- -- Max Read Request Size bits
-- cfg_MRS <= cfg_dcommand(C_CFG_MRS_BIT_TOP downto C_CFG_MRS_BIT_BOT);
--
--
--
-- -- --------------------------------
-- -- Decoding MPS
-- --
-- Trn_Rx_Decoding_MPS:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MPS is
-- when CONV_STD_LOGIC_VECTOR(0, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(1, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(2, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(3, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(4, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(5, 3) =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when Others =>
-- cfg_MPS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -- --------------------------------
-- -- Decoding MRS
-- --
-- Trn_Rx_Decoding_MRS:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MRS is
-- when CONV_STD_LOGIC_VECTOR(0, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(1, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(2, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(3, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(4, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when CONV_STD_LOGIC_VECTOR(5, 3) =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- when Others =>
-- cfg_MRS_decoded <= MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE);
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -------------------------------------------------------------
-- MaxSize_Thresholds(0) <= (CBIT_SENSE_OF_MAXSIZE=>'1', Others=>'0');
-- Gen_MaxSizes:
-- FOR i IN 1 TO C_TLP_FLD_WIDTH_OF_LENG-CBIT_SENSE_OF_MAXSIZE GENERATE
-- MaxSize_Thresholds(i) <= MaxSize_Thresholds(i-1)(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0)&'0';
-- END GENERATE;
--
-- -- --------------------------------
-- -- Calculation of MPS exceed
-- --
-- Trn_Rx_MaxPayloadSize_Exceeded:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MPS_decoded is
--
---- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
---- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
---- MaxPayloadSize_Exceeded <= '1';
---- else
---- MaxPayloadSize_Exceeded <= '0';
---- end if;
--
-- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- MaxPayloadSize_Exceeded <= '0'; -- !!
--
-- when OTHERS =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
-- MaxPayloadSize_Exceeded <= '1';
-- else
-- MaxPayloadSize_Exceeded <= '0';
-- end if;
--
-- end case;
--
-- end if;
-- end process;
--
--
-- -- --------------------------------
-- -- Calculation of MRS exceed
-- --
-- Trn_Rx_MaxReadReqSize_Exceeded:
-- process ( trn_clk )
-- begin
-- if trn_clk'event and trn_clk = '1' then
--
-- case cfg_MRS_decoded is
--
---- when CONV_STD_LOGIC_VECTOR(1, 6) => -- MaxSize_Thresholds(0)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
---- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
---- MaxReadReqSize_Exceeded <= '1';
---- else
---- MaxReadReqSize_Exceeded <= '0';
---- end if;
--
-- when CONV_STD_LOGIC_VECTOR(2, 6) => -- MaxSize_Thresholds(1)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(1) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(4, 6) => -- MaxSize_Thresholds(2)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(2) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(8, 6) => -- MaxSize_Thresholds(3)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(3) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(16, 6) => -- MaxSize_Thresholds(4)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(4) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- when CONV_STD_LOGIC_VECTOR(32, 6) => -- MaxSize_Thresholds(5)(C_TLP_FLD_WIDTH_OF_LENG downto CBIT_SENSE_OF_MAXSIZE) =>
-- MaxReadReqSize_Exceeded <= '0'; -- !!
--
-- when OTHERS =>
-- if trn_rd(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0) > MaxSize_Thresholds(0) then
-- MaxReadReqSize_Exceeded <= '1';
-- else
-- MaxReadReqSize_Exceeded <= '0';
-- end if;
--
-- end case;
--
-- end if;
-- end process;
-- ---------------------------------------------------------
---- Pipelining all trn_rx input signals for one clock
---- to get better timing
----
Trn_Rx_Inputs_Delayed:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_rsof_n_r1 <= trn_rsof_n;
trn_reof_n_r1 <= trn_reof_n;
trn_rrem_n_r1 <= trn_rrem_n;
trn_rd_r1 <= trn_rd;
trn_rerrfwd_n_r1 <= trn_rerrfwd_n;
trn_rsrc_rdy_n_r1 <= trn_rsrc_rdy_n;
trn_rdst_rdy_n_r1 <= trn_rdst_rdy_n_i;
trn_rsrc_dsc_n_r1 <= trn_rsrc_dsc_n;
trn_rbar_hit_n_r1 <= trn_rbar_hit_n;
end if;
end process;
-- -----------------------------------------
-- TLP Types
--
TLP_Decision_Registered:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
TLP_is_MRd_H3DW <= '0';
TLP_is_MRdLk_H3DW <= '0';
TLP_is_MRd_H4DW <= '0';
TLP_is_MRdLk_H4DW <= '0';
TLP_is_MWr_H3DW <= '0';
TLP_is_MWr_H4DW <= '0';
TLP_is_IORd <= '0';
TLP_is_IOWr <= '0';
TLP_is_CplD <= '0';
TLP_is_CplDLk <= '0';
TLP_is_Cpl <= '0';
TLP_is_CplLk <= '0';
elsif trn_clk'event and trn_clk = '1' then
-- IORd
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_IORd <= '1';
else
TLP_is_IORd <= '0';
end if;
-- IOWr
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_IO_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_IOWr <= '1';
else
TLP_is_IOWr <= '0';
end if;
-- MRd
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRd_H3DW <= '1';
else
TLP_is_MRd_H3DW <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRd_H4DW <= '1';
else
TLP_is_MRd_H4DW <= '0';
end if;
-- MRdLk
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRdLk_H3DW <= '1';
else
TLP_is_MRdLk_H3DW <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ_LK
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MRdLk_H4DW <= '1';
else
TLP_is_MRdLk_H4DW <= '0';
end if;
-- MWr
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MWr_H3DW <= '1';
else
TLP_is_MWr_H3DW <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT4_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_MEM_REQ
and trn_rd(C_TLP_EP_BIT) ='0'
-- and trn_rbar_hit_n(CINT_REGS_SPACE_BAR) ='0'
and trn_rbar_hit_n(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0)
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_MWr_H4DW <= '1';
else
TLP_is_MWr_H4DW <= '0';
end if;
-- CplD, Cpl/CplDLk, CplLk
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_CplD <= '1';
else
TLP_is_CplD <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_WITH_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_CplDLk <= '1';
else
TLP_is_CplDLk <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_Cpl <= '1';
else
TLP_is_Cpl <= '0';
end if;
if trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) = C_FMT3_NO_DATA
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_BOT) = C_TYPE_COMPLETION_LK
and trn_rd(C_TLP_EP_BIT) ='0'
and trn_rsrc_rdy_n ='0'
and trn_rsof_n ='0'
then
TLP_is_CplLk <= '1';
else
TLP_is_CplLk <= '0';
end if;
end if;
end process;
-- --------------------------------------------------------------------------
-- TLP_is_IORd <= TLP_is_IORd_BAR0 or TLP_is_IORd_BAR1;
-- TLP_is_IOWr <= TLP_is_IOWr_BAR0 or TLP_is_IOWr_BAR1;
-- TLP_is_MRd_H3DW <= TLP_is_MRd_BAR0_H3DW or TLP_is_MRd_BAR1_H3DW;
-- TLP_is_MRdLk_H3DW <= TLP_is_MRdLk_BAR0_H3DW or TLP_is_MRdLk_BAR1_H3DW;
-- TLP_is_MRd_H4DW <= TLP_is_MRd_BAR0_H4DW or TLP_is_MRd_BAR1_H4DW;
-- TLP_is_MRdLk_H4DW <= TLP_is_MRdLk_BAR0_H4DW or TLP_is_MRdLk_BAR1_H4DW;
-- TLP_is_MWr_H3DW <= TLP_is_MWr_BAR0_H3DW or TLP_is_MWr_BAR1_H3DW;
-- TLP_is_MWr_H4DW <= TLP_is_MWr_BAR0_H4DW or TLP_is_MWr_BAR1_H4DW;
-- --------------------------------------------------------------------------
IORd_Type_i <= TLP_is_IORd and Tlp_has_1DW_Length_i;
IOWr_Type_i <= TLP_is_IOWr and Tlp_has_1DW_Length_i;
MRd_Type_i <= (TLP_is_MRd_H3DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRdLk_H3DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRd_H4DW and not MaxReadReqSize_Exceeded)
& (TLP_is_MRdLk_H4DW and not MaxReadReqSize_Exceeded)
;
MWr_Type_i <= (TLP_is_MWr_H3DW and not MaxPayloadSize_Exceeded)
& (TLP_is_MWr_H4DW and not MaxPayloadSize_Exceeded)
;
CplD_Type_i <= (TLP_is_CplD and not MaxPayloadSize_Exceeded)
& (TLP_is_Cpl and not MaxPayloadSize_Exceeded)
& (TLP_is_CplDLk and not MaxPayloadSize_Exceeded)
& (TLP_is_CplLk and not MaxPayloadSize_Exceeded)
;
---------------------------------------------------
--
-- Synchronous Registered: TLP_Header_Resolution
--
FSM_TLP_Header_Resolution:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
FSM_TLP_Cnt <= TK_RST;
TLP_Payload_Address_i <= (OTHERS => '1');
MWr_on_Pool <= '0';
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
trn_rdst_rdy_n_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
-- States transition
case FSM_TLP_Cnt is
when TK_RST =>
FSM_TLP_Cnt <= TK_Idle;
trn_rdst_rdy_n_i <= '1';
when TK_Idle =>
trn_rdst_rdy_n_i <= '0';
if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
then
FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="11"
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
then
FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
elsif trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
then
FSM_TLP_Cnt <= TK_CplD_Hdr_C;
else
FSM_TLP_Cnt <= TK_Idle;
end if;
when TK_MWr_3Hdr_C =>
trn_rdst_rdy_n_i <= '0';
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
elsif trn_rsrc_rdy_n='1' then
FSM_TLP_Cnt <= TK_MWr_3Hdr_C;
else
FSM_TLP_Cnt <= TK_Body;
end if;
when TK_MWr_4Hdr_C =>
trn_rdst_rdy_n_i <= '0';
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
elsif trn_rsrc_rdy_n='1' then
FSM_TLP_Cnt <= TK_MWr_4Hdr_C;
else
FSM_TLP_Cnt <= TK_Body; -- TK_MWr_4Hdr_D;
end if;
when TK_Cpld_Hdr_C =>
trn_rdst_rdy_n_i <= '0';
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
elsif trn_rsrc_rdy_n='1' then
FSM_TLP_Cnt <= TK_Cpld_Hdr_C;
else
FSM_TLP_Cnt <= TK_Body;
end if;
when TK_Body =>
if trn_reof_n='0' and trn_reof_n_r1='1' then -- falling edge
FSM_TLP_Cnt <= TK_Idle;
trn_rdst_rdy_n_i <= '0';
else
FSM_TLP_Cnt <= TK_Body;
trn_rdst_rdy_n_i <= ((MWr_on_Pool or CplD_on_Pool_i) and Pool_wrBuf_full)
or ((MWr_on_EB or CplD_on_EB_i) and Link_Buf_full)
;
end if;
when OTHERS =>
FSM_TLP_Cnt <= TK_RST;
end case;
-- MWr_on_Pool
case FSM_TLP_Cnt is
when TK_RST =>
MWr_on_Pool <= '0';
MWr_on_EB <= '0';
when TK_Idle =>
if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
and trn_rd(C_TLP_FMT_BIT_TOP) = '1'
and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="00"
then
MWr_on_Pool <= not trn_rbar_hit_n(CINT_DDR_SPACE_BAR);
MWr_on_EB <= not trn_rbar_hit_n(CINT_FIFO_SPACE_BAR);
else
MWr_on_Pool <= MWr_on_Pool;
MWr_on_EB <= MWr_on_EB;
end if;
when OTHERS =>
MWr_on_Pool <= MWr_on_Pool;
MWr_on_EB <= MWr_on_EB;
end case;
-- CplD_on_Pool
case FSM_TLP_Cnt is
when TK_RST =>
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
when TK_Idle =>
CplD_on_Pool_i <= '0';
CplD_on_EB_i <= '0';
when TK_CplD_Hdr_C =>
-- if trn_rsof_n='0' and trn_rsrc_rdy_n='0'
-- and trn_rd(C_TLP_FMT_BIT_TOP downto C_TLP_FMT_BIT_BOT) ="10"
-- and trn_rd(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1) ="01"
-- then
CplD_on_Pool_i <= not trn_rd(C_CPLD_TAG_BIT_TOP) and not trn_rd(C_CPLD_TAG_BIT_TOP-1);
CplD_on_EB_i <= not trn_rd(C_CPLD_TAG_BIT_TOP) and trn_rd(C_CPLD_TAG_BIT_TOP-1);
-- else
-- CplD_on_Pool_i <= CplD_on_Pool_i;
-- CplD_on_EB_i <= CplD_on_EB_i;
-- end if;
when OTHERS =>
CplD_on_Pool_i <= CplD_on_Pool_i;
CplD_on_EB_i <= CplD_on_EB_i;
end case;
-- CplD_Tag
case FSM_TLP_Cnt is
when TK_RST =>
CplD_Tag_i <= (OTHERS => '1');
-- when TK_Idle =>
-- CplD_Tag_i <= CplD_Tag_i;
when TK_CplD_Hdr_C =>
-- if trn_reof_n='0' then
-- CplD_Tag_i <= (OTHERS => '1');
-- els
if trn_rsrc_rdy_n='0' -- and trn_rdst_rdy_n='0'
then
CplD_Tag_i <= trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT);
else
CplD_Tag_i <= CplD_Tag_i;
end if;
when OTHERS =>
CplD_Tag_i <= CplD_Tag_i;
end case;
end if;
end process;
---------------------------------------------------
--
-- Synchronous Registered: CplD_is_the_Last
--
Syn_Calc_CplD_is_the_Last:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
CplD_is_the_Last_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n='0' and trn_rsrc_rdy_n='0' then
if trn_rd(C_TLP_TYPE_BIT_TOP-1)= '1'
and (trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2)=trn_rd(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)
or trn_rd(1 downto 0)=CONV_STD_LOGIC_VECTOR(1, 2)) -- Zero-length
then
CplD_is_the_Last_i <= '1';
else
CplD_is_the_Last_i <= '0';
end if;
else
CplD_is_the_Last_i <= CplD_is_the_Last_i;
end if;
end if;
end process;
---------------------------------------------------
--
-- Synchronous Delay: FSM_TLP_Cnt
--
SynDelay_FSM_TLP_Cnt:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
FSM_TLP_Cnt_r1 <= FSM_TLP_Cnt;
end if;
end process;
---- --------------------------------------------------------------------------
--
-- TLP_Address_sig <= '0' & trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
--
---------------------------------------------------------------------------------------
---- Calculates the Address-Length combination carry-in
-- TLP_Calc_CarryIn_ALC:
-- process ( trn_clk, trn_reset_n)
-- begin
-- if trn_reset_n = '0' then
-- CarryIn_ALC <= (OTHERS =>'0');
-- elsif trn_clk'event and trn_clk = '1' then
-- CarryIn_ALC <= ('0'& TLP_DW_Length_i) + TLP_Address_sig;
-- end if;
-- end process;
--
--
-- ---------------------------------------------------
-- --
-- -- Synchronous Registered: Tlp_straddles_4KB
-- --
-- FSM_Output_Tlp_straddles_4KB:
-- process ( trn_clk, trn_reset_n)
-- begin
-- if trn_reset_n = '0' then
-- Tlp_straddles_4KB_i <= '0';
--
-- elsif trn_clk'event and trn_clk = '1' then
--
-- case FSM_TLP_Cnt_r1 is
--
-- when TK_RST =>
-- Tlp_straddles_4KB_i <= '0';
--
-- when TK_MWr_3Hdr_C =>
-- if Tlp_has_4KB_i='1'
-- and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- then
-- Tlp_straddles_4KB_i <= '1';
-- else
-- Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
-- end if;
--
-- when TK_MWr_4Hdr_D =>
-- if Tlp_has_4KB_i='1'
-- and trn_rd(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- /=C_ALL_ZEROS(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
-- then
-- Tlp_straddles_4KB_i <= '1';
-- else
-- Tlp_straddles_4KB_i <= CarryIn_ALC(C_TLP_FLD_WIDTH_OF_LENG);
-- end if;
--
--
-- when OTHERS =>
-- Tlp_straddles_4KB_i <= Tlp_straddles_4KB_i;
--
-- end case;
--
-- end if;
-- end process;
--
-- ---------------------------------------------------------
-- To Cpl/D channel as indicator when ReqID matched
--
TLP_ReqID_Matched:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
Req_ID_Match_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rd(C_CPLD_REQID_BIT_TOP downto C_CPLD_REQID_BIT_BOT)=localID then
Req_ID_Match_i <= '1';
else
Req_ID_Match_i <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------
-- To Cpl/D channel as indicator when us Tag_Descriptor matched
--
TLP_usDexTag_Matched:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
usDex_Tag_Matched_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag then
usDex_Tag_Matched_i <= '1';
else
usDex_Tag_Matched_i <= '0';
end if;
end if;
end process;
-- ------------------------------------------------------------
-- To Cpl/D channel as indicator when ds Tag_Descriptor matched
--
TLP_dsDexTag_Matched:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
dsDex_Tag_Matched_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rd(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag then
dsDex_Tag_Matched_i <= '1';
else
dsDex_Tag_Matched_i <= '0';
end if;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | 55316bac7e5bf0c0e837de4c6af187a1 | 0.482105 | 3.052 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/adau1761.vhd | 2 | 3,959 | ----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Create Date: 19:23:40 01/06/2014
-- Module Name: adau1761 - Behavioral
-- Description: Implement a Line in => I2S => FPGA => I2S => Headphones
-- using the ADAU1761 codec
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library unisim;
use unisim.vcomponents.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity adau1761 is
Port ( clk_100 : in STD_LOGIC;
clk_48_o :out STD_LOGIC;
AC_ADR0 : out STD_LOGIC;
AC_ADR1 : out STD_LOGIC;
AC_GPIO0 : out STD_LOGIC; -- I2S MISO
AC_GPIO1 : in STD_LOGIC; -- I2S MOSI
AC_GPIO2 : in STD_LOGIC; -- I2S_bclk
AC_GPIO3 : in STD_LOGIC; -- I2S_LR
AC_MCLK : out STD_LOGIC;
AC_SCK : out STD_LOGIC;
new_sample : out std_logic;
AUDIO_OUT_L : out STD_LOGIC_VECTOR(23 downto 0);
AUDIO_OUT_R : out STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_L : in STD_LOGIC_VECTOR(23 downto 0);
AUDIO_IN_R : in STD_LOGIC_VECTOR(23 downto 0);
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AC_SDA : inout STD_LOGIC;
sw : in STD_LOGIC_VECTOR(7 downto 0)
);
end adau1761;
architecture Behavioral of adau1761 is
COMPONENT adau1761_izedboard
PORT(
clk_48 : IN std_logic;
AC_GPIO1 : IN std_logic;
AC_GPIO2 : IN std_logic;
AC_GPIO3 : IN std_logic;
hphone_l : IN std_logic_vector(23 downto 0);
hphone_r : IN std_logic_vector(23 downto 0);
AC_SDA_I : IN std_logic;
AC_SDA_O : OUT std_logic;
AC_SDA_T : OUT std_logic;
--AC_SDA : INOUT std_logic;
AC_ADR0 : OUT std_logic;
AC_ADR1 : OUT std_logic;
AC_GPIO0 : OUT std_logic;
AC_MCLK : OUT std_logic;
AC_SCK : OUT std_logic;
line_in_l : OUT std_logic_vector(23 downto 0);
line_in_r : OUT std_logic_vector(23 downto 0);
new_sample: out std_logic;
sw : in std_logic_vector(1 downto 0);
active : out std_logic_vector(1 downto 0)
);
END COMPONENT;
component clocking
port(
CLK_100 : in std_logic;
CLK_48 : out std_logic;
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
signal clk_48 : std_logic;
signal sw_synced : std_logic_vector(7 downto 0);
signal active : std_logic_vector(1 downto 0);
constant hi : natural := 23;
begin
process(clk_48)
begin
if rising_edge(clk_48) then
sw_synced <= sw;
end if;
end process;
--i_clocking : clocking port map (
-- CLK_100 => CLK_100,
-- CLK_48 => CLK_48,
-- RESET => '0',
-- LOCKED => open
-- );
clk_divider_2083: entity WORK.ClkDividerN(Behavioral)
generic map(divFactor => 2)
port map(reset => '0',
clkIn => CLK_100,
clkOut => CLK_48);
clk_48_o <= clk_48;
Inst_adau1761_izedboard: adau1761_izedboard PORT MAP(
clk_48 => clk_48,
AC_ADR0 => AC_ADR0,
AC_ADR1 => AC_ADR1,
AC_GPIO0 => AC_GPIO0,
AC_GPIO1 => AC_GPIO1,
AC_GPIO2 => AC_GPIO2,
AC_GPIO3 => AC_GPIO3,
AC_MCLK => AC_MCLK,
AC_SCK => AC_SCK,
AC_SDA_I => AC_SDA_I,
AC_SDA_O => AC_SDA_O,
AC_SDA_T => AC_SDA_T,
--AC_SDA => AC_SDA,
hphone_l => AUDIO_IN_L,
hphone_r => AUDIO_IN_R,
line_in_l => AUDIO_OUT_L,
line_in_r => AUDIO_OUT_R,
new_sample => new_sample,
sw => sw(1 downto 0),
active => active
);
end Behavioral;
| mit | 80fda6510519e76bebb516d08d45ea20 | 0.510735 | 3.059505 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_dverif.vhd | 1 | 6,128 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
ENTITY rd_fifo_256to64_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF rd_fifo_256to64_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
SIGNAL rd_d_sel_d1 : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0):= (OTHERS => '0');
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_d_sel_d1 <= (OTHERS => '0');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF (rd_en_i = '1' AND EMPTY = '0' AND rd_en_d1 = '1') THEN
rd_d_sel_d1 <= rd_d_sel_d1+"1";
END IF;
END IF;
END PROCESS;
pr_r_en <= (AND_REDUCE(rd_d_sel_d1)) AND rd_en_i AND NOT EMPTY;
expected_dout <= rand_num(C_DIN_WIDTH-C_DOUT_WIDTH*conv_integer(rd_d_sel_d1)-1 DOWNTO C_DIN_WIDTH-C_DOUT_WIDTH*(conv_integer(rd_d_sel_d1)+1));
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:rd_fifo_256to64_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 55cf120295133b32bc41c0794bf8c631 | 0.574739 | 3.856514 | false | false | false | false |
peteut/nvc | test/sem/issue225.vhd | 1 | 1,189 | package p1 is
constant c1 : integer := 1;
end package;
package p2 is
constant c2 : integer := 2;
end package;
package p3 is
constant c3 : integer := 3;
end package;
package p4 is
constant c4 : integer := 4;
end package;
package p5 is
constant c5 : integer := 5;
end package;
package p6 is
constant c6 : integer := 6;
end package;
entity issue225 is
use work.p1.all;
end entity issue225;
architecture test of issue225 is
use work.p2.all; -- doesn't work
begin
g1: if true generate
use work.p3.all; -- doesn't work
begin
b1: block
use work.p4.all; -- doesn't work
begin
p1: process
use work.p5.all; -- doesn't work
procedure doit is
use work.p6.all; -- doesn't work
variable x : integer;
begin
x := c1 + c2 + c3 + c4 + c5 + c6;
wait;
end procedure doit;
begin
doit;
end process p1;
end block b1;
end generate g1;
end architecture test;
| gpl-3.0 | 81031faafba45760db9388bcef46031f | 0.501262 | 3.924092 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/axi_iic.vhd | 2 | 13,259 | -------------------------------------------------------------------------------
-- axi_iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: axi_iic.vhd
-- Version: v1.01.b
-- Description:
-- This file is the top level file that contains the IIC AXI
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- - Added function calc_tbuf in iic_control to calculate the TBUF delay
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Fixed the CR#613282 and CR#613486
-- - Release of v1.01.b
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_SMBUS_PMBUS_HOST -- Acts as SMBus/PMBus host when enabled
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
--AXI signals
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- IIC Signals
-- sda_i -- IIC serial data input
-- sda_o -- IIC serial data output
-- sda_t -- IIC seral data output enable
-- scl_i -- IIC serial clock input
-- scl_o -- IIC serial clock output
-- scl_t -- IIC serial clock output enable
-- gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity axi_iic is
generic (
-- FPGA Family Type specification
C_FAMILY : string := "virtex7";
-- Select the target architecture type
-- AXI Parameters
--C_S_AXI_ADDR_WIDTH : integer range 32 to 36 := 32; --9
C_S_AXI_ADDR_WIDTH : integer := 9; --9
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
-- AXI IIC Feature generics
C_IIC_FREQ : integer := 100E3;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 1;
C_S_AXI_ACLK_FREQ_HZ : integer := 25E6;
C_SCL_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_INERTIAL_DELAY : integer := 0; -- delay in nanoseconds
C_SDA_LEVEL : integer := 1; -- delay in nanoseconds
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port (
-- System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic := '1';
iic2intc_irpt : out std_logic;
-- AXI signals
s_axi_awaddr : in std_logic_vector (8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector (3 downto 0);
--((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(8 downto 0);
--(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector (31 downto 0);
--(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- IIC interface signals
sda_i : in std_logic;
sda_o : out std_logic;
sda_t : out std_logic;
scl_i : in std_logic;
scl_o : out std_logic;
scl_t : out std_logic;
gpo : out std_logic_vector(C_GPO_WIDTH-1 downto 0)
);
end entity axi_iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of axi_iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
constant C_NUM_IIC_REGS : integer := 18;
begin
X_IIC: entity axi_iic_v2_0.iic
generic map (
-- System Generics
C_NUM_IIC_REGS => C_NUM_IIC_REGS, -- Number of IIC Registers
--iic Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ, -- default iic Serial 100KHz
C_TEN_BIT_ADR => C_TEN_BIT_ADR, -- [integer]
C_GPO_WIDTH => C_GPO_WIDTH, -- [integer]
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY, -- delay in nanoseconds
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
-- Transmit FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_TX_FIFO_EXIST => TRUE, -- [boolean]
-- Recieve FIFO Generic
-- Removed as user input 10/08/01
-- Software will not be tested without FIFO's
C_RC_FIFO_EXIST => TRUE, -- [boolean]
-- AXI interface generics
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, -- [integer 9]
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH, -- [integer range 32 to 32]
-- Width of the AXI Data Bus (in bits)
C_FAMILY => C_FAMILY, -- [string]
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map
(
-- System signals
S_AXI_ACLK => s_axi_aclk,
S_AXI_ARESETN => s_axi_aresetn,
IIC2INTC_IRPT => iic2intc_iRPT,
-- AXI Interface signals
S_AXI_AWADDR => s_axi_awaddr,
S_AXI_AWVALID => s_axi_awvalid,
S_AXI_AWREADY => s_axi_awready,
S_AXI_WDATA => s_axi_wdata,
S_AXI_WSTRB => s_axi_wstrb,
S_AXI_WVALID => s_axi_wvalid,
S_AXI_WREADY => s_axi_wready,
S_AXI_BRESP => s_axi_bresp,
S_AXI_BVALID => s_axi_bvalid,
S_AXI_BREADY => s_axi_bready,
S_AXI_ARADDR => s_axi_araddr,
S_AXI_ARVALID => s_axi_arvalid,
S_AXI_ARREADY => s_axi_arready,
S_AXI_RDATA => s_axi_rdata,
S_AXI_RRESP => s_axi_rresp,
S_AXI_RVALID => s_axi_rvalid,
S_AXI_RREADY => s_axi_rready,
-- IIC Bus Signals
SDA_I => sda_i,
SDA_O => sda_o,
SDA_T => sda_t,
SCL_I => scl_i,
SCL_O => scl_o,
SCL_T => scl_t,
GPO => gpo
);
end architecture RTL;
| gpl-3.0 | 44b8ea1a4e4109355bf0a729b54c8bbb | 0.4394 | 4.186612 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_rst_M_AXI_GP1_ACLK_100M_0/sim/cpu_rst_M_AXI_GP1_ACLK_100M_0.vhd | 1 | 5,869 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY cpu_rst_M_AXI_GP1_ACLK_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_rst_M_AXI_GP1_ACLK_100M_0;
ARCHITECTURE cpu_rst_M_AXI_GP1_ACLK_100M_0_arch OF cpu_rst_M_AXI_GP1_ACLK_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_rst_M_AXI_GP1_ACLK_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END cpu_rst_M_AXI_GP1_ACLK_100M_0_arch;
| gpl-3.0 | 75e16e0becef0f50ae9c6947cef83734 | 0.705742 | 3.535542 | false | false | false | false |
peteut/nvc | test/simp/issue321.vhd | 2 | 798 | entity TEST_NG is
end TEST_NG;
architecture MODEL of TEST_NG is
function MAX(A,B:integer) return integer is begin
if (A > B) then return A;
else return B;
end if;
end function;
function CALC_DATA_SIZE(WIDTH:integer) return integer is
variable value : integer;
begin
value := 0;
-- Crashed here as result of ** was real
while (2**(value) < WIDTH) loop
value := value + 1;
end loop;
return value;
end function;
constant T_DATA_WIDTH : integer := 12;
constant M_DATA_WIDTH : integer := 23;
constant BUF_DATA_BITS : integer := MAX(T_DATA_WIDTH, M_DATA_WIDTH);
constant BUF_DATA_BIT_SIZE : integer := CALC_DATA_SIZE(BUF_DATA_BITS);
begin
end;
| gpl-3.0 | 24ad94f50109894b3755f27e722d6abd | 0.577694 | 3.677419 | false | true | false | false |
UnofficialRepos/OSVVM | ScoreboardPkg_slv.vhd | 1 | 2,387 | --
-- File Name: ScoreBoardPkg_slv.vhd
-- Design Unit Name: ScoreBoardPkg_slv
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Instance of Generic Package ScoreboardGenericPkg for std_logic_vector
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 04/2022 2022.04 Replaced to_hstring with to_hxstring
-- 10/2020 2020.10 Replaced STD_MATCH for std_logic family with AlertLogPkg.MetaMatch
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Released as part of OSVVM library
-- 08/2014 2013.08 Updated interface for Match and to_string
-- 08/2012 2012.08 Generic Instance of ScoreboardGenericPkg
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TextUtilPkg.all ;
package ScoreBoardPkg_slv is new work.ScoreboardGenericPkg
generic map (
ExpectedType => std_logic_vector,
ActualType => std_logic_vector,
-- Match => std_match, -- "=", [std_logic_vector, std_logic_vector return boolean]
Match => work.AlertLogPkg.MetaMatch, -- "=", [std_logic_vector, std_logic_vector return boolean]
expected_to_string => to_hxstring, -- [std_logic_vector return string]
actual_to_string => to_hxstring -- [std_logic_vector return string]
) ;
| artistic-2.0 | 45133d53bb18752d481074710e1f6858 | 0.651026 | 3.644275 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_out/simulation/weight_out_tb.vhd | 1 | 4,334 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: weight_out_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY weight_out_tb IS
END ENTITY;
ARCHITECTURE weight_out_tb_ARCH OF weight_out_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
weight_out_synth_inst:ENTITY work.weight_out_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-2-clause | 6b06bdfb370501d89976322498a0b1d0 | 0.620212 | 4.660215 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_rng.vhd | 1 | 3,905 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY k7_mBuf_128x72_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF k7_mBuf_128x72_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 036eeca091c4fd425d0721ac928834d5 | 0.638156 | 4.286498 | false | false | false | false |
peteut/nvc | test/regress/issue352.vhd | 1 | 897 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
-- use ieee.numeric_std.all;
-- use ieee.std_logic_unsigned.all;
entity issue352 is
end entity;
architecture arch of issue352 is
signal FixRealKCM_F400_uid2_Rtemp : std_logic_vector(4 downto 0) := "11111";
signal R :std_logic_vector(5 downto 0);
function check_dims(x : unsigned) return unsigned is
begin
assert x'low >= unsigned'low;
assert x'high <= unsigned'high;
return x;
end function;
begin
-- R <= "000000" - (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0));
R <= std_logic_vector(unsigned'(unsigned'("00000") - check_dims(unsigned (FixRealKCM_F400_uid2_Rtemp(4) & FixRealKCM_F400_uid2_Rtemp(4 downto 0)))));
process is
begin
wait for 1 ns;
assert R = "000001";
wait;
end process;
end architecture;
| gpl-3.0 | d5de96de4aa08769addd5694defca663 | 0.657748 | 3.158451 | false | false | false | false |
peteut/nvc | test/parse/cond1.vhd | 2 | 673 | package cond1 is
`if TOOL_NAME = "false" then
`error "Should not be here"
constant d : integer := 1;
`else
constant c : integer := 1;
`end if
`warning "this is a warning"
`if TOOL_NAME = "nvc" then
`warning "Using nvc"
`end if
`if not (TOOL_TYPE = "SIMULATION") then
`error "Should not be here"
`end if
`if TOOL_TYPE /= "SYNTHESIS" and TOOL_NAME = "nvc" then
`warning "correct"
`end if
`if VHDL_VERSION = "1993" then
`warning "VHDL version is correct"
`end if
end package;
package cond2 is
`if FOO = "bar" then
`end
`if TOOL_NAME = "nvc" then
-- Unterminated
end package
| gpl-3.0 | a4d7883dfeee1bba6e5608d619c2500f | 0.583952 | 3.38191 | false | false | false | false |
peteut/nvc | test/regress/issue143.vhd | 2 | 1,731 | package access_field_through_function_pkg is
type record_t is record
field : integer;
end record;
type protected_t is protected
function fun return record_t;
end protected;
function fun return record_t;
function fun(param : integer) return record_t;
function access_field_fun1 return integer;
function access_field_fun2 return integer;
function access_field_fun3 return integer;
end package;
package body access_field_through_function_pkg is
type protected_t is protected body
function fun return record_t is
begin
return (field => 0);
end function;
end protected body;
function fun return record_t is
begin
return (field => 0);
end function;
function fun(param : integer) return record_t is
begin
return (field => param);
end function;
function access_field_fun1 return integer is
begin
return fun.field; -- <-- does not work
end function;
function access_field_fun2 return integer is
variable x : integer := 10;
begin
return fun(x).field; -- <-- works
end function;
function access_field_fun3 return integer is
variable prot : protected_t;
begin
return prot.fun.field; -- <-- does not work
end function;
end package body;
-------------------------------------------------------------------------------
entity issue143 is
end entity;
use work.access_field_through_function_pkg.all;
architecture test of issue143 is
begin
process is
variable x : integer := 4;
begin
assert fun.field = 0;
assert fun(x).field = 4;
assert access_field_fun1 = 0;
assert access_field_fun2 = 10;
assert access_field_fun3 = 0;
wait;
end process;
end architecture;
| gpl-3.0 | 1de5f93f6a9e4f479e023634ecbc8584 | 0.651069 | 4.092199 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/DMA_Calculate.vhd | 1 | 35,902 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_Calculate is
port (
-- Downstream Registers from MWr Channel
DMA_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : IN std_logic;
BDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : IN std_logic;
Leng_Lo7b_True : IN std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : OUT std_logic;
DMA_Snout_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : OUT std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Only for downstream channel
DMA_PA_Snout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : OUT std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Engine control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : OUT std_logic; -- No more block(s) of Max_Size
ThereIs_Snout : OUT std_logic; -- 1st packet before Body blocks
ThereIs_Body : OUT std_logic; -- Block(s) of Max_Size
ThereIs_Tail : OUT std_logic; -- Last packet with size less than Max_Size
ThereIs_Dex : OUT std_logic; -- Not the last descriptor
HA64bit : OUT std_logic; -- Host Address is 64-bit
Addr_Inc : OUT std_logic; -- Peripheral Address increase token
-- FSM indicators
State_Is_LoadParam : IN std_logic;
State_Is_Snout : IN std_logic;
State_Is_Body : IN std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : IN std_logic_vector(2 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
end entity DMA_Calculate;
architecture Behavioral of DMA_Calculate is
-- Significant bits from the MaXSiZe parameter
signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Signals masked by MaxSize
signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Alias
signal Lo_Leng_Left_Msk_is_True : std_logic;
signal Lo_Leng_Mid_Msk_is_True : std_logic;
signal Lo_Leng_Right_Msk_is_True : std_logic;
-- Masked values of HA and Length
signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Indicates whether the DMA_PA is already accepted
signal PA_is_taken : std_logic;
-- Calculation for the PA of the next DMA, if UPA bit = 0
signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eventual PA parameter for the current DMA transaction
signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, only for better timing
signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
-- DMA parameters from the register module
signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- delay
signal State_Is_Snout_r1 : std_logic;
signal State_Is_Body_r1 : std_logic;
-- from control word
signal Dex_is_Last : std_logic;
signal Engine_Ends : std_logic;
-- Major FSM control signals
signal ThereIs_Snout_i : std_logic;
signal ThereIs_Body_i : std_logic;
signal ThereIs_Tail_i : std_logic;
signal Snout_Only : std_logic;
signal ThereIs_Dex_i : std_logic;
signal No_More_Bodies_i : std_logic;
-- Address/Length combination
signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Compressed ALc
-- ALc_B bit means the ALc has carry in, making an extra Body block.
signal ALc_B : std_logic;
signal ALc_B_wire : std_logic;
-- ALc_T bit means the ALc has trailer, making a final Tail block.
signal ALc_T : std_logic;
signal ALc_T_wire : std_logic;
-- Compressed Length
-- Leng_Two bit means Length >= 2 Max_Size.
signal Leng_Two : std_logic;
-- Leng_One bit means Length >= 1 Max_Size.
signal Leng_One : std_logic;
-- Leng_nint bit means Length is not integral of Max_Sizes.
signal Leng_nint : std_logic;
signal Length_analysis : std_logic_vector(2 downto 0);
signal Snout_Body_Tail : std_logic_vector(2 downto 0);
-- Byte counter
signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic
signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0);
-- Remote & Local Address variable
signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0);
signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- BDA parameter is buffered for FSM module
signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal BDA_is_64b_fsm_i : std_logic;
-- Token bits out of Control word
signal HA64bit_i : std_logic;
signal Addr_Inc_i : std_logic;
signal use_PA : std_logic;
-- for better timing
signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
--
signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- for better timing
signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
begin
-- Partition indicators
No_More_Bodies <= No_More_Bodies_i ;
ThereIs_Snout <= ThereIs_Snout_i ;
ThereIs_Body <= ThereIs_Body_i ;
ThereIs_Tail <= ThereIs_Tail_i ;
ThereIs_Dex <= ThereIs_Dex_i ;
HA64bit <= HA64bit_i ;
Addr_Inc <= Addr_Inc_i ;
--
DMA_PA_Loaded <= DMA_PA_Loaded_i ;
DMA_PA_Var <= DMA_PA_Var_i ;
DMA_HA_Var <= DMA_HA_Var_i ;
DMA_BDA_fsm <= DMA_BDA_fsm_i ;
BDA_is_64b_fsm <= BDA_is_64b_fsm_i;
-- Only for downstream channel
DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number <= DMA_BAR_Number_i;
-- different lengths
DMA_Snout_Length <= DMA_Snout_Length_i ;
DMA_Body_Length <= Max_TLP_Size ;
DMA_Tail_Length <= DMA_Tail_Length_i ;
-- Register stubs
DMA_PA_i <= DMA_PA;
DMA_HA_i <= DMA_HA;
DMA_BDA_i <= DMA_BDA;
DMA_Length_i <= DMA_Length;
DMA_Control_i <= DMA_Control;
-- ---------------------------------------------------------------
-- Parameters should be captured by the start/start2 and be kept
-- in case Pause command comes.
--
Syn_Param_Capture:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Addr_Inc_i <= '0';
use_PA <= '0';
Dex_is_Last <= '0';
Engine_Ends <= '1';
DMA_BAR_Number_i <= (OTHERS=>'0');
DMA_BDA_fsm_i <= (OTHERS=>'0');
BDA_is_64b_fsm_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start ='1' or DMA_Start2 ='1' then
Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT);
DMA_BDA_fsm_i <= DMA_BDA_i ;
BDA_is_64b_fsm_i <= BDA_is_64b ;
else
Addr_Inc_i <= Addr_Inc_i ;
use_PA <= use_PA ;
Dex_is_Last <= Dex_is_Last ;
Engine_Ends <= Engine_Ends ;
DMA_BAR_Number_i <= DMA_BAR_Number_i;
DMA_BDA_fsm_i <= DMA_BDA_fsm_i ;
BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i ;
end if;
end if;
end process;
-- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
-- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
-- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
-- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
-- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI);
-- Means there is consecutive descriptor(s)
ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends;
-- ---------------------------------------------------------------
-- PA_i selection
--
Syn_Calc_DMA_PA:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_current <= (Others=>'0');
-- DMA_BAR_Number_i <= (Others=>'0');
PA_is_taken <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken='0' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken='0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then
DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next;
PA_is_taken <= '1';
else
DMA_PA_current <= DMA_PA_current;
if DMA_Start='0' and DMA_Start2='0' then
PA_is_taken <= '0';
else
PA_is_taken <= PA_is_taken;
end if;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- PA_next Calculation
--
Syn_Calc_DMA_PA_next:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_next <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken='0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi
+ Carry_PA_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
end if;
elsif DMA_Start2 = '1' and PA_is_taken='0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi
+ Carry_PAx_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_next;
end if;
else
DMA_PA_next <= DMA_PA_next;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PA_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PA_plus_Leng:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PA_plus_Leng <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PAx_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PAx_plus_Leng:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PAx_plus_Leng <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PA_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PA_Hi:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PA_Hi <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PAx_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PAx_Hi:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PAx_Hi <= (Others=>'0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left;
DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid;
DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
-- -----------------------------------------------------------------------------------------------------------------------------------
Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk =C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
-- ----------------------------------------------------------
-- Synchronous Register: Leng_Info(Compressed Length Information)
---
Syn_Calc_Parameter_Leng_Info:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Two <= '0';
Leng_One <= '0';
Leng_nint <= '0';
elsif dma_clk'event and dma_clk = '1' then
Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True;
Leng_One <= Lo_Leng_Mid_Msk_is_True;
Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True;
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
else '1';
ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)
else '1';
-- -----------------------------------------------------------------------------------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Register: ALc (Address-Length combination)
---
Syn_Calc_Parameter_ALc:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ALc <= (Others=>'0');
ALc_B <= '0';
ALc_T <= '0';
elsif dma_clk'event and dma_clk = '1' then
ALc <= DMA_Length_Msk + DMA_HA_Msk;
ALc_B <= ALc_B_wire;
ALc_T <= ALc_T_wire;
end if;
end process;
-- concatenation of the Length information
Length_analysis <= Leng_Two & Leng_One & Leng_nint;
-- -------------------------------------------
-- Analysis on the DMA division
-- truth-table expressions
--
Comb_S_B_T:
process (
Length_analysis
, ALc_B
, ALc_T
)
begin
case Length_analysis is
-- Zero-length DMA, nothing to send
when "000" =>
Snout_Body_Tail <= "000";
-- Length < Max_Size. Always Snout and never Body, Tail depends on ALc.
when "001" =>
Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T);
-- Length = Max_Size. Division depends only on ALc-Tail.
when "010" =>
Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T;
-- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail.
-- Body = Leng_Two or not ALc_T
when "100" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
when "110" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
-- Length = (1+d) Max_Size, 0<d<1. Always Snout. Body and Tail copy ALc.
when "011" =>
Snout_Body_Tail <= '1' & ALc_B & ALc_T;
-- Length = (k+1+d) Max_Size, k>=1, 0<d<1. Always Snout and Body. Tail copies ALc-Tail.
-- Body = Leng_Two or ALc_B
when "101" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
when "111" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
-- dealt as zero-length DMA
when Others =>
Snout_Body_Tail <= "000";
end case;
end process;
-- -----------------------------------------------
-- Synchronous Register:
-- ThereIs_Snout
-- ThereIs_Body
-- ThereIs_Tail
--
Syn_Calc_Parameters_SBT:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Snout_i <= '0';
ThereIs_Body_i <= '0';
ThereIs_Tail_i <= '0';
Snout_Only <= '0';
elsif dma_clk'event and dma_clk = '1' then
ThereIs_Snout_i <= Snout_Body_Tail(2);
ThereIs_Body_i <= Snout_Body_Tail(1);
ThereIs_Tail_i <= Snout_Body_Tail(0);
Snout_Only <= ALc_T and not Snout_Body_Tail(0);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA_gap
--
Syn_Calc_HA_gap:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA_gap <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
HA_gap <= Max_TLP_Size - DMA_HA_Msk;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Snout_Carry
--
FSM_Calc_DMA_PA_Snout_Carry:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Snout_Carry <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Body_Carry
--
FSM_Calc_DMA_PA_Body_Carry:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Body_Carry <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size;
end if;
end process;
-- ------------------------------------------------------------------
-- Synchronous Register: Length_minus
--
Sync_Calc_Length_minus:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
Length_minus <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
Length_minus <= DMA_Length_i - Max_TLP_Size;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_BC_Carry
--
FSM_Calc_DMA_BC_Carry:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_BC_Carry <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size;
end if;
end process;
-- --------------------------------------------
-- Synchronous reg: DMA_Snout_Length
-- DMA_Tail_Length
--
FSM_Calc_DMA_Snout_Tail_Lengths:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Snout_Length_i <= (OTHERS =>'0');
DMA_Tail_Length_i <= (OTHERS =>'0');
raw_Tail_Length <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0);
if State_Is_LoadParam ='1' then
raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
+ DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
if Snout_Only='1' then
DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00";
else
DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk;
end if;
else
DMA_Snout_Length_i <= DMA_Snout_Length_i;
raw_Tail_Length <= raw_Tail_Length;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous Delays:
-- State_Is_Snout_r1
-- State_Is_Body_r1
--
Syn_Delay_State_is_x:
process ( dma_clk )
begin
if dma_clk'event and dma_clk = '1' then
State_Is_Snout_r1 <= State_Is_Snout;
State_Is_Body_r1 <= State_Is_Body;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Carry32
--
FSM_Calc_DMA_HA_Carry32:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Carry32 <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp
elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) &
(DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)
) + mxsz_mid;
else
DMA_HA_Carry32 <= DMA_HA_Carry32;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Var
--
FSM_Calc_DMA_HA_Var:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Var_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp
elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then
-- elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
+ DMA_HA_Carry32(C_DBUS_WIDTH/2);
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
& (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right))
+ mxsz_mid;
DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (Others => '0'); -- MaxSize aligned
else
DMA_HA_Var_i <= DMA_HA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA64bit
--
FSM_Calc_HA64bit:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA64bit_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
HA64bit_i <= HA_is_64b;
elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then
HA64bit_i <= '1';
else
HA64bit_i <= HA64bit_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Var
--
FSM_Calc_DMA_PA_Var:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Var_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if Addr_Inc_i='1' and ThereIs_Snout_i='1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0)
+ HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY);
else
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
end if;
elsif State_Is_Snout_r1 = '1' then
---- elsif State_Is_Snout = '1' then
if Addr_Inc_i= '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Snout_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
elsif State_Is_Body_r1 = '1' then
---- elsif State_Is_Body = '1' then
if Addr_Inc_i= '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Body_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Loaded_i
--
FSM_Calc_DMA_PA_Loaded_i:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Loaded_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
else
DMA_PA_Loaded_i <= DMA_PA_Loaded_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: DMA_Byte_Counter
---
FSM_Calc_DMA_Byte_Counter:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Byte_Counter <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if ALc_B='0' and ALc_T='1' then
DMA_Byte_Counter <= Length_minus;
else
DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00";
end if;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY)
- DMA_BC_Carry(CBIT_CARRY);
DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT);
else
DMA_Byte_Counter <= DMA_Byte_Counter;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: No_More_Bodies
---
FSM_Calc_No_More_Bodies:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
No_More_Bodies_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
No_More_Bodies_i <= not ThereIs_Body_i;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left)=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid)/=C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
then
No_More_Bodies_i <= '1';
else
No_More_Bodies_i <= '0';
end if;
else
No_More_Bodies_i <= No_More_Bodies_i;
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: Param_Max_Cfg
--
Syn_Config_Param_Max_Cfg:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then -- 0x0080 Bytes
mxsz_left <= "111110"; -- 6 bits
mxsz_mid <= "000001"; -- 6 bits
mxsz_right <= "000000"; -- 6 bits
elsif dma_clk'event and dma_clk = '1' then
case Param_Max_Cfg is
when "000" => -- 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
when "001" => -- 0x0100 Bytes
mxsz_left <= "111100";
mxsz_mid <= "000010";
mxsz_right <= "000001";
when "010" => -- 0x0200 Bytes
mxsz_left <= "111000";
mxsz_mid <= "000100";
mxsz_right <= "000011";
when "011" => -- 0x0400 Bytes
mxsz_left <= "110000";
mxsz_mid <= "001000";
mxsz_right <= "000111";
when "100" => -- 0x0800 Bytes
mxsz_left <= "100000";
mxsz_mid <= "010000";
mxsz_right <= "001111";
when "101" => -- 0x1000 Bytes
mxsz_left <= "000000";
mxsz_mid <= "100000";
mxsz_right <= "011111";
when Others => -- as 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
end case;
end if;
end process;
Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT);
end architecture Behavioral;
| gpl-2.0 | 5d2b5a331ab9819ff81a27986cbf21fb | 0.491811 | 3.408526 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_rng.vhd | 1 | 3,899 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY counter_fifo_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF counter_fifo_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 623d033aafc87080f25280b82db2e6b5 | 0.638369 | 4.366181 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_13/lab13_2/lab13_2.vhd | 1 | 680 | library ieee;
use ieee.std_logic_1164.all;
entity D_FF is
PORT ( D: in std_logic;
CLK: in std_logic;
CLR: in std_logic;
PRE: in std_logic;
QN: out std_logic;
Q: out std_logic);
end D_FF;
Architecture Arch_D_FF of D_FF is
begin
FF:process(CLK,PRE,CLR)
begin
if (CLR='0') then
Q<='0';
QN<='1';
else
if (PRE='0') then
Q<='1';
QN<='0';
else
if (CLK='1') and CLK'EVENT then
Q<=D;
QN<=not(D);
end if;
end if;
end if;
end process FF;
end Arch_D_FF; | gpl-2.0 | 2d022d342ba207c62d4c69a2b79206fb | 0.422059 | 3.300971 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/blk_mem_gen_v7_3/example_design/blk_mem_gen_v7_3_prod.vhd | 1 | 10,117 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 00
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 16
-- C_READ_DEPTH_A : 16
-- C_ADDRA_WIDTH : 4
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 16
-- C_READ_DEPTH_B : 16
-- C_ADDRB_WIDTH : 4
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| bsd-2-clause | 7d3e1799f4a37478ce382633393ffa91 | 0.492438 | 3.769374 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/blk_mem_gen_v7_3/simulation/bmg_stim_gen.vhd | 1 | 7,560 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(3 DOWNTO 0) <= WRITE_ADDR(3 DOWNTO 0);
READ_ADDR_INT(3 DOWNTO 0) <= READ_ADDR(3 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 16 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| bsd-2-clause | 6e1c42f2535cf1742ddf96b477f61b2e | 0.55754 | 3.770574 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_11/lab_11_1_1/altfp_exp0.vhd | 1 | 127,501 | -- megafunction wizard: %ALTFP_EXP%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: ALTFP_EXP
-- ============================================================
-- File Name: altfp_exp0.vhd
-- Megafunction Name(s):
-- ALTFP_EXP
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
--altfp_exp CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone III" PIPELINE=17 ROUNDING="TO_NEAREST" WIDTH_EXP=8 WIDTH_MAN=23 aclr clk_en clock data nan overflow result underflow zero
--VERSION_BEGIN 9.0SP2 cbx_altfp_exp 2008:09:22:00:13:40:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2009:05:07:10:25:28:SJ cbx_lpm_clshift 2008:08:18:00:16:00:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_mult 2008:09:30:18:36:56:SJ cbx_lpm_mux 2009:03:31:01:01:28:SJ cbx_mgl 2009:02:26:16:06:21:SJ cbx_padd 2008:09:04:11:11:31:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END
LIBRARY lpm;
USE lpm.lpm_components.all;
--synthesis_resources = lpm_add_sub 9 lpm_clshift 1 lpm_compare 3 lpm_mult 5 lpm_mux 3 mux21 124 reg 749
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altfp_exp0_altfp_exp_vdg IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '1';
clock : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
nan : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
underflow : OUT STD_LOGIC;
zero : OUT STD_LOGIC
);
END altfp_exp0_altfp_exp_vdg;
ARCHITECTURE RTL OF altfp_exp0_altfp_exp_vdg IS
SIGNAL barrel_shifter_underflow_dffe2_15_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL barrel_shifter_underflow_dffe2_15_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL distance_overflow_dffe2_15_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_0 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_1 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_10 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_2 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_3 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_5 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_6 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_7 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_8 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_b4_bias_dffe_9 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL exp_value_dffe1 : STD_LOGIC_VECTOR(8 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL extra_ln2_dffe_5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_extra_ln2_dffe_5_w_lg_q158w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL fraction_dffe1 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_infinity_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_nan_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL input_is_zero_16_pipes15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_overflow_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL man_prod_dffe14 : STD_LOGIC_VECTOR(61 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL man_round_dffe15 : STD_LOGIC_VECTOR(22 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL nan_dffe16 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL overflow_dffe16 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL result_pipe_dffe16 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL round_up_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe4 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe5 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe6 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe7 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe8 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe9 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe10 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe11 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe12 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe13 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe14 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL sign_dffe15 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_sign_dffe_w_lg_q448w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_sign_dffe_w_lg_q436w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL tbl1_compare_dffe11_4_pipes0 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes1 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes2 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_compare_dffe11_4_pipes3 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL tbl1_tbl2_prod_dffe12 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL tbl3_taylor_prod_dffe12 : STD_LOGIC_VECTOR(30 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL underflow_dffe16 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_0 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_1 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_2 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_3 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL x_fixed_dffe_4 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xf_pre_2_dffe10 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xf_pre_dffe9 : STD_LOGIC_VECTOR(37 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_exp_value_dffe4 : STD_LOGIC_VECTOR(7 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_ln2_prod_dffe7 : STD_LOGIC_VECTOR(45 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL xi_prod_dffe3 : STD_LOGIC_VECTOR(20 DOWNTO 0)
-- synopsys translate_off
:= (OTHERS => '0')
-- synopsys translate_on
;
SIGNAL zero_dffe16 : STD_LOGIC
-- synopsys translate_off
:= '0'
-- synopsys translate_on
;
SIGNAL wire_exp_minus_bias_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_minus_bias_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_minus_bias_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_w_lg_w_result_range442w446w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_dataa : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_add_bias_w_result_range442w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_lg_w_result_range434w437w438w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_result_range434w437w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range434w437w438w439w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_exp_value_man_over_datab : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_man_over_result : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL wire_exp_value_man_over_w_result_range434w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_invert_exp_value_dataa : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_invert_exp_value_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_invert_exp_value_w_result_range130w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_man_round_datab : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_man_round_result : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL wire_one_minus_xf_dataa : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_one_minus_xf_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_x_fixed_minus_xiln2_datab : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_x_fixed_minus_xiln2_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_xf_minus_ln2_datab : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_xf_minus_ln2_result : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_xi_add_one_datab : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_xi_add_one_result : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_rbarrel_shift_result : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL wire_distance_overflow_comp_agb : STD_LOGIC;
SIGNAL wire_tbl1_compare_ageb : STD_LOGIC;
SIGNAL wire_underflow_compare_agb : STD_LOGIC;
SIGNAL wire_man_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_tbl1_tbl2_prod_result : STD_LOGIC_VECTOR (63 DOWNTO 0);
SIGNAL wire_tbl3_taylor_prod_datab : STD_LOGIC_VECTOR (29 DOWNTO 0);
SIGNAL wire_tbl3_taylor_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_xi_ln2_prod_result : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL wire_xi_prod_result : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_table_one_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 31 DOWNTO 0);
SIGNAL wire_table_one_result : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL wire_table_three_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 20 DOWNTO 0);
SIGNAL wire_table_three_result : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL wire_table_two_data_2d : STD_LOGIC_2D(31 DOWNTO 0, 25 DOWNTO 0);
SIGNAL wire_table_two_result : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL wire_cin_to_bias_dataout : STD_LOGIC;
SIGNAL wire_exp_result_mux_prea_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_result_mux_prea_w_lg_dataout557w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_exp_value_b4_biasa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_value_selecta_dataout : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL wire_exp_value_to_compare_muxa_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_exp_value_to_ln2a_dataout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL wire_extra_ln2_muxa_dataout : STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL wire_man_result_muxa_dataout : STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL wire_xf_muxa_dataout : STD_LOGIC_VECTOR(30 DOWNTO 0);
SIGNAL wire_w_lg_man_prod_shifted408w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_w_lg_man_prod_wire407w : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL wire_w_lg_underflow_w554w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range10w35w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range13w37w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range16w39w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range19w41w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range22w43w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range25w45w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range28w47w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_data_all_one_w_range46w119w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range563w565w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range568w570w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range573w575w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range578w580w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range583w585w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range588w590w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range593w594w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range492w494w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range495w497w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range498w500w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range501w503w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range504w506w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range507w509w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range510w512w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range513w515w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range516w518w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range519w521w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range465w467w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range522w524w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range525w527w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range528w530w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range468w470w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range471w473w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range474w476w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range477w479w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range480w482w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range483w485w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range486w488w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_round_wi_range489w491w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_underflow_w554w555w556w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_barrel_shifter_underflow553w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_infinity_wo444w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_nan_wo443w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_input_is_zero_wo445w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_underflow_w455w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_data_not_zero_w_range115w118w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_wo_range402w406w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_underflow_w554w555w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w551w552w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w551w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_w_lg_overflow_w536w537w538w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_barrel_shifter_underflow549w550w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_overflow_w543w544w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_lg_overflow_w536w537w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_barrel_shifter_underflow549w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_distance_overflow447w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_distance_overflow456w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_overflow_w543w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_overflow_w536w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range78w80w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range81w83w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range84w86w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range87w89w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range90w92w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range93w95w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range96w98w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range99w101w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range102w104w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range105w107w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range51w53w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range108w110w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range111w113w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range114w116w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range10w12w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range13w15w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range16w18w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range19w21w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range22w24w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range25w27w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range54w56w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range28w30w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range57w59w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range60w62w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range63w65w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range66w68w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range69w71w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range72w74w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_data_range75w77w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range563w567w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range568w572w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range573w577w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range578w582w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range583w587w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range588w592w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_exp_result_w_range593w595w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range424w426w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range421w423w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range418w420w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_lg_w_man_prod_result_range415w417w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL addr_val_more_than_one : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL barrel_shifter_data : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL barrel_shifter_distance : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL barrel_shifter_underflow : STD_LOGIC;
SIGNAL barrel_shifter_underflow_wi : STD_LOGIC;
SIGNAL distance_overflow : STD_LOGIC;
SIGNAL distance_overflow_val_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL distance_overflow_wi : STD_LOGIC;
SIGNAL exp_bias : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_bias_all_ones_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_data_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_data_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_invert : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_one : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_all_one_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_out_not_zero_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_out : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_result_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL exp_value : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value_wi : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_value_wo : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL exp_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL extra_ln2 : STD_LOGIC;
SIGNAL fraction : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL fraction_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL fraction_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL gnd_w : STD_LOGIC;
SIGNAL guard_bit : STD_LOGIC;
SIGNAL input_is_infinity_wi : STD_LOGIC;
SIGNAL input_is_infinity_wo : STD_LOGIC;
SIGNAL input_is_nan_wi : STD_LOGIC;
SIGNAL input_is_nan_wo : STD_LOGIC;
SIGNAL input_is_zero_wi : STD_LOGIC;
SIGNAL input_is_zero_wo : STD_LOGIC;
SIGNAL ln2_w : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL man_data_not_zero_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_overflow : STD_LOGIC;
SIGNAL man_overflow_wi : STD_LOGIC;
SIGNAL man_overflow_wo : STD_LOGIC;
SIGNAL man_prod_result : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_shifted : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wi : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wire : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_prod_wo : STD_LOGIC_VECTOR (61 DOWNTO 0);
SIGNAL man_result_all_ones : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_result_w : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_round_wi : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL man_round_wo : STD_LOGIC_VECTOR (22 DOWNTO 0);
SIGNAL nan_w : STD_LOGIC;
SIGNAL nan_wi : STD_LOGIC;
SIGNAL nan_wo : STD_LOGIC;
SIGNAL negative_infinity : STD_LOGIC;
SIGNAL one_over_ln2_w : STD_LOGIC_VECTOR (8 DOWNTO 0);
SIGNAL overflow_w : STD_LOGIC;
SIGNAL overflow_wi : STD_LOGIC;
SIGNAL overflow_wo : STD_LOGIC;
SIGNAL positive_infinity : STD_LOGIC;
SIGNAL result_pipe_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL result_pipe_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL result_underflow_w : STD_LOGIC;
SIGNAL round_bit : STD_LOGIC;
SIGNAL round_up : STD_LOGIC;
SIGNAL round_up_wi : STD_LOGIC;
SIGNAL round_up_wo : STD_LOGIC;
SIGNAL shifted_value : STD_LOGIC;
SIGNAL sign_w : STD_LOGIC;
SIGNAL sticky_bits : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL table_one_data : STD_LOGIC_VECTOR (1023 DOWNTO 0);
SIGNAL table_one_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_three_data : STD_LOGIC_VECTOR (671 DOWNTO 0);
SIGNAL table_three_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_three_out_tmp : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL table_two_data : STD_LOGIC_VECTOR (831 DOWNTO 0);
SIGNAL table_two_out : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL table_two_out_tmp : STD_LOGIC_VECTOR (25 DOWNTO 0);
SIGNAL tbl1_compare_wi : STD_LOGIC;
SIGNAL tbl1_compare_wo : STD_LOGIC;
SIGNAL tbl1_tbl2_prod_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl1_tbl2_prod_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl3_taylor_prod_wi : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL tbl3_taylor_prod_wo : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL underflow_compare_val_w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL underflow_w : STD_LOGIC;
SIGNAL underflow_wi : STD_LOGIC;
SIGNAL underflow_wo : STD_LOGIC;
SIGNAL x_fixed : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL xf_pre : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_2_wi : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_2_wo : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_wi : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xf_pre_wo : STD_LOGIC_VECTOR (37 DOWNTO 0);
SIGNAL xi_exp_value : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_exp_value_wi : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_exp_value_wo : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL xi_ln2_prod_wi : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL xi_ln2_prod_wo : STD_LOGIC_VECTOR (45 DOWNTO 0);
SIGNAL xi_prod_wi : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL xi_prod_wo : STD_LOGIC_VECTOR (20 DOWNTO 0);
SIGNAL zero_w : STD_LOGIC;
SIGNAL zero_wi : STD_LOGIC;
SIGNAL zero_wo : STD_LOGIC;
SIGNAL wire_w_data_range78w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range81w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range84w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range87w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range90w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range93w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range96w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range99w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range102w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range105w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range51w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range108w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range111w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range114w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range10w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range13w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range16w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range19w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range22w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range25w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range54w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range28w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range57w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range60w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range63w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range66w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range69w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range72w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_data_range75w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range32w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range34w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range36w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range38w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range40w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range42w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range44w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_all_one_w_range46w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range8w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range11w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range14w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range17w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range20w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range23w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_data_not_zero_w_range26w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range559w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range564w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range569w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range574w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range579w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range584w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_all_one_w_range589w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range561w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range566w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range571w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range576w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range581w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range586w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_out_not_zero_w_range591w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range563w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range568w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range573w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range578w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range583w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range588w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_result_w_range593w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range129w : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range132w : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL wire_w_exp_value_wo_range131w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range49w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range79w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range82w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range85w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range88w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range91w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range94w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range97w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range100w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range103w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range106w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range52w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range109w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range112w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range115w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range55w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range58w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range61w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range64w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range67w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range70w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range73w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_data_not_zero_w_range76w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range424w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range421w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range418w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_result_range415w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_prod_wo_range402w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range463w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range493w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range496w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range499w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range502w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range505w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range508w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range511w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range514w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range517w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range520w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range466w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range523w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range526w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range469w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range472w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range475w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range478w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range481w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range484w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range487w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_result_all_ones_range490w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range492w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range495w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range498w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range501w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range504w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range507w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range510w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range513w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range516w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range519w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range465w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range522w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range525w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range528w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range468w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range471w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range474w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range477w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range480w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range483w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range486w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_man_round_wi_range489w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range413w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range416w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range419w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_sticky_bits_range422w : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL wire_w_xf_pre_2_wo_range183w : STD_LOGIC_VECTOR (30 DOWNTO 0);
SIGNAL wire_w_xf_pre_wo_range177w : STD_LOGIC_VECTOR (30 DOWNTO 0);
COMPONENT lpm_add_sub
GENERIC
(
LPM_DIRECTION : STRING := "DEFAULT";
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "SIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_add_sub"
);
PORT
(
aclr : IN STD_LOGIC := '0';
add_sub : IN STD_LOGIC := '1';
cin : IN STD_LOGIC := 'Z';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
cout : OUT STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT lpm_clshift
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_SHIFTTYPE : STRING := "LOGICAL";
LPM_WIDTH : NATURAL;
LPM_WIDTHDIST : NATURAL;
lpm_type : STRING := "lpm_clshift"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
direction : IN STD_LOGIC := '0';
distance : IN STD_LOGIC_VECTOR(LPM_WIDTHDIST-1 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
underflow : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT lpm_compare
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTH : NATURAL;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_compare"
);
PORT
(
aclr : IN STD_LOGIC := '0';
aeb : OUT STD_LOGIC;
agb : OUT STD_LOGIC;
ageb : OUT STD_LOGIC;
alb : OUT STD_LOGIC;
aleb : OUT STD_LOGIC;
aneb : OUT STD_LOGIC;
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
datab : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
COMPONENT lpm_mult
GENERIC
(
LPM_PIPELINE : NATURAL := 0;
LPM_REPRESENTATION : STRING := "UNSIGNED";
LPM_WIDTHA : NATURAL;
LPM_WIDTHB : NATURAL;
LPM_WIDTHP : NATURAL;
LPM_WIDTHS : NATURAL := 1;
lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "lpm_mult"
);
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
dataa : IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0);
sum : IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
loop0 : FOR i IN 0 TO 61 GENERATE
wire_w_lg_man_prod_shifted408w(i) <= man_prod_shifted(i) AND wire_w_man_prod_wo_range402w(0);
END GENERATE loop0;
loop1 : FOR i IN 0 TO 61 GENERATE
wire_w_lg_man_prod_wire407w(i) <= man_prod_wire(i) AND wire_w_lg_w_man_prod_wo_range402w406w(0);
END GENERATE loop1;
wire_w_lg_underflow_w554w(0) <= underflow_w AND wire_w_lg_barrel_shifter_underflow553w(0);
wire_w_lg_w_data_range10w35w(0) <= wire_w_data_range10w(0) AND wire_w_exp_data_all_one_w_range32w(0);
wire_w_lg_w_data_range13w37w(0) <= wire_w_data_range13w(0) AND wire_w_exp_data_all_one_w_range34w(0);
wire_w_lg_w_data_range16w39w(0) <= wire_w_data_range16w(0) AND wire_w_exp_data_all_one_w_range36w(0);
wire_w_lg_w_data_range19w41w(0) <= wire_w_data_range19w(0) AND wire_w_exp_data_all_one_w_range38w(0);
wire_w_lg_w_data_range22w43w(0) <= wire_w_data_range22w(0) AND wire_w_exp_data_all_one_w_range40w(0);
wire_w_lg_w_data_range25w45w(0) <= wire_w_data_range25w(0) AND wire_w_exp_data_all_one_w_range42w(0);
wire_w_lg_w_data_range28w47w(0) <= wire_w_data_range28w(0) AND wire_w_exp_data_all_one_w_range44w(0);
wire_w_lg_w_exp_data_all_one_w_range46w119w(0) <= wire_w_exp_data_all_one_w_range46w(0) AND wire_w_lg_w_man_data_not_zero_w_range115w118w(0);
wire_w_lg_w_exp_result_w_range563w565w(0) <= wire_w_exp_result_w_range563w(0) AND wire_w_exp_out_all_one_w_range559w(0);
wire_w_lg_w_exp_result_w_range568w570w(0) <= wire_w_exp_result_w_range568w(0) AND wire_w_exp_out_all_one_w_range564w(0);
wire_w_lg_w_exp_result_w_range573w575w(0) <= wire_w_exp_result_w_range573w(0) AND wire_w_exp_out_all_one_w_range569w(0);
wire_w_lg_w_exp_result_w_range578w580w(0) <= wire_w_exp_result_w_range578w(0) AND wire_w_exp_out_all_one_w_range574w(0);
wire_w_lg_w_exp_result_w_range583w585w(0) <= wire_w_exp_result_w_range583w(0) AND wire_w_exp_out_all_one_w_range579w(0);
wire_w_lg_w_exp_result_w_range588w590w(0) <= wire_w_exp_result_w_range588w(0) AND wire_w_exp_out_all_one_w_range584w(0);
wire_w_lg_w_exp_result_w_range593w594w(0) <= wire_w_exp_result_w_range593w(0) AND wire_w_exp_out_all_one_w_range589w(0);
wire_w_lg_w_man_round_wi_range492w494w(0) <= wire_w_man_round_wi_range492w(0) AND wire_w_man_result_all_ones_range490w(0);
wire_w_lg_w_man_round_wi_range495w497w(0) <= wire_w_man_round_wi_range495w(0) AND wire_w_man_result_all_ones_range493w(0);
wire_w_lg_w_man_round_wi_range498w500w(0) <= wire_w_man_round_wi_range498w(0) AND wire_w_man_result_all_ones_range496w(0);
wire_w_lg_w_man_round_wi_range501w503w(0) <= wire_w_man_round_wi_range501w(0) AND wire_w_man_result_all_ones_range499w(0);
wire_w_lg_w_man_round_wi_range504w506w(0) <= wire_w_man_round_wi_range504w(0) AND wire_w_man_result_all_ones_range502w(0);
wire_w_lg_w_man_round_wi_range507w509w(0) <= wire_w_man_round_wi_range507w(0) AND wire_w_man_result_all_ones_range505w(0);
wire_w_lg_w_man_round_wi_range510w512w(0) <= wire_w_man_round_wi_range510w(0) AND wire_w_man_result_all_ones_range508w(0);
wire_w_lg_w_man_round_wi_range513w515w(0) <= wire_w_man_round_wi_range513w(0) AND wire_w_man_result_all_ones_range511w(0);
wire_w_lg_w_man_round_wi_range516w518w(0) <= wire_w_man_round_wi_range516w(0) AND wire_w_man_result_all_ones_range514w(0);
wire_w_lg_w_man_round_wi_range519w521w(0) <= wire_w_man_round_wi_range519w(0) AND wire_w_man_result_all_ones_range517w(0);
wire_w_lg_w_man_round_wi_range465w467w(0) <= wire_w_man_round_wi_range465w(0) AND wire_w_man_result_all_ones_range463w(0);
wire_w_lg_w_man_round_wi_range522w524w(0) <= wire_w_man_round_wi_range522w(0) AND wire_w_man_result_all_ones_range520w(0);
wire_w_lg_w_man_round_wi_range525w527w(0) <= wire_w_man_round_wi_range525w(0) AND wire_w_man_result_all_ones_range523w(0);
wire_w_lg_w_man_round_wi_range528w530w(0) <= wire_w_man_round_wi_range528w(0) AND wire_w_man_result_all_ones_range526w(0);
wire_w_lg_w_man_round_wi_range468w470w(0) <= wire_w_man_round_wi_range468w(0) AND wire_w_man_result_all_ones_range466w(0);
wire_w_lg_w_man_round_wi_range471w473w(0) <= wire_w_man_round_wi_range471w(0) AND wire_w_man_result_all_ones_range469w(0);
wire_w_lg_w_man_round_wi_range474w476w(0) <= wire_w_man_round_wi_range474w(0) AND wire_w_man_result_all_ones_range472w(0);
wire_w_lg_w_man_round_wi_range477w479w(0) <= wire_w_man_round_wi_range477w(0) AND wire_w_man_result_all_ones_range475w(0);
wire_w_lg_w_man_round_wi_range480w482w(0) <= wire_w_man_round_wi_range480w(0) AND wire_w_man_result_all_ones_range478w(0);
wire_w_lg_w_man_round_wi_range483w485w(0) <= wire_w_man_round_wi_range483w(0) AND wire_w_man_result_all_ones_range481w(0);
wire_w_lg_w_man_round_wi_range486w488w(0) <= wire_w_man_round_wi_range486w(0) AND wire_w_man_result_all_ones_range484w(0);
wire_w_lg_w_man_round_wi_range489w491w(0) <= wire_w_man_round_wi_range489w(0) AND wire_w_man_result_all_ones_range487w(0);
wire_w_lg_w_lg_w_lg_underflow_w554w555w556w(0) <= NOT wire_w_lg_w_lg_underflow_w554w555w(0);
wire_w_lg_barrel_shifter_underflow553w(0) <= NOT barrel_shifter_underflow;
wire_w_lg_input_is_infinity_wo444w(0) <= NOT input_is_infinity_wo;
wire_w_lg_input_is_nan_wo443w(0) <= NOT input_is_nan_wo;
wire_w_lg_input_is_zero_wo445w(0) <= NOT input_is_zero_wo;
wire_w_lg_underflow_w455w(0) <= NOT underflow_w;
wire_w_lg_w_man_data_not_zero_w_range115w118w(0) <= NOT wire_w_man_data_not_zero_w_range115w(0);
wire_w_lg_w_man_prod_wo_range402w406w(0) <= NOT wire_w_man_prod_wo_range402w(0);
wire_w_lg_w_lg_underflow_w554w555w(0) <= wire_w_lg_underflow_w554w(0) OR negative_infinity;
wire_w_lg_w551w552w(0) <= wire_w551w(0) OR positive_infinity;
wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w(0) <= wire_w_lg_w_lg_w_lg_overflow_w536w537w538w(0) OR input_is_infinity_wo;
wire_w551w(0) <= wire_w_lg_w_lg_barrel_shifter_underflow549w550w(0) OR nan_w;
wire_w_lg_w_lg_w_lg_overflow_w536w537w538w(0) <= wire_w_lg_w_lg_overflow_w536w537w(0) OR input_is_zero_wo;
wire_w_lg_w_lg_barrel_shifter_underflow549w550w(0) <= wire_w_lg_barrel_shifter_underflow549w(0) OR input_is_zero_wo;
wire_w_lg_w_lg_overflow_w543w544w(0) <= wire_w_lg_overflow_w543w(0) OR positive_infinity;
wire_w_lg_w_lg_overflow_w536w537w(0) <= wire_w_lg_overflow_w536w(0) OR nan_w;
wire_w_lg_barrel_shifter_underflow549w(0) <= barrel_shifter_underflow OR overflow_w;
wire_w_lg_distance_overflow447w(0) <= distance_overflow OR wire_exp_value_add_bias_w_lg_w_result_range442w446w(0);
wire_w_lg_distance_overflow456w(0) <= distance_overflow OR wire_exp_value_add_bias_w_result_range442w(0);
wire_w_lg_overflow_w543w(0) <= overflow_w OR nan_w;
wire_w_lg_overflow_w536w(0) <= overflow_w OR underflow_w;
wire_w_lg_w_data_range78w80w(0) <= wire_w_data_range78w(0) OR wire_w_man_data_not_zero_w_range76w(0);
wire_w_lg_w_data_range81w83w(0) <= wire_w_data_range81w(0) OR wire_w_man_data_not_zero_w_range79w(0);
wire_w_lg_w_data_range84w86w(0) <= wire_w_data_range84w(0) OR wire_w_man_data_not_zero_w_range82w(0);
wire_w_lg_w_data_range87w89w(0) <= wire_w_data_range87w(0) OR wire_w_man_data_not_zero_w_range85w(0);
wire_w_lg_w_data_range90w92w(0) <= wire_w_data_range90w(0) OR wire_w_man_data_not_zero_w_range88w(0);
wire_w_lg_w_data_range93w95w(0) <= wire_w_data_range93w(0) OR wire_w_man_data_not_zero_w_range91w(0);
wire_w_lg_w_data_range96w98w(0) <= wire_w_data_range96w(0) OR wire_w_man_data_not_zero_w_range94w(0);
wire_w_lg_w_data_range99w101w(0) <= wire_w_data_range99w(0) OR wire_w_man_data_not_zero_w_range97w(0);
wire_w_lg_w_data_range102w104w(0) <= wire_w_data_range102w(0) OR wire_w_man_data_not_zero_w_range100w(0);
wire_w_lg_w_data_range105w107w(0) <= wire_w_data_range105w(0) OR wire_w_man_data_not_zero_w_range103w(0);
wire_w_lg_w_data_range51w53w(0) <= wire_w_data_range51w(0) OR wire_w_man_data_not_zero_w_range49w(0);
wire_w_lg_w_data_range108w110w(0) <= wire_w_data_range108w(0) OR wire_w_man_data_not_zero_w_range106w(0);
wire_w_lg_w_data_range111w113w(0) <= wire_w_data_range111w(0) OR wire_w_man_data_not_zero_w_range109w(0);
wire_w_lg_w_data_range114w116w(0) <= wire_w_data_range114w(0) OR wire_w_man_data_not_zero_w_range112w(0);
wire_w_lg_w_data_range10w12w(0) <= wire_w_data_range10w(0) OR wire_w_exp_data_not_zero_w_range8w(0);
wire_w_lg_w_data_range13w15w(0) <= wire_w_data_range13w(0) OR wire_w_exp_data_not_zero_w_range11w(0);
wire_w_lg_w_data_range16w18w(0) <= wire_w_data_range16w(0) OR wire_w_exp_data_not_zero_w_range14w(0);
wire_w_lg_w_data_range19w21w(0) <= wire_w_data_range19w(0) OR wire_w_exp_data_not_zero_w_range17w(0);
wire_w_lg_w_data_range22w24w(0) <= wire_w_data_range22w(0) OR wire_w_exp_data_not_zero_w_range20w(0);
wire_w_lg_w_data_range25w27w(0) <= wire_w_data_range25w(0) OR wire_w_exp_data_not_zero_w_range23w(0);
wire_w_lg_w_data_range54w56w(0) <= wire_w_data_range54w(0) OR wire_w_man_data_not_zero_w_range52w(0);
wire_w_lg_w_data_range28w30w(0) <= wire_w_data_range28w(0) OR wire_w_exp_data_not_zero_w_range26w(0);
wire_w_lg_w_data_range57w59w(0) <= wire_w_data_range57w(0) OR wire_w_man_data_not_zero_w_range55w(0);
wire_w_lg_w_data_range60w62w(0) <= wire_w_data_range60w(0) OR wire_w_man_data_not_zero_w_range58w(0);
wire_w_lg_w_data_range63w65w(0) <= wire_w_data_range63w(0) OR wire_w_man_data_not_zero_w_range61w(0);
wire_w_lg_w_data_range66w68w(0) <= wire_w_data_range66w(0) OR wire_w_man_data_not_zero_w_range64w(0);
wire_w_lg_w_data_range69w71w(0) <= wire_w_data_range69w(0) OR wire_w_man_data_not_zero_w_range67w(0);
wire_w_lg_w_data_range72w74w(0) <= wire_w_data_range72w(0) OR wire_w_man_data_not_zero_w_range70w(0);
wire_w_lg_w_data_range75w77w(0) <= wire_w_data_range75w(0) OR wire_w_man_data_not_zero_w_range73w(0);
wire_w_lg_w_exp_result_w_range563w567w(0) <= wire_w_exp_result_w_range563w(0) OR wire_w_exp_out_not_zero_w_range561w(0);
wire_w_lg_w_exp_result_w_range568w572w(0) <= wire_w_exp_result_w_range568w(0) OR wire_w_exp_out_not_zero_w_range566w(0);
wire_w_lg_w_exp_result_w_range573w577w(0) <= wire_w_exp_result_w_range573w(0) OR wire_w_exp_out_not_zero_w_range571w(0);
wire_w_lg_w_exp_result_w_range578w582w(0) <= wire_w_exp_result_w_range578w(0) OR wire_w_exp_out_not_zero_w_range576w(0);
wire_w_lg_w_exp_result_w_range583w587w(0) <= wire_w_exp_result_w_range583w(0) OR wire_w_exp_out_not_zero_w_range581w(0);
wire_w_lg_w_exp_result_w_range588w592w(0) <= wire_w_exp_result_w_range588w(0) OR wire_w_exp_out_not_zero_w_range586w(0);
wire_w_lg_w_exp_result_w_range593w595w(0) <= wire_w_exp_result_w_range593w(0) OR wire_w_exp_out_not_zero_w_range591w(0);
wire_w_lg_w_man_prod_result_range424w426w(0) <= wire_w_man_prod_result_range424w(0) OR wire_w_sticky_bits_range422w(0);
wire_w_lg_w_man_prod_result_range421w423w(0) <= wire_w_man_prod_result_range421w(0) OR wire_w_sticky_bits_range419w(0);
wire_w_lg_w_man_prod_result_range418w420w(0) <= wire_w_man_prod_result_range418w(0) OR wire_w_sticky_bits_range416w(0);
wire_w_lg_w_man_prod_result_range415w417w(0) <= wire_w_man_prod_result_range415w(0) OR wire_w_sticky_bits_range413w(0);
addr_val_more_than_one <= "10111";
barrel_shifter_data <= ( "00000000" & "1" & fraction_wo & "000000");
barrel_shifter_distance <= wire_exp_value_selecta_dataout;
barrel_shifter_underflow <= barrel_shifter_underflow_dffe2_15_pipes14;
barrel_shifter_underflow_wi <= (wire_underflow_compare_agb AND exp_value_wo(8));
distance_overflow <= distance_overflow_dffe2_15_pipes14;
distance_overflow_val_w <= "00000110";
distance_overflow_wi <= (wire_distance_overflow_comp_agb AND (NOT exp_value_wo(8)));
exp_bias <= "01111111";
exp_bias_all_ones_w <= (OTHERS => '1');
exp_data_all_one_w <= ( wire_w_lg_w_data_range28w47w & wire_w_lg_w_data_range25w45w & wire_w_lg_w_data_range22w43w & wire_w_lg_w_data_range19w41w & wire_w_lg_w_data_range16w39w & wire_w_lg_w_data_range13w37w & wire_w_lg_w_data_range10w35w & data(23));
exp_data_not_zero_w <= ( wire_w_lg_w_data_range28w30w & wire_w_lg_w_data_range25w27w & wire_w_lg_w_data_range22w24w & wire_w_lg_w_data_range19w21w & wire_w_lg_w_data_range16w18w & wire_w_lg_w_data_range13w15w & wire_w_lg_w_data_range10w12w & data(23));
exp_invert <= (xi_exp_value XOR exp_bias_all_ones_w);
exp_one <= ( wire_w_lg_w_lg_overflow_w543w544w & "1111111");
exp_out_all_one_w <= ( wire_w_lg_w_exp_result_w_range593w594w & wire_w_lg_w_exp_result_w_range588w590w & wire_w_lg_w_exp_result_w_range583w585w & wire_w_lg_w_exp_result_w_range578w580w & wire_w_lg_w_exp_result_w_range573w575w & wire_w_lg_w_exp_result_w_range568w570w & wire_w_lg_w_exp_result_w_range563w565w & exp_result_w(0));
exp_out_not_zero_w <= ( wire_w_lg_w_exp_result_w_range593w595w & wire_w_lg_w_exp_result_w_range588w592w & wire_w_lg_w_exp_result_w_range583w587w & wire_w_lg_w_exp_result_w_range578w582w & wire_w_lg_w_exp_result_w_range573w577w & wire_w_lg_w_exp_result_w_range568w572w & wire_w_lg_w_exp_result_w_range563w567w & exp_result_w(0));
exp_result_out <= wire_exp_result_mux_prea_w_lg_dataout557w;
exp_result_w <= wire_exp_value_man_over_result(7 DOWNTO 0);
exp_value <= wire_exp_minus_bias_result;
exp_value_wi <= exp_value;
exp_value_wo <= exp_value_dffe1;
exp_w <= data(30 DOWNTO 23);
extra_ln2 <= ((NOT xf_pre(37)) AND sign_dffe8);
fraction <= ( data(22 DOWNTO 0));
fraction_wi <= fraction;
fraction_wo <= fraction_dffe1;
gnd_w <= '0';
guard_bit <= man_prod_result(35);
input_is_infinity_wi <= wire_w_lg_w_exp_data_all_one_w_range46w119w(0);
input_is_infinity_wo <= input_is_infinity_16_pipes15;
input_is_nan_wi <= (exp_data_all_one_w(7) AND man_data_not_zero_w(22));
input_is_nan_wo <= input_is_nan_16_pipes15;
input_is_zero_wi <= (NOT exp_data_not_zero_w(7));
input_is_zero_wo <= input_is_zero_16_pipes15;
ln2_w <= "10110001011100100001011111110111110100";
man_data_not_zero_w <= ( wire_w_lg_w_data_range114w116w & wire_w_lg_w_data_range111w113w & wire_w_lg_w_data_range108w110w & wire_w_lg_w_data_range105w107w & wire_w_lg_w_data_range102w104w & wire_w_lg_w_data_range99w101w & wire_w_lg_w_data_range96w98w & wire_w_lg_w_data_range93w95w & wire_w_lg_w_data_range90w92w & wire_w_lg_w_data_range87w89w & wire_w_lg_w_data_range84w86w & wire_w_lg_w_data_range81w83w & wire_w_lg_w_data_range78w80w & wire_w_lg_w_data_range75w77w & wire_w_lg_w_data_range72w74w & wire_w_lg_w_data_range69w71w & wire_w_lg_w_data_range66w68w & wire_w_lg_w_data_range63w65w & wire_w_lg_w_data_range60w62w & wire_w_lg_w_data_range57w59w & wire_w_lg_w_data_range54w56w & wire_w_lg_w_data_range51w53w & data(0));
man_overflow <= (round_up AND man_result_all_ones(22));
man_overflow_wi <= man_overflow;
man_overflow_wo <= man_overflow_dffe15;
man_prod_result <= (wire_w_lg_man_prod_shifted408w OR wire_w_lg_man_prod_wire407w);
man_prod_shifted <= ( gnd_w & man_prod_wo(61 DOWNTO 1));
man_prod_wi <= wire_man_prod_result;
man_prod_wire <= man_prod_wo;
man_prod_wo <= man_prod_dffe14;
man_result_all_ones <= ( wire_w_lg_w_man_round_wi_range528w530w & wire_w_lg_w_man_round_wi_range525w527w & wire_w_lg_w_man_round_wi_range522w524w & wire_w_lg_w_man_round_wi_range519w521w & wire_w_lg_w_man_round_wi_range516w518w & wire_w_lg_w_man_round_wi_range513w515w & wire_w_lg_w_man_round_wi_range510w512w & wire_w_lg_w_man_round_wi_range507w509w & wire_w_lg_w_man_round_wi_range504w506w & wire_w_lg_w_man_round_wi_range501w503w & wire_w_lg_w_man_round_wi_range498w500w & wire_w_lg_w_man_round_wi_range495w497w & wire_w_lg_w_man_round_wi_range492w494w & wire_w_lg_w_man_round_wi_range489w491w & wire_w_lg_w_man_round_wi_range486w488w & wire_w_lg_w_man_round_wi_range483w485w & wire_w_lg_w_man_round_wi_range480w482w & wire_w_lg_w_man_round_wi_range477w479w & wire_w_lg_w_man_round_wi_range474w476w & wire_w_lg_w_man_round_wi_range471w473w & wire_w_lg_w_man_round_wi_range468w470w & wire_w_lg_w_man_round_wi_range465w467w & man_round_wi(0));
man_result_w <= wire_man_result_muxa_dataout;
man_round_wi <= man_prod_result(57 DOWNTO 35);
man_round_wo <= man_round_dffe15;
nan <= nan_wo;
nan_w <= input_is_nan_wo;
nan_wi <= nan_w;
nan_wo <= nan_dffe16;
negative_infinity <= (sign_dffe15 AND input_is_infinity_wo);
one_over_ln2_w <= "101110001";
overflow <= overflow_wo;
overflow_w <= (((wire_sign_dffe_w_lg_q436w(0) AND ((wire_w_lg_distance_overflow456w(0) OR exp_out_all_one_w(7)) OR wire_exp_value_man_over_result(8))) AND wire_w_lg_underflow_w455w(0)) AND wire_w_lg_input_is_nan_wo443w(0));
overflow_wi <= overflow_w;
overflow_wo <= overflow_dffe16;
positive_infinity <= (wire_sign_dffe_w_lg_q436w(0) AND input_is_infinity_wo);
result <= ( "0" & result_pipe_wo);
result_pipe_wi <= ( exp_result_out & man_result_w);
result_pipe_wo <= result_pipe_dffe16;
result_underflow_w <= ((NOT exp_out_not_zero_w(7)) AND wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range434w437w438w439w(0));
round_bit <= man_prod_result(34);
round_up <= (round_bit AND (guard_bit OR sticky_bits(4)));
round_up_wi <= round_up;
round_up_wo <= round_up_dffe15;
shifted_value <= (tbl1_compare_wo OR man_prod_wo(59));
sign_w <= data(31);
sticky_bits <= ( wire_w_lg_w_man_prod_result_range424w426w & wire_w_lg_w_man_prod_result_range421w423w & wire_w_lg_w_man_prod_result_range418w420w & wire_w_lg_w_man_prod_result_range415w417w & man_prod_result(33));
table_one_data <= ( "10101000100111100001011100110110" & "10100011011011100000001001111010" & "10011110011001101100101000011001" & "10011001100001110010110000111101" & "10010100110011011111000011111001" & "10010000001110011110100111111000" & "10001011110010011111001000110010" & "10000111011111001110110110100011" & "10000011010100011100100100000011" & "11111110100011101111001100001100" & "11110110101110011111100100100000" & "11101111001000101010111011111100" & "11100111110001110010111011000010" & "11100000101001011010000110001001" & "11011001101111000011111011100100" & "11010011000010010100110001110000" & "11001100100010110001110101101010" & "11000110010000000001001000111011" & "11000000001001101001100000011010" & "10111010001111010010100010011110" & "10110100100000100100100101100101" & "10101110111101001000101110110000" & "10101001100100101000110000000110" & "10100100010110101111000111100001" & "10011111010011000110111101010101" & "10011010011001011100000010111000" & "10010101101001011010110001011001" & "10010001000010110000001000101101" & "10001100100101001001101110000011" & "10001000010000010101101010111011" & "10000100000100000010101100000000" & "10000000000000000000000000000000");
table_one_out <= wire_table_one_result;
table_three_data <= ( "111110000001111000001" & "111100000001110000100" & "111010000001101001001" & "111000000001100010000" & "110110000001011011001" & "110100000001010100100" & "110010000001001110001" & "110000000001001000000" & "101110000001000010001" & "101100000000111100100" & "101010000000110111001" & "101000000000110010000" & "100110000000101101001" & "100100000000101000100" & "100010000000100100001" & "100000000000100000000" & "011110000000011100001" & "011100000000011000100" & "011010000000010101001" & "011000000000010010000" & "010110000000001111001" & "010100000000001100100" & "010010000000001010001" & "010000000000001000000" & "001110000000000110001" & "001100000000000100100" & "001010000000000011001" & "001000000000000010000" & "000110000000000001001" & "000100000000000000100" & "000010000000000000001" & "000000000000000000000");
table_three_out <= ( "1" & "0000000000" & table_three_out_tmp);
table_three_out_tmp <= wire_table_three_result;
table_two_data <= ( "11111011110010101100010101" & "11110011100011001101101010" & "11101011010100001111111011" & "11100011000101110011000111" & "11011010110111110111001100" & "11010010101010011100001000" & "11001010011101100001111000" & "11000010010001001000011011" & "10111010000101001111101110" & "10110001111001110111110000" & "10101001101111000000011110" & "10100001100100101001110111" & "10011001011010110011111000" & "10010001010001011110100000" & "10001001001000101001101100" & "10000001000000010101011010" & "01111000111000100001101001" & "01110000110001001110010101" & "01101000101010011011011110" & "01100000100100001001000001" & "01011000011110010110111100" & "01010000011001000101001110" & "01001000010100010011110011" & "01000000010000000010101011" & "00111000001100010001110010" & "00110000001001000001001000" & "00101000000110010000101001" & "00100000000100000000010101" & "00011000000010010000001001" & "00010000000001000000000010" & "00001000000000010000000000" & "00000000000000000000000000");
table_two_out <= ( "1" & "00000" & table_two_out_tmp);
table_two_out_tmp <= wire_table_two_result;
tbl1_compare_wi <= wire_tbl1_compare_ageb;
tbl1_compare_wo <= tbl1_compare_dffe11_4_pipes3;
tbl1_tbl2_prod_wi <= wire_tbl1_tbl2_prod_result(63 DOWNTO 33);
tbl1_tbl2_prod_wo <= tbl1_tbl2_prod_dffe12;
tbl3_taylor_prod_wi <= wire_tbl3_taylor_prod_result(61 DOWNTO 31);
tbl3_taylor_prod_wo <= tbl3_taylor_prod_dffe12;
underflow <= underflow_wo;
underflow_compare_val_w <= "00011101";
underflow_w <= (((((result_underflow_w OR barrel_shifter_underflow) OR wire_sign_dffe_w_lg_q448w(0)) AND wire_w_lg_input_is_zero_wo445w(0)) AND wire_w_lg_input_is_infinity_wo444w(0)) AND wire_w_lg_input_is_nan_wo443w(0));
underflow_wi <= underflow_w;
underflow_wo <= underflow_dffe16;
x_fixed <= wire_rbarrel_shift_result;
xf <= wire_xf_muxa_dataout;
xf_pre <= wire_x_fixed_minus_xiln2_result;
xf_pre_2_wi <= xf_pre_wo;
xf_pre_2_wo <= xf_pre_2_dffe10;
xf_pre_wi <= xf_pre;
xf_pre_wo <= xf_pre_dffe9;
xi_exp_value <= xi_prod_wo(18 DOWNTO 11);
xi_exp_value_wi <= xi_exp_value;
xi_exp_value_wo <= xi_exp_value_dffe4;
xi_ln2_prod_wi <= wire_xi_ln2_prod_result;
xi_ln2_prod_wo <= xi_ln2_prod_dffe7;
xi_prod_wi <= wire_xi_prod_result;
xi_prod_wo <= xi_prod_dffe3;
zero <= zero_wo;
zero_w <= negative_infinity;
zero_wi <= zero_w;
zero_wo <= zero_dffe16;
wire_w_data_range78w(0) <= data(10);
wire_w_data_range81w(0) <= data(11);
wire_w_data_range84w(0) <= data(12);
wire_w_data_range87w(0) <= data(13);
wire_w_data_range90w(0) <= data(14);
wire_w_data_range93w(0) <= data(15);
wire_w_data_range96w(0) <= data(16);
wire_w_data_range99w(0) <= data(17);
wire_w_data_range102w(0) <= data(18);
wire_w_data_range105w(0) <= data(19);
wire_w_data_range51w(0) <= data(1);
wire_w_data_range108w(0) <= data(20);
wire_w_data_range111w(0) <= data(21);
wire_w_data_range114w(0) <= data(22);
wire_w_data_range10w(0) <= data(24);
wire_w_data_range13w(0) <= data(25);
wire_w_data_range16w(0) <= data(26);
wire_w_data_range19w(0) <= data(27);
wire_w_data_range22w(0) <= data(28);
wire_w_data_range25w(0) <= data(29);
wire_w_data_range54w(0) <= data(2);
wire_w_data_range28w(0) <= data(30);
wire_w_data_range57w(0) <= data(3);
wire_w_data_range60w(0) <= data(4);
wire_w_data_range63w(0) <= data(5);
wire_w_data_range66w(0) <= data(6);
wire_w_data_range69w(0) <= data(7);
wire_w_data_range72w(0) <= data(8);
wire_w_data_range75w(0) <= data(9);
wire_w_exp_data_all_one_w_range32w(0) <= exp_data_all_one_w(0);
wire_w_exp_data_all_one_w_range34w(0) <= exp_data_all_one_w(1);
wire_w_exp_data_all_one_w_range36w(0) <= exp_data_all_one_w(2);
wire_w_exp_data_all_one_w_range38w(0) <= exp_data_all_one_w(3);
wire_w_exp_data_all_one_w_range40w(0) <= exp_data_all_one_w(4);
wire_w_exp_data_all_one_w_range42w(0) <= exp_data_all_one_w(5);
wire_w_exp_data_all_one_w_range44w(0) <= exp_data_all_one_w(6);
wire_w_exp_data_all_one_w_range46w(0) <= exp_data_all_one_w(7);
wire_w_exp_data_not_zero_w_range8w(0) <= exp_data_not_zero_w(0);
wire_w_exp_data_not_zero_w_range11w(0) <= exp_data_not_zero_w(1);
wire_w_exp_data_not_zero_w_range14w(0) <= exp_data_not_zero_w(2);
wire_w_exp_data_not_zero_w_range17w(0) <= exp_data_not_zero_w(3);
wire_w_exp_data_not_zero_w_range20w(0) <= exp_data_not_zero_w(4);
wire_w_exp_data_not_zero_w_range23w(0) <= exp_data_not_zero_w(5);
wire_w_exp_data_not_zero_w_range26w(0) <= exp_data_not_zero_w(6);
wire_w_exp_out_all_one_w_range559w(0) <= exp_out_all_one_w(0);
wire_w_exp_out_all_one_w_range564w(0) <= exp_out_all_one_w(1);
wire_w_exp_out_all_one_w_range569w(0) <= exp_out_all_one_w(2);
wire_w_exp_out_all_one_w_range574w(0) <= exp_out_all_one_w(3);
wire_w_exp_out_all_one_w_range579w(0) <= exp_out_all_one_w(4);
wire_w_exp_out_all_one_w_range584w(0) <= exp_out_all_one_w(5);
wire_w_exp_out_all_one_w_range589w(0) <= exp_out_all_one_w(6);
wire_w_exp_out_not_zero_w_range561w(0) <= exp_out_not_zero_w(0);
wire_w_exp_out_not_zero_w_range566w(0) <= exp_out_not_zero_w(1);
wire_w_exp_out_not_zero_w_range571w(0) <= exp_out_not_zero_w(2);
wire_w_exp_out_not_zero_w_range576w(0) <= exp_out_not_zero_w(3);
wire_w_exp_out_not_zero_w_range581w(0) <= exp_out_not_zero_w(4);
wire_w_exp_out_not_zero_w_range586w(0) <= exp_out_not_zero_w(5);
wire_w_exp_out_not_zero_w_range591w(0) <= exp_out_not_zero_w(6);
wire_w_exp_result_w_range563w(0) <= exp_result_w(1);
wire_w_exp_result_w_range568w(0) <= exp_result_w(2);
wire_w_exp_result_w_range573w(0) <= exp_result_w(3);
wire_w_exp_result_w_range578w(0) <= exp_result_w(4);
wire_w_exp_result_w_range583w(0) <= exp_result_w(5);
wire_w_exp_result_w_range588w(0) <= exp_result_w(6);
wire_w_exp_result_w_range593w(0) <= exp_result_w(7);
wire_w_exp_value_wo_range129w <= exp_value_wo(5 DOWNTO 0);
wire_w_exp_value_wo_range132w <= exp_value_wo(7 DOWNTO 0);
wire_w_exp_value_wo_range131w(0) <= exp_value_wo(8);
wire_w_man_data_not_zero_w_range49w(0) <= man_data_not_zero_w(0);
wire_w_man_data_not_zero_w_range79w(0) <= man_data_not_zero_w(10);
wire_w_man_data_not_zero_w_range82w(0) <= man_data_not_zero_w(11);
wire_w_man_data_not_zero_w_range85w(0) <= man_data_not_zero_w(12);
wire_w_man_data_not_zero_w_range88w(0) <= man_data_not_zero_w(13);
wire_w_man_data_not_zero_w_range91w(0) <= man_data_not_zero_w(14);
wire_w_man_data_not_zero_w_range94w(0) <= man_data_not_zero_w(15);
wire_w_man_data_not_zero_w_range97w(0) <= man_data_not_zero_w(16);
wire_w_man_data_not_zero_w_range100w(0) <= man_data_not_zero_w(17);
wire_w_man_data_not_zero_w_range103w(0) <= man_data_not_zero_w(18);
wire_w_man_data_not_zero_w_range106w(0) <= man_data_not_zero_w(19);
wire_w_man_data_not_zero_w_range52w(0) <= man_data_not_zero_w(1);
wire_w_man_data_not_zero_w_range109w(0) <= man_data_not_zero_w(20);
wire_w_man_data_not_zero_w_range112w(0) <= man_data_not_zero_w(21);
wire_w_man_data_not_zero_w_range115w(0) <= man_data_not_zero_w(22);
wire_w_man_data_not_zero_w_range55w(0) <= man_data_not_zero_w(2);
wire_w_man_data_not_zero_w_range58w(0) <= man_data_not_zero_w(3);
wire_w_man_data_not_zero_w_range61w(0) <= man_data_not_zero_w(4);
wire_w_man_data_not_zero_w_range64w(0) <= man_data_not_zero_w(5);
wire_w_man_data_not_zero_w_range67w(0) <= man_data_not_zero_w(6);
wire_w_man_data_not_zero_w_range70w(0) <= man_data_not_zero_w(7);
wire_w_man_data_not_zero_w_range73w(0) <= man_data_not_zero_w(8);
wire_w_man_data_not_zero_w_range76w(0) <= man_data_not_zero_w(9);
wire_w_man_prod_result_range424w(0) <= man_prod_result(29);
wire_w_man_prod_result_range421w(0) <= man_prod_result(30);
wire_w_man_prod_result_range418w(0) <= man_prod_result(31);
wire_w_man_prod_result_range415w(0) <= man_prod_result(32);
wire_w_man_prod_wo_range402w(0) <= man_prod_wo(59);
wire_w_man_result_all_ones_range463w(0) <= man_result_all_ones(0);
wire_w_man_result_all_ones_range493w(0) <= man_result_all_ones(10);
wire_w_man_result_all_ones_range496w(0) <= man_result_all_ones(11);
wire_w_man_result_all_ones_range499w(0) <= man_result_all_ones(12);
wire_w_man_result_all_ones_range502w(0) <= man_result_all_ones(13);
wire_w_man_result_all_ones_range505w(0) <= man_result_all_ones(14);
wire_w_man_result_all_ones_range508w(0) <= man_result_all_ones(15);
wire_w_man_result_all_ones_range511w(0) <= man_result_all_ones(16);
wire_w_man_result_all_ones_range514w(0) <= man_result_all_ones(17);
wire_w_man_result_all_ones_range517w(0) <= man_result_all_ones(18);
wire_w_man_result_all_ones_range520w(0) <= man_result_all_ones(19);
wire_w_man_result_all_ones_range466w(0) <= man_result_all_ones(1);
wire_w_man_result_all_ones_range523w(0) <= man_result_all_ones(20);
wire_w_man_result_all_ones_range526w(0) <= man_result_all_ones(21);
wire_w_man_result_all_ones_range469w(0) <= man_result_all_ones(2);
wire_w_man_result_all_ones_range472w(0) <= man_result_all_ones(3);
wire_w_man_result_all_ones_range475w(0) <= man_result_all_ones(4);
wire_w_man_result_all_ones_range478w(0) <= man_result_all_ones(5);
wire_w_man_result_all_ones_range481w(0) <= man_result_all_ones(6);
wire_w_man_result_all_ones_range484w(0) <= man_result_all_ones(7);
wire_w_man_result_all_ones_range487w(0) <= man_result_all_ones(8);
wire_w_man_result_all_ones_range490w(0) <= man_result_all_ones(9);
wire_w_man_round_wi_range492w(0) <= man_round_wi(10);
wire_w_man_round_wi_range495w(0) <= man_round_wi(11);
wire_w_man_round_wi_range498w(0) <= man_round_wi(12);
wire_w_man_round_wi_range501w(0) <= man_round_wi(13);
wire_w_man_round_wi_range504w(0) <= man_round_wi(14);
wire_w_man_round_wi_range507w(0) <= man_round_wi(15);
wire_w_man_round_wi_range510w(0) <= man_round_wi(16);
wire_w_man_round_wi_range513w(0) <= man_round_wi(17);
wire_w_man_round_wi_range516w(0) <= man_round_wi(18);
wire_w_man_round_wi_range519w(0) <= man_round_wi(19);
wire_w_man_round_wi_range465w(0) <= man_round_wi(1);
wire_w_man_round_wi_range522w(0) <= man_round_wi(20);
wire_w_man_round_wi_range525w(0) <= man_round_wi(21);
wire_w_man_round_wi_range528w(0) <= man_round_wi(22);
wire_w_man_round_wi_range468w(0) <= man_round_wi(2);
wire_w_man_round_wi_range471w(0) <= man_round_wi(3);
wire_w_man_round_wi_range474w(0) <= man_round_wi(4);
wire_w_man_round_wi_range477w(0) <= man_round_wi(5);
wire_w_man_round_wi_range480w(0) <= man_round_wi(6);
wire_w_man_round_wi_range483w(0) <= man_round_wi(7);
wire_w_man_round_wi_range486w(0) <= man_round_wi(8);
wire_w_man_round_wi_range489w(0) <= man_round_wi(9);
wire_w_sticky_bits_range413w(0) <= sticky_bits(0);
wire_w_sticky_bits_range416w(0) <= sticky_bits(1);
wire_w_sticky_bits_range419w(0) <= sticky_bits(2);
wire_w_sticky_bits_range422w(0) <= sticky_bits(3);
wire_w_xf_pre_2_wo_range183w <= xf_pre_2_wo(30 DOWNTO 0);
wire_w_xf_pre_wo_range177w <= xf_pre_wo(30 DOWNTO 0);
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes0 <= barrel_shifter_underflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes1 <= barrel_shifter_underflow_dffe2_15_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes2 <= barrel_shifter_underflow_dffe2_15_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes3 <= barrel_shifter_underflow_dffe2_15_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes4 <= barrel_shifter_underflow_dffe2_15_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes5 <= barrel_shifter_underflow_dffe2_15_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes6 <= barrel_shifter_underflow_dffe2_15_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes7 <= barrel_shifter_underflow_dffe2_15_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes8 <= barrel_shifter_underflow_dffe2_15_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes9 <= barrel_shifter_underflow_dffe2_15_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes10 <= barrel_shifter_underflow_dffe2_15_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes11 <= barrel_shifter_underflow_dffe2_15_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes12 <= barrel_shifter_underflow_dffe2_15_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes13 <= barrel_shifter_underflow_dffe2_15_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN barrel_shifter_underflow_dffe2_15_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN barrel_shifter_underflow_dffe2_15_pipes14 <= barrel_shifter_underflow_dffe2_15_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes0 <= distance_overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes1 <= distance_overflow_dffe2_15_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes2 <= distance_overflow_dffe2_15_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes3 <= distance_overflow_dffe2_15_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes4 <= distance_overflow_dffe2_15_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes5 <= distance_overflow_dffe2_15_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes6 <= distance_overflow_dffe2_15_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes7 <= distance_overflow_dffe2_15_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes8 <= distance_overflow_dffe2_15_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes9 <= distance_overflow_dffe2_15_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes10 <= distance_overflow_dffe2_15_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes11 <= distance_overflow_dffe2_15_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes12 <= distance_overflow_dffe2_15_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes13 <= distance_overflow_dffe2_15_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN distance_overflow_dffe2_15_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN distance_overflow_dffe2_15_pipes14 <= distance_overflow_dffe2_15_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_0 <= wire_exp_value_b4_biasa_dataout;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_1 <= exp_value_b4_bias_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_10 <= exp_value_b4_bias_dffe_9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_2 <= exp_value_b4_bias_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_3 <= exp_value_b4_bias_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_4 <= exp_value_b4_bias_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_5 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_5 <= exp_value_b4_bias_dffe_4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_6 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_6 <= exp_value_b4_bias_dffe_5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_7 <= exp_value_b4_bias_dffe_6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_8 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_8 <= exp_value_b4_bias_dffe_7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_b4_bias_dffe_9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_b4_bias_dffe_9 <= exp_value_b4_bias_dffe_8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN exp_value_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN exp_value_dffe1 <= exp_value_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_0 <= extra_ln2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_1 <= extra_ln2_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_2 <= extra_ln2_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_3 <= extra_ln2_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_4 <= extra_ln2_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN extra_ln2_dffe_5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN extra_ln2_dffe_5 <= extra_ln2_dffe_4;
END IF;
END IF;
END PROCESS;
wire_extra_ln2_dffe_5_w_lg_q158w(0) <= NOT extra_ln2_dffe_5;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN fraction_dffe1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN fraction_dffe1 <= fraction_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes0 <= input_is_infinity_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes1 <= input_is_infinity_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes2 <= input_is_infinity_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes3 <= input_is_infinity_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes4 <= input_is_infinity_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes5 <= input_is_infinity_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes6 <= input_is_infinity_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes7 <= input_is_infinity_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes8 <= input_is_infinity_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes9 <= input_is_infinity_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes10 <= input_is_infinity_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes11 <= input_is_infinity_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes12 <= input_is_infinity_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes13 <= input_is_infinity_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes14 <= input_is_infinity_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_infinity_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_infinity_16_pipes15 <= input_is_infinity_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes0 <= input_is_nan_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes1 <= input_is_nan_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes2 <= input_is_nan_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes3 <= input_is_nan_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes4 <= input_is_nan_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes5 <= input_is_nan_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes6 <= input_is_nan_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes7 <= input_is_nan_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes8 <= input_is_nan_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes9 <= input_is_nan_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes10 <= input_is_nan_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes11 <= input_is_nan_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes12 <= input_is_nan_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes13 <= input_is_nan_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes14 <= input_is_nan_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_nan_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_nan_16_pipes15 <= input_is_nan_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes0 <= input_is_zero_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes1 <= input_is_zero_16_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes2 <= input_is_zero_16_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes3 <= input_is_zero_16_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes4 <= input_is_zero_16_pipes3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes5 <= input_is_zero_16_pipes4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes6 <= input_is_zero_16_pipes5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes7 <= input_is_zero_16_pipes6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes8 <= input_is_zero_16_pipes7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes9 <= input_is_zero_16_pipes8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes10 <= input_is_zero_16_pipes9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes11 <= input_is_zero_16_pipes10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes12 <= input_is_zero_16_pipes11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes13 <= input_is_zero_16_pipes12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes14 <= input_is_zero_16_pipes13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN input_is_zero_16_pipes15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN input_is_zero_16_pipes15 <= input_is_zero_16_pipes14;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_overflow_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_overflow_dffe15 <= man_overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_prod_dffe14 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_prod_dffe14 <= man_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN man_round_dffe15 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN man_round_dffe15 <= man_round_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN nan_dffe16 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN nan_dffe16 <= nan_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN overflow_dffe16 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN overflow_dffe16 <= overflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN result_pipe_dffe16 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN result_pipe_dffe16 <= result_pipe_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN round_up_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN round_up_dffe15 <= round_up_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe0 <= sign_w;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe1 <= sign_dffe0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe2 <= sign_dffe1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe3 <= sign_dffe2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe4 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe4 <= sign_dffe3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe5 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe5 <= sign_dffe4;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe6 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe6 <= sign_dffe5;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe7 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe7 <= sign_dffe6;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe8 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe8 <= sign_dffe7;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe9 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe9 <= sign_dffe8;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe10 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe10 <= sign_dffe9;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe11 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe11 <= sign_dffe10;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe12 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe12 <= sign_dffe11;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe13 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe13 <= sign_dffe12;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe14 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe14 <= sign_dffe13;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN sign_dffe15 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN sign_dffe15 <= sign_dffe14;
END IF;
END IF;
END PROCESS;
wire_sign_dffe_w_lg_q448w(0) <= sign_dffe15 AND wire_w_lg_distance_overflow447w(0);
wire_sign_dffe_w_lg_q436w(0) <= NOT sign_dffe15;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes0 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes0 <= tbl1_compare_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes1 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes1 <= tbl1_compare_dffe11_4_pipes0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes2 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes2 <= tbl1_compare_dffe11_4_pipes1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_compare_dffe11_4_pipes3 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_compare_dffe11_4_pipes3 <= tbl1_compare_dffe11_4_pipes2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl1_tbl2_prod_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl1_tbl2_prod_dffe12 <= tbl1_tbl2_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN tbl3_taylor_prod_dffe12 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN tbl3_taylor_prod_dffe12 <= tbl3_taylor_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN underflow_dffe16 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN underflow_dffe16 <= underflow_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_0 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_0 <= x_fixed;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_1 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_1 <= x_fixed_dffe_0;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_2 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_2 <= x_fixed_dffe_1;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_3 <= x_fixed_dffe_2;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN x_fixed_dffe_4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN x_fixed_dffe_4 <= x_fixed_dffe_3;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xf_pre_2_dffe10 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xf_pre_2_dffe10 <= xf_pre_2_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xf_pre_dffe9 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xf_pre_dffe9 <= xf_pre_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_exp_value_dffe4 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_exp_value_dffe4 <= xi_exp_value_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_ln2_prod_dffe7 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_ln2_prod_dffe7 <= xi_ln2_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN xi_prod_dffe3 <= (OTHERS => '0');
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN xi_prod_dffe3 <= xi_prod_wi;
END IF;
END IF;
END PROCESS;
PROCESS (clock, aclr)
BEGIN
IF (aclr = '1') THEN zero_dffe16 <= '0';
ELSIF (clock = '1' AND clock'event) THEN
IF (clk_en = '1') THEN zero_dffe16 <= zero_wi;
END IF;
END IF;
END PROCESS;
wire_exp_minus_bias_dataa <= ( "0" & exp_w);
wire_exp_minus_bias_datab <= ( "0" & exp_bias);
exp_minus_bias : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => wire_exp_minus_bias_dataa,
datab => wire_exp_minus_bias_datab,
result => wire_exp_minus_bias_result
);
wire_exp_value_add_bias_w_lg_w_result_range442w446w(0) <= NOT wire_exp_value_add_bias_w_result_range442w(0);
wire_exp_value_add_bias_dataa <= ( "0" & exp_value_b4_bias_dffe_10);
wire_exp_value_add_bias_datab <= ( "0" & exp_bias(7 DOWNTO 1) & wire_extra_ln2_dffe_5_w_lg_q158w);
wire_exp_value_add_bias_w_result_range442w(0) <= wire_exp_value_add_bias_result(8);
exp_value_add_bias : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
aclr => aclr,
cin => wire_cin_to_bias_dataout,
clken => clk_en,
clock => clock,
dataa => wire_exp_value_add_bias_dataa,
datab => wire_exp_value_add_bias_datab,
result => wire_exp_value_add_bias_result
);
wire_exp_value_man_over_w_lg_w_lg_w_result_range434w437w438w(0) <= wire_exp_value_man_over_w_lg_w_result_range434w437w(0) AND wire_sign_dffe_w_lg_q436w(0);
wire_exp_value_man_over_w_lg_w_result_range434w437w(0) <= NOT wire_exp_value_man_over_w_result_range434w(0);
wire_exp_value_man_over_w_lg_w_lg_w_lg_w_result_range434w437w438w439w(0) <= wire_exp_value_man_over_w_lg_w_lg_w_result_range434w437w438w(0) OR sign_dffe15;
wire_exp_value_man_over_datab <= ( "00000000" & man_overflow_wo);
wire_exp_value_man_over_w_result_range434w(0) <= wire_exp_value_man_over_result(8);
exp_value_man_over : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 9
)
PORT MAP (
dataa => wire_exp_value_add_bias_result,
datab => wire_exp_value_man_over_datab,
result => wire_exp_value_man_over_result
);
wire_invert_exp_value_dataa <= (OTHERS => '0');
wire_invert_exp_value_w_result_range130w <= wire_invert_exp_value_result(5 DOWNTO 0);
invert_exp_value : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_invert_exp_value_dataa,
datab => exp_value(7 DOWNTO 0),
result => wire_invert_exp_value_result
);
wire_man_round_datab <= ( "0000000000000000000000" & round_up_wo);
man_round : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 23
)
PORT MAP (
dataa => man_round_wo,
datab => wire_man_round_datab,
result => wire_man_round_result
);
wire_one_minus_xf_dataa <= ( "1" & "000000000000000000000000000000");
one_minus_xf : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 31
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_one_minus_xf_dataa,
datab => wire_extra_ln2_muxa_dataout,
result => wire_one_minus_xf_result
);
wire_x_fixed_minus_xiln2_datab <= ( "0" & xi_ln2_prod_wo(45 DOWNTO 9));
x_fixed_minus_xiln2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 38
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => x_fixed_dffe_4,
datab => wire_x_fixed_minus_xiln2_datab,
result => wire_x_fixed_minus_xiln2_result
);
wire_xf_minus_ln2_datab <= ( "00" & ln2_w(37 DOWNTO 9));
xf_minus_ln2 : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "SUB",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 31
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => xf_pre(30 DOWNTO 0),
datab => wire_xf_minus_ln2_datab,
result => wire_xf_minus_ln2_result
);
wire_xi_add_one_datab <= "00000001";
xi_add_one : lpm_add_sub
GENERIC MAP (
LPM_DIRECTION => "ADD",
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "SIGNED",
LPM_WIDTH => 8
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => xi_exp_value,
datab => wire_xi_add_one_datab,
result => wire_xi_add_one_result
);
rbarrel_shift : lpm_clshift
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_SHIFTTYPE => "LOGICAL",
LPM_WIDTH => 38,
LPM_WIDTHDIST => 6
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
data => barrel_shifter_data,
direction => exp_value_wo(8),
distance => barrel_shifter_distance,
result => wire_rbarrel_shift_result
);
distance_overflow_comp : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
agb => wire_distance_overflow_comp_agb,
dataa => wire_exp_value_to_compare_muxa_dataout,
datab => distance_overflow_val_w
);
tbl1_compare : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 5
)
PORT MAP (
ageb => wire_tbl1_compare_ageb,
dataa => xf(28 DOWNTO 24),
datab => addr_val_more_than_one
);
underflow_compare : lpm_compare
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTH => 8
)
PORT MAP (
agb => wire_underflow_compare_agb,
dataa => wire_exp_value_to_compare_muxa_dataout,
datab => underflow_compare_val_w
);
man_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 31,
LPM_WIDTHB => 31,
LPM_WIDTHP => 62,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => tbl1_tbl2_prod_wo,
datab => tbl3_taylor_prod_wo,
result => wire_man_prod_result
);
tbl1_tbl2_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 32,
LPM_WIDTHB => 32,
LPM_WIDTHP => 64,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => table_one_out,
datab => table_two_out,
result => wire_tbl1_tbl2_prod_result
);
wire_tbl3_taylor_prod_datab <= ( "1" & "000000000000000" & xf(13 DOWNTO 0));
tbl3_taylor_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 1,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 32,
LPM_WIDTHB => 30,
LPM_WIDTHP => 62,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => table_three_out,
datab => wire_tbl3_taylor_prod_datab,
result => wire_tbl3_taylor_prod_result
);
xi_ln2_prod : lpm_mult
GENERIC MAP (
LPM_PIPELINE => 2,
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 8,
LPM_WIDTHB => 38,
LPM_WIDTHP => 46,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
aclr => aclr,
clken => clk_en,
clock => clock,
dataa => wire_exp_value_to_ln2a_dataout,
datab => ln2_w,
result => wire_xi_ln2_prod_result
);
xi_prod : lpm_mult
GENERIC MAP (
LPM_REPRESENTATION => "UNSIGNED",
LPM_WIDTHA => 12,
LPM_WIDTHB => 9,
LPM_WIDTHP => 21,
lpm_hint => "DEDICATED_MULTIPLIER_CIRCUITRY=YES"
)
PORT MAP (
dataa => x_fixed(37 DOWNTO 26),
datab => one_over_ln2_w,
result => wire_xi_prod_result
);
loop2 : FOR i IN 0 TO 31 GENERATE
loop3 : FOR j IN 0 TO 31 GENERATE
wire_table_one_data_2d(i, j) <= table_one_data(i*32+j);
END GENERATE loop3;
END GENERATE loop2;
table_one : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 32,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_one_data_2d,
result => wire_table_one_result,
sel => xf(28 DOWNTO 24)
);
loop4 : FOR i IN 0 TO 31 GENERATE
loop5 : FOR j IN 0 TO 20 GENERATE
wire_table_three_data_2d(i, j) <= table_three_data(i*21+j);
END GENERATE loop5;
END GENERATE loop4;
table_three : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 21,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_three_data_2d,
result => wire_table_three_result,
sel => xf(18 DOWNTO 14)
);
loop6 : FOR i IN 0 TO 31 GENERATE
loop7 : FOR j IN 0 TO 25 GENERATE
wire_table_two_data_2d(i, j) <= table_two_data(i*26+j);
END GENERATE loop7;
END GENERATE loop6;
table_two : lpm_mux
GENERIC MAP (
LPM_SIZE => 32,
LPM_WIDTH => 26,
LPM_WIDTHS => 5
)
PORT MAP (
data => wire_table_two_data_2d,
result => wire_table_two_result,
sel => xf(23 DOWNTO 19)
);
wire_cin_to_bias_dataout <= shifted_value;
wire_exp_result_mux_prea_dataout <= exp_one WHEN wire_w_lg_w551w552w(0) = '1' ELSE exp_result_w;
loop8 : FOR i IN 0 TO 7 GENERATE
wire_exp_result_mux_prea_w_lg_dataout557w(i) <= wire_exp_result_mux_prea_dataout(i) AND wire_w_lg_w_lg_w_lg_underflow_w554w555w556w(0);
END GENERATE loop8;
wire_exp_value_b4_biasa_dataout <= exp_invert WHEN sign_dffe3 = '1' ELSE xi_exp_value;
wire_exp_value_selecta_dataout <= wire_invert_exp_value_result(5 DOWNTO 0) WHEN exp_value_wo(8) = '1' ELSE exp_value_wo(5 DOWNTO 0);
wire_exp_value_to_compare_muxa_dataout <= wire_invert_exp_value_result WHEN exp_value_wo(8) = '1' ELSE exp_value_wo(7 DOWNTO 0);
wire_exp_value_to_ln2a_dataout <= wire_xi_add_one_result WHEN sign_dffe4 = '1' ELSE xi_exp_value_wo;
wire_extra_ln2_muxa_dataout <= wire_xf_minus_ln2_result WHEN extra_ln2_dffe_0 = '1' ELSE xf_pre_wo(30 DOWNTO 0);
wire_man_result_muxa_dataout <= ( nan_w & "0000000000000000000000") WHEN wire_w_lg_w_lg_w_lg_w_lg_overflow_w536w537w538w539w(0) = '1' ELSE wire_man_round_result;
wire_xf_muxa_dataout <= wire_one_minus_xf_result WHEN sign_dffe10 = '1' ELSE xf_pre_2_wo(30 DOWNTO 0);
END RTL; --altfp_exp0_altfp_exp_vdg
--VALID FILE
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altfp_exp0 IS
PORT
(
aclr : IN STD_LOGIC := '0';
clk_en : IN STD_LOGIC := '0';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0');
nan : OUT STD_LOGIC ;
overflow : OUT STD_LOGIC ;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
underflow : OUT STD_LOGIC ;
zero : OUT STD_LOGIC
);
END altfp_exp0;
ARCHITECTURE RTL OF altfp_exp0 IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT altfp_exp0_altfp_exp_vdg
PORT (
overflow : OUT STD_LOGIC ;
underflow : OUT STD_LOGIC ;
nan : OUT STD_LOGIC ;
clk_en : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
zero : OUT STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
overflow <= sub_wire0;
underflow <= sub_wire1;
nan <= sub_wire2;
zero <= sub_wire3;
result <= sub_wire4(31 DOWNTO 0);
altfp_exp0_altfp_exp_vdg_component : altfp_exp0_altfp_exp_vdg
PORT MAP (
clk_en => clk_en,
clock => clock,
aclr => aclr,
data => data,
overflow => sub_wire0,
underflow => sub_wire1,
nan => sub_wire2,
zero => sub_wire3,
result => sub_wire4
);
END RTL;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_exp"
-- Retrieval info: CONSTANT: PIPELINE NUMERIC "17"
-- Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
-- Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT GND "clk_en"
-- Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND "clock"
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: USED_PORT: data 0 0 32 0 INPUT GND "data[31..0]"
-- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-- Retrieval info: USED_PORT: nan 0 0 0 0 OUTPUT GND "nan"
-- Retrieval info: CONNECT: nan 0 0 0 0 @nan 0 0 0 0
-- Retrieval info: USED_PORT: overflow 0 0 0 0 OUTPUT GND "overflow"
-- Retrieval info: CONNECT: overflow 0 0 0 0 @overflow 0 0 0 0
-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT GND "result[31..0]"
-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
-- Retrieval info: USED_PORT: underflow 0 0 0 0 OUTPUT GND "underflow"
-- Retrieval info: CONNECT: underflow 0 0 0 0 @underflow 0 0 0 0
-- Retrieval info: USED_PORT: zero 0 0 0 0 OUTPUT GND "zero"
-- Retrieval info: CONNECT: zero 0 0 0 0 @zero 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL altfp_exp0.vhd TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altfp_exp0.qip TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altfp_exp0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altfp_exp0_inst.vhd FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altfp_exp0.inc FALSE TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altfp_exp0.cmp TRUE TRUE
-- Retrieval info: LIB_FILE: lpm
| gpl-2.0 | d0bfe03dbd870b9cfd0734cd98198b2e | 0.669728 | 2.539861 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/tb_pkg.vhd | 1 | 3,198 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : tb_pkg.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-04-26
-- Last update: 2016-04-26
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Testbench functions
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-04-26 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
package tb_pkg is
procedure clk_gen ( period : in time; duty : in integer; signal clk : out std_logic );
procedure rst_n_gen ( delay : in time; signal rst_n : out std_logic );
procedure run_clk ( signal clk : in std_logic; count : in natural );
end package tb_pkg;
package body tb_pkg is
-- ----------------------------------------------------------------------
-- Generate a clock
--
-- _____ _____
-- | |_____| |_____
--
-- |<--->| Duty cycle
-- |<--------->| Period
--
-- ----------------------------------------------------------------------
procedure clk_gen ( period : in time; duty : in integer; signal clk : out std_logic ) is
variable high : time;
variable low : time;
begin
high := period * duty / 100;
low := period - high;
clk <= '0';
loop
clk <= '1';
wait for high;
clk <= '0';
wait for low;
end loop;
end procedure;
-- ----------------------------------------------------------------------
-- Generate reset
--
-- ________________
-- ____________|
--
-- |<--------->| Delay
--
-- ----------------------------------------------------------------------
procedure rst_n_gen ( delay : in time; signal rst_n : out std_logic ) is
begin
rst_n <= '0';
wait for delay;
rst_n <= '1';
end procedure;
-- ----------------------------------------------------------------------
-- Wait for count cycles of input
--
-- ____________ ____________
-- ____________| |____________|
--
-- |<-- Stops here
--
-- ----------------------------------------------------------------------
procedure run_clk ( signal clk : in std_logic; count : in natural ) is
variable i : natural;
begin
i := count;
while (i > 0) loop
wait until (clk'event and clk = '0');
i := i - 1;
end loop;
end procedure;
end package body tb_pkg;
| gpl-3.0 | 892d1d514b4f14d9ca1734047338b23c | 0.319887 | 5.242623 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/cpu_test.vhd | 1 | 11,613 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : cpu_test.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-03-22
-- Last update: 2016-09-30
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: CPU EPC, GPIO output testbench
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-22 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
use work.tb_pkg.all;
entity cpu is
port (
DDR_addr : inout std_logic_vector (14 downto 0);
DDR_ba : inout std_logic_vector (2 downto 0);
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector (3 downto 0);
DDR_dq : inout std_logic_vector (31 downto 0);
DDR_dqs_n : inout std_logic_vector (3 downto 0);
DDR_dqs_p : inout std_logic_vector (3 downto 0);
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
EPC_INTF_addr : out std_logic_vector (0 to 31);
EPC_INTF_ads : out std_logic;
EPC_INTF_be : out std_logic_vector (0 to 3);
EPC_INTF_burst : out std_logic;
EPC_INTF_clk : in std_logic;
EPC_INTF_cs_n : out std_logic_vector (0 to 0);
EPC_INTF_data_i : in std_logic_vector (0 to 31);
EPC_INTF_data_o : out std_logic_vector (0 to 31);
EPC_INTF_data_t : out std_logic_vector (0 to 31);
EPC_INTF_rd_n : out std_logic;
EPC_INTF_rdy : in std_logic_vector (0 to 0);
EPC_INTF_rnw : out std_logic;
EPC_INTF_rst : in std_logic;
EPC_INTF_wr_n : out std_logic;
FCLK_CLK0 : out std_logic;
FCLK_RESET0_N : out std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
Vp_Vn_v_n : in std_logic;
Vp_Vn_v_p : in std_logic;
GPIO_tri_i : in std_logic_vector (15 downto 0);
GPIO_tri_o : out std_logic_vector (15 downto 0);
GPIO_tri_t : out std_logic_vector (15 downto 0);
IIC_0_scl_i : in std_logic;
IIC_0_scl_o : out std_logic;
IIC_0_scl_t : out std_logic;
IIC_0_sda_i : in std_logic;
IIC_0_sda_o : out std_logic;
IIC_0_sda_t : out std_logic;
IIC_1_scl_i : in std_logic;
IIC_1_scl_o : out std_logic;
IIC_1_scl_t : out std_logic;
IIC_1_sda_i : in std_logic;
IIC_1_sda_o : out std_logic;
IIC_1_sda_t : out std_logic;
IIC_scl_i : in std_logic;
IIC_scl_o : out std_logic;
IIC_scl_t : out std_logic;
IIC_sda_i : in std_logic;
IIC_sda_o : out std_logic;
IIC_sda_t : out std_logic;
UART_0_rxd : in std_logic;
UART_0_txd : out std_logic;
OCXO_CLK100 : in std_logic;
OCXO_RESETN : out std_logic_vector (0 to 0);
Int0 : in std_logic_vector (0 to 0);
Int1 : in std_logic_vector (0 to 0);
Int2 : in std_logic_vector (0 to 0);
Int3 : in std_logic_vector (0 to 0)
);
end cpu;
architecture TEST of cpu is
--SIGNAL DDR_cas_n : std_logic;
--SIGNAL DDR_cke : std_logic;
--SIGNAL DDR_ck_n : std_logic;
--SIGNAL DDR_ck_p : std_logic;
--SIGNAL DDR_cs_n : std_logic;
--SIGNAL DDR_reset_n : std_logic;
--SIGNAL DDR_odt : std_logic;
--SIGNAL DDR_ras_n : std_logic;
--SIGNAL DDR_we_n : std_logic;
--SIGNAL DDR_ba : std_logic_vector (2 downto 0);
--SIGNAL DDR_addr : std_logic_vector (14 downto 0);
--SIGNAL DDR_dm : std_logic_vector (3 downto 0);
--SIGNAL DDR_dq : std_logic_vector (31 downto 0);
--SIGNAL DDR_dqs_n : std_logic_vector (3 downto 0);
--SIGNAL DDR_dqs_p : std_logic_vector (3 downto 0);
--SIGNAL FIXED_IO_mio : std_logic_vector (53 downto 0);
--SIGNAL FIXED_IO_ddr_vrn: std_logic;
--SIGNAL FIXED_IO_ddr_vrp: std_logic;
--SIGNAL FIXED_IO_ps_srstb: std_logic;
--SIGNAL FIXED_IO_ps_clk: std_logic;
--SIGNAL FIXED_IO_ps_porb: std_logic;
--SIGNAL UART_0_txd : std_logic;
--SIGNAL UART_0_rxd : std_logic;
--SIGNAL IIC_0_sda_i : std_logic;
--SIGNAL IIC_0_sda_o : std_logic;
--SIGNAL IIC_0_sda_t : std_logic;
--SIGNAL IIC_0_scl_i : std_logic;
--SIGNAL IIC_0_scl_o : std_logic;
--SIGNAL IIC_0_scl_t : std_logic;
--SIGNAL IIC_1_sda_i : std_logic;
--SIGNAL IIC_1_sda_o : std_logic;
--SIGNAL IIC_1_sda_t : std_logic;
--SIGNAL IIC_1_scl_i : std_logic;
--SIGNAL IIC_1_scl_o : std_logic;
--SIGNAL IIC_1_scl_t : std_logic;
--SIGNAL GPIO_tri_i : std_logic_vector (15 downto 0);
--SIGNAL GPIO_tri_o : std_logic_vector (15 downto 0);
--SIGNAL GPIO_tri_t : std_logic_vector (15 downto 0);
--SIGNAL IIC_scl_i : std_logic;
--SIGNAL IIC_scl_o : std_logic;
--SIGNAL IIC_scl_t : std_logic;
--SIGNAL IIC_sda_i : std_logic;
--SIGNAL IIC_sda_o : std_logic;
--SIGNAL IIC_sda_t : std_logic;
--SIGNAL EPC_INTF_addr: std_logic_vector (0 to 31);
--SIGNAL EPC_INTF_ads : std_logic;
--SIGNAL EPC_INTF_be : std_logic_vector (0 to 3);
--SIGNAL EPC_INTF_burst: std_logic;
--SIGNAL EPC_INTF_clk : std_logic;
--SIGNAL EPC_INTF_cs_n: std_logic_vector (0 to 0);
--SIGNAL EPC_INTF_data_i: std_logic_vector (0 to 31);
--SIGNAL EPC_INTF_data_o: std_logic_vector (0 to 31);
--SIGNAL EPC_INTF_data_t: std_logic_vector (0 to 31);
--SIGNAL EPC_INTF_rd_n: std_logic;
--SIGNAL EPC_INTF_rdy : std_logic_vector (0 to 0);
--SIGNAL EPC_INTF_rnw : std_logic;
--SIGNAL EPC_INTF_rst : std_logic;
--SIGNAL EPC_INTF_wr_n: std_logic;
--SIGNAL FCLK_CLK0 : STD_LOGIC;
--SIGNAL FCLK_RESET0_N: STD_LOGIC;
--SIGNAL M_AXI_GP0_ACLK: STD_LOGIC;
--SIGNAL M_AXI_GP1_ACLK: std_logic;
--SIGNAL ext_reset_in : std_logic;
--SIGNAL ext_reset_in_1: STD_LOGIC;
signal clk : std_logic;
signal fclk : std_logic;
signal rst_n : std_logic;
begin
cpu_ck1: clk_gen(10 ns, 50, fclk);
cpu_rst: rst_n_gen(1 us, fclk_reset0_n);
ocxo_rst: rst_n_gen(1 us, rst_n);
FCLK_CLK0 <= fclk;
clk <= OCXO_CLK100;
OCXO_RESETN(0) <= rst_n;
-- Place holder signal assignments
IIC_0_scl_o <= '0';
IIC_0_scl_t <= '0';
IIC_0_sda_o <= '0';
IIC_0_sda_t <= '0';
IIC_1_scl_o <= '0';
IIC_1_scl_t <= '0';
IIC_1_sda_o <= '0';
IIC_1_sda_t <= '0';
IIC_scl_o <= '0';
IIC_scl_t <= '0';
IIC_sda_o <= '0';
IIC_sda_t <= '0';
UART_0_txd <= '0';
gpio:
process
begin
GPIO_tri_o <= x"00d3";
GPIO_tri_t <= (others => '0');
run_clk(fclk, 12000);
GPIO_tri_o <= x"00c2";
run_clk(fclk, 12000);
GPIO_tri_o <= x"00d3";
GPIO_tri_t <= (others => '0');
run_clk(fclk, 12000);
wait;
end process;
regw:
process
procedure reg_write (addr : in std_logic_vector(31 downto 0);
data : in std_logic_vector(31 downto 0)) is
variable count : natural;
begin
count := 0;
EPC_INTF_addr <= addr;
EPC_INTF_ads <= '1';
EPC_INTF_be <= x"F";
EPC_INTF_cs_n(0) <= '0';
EPC_INTF_data_o <= data;
EPC_INTF_data_t <= (others =>'0');
EPC_INTF_rnw <= '0';
run_clk(clk, 1);
EPC_INTF_ads <= '0';
while (EPC_INTF_rdy(0) /= '1' and count < 10) loop
count := count + 1;
run_clk(clk, 1);
end loop;
EPC_INTF_cs_n(0) <= '1';
EPC_INTF_rnw <= '1';
EPC_INTF_data_t <= (others =>'1');
run_clk(clk, 1);
end procedure;
procedure reg_read (addr : in std_logic_vector(31 downto 0)) is
variable count : natural;
begin
count := 0;
EPC_INTF_addr <= addr;
EPC_INTF_ads <= '1';
EPC_INTF_be <= x"F";
EPC_INTF_cs_n(0) <= '0';
EPC_INTF_data_t <= (others =>'1');
EPC_INTF_rnw <= '1';
run_clk(clk, 1);
EPC_INTF_ads <= '0';
while (EPC_INTF_rdy(0) /= '1' and count < 10) loop
count := count + 1;
run_clk(clk, 1);
end loop;
EPC_INTF_cs_n(0) <= '1';
EPC_INTF_rnw <= '1';
run_clk(clk, 1);
end procedure;
begin
EPC_INTF_addr <= (others =>'0');
EPC_INTF_ads <= '0';
EPC_INTF_be <= (others =>'0');
EPC_INTF_burst <= '0';
EPC_INTF_cs_n <= (others =>'1');
EPC_INTF_data_o <= (others =>'0');
EPC_INTF_data_t <= (others =>'1');
EPC_INTF_rd_n <= '1';
EPC_INTF_rnw <= '1';
EPC_INTF_wr_n <= '1';
run_clk(clk, 2000);
reg_write(x"aaaaaaaa", x"55555555");
run_clk(clk, 100);
reg_read(x"a5a5a5a5");
run_clk(clk, 100);
reg_write(x"00000100", x"12345678");
run_clk(clk, 10000);
reg_write(x"00000200", x"00000080");
run_clk(clk, 100);
reg_read(x"00000000");
run_clk(clk, 100);
reg_read(x"00000314");
run_clk(clk, 100);
reg_read(x"00000100");
run_clk(clk, 10000);
reg_write(x"00000200", x"000000ff");
run_clk(clk, 1000);
reg_read(x"00001004");
run_clk(clk, 1000);
reg_read(x"00001830");
run_clk(clk, 1000);
reg_read(x"00000004");
run_clk(clk, 1000);
reg_write(x"00000300", x"0000004f");
run_clk(clk, 100000);
reg_write(x"00000124", x"000080ff");
run_clk(clk, 100000);
reg_read(x"00000100");
run_clk(clk, 100000);
reg_read(x"00000104");
wait;
end process;
end TEST;
| gpl-3.0 | 207f37695971c3c4931c9a90ea8f27a9 | 0.469302 | 3.195652 | false | false | false | false |
UnofficialRepos/OSVVM | TranscriptPkg.vhd | 1 | 8,693 | --
-- File Name: TranscriptPkg.vhd
-- Design Unit Name: TranscriptPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Define file identifier TranscriptFile
-- provide subprograms to open, close, and print to it.
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.03 Create YAML with files opened during test
-- 12/2020 2020.12 Updated TranscriptOpen parameter Status to InOut to work around simulator bug.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.l1 Added procedure BlankLine
-- 01/2016 2016.01 TranscriptOpen function now calls procedure of same name
-- 01/2015 2015.01 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
package TranscriptPkg is
-- File Identifier to facilitate usage of one transcript file
file TranscriptFile : text ;
-- Cause compile errors if READ_MODE is passed to TranscriptOpen
subtype WRITE_APPEND_OPEN_KIND is FILE_OPEN_KIND range WRITE_MODE to APPEND_MODE ;
-- Open and close TranscriptFile. Function allows declarative opens
procedure TranscriptOpen (Status: InOut FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) ;
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS ;
procedure TranscriptClose ;
impure function IsTranscriptOpen return boolean ;
alias IsTranscriptEnabled is IsTranscriptOpen [return boolean] ;
-- Mirroring. When using TranscriptPkw WriteLine and Print, uses both TranscriptFile and OUTPUT
procedure SetTranscriptMirror (A : boolean := TRUE) ;
impure function IsTranscriptMirrored return boolean ;
alias GetTranscriptMirror is IsTranscriptMirrored [return boolean] ;
-- Write to TranscriptFile when open. Write to OUTPUT when not open or IsTranscriptMirrored
procedure WriteLine(buf : inout line) ;
procedure Print(s : string) ;
-- Create "count" number of blank lines
procedure BlankLine (count : integer := 1) ;
end TranscriptPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TranscriptPkg is
------------------------------------------------------------
type LocalBooleanPType is protected
procedure Set (A : boolean) ;
impure function get return boolean ;
end protected LocalBooleanPType ;
type LocalBooleanPType is protected body
variable GlobalVar : boolean := FALSE ;
procedure Set (A : boolean) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return boolean is
begin
return GlobalVar ;
end function get ;
end protected body LocalBooleanPType ;
file TranscriptYamlFile : text ;
------------------------------------------------------------
shared variable TranscriptEnable : LocalBooleanPType ;
shared variable TranscriptMirror : LocalBooleanPType ;
shared variable TranscriptOpened : LocalBooleanPType ;
------------------------------------------------------------
procedure CreateTranscriptYamlLog (Name : STRING) is
------------------------------------------------------------
variable buf : line ;
begin
-- Create Yaml file with list of files.
if not TranscriptOpened.Get then
file_open(TranscriptYamlFile, "OSVVM_transcript.yml", WRITE_MODE) ;
-- swrite(buf, "Transcripts: ") ;
-- WriteLine(TranscriptYamlFile, buf) ;
TranscriptOpened.Set(TRUE) ;
else
file_open(TranscriptYamlFile, "OSVVM_transcript.yml", APPEND_MODE) ;
end if ;
swrite(buf, " - " & Name) ;
WriteLine(TranscriptYamlFile, buf) ;
file_close(TranscriptYamlFile) ;
end procedure CreateTranscriptYamlLog ;
------------------------------------------------------------
procedure TranscriptOpen (Status: InOut FILE_OPEN_STATUS; ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
begin
file_open(Status, TranscriptFile, ExternalName, OpenKind) ;
if Status = OPEN_OK then
CreateTranscriptYamlLog(ExternalName) ;
TranscriptEnable.Set(TRUE) ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
if Status /= OPEN_OK then
report "TranscriptPkg.TranscriptOpen file: " &
ExternalName & " status is: " & to_string(status) & " and is not OPEN_OK" severity FAILURE ;
end if ;
end procedure TranscriptOpen ;
------------------------------------------------------------
impure function TranscriptOpen (ExternalName: STRING; OpenKind: WRITE_APPEND_OPEN_KIND := WRITE_MODE) return FILE_OPEN_STATUS is
------------------------------------------------------------
variable Status : FILE_OPEN_STATUS ;
begin
TranscriptOpen(Status, ExternalName, OpenKind) ;
return Status ;
end function TranscriptOpen ;
------------------------------------------------------------
procedure TranscriptClose is
------------------------------------------------------------
begin
if TranscriptEnable.Get then
file_close(TranscriptFile) ;
end if ;
TranscriptEnable.Set(FALSE) ;
end procedure TranscriptClose ;
------------------------------------------------------------
impure function IsTranscriptOpen return boolean is
------------------------------------------------------------
begin
return TranscriptEnable.Get ;
end function IsTranscriptOpen ;
------------------------------------------------------------
procedure SetTranscriptMirror (A : boolean := TRUE) is
------------------------------------------------------------
begin
TranscriptMirror.Set(A) ;
end procedure SetTranscriptMirror ;
------------------------------------------------------------
impure function IsTranscriptMirrored return boolean is
------------------------------------------------------------
begin
return TranscriptMirror.Get ;
end function IsTranscriptMirrored ;
------------------------------------------------------------
procedure WriteLine(buf : inout line) is
------------------------------------------------------------
begin
if not TranscriptEnable.Get then
WriteLine(OUTPUT, buf) ;
elsif TranscriptMirror.Get then
TEE(TranscriptFile, buf) ;
else
WriteLine(TranscriptFile, buf) ;
end if ;
end procedure WriteLine ;
------------------------------------------------------------
procedure Print(s : string) is
------------------------------------------------------------
variable buf : line ;
begin
write(buf, s) ;
WriteLine(buf) ;
end procedure Print ;
------------------------------------------------------------
procedure BlankLine (count : integer := 1) is
------------------------------------------------------------
begin
for i in 1 to count loop
print("") ;
end loop ;
end procedure Blankline ;
end package body TranscriptPkg ; | artistic-2.0 | 9e728b867ba1dcc62d759dcc4a02d0a0 | 0.550673 | 5.071762 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/example_design/k7_sfifo_15x128_exdes.vhd | 1 | 5,160 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity k7_sfifo_15x128_exdes is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end k7_sfifo_15x128_exdes;
architecture xilinx of k7_sfifo_15x128_exdes is
signal clk_i : std_logic;
component k7_sfifo_15x128 is
PORT (
CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
exdes_inst : k7_sfifo_15x128
PORT MAP (
CLK => clk_i,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | 44b4f4771b9188feb02d74d39bb82685 | 0.518605 | 4.886364 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/and_component.vhd | 1 | 1,358 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 06-04-2017
-- Package Name: alu_component
-- Module Name: AND_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity AND_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end entity;
architecture AND_COMPONENT_ARCH of AND_COMPONENT is
begin
OUTPUT(0) <= INPUT1(0) and INPUT2(0);
OUTPUT(1) <= INPUT1(1) and INPUT2(1);
OUTPUT(2) <= INPUT1(2) and INPUT2(2);
OUTPUT(3) <= INPUT1(3) and INPUT2(3);
OUTPUT(4) <= INPUT1(4) and INPUT2(4);
OUTPUT(5) <= INPUT1(5) and INPUT2(5);
OUTPUT(6) <= INPUT1(6) and INPUT2(6);
OUTPUT(7) <= INPUT1(7) and INPUT2(7);
OUTPUT(8) <= INPUT1(8) and INPUT2(8);
OUTPUT(9) <= INPUT1(9) and INPUT2(9);
OUTPUT(10) <= INPUT1(10) and INPUT2(10);
OUTPUT(11) <= INPUT1(11) and INPUT2(11);
OUTPUT(12) <= INPUT1(12) and INPUT2(12);
OUTPUT(13) <= INPUT1(13) and INPUT2(13);
OUTPUT(14) <= INPUT1(14) and INPUT2(14);
OUTPUT(15) <= INPUT1(15) and INPUT2(15);
end architecture;
| gpl-3.0 | b81072109b25e6fdbf2c46ccdc5a93eb | 0.522091 | 3.044843 | false | false | false | false |
dcsun88/ntpserver-fpga | sv/ip/ocxo_clk_pll/ocxo_clk_pll_funcsim.vhdl | 1 | 7,866 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Fri Nov 2 15:01:50 2018
-- Host : graviton running 64-bit Debian GNU/Linux 7.11 (wheezy)
-- Command : write_vhdl -force -mode funcsim
-- /home/guest/cae/fpga/ntpserver/sv/ip/ocxo_clk_pll/ocxo_clk_pll_funcsim.vhdl
-- Design : ocxo_clk_pll
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ocxo_clk_pll_ocxo_clk_pll_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ocxo_clk_pll_ocxo_clk_pll_clk_wiz : entity is "ocxo_clk_pll_clk_wiz";
end ocxo_clk_pll_ocxo_clk_pll_clk_wiz;
architecture STRUCTURE of ocxo_clk_pll_ocxo_clk_pll_clk_wiz is
signal clk_in1_ocxo_clk_pll : STD_LOGIC;
signal clkfbout_ocxo_clk_pll : STD_LOGIC;
signal reset_high : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_ocxo_clk_pll
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 63.750000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 100.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 6.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_ocxo_clk_pll,
CLKFBOUT => clkfbout_ocxo_clk_pll,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_ocxo_clk_pll,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => reset_high
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => reset_high
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ocxo_clk_pll is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ocxo_clk_pll : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of ocxo_clk_pll : entity is "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ocxo_clk_pll;
architecture STRUCTURE of ocxo_clk_pll is
begin
inst: entity work.ocxo_clk_pll_ocxo_clk_pll_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
| gpl-3.0 | 8f83c1854fc2708a1e0f809206fc791e | 0.623697 | 3.205379 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/reg_interface.vhd | 2 | 58,470 | -------------------------------------------------------------------------------
-- reg_interface.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: reg_interface.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the interface between the IPIF
-- and the iic controller. All registers are generated
-- here and all interrupts are processed here.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.or_reduce;
use ieee.std_logic_arith.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
library unisim;
use unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_TX_FIFO_BITS -- Transmit FIFO bit size
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_RC_FIFO_BITS -- Receive FIFO bit size
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_S_AXI_DATA_WIDTH -- Slave bus data width
-- C_NUM_IIC_REGS -- Number of IIC Registers
--
-- Definition of Ports:
-- Clk -- System clock
-- Rst -- System reset
-- Bus2IIC_Addr -- Bus to IIC address bus
-- Bus2IIC_Data -- Bus to IIC data bus
-- Bus2IIC_WrCE -- Bus to IIC write chip enable
-- Bus2IIC_RdCE -- Bus to IIC read chip enable
-- IIC2Bus_Data -- IIC to Bus data bus
-- IIC2Bus_IntrEvent -- IIC Interrupt events
-- Gpo -- General purpose outputs
-- Cr -- Control register
-- Msms_rst -- MSMS reset signal
-- Rsta_rst -- Repeated start reset
-- Msms_set -- MSMS set
-- DynMsmsSet -- Dynamic MSMS set signal
-- DynRstaSet -- Dynamic repeated start set signal
-- Cr_txModeSelect_set -- Sets transmit mode select
-- Cr_txModeSelect_clr -- Clears transmit mode select
-- Aas -- Addressed as slave indicator
-- Bb -- Bus busy indicator
-- Srw -- Slave read/write indicator
-- Abgc -- Addressed by general call indicator
-- Dtr -- Data transmit register
-- Rdy_new_xmt -- New data loaded in shift reg indicator
-- Dtre -- Data transmit register empty
-- Drr -- Data receive register
-- Data_i2c -- IIC data for processor
-- New_rcv_dta -- New Receive Data ready
-- Ro_prev -- Receive over run prevent
-- Adr -- IIC slave address
-- Ten_adr -- IIC slave 10 bit address
-- Al -- Arbitration lost indicator
-- Txer -- Received acknowledge indicator
-- Tx_under_prev -- DTR or Tx FIFO empty IRQ indicator
-- Tx_fifo_data -- FIFO data to transmit
-- Tx_data_exists -- next FIFO data exists
-- Tx_fifo_wr -- Decode to enable writes to FIFO
-- Tx_fifo_rd -- Decode to enable read from FIFO
-- Tx_fifo_rst -- Reset Tx FIFO on IP Reset or CR(6)
-- Tx_fifo_Full -- Transmit FIFO full indicator
-- Tx_addr -- Transmit FIFO address
-- Rc_fifo_data -- Read Fifo data for AXI
-- Rc_fifo_wr -- Write IIC data to fifo
-- Rc_fifo_rd -- AXI read from fifo
-- Rc_fifo_Full -- Read Fifo is full prevent rcv overrun
-- Rc_data_Exists -- Next FIFO data exists
-- Rc_addr -- Receive FIFO address
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity reg_interface is
generic(
C_SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_TX_FIFO_BITS : integer := 4;
C_RC_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_BITS : integer := 4;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_DATA_WIDTH : integer := 32;
C_SIZE : integer := 32;
C_NUM_IIC_REGS : integer;
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port(
-- IPIF Interface Signals
Clk : in std_logic;
Rst : in std_logic;
Bus2IIC_Addr : in std_logic_vector (0 to C_S_AXI_ADDR_WIDTH-1);
Bus2IIC_Data : in std_logic_vector (0 to C_S_AXI_DATA_WIDTH - 1);
Bus2IIC_WrCE : in std_logic_vector (0 to C_NUM_IIC_REGS - 1);
Bus2IIC_RdCE : in std_logic_vector (0 to C_NUM_IIC_REGS - 1);
IIC2Bus_Data : out std_logic_vector (0 to C_S_AXI_DATA_WIDTH - 1);
IIC2Bus_IntrEvent : out std_logic_vector (0 to 7);
-- Internal iic Bus Registers
-- GPO Register Offset 124h
Gpo : out std_logic_vector(32 - C_GPO_WIDTH to
C_S_AXI_DATA_WIDTH - 1);
-- Control Register Offset 100h
Cr : out std_logic_vector(0 to 7);
Msms_rst : in std_logic;
Rsta_rst : in std_logic;
Msms_set : out std_logic;
DynMsmsSet : in std_logic;
DynRstaSet : in std_logic;
Cr_txModeSelect_set : in std_logic;
Cr_txModeSelect_clr : in std_logic;
-- Status Register Offest 04h
Aas : in std_logic;
Bb : in std_logic;
Srw : in std_logic;
Abgc : in std_logic;
-- Data Transmit Register Offset 108h
Dtr : out std_logic_vector(0 to 7);
Rdy_new_xmt : in std_logic;
Dtre : out std_logic;
-- Data Receive Register Offset 10Ch
Drr : out std_logic_vector(0 to 7);
Data_i2c : in std_logic_vector(0 to 7);
New_rcv_dta : in std_logic;
Ro_prev : out std_logic;
-- Address Register Offset 10h
Adr : out std_logic_vector(0 to 7);
-- Ten Bit Address Register Offset 1Ch
Ten_adr : out std_logic_vector(5 to 7) := (others => '0');
Al : in std_logic;
Txer : in std_logic;
Tx_under_prev : in std_logic;
-- Timing Parameters to iic_control
Timing_param_tsusta : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsusto : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thdsta : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tsudat : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tbuf : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thigh : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_tlow : out std_logic_vector(C_SIZE-1 downto 0);
Timing_param_thddat : out std_logic_vector(C_SIZE-1 downto 0);
-- FIFO input (fifo write) and output (fifo read)
Tx_fifo_data : in std_logic_vector(0 to 7);
Tx_data_exists : in std_logic;
Tx_fifo_wr : out std_logic;
Tx_fifo_rd : out std_logic;
Tx_fifo_rst : out std_logic;
Tx_fifo_Full : in std_logic;
Tx_addr : in std_logic_vector(0 to C_TX_FIFO_BITS - 1);
Rc_fifo_data : in std_logic_vector(0 to 7);
Rc_fifo_wr : out std_logic;
Rc_fifo_rd : out std_logic;
Rc_fifo_Full : in std_logic;
Rc_data_Exists : in std_logic;
Rc_addr : in std_logic_vector(0 to C_RC_FIFO_BITS - 1);
reg_empty : in std_logic
);
end reg_interface;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of reg_interface is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
----------------------------------------------------------------------------
-- Constant Declarations
----------------------------------------------------------------------------
-- Calls the function from the iic_pkg.vhd
--constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
constant IIC_CNT : integer := (C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ - 14);
-- Calls the function from the iic_pkg.vhd
--constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
-- number of SYSCLK in iic SCL High time
constant HIGH_CNT : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/2 - C_SCL_INERTIAL_DELAY, C_SIZE);
-- number of SYSCLK in iic SCL Low time
constant LOW_CNT : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/2 - C_SCL_INERTIAL_DELAY, C_SIZE);
-- half of HIGH_CNT
constant HIGH_CNT_2 : std_logic_vector(C_SIZE-1 downto 0)
:= conv_std_logic_vector(IIC_CNT/4, C_SIZE);
----------------------------------------------------------------------------
-- Function calc_tsusta
--
-- This function returns Setup time integer value for repeated start for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsusta (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate setup time for repeated start condition depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.7 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/175438, C_SIZE);
-- Added to have 5.7 us (tr+tsu-sta)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tr+tsu-sta)
else
-- Fast Mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tr+tsu-sta)
end if;
end FUNCTION calc_tsusta;
----------------------------------------------------------------------------
-- Function calc_tsusto
--
-- This function returns Setup time integer value for stop condition for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsusto (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate setup time for stop condition depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.0 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/200000, C_SIZE);
-- Added to have 5 us (tr+tsu-sto)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tr+tsu-sto)
else
-- Fast-mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tr+tsu-sto)
end if;
end FUNCTION calc_tsusto;
----------------------------------------------------------------------------
-- Function calc_thdsta
--
-- This function returns Hold time integer value for reapeted start for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_thdsta (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate (repeated) START hold time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.0 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/232558, C_SIZE);
-- Added to have 4.3 us (tf+thd-sta)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 0.6 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1111111, C_SIZE);
-- Added to have 0.9 us (tf+thd-sta)
else
-- Fast-mode Plus timing is 0.26 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2631579, C_SIZE);
-- Added to have 0.380 us (tf+thd-sta)
end if;
end FUNCTION calc_thdsta;
----------------------------------------------------------------------------
-- Function calc_tsudat
--
-- This function returns Data Setup time integer value for
-- Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tsudat (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data setup time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 250 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1818181, C_SIZE);
-- Added to have 550 ns (tf+tsu-dat)
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 100 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/2500000, C_SIZE);
-- Added to have 400 ns (tf+tsu-dat)
else
-- Fast-mode Plus timing is 50 ns
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/5882353, C_SIZE);
-- Added to have 170 ns (tf+tsu-dat)
end if;
end FUNCTION calc_tsudat;
----------------------------------------------------------------------------
-- Function calc_tbuf
--
-- This function returns Bus free time between a STOP and START condition
-- integer value for Standerd mode or Fast mode opertation.
----------------------------------------------------------------------------
FUNCTION calc_tbuf (
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data setup time depending on the
-- mode {standard, fast}
if (C_IIC_FREQ <= 100000) then
-- Standard Mode timing 4.7 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/200000, C_SIZE);
-- Added to have 5 us
elsif (C_IIC_FREQ <= 400000) then
-- Fast Mode timing is 1.3 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/625000, C_SIZE);
-- Added to have 1.6 us
else
-- Fast-mode Plus timing is 0.5 us
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/1612904, C_SIZE);
-- Added to have 0.62 us
end if;
end FUNCTION calc_tbuf;
----------------------------------------------------------------------------
-- Function calc_thddat
--
-- This function returns the data hold time integer value for I2C and
-- SMBus/PMBus protocols.
----------------------------------------------------------------------------
FUNCTION calc_thddat (
constant C_SMBUS_PMBUS_HOST : integer;
constant C_IIC_FREQ : integer;
constant C_S_AXI_ACLK_FREQ_HZ : integer;
constant C_SIZE : integer)
RETURN std_logic_vector is
begin
-- Calculate data hold time depending on SMBus/PMBus compatability
if (C_SMBUS_PMBUS_HOST = 1) then
-- hold time of 300 ns for SMBus/PMBus
RETURN conv_std_logic_vector(C_S_AXI_ACLK_FREQ_HZ/3333334, C_SIZE);
else
-- hold time of 0 ns for normal I2C
RETURN conv_std_logic_vector(1, C_SIZE);
end if;
end FUNCTION calc_thddat;
-- Set-up time for a repeated start
constant TSUSTA : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsusta(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Set-up time for a stop
constant TSUSTO : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsusto(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Hold time (repeated) START condition. After this period, the first clock
-- pulse is generated.
constant THDSTA : std_logic_vector(C_SIZE-1 downto 0)
:= calc_thdsta(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Data setup time.
constant TSUDAT : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tsudat(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Bus free time.
constant TBUF : std_logic_vector(C_SIZE-1 downto 0)
:= calc_tbuf(C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
-- Data Hold time
constant THDDAT : std_logic_vector(C_SIZE-1 downto 0)
:= calc_thddat(C_SMBUS_PMBUS_HOST, C_IIC_FREQ, C_S_AXI_ACLK_FREQ_HZ, C_SIZE);
----------------------------------------------------------------------------
-- Signal and Type Declarations
----------------------------------------------------------------------------
signal cr_i : std_logic_vector(0 to 7); -- intrnl control reg
signal sr_i : std_logic_vector(0 to 7); -- intrnl statuss reg
signal dtr_i : std_logic_vector(0 to 7); -- intrnl dta trnsmt reg
signal drr_i : std_logic_vector(0 to 7); -- intrnl dta receive reg
signal adr_i : std_logic_vector(0 to 7); -- intrnl slave addr reg
signal rc_fifo_pirq_i : std_logic_vector(4 to 7); -- intrnl slave addr reg
signal ten_adr_i : std_logic_vector(5 to 7) := (others => '0');
-- intrnl slave addr reg
signal ro_a : std_logic; -- receive overrun SRFF
signal ro_i : std_logic; -- receive overrun SRFF
signal dtre_i : std_logic; -- data tranmit register empty register
signal new_rcv_dta_d1 : std_logic; -- delay new_rcv_dta to find rising edge
signal msms_d1 : std_logic; -- delay msms cr(5)
signal ro_prev_i : std_logic; -- internal Ro_prev
signal msms_set_i : std_logic; -- SRFF set on falling edge of msms
signal rtx_i : std_logic_vector(0 to 7);
signal rrc_i : std_logic_vector(0 to 7);
signal rtn_i : std_logic_vector(0 to 7);
signal rpq_i : std_logic_vector(0 to 7);
signal gpo_i : std_logic_vector(32 - C_GPO_WIDTH to 31); -- GPO
signal timing_param_tsusta_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tsusto_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thdsta_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tsudat_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tbuf_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thigh_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_tlow_i : std_logic_vector(C_SIZE-1 downto 0);
signal timing_param_thddat_i : std_logic_vector(C_SIZE-1 downto 0);
signal rback_data : std_logic_vector(0 to 32 * C_NUM_IIC_REGS - 1)
:= (others => '0');
begin
----------------------------------------------------------------------------
-- CONTROL_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the control register is enabled.
----------------------------------------------------------------------------
CONTROL_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
cr_i <= (others => '0');
elsif -- Load Control Register with AXI
-- data if there is a write request
-- and the control register is enabled
Bus2IIC_WrCE(0) = '1' then
cr_i(0 to 7) <= Bus2IIC_Data(24 to 31);
else -- Load Control Register with iic data
cr_i(0) <= cr_i(0);
cr_i(1) <= cr_i(1);
cr_i(2) <= (cr_i(2) or DynRstaSet) and not(Rsta_rst);
cr_i(3) <= cr_i(3);
cr_i(4) <= (cr_i(4) or Cr_txModeSelect_set) and
not(Cr_txModeSelect_clr);
cr_i(5) <= (cr_i(5) or DynMsmsSet) and not (Msms_rst);
cr_i(6) <= cr_i(6);
cr_i(7) <= cr_i(7);
end if;
end if;
end process CONTROL_REGISTER_PROCESS;
Cr <= cr_i;
----------------------------------------------------------------------------
-- Delay msms by one clock to find falling edge
----------------------------------------------------------------------------
MSMS_DELAY_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
msms_d1 <= '0';
else
msms_d1 <= cr_i(5);
end if;
end if;
end process MSMS_DELAY_PROCESS;
----------------------------------------------------------------------------
-- Set when a fall edge of msms has occurred and Ro_prev is active
-- This will prevent a throttle condition when a master receiver and
-- trying to initiate a stop condition.
----------------------------------------------------------------------------
MSMS_EDGE_SET_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
msms_set_i <= '0';
elsif ro_prev_i = '1' and cr_i(5) = '0' and msms_d1 = '1' then
msms_set_i <= '1';
elsif (cr_i(5) = '1' and msms_d1 = '0') or Bb = '0' then
msms_set_i <= '0';
else
msms_set_i <= msms_set_i;
end if;
end if;
end process MSMS_EDGE_SET_PROCESS;
Msms_set <= msms_set_i;
----------------------------------------------------------------------------
-- STATUS_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process resets the status register. The status register is read only
----------------------------------------------------------------------------
STATUS_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
sr_i <= (others => '0');
else -- Load Status Register with iic data
sr_i(0) <= not Tx_data_exists;
sr_i(1) <= not Rc_data_Exists;
sr_i(2) <= Rc_fifo_Full;
sr_i(3) <= Tx_fifo_Full; -- addressed by a general call
sr_i(4) <= Srw; -- slave read/write
sr_i(5) <= Bb; -- bus busy
sr_i(6) <= Aas; -- addressed as slave
sr_i(7) <= Abgc; -- addressed by a general call
end if;
end if;
end process STATUS_REGISTER_PROCESS;
----------------------------------------------------------------------------
-- Transmit FIFO CONTROL signal GENERATION
----------------------------------------------------------------------------
-- This process allows the AXI to write data to the write FIFO and assigns
-- that data to the output port and to the internal signals for reading
----------------------------------------------------------------------------
FIFO_GEN_DTR : if C_TX_FIFO_EXIST generate
-------------------------------------------------------------------------
-- FIFO_WR_CNTL_PROCESS - Tx fifo write process
-------------------------------------------------------------------------
FIFO_WR_CNTL_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
Tx_fifo_wr <= '0';
elsif
Bus2IIC_WrCE(2) = '1' then
Tx_fifo_wr <= '1';
else
Tx_fifo_wr <= '0';
end if;
end if;
end process FIFO_WR_CNTL_PROCESS;
-------------------------------------------------------------------------
-- FIFO_DTR_REG_PROCESS
-------------------------------------------------------------------------
FIFO_DTR_REG_PROCESS : process (Tx_fifo_data)
begin -- process
Dtr <= Tx_fifo_data;
dtr_i <= Tx_fifo_data;
end process FIFO_DTR_REG_PROCESS;
-------------------------------------------------------------------------
-- Tx_FIFO_RD_PROCESS
-------------------------------------------------------------------------
-- This process generates the Read from the Transmit FIFO
-------------------------------------------------------------------------
Tx_FIFO_RD_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
Tx_fifo_rd <= '0';
elsif Rdy_new_xmt = '1' then
Tx_fifo_rd <= '1';
elsif Rdy_new_xmt = '0' --and Tx_data_exists = '1'
then Tx_fifo_rd <= '0';
end if;
end if;
end process Tx_FIFO_RD_PROCESS;
-------------------------------------------------------------------------
-- DTRE_PROCESS
-------------------------------------------------------------------------
-- This process generates the Data Transmit Register Empty Interrupt
-- Interrupt(2)
-------------------------------------------------------------------------
DTRE_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
dtre_i <= '0';
else
dtre_i <= not (Tx_data_exists);
end if;
end if;
end process DTRE_PROCESS;
-------------------------------------------------------------------------
-- Additional FIFO Interrupt
-------------------------------------------------------------------------
-- FIFO_Int_PROCESS generates interrupts back to the IPIF when Tx FIFO
-- exists
-------------------------------------------------------------------------
FIFO_INT_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
IIC2Bus_IntrEvent(7) <= '0';
else
IIC2Bus_IntrEvent(7) <= not Tx_addr(3); -- Tx FIFO half empty
end if;
end if;
end process FIFO_INT_PROCESS;
-------------------------------------------------------------------------
-- Tx_FIFO_RESET_PROCESS
-------------------------------------------------------------------------
-- This process generates the Data Transmit Register Empty Interrupt
-- Interrupt(2)
-------------------------------------------------------------------------
TX_FIFO_RESET_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
Tx_fifo_rst <= '1';
else
Tx_fifo_rst <= cr_i(6);
end if;
end if;
end process TX_FIFO_RESET_PROCESS;
end generate FIFO_GEN_DTR;
Dtre <= dtre_i;
----------------------------------------------------------------------------
-- If a read FIFO exists then generate control signals
----------------------------------------------------------------------------
RD_FIFO_CNTRL : if (C_RC_FIFO_EXIST) generate
-------------------------------------------------------------------------
-- WRITE_TO_READ_FIFO_PROCESS
-------------------------------------------------------------------------
WRITE_TO_READ_FIFO_PROCESS : process (Clk)
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
Rc_fifo_wr <= '0';
-- Load iic Data When new data x-fer complete and not x-mitting
elsif
New_rcv_dta = '1' and new_rcv_dta_d1 = '0' then
Rc_fifo_wr <= '1';
else
Rc_fifo_wr <= '0';
end if;
end if;
end process WRITE_TO_READ_FIFO_PROCESS;
-------------------------------------------------------------------------
-- Assign the Receive FIFO data to the DRR so AXI can read the data
-------------------------------------------------------------------------
AXI_READ_FROM_READ_FIFO_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
Rc_fifo_rd <= '0';
elsif Bus2IIC_RdCE(3) = '1' then
Rc_fifo_rd <= '1';
else
Rc_fifo_rd <= '0';
end if;
end if;
end process AXI_READ_FROM_READ_FIFO_PROCESS;
-------------------------------------------------------------------------
-- Assign the Receive FIFO data to the DRR so AXI can read the data
-------------------------------------------------------------------------
RD_FIFO_DRR_PROCESS : process (Rc_fifo_data)
begin
Drr <= Rc_fifo_data;
drr_i <= Rc_fifo_data;
end process RD_FIFO_DRR_PROCESS;
-------------------------------------------------------------------------
-- Rc_FIFO_PIRQ
-------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the Rc_FIFO_PIRQ register is enabled.
-------------------------------------------------------------------------
Rc_FIFO_PIRQ_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
rc_fifo_pirq_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
Bus2IIC_WrCE(8) = '1' then
rc_fifo_pirq_i(4 to 7) <= Bus2IIC_Data(28 to 31);
else
rc_fifo_pirq_i(4 to 7) <= rc_fifo_pirq_i(4 to 7);
end if;
end if;
end process Rc_FIFO_PIRQ_PROCESS;
-------------------------------------------------------------------------
-- RC_FIFO_FULL_PROCESS
-------------------------------------------------------------------------
-- This process throttles the bus when receiving and the RC_FIFO_PIRQ is
-- equalto the Receive FIFO Occupancy value
-------------------------------------------------------------------------
RC_FIFO_FULL_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
ro_prev_i <= '0';
elsif msms_set_i = '1' then
ro_prev_i <= '0';
elsif (rc_fifo_pirq_i(4) = Rc_addr(3) and
rc_fifo_pirq_i(5) = Rc_addr(2) and
rc_fifo_pirq_i(6) = Rc_addr(1) and
rc_fifo_pirq_i(7) = Rc_addr(0)) and
Rc_data_Exists = '1'
then
ro_prev_i <= '1';
else
ro_prev_i <= '0';
end if;
end if;
end process RC_FIFO_FULL_PROCESS;
Ro_prev <= ro_prev_i;
end generate RD_FIFO_CNTRL;
----------------------------------------------------------------------------
-- RCV_OVRUN_PROCESS
----------------------------------------------------------------------------
-- This process determines when the data receive register has had new data
-- written to it without a read of the old data
----------------------------------------------------------------------------
NEW_RECIEVE_DATA_PROCESS : process (Clk) -- delay new_rcv_dta to find edge
begin
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
new_rcv_dta_d1 <= '0';
else
new_rcv_dta_d1 <= New_rcv_dta;
end if;
end if;
end process NEW_RECIEVE_DATA_PROCESS;
----------------------------------------------------------------------------
-- RCV_OVRUN_PROCESS
----------------------------------------------------------------------------
RCV_OVRUN_PROCESS : process (Clk)
begin
-- SRFF set when new data is received, reset when a read of DRR occurs
-- The second SRFF is set when new data is again received before a
-- read of DRR occurs. This sets the Receive Overrun Status Bit
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
ro_a <= '0';
elsif New_rcv_dta = '1' and new_rcv_dta_d1 = '0' then
ro_a <= '1';
elsif New_rcv_dta = '0' and Bus2IIC_RdCE(3) = '1'
then ro_a <= '0';
else
ro_a <= ro_a;
end if;
end if;
end process RCV_OVRUN_PROCESS;
----------------------------------------------------------------------------
-- ADDRESS_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the address register is enabled.
----------------------------------------------------------------------------
ADDRESS_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
adr_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
-- Bus2IIC_WrReq = '1' and Bus2IIC_WrCE(4) = '1' then
Bus2IIC_WrCE(4) = '1' then
adr_i(0 to 7) <= Bus2IIC_Data(24 to 31);
else
adr_i <= adr_i;
end if;
end if;
end process ADDRESS_REGISTER_PROCESS;
Adr <= adr_i;
--PER_BIT_0_TO_31_GEN : for i in 0 to C_S_AXI_DATA_WIDTH-1 generate
-- BIT_0_TO_31_LOOP : process (rback_data, Bus2IIC_RdCE) is
-- begin
-- if (or_reduce(Bus2IIC_RdCE) = '1') then
-- for m in 0 to C_NUM_IIC_REGS-1 loop
-- if (Bus2IIC_RdCE(m) = '1') then
-- IIC2Bus_Data(i) <= rback_data(m*32 + i);
-- else
-- IIC2Bus_Data(i) <= '0';
-- end if;
-- end loop;
-- else
-- IIC2Bus_Data(i) <= '0';
-- end if;
-- end process BIT_0_TO_31_LOOP;
--end generate PER_BIT_0_TO_31_GEN;
OUTPUT_DATA_GEN_P : process (rback_data, Bus2IIC_RdCE, Bus2IIC_Addr) is
begin
if (or_reduce(Bus2IIC_RdCE) = '1') then
--IIC2Bus_Data <= rback_data((32*TO_INTEGER(unsigned(Bus2IIC_Addr(24 to 29))))
-- to ((32*TO_INTEGER(unsigned(Bus2IIC_Addr(24 to 29))))+31)); -- CR
--case Bus2IIC_Addr(C_S_AXI_ADDR_WIDTH-8 to C_S_AXI_ADDR_WIDTH-1) is
case Bus2IIC_Addr(1 to 8) is
when X"00" => IIC2Bus_Data <= rback_data(0 to 31); -- CR
when X"04" => IIC2Bus_Data <= rback_data(32 to 63); -- SR
when X"08" => IIC2Bus_Data <= rback_data(64 to 95); -- TX_FIFO
when X"0C" => IIC2Bus_Data <= rback_data(96 to 127); -- RX_FIFO
when X"10" => IIC2Bus_Data <= rback_data(128 to 159); -- ADR
when X"14" => IIC2Bus_Data <= rback_data(160 to 191); -- TX_FIFO_OCY
when X"18" => IIC2Bus_Data <= rback_data(192 to 223); -- RX_FIFO_OCY
when X"1C" => IIC2Bus_Data <= rback_data(224 to 255); -- TEN_ADR
when X"20" => IIC2Bus_Data <= rback_data(256 to 287); -- RX_FIFO_PIRQ
when X"24" => IIC2Bus_Data <= rback_data(288 to 319); -- GPO
when X"28" => IIC2Bus_Data <= rback_data(320 to 351); -- TSUSTA
when X"2C" => IIC2Bus_Data <= rback_data(352 to 383); -- TSUSTO
when X"30" => IIC2Bus_Data <= rback_data(384 to 415); -- THDSTA
when X"34" => IIC2Bus_Data <= rback_data(416 to 447); -- TSUDAT
when X"38" => IIC2Bus_Data <= rback_data(448 to 479); -- TBUF
when X"3C" => IIC2Bus_Data <= rback_data(480 to 511); -- THIGH
when X"40" => IIC2Bus_Data <= rback_data(512 to 543); -- TLOW
when X"44" => IIC2Bus_Data <= rback_data(544 to 575); -- THDDAT
when others => IIC2Bus_Data <= (others => '0');
end case;
else
IIC2Bus_Data <= (others => '0');
end if;
end process OUTPUT_DATA_GEN_P;
----------------------------------------------------------------------------
-- READ_REGISTER_PROCESS
----------------------------------------------------------------------------
rback_data(32*1-8 to 32*1-1) <= cr_i(0 to 7);
rback_data(32*2-9 to 32*2-1) <= '0' & sr_i(0 to 7);--reg_empty & sr_i(0 to 7);
rback_data(32*3-8 to 32*3-1) <= dtr_i(0 to 7);
rback_data(32*4-8 to 32*4-1) <= drr_i(0 to 7);
rback_data(32*5-8 to 32*5-2) <= adr_i(0 to 6);
rback_data(32*6-8 to 32*6-1) <= rtx_i(0 to 7);
rback_data(32*7-8 to 32*7-1) <= rrc_i(0 to 7);
rback_data(32*8-8 to 32*8-1) <= rtn_i(0 to 7);
rback_data(32*9-8 to 32*9-1) <= rpq_i(0 to 7);
----------------------------------------------------------------------------
-- GPO_RBACK_GEN generate
----------------------------------------------------------------------------
GPO_RBACK_GEN : if C_GPO_WIDTH /= 0 generate
rback_data(32*10-C_GPO_WIDTH to 32*10-1)
<= gpo_i(32 - C_GPO_WIDTH to C_S_AXI_DATA_WIDTH - 1);
end generate GPO_RBACK_GEN;
rback_data(32*11-C_SIZE to 32*11-1) <= timing_param_tsusta_i(C_SIZE-1 downto 0);
rback_data(32*12-C_SIZE to 32*12-1) <= timing_param_tsusto_i(C_SIZE-1 downto 0);
rback_data(32*13-C_SIZE to 32*13-1) <= timing_param_thdsta_i(C_SIZE-1 downto 0);
rback_data(32*14-C_SIZE to 32*14-1) <= timing_param_tsudat_i(C_SIZE-1 downto 0);
rback_data(32*15-C_SIZE to 32*15-1) <= timing_param_tbuf_i(C_SIZE-1 downto 0);
rback_data(32*16-C_SIZE to 32*16-1) <= timing_param_thigh_i(C_SIZE-1 downto 0);
rback_data(32*17-C_SIZE to 32*17-1) <= timing_param_tlow_i(C_SIZE-1 downto 0);
rback_data(32*18-C_SIZE to 32*18-1) <= timing_param_thddat_i(C_SIZE-1 downto 0);
rtx_i(0 to 3) <= (others => '0');
rtx_i(4) <= Tx_addr(3);
rtx_i(5) <= Tx_addr(2);
rtx_i(6) <= Tx_addr(1);
rtx_i(7) <= Tx_addr(0);
rrc_i(0 to 3) <= (others => '0');
rrc_i(4) <= Rc_addr(3);
rrc_i(5) <= Rc_addr(2);
rrc_i(6) <= Rc_addr(1);
rrc_i(7) <= Rc_addr(0);
rtn_i(0 to 4) <= (others => '0');
rtn_i(5 to 7) <= ten_adr_i(5 to 7);
rpq_i(0 to 3) <= (others => '0');
rpq_i(4 to 7) <= rc_fifo_pirq_i(4 to 7);
----------------------------------------------------------------------------
-- Interrupts
----------------------------------------------------------------------------
-- Int_PROCESS generates interrupts back to the IPIF
----------------------------------------------------------------------------
INT_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
IIC2Bus_IntrEvent(0 to 6) <= (others => '0');
else
IIC2Bus_IntrEvent(0) <= Al; -- arbitration lost interrupt
IIC2Bus_IntrEvent(1) <= Txer; -- transmit error interrupt
IIC2Bus_IntrEvent(2) <= Tx_under_prev; --dtre_i;
-- Data Tx Register Empty interrupt
IIC2Bus_IntrEvent(3) <= ro_prev_i; --New_rcv_dta;
-- Data Rc Register Full interrupt
IIC2Bus_IntrEvent(4) <= not Bb;
IIC2Bus_IntrEvent(5) <= Aas;
IIC2Bus_IntrEvent(6) <= not Aas;
end if;
end if;
end process INT_PROCESS;
----------------------------------------------------------------------------
-- Ten Bit Slave Address Generate
----------------------------------------------------------------------------
-- Int_PROCESS generates interrupts back to the IPIF
----------------------------------------------------------------------------
TEN_ADR_GEN : if (C_TEN_BIT_ADR = 1) generate
-------------------------------------------------------------------------
-- TEN_ADR_REGISTER_PROCESS
-------------------------------------------------------------------------
TEN_ADR_REGISTER_PROCESS : process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
ten_adr_i <= (others => '0');
elsif -- Load Status Register with AXI
-- data if there is a write request
-- and the status register is enabled
Bus2IIC_WrCE(7) = '1' then
ten_adr_i(5 to 7) <= Bus2IIC_Data(29 to 31);
else
ten_adr_i <= ten_adr_i;
end if;
end if;
end process TEN_ADR_REGISTER_PROCESS;
Ten_adr <= ten_adr_i;
end generate TEN_ADR_GEN;
----------------------------------------------------------------------------
-- General Purpose Ouput Register Generate
----------------------------------------------------------------------------
-- Generate the GPO if C_GPO_WIDTH is not equal to zero
----------------------------------------------------------------------------
GPO_GEN : if (C_GPO_WIDTH /= 0) generate
-------------------------------------------------------------------------
-- GPO_REGISTER_PROCESS
-------------------------------------------------------------------------
GPO_REGISTER_PROCESS : process (Clk)
begin -- process
if Clk'event and Clk = '1' then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
gpo_i <= C_DEFAULT_VALUE(C_GPO_WIDTH - 1 downto 0);
elsif -- Load Status Register with AXI
-- data if there is a write CE
--Bus2IIC_WrCE(C_NUM_IIC_REGS - 1) = '1' then
Bus2IIC_WrCE(9) = '1' then
gpo_i(32 - C_GPO_WIDTH to 31) <=
Bus2IIC_Data(32 - C_GPO_WIDTH to 31);
else
gpo_i <= gpo_i;
end if;
end if;
end process GPO_REGISTER_PROCESS;
Gpo <= gpo_i;
end generate GPO_GEN;
----------------------------------------------------------------------------
-- TSUSTA_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tsusta register is enabled.
----------------------------------------------------------------------------
TSUSTA_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
--timing_param_tsusta_i <= (others => '0');
timing_param_tsusta_i <= TSUSTA;
elsif -- Load tsusta Register with AXI
-- data if there is a write request
-- and the tsusta register is enabled
Bus2IIC_WrCE(10) = '1' then
timing_param_tsusta_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsusta_i(C_SIZE-1 downto 0) <= timing_param_tsusta_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUSTA_REGISTER_PROCESS;
Timing_param_tsusta <= timing_param_tsusta_i;
----------------------------------------------------------------------------
-- TSUSTO_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tsusto register is enabled.
----------------------------------------------------------------------------
TSUSTO_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
--timing_param_tsusto_i <= (others => '0');
timing_param_tsusto_i <= TSUSTO;
elsif -- Load tsusto Register with AXI
-- data if there is a write request
-- and the tsusto register is enabled
Bus2IIC_WrCE(11) = '1' then
timing_param_tsusto_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsusto_i(C_SIZE-1 downto 0) <= timing_param_tsusto_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUSTO_REGISTER_PROCESS;
Timing_param_tsusto <= timing_param_tsusto_i;
----------------------------------------------------------------------------
-- THDSTA_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thdsta register is enabled.
----------------------------------------------------------------------------
THDSTA_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
timing_param_thdsta_i <= THDSTA;
elsif -- Load thdsta Register with AXI
-- data if there is a write request
-- and the thdsta register is enabled
Bus2IIC_WrCE(12) = '1' then
timing_param_thdsta_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thdsta_i(C_SIZE-1 downto 0) <= timing_param_thdsta_i(C_SIZE-1 downto 0);
end if;
end if;
end process THDSTA_REGISTER_PROCESS;
Timing_param_thdsta <= timing_param_thdsta_i;
----------------------------------------------------------------------------
-- TSUDAT_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thdsta register is enabled.
----------------------------------------------------------------------------
TSUDAT_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
timing_param_tsudat_i <= TSUDAT;
elsif -- Load tsudat Register with AXI
-- data if there is a write request
-- and the tsudat register is enabled
Bus2IIC_WrCE(13) = '1' then
timing_param_tsudat_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tsudat_i(C_SIZE-1 downto 0) <= timing_param_tsudat_i(C_SIZE-1 downto 0);
end if;
end if;
end process TSUDAT_REGISTER_PROCESS;
Timing_param_tsudat <= timing_param_tsudat_i;
----------------------------------------------------------------------------
-- TBUF_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the tbuf register is enabled.
----------------------------------------------------------------------------
TBUF_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
timing_param_tbuf_i <= TBUF;
elsif -- Load tbuf Register with AXI
-- data if there is a write request
-- and the tbuf register is enabled
Bus2IIC_WrCE(14) = '1' then
timing_param_tbuf_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tbuf_i(C_SIZE-1 downto 0) <= timing_param_tbuf_i(C_SIZE-1 downto 0);
end if;
end if;
end process TBUF_REGISTER_PROCESS;
Timing_param_tbuf <= timing_param_tbuf_i;
----------------------------------------------------------------------------
-- THIGH_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thigh register is enabled.
----------------------------------------------------------------------------
THIGH_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
timing_param_thigh_i <= HIGH_CNT;
elsif -- Load thigh Register with AXI
-- data if there is a write request
-- and the thigh register is enabled
Bus2IIC_WrCE(15) = '1' then
timing_param_thigh_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thigh_i(C_SIZE-1 downto 0) <= timing_param_thigh_i(C_SIZE-1 downto 0);
end if;
end if;
end process THIGH_REGISTER_PROCESS;
Timing_param_thigh <= timing_param_thigh_i;
----------------------------------------------------------------------------
-- TLOW_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thigh register is enabled.
----------------------------------------------------------------------------
TLOW_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
timing_param_tlow_i <= LOW_CNT;
elsif -- Load tlow Register with AXI
-- data if there is a write request
-- and the tlow register is enabled
Bus2IIC_WrCE(16) = '1' then
timing_param_tlow_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_tlow_i(C_SIZE-1 downto 0) <= timing_param_tlow_i(C_SIZE-1 downto 0);
end if;
end if;
end process TLOW_REGISTER_PROCESS;
Timing_param_tlow <= timing_param_tlow_i;
----------------------------------------------------------------------------
-- THDDAT_REGISTER_PROCESS
----------------------------------------------------------------------------
-- This process loads data from the AXI when there is a write request and
-- the thddat register is enabled.
----------------------------------------------------------------------------
THDDAT_REGISTER_PROCESS: process (Clk)
begin -- process
if (Clk'event and Clk = '1') then
if Rst = axi_iic_v2_0.iic_pkg.RESET_ACTIVE then
timing_param_thddat_i <= THDDAT;
elsif -- Load thddat Register with AXI
-- data if there is a write request
-- and the thddat register is enabled
Bus2IIC_WrCE(17) = '1' then
timing_param_thddat_i(C_SIZE-1 downto 0) <= Bus2IIC_Data(C_S_AXI_DATA_WIDTH-C_SIZE to C_S_AXI_DATA_WIDTH-1);
else -- Load Control Register with iic data
timing_param_thddat_i(C_SIZE-1 downto 0) <= timing_param_thddat_i(C_SIZE-1 downto 0);
end if;
end if;
end process THDDAT_REGISTER_PROCESS;
Timing_param_thddat <= timing_param_thddat_i;
end architecture RTL;
| gpl-3.0 | d6d3f50796b8d9916030b3d6f60bf204 | 0.452762 | 4.16542 | false | false | false | false |
peteut/nvc | test/regress/issue371.vhd | 2 | 1,834 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue371 is
end issue371;
architecture behav of issue371 is
signal clock : std_logic;
signal chip_select_sig : std_logic;
signal address_sig : std_logic_vector(2 downto 0);
signal write_sig : std_logic;
signal host_data_bus_sig : std_logic_vector(7 downto 0);
procedure wait_for_ticks (num_clock_cycles : in integer) is
begin
for i in 1 to num_clock_cycles loop
wait until rising_edge(clock);
end loop;
end procedure wait_for_ticks;
procedure host_write (addr: in std_logic_vector;
byte : in std_logic_vector;
signal clock : in std_logic;
signal chip_select : out std_logic;
signal address : out std_logic_vector;
signal write : out std_logic;
signal host_data_bus : out std_logic_vector;
invert_cs_etc : in std_logic
) is
begin
wait until rising_edge(clock);
write <= '1' xor invert_cs_etc;
chip_select <= '1' xor invert_cs_etc;
address <= addr;
host_data_bus <= byte;
wait_for_ticks(1);
write <= '0' xor invert_cs_etc;
chip_select <= '0' xor invert_cs_etc;
for i in address'LOW to address'HIGH loop
address(i) <= '0';
end loop;
for i in host_data_bus'LOW to host_data_bus'HIGH loop
host_data_bus(i) <= '0';
end loop;
wait until rising_edge(clock);
end procedure host_write;
begin
process
begin
for i in 0 to 10 loop
clock <= '0';
wait for 1 us;
clock <= '1';
wait for 1 us;
end loop;
wait;
end process;
process
begin
host_write("001", X"aa", clock, chip_select_sig, address_sig, write_sig, host_data_bus_sig, '0');
for i in address_sig'LOW to address_sig'HIGH loop
assert address_sig(i) = '0';
end loop;
for i in host_data_bus_sig'LOW to host_data_bus_sig'HIGH loop
assert host_data_bus_sig(i) = '0';
end loop;
wait;
end process;
end behav;
| gpl-3.0 | 7f1db310ef32960b8f52dfaf7cd6cc8d | 0.677754 | 2.762048 | false | false | false | false |
UnofficialRepos/OSVVM | ResizePkg.vhd | 1 | 7,303 | --
-- File Name: ResizePkg.vhd
-- Design Unit Name: ResizePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
-- Resizing for transaction records
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2021 2021.06 Refactored from ResolutionPkg
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.AlertLogPkg.all ;
use work.ResolutionPkg.all ;
package ResizePkg is
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector ;
impure function SafeResize(A : std_logic_vector; Size : natural) return std_logic_vector ;
impure function SafeResize(A : std_logic_vector; Size : natural) return std_logic_vector_max_c ;
impure function SafeResize(A : std_logic_vector_max_c; Size : natural) return std_logic_vector ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max_c) return integer ;
--
-- ToTransaction and FromTransaction for _max provided to support a
-- common methodology, conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector ;
function FromTransaction (A: std_logic_vector_max) return integer ;
end package ResizePkg ;
package body ResizePkg is
--
-- ToTransaction and FromTransaction
-- Convert from Common types to their corresponding _max_c type
--
function Extend(A: std_logic_vector; Size : natural) return std_logic_vector is
variable extA : std_logic_vector(Size downto 1) := (others => '0') ;
begin
extA(A'length downto 1) := A ;
return extA ;
end function Extend ;
function Reduce(A: std_logic_vector; Size : natural) return std_logic_vector is
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
return aA(Size-1 downto 0) ;
end function Reduce ;
-- SafeResize - handles std_logic_vector as unsigned
impure function LocalSafeResize(A : std_logic_vector; Size : natural) return std_logic_vector is
variable Result : std_logic_vector(Size-1 downto 0) := (others => '0') ;
alias aA : std_logic_vector(A'length-1 downto 0) is A ;
begin
if A'length <= Size then
-- Extend A
Result(A'length-1 downto 0) := aA ;
else
-- Reduce A and Error if any extra bits of A are a '1'
AlertIf((OR aA(A'length-1 downto Size) = '1'), "ToTransaction/FromTransaction, threw away a 1") ;
Result := aA(Size-1 downto 0) ;
end if ;
return Result ;
end function LocalSafeResize ;
impure function SafeResize(A : std_logic_vector; Size : natural) return std_logic_vector is
begin
return LocalSafeResize(A, Size) ;
end function SafeResize ;
impure function SafeResize(A : std_logic_vector; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(LocalSafeResize(A, Size)) ;
end function SafeResize ;
impure function SafeResize(A : std_logic_vector_max_c; Size : natural) return std_logic_vector is
begin
return LocalSafeResize(std_logic_vector(A), Size) ;
end function SafeResize ;
function ToTransaction(A : std_logic_vector) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(A) ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(LocalSafeResize(A, Size)) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max_c is
begin
return std_logic_vector_max_c(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return std_logic_vector is
begin
return std_logic_vector(A) ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max_c ; Size : natural) return std_logic_vector is
begin
return LocalSafeResize(std_logic_vector(A), Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max_c) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
----------------------
-- Support for _max provided to support a common methodology,
-- conversions are not needed
function ToTransaction(A : std_logic_vector) return std_logic_vector_max is
begin
return A ;
end function ToTransaction ;
impure function ToTransaction(A : std_logic_vector ; Size : natural) return std_logic_vector_max is
begin
return LocalSafeResize(A, Size) ;
end function ToTransaction ;
function ToTransaction(A : integer; Size : natural) return std_logic_vector_max is
begin
return std_logic_vector_max(to_signed(A, Size)) ;
end function ToTransaction ;
function FromTransaction (A: std_logic_vector_max) return std_logic_vector is
begin
return A ;
end function FromTransaction ;
impure function FromTransaction (A: std_logic_vector_max ; Size : natural) return std_logic_vector is
begin
return LocalSafeResize(A, Size) ;
end function FromTransaction ;
function FromTransaction (A: std_logic_vector_max) return integer is
begin
return to_integer(signed(A)) ;
end function FromTransaction ;
end package body ResizePkg ;
| artistic-2.0 | 754c033424daa6406877a9e1deaec079 | 0.698206 | 3.660652 | false | false | false | false |
UnofficialRepos/OSVVM | TextUtilPkg.vhd | 1 | 24,716 | --
-- File Name: TextUtilPkg.vhd
-- Design Unit Name: TextUtilPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Shared Utilities for handling text files
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated to_hxstring to print U, X, Z, W, - when there are 4 in a row and ? for mixed meta
-- Added Justify that aligns LEFT, RIGHT, and CENTER with parameters in a sensible order.
-- 01/2022 2022.01 Added to_hxstring - based on hxwrite (in TbUtilPkg prior to release)
-- 08/2020 2020.08 Added ReadUntilDelimiterOrEOL and FindDelimiter
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Added IsUpper, IsLower, to_upper, to_lower
-- 01/2016 2016.01 Update for L.all(L'left)
-- 01/2015 2015.05 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package TextUtilPkg is
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean ;
function IsLower (constant Char : character ) return boolean ;
function to_lower (constant Char : character ) return character ;
function to_lower (constant Str : string ) return string ;
function to_upper (constant Char : character ) return character ;
function to_upper (constant Str : string ) return string ;
function IsHex (constant Char : character ) return boolean ;
function IsNumber (constant Char : character ) return boolean ;
function IsNumber (Name : string ) return boolean ;
function isstd_logic (constant Char : character ) return boolean ;
-- Crutch until VHDL-2019 conditional initialization
function IfElse(Expr : boolean ; A, B : string) return string ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) ;
procedure SkipWhiteSpace (variable L : InOut line) ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) ;
------------------------------------------------------------
-- to_hxstring
-- print in hex. If string contains X, then also print in binary
------------------------------------------------------------
function to_hxstring ( A : std_ulogic_vector) return string ;
function to_hxstring ( A : unsigned) return string ;
function to_hxstring ( A : signed) return string ;
------------------------------------------------------------
-- Justify
-- w/ Fill Character
-- w/o Fill character, Parameter order & names sensible
------------------------------------------------------------
type AlignType is (RIGHT, LEFT, CENTER) ;
function Justify (
S : string ;
Amount : natural ;
Align : AlignType := LEFT
) return string ;
function Justify (
S : string ;
Fill : character ;
Amount : natural ;
Align : AlignType := LEFT
) return string ;
------------------------------------------------------------
-- FileExists
-- Return TRUE if file exists
------------------------------------------------------------
impure function FileExists(FileName : string) return boolean ;
end TextUtilPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body TextUtilPkg is
type stdulogic_indexby_stdulogic is array (std_ulogic) of std_ulogic;
constant LOWER_TO_UPPER_OFFSET : integer := character'POS('a') - character'POS('A') ;
------------------------------------------------------------
function "-" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) - L) ;
end function "-" ;
------------------------------------------------------------
function "+" (R : character ; L : integer ) return character is
------------------------------------------------------------
begin
return character'VAL(character'pos(R) + L) ;
end function "+" ;
------------------------------------------------------------
function IsUpper (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'A' and Char <= 'Z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsUpper ;
------------------------------------------------------------
function IsLower (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= 'a' and Char <= 'z' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsLower ;
------------------------------------------------------------
function to_lower (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsUpper(Char) then
return Char + LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_lower ;
------------------------------------------------------------
function to_lower (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_lower(Str(i)) ;
end loop ;
return result ;
end function to_lower ;
------------------------------------------------------------
function to_upper (constant Char : character ) return character is
------------------------------------------------------------
begin
if IsLower(Char) then
return Char - LOWER_TO_UPPER_OFFSET ;
else
return Char ;
end if ;
end function to_upper ;
------------------------------------------------------------
function to_upper (constant Str : string ) return string is
------------------------------------------------------------
variable result : string(Str'range) ;
begin
for i in Str'range loop
result(i) := to_upper(Str(i)) ;
end loop ;
return result ;
end function to_upper ;
------------------------------------------------------------
function IsHex (constant Char : character ) return boolean is
------------------------------------------------------------
begin
if Char >= '0' and Char <= '9' then
return TRUE ;
elsif Char >= 'a' and Char <= 'f' then
return TRUE ;
elsif Char >= 'A' and Char <= 'F' then
return TRUE ;
else
return FALSE ;
end if ;
end function IsHex ;
------------------------------------------------------------
function IsNumber (constant Char : character ) return boolean is
------------------------------------------------------------
begin
return Char >= '0' and Char <= '9' ;
end function IsNumber ;
------------------------------------------------------------
function IsNumber (Name : string ) return boolean is
------------------------------------------------------------
begin
for i in Name'range loop
if not IsNumber(Name(i)) then
return FALSE ;
end if ;
end loop ;
return TRUE ;
end function IsNumber ;
------------------------------------------------------------
function isstd_logic (constant Char : character ) return boolean is
------------------------------------------------------------
begin
case Char is
when 'U' | 'X' | '0' | '1' | 'Z' | 'W' | 'L' | 'H' | '-' =>
return TRUE ;
when others =>
return FALSE ;
end case ;
end function isstd_logic ;
------------------------------------------------------------
function IfElse(Expr : boolean ; A, B : string) return string is
------------------------------------------------------------
begin
if Expr then
return A ;
else
return B ;
end if ;
end function IfElse ;
-- ------------------------------------------------------------
-- function iscomment (constant Char : character ) return boolean is
-- ------------------------------------------------------------
-- begin
-- case Char is
-- when '#' | '/' | '-' =>
-- return TRUE ;
-- when others =>
-- return FALSE ;
-- end case ;
-- end function iscomment ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean
) is
variable Valid : boolean ;
variable Char : character ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
Empty := TRUE ;
WhiteSpLoop : while L /= null and L.all'length > 0 loop
if (L.all(L'left) = ' ' or L.all(L'left) = NBSP or L.all(L'left) = HT) then
read (L, Char, Valid) ;
exit when not Valid ;
else
Empty := FALSE ;
return ;
end if ;
end loop WhiteSpLoop ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
procedure SkipWhiteSpace (
------------------------------------------------------------
variable L : InOut line
) is
variable Empty : boolean ;
begin
SkipWhiteSpace(L, Empty) ;
end procedure SkipWhiteSpace ;
------------------------------------------------------------
-- Package Local
procedure FindCommentEnd (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : out boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Char : character ;
begin
MultiLineComment := TRUE ;
Empty := TRUE ;
FindEndOfCommentLoop : while L /= null and L.all'length > 1 loop
read(L, Char, Valid) ;
if Char = '*' and L.all(L'left) = '/' then
read(L, Char, Valid) ;
Empty := FALSE ;
MultiLineComment := FALSE ;
exit FindEndOfCommentLoop ;
end if ;
end loop ;
end procedure FindCommentEnd ;
------------------------------------------------------------
procedure EmptyOrCommentLine (
------------------------------------------------------------
variable L : InOut line ;
variable Empty : InOut boolean ;
variable MultiLineComment : inout boolean
) is
variable Valid : boolean ;
variable Next2Char : string(1 to 2) ;
constant NBSP : CHARACTER := CHARACTER'val(160); -- space character
begin
if MultiLineComment then
FindCommentEnd(L, Empty, MultiLineComment) ;
end if ;
EmptyCheckLoop : while not MultiLineComment loop
SkipWhiteSpace(L, Empty) ;
exit when Empty ; -- line null or 0 in length detected by SkipWhite
Empty := TRUE ;
exit when L.all(L'left) = '#' ; -- shell style comment
if L.all'length >= 2 then
if L'ascending then
Next2Char := L.all(L'left to L'left+1) ;
else
Next2Char := L.all(L'left downto L'left-1) ;
end if;
exit when Next2Char = "//" ; -- C style comment
exit when Next2Char = "--" ; -- VHDL style comment
if Next2Char = "/*" then -- C style multi line comment
FindCommentEnd(L, Empty, MultiLineComment) ;
exit when Empty ;
next EmptyCheckLoop ; -- Found end of comment, restart processing line
end if ;
end if ;
Empty := FALSE ;
exit ;
end loop EmptyCheckLoop ;
end procedure EmptyOrCommentLine ;
------------------------------------------------------------
procedure ReadUntilDelimiterOrEOL(
------------------------------------------------------------
variable L : InOut line ;
variable Name : InOut line ;
constant Delimiter : In character ;
variable ReadValid : Out boolean
) is
variable NameStr : string(1 to L'length) ;
variable ReadLen : integer := 1 ;
variable Good : boolean ;
begin
ReadValid := TRUE ;
for i in NameStr'range loop
Read(L, NameStr(i), Good) ;
ReadValid := ReadValid and Good ;
if NameStr(i) = Delimiter then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i-1)) ;
exit ;
elsif i = NameStr'length then
-- Read(L, NameStr(1 to i), ReadValid) ;
Name := new string'(NameStr(1 to i)) ;
exit ;
end if ;
end loop ;
end procedure ReadUntilDelimiterOrEOL ;
------------------------------------------------------------
procedure FindDelimiter(
------------------------------------------------------------
variable L : InOut line ;
constant Delimiter : In character ;
variable Found : Out boolean
) is
variable Char : Character ;
variable ReadValid : boolean ;
begin
Found := FALSE ;
ReadLoop : loop
if Delimiter /= ' ' then
SkipWhiteSpace(L) ;
end if ;
Read(L, Char, ReadValid) ;
exit when ReadValid = FALSE or Char /= Delimiter ;
Found := TRUE ;
exit ;
end loop ;
end procedure FindDelimiter ;
------------------------------------------------------------
procedure ReadHexToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
constant NumHexChars : integer := (Result'length+3)/4 ;
constant ResultNormLen : integer := NumHexChars * 4 ;
variable NextChar : character ;
variable CharCount : integer ;
variable ReturnVal : std_logic_vector(ResultNormLen-1 downto 0) ;
variable ReadVal : std_logic_vector(3 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if ishex(NextChar) or NextChar = 'X' or NextChar = 'Z' then
hread(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(ResultNormLen-5 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= NumHexChars ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
if CharCount >= NumHexChars then
StrLen := Result'length ;
else
StrLen := CharCount * 4 ;
end if ;
Result := ReturnVal(Result'length-1 downto 0) ;
end procedure ReadHexToken ;
------------------------------------------------------------
procedure ReadBinaryToken (
-- Reads Upto Result'length values, less is ok.
-- Does not skip white space
------------------------------------------------------------
variable L : InOut line ;
variable Result : Out std_logic_vector ;
variable StrLen : Out integer
) is
variable NextChar : character ;
variable CharCount : integer ;
variable ReadVal : std_logic ;
variable ReturnVal : std_logic_vector(Result'length-1 downto 0) ;
variable ReadValid : boolean ;
begin
ReturnVal := (others => '0') ;
CharCount := 0 ;
ReadLoop : while L /= null and L.all'length > 0 loop
NextChar := L.all(L'left) ;
if isstd_logic(NextChar) then
read(L, ReadVal, ReadValid) ;
ReturnVal := ReturnVal(Result'length-2 downto 0) & ReadVal ;
CharCount := CharCount + 1 ;
exit ReadLoop when CharCount >= Result'length ;
elsif NextChar = '_' then
read(L, NextChar, ReadValid) ;
else
exit ;
end if ;
end loop ReadLoop ;
StrLen := CharCount ;
Result := ReturnVal ;
end procedure ReadBinaryToken ;
------------------------------------------------------------
-- RemoveHLTable
-- Convert L to 0 and H to 1, and nothing else
------------------------------------------------------------
constant RemoveHLTable : stdulogic_indexby_stdulogic := (
'U' => 'U',
'X' => 'X',
'0' => '0',
'1' => '1',
'Z' => 'Z',
'W' => 'W',
'L' => '0',
'H' => '1',
'-' => '-'
);
------------------------------------------------------------
-- local
function RemoveHL(A : std_ulogic_vector) return std_ulogic_vector is
------------------------------------------------------------
variable result : A'subtype ;
begin
for i in result'range loop
result(i) := RemoveHLTable(A(i)) ;
end loop ;
return result ;
end function RemoveHL ;
------------------------------------------------------------
-- local_to_hxstring
function local_to_hxstring ( A : std_ulogic_vector; IsSigned : Boolean := TRUE ) return string is
-- Code based on to_hstring from std_logic_1164-body.vhd
-- Copyright 2019 IEEE P1076 WG Authors
-- License: Apache License 2.0 - same as this package
------------------------------------------------------------
constant STRING_LEN : integer := (A'length+3)/4;
variable result : string(1 to STRING_LEN);
constant EXTEND_A_LEN : integer := STRING_LEN*4 ;
variable ExtendedA : std_ulogic_vector(1 to EXTEND_A_LEN) ;
variable PadA : std_ulogic_vector(1 to EXTEND_A_LEN - A'length) ;
variable HexVal : std_ulogic_vector(1 to 4) ;
variable PrintBinary : boolean := FALSE ;
begin
if A'length = 0 then
return "" ;
end if ;
if IsSigned or is_x(A(A'left)) then
PadA := (others => A(A'left)) ;
else
PadA := (others => '0') ;
end if ;
ExtendedA := RemoveHL(PadA & A) ;
for i in result'range loop
HexVal := ExtendedA(4*i-3 to 4*i);
case HexVal is
when X"0" => result(i) := '0';
when X"1" => result(i) := '1';
when X"2" => result(i) := '2';
when X"3" => result(i) := '3';
when X"4" => result(i) := '4';
when X"5" => result(i) := '5';
when X"6" => result(i) := '6';
when X"7" => result(i) := '7';
when X"8" => result(i) := '8';
when X"9" => result(i) := '9';
when X"A" => result(i) := 'A';
when X"B" => result(i) := 'B';
when X"C" => result(i) := 'C';
when X"D" => result(i) := 'D';
when X"E" => result(i) := 'E';
when X"F" => result(i) := 'F';
when "UUUU" => result(i) := 'U';
when "XXXX" => result(i) := 'X';
when "ZZZZ" => result(i) := 'Z';
when "WWWW" => result(i) := 'W';
when "----" => result(i) := '-';
when others => result(i) := '?'; PrintBinary := TRUE ;
end case;
end loop;
if PrintBinary then
return result & " (" & to_string(A) & ")" ;
else
return result ;
end if ;
end function local_to_hxstring;
------------------------------------------------------------
-- to_hxstring
function to_hxstring ( A : std_ulogic_vector) return string is
------------------------------------------------------------
begin
return local_to_hxstring(A, IsSigned => FALSE) ;
end function to_hxstring ;
------------------------------------------------------------
-- to_hxstring
function to_hxstring ( A : unsigned) return string is
------------------------------------------------------------
begin
return local_to_hxstring(std_ulogic_vector(A), IsSigned => FALSE) ;
end function to_hxstring ;
------------------------------------------------------------
-- to_hxstring
function to_hxstring (A : signed) return string is
------------------------------------------------------------
begin
return local_to_hxstring(std_ulogic_vector(A), IsSigned => TRUE) ;
end function to_hxstring ;
------------------------------------------------------------
-- Justify
-- w/ Fill Character
-- w/o Fill character, Parameter order & names sensible
------------------------------------------------------------
function Justify (
S : string ;
Fill : character ;
Amount : natural ;
Align : AlignType := LEFT
) return string is
constant FillLen : integer := maximum(1, Amount - S'length) ;
constant HalfFillLen : integer := (FillLen+1)/2 ;
constant FillString : string(1 to FillLen) := (others => FILL) ;
begin
if S'length >= Amount then
return S ;
end if ;
case Align is
when LEFT => return S & FillString ;
when RIGHT => return FillString & S ;
when CENTER => return FillString(1 to HalfFillLen) & S & FillString(HalfFillLen+1 to FillLen) ;
end case ;
end function Justify ;
function Justify (
S : string ;
Amount : natural ;
Align : AlignType := LEFT
) return string is
begin
return Justify(S, ' ', Amount, Align) ;
end function Justify ;
------------------------------------------------------------
-- FileExists
-- Return TRUE if file exists
------------------------------------------------------------
impure function FileExists(FileName : string) return boolean is
file FileID : text ;
variable status : file_open_status ;
begin
file_open(status, FileID, FileName, READ_MODE) ;
file_close(FileID) ;
return status = OPEN_OK ;
end function FileExists ;
end package body TextUtilPkg ; | artistic-2.0 | b277f25ac63040fcda0826e8609af44b | 0.465002 | 4.681061 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_10/lab10_2/lpm_ram_dq0.vhd | 1 | 7,470 | -- megafunction wizard: %LPM_RAM_DQ%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: lpm_ram_dq0.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY lpm_ram_dq0 IS
PORT
(
address : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rden : IN STD_LOGIC := '1';
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END lpm_ram_dq0;
ARCHITECTURE SYN OF lpm_ram_dq0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
COMPONENT altsyncram
GENERIC (
clock_enable_input_a : STRING;
clock_enable_output_a : STRING;
init_file : STRING;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
numwords_a : NATURAL;
operation_mode : STRING;
outdata_aclr_a : STRING;
outdata_reg_a : STRING;
power_up_uninitialized : STRING;
read_during_write_mode_port_a : STRING;
widthad_a : NATURAL;
width_a : NATURAL;
width_byteena_a : NATURAL
);
PORT (
wren_a : IN STD_LOGIC ;
clock0 : IN STD_LOGIC ;
address_a : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
rden_a : IN STD_LOGIC ;
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "lab10_2.mif",
intended_device_family => "Cyclone III",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 128,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 7,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
wren_a => wren,
clock0 => clock,
address_a => address,
rden_a => rden,
data_a => data,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "lab10_2.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "128"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "7"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "1"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "lab10_2.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "128"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "7"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 7 0 INPUT NODEFVAL address[6..0]
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC rden
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
-- Retrieval info: CONNECT: @address_a 0 0 7 0 address 0 0 7 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ram_dq0_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
| gpl-2.0 | 5883631c887cc2b78aabc42815d5dd99 | 0.673226 | 3.409402 | false | false | false | false |
UnofficialRepos/OSVVM | AlertLogPkg.vhd | 1 | 300,689 | --
-- File Name: AlertLogPkg.vhd
-- Design Unit Name: AlertLogPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
-- Rob Gaddi Highland Technology. Inspired SetAlertLogPrefix / Suffix
--
--
-- Description:
-- Alert handling and log filtering (verbosity control)
-- Alert handling provides a method to count failures, errors, and warnings
-- To accumlate counts, a data structure is created in a shared variable
-- It is of type AlertLogStructPType which is defined in AlertLogBasePkg
-- Log filtering provides verbosity control for logs (display or do not display)
-- AlertLogPkg provides a simplified interface to the shared variable
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 SetAlertPrintCount and GetAlertPrintCount
-- Added NewID with ReportMode, PrintParent
-- Updated Alert s.t. on StopCount prints WriteAlertSummaryYaml and WriteAlertYaml
-- 01/2022 2022.01 For AlertIfEqual and AffirmIfEqual, all arrays of std_ulogic use to_hxstring
-- Updated return value for PathTail
-- 10/2021 2021.10 Moved EndOfTestSummary to ReportPkg
-- 09/2021 2021.09 Added EndOfTestSummary and CreateYamlReport - Experimental Release
-- 07/2021 2021.07 When printing time value from GetOsvvmDefaultTimeUnits is used.
-- 06/2021 2021.06 FindAlertLogID updated to allow an ID name to match the name set by SetAlertLogName (ALERTLOG_BASE_ID)
-- 12/2020 2020.12 Added MetaMatch to AffirmIfEqual and AffirmIfNotEqual for std_logic family to use MetaMatch
-- Added AffirmIfEqual for boolean
-- 10/2020 2020.10 Added MetaMatch.
-- Updated AlertIfEqual and AlertIfNotEqual for std_logic family to use MetaMatch
-- 08/2020 2020.08 Alpha Test Release of Specification Tracking - Changes are provisional and subject to change
-- Added Passed Goals - reported with ReportAlerts and ReportRequirements.
-- Added WriteAlerts - CSV format of the information in ReportAlerts
-- Tests fail when requirements are not met and FailOnRequirementErrors is true (default TRUE).
-- Set using: SetAlertLogOptions(FailOnRequirementErrors => TRUE)
-- Turn on requirements printing in summary and details with PrintRequirements (default FALSE,
-- Turn on requirements printing in summary with PrintIfHaveRequirements (Default TRUE)
-- Added Requirements Bin, ReadSpecification, GetReqID, SetPassedGoal
-- Added AffirmIf("Req ID 1", ...) -- will work even if ID not set by GetReqID or ReadSpecification
-- Added ReportRequirements, WriteRequirements, and ReadRequirements (to merge results of multiple tests)
-- Added WriteTestSummary, ReadTestSummaries, ReportTestSummaries, and WriteTestSummaries.
-- 05/2020 2020.05 Added internal variables AlertCount (W, E, F) and ErrorCount (integer)
-- that hold the error state. These can be displayed in wave windows
-- in simulation to track number of errors.
-- Calls to std.env.stop now return ErrorCount
-- Updated calls to check for valid AlertLogIDs
-- Added affirmation count for each level.
-- Turn off reporting with SetAlertLogOptions (PrintAffirmations => TRUE) ;
-- Disabled Alerts now handled in separate bins and reported separately.
-- Turn off reporting with SetAlertLogOptions (PrintDisabledAlerts => TRUE) ;
-- 01/2020 2020.01 Updated Licenses to Apache
-- 10/2018 2018.10 Added pragmas to allow alerts, logs, and affirmations in RTL code
-- Added local variable to mirror top level ErrorCount and display in simulator
-- Added prefix and suffix
-- Debug printing with number of errors as prefix
-- 04/2018 2018.04 Fix to PathTail. Prep to change AlertLogIDType to a type.
-- 05/2017 2017.05 AffirmIfEqual, AffirmIfDiff,
-- GetAffirmCount (deprecates GetAffirmCheckCount), IncAffirmCount (deprecates IncAffirmCheckCount),
-- IsAlertEnabled (alias), IsLogEnabled (alias)
-- 02/2016 2016.02 Fixed IsLogEnableType (for PASSED), AffirmIf (to pass AlertLevel)
-- Created LocalInitialize
-- 07/2015 2016.01 Fixed AlertLogID issue with > 32 IDs
-- 05/2015 2015.06 Added IncAlertCount, AffirmIf
-- 03/2015 2015.03 Added: AlertIfEqual, AlertIfNotEqual, AlertIfDiff, PathTail,
-- ReportNonZeroAlerts, ReadLogEnables
-- 01/2015 2015.01 Initial revision
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
library IEEE ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package AlertLogPkg is
-- type AlertLogIDType is range integer'low to integer'high ; -- next revision
subtype AlertLogIDType is integer ;
type AlertLogIDVectorType is array (integer range <>) of AlertLogIDType ;
type AlertType is (FAILURE, ERROR, WARNING) ; -- NEVER
subtype AlertIndexType is AlertType range FAILURE to WARNING ;
type AlertCountType is array (AlertIndexType) of integer ;
type AlertEnableType is array(AlertIndexType) of boolean ;
type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER -- See function IsLogEnableType
subtype LogIndexType is LogType range DEBUG to PASSED ;
type LogEnableType is array (LogIndexType) of boolean ;
type AlertLogReportModeType is (DISABLED, ENABLED, NONZERO) ;
type AlertLogPrintParentType is (PRINT_NAME, PRINT_NAME_AND_PARENT) ;
constant REPORTS_DIRECTORY : string := "" ;
-- constant REPORTS_DIRECTORY : string := "./reports/" ;
constant ALERTLOG_BASE_ID : AlertLogIDType := 0 ; -- Careful as some code may assume this is 0.
constant ALERTLOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_BASE_ID + 1 ;
constant OSVVM_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 2 ; -- reporting for packages
constant REQUIREMENT_ALERTLOG_ID : AlertLogIDType := ALERTLOG_BASE_ID + 3 ;
-- May have its own ID or OSVVM_ALERTLOG_ID as default - most scoreboards allocate their own ID
constant OSVVM_SCOREBOARD_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
constant OSVVM_COV_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-- Same as ALERTLOG_DEFAULT_ID
constant ALERT_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant LOG_DEFAULT_ID : AlertLogIDType := ALERTLOG_DEFAULT_ID ;
constant ALERTLOG_ID_NOT_FOUND : AlertLogIDType := -1 ; -- alternately integer'right
constant ALERTLOG_ID_NOT_ASSIGNED : AlertLogIDType := -1 ;
constant MIN_NUM_AL_IDS : AlertLogIDType := 32 ; -- Number IDs initially allocated
------------------------------------------------------------
-- Alert always goes to the transcript file
procedure Alert(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) ;
procedure Alert( Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
procedure IncAlertCount( -- A silent form of alert
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) ;
procedure IncAlertCount( Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Similar to assert, except condition is positive
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- Direct replacement for assert
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean ;
------------------------------------------------------------
-- overloading for common functionality
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) ;
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
-- Simple Diff for file comparisons
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) ;
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean ;
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) ;
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) ;
procedure AffirmError( Message : string ) ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE );
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfNotDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfNotDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
-- Deprecated as they are misnamed - should be AffirmIfNotDiff
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
-- Support for Specification / Requirements Tracking
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) ;
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) ;
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0) ;
ReportAll : Boolean := FALSE
) ;
procedure ReportNonZeroAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0)
) ;
procedure WriteAlertYaml (
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteAlertSummaryYaml (FileName : string := "" ; ExternalErrors : AlertCountType := (0,0,0)) ;
procedure CreateYamlReport (ExternalErrors : AlertCountType := (0,0,0)) ; -- Deprecated. Use WriteAlertSummaryYaml.
-- impure function EndOfTestReports (
-- ReportAll : boolean := FALSE ;
-- ExternalErrors : AlertCountType := (0,0,0)
-- ) return integer ;
--
-- procedure EndOfTestReports (
-- ReportAll : boolean := FALSE ;
-- ExternalErrors : AlertCountType := (0,0,0) ;
-- Stop : boolean := FALSE
-- ) ;
--
-- alias EndOfTestSummary is EndOfTestReports[boolean, AlertCountType return integer] ;
-- alias EndOfTestSummary is EndOfTestReports[boolean, AlertCountType, boolean] ;
procedure WriteTestSummary (
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE ;
Prefix : string := "" ;
Suffix : string := "" ;
ExternalErrors : AlertCountType := (0,0,0) ;
WriteFieldName : boolean := FALSE
) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind := WRITE_MODE ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean := FALSE
) ;
procedure ReadTestSummaries (FileName : string) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
procedure ClearAlertCounts ;
function "ABS" (L : AlertCountType) return AlertCountType ;
function "+" (L, R : AlertCountType) return AlertCountType ;
function "-" (L, R : AlertCountType) return AlertCountType ;
function "-" (R : AlertCountType) return AlertCountType ;
impure function SumAlertCount(AlertCount: AlertCountType) return integer ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount return integer ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer ;
------------------------------------------------------------
-- log filtering for verbosity control, optionally has a separate file parameter
procedure Log(
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) ;
------------------------------------------------------------
-- Alert Enables
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
impure function GetAlertEnable(Level : AlertType) return boolean ;
alias IsAlertEnabled is GetAlertEnable[AlertLogIDType, AlertType return boolean] ;
alias IsAlertEnabled is GetAlertEnable[AlertType return boolean] ;
-- Log Enables
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
impure function GetLogEnable(Level : LogType) return boolean ;
alias IsLogEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as GetLogEnable
alias IsLogEnabled is GetLogEnable [LogType return boolean] ; -- same as GetLogEnable
procedure ReportLogEnables ;
procedure SetAlertLogName(Name : string ) ;
-- synthesis translate_off
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string ;
-- synthesis translate_on
procedure DeallocateAlertLogStruct ;
procedure InitializeAlertLogStruct ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function NewID(
Name : string ;
ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ;
ReportMode : AlertLogReportModeType := ENABLED ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT ;
CreateHierarchy : boolean := TRUE
) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
-- synthesis translate_off
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
-- synthesis translate_on
------------------------------------------------------------
-- Accessor Methods
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertStopCount(Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertStopCount(Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
procedure SetAlertPrintCount( Level : AlertType ; Count : integer) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
impure function GetAlertPrintCount( Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) ;
procedure SetAlertPrintCount( Count : AlertCountType) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType ;
impure function GetAlertPrintCount return AlertCountType ;
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) ;
procedure SetAlertLogPrintParent( PrintParent : AlertLogPrintParentType) ;
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType ;
impure function GetAlertLogPrintParent return AlertLogPrintParentType ;
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) ;
procedure SetAlertLogReportMode( ReportMode : AlertLogReportModeType) ;
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType ;
impure function GetAlertLogReportMode return AlertLogReportModeType ;
------------------------------------------------------------
procedure SetAlertLogOptions (
FailOnWarning : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT ;
IdSeparator : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
procedure ReportAlertLogOptions ;
-- synthesis translate_off
impure function GetAlertLogFailOnWarning return OsvvmOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType ;
impure function GetAlertLogReportHierarchy return OsvvmOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertName return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType ;
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteLogName return OsvvmOptionsType ;
impure function GetAlertLogWriteLogTime return OsvvmOptionsType ;
impure function GetAlertLogPrintPassed return OsvvmOptionsType ;
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType ;
impure function GetAlertLogPrintRequirements return OsvvmOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
-- File Reading Utilities
function IsLogEnableType (Name : String) return boolean ;
procedure ReadLogEnables (file AlertLogInitFile : text) ;
procedure ReadLogEnables (FileName : string) ;
-- String Helper Functions -- This should be in a more general string package
function PathTail (A : string) return string ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
function MetaMatch (l, r : std_ulogic) return boolean ;
function MetaMatch (L, R : std_ulogic_vector) return boolean ;
function MetaMatch (L, R : unresolved_unsigned) return boolean ;
function MetaMatch (L, R : unresolved_signed) return boolean ;
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolvePrintParent (
------------------------------------------------------------
UniqueParent : boolean ;
PrintParent : AlertLogPrintParentType
) return AlertLogPrintParentType ;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
-- See NewID - consistency and parameter update. DoNotReport replaced by ReportMode
impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) return AlertLogIDType ;
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) ;
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean ;
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) ;
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) ;
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) ;
alias IncAffirmCheckCount is IncAffirmCount [AlertLogIDType] ;
alias GetAffirmCheckCount is GetAffirmCount [return natural] ;
alias IsLoggingEnabled is GetLogEnable [AlertLogIDType, LogType return boolean] ; -- same as IsLogEnabled
alias IsLoggingEnabled is GetLogEnable [LogType return boolean] ; -- same as IsLogEnabled
end AlertLogPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
use work.NamePkg.all ;
package body AlertLogPkg is
-- synthesis translate_off
-- instead of justify(to_upper(to_string())), just look up the upper case, left justified values
type AlertNameType is array(AlertType) of string(1 to 7) ;
constant ALERT_NAME : AlertNameType := (WARNING => "WARNING", ERROR => "ERROR ", FAILURE => "FAILURE") ; -- , NEVER => "NEVER "
type LogNameType is array(LogType) of string(1 to 7) ;
constant LOG_NAME : LogNameType := (DEBUG => "DEBUG ", FINAL => "FINAL ", INFO => "INFO ", ALWAYS => "ALWAYS ", PASSED => "PASSED ") ; -- , NEVER => "NEVER "
------------------------------------------------------------
-- Package Local
function LeftJustify(A : String; Amount : integer) return string is
------------------------------------------------------------
constant Spaces : string(1 to maximum(1, Amount)) := (others => ' ') ;
begin
if A'length >= Amount then
return A ;
else
return A & Spaces(1 to Amount - A'length) ;
end if ;
end function LeftJustify ;
type AlertLogStructPType is protected
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) ;
------------------------------------------------------------
procedure IncAlertCount ( AlertLogID : AlertLogIDType ; level : AlertType := ERROR ) ;
procedure SetJustify (
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) ;
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) ;
procedure ReportRequirements ;
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (0,0,0) ;
ReportAll : boolean := FALSE ;
ReportWhenZero : boolean := TRUE
) ;
procedure WriteAlertYaml (
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) ;
procedure WriteTestSummary (
FileName : string ;
OpenKind : File_Open_Kind ;
Prefix : string ;
Suffix : string ;
ExternalErrors : AlertCountType ;
WriteFieldName : boolean
) ;
procedure WriteTestSummaries ( FileName : string ; OpenKind : File_Open_Kind ) ;
procedure ReportTestSummaries ;
procedure WriteAlerts (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure WriteRequirements (
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) ;
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) ;
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) ;
procedure ClearAlerts ;
procedure ClearAlertStopCounts ;
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType ;
impure function GetDisabledAlertCount return AlertCountType ;
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) ;
------------------------------------------------------------
-- FILE IO Controls
-- procedure SetTranscriptEnable (A : boolean := TRUE) ;
-- impure function IsTranscriptEnabled return boolean ;
-- procedure MirrorTranscript (A : boolean := TRUE) ;
-- impure function IsTranscriptMirrored return boolean ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) ;
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) ;
impure function FindAlertLogID(Name : string ) return AlertLogIDType ;
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType ;
impure function NewID(
Name : string ;
ParentID : AlertLogIDType ;
ReportMode : AlertLogReportModeType ;
PrintParent : AlertLogPrintParentType ;
CreateHierarchy : boolean
) return AlertLogIDType ;
-- impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType; CreateHierarchy : Boolean; DoNotReport : Boolean) return AlertLogIDType ;
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType ;
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) ;
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType ;
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) ;
procedure DeallocateAlertLogStruct ;
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string ;
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) ;
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) ;
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) ;
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string ;
impure function GetGlobalAlertEnable return boolean ;
procedure IncAffirmCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmCount return natural ;
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) ;
impure function GetAffirmPassedCount return natural ;
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer ;
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) ;
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType ;
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) ;
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType ;
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) ;
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType ;
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) ;
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean ;
procedure SetLogEnable(Level : LogType ; Enable : boolean) ;
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) ;
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean ;
procedure ReportLogEnables ;
------------------------------------------------------------
-- Reporting Accessor
procedure SetAlertLogOptions (
FailOnWarning : OsvvmOptionsType ;
FailOnDisabledErrors : OsvvmOptionsType ;
FailOnRequirementErrors : OsvvmOptionsType ;
ReportHierarchy : OsvvmOptionsType ;
WriteAlertErrorCount : OsvvmOptionsType ;
WriteAlertLevel : OsvvmOptionsType ;
WriteAlertName : OsvvmOptionsType ;
WriteAlertTime : OsvvmOptionsType ;
WriteLogErrorCount : OsvvmOptionsType ;
WriteLogLevel : OsvvmOptionsType ;
WriteLogName : OsvvmOptionsType ;
WriteLogTime : OsvvmOptionsType ;
PrintPassed : OsvvmOptionsType ;
PrintAffirmations : OsvvmOptionsType ;
PrintDisabledAlerts : OsvvmOptionsType ;
PrintRequirements : OsvvmOptionsType ;
PrintIfHaveRequirements : OsvvmOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string ;
IdSeparator : string
) ;
procedure ReportAlertLogOptions ;
impure function GetAlertLogFailOnWarning return OsvvmOptionsType ;
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType ;
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType ;
impure function GetAlertLogReportHierarchy return OsvvmOptionsType ;
impure function GetAlertLogFoundReportHier return boolean ;
impure function GetAlertLogFoundAlertHier return boolean ;
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertName return OsvvmOptionsType ;
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType ;
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType ;
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType ;
impure function GetAlertLogWriteLogName return OsvvmOptionsType ;
impure function GetAlertLogWriteLogTime return OsvvmOptionsType ;
impure function GetAlertLogPrintPassed return OsvvmOptionsType ;
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType ;
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType ;
impure function GetAlertLogPrintRequirements return OsvvmOptionsType ;
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType ;
impure function GetAlertLogDefaultPassedGoal return integer ;
impure function GetAlertLogAlertPrefix return string ;
impure function GetAlertLogLogPrefix return string ;
impure function GetAlertLogReportPrefix return string ;
impure function GetAlertLogDoneName return string ;
impure function GetAlertLogPassName return string ;
impure function GetAlertLogFailName return string ;
end protected AlertLogStructPType ;
--- ///////////////////////////////////////////////////////////////////////////
type AlertLogStructPType is protected body
variable GlobalAlertEnabledVar : boolean := TRUE ; -- Allows turn off and on
variable AffirmCheckCountVar : natural := 0 ;
variable PassedCountVar : natural := 0 ;
variable ErrorCount : integer := 0 ;
variable AlertCount : AlertCountType := (0, 0, 0) ;
------------------------------------------------------------
type AlertLogRecType is record
------------------------------------------------------------
Name : Line ;
NameLower : Line ;
Prefix : Line ;
Suffix : Line ;
ParentID : AlertLogIDType ;
ParentIDSet : Boolean ;
SiblingID : AlertLogIDType ;
ChildID : AlertLogIDType ;
ChildIDLast : AlertLogIDType ;
AlertCount : AlertCountType ;
DisabledAlertCount : AlertCountType ;
PassedCount : Integer ;
AffirmCount : Integer ;
PassedGoal : Integer ;
PassedGoalSet : Boolean ;
AlertStopCount : AlertCountType ;
AlertPrintCount : AlertCountType ;
AlertEnabled : AlertEnableType ;
LogEnabled : LogEnableType ;
ReportMode : AlertLogReportModeType ;
PrintParent : AlertLogPrintParentType ;
-- Used only by ReadTestSummaries
TotalErrors : integer ;
AffirmPassedCount : integer ;
-- IsRequirment : boolean ;
end record AlertLogRecType ;
------------------------------------------------------------
-- Basis for AlertLog Data Structure
variable NumAlertLogIDsVar : AlertLogIDType := 0 ; -- defined by initialize
variable NumAllocatedAlertLogIDsVar : AlertLogIDType := 0 ;
type AlertLogRecPtrType is access AlertLogRecType ;
type AlertLogArrayType is array (AlertLogIDType range <>) of AlertLogRecPtrType ;
type AlertLogArrayPtrType is access AlertLogArrayType ;
variable AlertLogPtr : AlertLogArrayPtrType ;
------------------------------------------------------------
-- Report formatting settings, with defaults
variable PrintPassedVar : boolean := TRUE ;
variable PrintAffirmationsVar : boolean := FALSE ;
variable PrintDisabledAlertsVar : boolean := FALSE ;
variable PrintRequirementsVar : boolean := FALSE ;
variable HasRequirementsVar : boolean := FALSE ;
variable PrintIfHaveRequirementsVar : boolean := TRUE ;
variable DefaultPassedGoalVar : integer := 1 ;
variable FailOnWarningVar : boolean := TRUE ;
variable FailOnDisabledErrorsVar : boolean := TRUE ;
variable FailOnRequirementErrorsVar : boolean := TRUE ;
variable ReportHierarchyVar : boolean := TRUE ;
variable FoundReportHierVar : boolean := FALSE ;
variable FoundAlertHierVar : boolean := FALSE ;
variable WriteAlertErrorCountVar : boolean := FALSE ;
variable WriteAlertLevelVar : boolean := TRUE ;
variable WriteAlertNameVar : boolean := TRUE ;
variable WriteAlertTimeVar : boolean := TRUE ;
variable WriteLogErrorCountVar : boolean := FALSE ;
variable WriteLogLevelVar : boolean := TRUE ;
variable WriteLogNameVar : boolean := TRUE ;
variable WriteLogTimeVar : boolean := TRUE ;
variable AlertPrefixVar : NamePType ;
variable LogPrefixVar : NamePType ;
variable ReportPrefixVar : NamePType ;
variable DoneNameVar : NamePType ;
variable PassNameVar : NamePType ;
variable FailNameVar : NamePType ;
variable IdSeparatorVar : NamePType ;
variable AlertLogJustifyAmountVar : integer := 0 ;
variable ReportJustifyAmountVar : integer := 0 ;
------------------------------------------------------------
-- PT Local
impure function VerifyID(
AlertLogID : AlertLogIDType ;
LowestID : AlertLogIDType := ALERTLOG_BASE_ID ;
InvalidID : AlertLogIDType := ALERTLOG_DEFAULT_ID
) return AlertLogIDType is
------------------------------------------------------------
begin
if AlertLogID < LowestID or AlertLogID > NumAlertLogIDsVar then
Alert("Invalid AlertLogID") ;
return InvalidID ;
else
return AlertLogID ;
end if ;
end function VerifyID ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
begin
return AffirmCheckCountVar ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).PassedCount := AlertLogPtr(localAlertLogID).PassedCount + 1 ;
PassedCountVar := PassedCountVar + 1 ;
AlertLogPtr(localAlertLogID).AffirmCount := AlertLogPtr(localAlertLogID).AffirmCount + 1 ;
AffirmCheckCountVar := AffirmCheckCountVar + 1 ;
end if ;
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
begin
return PassedCountVar ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
-- PT Local
procedure IncrementAlertCount(
------------------------------------------------------------
constant AlertLogID : in AlertLogIDType ;
constant Level : in AlertType ;
variable StopDueToCount : inout boolean ;
variable IncrementByAmount : in integer := 1
) is
begin
if AlertLogPtr(AlertLogID).AlertEnabled(Level) then
AlertLogPtr(AlertLogID).AlertCount(Level) := AlertLogPtr(AlertLogID).AlertCount(Level) + IncrementByAmount ;
-- Exceeded Stop Count at this level?
if AlertLogPtr(AlertLogID).AlertCount(Level) >= AlertLogPtr(AlertLogID).AlertStopCount(Level) then
StopDueToCount := TRUE ;
end if ;
-- Propagate counts to parent(s) -- Ascend Hierarchy
if AlertLogID /= ALERTLOG_BASE_ID then
IncrementAlertCount(AlertLogPtr(AlertLogID).ParentID, Level, StopDueToCount, IncrementByAmount) ;
end if ;
else
-- Disabled, increment disabled count
AlertLogPtr(AlertLogID).DisabledAlertCount(Level) := AlertLogPtr(AlertLogID).DisabledAlertCount(Level) + IncrementByAmount ;
end if ;
end procedure IncrementAlertCount ;
------------------------------------------------------------
procedure alert (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
message : string ;
level : AlertType := ERROR
) is
variable buf : Line ;
-- constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
variable ParentID : AlertLogIDType ;
begin
-- Only write and count when GlobalAlertEnabledVar is enabled
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
-- Write when Alert is Enabled
if AlertLogPtr(localAlertLogID).AlertEnabled(Level) and (AlertLogPtr(localAlertLogID).AlertCount(Level) < AlertLogPtr(localAlertLogID).AlertPrintCount(Level)) then
-- Print %% Alert (nominally)
-- write(buf, AlertPrefix) ;
write(buf, AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ) ;
-- Debug Mode
if WriteAlertErrorCountVar then
write(buf, ' ' & justify(to_string(ErrorCount + 1), RIGHT, 2));
end if ;
-- Level Name, when enabled (default)
if WriteAlertLevelVar then
write(buf, " " & ALERT_NAME(Level)) ; -- uses constant lookup
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteAlertNameVar then
if AlertLogPtr(localAlertLogID).PrintParent = PRINT_NAME then
write(buf, " in " & LeftJustify(AlertLogPtr(localAlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
else
ParentID := AlertLogPtr(localAlertLogID).ParentID ;
write(buf, " in " & LeftJustify(AlertLogPtr(ParentID).Name.all & ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) &
AlertLogPtr(localAlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
end if ;
-- Prefix
if AlertLogPtr(localAlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(localAlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(localAlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteAlertTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end if ;
-- Always Count
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
-- write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
write(buf, LF & AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportWhenZero => TRUE) ;
if FileExists("OsvvmRun.yml") then
-- work.ReportPkg.EndOfTestReports ; -- creates circular package issues
WriteAlertSummaryYaml(
FileName => "OsvvmRun.yml"
) ;
WriteAlertYaml (
FileName => REPORTS_DIRECTORY & GetAlertLogName(ALERTLOG_BASE_ID) & "_alerts.yml"
) ;
end if ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
level : AlertType := ERROR
) is
variable buf : Line ;
-- constant AlertPrefix : string := AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
variable StopDueToCount : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
if GlobalAlertEnabledVar then
localAlertLogID := VerifyID(AlertLogID) ;
IncrementAlertCount(localAlertLogID, Level, StopDueToCount) ;
AlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount;
ErrorCount := SumAlertCount(AlertCount);
if StopDueToCount then
-- write(buf, LF & AlertPrefix & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
write(buf, LF & AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) & " Stop Count on " & ALERT_NAME(Level) & " reached") ;
if FoundAlertHierVar then
write(buf, " in " & AlertLogPtr(localAlertLogID).Name.all) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns) & " ") ;
writeline(buf) ;
ReportAlerts(ReportWhenZero => TRUE) ;
std.env.stop(ErrorCount) ;
end if ;
end if ;
end procedure IncAlertCount ;
------------------------------------------------------------
-- PT Local
impure function CalcJustify (AlertLogID : AlertLogIDType; CurrentLength : integer; IndentAmount : integer; IdSeparatorLength : integer) return integer_vector is
------------------------------------------------------------
variable ResultValues, LowerLevelValues : integer_vector(1 to 2) ; -- 1 = Max, 2 = Indented
variable CurID, ParentID : AlertLogIDType ;
variable ParentNameLen : integer ;
begin
ResultValues(1) := CurrentLength + 1 ; -- AlertLogJustifyAmountVar
ResultValues(2) := CurrentLength + IndentAmount ; -- ReportJustifyAmountVar
if AlertLogPtr(AlertLogID).PrintParent = PRINT_NAME_AND_PARENT then
ParentID := AlertLogPtr(AlertLogID).ParentID ;
ParentNameLen := AlertLogPtr(ParentID).Name'length ;
ResultValues(1) := IdSeparatorLength + ParentNameLen + ResultValues(1) ; -- AlertLogJustifyAmountVar
-- ResultValues(2) := IdSeparatorLength + ParentNameLen + ResultValues(2) ; -- ReportJustifyAmountVar
end if ;
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
LowerLevelValues := CalcJustify(CurID, AlertLogPtr(CurID).Name'length, IndentAmount + 2, IdSeparatorLength) ;
ResultValues(1) := maximum(ResultValues(1), LowerLevelValues(1)) ;
if AlertLogPtr(AlertLogID).ReportMode /= DISABLED then
ResultValues(2) := maximum(ResultValues(2), LowerLevelValues(2)) ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return ResultValues ;
end function CalcJustify ;
------------------------------------------------------------
procedure SetJustify (
------------------------------------------------------------
Enable : boolean := TRUE ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID
) is
constant Separator : string := ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) ;
begin
if Enable then
(AlertLogJustifyAmountVar, ReportJustifyAmountVar) := CalcJustify(AlertLogID, 0, 0, Separator'length) ;
else
AlertLogJustifyAmountVar := 0 ;
ReportJustifyAmountVar := 0 ;
end if;
end procedure SetJustify ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertCount ;
end function GetAlertCount ;
------------------------------------------------------------
-- Local
impure function RemoveNonFailingWarnings(A : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
begin
Count := A ;
if not FailOnWarningVar then
Count(WARNING) := 0 ;
end if ;
return Count ;
end function RemoveNonFailingWarnings ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
variable Count : AlertCountType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return RemoveNonFailingWarnings( AlertLogPtr(localAlertLogID).AlertCount ) ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType := (others => 0) ;
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Count := Count + AlertLogPtr(i).DisabledAlertCount ;
--? Should excluded warnings get counted as disabled errors?
--? if not FailOnWarningVar then
--? Count(WARNING) := Count(WARNING) + AlertLogPtr(i).AlertCount(WARNING) ;
--? end if ;
end loop ;
return Count ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function LocalGetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable Count : AlertCountType ;
variable CurID : AlertLogIDType ;
begin
Count := AlertLogPtr(AlertLogID).DisabledAlertCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
Count := Count + LocalGetDisabledAlertCount(CurID) ; -- Recursively descend into children
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
return Count ;
end function LocalGetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return LocalGetDisabledAlertCount(localAlertLogID) ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
-- Local GetRequirementsCount
-- Each bin contains a separate requirement
-- RequirementsGoal = # of bins with PassedGoal > 0
-- RequirementsPassed = # bins with PassedGoal > 0 and PassedCount > PassedGoal
procedure GetRequirementsCount(
AlertLogID : AlertLogIDType;
RequirementsPassed : out integer ;
RequirementsGoal : out integer
) is
------------------------------------------------------------
variable ChildRequirementsPassed, ChildRequirementsGoal : integer ;
variable CurID : AlertLogIDType ;
begin
RequirementsPassed := 0 ;
RequirementsGoal := 0 ;
if AlertLogPtr(AlertLogID).PassedGoal > 0 then
RequirementsGoal := 1 ;
if AlertLogPtr(AlertLogID).PassedCount >= AlertLogPtr(AlertLogID).PassedGoal then
RequirementsPassed := 1 ;
end if ;
end if ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetRequirementsCount(CurID, ChildRequirementsPassed, ChildRequirementsGoal) ;
RequirementsPassed := RequirementsPassed + ChildRequirementsPassed ;
RequirementsGoal := RequirementsGoal + ChildRequirementsGoal ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetRequirementsCount ;
------------------------------------------------------------
-- Only used at top level and superceded by variables PassedCountVar AffirmCheckCountVar
-- Local
procedure GetPassedAffirmCount(
AlertLogID : AlertLogIDType;
PassedCount : out integer ;
AffirmCount : out integer
) is
------------------------------------------------------------
variable ChildPassedCount, ChildAffirmCount : integer ;
variable CurID : AlertLogIDType ;
begin
PassedCount := AlertLogPtr(AlertLogID).PassedCount ;
AffirmCount := AlertLogPtr(AlertLogID).AffirmCount ;
-- Find Children of this ID
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
GetPassedAffirmCount(CurID, ChildPassedCount, ChildAffirmCount) ;
PassedCount := PassedCount + ChildPassedCount ;
AffirmCount := AffirmCount + ChildAffirmCount ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure GetPassedAffirmCount ;
------------------------------------------------------------
-- Local
procedure CalcTopTotalErrors (
------------------------------------------------------------
constant ExternalErrors : in AlertCountType ;
variable TotalErrors : out integer ;
variable TotalAlertCount : out AlertCountType ;
variable TotalRequirementsPassed : out integer ;
variable TotalRequirementsCount : out integer
) is
variable DisabledAlertCount : AlertCountType ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementErrors : integer ;
begin
TotalAlertCount := AlertLogPtr(ALERTLOG_BASE_ID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
TotalErrors := TotalAlertErrors ;
DisabledAlertCount := GetDisabledAlertCount(ALERTLOG_BASE_ID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
if FailOnDisabledErrorsVar then
TotalAlertCount := TotalAlertCount + DisabledAlertCount ;
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
-- Perspective, 1 requirement per bin
GetRequirementsCount(ALERTLOG_BASE_ID, TotalRequirementsPassed, TotalRequirementsCount) ;
TotalRequirementErrors := TotalRequirementsCount - TotalRequirementsPassed ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
-- Set AffirmCount for top level
AlertLogPtr(ALERTLOG_BASE_ID).PassedCount := PassedCountVar ;
AlertLogPtr(ALERTLOG_BASE_ID).AffirmCount := AffirmCheckCountVar ;
end procedure CalcTopTotalErrors ;
------------------------------------------------------------
-- Local
impure function CalcTotalErrors (AlertLogID : AlertLogIDType) return integer is
------------------------------------------------------------
variable TotalErrors : integer ;
variable TotalAlertCount, DisabledAlertCount : AlertCountType ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsCount : integer ;
begin
TotalAlertCount := AlertLogPtr(AlertLogID).AlertCount ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
TotalErrors := TotalAlertErrors ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
-- Perspective, 1 requirement per bin
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsCount) ;
TotalRequirementErrors := TotalRequirementsCount - TotalRequirementsPassed ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
return TotalErrors ;
end function CalcTotalErrors ;
------------------------------------------------------------
-- PT Local
procedure PrintTopAlerts (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Name : string ;
ExternalErrors : AlertCountType ;
variable HasDisabledAlerts : inout Boolean ;
variable TestFailed : inout Boolean
) is
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
-- constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
-- constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
-- constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal, TotalRequirementErrors : integer ;
variable AlertCountVar, DisabledAlertCount : AlertCountType ;
variable PassedCount, AffirmCheckCount : integer ;
begin
--!!
--!! Update to use CalcTopTotalErrors
--!!
AlertCountVar := AlertLogPtr(AlertLogID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(AlertCountVar)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
HasDisabledAlerts := TotalDisabledAlertErrors /= 0 ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
TestFailed := TotalErrors /= 0 ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCheckCount) ;
if not TestFailed then
-- write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ; -- PASSED
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmPassName(PassNameVar.GetOpt) & " " & -- PassName
Name
) ;
else
-- write(buf, ReportPrefix & DoneName & " " & FailName & " " & Name) ; -- FAILED
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmFailName(FailNameVar.GetOpt) & " " & -- FailName
Name
) ;
end if ;
--? Also print when warnings exist and are hidden by FailOnWarningVar=FALSE
if TestFailed then
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCountVar(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCountVar(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCountVar(WARNING) ) ) ;
end if ;
if HasDisabledAlerts or PrintDisabledAlertsVar then -- print if exist or enabled
write(buf, " Total Disabled Error(s) = " & to_string(TotalDisabledAlertErrors)) ;
end if ;
if (HasDisabledAlerts and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then -- print if enabled
write(buf, " Failures: " & to_string(DisabledAlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or (AffirmCheckCount /= 0) or PrintAffirmationsVar then -- Print if passed or printing affirmations
write(buf, " Passed: " & to_string(PassedCount)) ;
end if;
if (AffirmCheckCount /= 0) or PrintAffirmationsVar then
write(buf, " Affirmations Checked: " & to_string(AffirmCheckCount)) ;
end if ;
if PrintRequirementsVar or
(PrintIfHaveRequirementsVar and HasRequirementsVar) or
(FailOnRequirementErrorsVar and TotalRequirementErrors /= 0)
then
write(buf, " Requirements Passed: " & to_string(TotalRequirementsPassed) &
" of " & to_string(TotalRequirementsGoal) ) ;
end if ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
end procedure PrintTopAlerts ;
------------------------------------------------------------
-- PT Local
procedure PrintOneChild(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportWhenZero : boolean ;
HasErrors : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
alias CurID : AlertLogIDType is AlertLogID ;
begin
if ReportWhenZero or HasErrors then
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(CurID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
write(buf, " Failures: " & to_string(AlertLogPtr(CurID).AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).AlertCount(WARNING) ) ) ;
if (HasDisabledErrors and FailOnDisabledErrorsVar) or PrintDisabledAlertsVar then
write(buf, " Disabled Failures: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertLogPtr(CurID).DisabledAlertCount(WARNING) ) ) ;
end if ;
if PrintPassedVar or PrintRequirementsVar then
write(buf, " Passed: " & to_string(AlertLogPtr(CurID).PassedCount)) ;
end if;
if PrintRequirementsVar then
write(buf, " of " & to_string(AlertLogPtr(CurID).PassedGoal) ) ;
end if ;
if PrintAffirmationsVar then
write(buf, " Affirmations: " & to_string(AlertLogPtr(CurID).AffirmCount ) ) ;
end if ;
WriteLine(buf) ;
end if ;
end procedure PrintOneChild ;
------------------------------------------------------------
-- PT Local
procedure IterateAndPrintChildren(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer ;
ReportWhenZero : boolean ;
HasDisabledErrors : boolean
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
variable HasErrors : boolean ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Don't print requirements if there no requirements
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
HasErrors :=
(SumAlertCount(AlertLogPtr(CurID).AlertCount) > 0) or
(FailOnDisabledErrorsVar and (SumAlertCount(AlertLogPtr(CurID).DisabledAlertCount) > 0)) or
(FailOnRequirementErrorsVar and (AlertLogPtr(CurID).PassedCount < AlertLogPtr(CurID).PassedGoal)) ;
if AlertLogPtr(CurID).ReportMode = ENABLED or (AlertLogPtr(CurID).ReportMode = NONZERO and HasErrors) then
PrintOneChild(
AlertLogID => CurID,
Prefix => Prefix,
IndentAmount => IndentAmount,
ReportWhenZero => ReportWhenZero,
HasErrors => HasErrors,
HasDisabledErrors => HasDisabledErrors
) ;
IterateAndPrintChildren(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2,
ReportWhenZero => ReportWhenZero,
HasDisabledErrors => HasDisabledErrors
) ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure IterateAndPrintChildren ;
------------------------------------------------------------
procedure ReportAlerts (
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (0,0,0) ;
ReportAll : boolean := FALSE ;
ReportWhenZero : boolean := TRUE
) is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
if IsOsvvmStringSet(Name) then
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => Name,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
else
PrintTopAlerts (
AlertLogID => localAlertLogID,
Name => AlertLogPtr(localAlertLogID).Name.all,
ExternalErrors => ExternalErrors,
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
end if ;
--Print Hierarchy when enabled and test failed
if ReportAll or (FoundReportHierVar and ReportHierarchyVar and TestFailed) then
-- (NumErrors /= 0 or (NumDisabledErrors /=0 and FailOnDisabledErrorsVar)) then
IterateAndPrintChildren(
AlertLogID => localAlertLogID,
-- Prefix => ReportPrefix & " ",
Prefix => ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & " ",
IndentAmount => 2,
ReportWhenZero => ReportAll or ReportWhenZero,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
end if ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
variable TestFailed, HasDisabledErrors : boolean ;
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
variable TurnedOnJustify : boolean := FALSE ;
variable SavedPrintRequirementsVar : boolean ;
begin
SavedPrintRequirementsVar := PrintRequirementsVar ;
PrintRequirementsVar := TRUE ;
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintTopAlerts (
AlertLogID => ALERTLOG_BASE_ID,
Name => AlertLogPtr(ALERTLOG_BASE_ID).Name.all,
ExternalErrors => (0,0,0),
HasDisabledAlerts => HasDisabledErrors,
TestFailed => TestFailed
) ;
IterateAndPrintChildren(
AlertLogID => REQUIREMENT_ALERTLOG_ID,
-- Prefix => ReportPrefix & " ",
Prefix => ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & " ",
IndentAmount => 2,
ReportWhenZero => TRUE,
HasDisabledErrors => HasDisabledErrors -- NumDisabledErrors /= 0
) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
PrintRequirementsVar := SavedPrintRequirementsVar ;
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts ( Name : string ; AlertCount : AlertCountType ) is
------------------------------------------------------------
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
-- constant DoneName : string := ResolveOsvvmDoneName(DoneNameVar.GetOpt ) ;
-- constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
-- constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
variable buf : line ;
variable NumErrors : integer ;
begin
NumErrors := SumAlertCount(AlertCount) ;
if NumErrors = 0 then
-- Passed
-- write(buf, ReportPrefix & DoneName & " " & PassName & " " & Name) ;
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmPassName(PassNameVar.GetOpt) & " " & -- PassName
Name
) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
WriteLine(buf) ;
else
-- Failed
-- write(buf, ReportPrefix & DoneName & " " & FailName & " "& Name) ;
write(buf,
ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) & -- ReportPrefix
ResolveOsvvmDoneName(DoneNameVar.GetOpt) & " " & -- DoneName
ResolveOsvvmFailName(FailNameVar.GetOpt) & " " & -- FailName
Name
) ;
write(buf, " Total Error(s) = " & to_string(NumErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE)) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " at " & to_string(NOW, 1 ns)) ;
writeLine(buf) ;
end if ;
end procedure ReportAlerts ;
------------------------------------------------------------
-- pt local
procedure WriteOneAlertYaml (
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
TotalErrors : integer ;
RequirementsPassed : integer ;
RequirementsGoal : integer ;
FirstPrefix : string := "" ;
Prefix : string := ""
) is
variable buf : line ;
constant DELIMITER : string := ", " ;
begin
Write(buf,
FirstPrefix & "Name: " & '"' & AlertLogPtr(AlertLogID).Name.all & '"' & LF &
Prefix & "Status: " & IfElse(TotalErrors=0, "PASSED", "FAILED") & LF &
Prefix & "Results: {" &
"TotalErrors: " & to_string( TotalErrors ) & DELIMITER &
"AlertCount: {" &
"Failure: " & to_string( AlertLogPtr(AlertLogID).AlertCount(FAILURE) ) & DELIMITER &
"Error: " & to_string( AlertLogPtr(AlertLogID).AlertCount(ERROR) ) & DELIMITER &
"Warning: " & to_string( AlertLogPtr(AlertLogID).AlertCount(WARNING) ) &
"}" & DELIMITER &
"PassedCount: " & to_string( AlertLogPtr(AlertLogID).PassedCount ) & DELIMITER &
"AffirmCount: " & to_string( AlertLogPtr(AlertLogID).AffirmCount ) & DELIMITER &
"RequirementsPassed: " & to_string( RequirementsPassed ) & DELIMITER &
"RequirementsGoal: " & to_string( RequirementsGoal ) & DELIMITER &
"DisabledAlertCount: {" &
"Failure: " & to_string( AlertLogPtr(AlertLogID).DisabledAlertCount(FAILURE) ) & DELIMITER &
"Error: " & to_string( AlertLogPtr(AlertLogID).DisabledAlertCount(ERROR) ) & DELIMITER &
"Warning: " & to_string( AlertLogPtr(AlertLogID).DisabledAlertCount(WARNING) ) &
"}" &
"}"
) ;
WriteLine(TestFile, buf) ;
end procedure WriteOneAlertYaml ;
------------------------------------------------------------
-- PT Local
procedure IterateAndWriteChildrenYaml(
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
Prefix : string
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
variable RequirementsPassed, RequirementsGoal : integer ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
if CurID >= ALERTLOG_BASE_ID then
-- Write "Children:" at current level
Write(buf, Prefix & "Children: " ) ;
WriteLine(TestFile, buf) ;
while CurID > ALERTLOG_BASE_ID loop
-- Don't print requirements if there no requirements
if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
CurID := AlertLogPtr(CurID).SiblingID ;
next ;
end if ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
if AlertLogPtr(CurID).PassedGoalSet and (RequirementsGoal > 0) then
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
else
RequirementsPassed := 0 ;
RequirementsGoal := 0 ;
end if ;
if AlertLogPtr(AlertLogID).ReportMode /= DISABLED then
WriteOneAlertYaml(
TestFile => TestFile,
AlertLogID => CurID,
TotalErrors => CalcTotalErrors(CurID),
RequirementsPassed => RequirementsPassed,
RequirementsGoal => RequirementsGoal,
FirstPrefix => Prefix & " - ",
Prefix => Prefix & " "
) ;
IterateAndWriteChildrenYaml(
TestFile => TestFile,
AlertLogID => CurID,
Prefix => Prefix & " "
) ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
else
-- No Children, Print Empty List
Write(buf, Prefix & "Children: {}" ) ;
WriteLine(TestFile, buf) ;
end if ;
end procedure IterateAndWriteChildrenYaml ;
------------------------------------------------------------
-- pt local
procedure WriteSettingsYaml (
------------------------------------------------------------
file TestFile : text ;
ExternalErrors : AlertCountType ;
Prefix : string := ""
) is
variable buf : line ;
constant DELIMITER : string := ", " ;
begin
Write(buf,
Prefix & "Settings: {" &
"ExternalErrors: {" &
"Failure: " & '"' & to_string( ExternalErrors(FAILURE) ) & '"' & DELIMITER &
"Error: " & '"' & to_string( ExternalErrors(ERROR) ) & '"' & DELIMITER &
"Warning: " & '"' & to_string( ExternalErrors(WARNING) ) & '"' &
"}" & DELIMITER &
"FailOnDisabledErrors: " & '"' & to_string( FailOnDisabledErrorsVar ) & '"' & DELIMITER &
"FailOnRequirementErrors: " & '"' & to_string( FailOnRequirementErrorsVar ) & '"' & DELIMITER &
"FailOnWarning: " & '"' & to_string( FailOnWarningVar ) & '"' &
"}"
) ;
WriteLine(TestFile, buf) ;
end procedure WriteSettingsYaml ;
------------------------------------------------------------
-- pt local
procedure WriteAlertYaml (
------------------------------------------------------------
file TestFile : text ;
ExternalErrors : AlertCountType ;
Prefix : string ;
PrintSettings : boolean ;
PrintChildren : boolean
) is
-- Format: Action Count min1 max1 min2 max2
variable TotalErrors : integer ;
variable TotalAlertCount : AlertCountType ;
variable TotalRequirementsPassed, TotalRequirementsCount : integer ;
begin
CalcTopTotalErrors (
ExternalErrors => ExternalErrors ,
TotalErrors => TotalErrors ,
TotalAlertCount => TotalAlertCount ,
TotalRequirementsPassed => TotalRequirementsPassed,
TotalRequirementsCount => TotalRequirementsCount
) ;
WriteOneAlertYaml (
TestFile => TestFile,
AlertLogID => ALERTLOG_BASE_ID,
TotalErrors => TotalErrors,
RequirementsPassed => TotalRequirementsPassed,
RequirementsGoal => TotalRequirementsCount,
FirstPrefix => Prefix,
Prefix => Prefix
) ;
if PrintSettings then
WriteSettingsYaml(
TestFile => TestFile,
ExternalErrors => ExternalErrors,
Prefix => Prefix
) ;
end if ;
if PrintChildren then
IterateAndWriteChildrenYaml(
TestFile => TestFile,
AlertLogID => ALERTLOG_BASE_ID,
Prefix => Prefix
) ;
end if ;
end procedure WriteAlertYaml ;
------------------------------------------------------------
procedure WriteAlertYaml (
------------------------------------------------------------
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
file FileID : text ;
variable status : file_open_status ;
begin
file_open(status, FileID, FileName, OpenKind) ;
if status = OPEN_OK then
WriteAlertYaml(FileID, ExternalErrors, Prefix, PrintSettings, PrintChildren) ;
file_close(FileID) ;
else
Alert("WriteAlertYaml, File: " & FileName & " did not open for " & to_string(OpenKind)) ;
end if ;
end procedure WriteAlertYaml ;
------------------------------------------------------------
-- PT Local
impure function IsRequirement(AlertLogID : AlertLogIDType) return boolean is
------------------------------------------------------------
begin
if AlertLogID = REQUIREMENT_ALERTLOG_ID then
return TRUE ;
elsif AlertLogID <= ALERTLOG_BASE_ID then
return FALSE ;
else
return IsRequirement(AlertLogPtr(AlertLogID).ParentID) ;
end if ;
end function IsRequirement ;
------------------------------------------------------------
-- pt local
procedure WriteOneTestSummary (
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string ;
Prefix : string := "" ;
Suffix : string := "" ;
WriteFieldName : boolean := FALSE
) is
variable buf : line ;
begin
-- Should disabled errors be included here?
-- In the previous step, we counted DisabledErrors as a regular error if FailOnDisabledErrorsVar (default TRUE)
Write(buf,
Prefix &
IfElse(WriteFieldName, "Status: " & IfElse(TotalErrors=0, "PASSED", "FAILED") & LF, "") &
IfElse(WriteFieldName, Prefix & "Results: {Name: ", "") &
AlertLogPtr(AlertLogID).Name.all & Delimiter &
IfElse(WriteFieldName, "RequirementsGoal: ", "") &
to_string( RequirementsGoal ) & Delimiter &
IfElse(WriteFieldName, "RequirementsPassed: ", "") &
to_string( RequirementsPassed ) & Delimiter &
IfElse(WriteFieldName, "TotalErrors: ", "") &
to_string( TotalErrors ) & Delimiter &
IfElse(WriteFieldName, "Failure: ", "") &
to_string( AlertCount(FAILURE) ) & Delimiter &
IfElse(WriteFieldName, "Error: ", "") &
to_string( AlertCount(ERROR) ) & Delimiter &
IfElse(WriteFieldName, "Warning: ", "") &
to_string( AlertCount(WARNING) ) & Delimiter &
IfElse(WriteFieldName, "AffirmCount: ", "") &
to_string( AffirmCount ) & Delimiter &
IfElse(WriteFieldName, "PassedCount: ", "") &
to_string( PassedCount ) &
IfElse(WriteFieldName, "}", "") &
Suffix
) ;
-- ## Write(buf,
-- ## Prefix &
-- ## IfElse(WriteFieldName, "Status: " & IfElse(TotalErrors=0, "PASSED", "FAILED") & Delimiter, "") &
-- ## IfElse(WriteFieldName, "Name: ", "") &
-- ## AlertLogPtr(AlertLogID).Name.all & Delimiter &
-- ## IfElse(WriteFieldName, "RequirementsGoal: ", "") &
-- ## to_string( RequirementsGoal ) & Delimiter &
-- ## IfElse(WriteFieldName, "RequirementsPassed: ", "") &
-- ## to_string( RequirementsPassed ) & Delimiter &
-- ## IfElse(WriteFieldName, "TotalErrors: ", "") &
-- ## to_string( TotalErrors ) & Delimiter &
-- ## IfElse(WriteFieldName, "Failure: ", "") &
-- ## to_string( AlertCount(FAILURE) ) & Delimiter &
-- ## IfElse(WriteFieldName, "Error: ", "") &
-- ## to_string( AlertCount(ERROR) ) & Delimiter &
-- ## IfElse(WriteFieldName, "Warning: ", "") &
-- ## to_string( AlertCount(WARNING) ) & Delimiter &
-- ## IfElse(WriteFieldName, "AffirmCount: ", "") &
-- ## to_string( AffirmCount ) & Delimiter &
-- ## IfElse(WriteFieldName, "PassedCount: ", "") &
-- ## to_string( PassedCount ) & Suffix
-- ## ) ;
WriteLine(TestFile, buf) ;
end procedure WriteOneTestSummary ;
------------------------------------------------------------
-- pt local
procedure WriteTestSummary (
------------------------------------------------------------
file TestFile : text ;
Prefix : string := "" ;
Suffix : string := "" ;
ExternalErrors : AlertCountType := (0,0,0) ;
WriteFieldName : boolean := FALSE
) is
-- Format: Action Count min1 max1 min2 max2
variable TotalErrors : integer ;
variable TotalAlertErrors, TotalDisabledAlertErrors : integer ;
variable TotalRequirementsPassed, TotalRequirementsGoal : integer ;
variable TotalRequirementErrors : integer ;
variable TotalAlertCount, DisabledAlertCount : AlertCountType ;
constant AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
variable PassedCount, AffirmCount : integer ;
constant DELIMITER : string := ", " ;
begin
--!!
--!! Update to use CalcTopTotalErrors
--!!
TotalAlertCount := AlertLogPtr(AlertLogID).AlertCount + ExternalErrors ;
TotalAlertErrors := SumAlertCount( RemoveNonFailingWarnings(TotalAlertCount)) ;
DisabledAlertCount := GetDisabledAlertCount(AlertLogID) ;
TotalDisabledAlertErrors := SumAlertCount( RemoveNonFailingWarnings(DisabledAlertCount) ) ;
GetRequirementsCount(AlertLogID, TotalRequirementsPassed, TotalRequirementsGoal) ;
TotalRequirementErrors := TotalRequirementsGoal - TotalRequirementsPassed ;
TotalErrors := TotalAlertErrors ;
if FailOnDisabledErrorsVar then
TotalErrors := TotalErrors + TotalDisabledAlertErrors ;
TotalAlertCount := TotalAlertCount + DisabledAlertCount ;
end if ;
if FailOnRequirementErrorsVar then
TotalErrors := TotalErrors + TotalRequirementErrors ;
end if ;
GetPassedAffirmCount(AlertLogID, PassedCount, AffirmCount) ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => AlertLogID,
RequirementsGoal => TotalRequirementsGoal,
RequirementsPassed => TotalRequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => TotalAlertCount,
AffirmCount => AffirmCount,
PassedCount => PassedCount,
Delimiter => DELIMITER,
Prefix => Prefix,
Suffix => Suffix,
WriteFieldName => WriteFieldName
) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind ;
Prefix : string ;
Suffix : string ;
ExternalErrors : AlertCountType ;
WriteFieldName : boolean
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummary(TestFile => TestFile, Prefix => Prefix, Suffix => Suffix, ExternalErrors => ExternalErrors, WriteFieldName => WriteFieldName) ;
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries ( -- PT Local
------------------------------------------------------------
file TestFile : text ;
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
-- Descend from WriteRequirements
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
WriteOneTestSummary(
TestFile => TestFile,
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
WriteTestSummaries(TestFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file TestFile : text open OpenKind is FileName ;
begin
WriteTestSummaries(
TestFile => TestFile,
AlertLogID => REQUIREMENT_ALERTLOG_ID
) ;
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportOneTestSummary ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
RequirementsGoal : integer ;
RequirementsPassed : integer ;
TotalErrors : integer ;
AlertCount : AlertCountType ;
AffirmCount : integer ;
PassedCount : integer ;
Delimiter : string
) is
variable buf : line ;
-- constant ReportPrefix : string := ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt ) ;
-- constant PassName : string := ResolveOsvvmPassName(PassNameVar.GetOpt ) ;
-- constant FailName : string := ResolveOsvvmFailName(FailNameVar.GetOpt ) ;
begin
-- write(buf, ReportPrefix & " ") ;
write(buf, ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & " ") ;
if (AffirmCount > 0) and (TotalErrors = 0) then
-- write(buf, PassName) ;
write(buf, ResolveOsvvmPassName(PassNameVar.GetOpt)) ;
elsif TotalErrors > 0 then
-- write(buf, FailName) ;
write(buf, ResolveOsvvmFailName(FailNameVar.GetOpt)) ;
else
write(buf, string'("ReportTestSummaries Warning: No checking done. ")) ;
end if ;
write(buf, " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar)) ;
write(buf, " Total Error(s) = " & to_string(TotalErrors) ) ;
write(buf, " Failures: " & to_string(AlertCount(FAILURE) ) ) ;
write(buf, " Errors: " & to_string(AlertCount(ERROR) ) ) ;
write(buf, " Warnings: " & to_string(AlertCount(WARNING) ) ) ;
write(buf, " Affirmations Passed: " & to_string(PassedCount) &
" of " & to_string(AffirmCount)) ;
write(buf, " Requirements Passed: " & to_string(RequirementsPassed) &
" of " & to_string(RequirementsGoal) ) ;
WriteLine(buf) ;
end procedure ReportOneTestSummary ;
------------------------------------------------------------
procedure ReportTestSummaries ( -- PT Local
------------------------------------------------------------
AlertLogID : AlertLogIDType
) is
variable CurID : AlertLogIDType ;
variable TotalErrors, RequirementsGoal, RequirementsPassed : integer ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
TotalErrors := AlertLogPtr(CurID).TotalErrors ;
RequirementsGoal := AlertLogPtr(CurID).PassedGoal ;
RequirementsPassed := AlertLogPtr(CurID).PassedCount ;
if AlertLogPtr(CurID).AffirmCount <= 0 and FailOnRequirementErrorsVar and
(RequirementsGoal > RequirementsPassed) then
-- Add errors for tests that did not run.
TotalErrors := RequirementsGoal - RequirementsPassed ;
end if ;
ReportOneTestSummary(
AlertLogID => CurID,
RequirementsGoal => RequirementsGoal,
RequirementsPassed => RequirementsPassed,
TotalErrors => TotalErrors,
AlertCount => AlertLogPtr(CurID).AlertCount,
AffirmCount => AlertLogPtr(CurID).AffirmCount,
PassedCount => AlertLogPtr(CurID).AffirmPassedCount,
Delimiter => ","
) ;
ReportTestSummaries(
AlertLogID => CurID
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
variable IgnoredValue, OldReportJustifyAmount : integer ;
constant Separator : string := ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) ;
begin
OldReportJustifyAmount := ReportJustifyAmountVar ;
(IgnoredValue, ReportJustifyAmountVar) := CalcJustify(REQUIREMENT_ALERTLOG_ID, 0, 0, Separator'length) ;
ReportTestSummaries(AlertLogID => REQUIREMENT_ALERTLOG_ID) ;
ReportJustifyAmountVar := OldReportJustifyAmount ;
end procedure ReportTestSummaries ;
------------------------------------------------------------
-- pt local
procedure WriteAlerts ( -- pt local
file AlertsFile : text ;
AlertLogID : AlertLogIDType
) is
------------------------------------------------------------
-- Format: Name, PassedGoal, #Passed, #TotalErrors, FAILURE, ERROR, WARNING, Affirmations
variable buf : line ;
variable AlertCountVar : AlertCountType ;
constant DELIMITER : character := ',' ;
variable CurID : AlertLogIDType ;
begin
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
write(buf, AlertLogPtr(CurID).Name.all) ;
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedGoal)) ;
-- Handling for PassedCount > PassedGoal done in ReadRequirements
write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ;
AlertCountVar := AlertLogPtr(CurID).AlertCount ;
if FailOnDisabledErrorsVar then
AlertCountVar := AlertCountVar + AlertLogPtr(CurID).DisabledAlertCount ;
end if;
-- TotalErrors
write(buf, DELIMITER & to_string( SumAlertCount(RemoveNonFailingWarnings(AlertCountVar)))) ;
write(buf, DELIMITER & to_string( AlertCountVar(FAILURE) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(ERROR) )) ;
write(buf, DELIMITER & to_string( AlertCountVar(WARNING) )) ;
write(buf, DELIMITER & to_string( AlertLogPtr(CurID).AffirmCount )) ;
-- write(buf, DELIMITER & to_string(AlertLogPtr(CurID).PassedCount)) ; -- redundancy intentional, for reading WriteTestSummary
WriteLine(AlertsFile, buf) ;
WriteAlerts(AlertsFile, CurID) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(RequirementsFile) ;
if IsRequirement(localAlertLogID) then
WriteAlerts(RequirementsFile, localAlertLogID) ;
else
Alert("WriteRequirements: Called without a Requirement") ;
WriteAlerts(RequirementsFile, REQUIREMENT_ALERTLOG_ID) ;
end if ;
end procedure WriteRequirements ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType ;
OpenKind : File_Open_Kind
) is
-- Format: Action Count min1 max1 min2 max2
file AlertsFile : text open OpenKind is FileName ;
variable LocalAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
WriteTestSummary(AlertsFile) ;
WriteAlerts(AlertsFile, localAlertLogID) ;
end procedure WriteAlerts ;
------------------------------------------------------------
procedure ReadSpecification (file SpecificationFile : text ; PassedGoalIn : integer ) is -- PT Local
------------------------------------------------------------
variable buf,Name,Description : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable PassedGoal : integer ;
variable PassedGoalSet : boolean ;
variable Char : character ;
constant DELIMITER : character := ',' ;
variable AlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
-- Format: Spec Name, [Spec Description = "",] [Requirement Goal = 0]
ReadFileLoop : while not EndFile(SpecificationFile) loop
ReadLoop : loop
ReadLine(SpecificationFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
PassedGoal := DefaultPassedGoalVar ;
PassedGoalSet := FALSE ;
-- Read Name and Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Name", FAILURE) ;
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Optional: Read Description
ReadUntilDelimiterOrEOL(buf, Description, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading Description", FAILURE) ;
if IsNumber(Description.all) then
read(Description, PassedGoal, ReadValid) ;
deallocate(Description) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal (while skipping Description)", FAILURE) ;
PassedGoalSet := TRUE ;
else
-- If rest of line is blank or comment, then skip it.
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
exit ReadLoop when Empty ;
-- Read PassedGoal
read(buf, PassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadSpecification: Failed while reading PassedGoal", FAILURE) ;
PassedGoalSet := TRUE ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ; -- For new items, sets DefaultPassedGoalVar and PassedGoalSet = FALSE.
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ;
deallocate(Name) ;
deallocate(Description) ; -- not used
-- Implementation 1: Just put the values in
-- If Override values specified, then use them.
if PassedGoalIn >= 0 then
PassedGoal := PassedGoalIn ;
PassedGoalSet := TRUE ;
end if ;
if PassedGoalSet then
-- Is there a goal to update?
if AlertLogPtr(AlertLogID).PassedGoalSet then
-- Merge Old and New
AlertLogPtr(AlertLogID).PassedGoal := maximum(PassedGoal, AlertLogPtr(AlertLogID).PassedGoal) ;
else
-- No Old, Just use New
AlertLogPtr(AlertLogID).PassedGoal := PassedGoal ;
end if ;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end if ;
end loop ReadFileLoop ;
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer ) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file SpecificationFile : text open READ_MODE is FileName ;
begin
ReadSpecification(SpecificationFile, PassedGoal) ;
end procedure ReadSpecification ;
------------------------------------------------------------
-- PT Local
procedure ReadRequirements ( -- PT Local
file RequirementsFile : text ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
constant DELIMITER : character := ',' ;
variable buf,Name : line ;
variable ReadValid : boolean ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable StopDueToCount : boolean := FALSE ;
-- variable ReadFailed : boolean := TRUE ;
variable Found : boolean ;
variable ReqPassedGoal : integer ;
variable ReqPassedCount : integer ;
variable TotalErrorCount : integer ;
variable AlertCount : AlertCountType ;
variable AffirmCount : integer ;
variable AffirmPassedCount : integer ;
variable AlertLogID : AlertLogIDType ;
begin
if not TestSummary then
-- For requirements, skip the first line that has the test summary
ReadLine(RequirementsFile, buf) ;
end if ;
ReadFileLoop : while not EndFile(RequirementsFile) loop
ReadLoop : loop
ReadLine(RequirementsFile, buf) ;
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadFileLoop when Empty ;
-- defaults
-- ReadFailed := TRUE ;
ReqPassedGoal := 0 ;
ReqPassedCount := 0 ;
TotalErrorCount := 0 ;
AlertCount := (0, 0, 0) ;
AffirmCount := 0 ;
AffirmPassedCount := 0 ;
-- Read Name. Remove delimiter
ReadUntilDelimiterOrEOL(buf, Name, DELIMITER, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading Name", FAILURE) ;
-- Read ReqPassedGoal
read(buf, ReqPassedGoal, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedGoal", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedGoal", FAILURE) ;
-- Read ReqPassedCount
read(buf, ReqPassedCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading PassedCount", FAILURE) ;
AffirmPassedCount := ReqPassedGoal ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read TotalErrorCount
read(buf, TotalErrorCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading TotalErrorCount", FAILURE) ;
AlertCount := (0, TotalErrorCount, 0) ; -- Default
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading PassedCount", FAILURE) ;
-- Read AlertCount
for i in AlertType'left to AlertType'right loop
read(buf, AlertCount(i), ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading " &
"AlertCount(" & to_string(i) & ")", FAILURE) ;
end loop ;
-- Read AffirmCount
read(buf, AffirmCount, ReadValid) ;
exit ReadFileLoop when AlertIfNot(OSVVM_ALERTLOG_ID, ReadValid,
"AlertLogPkg.ReadRequirements: Failed while reading AffirmCount", FAILURE) ;
if TestSummary then
FindDelimiter(buf, DELIMITER, Found) ;
exit ReadFileLoop when AlertIf(OSVVM_ALERTLOG_ID, not Found,
"AlertLogPkg.ReadRequirements: Failed after reading AffirmCount", FAILURE) ;
-- Read AffirmPassedCount
read(buf, AffirmPassedCount, ReadValid) ;
if not ReadValid then
AffirmPassedCount := ReqPassedGoal ;
Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadRequirements: Failed while reading AffirmPassedCount", FAILURE) ;
exit ReadFileLoop ;
end if ;
end if ;
exit ReadLoop ;
end loop ReadLoop ;
-- AlertLogID := GetReqID(Name.all) ;
AlertLogID := GetReqID(Name => Name.all, PassedGoal => -1, ParentID=> ALERTLOG_ID_NOT_ASSIGNED, CreateHierarchy => TRUE) ; --! GHDL
deallocate(Name) ;
-- if Merge then
-- Passed Goal
if AlertLogPtr(AlertLogID).PassedGoalSet then
AlertLogPtr(AlertLogID).PassedGoal := maximum(AlertLogPtr(AlertLogID).PassedGoal, ReqPassedGoal) ;
else
AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
end if ;
-- Requirements Passed Count
if ThresholdPassed then
ReqPassedCount := minimum(ReqPassedCount, ReqPassedGoal) ;
end if ;
AlertLogPtr(AlertLogID).PassedCount := AlertLogPtr(AlertLogID).PassedCount + ReqPassedCount ;
AlertLogPtr(AlertLogID).TotalErrors := AlertLogPtr(AlertLogID).TotalErrors + TotalErrorCount ;
-- AlertCount
IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
-- AffirmCount
AlertLogPtr(AlertLogID).AffirmCount := AlertLogPtr(AlertLogID).AffirmCount + AffirmCount ;
AlertLogPtr(AlertLogID).AffirmPassedCount := AlertLogPtr(AlertLogID).AffirmPassedCount + AffirmPassedCount ;
-- else
-- AlertLogPtr(AlertLogID).PassedGoal := ReqPassedGoal ;
-- AlertLogPtr(AlertLogID).PassedCount := ReqPassedCount ;
--
-- IncrementAlertCount(AlertLogID, FAILURE, StopDueToCount, AlertCount(FAILURE)) ;
-- IncrementAlertCount(AlertLogID, ERROR, StopDueToCount, AlertCount(ERROR)) ;
-- IncrementAlertCount(AlertLogID, WARNING, StopDueToCount, AlertCount(WARNING)) ;
--
-- AlertLogPtr(AlertLogID).AffirmCount := ReqPassedCount + TotalErrorCount ;
-- end if;
AlertLogPtr(AlertLogID).PassedGoalSet := TRUE ;
end loop ReadFileLoop ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadRequirements (
FileName : string ;
ThresholdPassed : boolean ;
TestSummary : boolean
) is
------------------------------------------------------------
-- Format: Action Count min1 max1 min2 max2
file RequirementsFile : text open READ_MODE is FileName ;
begin
ReadRequirements(RequirementsFile, ThresholdPassed, TestSummary) ;
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
AlertCount := (0, 0, 0) ;
ErrorCount := 0 ;
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertCount := (0, 0, 0) ;
AlertLogPtr(i).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(i).AffirmCount := 0 ;
AlertLogPtr(i).PassedCount := 0 ;
AlertLogPtr(i).PassedGoal := 0 ;
end loop ;
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
AlertLogPtr(ALERTLOG_BASE_ID).AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
for i in ALERTLOG_BASE_ID + 1 to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertStopCount := (FAILURE => integer'right, ERROR => integer'right, WARNING => integer'right) ;
end loop ;
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
-- PT Local
procedure LocalLog (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType
) is
variable buf : line ;
variable ParentID : AlertLogIDType ;
-- constant LogPrefix : string := LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
begin
-- Print %% log (nominally)
-- write(buf, LogPrefix) ;
write(buf, LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) ;
-- Debug Mode
if WriteLogErrorCountVar then
if WriteAlertErrorCountVar then
if ErrorCount > 0 then
write(buf, ' ' & justify(to_string(ErrorCount), RIGHT, 2)) ;
else
swrite(buf, " ") ;
end if ;
end if ;
end if ;
-- Level Name, when enabled (default)
if WriteLogLevelVar then
write(buf, " " & LOG_NAME(Level) ) ;
end if ;
-- AlertLog Name
if FoundAlertHierVar and WriteLogNameVar then
if AlertLogPtr(AlertLogID).PrintParent = PRINT_NAME then
write(buf, " in " & LeftJustify(AlertLogPtr(AlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
else
ParentID := AlertLogPtr(AlertLogID).ParentID ;
write(buf, " in " & LeftJustify(AlertLogPtr(ParentID).Name.all & ResolveOsvvmIdSeparator(IdSeparatorVar.GetOpt) &
AlertLogPtr(AlertLogID).Name.all & ',', AlertLogJustifyAmountVar) ) ;
end if ;
end if ;
-- Prefix
if AlertLogPtr(AlertLogID).Prefix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Prefix.all) ;
end if ;
-- Message
write(buf, " " & Message) ;
-- Suffix
if AlertLogPtr(AlertLogID).Suffix /= NULL then
write(buf, ' ' & AlertLogPtr(AlertLogID).Suffix.all) ;
end if ;
-- Time
if WriteLogTimeVar then
write(buf, " at " & to_string(NOW, 1 ns)) ;
end if ;
writeline(buf) ;
end procedure LocalLog ;
------------------------------------------------------------
procedure log (
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS or Enable then
LocalLog(localAlertLogID, Message, Level) ;
elsif AlertLogPtr(localAlertLogID).LogEnabled(Level) then
LocalLog(localAlertLogID, Message, Level) ;
end if ;
if Level = PASSED then
IncAffirmPassedCount(AlertLogID) ; -- count the passed and affirmation
end if ;
end procedure log ;
------------------------------------------------------------
------------------------------------------------------------
-- AlertLog Structure Creation and Interaction Methods
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
Deallocate(AlertLogPtr(ALERTLOG_BASE_ID).Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).Name := new string'(Name) ;
AlertLogPtr(ALERTLOG_BASE_ID).NameLower := new string'(to_lower(NAME)) ;
end procedure SetAlertLogName ;
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Name.all ;
end function GetAlertLogName ;
------------------------------------------------------------
-- PT Local
procedure DeQueueID(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable ParentID, CurID : AlertLogIDType ;
begin
ParentID := AlertLogPtr(AlertLogID).ParentID ;
CurID := AlertLogPtr(ParentID).ChildID ;
-- Found at top of list
if AlertLogPtr(ParentID).ChildID = AlertLogID then
AlertLogPtr(ParentID).ChildID := AlertLogPtr(AlertLogID).SiblingID ;
else
-- Find among Siblings
loop
if AlertLogPtr(CurID).SiblingID = AlertLogID then
AlertLogPtr(CurID).SiblingID := AlertLogPtr(AlertLogID).SiblingID ;
exit ;
end if ;
if AlertLogPtr(CurID).SiblingID <= ALERTLOG_BASE_ID then
Alert("DeQueueID: AlertLogID not found") ;
exit ;
end if ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure DeQueueID ;
------------------------------------------------------------
-- PT Local
procedure EnQueueID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
AlertLogPtr(AlertLogID).ParentID := ParentID ;
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
if AlertLogPtr(ParentID).ChildID < ALERTLOG_BASE_ID then
AlertLogPtr(ParentID).ChildID := AlertLogID ;
else
CurID := AlertLogPtr(ParentID).ChildIDLast ;
AlertLogPtr(CurID).SiblingID := AlertLogID ;
end if ;
AlertLogPtr(ParentID).ChildIDLast := AlertLogID ;
end procedure EnQueueID ;
------------------------------------------------------------
-- PT Local
procedure NewAlertLogRec(AlertLogID : AlertLogIDType ; iName : string ; ParentID : AlertLogIDType; ReportMode : AlertLogReportModeType := ENABLED; PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT) is
------------------------------------------------------------
variable AlertEnabled : AlertEnableType ;
variable AlertStopCount : AlertCountType ;
variable LogEnabled : LogEnableType ;
begin
AlertLogPtr(AlertLogID) := new AlertLogRecType ;
if AlertLogID = ALERTLOG_BASE_ID then
AlertEnabled := (TRUE, TRUE, TRUE) ;
LogEnabled := (others => FALSE) ;
AlertStopCount := (FAILURE => 0, ERROR => integer'right, WARNING => integer'right) ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, TRUE) ;
else
if ParentID < ALERTLOG_BASE_ID then
AlertEnabled := AlertLogPtr(ALERTLOG_BASE_ID).AlertEnabled ;
LogEnabled := AlertLogPtr(ALERTLOG_BASE_ID).LogEnabled ;
EnQueueID(AlertLogID, ALERTLOG_BASE_ID, FALSE) ;
else
AlertEnabled := AlertLogPtr(ParentID).AlertEnabled ;
LogEnabled := AlertLogPtr(ParentID).LogEnabled ;
EnQueueID(AlertLogID, ParentID, TRUE) ;
end if ;
AlertStopCount := (FAILURE | ERROR | WARNING => integer'right) ;
end if ;
AlertLogPtr(AlertLogID).Name := new string'(iName) ;
AlertLogPtr(AlertLogID).NameLower := new string'(to_lower(iName)) ;
AlertLogPtr(AlertLogID).AlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).DisabledAlertCount := (0, 0, 0) ;
AlertLogPtr(AlertLogID).AffirmCount := 0 ;
AlertLogPtr(AlertLogID).PassedCount := 0 ;
AlertLogPtr(AlertLogID).PassedGoal := 0 ;
AlertLogPtr(AlertLogID).AlertEnabled := AlertEnabled ;
AlertLogPtr(AlertLogID).AlertStopCount := AlertStopCount ;
AlertLogPtr(AlertLogID).AlertPrintCount := (FAILURE | ERROR | WARNING => integer'right) ;
AlertLogPtr(AlertLogID).LogEnabled := LogEnabled ;
AlertLogPtr(AlertLogID).ReportMode := ReportMode ;
-- Update PrintParent
if ParentID > ALERTLOG_BASE_ID then
AlertLogPtr(AlertLogID).PrintParent := PrintParent ;
else
AlertLogPtr(AlertLogID).PrintParent := PRINT_NAME ;
end if ;
-- Set ChildID, ChildIDLast, SiblingID to ALERTLOG_ID_NOT_ASSIGNED
AlertLogPtr(AlertLogID).SiblingID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildID := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).ChildIDLast := ALERTLOG_ID_NOT_ASSIGNED ;
AlertLogPtr(AlertLogID).TotalErrors := 0 ;
AlertLogPtr(AlertLogID).AffirmPassedCount := 0 ;
end procedure NewAlertLogRec ;
------------------------------------------------------------
-- PT Local
-- Construct initial data structure
procedure LocalInitialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
if NumAllocatedAlertLogIDsVar /= 0 then
Alert(ALERT_DEFAULT_ID, "AlertLogPkg: Initialize, data structure already initialized", FAILURE) ;
return ;
end if ;
-- Initialize Pointer
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to ALERTLOG_BASE_ID + NewNumAlertLogIDs) ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
-- Create BASE AlertLogID (if it differs from DEFAULT
NewAlertLogRec(ALERTLOG_BASE_ID, "AlertLogTop", ALERTLOG_BASE_ID) ;
-- Create DEFAULT AlertLogID
NewAlertLogRec(ALERT_DEFAULT_ID, "Default", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := ALERT_DEFAULT_ID ;
-- Create OSVVM AlertLogID (if it differs from DEFAULT
if OSVVM_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(OSVVM_ALERTLOG_ID, "OSVVM", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if REQUIREMENT_ALERTLOG_ID /= ALERT_DEFAULT_ID then
NewAlertLogRec(REQUIREMENT_ALERTLOG_ID, "Requirements", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
if OSVVM_SCOREBOARD_ALERTLOG_ID /= OSVVM_ALERTLOG_ID then
NewAlertLogRec(OSVVM_SCOREBOARD_ALERTLOG_ID, "OSVVM Scoreboard", ALERTLOG_BASE_ID) ;
NumAlertLogIDsVar := NumAlertLogIDsVar + 1 ;
end if ;
end procedure LocalInitialize ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize(NewNumAlertLogIDs : AlertLogIDType := MIN_NUM_AL_IDS) is
------------------------------------------------------------
begin
LocalInitialize(NewNumAlertLogIDs) ;
end procedure Initialize ;
------------------------------------------------------------
-- PT Local
-- Constructs initial data structure using constant below
impure function LocalInitialize return boolean is
------------------------------------------------------------
begin
LocalInitialize(MIN_NUM_AL_IDS) ;
return TRUE ;
end function LocalInitialize ;
constant CONSTRUCT_ALERT_DATA_STRUCTURE : boolean := LocalInitialize ;
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
Deallocate(AlertLogPtr(i).Name) ;
Deallocate(AlertLogPtr(i)) ;
end loop ;
deallocate(AlertLogPtr) ;
-- Free up space used by protected types within AlertLogPkg
AlertPrefixVar.Deallocate ;
LogPrefixVar.Deallocate ;
ReportPrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
-- Restore variables to their initial state
PrintPassedVar := TRUE ;
PrintAffirmationsVar := FALSE ;
PrintDisabledAlertsVar := FALSE ;
PrintRequirementsVar := FALSE ;
PrintIfHaveRequirementsVar := TRUE ;
DefaultPassedGoalVar := 1 ;
NumAlertLogIDsVar := 0 ;
NumAllocatedAlertLogIDsVar := 0 ;
GlobalAlertEnabledVar := TRUE ; -- Allows turn off and on
AffirmCheckCountVar := 0 ;
PassedCountVar := 0 ;
FailOnWarningVar := TRUE ;
FailOnDisabledErrorsVar := TRUE ;
FailOnRequirementErrorsVar := TRUE ;
ReportHierarchyVar := TRUE ;
FoundReportHierVar := FALSE ;
FoundAlertHierVar := FALSE ;
WriteAlertErrorCountVar := FALSE ;
WriteAlertLevelVar := TRUE ;
WriteAlertNameVar := TRUE ;
WriteAlertTimeVar := TRUE ;
WriteLogErrorCountVar := FALSE ;
WriteLogLevelVar := TRUE ;
WriteLogNameVar := TRUE ;
WriteLogTimeVar := TRUE ;
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
-- PT Local.
procedure GrowAlertStructure (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NumAllocatedAlertLogIDsVar = 0 then
Initialize (NewNumAlertLogIDs) ; -- Construct initial structure
else
oldAlertLogPtr := AlertLogPtr ;
AlertLogPtr := new AlertLogArrayType(ALERTLOG_BASE_ID to NewNumAlertLogIDs) ;
AlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) := oldAlertLogPtr(ALERTLOG_BASE_ID to NumAlertLogIDsVar) ;
deallocate(oldAlertLogPtr) ;
end if ;
NumAllocatedAlertLogIDsVar := NewNumAlertLogIDs ;
end procedure GrowAlertStructure ;
------------------------------------------------------------
-- Sets a AlertLogPtr to a particular size
-- Use for small bins to save space or large bins to
-- suppress the resize and copy in autosizes.
procedure SetNumAlertLogIDs (NewNumAlertLogIDs : AlertLogIDType) is
------------------------------------------------------------
variable oldAlertLogPtr : AlertLogArrayPtrType ;
begin
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NewNumAlertLogIDs) ;
end if;
end procedure SetNumAlertLogIDs ;
------------------------------------------------------------
-- PT Local
impure function GetNextAlertLogID return AlertLogIDType is
------------------------------------------------------------
variable NewNumAlertLogIDs : AlertLogIDType ;
begin
NewNumAlertLogIDs := NumAlertLogIDsVar + 1 ;
if NewNumAlertLogIDs > NumAllocatedAlertLogIDsVar then
GrowAlertStructure(NumAllocatedAlertLogIDsVar + MIN_NUM_AL_IDS) ;
end if ;
NumAlertLogIDsVar := NewNumAlertLogIDs ;
return NumAlertLogIDsVar ;
end function GetNextAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
for i in ALERTLOG_BASE_ID+1 to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
impure function LocalFindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
constant NameLower : string := to_lower(Name) ;
begin
if ParentID = ALERTLOG_ID_NOT_ASSIGNED then
return FindAlertLogID(Name) ;
else
for i in ALERTLOG_BASE_ID+1 to NumAlertLogIDsVar loop
if NameLower = AlertLogPtr(i).NameLower.all and
(AlertLogPtr(i).ParentID = ParentID or AlertLogPtr(i).ParentIDSet = FALSE)
then
return i ;
end if ;
end loop ;
return ALERTLOG_ID_NOT_FOUND ; -- not found
end if ;
end function LocalFindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED) ;
return LocalFindAlertLogID(Name, localParentID) ;
end function FindAlertLogID ;
------------------------------------------------------------
-- PT Local
procedure AdjustID(AlertLogID, ParentID : AlertLogIDType ; ParentIDSet : boolean := TRUE) is
------------------------------------------------------------
begin
if IsRequirement(AlertLogID) and not IsRequirement(ParentID) then
Alert(AlertLogID, "GetAlertLogID/GetReqID: Parent of a Requirement must be a Requirement") ;
else
if ParentID /= AlertLogPtr(AlertLogID).ParentID then
DeQueueID(AlertLogID) ;
EnQueueID(AlertLogID, ParentID, ParentIDSet) ;
else
AlertLogPtr(AlertLogID).ParentIDSet := ParentIDSet ;
end if ;
end if ;
end procedure AdjustID ;
------------------------------------------------------------
impure function NewID(
Name : string ;
ParentID : AlertLogIDType ;
ReportMode : AlertLogReportModeType ;
PrintParent : AlertLogPrintParentType ;
CreateHierarchy : boolean
) return AlertLogIDType is
-- impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType; CreateHierarchy : Boolean; DoNotReport : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID = ALERTLOG_ID_NOT_FOUND then
-- Create a new ID
ResultID := GetNextAlertLogID ;
NewAlertLogRec(ResultID, Name, localParentID, ReportMode, PrintParent) ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy and ReportMode /= DISABLED then
FoundReportHierVar := TRUE ;
end if ;
AlertLogPtr(ResultID).PassedGoal := 0 ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
else
-- Found existing ID. Update it.
if AlertLogPtr(ResultID).ParentIDSet = FALSE then
if localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
-- Update ParentID and potentially relocate in the structure
AdjustID(ResultID, localParentID, TRUE) ;
-- Update PrintParent
if localParentID /= ALERTLOG_BASE_ID then
AlertLogPtr(ResultID).PrintParent := PrintParent ;
else
AlertLogPtr(ResultID).PrintParent := PRINT_NAME ;
end if ;
-- else -- do not update as ParentIDs are either same or input localParentID = ALERTLOG_ID_NOT_ASSIGNED
end if ;
end if ;
end if ;
return ResultID ;
end function NewID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer ; ParentID : AlertLogIDType ; CreateHierarchy : Boolean) return AlertLogIDType is
------------------------------------------------------------
variable ResultID : AlertLogIDType ;
variable localParentID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localParentID := VerifyID(ParentID, ALERTLOG_ID_NOT_ASSIGNED, ALERTLOG_ID_NOT_ASSIGNED) ;
ResultID := LocalFindAlertLogID(Name, localParentID) ;
if ResultID = ALERTLOG_ID_NOT_FOUND then
-- Create a new ID
ResultID := GetNextAlertLogID ;
if localParentID = ALERTLOG_ID_NOT_ASSIGNED then
NewAlertLogRec(ResultID, Name, REQUIREMENT_ALERTLOG_ID, ENABLED, PRINT_NAME) ;
AlertLogPtr(ResultID).ParentIDSet := FALSE ;
else
-- May want just PRINT_NAME here as PRINT_NAME_AND_PARENT is not backward compatible
-- NewAlertLogRec(ResultID, Name, localParentID, ENABLED, PRINT_NAME_AND_PARENT) ;
NewAlertLogRec(ResultID, Name, localParentID, ENABLED, PRINT_NAME) ;
end if ;
FoundAlertHierVar := TRUE ;
if CreateHierarchy then
FoundReportHierVar := TRUE ;
end if ;
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
else
-- Found existing ID. Update it.
if AlertLogPtr(ResultID).ParentIDSet = FALSE then
if localParentID /= ALERTLOG_ID_NOT_ASSIGNED then
AdjustID(ResultID, localParentID, TRUE) ;
if localParentID /= REQUIREMENT_ALERTLOG_ID then
-- May want just PRINT_NAME here as PRINT_NAME_AND_PARENT is not backward compatible
-- AlertLogPtr(ResultID).PrintParent := PRINT_NAME_AND_PARENT ;
AlertLogPtr(ResultID).PrintParent := PRINT_NAME ;
else
AlertLogPtr(ResultID).PrintParent := PRINT_NAME ;
end if ;
else
-- Update if originally set by NewID/GetAlertLogID
AdjustID(ResultID, REQUIREMENT_ALERTLOG_ID, FALSE) ;
end if ;
end if ;
if AlertLogPtr(ResultID).PassedGoalSet = FALSE then
if PassedGoal >= 0 then
AlertLogPtr(ResultID).PassedGoal := PassedGoal ;
AlertLogPtr(ResultID).PassedGoalSet := TRUE ;
else
AlertLogPtr(ResultID).PassedGoal := DefaultPassedGoalVar ;
AlertLogPtr(ResultID).PassedGoalSet := FALSE ;
end if ;
end if ;
end if ;
return ResultID ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
HasRequirementsVar := TRUE ;
localAlertLogID := VerifyID(AlertLogID) ;
if PassedGoal >= 0 then
AlertLogPtr(localAlertLogID).PassedGoal := PassedGoal ;
else
AlertLogPtr(localAlertLogID).PassedGoal := DefaultPassedGoalVar ;
end if ;
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).ParentID ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Prefix := new string'(Name) ;
end if ;
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Prefix) ;
end procedure UnSetAlertLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Prefix.all ;
end function GetAlertLogPrefix ;
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
if Name'length > 0 then
AlertLogPtr(localAlertLogID).Suffix := new string'(Name) ;
end if ;
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
Deallocate(AlertLogPtr(localAlertLogID).Suffix) ;
end procedure UnSetAlertLogSuffix ;
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).Suffix.all ;
end function GetAlertLogSuffix ;
------------------------------------------------------------
------------------------------------------------------------
-- Accessor Methods
------------------------------------------------------------
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
GlobalAlertEnabledVar := A ;
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
begin
return GlobalAlertEnabledVar ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
-- PT LOCAL
procedure SetOneStopCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType ;
Count : integer
) is
begin
if AlertLogPtr(AlertLogID).AlertStopCount(Level) = integer'right then
AlertLogPtr(AlertLogID).AlertStopCount(Level) := Count ;
else
AlertLogPtr(AlertLogID).AlertStopCount(Level) :=
AlertLogPtr(AlertLogID).AlertStopCount(Level) + Count ;
end if ;
end procedure SetOneStopCount ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
SetOneStopCount(AlertLogID, Level, Count) ;
if AlertLogID /= ALERTLOG_BASE_ID then
LocalSetAlertStopCount(AlertLogPtr(AlertLogID).ParentID, Level, Count) ;
end if ;
end procedure LocalSetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertStopCount(localAlertLogID, Level, Count) ;
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertStopCount(Level) ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(Level) := Count ;
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertPrintCount(Level) ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(FAILURE) := Count(FAILURE) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(ERROR) := Count(ERROR) ;
AlertLogPtr(localAlertLogID).AlertPrintCount(WARNING) := Count(WARNING) ;
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertPrintCount ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) is
------------------------------------------------------------
variable localAlertLogID, ParentID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
ParentID := AlertLogPtr(localAlertLogID).ParentID ;
if (ParentID = ALERTLOG_BASE_ID or ParentID = REQUIREMENT_ALERTLOG_ID) then
AlertLogPtr(localAlertLogID).PrintParent := PRINT_NAME ;
else
AlertLogPtr(localAlertLogID).PrintParent := PrintParent ;
end if ;
end procedure SetAlertLogPrintParent ;
------------------------------------------------------------
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).PrintParent ;
end function GetAlertLogPrintParent ;
------------------------------------------------------------
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
AlertLogPtr(localAlertLogID).ReportMode := ReportMode ;
end procedure SetAlertLogReportMode ;
------------------------------------------------------------
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).ReportMode ;
end function GetAlertLogReportMode ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).AlertEnabled(Level) := Enable ;
end loop ;
end procedure SetAlertEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).AlertEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetAlertEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetAlertEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
return AlertLogPtr(localAlertLogID).AlertEnabled(Level) ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
for i in ALERTLOG_BASE_ID to NumAlertLogIDsVar loop
AlertLogPtr(i).LogEnabled(Level) := Enable ;
end loop ;
end procedure SetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure LocalSetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable CurID : AlertLogIDType ;
begin
AlertLogPtr(AlertLogID).LogEnabled(Level) := Enable ;
if DescendHierarchy then
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
LocalSetLogEnable(CurID, Level, Enable, DescendHierarchy) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end if ;
end procedure LocalSetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
LocalSetLogEnable(localAlertLogID, Level, Enable, DescendHierarchy) ;
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable localAlertLogID : AlertLogIDType ;
begin
localAlertLogID := VerifyID(AlertLogID) ;
if Level = ALWAYS then
return TRUE ;
else
return AlertLogPtr(localAlertLogID).LogEnabled(Level) ;
end if ;
end function GetLogEnable ;
------------------------------------------------------------
-- PT Local
procedure PrintLogLevels(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Prefix : string ;
IndentAmount : integer
) is
variable buf : line ;
variable CurID : AlertLogIDType ;
begin
write(buf, Prefix & " " & LeftJustify(AlertLogPtr(AlertLogID).Name.all, ReportJustifyAmountVar - IndentAmount)) ;
for i in LogIndexType loop
if AlertLogPtr(AlertLogID).LogEnabled(i) then
-- write(buf, " " & to_string(AlertLogPtr(AlertLogID).LogEnabled(i)) ) ;
write(buf, " " & to_string(i)) ;
end if ;
end loop ;
WriteLine(buf) ;
CurID := AlertLogPtr(AlertLogID).ChildID ;
while CurID > ALERTLOG_BASE_ID loop
-- Always print requirements
-- if CurID = REQUIREMENT_ALERTLOG_ID and HasRequirementsVar = FALSE then
-- CurID := AlertLogPtr(CurID).SiblingID ;
-- next ;
-- end if ;
PrintLogLevels(
AlertLogID => CurID,
Prefix => Prefix & " ",
IndentAmount => IndentAmount + 2
) ;
CurID := AlertLogPtr(CurID).SiblingID ;
end loop ;
end procedure PrintLogLevels ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
variable TurnedOnJustify : boolean := FALSE ;
begin
if ReportJustifyAmountVar <= 0 then
TurnedOnJustify := TRUE ;
SetJustify ;
end if ;
PrintLogLevels(ALERTLOG_BASE_ID, "", 0) ;
if TurnedOnJustify then
-- Turn it back off
SetJustify(FALSE) ;
end if ;
end procedure ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : OsvvmOptionsType ;
FailOnDisabledErrors : OsvvmOptionsType ;
FailOnRequirementErrors : OsvvmOptionsType ;
ReportHierarchy : OsvvmOptionsType ;
WriteAlertErrorCount : OsvvmOptionsType ;
WriteAlertLevel : OsvvmOptionsType ;
WriteAlertName : OsvvmOptionsType ;
WriteAlertTime : OsvvmOptionsType ;
WriteLogErrorCount : OsvvmOptionsType ;
WriteLogLevel : OsvvmOptionsType ;
WriteLogName : OsvvmOptionsType ;
WriteLogTime : OsvvmOptionsType ;
PrintPassed : OsvvmOptionsType ;
PrintAffirmations : OsvvmOptionsType ;
PrintDisabledAlerts : OsvvmOptionsType ;
PrintRequirements : OsvvmOptionsType ;
PrintIfHaveRequirements : OsvvmOptionsType ;
DefaultPassedGoal : integer ;
AlertPrefix : string ;
LogPrefix : string ;
ReportPrefix : string ;
DoneName : string ;
PassName : string ;
FailName : string ;
IdSeparator : string
) is
begin
if FailOnWarning /= OPT_INIT_PARM_DETECT then
FailOnWarningVar := IsEnabled(FailOnWarning) ;
end if ;
if FailOnDisabledErrors /= OPT_INIT_PARM_DETECT then
FailOnDisabledErrorsVar := IsEnabled(FailOnDisabledErrors) ;
end if ;
if FailOnRequirementErrors /= OPT_INIT_PARM_DETECT then
FailOnRequirementErrorsVar := IsEnabled(FailOnRequirementErrors) ;
end if ;
if ReportHierarchy /= OPT_INIT_PARM_DETECT then
ReportHierarchyVar := IsEnabled(ReportHierarchy) ;
end if ;
if WriteAlertErrorCount /= OPT_INIT_PARM_DETECT then
WriteAlertErrorCountVar := IsEnabled(WriteAlertErrorCount) ;
end if ;
if WriteAlertLevel /= OPT_INIT_PARM_DETECT then
WriteAlertLevelVar := IsEnabled(WriteAlertLevel) ;
end if ;
if WriteAlertName /= OPT_INIT_PARM_DETECT then
WriteAlertNameVar := IsEnabled(WriteAlertName) ;
end if ;
if WriteAlertTime /= OPT_INIT_PARM_DETECT then
WriteAlertTimeVar := IsEnabled(WriteAlertTime) ;
end if ;
if WriteLogErrorCount /= OPT_INIT_PARM_DETECT then
WriteLogErrorCountVar := IsEnabled(WriteLogErrorCount) ;
end if ;
if WriteLogLevel /= OPT_INIT_PARM_DETECT then
WriteLogLevelVar := IsEnabled(WriteLogLevel) ;
end if ;
if WriteLogName /= OPT_INIT_PARM_DETECT then
WriteLogNameVar := IsEnabled(WriteLogName) ;
end if ;
if WriteLogTime /= OPT_INIT_PARM_DETECT then
WriteLogTimeVar := IsEnabled(WriteLogTime) ;
end if ;
if PrintPassed /= OPT_INIT_PARM_DETECT then
PrintPassedVar := IsEnabled(PrintPassed) ;
end if ;
if PrintAffirmations /= OPT_INIT_PARM_DETECT then
PrintAffirmationsVar := IsEnabled(PrintAffirmations) ;
end if ;
if PrintDisabledAlerts /= OPT_INIT_PARM_DETECT then
PrintDisabledAlertsVar := IsEnabled(PrintDisabledAlerts) ;
end if ;
if PrintRequirements /= OPT_INIT_PARM_DETECT then
PrintRequirementsVar := IsEnabled(PrintRequirements) ;
end if ;
if PrintIfHaveRequirements /= OPT_INIT_PARM_DETECT then
PrintIfHaveRequirementsVar := IsEnabled(PrintIfHaveRequirements) ;
end if ;
if DefaultPassedGoal > 0 then
DefaultPassedGoalVar := DefaultPassedGoal ;
end if ;
if AlertPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
AlertPrefixVar.Set(AlertPrefix) ;
end if ;
if LogPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
LogPrefixVar.Set(LogPrefix) ;
end if ;
if ReportPrefix /= OSVVM_STRING_INIT_PARM_DETECT then
ReportPrefixVar.Set(ReportPrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
if IdSeparator /= OSVVM_STRING_INIT_PARM_DETECT then
IdSeparatorVar.Set(FailName) ;
end if ;
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
variable buf : line ;
begin
-- Boolean Values
swrite(buf, "ReportAlertLogOptions" & LF ) ;
swrite(buf, "---------------------" & LF ) ;
swrite(buf, "FailOnWarningVar: " & to_string(FailOnWarningVar ) & LF ) ;
swrite(buf, "FailOnDisabledErrorsVar: " & to_string(FailOnDisabledErrorsVar ) & LF ) ;
swrite(buf, "FailOnRequirementErrorsVar: " & to_string(FailOnRequirementErrorsVar ) & LF ) ;
swrite(buf, "ReportHierarchyVar: " & to_string(ReportHierarchyVar ) & LF ) ;
swrite(buf, "FoundReportHierVar: " & to_string(FoundReportHierVar ) & LF ) ; -- Not set by user
swrite(buf, "FoundAlertHierVar: " & to_string(FoundAlertHierVar ) & LF ) ; -- Not set by user
swrite(buf, "WriteAlertErrorCountVar: " & to_string(WriteAlertErrorCountVar ) & LF ) ;
swrite(buf, "WriteAlertLevelVar: " & to_string(WriteAlertLevelVar ) & LF ) ;
swrite(buf, "WriteAlertNameVar: " & to_string(WriteAlertNameVar ) & LF ) ;
swrite(buf, "WriteAlertTimeVar: " & to_string(WriteAlertTimeVar ) & LF ) ;
swrite(buf, "WriteLogErrorCountVar: " & to_string(WriteLogErrorCountVar ) & LF ) ;
swrite(buf, "WriteLogLevelVar: " & to_string(WriteLogLevelVar ) & LF ) ;
swrite(buf, "WriteLogNameVar: " & to_string(WriteLogNameVar ) & LF ) ;
swrite(buf, "WriteLogTimeVar: " & to_string(WriteLogTimeVar ) & LF ) ;
swrite(buf, "PrintPassedVar: " & to_string(PrintPassedVar ) & LF ) ;
swrite(buf, "PrintAffirmationsVar: " & to_string(PrintAffirmationsVar ) & LF ) ;
swrite(buf, "PrintDisabledAlertsVar: " & to_string(PrintDisabledAlertsVar ) & LF ) ;
swrite(buf, "PrintRequirementsVar: " & to_string(PrintRequirementsVar ) & LF ) ;
swrite(buf, "PrintIfHaveRequirementsVar: " & to_string(PrintIfHaveRequirementsVar ) & LF ) ;
-- String
swrite(buf, "AlertPrefixVar: " & string'(AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX)) & LF ) ;
swrite(buf, "LogPrefixVar: " & string'(LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX)) & LF ) ;
swrite(buf, "ReportPrefixVar: " & ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) & LF ) ;
swrite(buf, "DoneNameVar: " & ResolveOsvvmDoneName(DoneNameVar.GetOpt) & LF ) ;
swrite(buf, "PassNameVar: " & ResolveOsvvmPassName(PassNameVar.GetOpt) & LF ) ;
swrite(buf, "FailNameVar: " & ResolveOsvvmFailName(FailNameVar.GetOpt) & LF ) ;
writeline(buf) ;
end procedure ReportAlertLogOptions ;
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnWarningVar) ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnDisabledErrorsVar) ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(FailOnRequirementErrorsVar) ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(ReportHierarchyVar) ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return FoundReportHierVar ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return FoundAlertHierVar ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertErrorCountVar) ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertLevelVar) ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertNameVar) ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteAlertTimeVar) ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogErrorCountVar) ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogLevelVar) ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogNameVar) ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(WriteLogTimeVar) ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintPassedVar) ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintAffirmationsVar) ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintDisabledAlertsVar) ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintRequirementsVar) ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return to_OsvvmOptionsType(PrintIfHaveRequirementsVar) ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return DefaultPassedGoalVar ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertPrefixVar.Get(OSVVM_DEFAULT_ALERT_PREFIX) ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return LogPrefixVar.Get(OSVVM_DEFAULT_LOG_PREFIX) ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return ResolveOsvvmWritePrefix(ReportPrefixVar.GetOpt) ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return ResolveOsvvmDoneName(DoneNameVar.GetOpt) ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return ResolveOsvvmPassName(PassNameVar.GetOpt) ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return ResolveOsvvmFailName(FailNameVar.GetOpt) ;
end function GetAlertLogFailName ;
end protected body AlertLogStructPType ;
shared variable AlertLogStruct : AlertLogStructPType ;
-- synthesis translate_on
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
------------------------------------------------------------
procedure Alert(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure Alert( Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
-- synthesis translate_on
end procedure alert ;
------------------------------------------------------------
procedure IncAlertCount(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Level : AlertType := ERROR
) is
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(AlertLogID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure IncAlertCount( Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAlertCount(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
end procedure IncAlertCount ;
------------------------------------------------------------
procedure AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
procedure AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID , Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIf( not ReadValid, failure, "Read Failed") ;
impure function AlertIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(AlertLogID , Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
impure function AlertIf( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return condition ;
end function AlertIf ;
------------------------------------------------------------
procedure AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
procedure AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AlertIfNot( not ReadValid, failure, "Read Failed") ;
impure function AlertIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(AlertLogID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
impure function AlertIfNot( condition : boolean ; Message : string ; Level : AlertType := ERROR ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
if not condition then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message, Level) ;
end if ;
-- synthesis translate_on
return not condition ;
end function AlertIfNot ;
------------------------------------------------------------
-- AlertIfEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(AlertLogID, Message & " L = R, L = " & to_string(L, GetOsvvmDefaultTimeUnits)
& " R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
procedure AlertIfEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L = R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L = R, L = " & to_string(L, GetOsvvmDefaultTimeUnits)
& " R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfEqual ;
------------------------------------------------------------
-- AlertIfNotEqual with AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( AlertLogID : AlertLogIDType ; L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(AlertLogID, Message & " L /= R, L = " & to_string(L, GetOsvvmDefaultTimeUnits) &
" R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- AlertIfNotEqual without AlertLogID
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : std_logic_vector ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : unsigned ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : signed ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if not MetaMatch(L, R) then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_hxstring(L) & " R = " & to_hxstring(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : integer ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L) & " R = " & to_string(R), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : real ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, 4) & " R = " & to_string(R, 4), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : character ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : string ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & L & " R = " & R, Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
procedure AlertIfNotEqual( L, R : time ; Message : string ; Level : AlertType := ERROR ) is
------------------------------------------------------------
begin
-- synthesis translate_off
if L /= R then
AlertLogStruct.Alert(ALERT_DEFAULT_ID, Message & " L /= R, L = " & to_string(L, GetOsvvmDefaultTimeUnits) &
" R = " & to_string(R, GetOsvvmDefaultTimeUnits), Level) ;
end if ;
-- synthesis translate_on
end procedure AlertIfNotEqual ;
------------------------------------------------------------
-- Local
function LocalDiff (Line1, Line2 : string) return boolean is
-- Simple diff. Move to string handling functions?
------------------------------------------------------------
alias aLine1 : string (1 to Line1'length) is Line1 ;
alias aLine2 : string (1 to Line2'length) is Line2 ;
variable EndLine1 : integer := Line1'length;
variable EndLine2 : integer := Line2'length;
begin
-- Strip off any windows or unix end of line characters
for i in Line1'length downto 1 loop
exit when aLine1(i) /= LF and aLine1(i) /= CR ;
EndLine1 := i - 1;
end loop ;
for i in Line2'length downto 1 loop
exit when aLine2(i) /= LF and aLine2(i) /= CR ;
EndLine2 := i - 1;
end loop ;
return aLine1(1 to EndLine1) /= aLine2(1 to EndLine2) ;
end function LocalDiff ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string ; Level : AlertType ; Valid : out boolean ) is
------------------------------------------------------------
variable Buf1, Buf2 : line ;
variable File1Done, File2Done : boolean ;
variable LineCount : integer := 0 ;
begin
-- synthesis translate_off
ReadLoop : loop
File1Done := EndFile(File1) ;
File2Done := EndFile(File2) ;
exit ReadLoop when File1Done or File2Done ;
ReadLine(File1, Buf1) ;
ReadLine(File2, Buf2) ;
LineCount := LineCount + 1 ;
-- if Buf1.all /= Buf2.all then -- fails when use Windows file in Unix
if LocalDiff(Buf1.all, Buf2.all) then
AlertLogStruct.Alert(AlertLogID , Message & " File miscompare on line " & to_string(LineCount), Level) ;
exit ReadLoop ;
end if ;
end loop ReadLoop ;
if File1Done /= File2Done then
if not File1Done then
AlertLogStruct.Alert(AlertLogID , Message & " File1 longer than File2 " & to_string(LineCount), Level) ;
end if ;
if not File2Done then
AlertLogStruct.Alert(AlertLogID , Message & " File2 longer than File1 " & to_string(LineCount), Level) ;
end if ;
end if;
if File1Done and File2Done then
Valid := TRUE ;
else
Valid := FALSE ;
end if ;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
-- Local
procedure LocalAlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string ; Level : AlertType ; Valid : out boolean ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
file FileID1, FileID2 : text ;
variable status1, status2 : file_open_status ;
begin
-- synthesis translate_off
Valid := FALSE ;
file_open(status1, FileID1, Name1, READ_MODE) ;
file_open(status2, FileID2, Name2, READ_MODE) ;
if status1 = OPEN_OK and status2 = OPEN_OK then
LocalAlertIfDiff (AlertLogID, FileID1, FileID2, Message & " " & Name1 & " /= " & Name2 & ", ", Level, Valid) ;
else
if status1 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name1 & ", did not open", Level) ;
end if ;
if status2 /= OPEN_OK then
AlertLogStruct.Alert(AlertLogID , Message & " File, " & Name2 & ", did not open", Level) ;
end if ;
end if;
-- synthesis translate_on
end procedure LocalAlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
-- Open files and call AlertIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (Name1, Name2 : string; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, Name1, Name2, Message, Level, Valid) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AlertIfDiff (file File1, File2 : text; Message : string := "" ; Level : AlertType := ERROR ) is
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (ALERT_DEFAULT_ID, File1, File2, Message, Level, Valid ) ;
-- synthesis translate_on
end procedure AlertIfDiff ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
ReceivedMessage : string ;
ExpectedMessage : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, ReceivedMessage, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, ReceivedMessage & ' ' & ExpectedMessage, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, ERROR) ;
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf(condition : boolean ; Message : string ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIf( ID, not ReadValid, "Read Failed") ;
impure function AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
impure function AffirmIf( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, Enable) ;
-- synthesis translate_on
return condition ;
end function AffirmIf ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
procedure AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNot ;
------------------------------------------------------------
-- useful in a loop: exit when AffirmIfNot( not ReadValid, failure, "Read Failed") ;
impure function AffirmIfNot( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
impure function AffirmIfNot( condition : boolean ; Message : string ; Enable : boolean := FALSE ) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, not condition, Message, Enable) ;
-- synthesis translate_on
return not condition ;
end function AffirmIfNot ;
------------------------------------------------------------
------------------------------------------------------------
procedure AffirmPassed( AlertLogID : AlertLogIDType ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmPassed( Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, TRUE, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmPassed ;
------------------------------------------------------------
procedure AffirmError( AlertLogID : AlertLogIDType ; Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
------------------------------------------------------------
procedure AffirmError( Message : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, FALSE, Message, FALSE) ;
-- synthesis translate_on
end procedure AffirmError ;
-- With AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( AlertLogID : AlertLogIDType ; Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(AlertLogID, Received = Expected,
Message & " Received : " & to_string(Received, GetOsvvmDefaultTimeUnits),
"= Expected : " & to_string(Expected, GetOsvvmDefaultTimeUnits),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
-- Without AlertLogID
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : boolean ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_string(Received),
"?= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : std_logic_vector ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : unsigned ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : signed ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, MetaMatch(Received, Expected),
Message & " Received : " & to_hxstring(Received),
"?= Expected : " & to_hxstring(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : integer ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : real ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received, 4),
"= Expected : " & to_string(Expected, 4),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : character ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received),
"= Expected : " & to_string(Expected),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : string ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & Received,
"= Expected : " & Expected,
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfEqual( Received, Expected : time ; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, Received = Expected,
Message & " Received : " & to_string(Received, GetOsvvmDefaultTimeUnits),
"= Expected : " & to_string(Expected, GetOsvvmDefaultTimeUnits),
Enable) ;
-- synthesis translate_on
end procedure AffirmIfEqual ;
------------------------------------------------------------
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
-- Open files and call AffirmIfNotDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
procedure AffirmIfNotDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfNotDiff(ALERT_DEFAULT_ID, Name1, Name2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
procedure AffirmIfNotDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
procedure AffirmIfNotDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfNotDiff(ALERT_DEFAULT_ID, File1, File2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfNotDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
-- Open files and call AffirmIfDiff[text, ...]
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, Name1, Name2, Message, ERROR, Valid) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message & " " & Name1 & " = " & Name2, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (Name1, Name2 : string; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, Name1, Name2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (AlertLogID : AlertLogIDType ; file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
-- Simple diff.
------------------------------------------------------------
variable Valid : boolean ;
begin
-- synthesis translate_off
LocalAlertIfDiff (AlertLogID, File1, File2, Message, ERROR, Valid ) ;
if Valid then
AlertLogStruct.Log(AlertLogID, Message, PASSED, Enable) ;
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
-- Alert already signaled by LocalAlertIfDiff
end if ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
------------------------------------------------------------
-- DEPRECATED - naming polarity is incorrect. Should be AffirmIfNotDiff
procedure AffirmIfDiff (file File1, File2 : text; Message : string := "" ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AffirmIfDiff(ALERT_DEFAULT_ID, File1, File2, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIfDiff ;
-- Support for Specification / Requirements Tracking
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; ReceivedMessage, ExpectedMessage : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, ReceivedMessage, ExpectedMessage, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure AffirmIf( RequirementsIDName : string ; condition : boolean ; Message : string ; Enable : boolean := FALSE ) is
------------------------------------------------------------
begin
-- synthesis translate_off
--?? Set Goal to 1? Should the ID already exist?
AffirmIf(GetReqID(RequirementsIDName), condition, Message, Enable) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
procedure SetAlertLogJustify (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetJustify(Enable) ;
-- synthesis translate_on
end procedure SetAlertLogJustify ;
------------------------------------------------------------
procedure ReportAlerts ( Name : String ; AlertCount : AlertCountType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertCount) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportRequirements is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportRequirements ;
-- synthesis translate_on
end procedure ReportRequirements ;
------------------------------------------------------------
procedure ReportAlerts (
------------------------------------------------------------
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0) ;
ReportAll : Boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, ReportAll, TRUE) ;
-- synthesis translate_on
end procedure ReportAlerts ;
------------------------------------------------------------
procedure ReportNonZeroAlerts (
------------------------------------------------------------
Name : string := OSVVM_STRING_INIT_PARM_DETECT ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
ExternalErrors : AlertCountType := (others => 0)
) is
begin
-- synthesis translate_off
AlertLogStruct.ReportAlerts(Name, AlertLogID, ExternalErrors, FALSE, FALSE) ;
-- synthesis translate_on
end procedure ReportNonZeroAlerts ;
------------------------------------------------------------
procedure WriteAlertYaml (
------------------------------------------------------------
FileName : string ;
ExternalErrors : AlertCountType := (0,0,0) ;
Prefix : string := "" ;
PrintSettings : boolean := TRUE ;
PrintChildren : boolean := TRUE ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteAlertYaml(FileName, ExternalErrors, Prefix, PrintSettings, PrintChildren, OpenKind) ;
-- synthesis translate_on
end procedure WriteAlertYaml ;
------------------------------------------------------------
procedure WriteAlertSummaryYaml (FileName : string := "" ; ExternalErrors : AlertCountType := (0,0,0)) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", "OsvvmRun.yml", FileName) ;
begin
-- synthesis translate_off
WriteAlertYaml(FileName => RESOLVED_FILE_NAME, ExternalErrors => ExternalErrors, Prefix => " ", PrintSettings => FALSE, PrintChildren => FALSE, OpenKind => APPEND_MODE) ;
-- WriteTestSummary(FileName => "OsvvmRun.yml", OpenKind => APPEND_MODE, Prefix => " ", Suffix => "", ExternalErrors => ExternalErrors, WriteFieldName => TRUE) ;
-- synthesis translate_on
end procedure WriteAlertSummaryYaml ;
------------------------------------------------------------
-- Deprecated. Use WriteAlertSummaryYaml Instead.
procedure CreateYamlReport (ExternalErrors : AlertCountType := (0,0,0)) is
begin
-- synthesis translate_off
WriteAlertSummaryYaml(ExternalErrors => ExternalErrors) ;
-- synthesis translate_on
end procedure CreateYamlReport ;
------------------------------------------------------------
procedure WriteTestSummary (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := APPEND_MODE ;
Prefix : string := "" ;
Suffix : string := "" ;
ExternalErrors : AlertCountType := (0,0,0) ;
WriteFieldName : boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummary(FileName, OpenKind, Prefix, Suffix, ExternalErrors, WriteFieldName) ;
-- synthesis translate_on
end procedure WriteTestSummary ;
------------------------------------------------------------
procedure WriteTestSummaries (
------------------------------------------------------------
FileName : string ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteTestSummaries(FileName, OpenKind) ;
-- synthesis translate_on
end procedure WriteTestSummaries ;
------------------------------------------------------------
procedure ReportTestSummaries is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportTestSummaries ;
-- synthesis translate_on
end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure WriteAlerts (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteAlerts(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteAlerts ;
------------------------------------------------------------
procedure WriteRequirements (
------------------------------------------------------------
FileName : string ;
AlertLogID : AlertLogIDType := REQUIREMENT_ALERTLOG_ID ;
OpenKind : File_Open_Kind := WRITE_MODE
) is
begin
-- synthesis translate_off
AlertLogStruct.WriteRequirements(FileName, AlertLogID, OpenKind) ;
-- synthesis translate_on
end procedure WriteRequirements ;
------------------------------------------------------------
procedure ReadSpecification (FileName : string ; PassedGoal : integer := -1 ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadSpecification(FileName, PassedGoal) ;
-- synthesis translate_on
end procedure ReadSpecification ;
------------------------------------------------------------
procedure ReadRequirements (
------------------------------------------------------------
FileName : string ;
ThresholdPassed : boolean := FALSE
) is
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed, TestSummary => FALSE) ;
-- synthesis translate_on
end procedure ReadRequirements ;
------------------------------------------------------------
procedure ReadTestSummaries (FileName : string) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- synthesis translate_on
end procedure ReadTestSummaries ;
-- ------------------------------------------------------------
-- procedure ReportTestSummaries (FileName : string) is
-- ------------------------------------------------------------
-- begin
-- -- synthesis translate_off
-- AlertLogStruct.ReadRequirements(FileName, ThresholdPassed => FALSE, TestSummary => TRUE) ;
-- -- synthesis translate_on
-- end procedure ReportTestSummaries ;
------------------------------------------------------------
procedure ClearAlerts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
-- synthesis translate_on
end procedure ClearAlerts ;
------------------------------------------------------------
procedure ClearAlertStopCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertStopCounts ;
------------------------------------------------------------
procedure ClearAlertCounts is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ClearAlerts ;
AlertLogStruct.ClearAlertStopCounts ;
-- synthesis translate_on
end procedure ClearAlertCounts ;
------------------------------------------------------------
function "ABS" (L : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := ABS( L(FAILURE) ) ;
Result(ERROR) := ABS( L(ERROR) ) ;
Result(WARNING) := ABS( L(WARNING) );
-- synthesis translate_on
return Result ;
end function "ABS" ;
------------------------------------------------------------
function "+" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) + R(FAILURE) ;
Result(ERROR) := L(ERROR) + R(ERROR) ;
Result(WARNING) := L(WARNING) + R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "+" ;
------------------------------------------------------------
function "-" (L, R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := L(FAILURE) - R(FAILURE) ;
Result(ERROR) := L(ERROR) - R(ERROR) ;
Result(WARNING) := L(WARNING) - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
function "-" (R : AlertCountType) return AlertCountType is
------------------------------------------------------------
variable Result : AlertCountType ;
begin
-- synthesis translate_off
Result(FAILURE) := - R(FAILURE) ;
Result(ERROR) := - R(ERROR) ;
Result(WARNING) := - R(WARNING) ;
-- synthesis translate_on
return Result ;
end function "-" ;
------------------------------------------------------------
impure function SumAlertCount(AlertCount: AlertCountType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
-- Using ABS ensures correct expected error handling.
result := abs(AlertCount(FAILURE)) + abs(AlertCount(ERROR)) + abs(AlertCount(WARNING)) ;
-- synthesis translate_on
return result ;
end function SumAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetEnabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetEnabledAlertCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetEnabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetEnabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetDisabledAlertCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
impure function GetDisabledAlertCount(AlertLogID: AlertLogIDType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := SumAlertCount(AlertLogStruct.GetDisabledAlertCount(AlertLogID)) ;
-- synthesis translate_on
return result ;
end function GetDisabledAlertCount ;
------------------------------------------------------------
procedure Log(
------------------------------------------------------------
AlertLogID : AlertLogIDType ;
Message : string ;
Level : LogType := ALWAYS ;
Enable : boolean := FALSE -- override internal enable
) is
begin
-- synthesis translate_off
AlertLogStruct.Log(AlertLogID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure Log( Message : string ; Level : LogType := ALWAYS ; Enable : boolean := FALSE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Log(LOG_DEFAULT_ID, Message, Level, Enable) ;
-- synthesis translate_on
end procedure log ;
------------------------------------------------------------
procedure SetAlertEnable(Level : AlertType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
procedure SetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(AlertLogID : AlertLogIDType ; Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
impure function GetAlertEnable(Level : AlertType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertEnable(ALERT_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertEnable ;
------------------------------------------------------------
procedure SetLogEnable(Level : LogType ; Enable : boolean) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(Level, Enable) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
procedure SetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType ; Enable : boolean ; DescendHierarchy : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetLogEnable(AlertLogID, Level, Enable, DescendHierarchy) ;
-- synthesis translate_on
end procedure SetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(AlertLogID : AlertLogIDType ; Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
impure function GetLogEnable(Level : LogType) return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetLogEnable(LOG_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetLogEnable ;
------------------------------------------------------------
procedure ReportLogEnables is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportLogEnables ;
-- synthesis translate_on
end ReportLogEnables ;
------------------------------------------------------------
procedure SetAlertLogName(Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogName(Name) ;
-- synthesis translate_on
end procedure SetAlertLogName ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogName(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogName(AlertLogID) ;
end GetAlertLogName ;
-- synthesis translate_on
------------------------------------------------------------
procedure DeallocateAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.DeallocateAlertLogStruct ;
-- synthesis translate_on
end procedure DeallocateAlertLogStruct ;
------------------------------------------------------------
procedure InitializeAlertLogStruct is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.Initialize ;
-- synthesis translate_on
end procedure InitializeAlertLogStruct ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function FindAlertLogID(Name : string ; ParentID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.FindAlertLogID(Name, ParentID) ;
-- synthesis translate_on
return result ;
end function FindAlertLogID ;
------------------------------------------------------------
impure function NewID(
------------------------------------------------------------
Name : string ;
ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED;
ReportMode : AlertLogReportModeType := ENABLED ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT ;
CreateHierarchy : boolean := TRUE
) return AlertLogIDType is
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy) ;
-- synthesis translate_on
return result ;
end function NewID ;
------------------------------------------------------------
impure function GetAlertLogID(Name : string; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
variable ReportMode : AlertLogReportModeType := ENABLED ;
begin
-- synthesis translate_off
if DoNotReport then
ReportMode := DISABLED ;
end if;
-- PrintParent PRINT_NAME_AND_PARENT is not backward compatible with PRINT_NAME of the past
result := AlertLogStruct.NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
-- result := AlertLogStruct.GetAlertLogID(Name, ParentID, CreateHierarchy, DoNotReport) ;
-- synthesis translate_on
return result ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetReqID(Name : string ; PassedGoal : integer := -1 ; ParentID : AlertLogIDType := ALERTLOG_ID_NOT_ASSIGNED ; CreateHierarchy : Boolean := TRUE) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetReqID(Name, PassedGoal, ParentID, CreateHierarchy) ;
-- synthesis translate_on
return result ;
end function GetReqID ;
------------------------------------------------------------
procedure SetPassedGoal(AlertLogID : AlertLogIDType ; PassedGoal : integer ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetPassedGoal(AlertLogID, PassedGoal) ;
-- synthesis translate_on
end procedure SetPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogParentID(AlertLogID : AlertLogIDType) return AlertLogIDType is
------------------------------------------------------------
variable result : AlertLogIDType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogParentID(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogParentID ;
------------------------------------------------------------
procedure SetAlertLogPrefix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrefix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogPrefix ;
------------------------------------------------------------
procedure UnSetAlertLogPrefix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogPrefix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogPrefix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogPrefix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrefix(AlertLogID) ;
end function GetAlertLogPrefix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetAlertLogSuffix(AlertLogID : AlertLogIDType; Name : string ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogSuffix(AlertLogID, Name) ;
-- synthesis translate_on
end procedure SetAlertLogSuffix ;
------------------------------------------------------------
procedure UnSetAlertLogSuffix(AlertLogID : AlertLogIDType ) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.UnSetAlertLogSuffix(AlertLogID) ;
-- synthesis translate_on
end procedure UnSetAlertLogSuffix ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogSuffix(AlertLogID : AlertLogIDType) return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogSuffix(AlertLogID) ;
end function GetAlertLogSuffix ;
-- synthesis translate_on
------------------------------------------------------------
procedure SetGlobalAlertEnable (A : boolean := TRUE) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
end procedure SetGlobalAlertEnable ;
------------------------------------------------------------
-- Set using constant. Set before code runs.
impure function SetGlobalAlertEnable (A : boolean := TRUE) return boolean is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetGlobalAlertEnable(A) ;
-- synthesis translate_on
return A ;
end function SetGlobalAlertEnable ;
------------------------------------------------------------
impure function GetGlobalAlertEnable return boolean is
------------------------------------------------------------
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetGlobalAlertEnable ;
-- synthesis translate_on
return result ;
end function GetGlobalAlertEnable ;
------------------------------------------------------------
procedure IncAffirmCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmCount ;
------------------------------------------------------------
impure function GetAffirmCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmCount ;
-- synthesis translate_on
return result ;
end function GetAffirmCount ;
------------------------------------------------------------
procedure IncAffirmPassedCount(AlertLogID : AlertLogIDType := ALERTLOG_BASE_ID) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.IncAffirmPassedCount(AlertLogID) ;
-- synthesis translate_on
end procedure IncAffirmPassedCount ;
------------------------------------------------------------
impure function GetAffirmPassedCount return natural is
------------------------------------------------------------
variable result : natural ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAffirmPassedCount ;
-- synthesis translate_on
return result ;
end function GetAffirmPassedCount ;
------------------------------------------------------------
procedure SetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(AlertLogID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertStopCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertStopCount(ALERTLOG_BASE_ID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
impure function GetAlertStopCount(Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertStopCount(ALERTLOG_BASE_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertStopCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(AlertLogID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(Level : AlertType ; Count : integer) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(ALERTLOG_DEFAULT_ID, Level, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType ; Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(AlertLogID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(Level : AlertType) return integer is
------------------------------------------------------------
variable result : integer ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(ALERTLOG_DEFAULT_ID, Level) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(AlertLogID : AlertLogIDType ; Count : AlertCountType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(AlertLogID, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertPrintCount(Count : AlertCountType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertPrintCount(ALERTLOG_DEFAULT_ID, Count) ;
-- synthesis translate_on
end procedure SetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount(AlertLogID : AlertLogIDType) return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
impure function GetAlertPrintCount return AlertCountType is
------------------------------------------------------------
variable result : AlertCountType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertPrintCount(ALERTLOG_DEFAULT_ID) ;
-- synthesis translate_on
return result ;
end function GetAlertPrintCount ;
------------------------------------------------------------
procedure SetAlertLogPrintParent(AlertLogID : AlertLogIDType ; PrintParent : AlertLogPrintParentType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrintParent(AlertLogID, PrintParent) ;
-- synthesis translate_on
end procedure SetAlertLogPrintParent ;
------------------------------------------------------------
procedure SetAlertLogPrintParent( PrintParent : AlertLogPrintParentType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogPrintParent(ALERTLOG_DEFAULT_ID, PrintParent) ;
-- synthesis translate_on
end procedure SetAlertLogPrintParent ;
------------------------------------------------------------
impure function GetAlertLogPrintParent(AlertLogID : AlertLogIDType) return AlertLogPrintParentType is
------------------------------------------------------------
variable result : AlertLogPrintParentType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogPrintParent(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogPrintParent ;
------------------------------------------------------------
impure function GetAlertLogPrintParent return AlertLogPrintParentType is
------------------------------------------------------------
variable result : AlertLogPrintParentType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogPrintParent(ALERTLOG_DEFAULT_ID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogPrintParent ;
------------------------------------------------------------
procedure SetAlertLogReportMode(AlertLogID : AlertLogIDType ; ReportMode : AlertLogReportModeType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogReportMode(AlertLogID, ReportMode) ;
-- synthesis translate_on
end procedure SetAlertLogReportMode ;
------------------------------------------------------------
procedure SetAlertLogReportMode( ReportMode : AlertLogReportModeType) is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogReportMode(ALERTLOG_DEFAULT_ID, ReportMode) ;
-- synthesis translate_on
end procedure SetAlertLogReportMode ;
------------------------------------------------------------
impure function GetAlertLogReportMode(AlertLogID : AlertLogIDType) return AlertLogReportModeType is
------------------------------------------------------------
variable result : AlertLogReportModeType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogReportMode(AlertLogID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogReportMode ;
------------------------------------------------------------
impure function GetAlertLogReportMode return AlertLogReportModeType is
------------------------------------------------------------
variable result : AlertLogReportModeType ;
begin
-- synthesis translate_off
result := AlertLogStruct.GetAlertLogReportMode(ALERTLOG_DEFAULT_ID) ;
-- synthesis translate_on
return result ;
end function GetAlertLogReportMode ;
------------------------------------------------------------
procedure SetAlertLogOptions (
------------------------------------------------------------
FailOnWarning : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnDisabledErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
FailOnRequirementErrors : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
ReportHierarchy : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAlertTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogErrorCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogLevel : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogName : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteLogTime : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintPassed : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintAffirmations : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintDisabledAlerts : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
PrintIfHaveRequirements : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
DefaultPassedGoal : integer := integer'left ;
AlertPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
LogPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
ReportPrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT ;
IdSeparator : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
-- synthesis translate_off
AlertLogStruct.SetAlertLogOptions (
FailOnWarning => FailOnWarning,
FailOnDisabledErrors => FailOnDisabledErrors,
FailOnRequirementErrors => FailOnRequirementErrors,
ReportHierarchy => ReportHierarchy,
WriteAlertErrorCount => WriteAlertErrorCount,
WriteAlertLevel => WriteAlertLevel,
WriteAlertName => WriteAlertName,
WriteAlertTime => WriteAlertTime,
WriteLogErrorCount => WriteLogErrorCount,
WriteLogLevel => WriteLogLevel,
WriteLogName => WriteLogName,
WriteLogTime => WriteLogTime,
PrintPassed => PrintPassed,
PrintAffirmations => PrintAffirmations,
PrintDisabledAlerts => PrintDisabledAlerts,
PrintRequirements => PrintRequirements,
PrintIfHaveRequirements => PrintIfHaveRequirements,
DefaultPassedGoal => DefaultPassedGoal,
AlertPrefix => AlertPrefix,
LogPrefix => LogPrefix,
ReportPrefix => ReportPrefix,
DoneName => DoneName,
PassName => PassName,
FailName => FailName,
IdSeparator => IdSeparator
);
-- synthesis translate_on
end procedure SetAlertLogOptions ;
------------------------------------------------------------
procedure ReportAlertLogOptions is
------------------------------------------------------------
begin
-- synthesis translate_off
AlertLogStruct.ReportAlertLogOptions ;
-- synthesis translate_on
end procedure ReportAlertLogOptions ;
-- synthesis translate_off
------------------------------------------------------------
impure function GetAlertLogFailOnWarning return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnWarning ;
end function GetAlertLogFailOnWarning ;
------------------------------------------------------------
impure function GetAlertLogFailOnDisabledErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnDisabledErrors ;
end function GetAlertLogFailOnDisabledErrors ;
------------------------------------------------------------
impure function GetAlertLogFailOnRequirementErrors return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailOnRequirementErrors ;
end function GetAlertLogFailOnRequirementErrors ;
------------------------------------------------------------
impure function GetAlertLogReportHierarchy return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportHierarchy ;
end function GetAlertLogReportHierarchy ;
------------------------------------------------------------
impure function GetAlertLogFoundReportHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundReportHier ;
end function GetAlertLogFoundReportHier ;
------------------------------------------------------------
impure function GetAlertLogFoundAlertHier return boolean is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFoundAlertHier ;
end function GetAlertLogFoundAlertHier ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertErrorCount ;
end function GetAlertLogWriteAlertErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertLevel ;
end function GetAlertLogWriteAlertLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertName return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertName ;
end function GetAlertLogWriteAlertName ;
------------------------------------------------------------
impure function GetAlertLogWriteAlertTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteAlertTime ;
end function GetAlertLogWriteAlertTime ;
------------------------------------------------------------
impure function GetAlertLogWriteLogErrorCount return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogErrorCount ;
end function GetAlertLogWriteLogErrorCount ;
------------------------------------------------------------
impure function GetAlertLogWriteLogLevel return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogLevel ;
end function GetAlertLogWriteLogLevel ;
------------------------------------------------------------
impure function GetAlertLogWriteLogName return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogName ;
end function GetAlertLogWriteLogName ;
------------------------------------------------------------
impure function GetAlertLogWriteLogTime return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogWriteLogTime ;
end function GetAlertLogWriteLogTime ;
------------------------------------------------------------
impure function GetAlertLogPrintPassed return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintPassed ;
end function GetAlertLogPrintPassed ;
------------------------------------------------------------
impure function GetAlertLogPrintAffirmations return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintAffirmations ;
end function GetAlertLogPrintAffirmations ;
------------------------------------------------------------
impure function GetAlertLogPrintDisabledAlerts return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintDisabledAlerts ;
end function GetAlertLogPrintDisabledAlerts ;
------------------------------------------------------------
impure function GetAlertLogPrintRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintRequirements ;
end function GetAlertLogPrintRequirements ;
------------------------------------------------------------
impure function GetAlertLogPrintIfHaveRequirements return OsvvmOptionsType is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPrintIfHaveRequirements ;
end function GetAlertLogPrintIfHaveRequirements ;
------------------------------------------------------------
impure function GetAlertLogDefaultPassedGoal return integer is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDefaultPassedGoal ;
end function GetAlertLogDefaultPassedGoal ;
------------------------------------------------------------
impure function GetAlertLogAlertPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogAlertPrefix ;
end function GetAlertLogAlertPrefix ;
------------------------------------------------------------
impure function GetAlertLogLogPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogLogPrefix ;
end function GetAlertLogLogPrefix ;
------------------------------------------------------------
impure function GetAlertLogReportPrefix return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogReportPrefix ;
end function GetAlertLogReportPrefix ;
------------------------------------------------------------
impure function GetAlertLogDoneName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogDoneName ;
end function GetAlertLogDoneName ;
------------------------------------------------------------
impure function GetAlertLogPassName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogPassName ;
end function GetAlertLogPassName ;
------------------------------------------------------------
impure function GetAlertLogFailName return string is
------------------------------------------------------------
begin
return AlertLogStruct.GetAlertLogFailName ;
end function GetAlertLogFailName ;
------------------------------------------------------------
-- Package Local
procedure ToLogLevel(LogLevel : out LogType; Name : in String; LogValid : out boolean) is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then
LogLevel := PASSED ;
LogValid := TRUE ;
elsif Name = "DEBUG" then
LogLevel := DEBUG ;
LogValid := TRUE ;
elsif Name = "FINAL" then
LogLevel := FINAL ;
LogValid := TRUE ;
elsif Name = "INFO" then
LogLevel := INFO ;
LogValid := TRUE ;
else
LogLevel := ALWAYS ;
LogValid := FALSE ;
end if ;
end procedure ToLogLevel ;
------------------------------------------------------------
function IsLogEnableType (Name : String) return boolean is
------------------------------------------------------------
-- type LogType is (ALWAYS, DEBUG, FINAL, INFO, PASSED) ; -- NEVER
begin
if Name = "PASSED" then return TRUE ;
elsif Name = "DEBUG" then return TRUE ;
elsif Name = "FINAL" then return TRUE ;
elsif Name = "INFO" then return TRUE ;
end if ;
return FALSE ;
end function IsLogEnableType ;
------------------------------------------------------------
procedure ReadLogEnables (file AlertLogInitFile : text) is
-- Preferred Read format
-- Line 1: instance1_name log_enable log_enable log_enable
-- Line 2: instance2_name log_enable log_enable log_enable
-- when reading multiple log_enables on a line, they must be separated by a space
--
--- Also supports alternate format from Lyle/....
-- Line 1: instance1_name
-- Line 2: log enable
-- Line 3: instance2_name
-- Line 4: log enable
--
------------------------------------------------------------
type ReadStateType is (GET_ID, GET_ENABLE) ;
variable ReadState : ReadStateType := GET_ID ;
variable buf : line ;
variable Empty : boolean ;
variable MultiLineComment : boolean := FALSE ;
variable Name : string(1 to 80) ;
variable NameLen : integer ;
variable AlertLogID : AlertLogIDType ;
variable ReadAnEnable : boolean ;
variable LogValid : boolean ;
variable LogLevel : LogType ;
begin
ReadState := GET_ID ;
ReadLineLoop : while not EndFile(AlertLogInitFile) loop
ReadLine(AlertLogInitFile, buf) ;
if ReadAnEnable then
-- Read one or more enable values, next line read AlertLog name
-- Note that any newline with ReadAnEnable TRUE will result in
-- searching for another AlertLogID name - this includes multi-line comments.
ReadState := GET_ID ;
end if ;
ReadNameLoop : loop
EmptyOrCommentLine(buf, Empty, MultiLineComment) ;
next ReadLineLoop when Empty ;
case ReadState is
when GET_ID =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
AlertLogID := GetAlertLogID(Name(1 to NameLen), ALERTLOG_ID_NOT_ASSIGNED) ;
ReadState := GET_ENABLE ;
ReadAnEnable := FALSE ;
when GET_ENABLE =>
sread(buf, Name, NameLen) ;
exit ReadNameLoop when NameLen = 0 ;
ReadAnEnable := TRUE ;
-- if not IsLogEnableType(Name(1 to NameLen)) then
-- Alert(OSVVM_ALERTLOG_ID, "AlertLogPkg.ReadLogEnables: Found Invalid LogEnable: " & Name(1 to NameLen)) ;
-- exit ReadNameLoop ;
-- end if ;
---- Log(OSVVM_ALERTLOG_ID, "SetLogEnable(OSVVM_ALERTLOG_ID, " & Name(1 to NameLen) & ", TRUE) ;", DEBUG) ;
-- LogLevel := LogType'value("" & Name(1 to NameLen)) ; -- "" & added for RivieraPro 2020.10
ToLogLevel(LogLevel, Name(1 to NameLen), LogValid) ;
exit ReadNameLoop when not LogValid ;
SetLogEnable(AlertLogID, LogLevel, TRUE) ;
end case ;
end loop ReadNameLoop ;
end loop ReadLineLoop ;
end procedure ReadLogEnables ;
------------------------------------------------------------
procedure ReadLogEnables (FileName : string) is
------------------------------------------------------------
file AlertLogInitFile : text open READ_MODE is FileName ;
begin
ReadLogEnables(AlertLogInitFile) ;
end procedure ReadLogEnables ;
------------------------------------------------------------
function PathTail (A : string) return string is
------------------------------------------------------------
alias aA : string(1 to A'length) is A ;
variable LenA : integer := A'length ;
variable Result : string(1 to A'length) ;
begin
if aA(LenA) = ':' then
LenA := LenA - 1 ;
end if ;
for i in LenA downto 1 loop
if aA(i) = ':' then
--!! GHDL Issue
-- return (1 to LenA - i => aA(i+1 to LenA)) ;
Result(1 to LenA - i) := aA(i+1 to LenA) ;
return Result(1 to LenA - i) ;
end if ;
end loop ;
return aA(1 to LenA) ;
end function PathTail ;
------------------------------------------------------------
-- MetaMatch
-- Similar to STD_MATCH, except
-- it returns TRUE for U=U, X=X, Z=Z, and W=W
-- All other values are consistent with STD_MATCH
-- MetaMatch, BooleanTableType, and MetaMatchTable are derivatives
-- of STD_MATCH from IEEE.Numeric_Std copyright by IEEE.
-- Numeric_Std is also released under the Apache License, Version 2.0.
-- Coding Styles were updated to match OSVVM
------------------------------------------------------------
type BooleanTableType is array(std_ulogic, std_ulogic) of boolean;
constant MetaMatchTable : BooleanTableType := (
--------------------------------------------------------------------------
-- U X 0 1 Z W L H -
--------------------------------------------------------------------------
(TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | U |
(FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, TRUE), -- | X |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | 0 |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | 1 |
(FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE), -- | Z |
(FALSE, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, TRUE), -- | W |
(FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, FALSE, TRUE), -- | L |
(FALSE, FALSE, FALSE, TRUE, FALSE, FALSE, FALSE, TRUE, TRUE), -- | H |
(TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE) -- | - |
);
function MetaMatch (l, r : std_ulogic) return boolean is
begin
return MetaMatchTable(l, r);
end function MetaMatch;
function MetaMatch (L, R : std_ulogic_vector) return boolean is
alias aL : std_ulogic_vector(1 to L'length) is L;
alias aR : std_ulogic_vector(1 to R'length) is R;
begin
if aL'length /= aR'length then
--! log(OSVVM_ALERTLOG_ID, "AlertLogPkg.MetaMatch: Length Mismatch", DEBUG) ;
return FALSE;
else
for i in aL'range loop
if not (MetaMatchTable(aL(i), aR(i))) then
return FALSE;
end if;
end loop;
return TRUE;
end if;
end function MetaMatch;
function MetaMatch (L, R : unresolved_unsigned) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
function MetaMatch (L, R : unresolved_signed) return boolean is
begin
return MetaMatch( std_ulogic_vector(L), std_ulogic_vector(R)) ;
end function MetaMatch;
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolvePrintParent (
------------------------------------------------------------
UniqueParent : boolean ;
PrintParent : AlertLogPrintParentType
) return AlertLogPrintParentType is
variable result : AlertLogPrintParentType ;
begin
if (not UniqueParent) and PrintParent = PRINT_NAME_AND_PARENT then
result := PRINT_NAME ;
else
result := PrintParent ;
end if ;
return result ;
end function ResolvePrintParent ;
-- synthesis translate_on
-- ------------------------------------------------------------
-- Deprecated
--
------------------------------------------------------------
-- deprecated
procedure AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIf ;
------------------------------------------------------------
-- deprecated
impure function AlertIf( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIf( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIf ;
------------------------------------------------------------
-- deprecated
procedure AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) is
begin
-- synthesis translate_off
AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
end procedure AlertIfNot ;
------------------------------------------------------------
-- deprecated
impure function AlertIfNot( condition : boolean ; AlertLogID : AlertLogIDType ; Message : string ; Level : AlertType := ERROR ) return boolean is
variable result : boolean ;
begin
-- synthesis translate_off
result := AlertIfNot( AlertLogID, condition, Message, Level) ;
-- synthesis translate_on
return result ;
end function AlertIfNot ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(
AlertLogID : AlertLogIDType ;
condition : boolean ;
Message : string ;
LogLevel : LogType ; -- := PASSED
AlertLevel : AlertType := ERROR
) is
begin
-- synthesis translate_off
if condition then
-- PASSED. Count affirmations and PASSED internal to LOG to catch all of them
AlertLogStruct.Log(AlertLogID, Message, LogLevel) ; -- call log
else
AlertLogStruct.IncAffirmCount(AlertLogID) ; -- count the affirmation
AlertLogStruct.Alert(AlertLogID, Message, AlertLevel) ; -- signal failure
end if ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf( AlertLogID : AlertLogIDType ; condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(AlertLogID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf ;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; LogLevel : LogType ; AlertLevel : AlertType := ERROR) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, LogLevel, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
------------------------------------------------------------
-- deprecated
procedure AffirmIf(condition : boolean ; Message : string ; AlertLevel : AlertType ) is
begin
-- synthesis translate_off
AffirmIf(ALERT_DEFAULT_ID, condition, Message, PASSED, AlertLevel) ;
-- synthesis translate_on
end procedure AffirmIf;
end package body AlertLogPkg ; | artistic-2.0 | 171b3f674315bd4ec64c639944e20a3c | 0.55147 | 5.443123 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/filter.vhd | 2 | 9,240 | -------------------------------------------------------------------------------
-- filter.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: filter.vhd
-- Version: v1.01.b
-- Description:
-- This file implements a simple debounce (inertial delay)
-- filter to remove short glitches from the SCL and SDA signals
-- using user definable delay parameters. SCL cross couples to
-- SDA to prevent SDA from changing near changes in SDA.
-- Notes:
-- 1) The default value for both debounce instances is '1' to conform to the
-- IIC bus default value of '1' ('H').
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axi_iic_v2_0;
use axi_iic_v2_0.debounce;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- SCL_INERTIAL_DELAY -- SCL filtering delay
-- SDA_INERTIAL_DELAY -- SDA filtering delay
-- Definition of Ports:
-- Sysclk -- System clock
-- Scl_noisy -- IIC SCL is noisy
-- Scl_clean -- IIC SCL is clean
-- Sda_noisy -- IIC SDA is Noisy
-- Sda_clean -- IIC SDA is clean
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity filter is
generic (
SCL_INERTIAL_DELAY : integer range 0 to 255 := 5;
SDA_INERTIAL_DELAY : integer range 0 to 255 := 5
);
port (
Sysclk : in std_logic;
Rst : in std_logic;
Scl_noisy : in std_logic;
Scl_clean : out std_logic;
Sda_noisy : in std_logic;
Sda_clean : out std_logic
);
end entity filter;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of filter is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
signal scl_unstable_n : std_logic;
begin
----------------------------------------------------------------------------
-- The inertial delay is cross coupled between the two IIC signals to ensure
-- that a delay in SCL because of a glitch also prevents any changes in SDA
-- until SCL is clean. This prevents inertial delay on SCL from creating a
-- situation whereby SCL is held high but SDA transitions low to high thus
-- making the core think a STOP has occured. Changes on SDA do not inihibit
-- SCL because that could alter the timing relationships for the clock
-- edges. If other I2C devices follow the spec then SDA should be stable
-- prior to the rising edge of SCL anyway. (Excluding noise of course)
----------------------------------------------------------------------------
----------------------------------------------------------------------------
-- Assertion that reports the SCL inertial delay
----------------------------------------------------------------------------
ASSERT (FALSE) REPORT "axi_iic configured for SCL inertial delay of "
& integer'image(SCL_INERTIAL_DELAY) & " clocks."
SEVERITY NOTE;
----------------------------------------------------------------------------
-- Instantiating component debounce
----------------------------------------------------------------------------
SCL_DEBOUNCE : entity axi_iic_v2_0.debounce
generic map (
C_INERTIAL_DELAY => SCL_INERTIAL_DELAY,
C_DEFAULT => '1')
port map (
Sysclk => Sysclk,
Rst => Rst,
Stable => '1',
Unstable_n => scl_unstable_n,
Noisy => Scl_noisy,
Clean => Scl_clean);
----------------------------------------------------------------------------
-- Assertion that reports the SDA inertial delay
----------------------------------------------------------------------------
ASSERT (FALSE) REPORT "axi_iic configured for SDA inertial delay of "
& integer'image(SDA_INERTIAL_DELAY) & " clocks."
SEVERITY NOTE;
----------------------------------------------------------------------------
-- Instantiating component debounce
----------------------------------------------------------------------------
SDA_DEBOUNCE : entity axi_iic_v2_0.debounce
generic map (
C_INERTIAL_DELAY => SDA_INERTIAL_DELAY,
C_DEFAULT => '1')
port map (
Sysclk => Sysclk,
Rst => Rst,
Stable => scl_unstable_n,
Unstable_n => open,
Noisy => Sda_noisy,
Clean => Sda_clean);
end architecture RTL;
| gpl-3.0 | 616a202295dd2c04b2800f35d2c5ee5c | 0.42013 | 5.381479 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_proc_common_pkg.vhd | 1 | 18,673 | -------------------------------------------------------------------------------
-- Processor Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_proc_common_pkg.vhd
-- Version: v1.21b
-- Description: This file contains the constants and functions used in the
-- processor common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
-- ALS 09/12/01 -- Created from opb_arb_pkg.vhd
--
-- ALS 09/21/01
-- ^^^^^^
-- Added pwr function. Replaced log2 function with one that works for XST.
-- ~~~~~~
--
-- ALS 12/07/01
-- ^^^^^^
-- Added Addr_bits function.
-- ~~~~~~
-- ALS 01/31/02
-- ^^^^^^
-- Added max2 function.
-- ~~~~~~
-- FLO 02/22/02
-- ^^^^^^
-- Extended input argument range of log2 function to 2^30. Also, added
-- a check that the argument does not exceed this value; a failure
-- assertion violation is generated if it does not.
-- ~~~~~~
-- FLO 08/31/06
-- ^^^^^^
-- Removed type TARGET_FAMILY_TYPE and functions Get_Reg_File_Area and
-- Get_RLOC_Name. These objects are not used. Further, the functions
-- produced misleading warnings (CR419886, CR419898).
-- ~~~~~~
-- FLO 05/25/07
-- ^^^^^^
-- -Reimplemented function pad_power2 to correct error when the input
-- argument is 1. (fixes CR 303469)
-- -Added function clog2(x), which returns the integer ceiling of the
-- base 2 logarithm of x. This function can be used in place of log2
-- when wishing to avoid the XST warning, "VHDL Assertion Statement
-- with non constant condition is ignored".
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-- DET 5/8/2009 v3_00_a for EDK L.SP2
-- ~~~~~~
-- - Per CR520627
-- - Added synthesis translate_off/on constructs to the log2 function
-- around the assertion statement. This removes a repetative XST Warning
-- in SRP files about a non-constant assertion check.
-- ^^^^^^
-- FL0 20/27/2010
-- ^^^^^^
-- Removed 42 TBD comment, again. (CR 568493)
-- ~~~~~~
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package cpu_xadc_wiz_0_0_proc_common_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type CHAR_TO_INT_TYPE is array (character) of integer;
-- type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-- Type SLV64_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 63);
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer;
function min2 (num1, num2 : integer) return integer;
function Addr_Bits(x,y : std_logic_vector) return integer;
function clog2(x : positive) return natural;
function pad_power2 ( in_num : integer ) return integer;
function pad_4 ( in_num : integer ) return integer;
function log2(x : natural) return integer;
function pwr(x: integer; y: integer) return integer;
function String_To_Int(S : string) return integer;
function itoa (int : integer) return string;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- the RESET_ACTIVE constant should denote the logic level of an active reset
constant RESET_ACTIVE : std_logic := '1';
-- table containing strings representing hex characters for conversion to
-- integers
constant STRHEX_TO_INT_TABLE : CHAR_TO_INT_TYPE :=
('0' => 0,
'1' => 1,
'2' => 2,
'3' => 3,
'4' => 4,
'5' => 5,
'6' => 6,
'7' => 7,
'8' => 8,
'9' => 9,
'A'|'a' => 10,
'B'|'b' => 11,
'C'|'c' => 12,
'D'|'d' => 13,
'E'|'e' => 14,
'F'|'f' => 15,
others => -1);
end cpu_xadc_wiz_0_0_proc_common_pkg;
package body cpu_xadc_wiz_0_0_proc_common_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function max2
--
-- This function returns the greater of two numbers.
-------------------------------------------------------------------------------
function max2 (num1, num2 : integer) return integer is
begin
if num1 >= num2 then
return num1;
else
return num2;
end if;
end function max2;
-------------------------------------------------------------------------------
-- Function min2
--
-- This function returns the lesser of two numbers.
-------------------------------------------------------------------------------
function min2 (num1, num2 : integer) return integer is
begin
if num1 <= num2 then
return num1;
else
return num2;
end if;
end function min2;
-------------------------------------------------------------------------------
-- Function Addr_bits
--
-- function to convert an address range (base address and an upper address)
-- into the number of upper address bits needed for decoding a device
-- select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits(x,y : std_logic_vector) return integer is
variable addr_xor : std_logic_vector(x'range);
variable count : integer := 0;
begin
assert x'length = y'length and (x'ascending xnor y'ascending)
report "Addr_Bits: arguments are not the same type"
severity ERROR;
addr_xor := x xor y;
for i in x'range
loop
if addr_xor(i) = '1' then return count;
end if;
count := count + 1;
end loop;
return x'length;
end Addr_Bits;
--------------------------------------------------------------------------------
-- Function clog2 - returns the integer ceiling of the base 2 logarithm of x,
-- i.e., the least integer greater than or equal to log2(x).
--------------------------------------------------------------------------------
function clog2(x : positive) return natural is
variable r : natural := 0;
variable rp : natural := 1; -- rp tracks the value 2**r
begin
while rp < x loop -- Termination condition T: x <= 2**r
-- Loop invariant L: 2**(r-1) < x
r := r + 1;
if rp > integer'high - rp then exit; end if; -- If doubling rp overflows
-- the integer range, the doubled value would exceed x, so safe to exit.
rp := rp + rp;
end loop;
-- L and T <-> 2**(r-1) < x <= 2**r <-> (r-1) < log2(x) <= r
return r; --
end clog2;
-------------------------------------------------------------------------------
-- Function pad_power2
--
-- This function returns the next power of 2 from the input number. If the
-- input number is a power of 2, this function returns the input number.
--
-- This function is used to round up the number of masters to the next power
-- of 2 if the number of masters is not already a power of 2.
--
-- Input argument 0, which is not a power of two, is accepted and returns 0.
-- Input arguments less than 0 are not allowed.
-------------------------------------------------------------------------------
--
function pad_power2 (in_num : integer ) return integer is
begin
if in_num = 0 then
return 0;
else
return 2**(clog2(in_num));
end if;
end pad_power2;
-------------------------------------------------------------------------------
-- Function pad_4
--
-- This function returns the next multiple of 4 from the input number. If the
-- input number is a multiple of 4, this function returns the input number.
--
-------------------------------------------------------------------------------
--
function pad_4 (in_num : integer ) return integer is
variable out_num : integer;
begin
out_num := (((in_num-1)/4) + 1)*4;
return out_num;
end pad_4;
-------------------------------------------------------------------------------
-- Function log2 -- returns number of bits needed to encode x choices
-- x = 0 returns 0
-- x = 1 returns 0
-- x = 2 returns 1
-- x = 4 returns 2, etc.
-------------------------------------------------------------------------------
--
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
-- Fix per CR520627 XST was ignoring this anyway and printing a
-- Warning in SRP file. This will get rid of the warning and not
-- impact simulation.
-- synthesis translate_off
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Function pwr -- x**y
-- negative numbers not allowed for y
-------------------------------------------------------------------------------
function pwr(x: integer; y: integer) return integer is
variable z : integer := 1;
begin
if y = 0 then return 1;
else
for i in 1 to y loop
z := z * x;
end loop;
return z;
end if;
end function pwr;
-------------------------------------------------------------------------------
-- Function itoa
--
-- The itoa function converts an integer to a text string.
-- This function is required since `image doesn't work in Synplicity
-- Valid input range is -9999 to 9999
-------------------------------------------------------------------------------
--
function itoa (int : integer) return string is
type table is array (0 to 9) of string (1 to 1);
constant LUT : table :=
("0", "1", "2", "3", "4", "5", "6", "7", "8", "9");
variable str1 : string(1 to 1);
variable str2 : string(1 to 2);
variable str3 : string(1 to 3);
variable str4 : string(1 to 4);
variable str5 : string(1 to 5);
variable abs_int : natural;
variable thousands_place : natural;
variable hundreds_place : natural;
variable tens_place : natural;
variable ones_place : natural;
variable sign : integer;
begin
abs_int := abs(int);
if abs_int > int then sign := -1;
else sign := 1;
end if;
thousands_place := abs_int/1000;
hundreds_place := (abs_int-thousands_place*1000)/100;
tens_place := (abs_int-thousands_place*1000-hundreds_place*100)/10;
ones_place :=
(abs_int-thousands_place*1000-hundreds_place*100-tens_place*10);
if sign>0 then
if thousands_place>0 then
str4 := LUT(thousands_place) & LUT(hundreds_place) & LUT(tens_place) &
LUT(ones_place);
return str4;
elsif hundreds_place>0 then
str3 := LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str3;
elsif tens_place>0 then
str2 := LUT(tens_place) & LUT(ones_place);
return str2;
else
str1 := LUT(ones_place);
return str1;
end if;
else
if thousands_place>0 then
str5 := "-" & LUT(thousands_place) & LUT(hundreds_place) &
LUT(tens_place) & LUT(ones_place);
return str5;
elsif hundreds_place>0 then
str4 := "-" & LUT(hundreds_place) & LUT(tens_place) & LUT(ones_place);
return str4;
elsif tens_place>0 then
str3 := "-" & LUT(tens_place) & LUT(ones_place);
return str3;
else
str2 := "-" & LUT(ones_place);
return str2;
end if;
end if;
end itoa;
-----------------------------------------------------------------------------
-- Function String_To_Int
--
-- Converts a string of hex character to an integer
-- accept negative numbers
-----------------------------------------------------------------------------
function String_To_Int(S : String) return Integer is
variable Result : integer := 0;
variable Temp : integer := S'Left;
variable Negative : integer := 1;
begin
for I in S'Left to S'Right loop
if (S(I) = '-') then
Temp := 0;
Negative := -1;
else
Temp := STRHEX_TO_INT_TABLE(S(I));
if (Temp = -1) then
assert false
report "Wrong value in String_To_Int conversion " & S(I)
severity error;
end if;
end if;
Result := Result * 16 + Temp;
end loop;
return (Negative * Result);
end String_To_Int;
end package body cpu_xadc_wiz_0_0_proc_common_pkg;
| gpl-3.0 | a797e3a69d88b0ce38f5afef0b773660 | 0.46918 | 4.608342 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_13/lab13_4/lab13_4.vhd | 1 | 739 | library ieee;
use ieee.std_logic_1164.all;
entity T_FF is
PORT ( T: in std_logic;
CLK: in std_logic;
RST: in std_logic;
PRST: in std_logic;
Q: out std_logic);
end T_FF;
Architecture Arch_T_FF of T_FF is
begin
FF:process(CLK,RST,PRST)
variable x:std_logic;
begin
if (RST='0') then
x:='0';
else
if (RST='1' and PRST='0') then
x:='1';
else
if (CLK='1' and CLK'EVENT ) then
if (T='1') then
x:= not x;
end if;
end if;
end if;
end if;
Q<=x;
end process FF;
end Arch_T_FF; | gpl-2.0 | f0fcbeb64cb3e495d96d4eb4dd7f8b21 | 0.415426 | 3.453271 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/sync_cntl.vhd | 1 | 57,373 | -------------------------------------------------------------------------------
-- sync_cntl.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- File : sync_cntl.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI bus sync logic
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.or_reduce;
library axi_lite_ipif_v3_0;
library lib_pkg_v1_0;
library axi_epc_v2_0;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
use axi_epc_v2_0.ld_arith_reg;
use lib_pkg_v1_0.lib_pkg.log2;
use lib_pkg_v1_0.lib_pkg.max2;
library unisim;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics --
-------------------------------------------------------------------------------
-- C_SPLB_NATIVE_DWIDTH - Data bus width of OPB bus.
-- C_NUM_PERIPHERALS - No of peripherals.
-- C_PRH_CLK_SUPPORT - Indication of whether the synchronous interface
-- operates on peripheral clock or on OPB clock
-- C_PRH(0:3)_ADDR_TSU - External device (0:3) address setup time with
-- respect to rising edge of address strobe
-- (for multiplexed address and data bus)
-- C_PRH(0:3)_ADDR_TH - External device (0:3) address hold time with
-- respect to rising edge of address strobe
-- (for multiplexed address and data bus)
-- C_PRH(0:3)_ADS_WIDTH - Minimum pulse width of address strobe
-- C_PRH(0:3)_RDY_WIDTH - Maximum wait period for external device ready
-- signal assertion
-- LOCAL_CLK_PERIOD_PS - The clock period of operational clock of
-- peripheral interface in picoseconds
-- MAX_PERIPHERALS - Maximum number of peripherals supported by the
-- external peripheral controller
-- ADDRCNT_WIDTH - Width of counter generating address suffix (low
-- order address bits) in case of data width matching
-- NO_PRH_SYNC - Indicates all devices are configured for
-- asynchronous interface
-- PRH_SYNC - Indicates if the devices are configured for
-- asynchronous or synchronous interface
-- NO_PRH_DWIDTH_MATCH - Indication that no device is employing data width
-- matching
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Bus2IP_Clk - OPB Clock
-- Bus2IP_Rst - OPB Reset
-- Local_Clk - Operational clock for peripheral interface
-- Local_Rst - Reset for peripheral interface
-- Bus2IP_BE - Byte enables from IPIC interface
-- Dev_id - The decoded identification vector for the currently
-- - selected device
-- Dev_in_access - Indicates if any of the synchronous peripheral device
-- is currently being accessed
-- Dev_fifo_access - Indicates if the current access is to a FIFO
-- within the external peripheral device
-- Dev_rnw - Read/write control indication from IPIC interface
-- Dev_bus_multiplex - Indicates if the currently selected device employs
-- multiplexed bus
-- Dev_dwidth_match - Indicates if the current device employs data
-- width matching
-- Dev_dbus_width - Indicates decoded value for the data bus width
-- IPIC_sync_req - Request from the IPIC interface for an access to be
-- generated for a synchronous peripheral
-- IP_sync_req_rst - Request reset to the IPIC control logic
-- IP_sync_ack - Acknowledgement to the IPIC control logic
-- IPIC_sync_ack_rst - Acknowledgement reset from the IPIC control logic
-- IP_sync_addrack - Address acknowledgement for synchronous access
-- IP_sync_errack - Transaction error indication for synchronous access
-- Sync_addr_cnt_ld - Load signal for the address suffix counter for
-- synchronous peripheral accesses
-- Sync_addr_cnt_ce - Enable for address suffix counter for synchronous
-- synchronous peripheral accesses
-- Sync_en - Indication to data steering logic to latch the
-- read data bus
-- Sync_ce - Indication of currently read bytes from the data
-- steering logic
-- Steer_index - Index for data steering
-- Dev_Rdy - Currently selected device ready indication
-- (Decoded from multiple PRH_RDY signal)
-- Sync_ADS - Address strobe for synchronous access
-- Sync_CS_n - Chip select signals for synchronous peripheral
-- devices
-- Sync_RNW - Read/Write control for synchronous access
-- Sync_Burst - Burst indication for synchronous access
-- Sync_addr_ph - Address phase indication for synchronous access
-- in case of multiplexed address and data bus
-- Sync_data_oe - Data bus output enable for synchronous access
-------------------------------------------------------------------------------
entity sync_cntl is
generic (
C_SPLB_NATIVE_DWIDTH : integer;
C_NUM_PERIPHERALS : integer;
C_PRH_CLK_SUPPORT : integer;
C_PRH0_ADDR_TSU : integer;
C_PRH1_ADDR_TSU : integer;
C_PRH2_ADDR_TSU : integer;
C_PRH3_ADDR_TSU : integer;
C_PRH0_ADDR_TH : integer;
C_PRH1_ADDR_TH : integer;
C_PRH2_ADDR_TH : integer;
C_PRH3_ADDR_TH : integer;
C_PRH0_ADS_WIDTH : integer;
C_PRH1_ADS_WIDTH : integer;
C_PRH2_ADS_WIDTH : integer;
C_PRH3_ADS_WIDTH : integer;
C_PRH0_RDY_WIDTH : integer;
C_PRH1_RDY_WIDTH : integer;
C_PRH2_RDY_WIDTH : integer;
C_PRH3_RDY_WIDTH : integer;
LOCAL_CLK_PERIOD_PS : integer;
MAX_PERIPHERALS : integer;
ADDRCNT_WIDTH : integer;
NO_PRH_SYNC : integer;
PRH_SYNC : std_logic_vector;
NO_PRH_DWIDTH_MATCH : integer
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
Local_Clk : in std_logic;
Local_Rst : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 -1);
Dev_id : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Dev_in_access : in std_logic;
Dev_fifo_access : in std_logic;
Dev_rnw : in std_logic;
Dev_bus_multiplex : in std_logic;
Dev_dwidth_match : in std_logic;
Dev_dbus_width : in std_logic_vector(0 to 2);
IPIC_sync_req : in std_logic;
IP_sync_req_rst : out std_logic;
IP_sync_Wrack : out std_logic;
IP_sync_Rdack : out std_logic;
IPIC_sync_ack_rst : in std_logic;
IP_sync_errack : out std_logic;
Sync_addr_cnt_ld : out std_logic;
Sync_addr_cnt_ce : out std_logic;
Sync_en : out std_logic;
Sync_ce : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8 -1);
Steer_index : in std_logic_vector(0 to ADDRCNT_WIDTH-1);
Dev_Rdy : in std_logic;
Sync_ADS : out std_logic;
Sync_CS_n : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Sync_RNW : out std_logic;
Sync_Burst : out std_logic;
Sync_addr_ph : out std_logic;
Sync_data_oe : out std_logic
);
end entity sync_cntl;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of sync_cntl is
attribute ASYNC_REG : string;
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- NAME: find_effective_max
-----------------------------------------------------------------------------
-- Description: Given an array and an std_logic_vector indicating if
-- the elements of the array corresponds to synchronous
-- access, returns the maximum of those array elements that
-- corresponds to synchronous access.
-----------------------------------------------------------------------------
function find_effective_max (array_size : integer;
sync_identify : std_logic_vector;
int_array : INTEGER_ARRAY_TYPE)
return integer is
variable temp : integer := 1;
begin
for i in 0 to (array_size-1) loop
if sync_identify(i) = '1' then
if int_array(i) >= temp then
temp := int_array(i);
end if;
end if;
end loop;
return temp;
end function find_effective_max;
-----------------------------------------------------------------------------
-- NAME: find_effective_cnt
-----------------------------------------------------------------------------
-- Description: Given a signal indicating if the current access is for
-- synchronous device and a value, returns the effective value
-- corresponding to the device access. The effective value is
-- the input value if the access corresponds to a synchronous
-- device else zero.
-----------------------------------------------------------------------------
function find_effective_cnt(sync_identify : std_logic;
value : integer)
return integer is
variable temp : integer := 0;
begin
if sync_identify = '1' then
temp := value;
else
temp := 0;
end if;
return temp;
end function find_effective_cnt;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant BYTE_SIZE: integer := 8;
constant ADS_ASSERT_CNT0: integer :=
(max2((C_PRH0_ADDR_TSU/LOCAL_CLK_PERIOD_PS),
(C_PRH0_ADS_WIDTH/LOCAL_CLK_PERIOD_PS)));
constant ADS_ASSERT_CNT1: integer :=
(max2((C_PRH1_ADDR_TSU/LOCAL_CLK_PERIOD_PS),
(C_PRH1_ADS_WIDTH/LOCAL_CLK_PERIOD_PS)));
constant ADS_ASSERT_CNT2: integer :=
(max2((C_PRH2_ADDR_TSU/LOCAL_CLK_PERIOD_PS),
(C_PRH2_ADS_WIDTH/LOCAL_CLK_PERIOD_PS)));
constant ADS_ASSERT_CNT3: integer :=
(max2((C_PRH3_ADDR_TSU/LOCAL_CLK_PERIOD_PS),
(C_PRH3_ADS_WIDTH/LOCAL_CLK_PERIOD_PS)));
constant ADS_ASSERT_CNT_WIDTH0: integer := max2(1,log2(ADS_ASSERT_CNT0+1));
constant ADS_ASSERT_CNT_WIDTH1: integer := max2(1,log2(ADS_ASSERT_CNT1+1));
constant ADS_ASSERT_CNT_WIDTH2: integer := max2(1,log2(ADS_ASSERT_CNT2+1));
constant ADS_ASSERT_CNT_WIDTH3: integer := max2(1,log2(ADS_ASSERT_CNT3+1));
constant ADS_ASSERT_CNT_WIDTH_ARRAY:
INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( find_effective_cnt(PRH_SYNC(0),ADS_ASSERT_CNT_WIDTH0),
find_effective_cnt(PRH_SYNC(1),ADS_ASSERT_CNT_WIDTH1),
find_effective_cnt(PRH_SYNC(2),ADS_ASSERT_CNT_WIDTH2),
find_effective_cnt(PRH_SYNC(3),ADS_ASSERT_CNT_WIDTH3)
);
constant MAX_ADS_ASSERT_CNT_WIDTH: integer :=
find_effective_max(C_NUM_PERIPHERALS,
PRH_SYNC,
ADS_ASSERT_CNT_WIDTH_ARRAY);
type SLV_ADS_ASSERT_ARRAY_TYPE is array (natural range <>) of
std_logic_vector(0 to MAX_ADS_ASSERT_CNT_WIDTH-1);
constant ADS_ASSERT_DELAY_CNT_ARRAY:
SLV_ADS_ASSERT_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( conv_std_logic_vector(ADS_ASSERT_CNT0, MAX_ADS_ASSERT_CNT_WIDTH),
conv_std_logic_vector(ADS_ASSERT_CNT1, MAX_ADS_ASSERT_CNT_WIDTH),
conv_std_logic_vector(ADS_ASSERT_CNT2, MAX_ADS_ASSERT_CNT_WIDTH),
conv_std_logic_vector(ADS_ASSERT_CNT3, MAX_ADS_ASSERT_CNT_WIDTH)
);
constant DEV_ADS_ASSERT_ADDRCNT_RST_VAL:
std_logic_vector(0 to MAX_ADS_ASSERT_CNT_WIDTH-1) := (others => '0');
----------------------------------------------------------------------------
constant ADS_DEASSERT_CNT0: integer := (C_PRH0_ADDR_TH/LOCAL_CLK_PERIOD_PS)+1;
constant ADS_DEASSERT_CNT1: integer := (C_PRH1_ADDR_TH/LOCAL_CLK_PERIOD_PS)+1;
constant ADS_DEASSERT_CNT2: integer := (C_PRH2_ADDR_TH/LOCAL_CLK_PERIOD_PS)+1;
constant ADS_DEASSERT_CNT3: integer := (C_PRH3_ADDR_TH/LOCAL_CLK_PERIOD_PS)+1;
constant ADS_DEASSERT_CNT_WIDTH0: integer := max2(1,log2(ADS_DEASSERT_CNT0+1));
constant ADS_DEASSERT_CNT_WIDTH1: integer := max2(1,log2(ADS_DEASSERT_CNT1+1));
constant ADS_DEASSERT_CNT_WIDTH2: integer := max2(1,log2(ADS_DEASSERT_CNT2+1));
constant ADS_DEASSERT_CNT_WIDTH3: integer := max2(1,log2(ADS_DEASSERT_CNT3+1));
constant ADS_DEASSERT_CNT_WIDTH_ARRAY:
INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( find_effective_cnt(PRH_SYNC(0),ADS_DEASSERT_CNT_WIDTH0),
find_effective_cnt(PRH_SYNC(1),ADS_DEASSERT_CNT_WIDTH1),
find_effective_cnt(PRH_SYNC(2),ADS_DEASSERT_CNT_WIDTH2),
find_effective_cnt(PRH_SYNC(3),ADS_DEASSERT_CNT_WIDTH3)
);
constant MAX_ADS_DEASSERT_CNT_WIDTH: integer :=
find_effective_max(C_NUM_PERIPHERALS,
PRH_SYNC,
ADS_DEASSERT_CNT_WIDTH_ARRAY);
type SLV_ADS_DEASSERT_ARRAY_TYPE is array (natural range <>) of
std_logic_vector(0 to MAX_ADS_DEASSERT_CNT_WIDTH-1);
constant ADS_DEASSERT_DELAY_CNT_ARRAY:
SLV_ADS_DEASSERT_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( conv_std_logic_vector(ADS_DEASSERT_CNT0, MAX_ADS_DEASSERT_CNT_WIDTH),
conv_std_logic_vector(ADS_DEASSERT_CNT1, MAX_ADS_DEASSERT_CNT_WIDTH),
conv_std_logic_vector(ADS_DEASSERT_CNT2, MAX_ADS_DEASSERT_CNT_WIDTH),
conv_std_logic_vector(ADS_DEASSERT_CNT3, MAX_ADS_DEASSERT_CNT_WIDTH)
);
constant DEV_ADS_DEASSERT_ADDRCNT_RST_VAL:
std_logic_vector(0 to MAX_ADS_DEASSERT_CNT_WIDTH-1) := (others => '0');
------------------------------------------------------------------------------
constant RDY_CNT0: integer := (C_PRH0_RDY_WIDTH/LOCAL_CLK_PERIOD_PS)+1;
constant RDY_CNT1: integer := (C_PRH1_RDY_WIDTH/LOCAL_CLK_PERIOD_PS)+1;
constant RDY_CNT2: integer := (C_PRH2_RDY_WIDTH/LOCAL_CLK_PERIOD_PS)+1;
constant RDY_CNT3: integer := (C_PRH3_RDY_WIDTH/LOCAL_CLK_PERIOD_PS)+1;
constant RDY_CNT_WIDTH0: integer := max2(1,log2(RDY_CNT0+1));
constant RDY_CNT_WIDTH1: integer := max2(1,log2(RDY_CNT1+1));
constant RDY_CNT_WIDTH2: integer := max2(1,log2(RDY_CNT2+1));
constant RDY_CNT_WIDTH3: integer := max2(1,log2(RDY_CNT3+1));
constant RDY_CNT_WIDTH_ARRAY: INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( find_effective_cnt(PRH_SYNC(0),RDY_CNT_WIDTH0),
find_effective_cnt(PRH_SYNC(1),RDY_CNT_WIDTH1),
find_effective_cnt(PRH_SYNC(2),RDY_CNT_WIDTH2),
find_effective_cnt(PRH_SYNC(3),RDY_CNT_WIDTH3)
);
constant MAX_RDY_CNT_WIDTH: integer :=
find_effective_max(C_NUM_PERIPHERALS, PRH_SYNC, RDY_CNT_WIDTH_ARRAY);
type SLV_RDY_ARRAY_TYPE is array (natural range <>) of
std_logic_vector(0 to MAX_RDY_CNT_WIDTH-1);
constant RDY_DELAY_CNT_ARRAY : SLV_RDY_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( conv_std_logic_vector(RDY_CNT0, MAX_RDY_CNT_WIDTH),
conv_std_logic_vector(RDY_CNT1, MAX_RDY_CNT_WIDTH),
conv_std_logic_vector(RDY_CNT2, MAX_RDY_CNT_WIDTH),
conv_std_logic_vector(RDY_CNT3, MAX_RDY_CNT_WIDTH)
);
constant DEV_RDY_ADDRCNT_RST_VAL : std_logic_vector(0 to MAX_RDY_CNT_WIDTH-1)
:= (others => '0');
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SYNC_SM_TYPE is (
IDLE, -- common state
-----
ADS_ASSERT, -- used for muxed logic
ADS_DEASSERT, -- used for muxed logic
ADS_PRE_DATA_PHASE,--new addition to seperate muxed logic
ADS_DATA_PHASE, --new addition
ADS_TURN_AROUND, -- used for muxed logic
---
PRE_DATA_PHASE, -- used for non-muxed logic
DATA_PHASE, -- used for non-muxed logic
---
ACK_GEN, -- common state
ERRACK_GEN, -- common state
TURN_AROUND -- common state
);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal state_ns : SYNC_SM_TYPE := IDLE;
signal state_cs : SYNC_SM_TYPE;
signal sync_ads_i : std_logic:='0';
signal sync_cs_i : std_logic:='0';
signal sync_cs_n_i : std_logic_vector(0 to C_NUM_PERIPHERALS-1) :=
(others => '0');
signal sync_burst_en : std_logic:='0';
signal sync_burst_i : std_logic:='0';
signal sync_en_i : std_logic:='0';
signal sync_wr : std_logic:='0';
signal next_addr_ph : std_logic:='0';
signal next_pre_data_ph : std_logic:='0';
signal next_data_ph : std_logic:='0';
signal sync_data_oe_i : std_logic:='0';
signal sync_start : std_logic:='0';
signal sync_cycle_bit_rst :std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1):=
(others => '0');
signal sync_cycle_bit :std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1):=
(others => '0');
signal sync_cycle_en : std_logic:='0';
signal sync_cycle : std_logic:='0';
signal ack : std_logic:='0';
signal sync_ack : std_logic:='0';
signal ip_sync_ack_i : std_logic:='0';
signal local_sync_ack : std_logic:='0';
signal local_sync_ack_rst : std_logic:='0';
signal local_sync_ack_d1 : std_logic:='0';
signal local_sync_ack_d2 : std_logic:='0';
signal local_sync_ack_d3 : std_logic:='0';
signal errack : std_logic:='0';
signal sync_errack : std_logic:='0';
signal local_sync_errack : std_logic:='0';
signal local_sync_errack_rst : std_logic:='0';
signal local_sync_errack_d1 : std_logic:='0';
signal local_sync_errack_d2 : std_logic:='0';
signal local_sync_errack_d3 : std_logic:='0';
signal dev_rdy_addrcnt_ld : std_logic:='0';
signal dev_rdy_addrcnt_ce : std_logic:='0';
signal dev_rdy_addrcnt : std_logic_vector(0 to MAX_RDY_CNT_WIDTH-1) :=
(others => '0');
signal dev_rdy_ld_val : std_logic_vector(0 to MAX_RDY_CNT_WIDTH-1) :=
(others => '0');
signal dev_ads_assert_addrcnt_ld : std_logic:='0';
signal dev_ads_assert_addrcnt_ce : std_logic:='0';
signal dev_ads_assert_addrcnt :
std_logic_vector(0 to MAX_ADS_ASSERT_CNT_WIDTH-1) := (others => '0');
--conv_std_logic_vector(1,MAX_ADS_ASSERT_CNT_WIDTH);
signal dev_ads_assert_ld_val :
std_logic_vector(0 to MAX_ADS_ASSERT_CNT_WIDTH-1) := (others => '0');
constant DEV_ADS_ASSERT_ADDRCNT_ZERO:
std_logic_vector(0 to MAX_ADS_ASSERT_CNT_WIDTH-1) :=
conv_std_logic_vector(1,MAX_ADS_ASSERT_CNT_WIDTH);
constant DEV_ADS_DEASSERT_ADDRCNT_ZERO:
std_logic_vector(0 to MAX_ADS_DEASSERT_CNT_WIDTH-1) :=
conv_std_logic_vector(1,MAX_ADS_DEASSERT_CNT_WIDTH);
constant DEV_RDY_ADDRCNT_ZERO : std_logic_vector(0 to MAX_RDY_CNT_WIDTH-1)
:= conv_std_logic_vector(0,MAX_RDY_CNT_WIDTH);
signal dev_ads_deassert_addrcnt_ld : std_logic:='0';
signal dev_ads_deassert_addrcnt_ce : std_logic:='0';
signal dev_ads_deassert_addrcnt :
std_logic_vector(0 to MAX_ADS_DEASSERT_CNT_WIDTH-1) := (others => '0');
signal dev_ads_deassert_ld_val :
std_logic_vector(0 to MAX_ADS_DEASSERT_CNT_WIDTH-1) := (others => '0');
signal sig1: std_logic;
signal sig2: std_logic;
signal temp_1_rst: std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- NAME: NO_DEV_SYNC_GEN
-------------------------------------------------------------------------------
-- Description: All devices are configured as asynchronous devices
-------------------------------------------------------------------------------
NO_DEV_SYNC_GEN: if NO_PRH_SYNC = 1 generate
IP_sync_req_rst <= '1';
IP_sync_Wrack <= '0';
IP_sync_Rdack <= '0';
IP_sync_errack <= '0';
Sync_addr_cnt_ld <= '0';
Sync_addr_cnt_ce <= '0';
Sync_en <= '0';
Sync_ADS <= '0';
Sync_CS_n <= (others => '1');
Sync_RNW <= '1';
Sync_Burst <= '0';
Sync_addr_ph <= '0';
Sync_data_oe <= '0';
end generate NO_DEV_SYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: SOME_DEV_SYNC_GEN
-------------------------------------------------------------------------------
-- Description: Some devices are configured as synchronous devices
-------------------------------------------------------------------------------
SOME_DEV_SYNC_GEN: if NO_PRH_SYNC = 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of I_SYNC_DEV_RDY_CNT: label is "TRUE";
begin
-----------------------------------------------------------------------------
-- NAME: SYNC_SM_CMB_PROCESS
-----------------------------------------------------------------------------
-- Description: Combinational logic for state machine.
-----------------------------------------------------------------------------
SYNC_SM_CMB_PROCESS : process (state_cs, Dev_bus_multiplex,
Dev_dwidth_match, sync_cycle,
Dev_in_access, Dev_fifo_access,
IPIC_sync_req,
dev_ads_assert_addrcnt,
dev_ads_deassert_addrcnt,
Dev_Rdy, dev_rdy_addrcnt)
begin
state_ns <= IDLE;
sync_start <= '0'; -- Assigned when next state is IDLE
sync_en_i <= '0'; -- Assinged when current state is
-- DATA_PHASE and Rdy is asserted
ack <= '0'; -- Assigned when current state is
-- ACK_GEN or ERRACK_GEN
errack <= '0'; -- Assigned when current state is
-- ERRACK_GEN
sync_ads_i <= '0'; -- Assigned when next state is
-- ADS_ASSERT
next_addr_ph <= '0'; -- Assigned when next state is
-- ADS_ASSERT and ADS_DEASSERT
next_pre_data_ph <= '0'; -- Assigned when next state is
-- PRE_DATA_PHASE
sync_cs_i <= '0'; -- Assigned when next state is
next_data_ph <= '0'; -- DATA_PHASE
Sync_addr_cnt_ld <= '0'; -- Assigned when current state is
-- IDLE and next state is
-- ADS_ASSERT or DATA_PHASE
Sync_addr_cnt_ce <= '0'; -- Assigned when current state is
-- DATA_PHASE and device is ready
dev_rdy_addrcnt_ld <= '0'; -- Assigned when next state is
-- DATA_PHASE and not both current
-- state DATA_PHASE and device not
-- ready is true
dev_rdy_addrcnt_ce <= '0'; -- Assigned when the current state
-- state is DATA_PHASE and device
-- not ready
dev_ads_assert_addrcnt_ld <= '0'; -- Assigned when next state is
-- ADS_ASSERT and the current state
-- is not ADS_ASSERT
dev_ads_assert_addrcnt_ce <= '0'; -- Assigned when the current state
-- is next state is ADS_ASSERT and
-- current state is ADS_ASSERT
dev_ads_deassert_addrcnt_ld <= '0'; -- Assigned when next state is
-- ADS_DEASSERT and the current
-- state is not ADS_DEASSERT
dev_ads_deassert_addrcnt_ce <= '0'; -- Assigned when the next state
-- is ADS_DEASSERT and current
-- state is ADS_DEASSERT
case state_cs is
when IDLE =>
dev_ads_assert_addrcnt_ld <= '1';
dev_ads_deassert_addrcnt_ld <= '1';
Sync_addr_cnt_ld <= '1';
if (IPIC_sync_req = '1' and Dev_bus_multiplex = '1' and
Dev_in_access = '1')then
sync_cs_i <= '1'; -- added 6/26/2009
sync_ads_i <= '1';
next_addr_ph <= '1';
state_ns <= ADS_ASSERT;
elsif (IPIC_sync_req = '1' and Dev_bus_multiplex = '0' and
Dev_in_access = '1')then
next_pre_data_ph <= '1';
--sync_cs_i <= '1'; -- added 6/26/2009
dev_rdy_addrcnt_ld <= '1';
state_ns <= PRE_DATA_PHASE;
else
sync_start <= '1';
state_ns <= IDLE;
end if;
-------------------------------
--multiplexing mode FSM states - ADS_ASSERT,ADS_DEASSERT,ADS_PRE_DATA_PHASE and
------------------------------- ADS_DATA_PHASE
when ADS_ASSERT =>
sync_cs_i <= '1'; -- added 6/26/2009
sync_ads_i <= '1';
next_addr_ph <= '1';
dev_ads_assert_addrcnt_ce <= '1';
if (dev_ads_assert_addrcnt = DEV_ADS_ASSERT_ADDRCNT_ZERO) then
next_addr_ph <= '1';
dev_ads_assert_addrcnt_ce <= '0';
sync_ads_i <= '0'; -- added on 19th June, 09
state_ns <= ADS_DEASSERT;
else
dev_ads_assert_addrcnt_ce <= '1';
state_ns <= ADS_ASSERT;
end if;
when ADS_DEASSERT =>
sync_cs_i <= '1'; -- added 6/26/2009
if (dev_ads_deassert_addrcnt = DEV_ADS_DEASSERT_ADDRCNT_ZERO) then
next_pre_data_ph <= '1';
dev_rdy_addrcnt_ld <= '1';
sync_cs_i <= '0'; -- added 7/15/2009
state_ns <= ADS_PRE_DATA_PHASE; --PRE_DATA_PHASE;
else
dev_ads_deassert_addrcnt_ce <= '1';
next_addr_ph <= '1';
state_ns <= ADS_DEASSERT;
end if;
when ADS_PRE_DATA_PHASE =>
next_data_ph <= '1';
sync_cs_i <= '1';
state_ns <= ADS_DATA_PHASE;
when ADS_DATA_PHASE =>
sync_cs_i <= '1';
if (Dev_Rdy = '0') then -- Device not ready
sync_en_i <= '0';
dev_rdy_addrcnt_ce <= '1';
if (dev_rdy_addrcnt = DEV_RDY_ADDRCNT_ZERO) then
state_ns <= ERRACK_GEN;
else
sync_cs_i <= '1';
next_data_ph <= '1';
state_ns <= ADS_DATA_PHASE;
end if;
else -- Device ready
sync_en_i <= '1';
Sync_addr_cnt_ce <= '1';
if (Dev_dwidth_match = '1' and sync_cycle = '1') then
if (Dev_bus_multiplex = '1' and Dev_fifo_access = '0') then
sync_cs_i <= '0';
state_ns <= ADS_TURN_AROUND;
else
dev_rdy_addrcnt_ld <= '1';
sync_cs_i <= '1';
next_data_ph <= '1';
state_ns <= ADS_DATA_PHASE;
end if;
else
state_ns <= ACK_GEN;
end if;
end if;
when ADS_TURN_AROUND =>
dev_ads_assert_addrcnt_ld <= '1';
dev_ads_deassert_addrcnt_ld <= '1';
sync_cs_i <= '1';
sync_ads_i <= '1';
next_addr_ph <= '1';
state_ns <= ADS_ASSERT;
-------------------------------
--Non-multiplexing mode FSM states-PRE_DATA_PHASE,DATA_PHASE,ADS_TURN_AROUND,
-------------------------------
when PRE_DATA_PHASE =>
sync_cs_i <= '1';
next_data_ph <= '1';
state_ns <= DATA_PHASE;
when DATA_PHASE =>
-- Master abort
if (Dev_Rdy = '0') then -- Device not ready
sync_en_i <= '0';
dev_rdy_addrcnt_ce <= '1';
if (dev_rdy_addrcnt = DEV_RDY_ADDRCNT_ZERO) then
state_ns <= ERRACK_GEN;
else
sync_cs_i <= '1';
next_data_ph <= '1';
state_ns <= DATA_PHASE;
end if;
else -- Device ready
sync_en_i <= '1';
Sync_addr_cnt_ce <= '1';
if (Dev_dwidth_match = '1' and sync_cycle = '1') then
--if (Dev_bus_multiplex = '1' and Dev_fifo_access = '0') then
-- state_ns <= ADS_TURN_AROUND;
--else
dev_rdy_addrcnt_ld <= '1';
sync_cs_i <= '1';
next_data_ph <= '1';
state_ns <= DATA_PHASE;
--end if;
else
state_ns <= ACK_GEN;
end if;
end if;
-- common to multiplexing and non-multiplexing states
when ACK_GEN =>
ack <= '1';
state_ns <= TURN_AROUND;
when ERRACK_GEN =>
ack <= '1';
errack <= '1';
state_ns <= TURN_AROUND;
when TURN_AROUND =>
sync_start <= '1';
state_ns <= IDLE;
when others =>
end case;
end process SYNC_SM_CMB_PROCESS;
--------------------------------------------
Sync_en <= sync_en_i;
sync_wr <= (not Dev_rnw) and next_data_ph;
sync_data_oe_i <= Dev_in_access and ( next_addr_ph or
(not Dev_rnw and next_pre_data_ph) or
(not Dev_rnw and next_data_ph)
);
-----------------------------------------------------------------------------
-- NAME: SYNC_CS_SEL_PROCESS
-----------------------------------------------------------------------------
-- Description: Drives an internal signal (SYNC_CS_N) from the synchronous
-- control logic to be used as the chip select for the external
-- peripheral device
-----------------------------------------------------------------------------
SYNC_CS_SEL_PROCESS: process (Dev_id,sync_cs_i) is
begin
sync_cs_n_i <= (others => '1');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Dev_id(i) = '1') then
sync_cs_n_i(i) <= not sync_cs_i;
end if;
end loop;
end process SYNC_CS_SEL_PROCESS;
-----------------------------------------------------------------------------
-- NAME: SYNC_SM_REG_PROCESS
-----------------------------------------------------------------------------
-- Description: Register state machine outputs
-----------------------------------------------------------------------------
SYNC_SM_REG_PROCESS : process (Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1') then
if (Local_Rst = '1') then
Sync_ADS <= '0';
Sync_Burst <= '0';
Sync_CS_n <= (others => '1');
Sync_RNW <= '1';
Sync_addr_ph <= '0';
Sync_data_oe <= '0';
state_cs <= IDLE;
else
Sync_ADS <= sync_ads_i;
Sync_CS_n <= sync_cs_n_i;
Sync_RNW <= not sync_wr;
Sync_Burst <= sync_burst_i;
Sync_addr_ph <= next_addr_ph;
Sync_data_oe <= sync_data_oe_i;
state_cs <= state_ns;
end if;
end if;
end process SYNC_SM_REG_PROCESS;
-----------------------------------------------------------------------------
-- NAME: NO_PRH_DWIDTH_MATCH_GEN
-----------------------------------------------------------------------------
-- Description: If no device employs data width matching, then generate
-- default values for SYNC_CYCLE and SYNC_BURST_I signals
-----------------------------------------------------------------------------
NO_PRH_DWIDTH_MATCH_GEN : if NO_PRH_DWIDTH_MATCH = 1 generate
sync_cycle <= '0';
sync_burst_i <= '0';
end generate NO_PRH_DWIDTH_MATCH_GEN;
-----------------------------------------------------------------------------
-- NAME: PRH_DWIDTH_MATCH_GEN
-----------------------------------------------------------------------------
-- Description: If any device employs data width matching, then generate
-- SYNC_CYCLE and SYNC_BURST_I signals
-----------------------------------------------------------------------------
PRH_DWIDTH_MATCH_GEN : if NO_PRH_DWIDTH_MATCH = 0 generate
---------------------------------------------------------------------------
-- NAME: SYNC_CYCLE_BIT_RST_GEN
---------------------------------------------------------------------------
-- Generate reset for synchronous cycle bit.
---------------------------------------------------------------------------
SYNC_CYCLE_BIT_RST_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/8-1 generate
sync_cycle_bit_rst(i) <= Local_Rst or Sync_ce(i);
end generate SYNC_CYCLE_BIT_RST_GEN;
---------------------------------------------------------------------------
-- NAME: SYNC_CYCLE_BIT_GEN
---------------------------------------------------------------------------
-- Description: Generate an indication for the byte lanes read
---------------------------------------------------------------------------
SYNC_CYCLE_BIT_GEN: for i in 0 to C_SPLB_NATIVE_DWIDTH/8-1 generate
-------------------------------------------------------------------------
-- NAME: SYNC_CYCLE_BIT_PROCESS
-------------------------------------------------------------------------
-- Description: Generate an indication for the byte lanes read
-------------------------------------------------------------------------
SYNC_CYCLE_BIT_PROCESS: process (Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1') then
if (sync_cycle_bit_rst(i) = '1' ) then
sync_cycle_bit(i) <= '0';
elsif (sync_start = '1') then
sync_cycle_bit(i) <= Bus2IP_BE(i);
end if;
end if;
end process SYNC_CYCLE_BIT_PROCESS;
end generate SYNC_CYCLE_BIT_GEN;
---------------------------------------------------------------------------
-- NAME: SYNC_CYCLE_EN_PROCESS
---------------------------------------------------------------------------
-- Description: Generate enable for sync cycle
-- Enable for sync cycle is generated when the next data
-- is to be flushed to the device. For the last access
-- sync cycle enable will remain zero
---------------------------------------------------------------------------
SYNC_CYCLE_EN_PROCESS: process(Dev_dbus_width, Steer_index,
sync_cycle_bit, sync_en_i)
variable next_access : integer;
variable next_to_next: integer;
variable cycle_on : std_logic;
variable next_cycle_on : std_logic;
begin
sync_cycle_en <= '0';
sync_burst_en <= '0';
case Dev_dbus_width is
when "001" =>
for i in 0 to C_SPLB_NATIVE_DWIDTH/BYTE_SIZE-1 loop
if steer_index = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
next_access := i+1;
next_to_next := i+2;
if (next_access < C_SPLB_NATIVE_DWIDTH/BYTE_SIZE) then
cycle_on := or_reduce(sync_cycle_bit(next_access to C_SPLB_NATIVE_DWIDTH/8-1));
else
cycle_on := '0';
end if;
if (next_to_next < C_SPLB_NATIVE_DWIDTH/BYTE_SIZE) then
next_cycle_on := or_reduce(sync_cycle_bit(next_to_next to C_SPLB_NATIVE_DWIDTH/8-1));
else
next_cycle_on := '0';
end if;
sync_cycle_en <= cycle_on;
sync_burst_en <= cycle_on and ((not sync_en_i) or
(sync_en_i and next_cycle_on));
end if;
end loop;
when "010" =>
for i in 0 to (C_SPLB_NATIVE_DWIDTH/BYTE_SIZE)/2-1 loop
if steer_index = conv_std_logic_vector(i, ADDRCNT_WIDTH) then
next_access := (i+1) * 2;
next_to_next := (i+2) * 2;
if (next_access < C_SPLB_NATIVE_DWIDTH/BYTE_SIZE) then
cycle_on := sync_cycle_bit(next_access) or
sync_cycle_bit(next_access+1);
else
cycle_on := '0';
end if;
-- coverage off
if (next_to_next < C_SPLB_NATIVE_DWIDTH/BYTE_SIZE) then
next_cycle_on := sync_cycle_bit(next_to_next) or
sync_cycle_bit(next_to_next+1);
else
-- coverage on
next_cycle_on := '0';
-- coverage off
end if;
-- coverage on
sync_cycle_en <= cycle_on;
sync_burst_en <= cycle_on and ((not sync_en_i) or
(sync_en_i and next_cycle_on));
end if;
end loop;
when others =>
sync_cycle_en <= '0';
sync_burst_en <= '0';
end case;
end process SYNC_CYCLE_EN_PROCESS;
sync_cycle <= sync_cycle_en and Dev_dwidth_match;
sync_burst_i <= sync_burst_en and next_data_ph and Dev_dwidth_match and
(not Dev_bus_multiplex or Dev_fifo_access);
end generate PRH_DWIDTH_MATCH_GEN;
-----------------------------------------------------------------------------
-- NAME: SYNC_ACK_NO_PRH_CLK_GEN
-----------------------------------------------------------------------------
-- Description: Generate data ack and error ack when the synchronous logic
-- operates on OPB Clock. IP_SYNC_REQ_RST will not be used
-- by ipic_if_decode logic. Drive it to default value
-----------------------------------------------------------------------------
SYNC_ACK_NO_PRH_CLK_GEN: if C_PRH_CLK_SUPPORT = 0 generate
IP_sync_req_rst <= '1';
---------------------------------------------------------------------------
-- NAME: SYNC_ACK_NO_PRH_CLK_PROCESS
---------------------------------------------------------------------------
-- Description: Generate data ack and error ack when the synchronous logic
-- operates on OPB Clock.
---------------------------------------------------------------------------
SYNC_ACK_NO_PRH_CLK_PROCESS : process (Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1') then
if (Local_Rst = '1') then
ip_sync_ack_i <= '0';
IP_sync_errack <= '0';
else
ip_sync_ack_i <= ack;
IP_sync_errack <= errack;
end if;
end if;
end process SYNC_ACK_NO_PRH_CLK_PROCESS;
end generate SYNC_ACK_NO_PRH_CLK_GEN;
-----------------------------------------------------------------------------
-- NAME: SYNC_ACK_PRH_CLK_GEN
-----------------------------------------------------------------------------
-- Description: Generate data ack, error ack and reset for synchronos
-- request when the synchronous logic operates on peripheral
-- clock
-----------------------------------------------------------------------------
SYNC_ACK_PRH_CLK_GEN: if C_PRH_CLK_SUPPORT = 1 generate
attribute ASYNC_REG of REG_SYNC_ACK: label is "TRUE";
attribute ASYNC_REG of REG_SYNC_ERRACK: label is "TRUE";
begin
----------------------------------------------------------------------------
-- NAME: SYNC_REQ_RST_PROCESS
----------------------------------------------------------------------------
-- Description: Generate reset for synchronous request when the synchronous
-- control operates on peripheral clock.
----------------------------------------------------------------------------
SYNC_REQ_RST_PROCESS : process (state_cs)
begin
if (state_cs = ACK_GEN or state_cs = ERRACK_GEN) then
IP_sync_req_rst <= '1';
else
IP_sync_req_rst <= '0';
end if;
end process SYNC_REQ_RST_PROCESS;
---------------------------------------------------------------------------
-- NAME: SYNC_ACK_PRH_CLK_PROCESS
---------------------------------------------------------------------------
-- Description: Generate data ack and error ack when the synchronous logic
-- operates on peripheral clock.
---------------------------------------------------------------------------
SYNC_ACK_PRH_CLK_PROCESS : process (Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1') then
if (Local_Rst = '1') then
sync_ack <= '0';
sync_errack <= '0';
else
sync_ack <= ack;
sync_errack <= errack;
end if;
end if;
end process SYNC_ACK_PRH_CLK_PROCESS;
---------------------------------------------------------------------------
-- NAME: ACK_HOLD_GEN_PROCESS
---------------------------------------------------------------------------
-- Description: Latch in the synchronous data ack until it is reset by the
-- ipic_if_decode logic
---------------------------------------------------------------------------
temp_1_rst <= Bus2IP_Rst or IPIC_sync_ack_rst;
ACK_HOLD_GEN_PROCESS : process (Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(temp_1_rst = '1') then
sig1 <= '0';
elsif(sync_ack = '1') then
sig1 <= '1';
end if;
end if;
end process ACK_HOLD_GEN_PROCESS;
local_sync_ack <= sync_ack or ( sig1 and (not temp_1_rst));
--------------------------------------------------------------------------------
local_sync_ack_rst <= Bus2IP_Rst or IPIC_sync_ack_rst;
REG_SYNC_ACK: component FDRE
port map (
Q => local_sync_ack_d1,
C => Bus2IP_Clk,
CE => '1',
D => local_sync_ack,
R => local_sync_ack_rst
);
---------------------------------------------------------------------------
-- NAME: ERRACK_HOLD_GEN_PROCESS
---------------------------------------------------------------------------
-- Description: Latch in the synchronous error ack until it is reset by the
-- ipic_if_decode logic
---------------------------------------------------------------------------
ERRACK_HOLD_GEN_PROCESS : process (Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(temp_1_rst = '1') then
sig2 <= '0';
elsif(sync_errack = '1') then
sig2 <= '1';
end if;
end if;
end process ERRACK_HOLD_GEN_PROCESS;
local_sync_errack <= sync_errack or (sig2 and (not temp_1_rst));
--------------------------------------------------------------------------------
REG_SYNC_ERRACK: component FDRE
port map (
Q => local_sync_errack_d1,
C => Bus2IP_Clk,
CE => '1',
D => local_sync_errack,
R => local_sync_ack_rst
);
---------------------------------------------------------------------------
-- NAME: DOUBLE_SYNC_PROCESS
---------------------------------------------------------------------------
-- Description: Double synchronize data ack and error ack
---------------------------------------------------------------------------
DOUBLE_SYNC_PROCESS: process(Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if (local_sync_ack_rst = '1') then
local_sync_ack_d2 <= '0';
local_sync_ack_d3 <= '0';
local_sync_errack_d2 <= '0';
local_sync_errack_d3 <= '0';
else
local_sync_ack_d2 <= local_sync_ack_d1;
local_sync_ack_d3 <= local_sync_ack_d2;
local_sync_errack_d2 <= local_sync_errack_d1;
local_sync_errack_d3 <= local_sync_errack_d2;
end if;
end if;
end process DOUBLE_SYNC_PROCESS;
-- Generate a pulse for data ack and error ack when the synchronous
-- logic operates on peripheral clock
ip_sync_ack_i <= local_sync_ack_d2 and not local_sync_ack_d3;
IP_sync_errack <= local_sync_errack_d2 and not local_sync_errack_d3;
end generate SYNC_ACK_PRH_CLK_GEN;
-----------------------------------------------------------------------------
-- NAME: DEV_ADS_ASSERT_CNT_SEL_PROCESS
-----------------------------------------------------------------------------
-- Description: Selects the device ADS assert width count for the currently
-- selected device
-----------------------------------------------------------------------------
DEV_ADS_ASSERT_CNT_SEL_PROCESS: process (Dev_id) is
begin
dev_ads_assert_ld_val <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Dev_id(i) = '1') then
dev_ads_assert_ld_val <= ADS_ASSERT_DELAY_CNT_ARRAY(i);
end if;
end loop;
end process DEV_ADS_ASSERT_CNT_SEL_PROCESS;
-- Generate a counter for device ADS assert delay count
I_SYNC_DEV_ADS_ASSERT_CNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => false,
C_REG_WIDTH => MAX_ADS_ASSERT_CNT_WIDTH,
C_RESET_VALUE => DEV_ADS_ASSERT_ADDRCNT_RST_VAL,
C_LD_WIDTH => MAX_ADS_ASSERT_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Local_Clk,
RST => Local_Rst,
Q => dev_ads_assert_addrcnt,
LD => dev_ads_assert_ld_val,
AD => "1",
LOAD => dev_ads_assert_addrcnt_ld,
OP => dev_ads_assert_addrcnt_ce
);
-----------------------------------------------------------------------------
-- NAME: DEV_ADS_DEASSERT_CNT_SEL_PROCESS
-----------------------------------------------------------------------------
-- Description: Selects the device ADS deassert width count for the currently
-- selected device
-----------------------------------------------------------------------------
DEV_ADS_DEASSERT_CNT_SEL_PROCESS: process (Dev_id) is
begin
dev_ads_deassert_ld_val <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Dev_id(i) = '1') then
dev_ads_deassert_ld_val <= ADS_DEASSERT_DELAY_CNT_ARRAY(i);
end if;
end loop;
end process DEV_ADS_DEASSERT_CNT_SEL_PROCESS;
-- Generate a counter for device ADS deassert delay count
I_SYNC_DEV_ADS_DEASSERT_CNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => false,
C_REG_WIDTH => MAX_ADS_DEASSERT_CNT_WIDTH,
C_RESET_VALUE => DEV_ADS_DEASSERT_ADDRCNT_RST_VAL,
C_LD_WIDTH => MAX_ADS_DEASSERT_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Local_Clk,
RST => Local_Rst,
Q => dev_ads_deassert_addrcnt,
LD => dev_ads_deassert_ld_val,
AD => "1",
LOAD => dev_ads_deassert_addrcnt_ld,
OP => dev_ads_deassert_addrcnt_ce
);
-----------------------------------------------------------------------------
-- NAME: DEV_RDY_CNT_SEL_PROCESS
-----------------------------------------------------------------------------
-- Description: Selects the device ready width count for the currently
-- selected device
-----------------------------------------------------------------------------
DEV_RDY_CNT_SEL_PROCESS: process (Dev_id) is
begin
dev_rdy_ld_val <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Dev_id(i) = '1') then
dev_rdy_ld_val <= RDY_DELAY_CNT_ARRAY(i);
end if;
end loop;
end process DEV_RDY_CNT_SEL_PROCESS;
-- Generate a counter for device ready delay count
I_SYNC_DEV_RDY_CNT: entity axi_epc_v2_0.ld_arith_reg
generic map ( C_ADD_SUB_NOT => false,
C_REG_WIDTH => MAX_RDY_CNT_WIDTH,
C_RESET_VALUE => DEV_RDY_ADDRCNT_RST_VAL,
C_LD_WIDTH => MAX_RDY_CNT_WIDTH,
C_LD_OFFSET => 0,
C_AD_WIDTH => 1,
C_AD_OFFSET => 0
)
port map ( CK => Local_Clk,
RST => Local_Rst,
Q => dev_rdy_addrcnt,
LD => dev_rdy_ld_val,
AD => "1",
LOAD => dev_rdy_addrcnt_ld,
OP => dev_rdy_addrcnt_ce
);
------------------------------------------------------------------------------
-- Qualify the PLB read and write ack
IP_sync_Wrack <= ip_sync_ack_i and (not Dev_rnw);
IP_sync_Rdack <= (ip_sync_ack_i and Dev_rnw);
------------------------------------------------------------------------------
end generate SOME_DEV_SYNC_GEN;
------------------------------------------------------------------------------
end architecture imp;
------------------------------------------------------------------------------
| gpl-3.0 | 8406af7b7a4645f7c8216293a4395b3a | 0.443432 | 4.283485 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_sp/example_design/ram_16x1k_sp_prod.vhd | 1 | 10,186 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_sp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_sp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x1k_sp_prod;
ARCHITECTURE xilinx OF ram_16x1k_sp_prod IS
COMPONENT ram_16x1k_sp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x1k_sp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| bsd-3-clause | 884575874aa3d264b82cbb847f93b8df | 0.492931 | 3.795082 | false | false | false | false |
esar/hdmilight-v1 | fpga/ws2811Driver.vhd | 2 | 3,565 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ws2811Driver is
Port ( clk : in STD_LOGIC;
load : in STD_LOGIC;
datain : in STD_LOGIC_VECTOR (23 downto 0);
busy : out STD_LOGIC := '0';
dataout : out STD_LOGIC);
end ws2811Driver;
architecture Behavioral of ws2811Driver is
signal bitcount : std_logic_vector(4 downto 0);
signal subbitcount : std_logic_vector(4 downto 0);
--signal count : std_logic_vector(9 downto 0) := "1011111000";
signal countEnable : std_logic;
signal shiftData : std_logic_vector(23 downto 0);
signal shiftEnable : std_logic;
signal shiftOutput : std_logic;
signal nextOutput : std_logic;
begin
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
bitcount <= (others => '0');
subbitcount <= (others => '0');
elsif(countEnable = '1') then
subbitcount <= std_logic_vector(unsigned(subbitcount) + 1);
if(subbitcount = "10011") then
bitcount <= std_logic_vector(unsigned(bitcount) + 1);
subbitcount <= (others => '0');
end if;
end if;
end if;
end process;
--process(clk)
--begin
-- if(rising_edge(clk)) then
-- if(load = '1') then
-- count <= (others => '0');
-- elsif(countEnable = '1') then
-- count <= std_logic_vector(unsigned(count) + 1);
-- end if;
-- end if;
--end process;
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
shiftData <= datain;
elsif(shiftEnable = '1') then
shiftData <= shiftData(22 downto 0) & "0";
end if;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
dataout <= nextOutput;
end if;
end process;
process(clk)
begin
if(rising_edge(clk)) then
if(load = '1') then
busy <= '1';
elsif (bitcount = "10111" and subbitcount = "10001") then
busy <= '0';
end if;
end if;
end process;
-- freeze counter when it reaches 24 bytes (24*4 clocks)
countEnable <= '0' when bitcount = "10111" and subbitcount = "10011" else '1';
-- enable shift every 4 clocks
shiftEnable <= '1' when subbitcount = "10011" else '0';
shiftOutput <= shiftData(23);
-- over a 4 clock period:
-- for a 1 output 1 1 1 0
-- for a 0 output 1 0 0 0
nextOutput <= '1' when subbitcount(4 downto 2) = "000" else
'0' when subbitcount(4 downto 2) = "100" else
shiftOutput;
end Behavioral;
| gpl-2.0 | cbc1f547153aa64c834229e80b3871d4 | 0.638429 | 3.427885 | false | false | false | false |
peteut/nvc | test/elab/issue330.vhd | 2 | 2,531 | entity DUMMY is
generic(
BITS: integer := 1
);
port(
I: in bit_vector(BITS-1 downto 0);
O: out bit_vector(BITS-1 downto 0)
);
end DUMMY;
architecture MODEL of DUMMY is
begin
O <= I;
end MODEL;
-- test_ng_comp.vhd
entity TEST_NG_COMP is
generic (
INFO_BITS : integer := 1
);
port (
I_INFO_0 : in bit_vector(INFO_BITS-1 downto 0);
I_INFO_1 : in bit_vector(INFO_BITS-1 downto 0);
O_INFO_0 : out bit_vector(INFO_BITS-1 downto 0);
O_INFO_1 : out bit_vector(INFO_BITS-1 downto 0)
);
end TEST_NG_COMP;
architecture MODEL of TEST_NG_COMP is
type INFO_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
end record;
type VEC_RANGE_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
INFO_0 : INFO_RANGE_TYPE;
INFO_1 : INFO_RANGE_TYPE;
end record;
function SET_VEC_RANGE return VEC_RANGE_TYPE is
variable d_pos : integer;
variable v : VEC_RANGE_TYPE;
procedure SET_INFO_RANGE(INFO_RANGE: inout INFO_RANGE_TYPE; BITS: in integer) is
begin
INFO_RANGE.DATA_LO := d_pos;
INFO_RANGE.DATA_HI := d_pos + BITS-1;
d_pos := d_pos + BITS;
end procedure;
begin
d_pos := 0;
v.DATA_LO := d_pos;
SET_INFO_RANGE(v.INFO_0, INFO_BITS);
SET_INFO_RANGE(v.INFO_1, INFO_BITS);
v.DATA_HI := d_pos - 1;
return v;
end function;
constant VEC_RANGE : VEC_RANGE_TYPE := SET_VEC_RANGE;
signal i_data : bit_vector(VEC_RANGE.DATA_HI downto VEC_RANGE.DATA_LO);
component DUMMY
generic(
BITS: integer := 1
);
port(
I: in bit_vector(BITS-1 downto 0);
O: out bit_vector(BITS-1 downto 0)
);
end component;
begin
I0: DUMMY generic map(BITS => INFO_BITS) port map(
I => I_INFO_0,
O => i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO)
);
I1: DUMMY generic map(BITS => INFO_BITS) port map(
I => I_INFO_1,
O => i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO)
);
O_INFO_0 <= i_data(VEC_RANGE.INFO_0.DATA_HI downto VEC_RANGE.INFO_0.DATA_LO);
O_INFO_1 <= i_data(VEC_RANGE.INFO_1.DATA_HI downto VEC_RANGE.INFO_1.DATA_LO);
end MODEL;
| gpl-3.0 | c3a99f1ba3829a88f53058ce35ca5a48 | 0.530225 | 3.244872 | false | true | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/controller.vhd | 1 | 7,280 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity CU is
port (
clk, ExternalReset,
carry, zero, sign, parity, borrow, overflow -- status register
: in STD_LOGIC;
IRout : in STD_LOGIC_VECTOR(15 downto 0); -- IR
reg0 : in STD_LOGIC_VECTOR(15 downto 0); -- Register(0)
ALUout_on_Databus, -- Data Bus
IRload, -- IR
ResetPC, Im, PCplus1, EnablePC, -- Address Unit
W_EN, -- register file
we, re, -- memory
itype
: out STD_LOGIC;
-- ALU's bits
alu_operation : out std_logic_vector(3 downto 0);
databus : inout std_logic_vector(15 downto 0)
);
end entity;
architecture CU_ARCH of CU is
type state is (reset, fetch, baseExe, halt, PCInc, shiftRighting, shiftLefting);
signal currentState : state := reset;
signal nextState : state;
constant add : STD_LOGIC_VECTOR(3 downto 0) := "0000";
constant sub : STD_LOGIC_VECTOR(3 downto 0) := "0001";
constant andD : STD_LOGIC_VECTOR(3 downto 0) := "0010";
constant orD : STD_LOGIC_VECTOR(3 downto 0) := "0011";
constant xorD : STD_LOGIC_VECTOR(3 downto 0) := "0100";
constant notD : STD_LOGIC_VECTOR(3 downto 0) := "0101";
constant mul : STD_LOGIC_VECTOR(3 downto 0) := "0110";
constant jmp : STD_LOGIC_VECTOR(3 downto 0) := "0111";
constant addi : STD_LOGIC_VECTOR(3 downto 0) := "1000";
constant srlD : STD_LOGIC_VECTOR(3 downto 0) := "1001";
constant andi : STD_LOGIC_VECTOR(3 downto 0) := "1010";
constant ori : STD_LOGIC_VECTOR(3 downto 0) := "1011";
constant sllD : STD_LOGIC_VECTOR(3 downto 0) := "1100";
constant store : STD_LOGIC_VECTOR(3 downto 0) := "1101";
constant load : STD_LOGIC_VECTOR(3 downto 0) := "1110";
constant brnz : STD_LOGIC_VECTOR(3 downto 0) := "1111";
---------- ALU Operations ----------------------
constant ALU_and : std_logic_vector (3 downto 0) := "0000";
constant ALU_or : std_logic_vector (3 downto 0) := "0001";
constant ALU_xor : std_logic_vector (3 downto 0) := "0010";
constant ALU_sl : std_logic_vector (3 downto 0) := "0100";
constant ALU_sr : std_logic_vector (3 downto 0) := "0101";
constant ALU_add : std_logic_vector (3 downto 0) := "0110";
constant ALU_mul : std_logic_vector (3 downto 0) := "1001";
constant ALU_sub : std_logic_vector (3 downto 0) := "0111";
constant ALU_not : std_logic_vector (3 downto 0) := "1000";
constant ALU_input2 : std_logic_vector (3 downto 0) := "1010";
signal Immediate : std_logic_vector(7 downto 0);
signal shiftTempSig : std_logic_vector(15 downto 0);
begin
Immediate <= IRout(7 downto 0);
-- state changer
process (clk, ExternalReset)
begin
if ExternalReset = '1' then
currentState <= reset;
elsif clk'event and clk = '1' then
currentState <= nextState;
end if;
end process;
-- control signals base on state
process (currentState)
variable shiftCounter : integer;
begin
-- set defaults
ALUout_on_Databus <= '0';
IRload <= '0';
ResetPC <= '0';
EnablePC <= '0';
PCplus1 <= '0';
itype <= '0';
ALUout_on_Databus <= '0';
W_EN <= '0';
we <= '0';
re <= '0';
case currentState is
when halt =>
nextState <= halt;
when reset =>
ResetPC <= '1';
EnablePC <= '1';
nextState <= fetch;
when fetch =>
re <= '1';
IRload <= '1';
nextState <= baseExe;
when baseExe =>
case IRout(15 downto 12) is
when add =>
alu_operation <= ALU_add;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when addi =>
alu_operation <= ALU_add;
PCplus1 <= '1';
EnablePC <= '1';
itype <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when sub =>
alu_operation <= ALU_sub;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when andD =>
alu_operation <= ALU_and;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when andi =>
alu_operation <= ALU_and;
PCplus1 <= '1';
EnablePC <= '1';
itype <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when orD =>
alu_operation <= ALU_or;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when ori =>
alu_operation <= ALU_or;
PCplus1 <= '1';
EnablePC <= '1';
itype <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when xorD =>
alu_operation <= ALU_xor;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when notD =>
alu_operation <= ALU_not;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when mul =>
alu_operation <= ALU_mul;
PCplus1 <= '1';
EnablePC <= '1';
ALUout_on_Databus <= '1';
W_EN <='1';
nextState <= fetch;
when jmp =>
nextState <= fetch;
Im <= '1';
EnablePC <= '1';
when brnz =>
alu_operation <= ALU_sub;
if (reg0 = "0000000000000000") then -- if reg(0) is 0
nextState <= fetch;
Im <= '1';
EnablePC <= '1';
else
nextState <= fetch;
EnablePC <= '1';
PCplus1 <= '1';
end if;
when store =>
Im <= '1';
we <= '1';
alu_operation <= ALU_input2;
ALUout_on_Databus <= '1';
nextState <= PCInc;
when load =>
Im <='1';
re <= '1';
W_EN <='1';
nextState <= PCInc;
when srlD =>
shiftCounter := to_integer(unsigned(Immediate));
alu_operation <= ALU_input2;
ALUout_on_Databus <= '1';
W_EN <='1';
shiftTempSig <= databus;
nextState <= shiftRighting;
when sllD =>
shiftCounter := to_integer(unsigned(Immediate));
alu_operation <= ALU_input2;
ALUout_on_Databus <= '1';
W_EN <='1';
shiftTempSig <= databus;
nextState <= shiftLefting;
when others =>
assert false report "X is out";
end case;
when PCInc =>
PCplus1 <= '1';
EnablePC <= '1';
nextState <= fetch;
when shiftRighting =>
case to_integer(unsigned(Immediate)) is
when 0 =>
ALUout_on_Databus <= '1';
W_EN <='1';
PCplus1 <= '1';
EnablePC <= '1';
nextState <= fetch;
when OTHERS =>
nextState <= shiftRighting;
end case;
shiftCounter := shiftCounter - 1;
when shiftLefting =>
case to_integer(unsigned(Immediate)) is
when 0 =>
ALUout_on_Databus <= '1';
W_EN <='1';
PCplus1 <= '1';
EnablePC <= '1';
nextState <= fetch;
when OTHERS =>
shiftTempSig <= shiftTempSig(14 downto 0) & '0';
nextState <= shiftLefting;
end case;
shiftCounter := shiftCounter - 1;
-- when comparator =>
when OTHERS =>
nextState <= reset;
end case;
end process;
end architecture;
| gpl-3.0 | 46c17aebce7ab496b8dd1891ff53d9a6 | 0.539011 | 3.140638 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/custom_pkg.vhd | 1 | 2,145 | --
-- Package File Template
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
-- To use any of the example code shown below, uncomment the lines and modify as necessary
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package custom_pkg is
type eight_bit is array (natural range <> ) of std_logic_vector( 7 downto 0);
type sixteen_bit is array (natural range <> ) of std_logic_vector(15 downto 0);
type thirtytwo_bit is array (natural range <> ) of std_logic_vector(31 downto 0);
type layer_type is (idle, weighted_sum_layer1, weighted_sum_layer2, activate_layer1, activate_layer2, reset_layer, predict_layer);
constant num_neurons : Integer;
-- type <new_type> is
-- record
-- <type_name> : std_logic_vector( 7 downto 0);
-- <type_name> : std_logic;
-- end record;
--
-- Declare constants
--
-- constant <constant_name> : time := <time_unit> ns;
-- constant <constant_name> : integer := <value;
--
-- Declare functions and procedure
--
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>);
--
end custom_pkg;
package body custom_pkg is
constant num_neurons : integer := 40;
---- Example 1
-- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- variable <variable_name> : <type_declaration>;
-- begin
-- <variable_name> := <signal_name> xor <signal_name>;
-- return <variable_name>;
-- end <function_name>;
---- Example 2
-- function <function_name> (signal <signal_name> : in <type_declaration>;
-- signal <signal_name> : in <type_declaration> ) return <type_declaration> is
-- begin
-- if (<signal_name> = '1') then
-- return <signal_name>;
-- else
-- return 'Z';
-- end if;
-- end <function_name>;
---- Procedure Example
-- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is
--
-- begin
--
-- end <procedure_name>;
end custom_pkg;
| bsd-2-clause | 16f843f68ee1df42ddf120c6a7cba93d | 0.649417 | 3.284839 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/epc_core.vhd | 1 | 45,561 |
-------------------------------------------------------------------------------
-- epc_core.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- File : epc_core.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : External Peripheral Controller for AXI epc core interface
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
library axi_epc_v2_0;
-------------------------------------------------------------------------------
-- Definition of Generics : --
-------------------------------------------------------------------------------
-- C_SPLB_CLK_PERIOD_PS - The clock period of PLB Clock in picoseconds
-- C_SPLB_AWIDTH - Address width of PLB BUS.
-- C_SPLB_DWIDTH - Data width of PLB BUS.
-- C_FAMILY - FPGA Family for which the external peripheral
-- controller is targeted
-- C_NUM_PERIPHERALS - Number of external devices connected to XPS EPC
-- C_PRH_MAX_AWIDTH - Maximum of address bus width of all peripherals
-- C_PRH_MAX_DWIDTH - Maximum of data bus width of all peripherals
-- C_PRH_MAX_ADWIDTH - Maximum of data bus width of all peripherals
-- and address bus width of peripherals employing
-- multiplexed address/data bus
-- C_PRH_CLK_SUPPORT - Indication of whether the synchronous interface
-- operates on peripheral clock or on XPSclock
-- C_PRH_BURST_SUPPORT - Indicates if the XPS EPC supports burst
-- C_PRH(0:3)_FIFO_ACCESS - Indicates if the support for accessing FIFO
-- like structure within external device is
-- required
-- C_PRH(0:3)_FIFO_OFFSET - Byte offset of FIFO from the base address
-- assigned to peripheral
-- C_PRH(0:3)_AWIDTH - External peripheral (0:3) address bus width
-- C_PRH(0:3)_DWIDTH - External peripheral (0:3) data bus width
-- C_PRH(0:3)_DWIDTH_MATCH - Indication of whether external peripheral (0:3)
-- supports multiple access cycle on the
-- peripheral interface for a single XPScycle
-- when the peripheral data bus width is less than
-- that of XPSbus data width
-- C_PRH(0:3)_SYNC - Indicates if the external device (0:3) uses
-- synchronous or asynchronous interface
-- C_PRH(0:3)_BUS_MULTIPLEX - Indicates if the external device (0:3) uses a
-- multiplexed or non-multiplexed device
-- C_PRH(0:3)_ADDR_TSU - External device (0:3) address setup time with
-- respect to rising edge of address strobe
-- (multiplexed address and data bus) or falling
-- edge of read/write signal (non-multiplexed
-- address/data bus)
-- C_PRH(0:3)_ADDR_TH - External device (0:3) address hold time with
-- respect to rising edge of address strobe
-- (multiplexed address and data bus) or rising
-- edge of read/write signal (non-multiplexed
-- address/data bus)
-- C_PRH(0:3)_ADS_WIDTH - Minimum pulse width of address strobe
-- C_PRH(0:3)_CSN_TSU - External device (0:3) chip select setup time
-- with respect to falling edge of read/write
-- signal
-- C_PRH(0:3)_CSN_TH - External device (0:3) chip select hold time with
-- respect to rising edge of read/write signal
-- C_PRH(0:3)_WRN_WIDTH - External device (0:3) write signal minimum
-- pulse width
-- C_PRH(0:3)_WR_CYCLE - External device (0:3) write cycle time
-- C_PRH(0:3)_DATA_TSU - External device (0:3) data bus setup with
-- respect to rising edge of write signal
-- C_PRH(0:3)_DATA_TH - External device (0:3) data bus hold with
-- respect to rising edge of write signal
-- C_PRH(0:3)_RDN_WIDTH - External device (0:3) read signal minimum
-- pulse width
-- C_PRH(0:3)_RD_CYCLE - External device (0:3) read cycle time
-- C_PRH(0:3)_DATA_TOUT - External device (0:3) data bus validity with
-- respect to falling edge of read signal
-- C_PRH(0:3)_DATA_TINV - External device (0:3) data bus high impedence
-- with respect to rising edge of read signal
-- C_PRH(0:3)_RDY_TOUT - External device (0:3) device ready validity from
-- falling edge of read/write signal
-- C_PRH(0:3)_RDY_WIDTH - Maximimum wait period for external device (0:3)
-- ready signal assertion
-- LOCAL_CLK_PERIOD_PS - The clock period of operating clock for
-- synchronous interface in picoseconds
-- MAX_PERIPHERALS - Maximum number of peripherals supported by the
-- external peripheral controller
-- PRH(0:3)_FIFO_ADDRESS - The address of external peripheral device FIFO
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
----------------------------------------
-- IPIC INTERFACE
----------------------------------------
-- Bus2IP_Clk - IPIC clock
-- Bus2IP_Rst - IPIC reset
-- Bus2IP_CS - IPIC chip select signals
-- Bus2IP_RdCE - IPIC read transaction chip enables
-- Bus2IP_WrCE - IPIC write transaction chip enables
-- Bus2IP_Addr - IPIC address
-- Bus2IP_RNW - IPIC read/write indication
-- Bus2IP_BE - IPIC byte enables
-- Bus2IP_Data - IPIC write data
-- IP2Bus_Data - Read data from IP to IPIC interface
-- IP2Bus_WrAck - Write Data acknowledgment from IP to IPIC interface
-- IP2Bus_RdAck - Read Data acknowledgment from IP to IPIC interface
-- IP2Bus_Error - Error indication from IP to IPIC interface
----------------------------------------
-- PERIPHERAL INTERFACE
----------------------------------------
-- Local_Clk - Operational clock for peripheral interface
-- Local_Rst - Reset for peripheral interface
-- PRH_CS_n - Peripheral interface chip select
-- PRH_Addr - Peripheral interface address bus
-- PRH_ADS - Peripheral interface address strobe
-- PRH_BE - Peripheral interface byte enables
-- PRH_RNW - Peripheral interface read/write control for
-- synchronous interface
-- PRH_Rd_n - Peripheral interface read strobe for asynchronous
-- interface
-- PRH_Wr_n - Peripheral interface write strobe for asynchronous
-- interface
-- PRH_Burst - Peripheral interface burst indication signal
-- PRH_Rdy - Peripheral interface device ready signal
-- PRH_Data_I - Peripheral interface input data bus
-- PRH_Data_O - Peripehral interface output data bus
-- PRH_Data_T - 3-state control for peripheral interface output data
-- bus
-------------------------------------------------------------------------------
entity epc_core is
generic (
C_SPLB_CLK_PERIOD_PS : integer;
LOCAL_CLK_PERIOD_PS : integer;
---------------- -------------------------
C_SPLB_AWIDTH : integer;
C_SPLB_DWIDTH : integer;
C_SPLB_NATIVE_DWIDTH : integer;
C_FAMILY : string;
---------------- -------------------------
C_NUM_PERIPHERALS : integer;
C_PRH_MAX_AWIDTH : integer;
C_PRH_MAX_DWIDTH : integer;
C_PRH_MAX_ADWIDTH : integer;
C_PRH_CLK_SUPPORT : integer;
C_PRH_BURST_SUPPORT : integer;
---------------- -------------------------
C_PRH0_FIFO_ACCESS : integer;
C_PRH0_AWIDTH : integer;
C_PRH0_DWIDTH : integer;
C_PRH0_DWIDTH_MATCH : integer;
C_PRH0_SYNC : integer;
C_PRH0_BUS_MULTIPLEX : integer;
C_PRH0_ADDR_TSU : integer;
C_PRH0_ADDR_TH : integer;
C_PRH0_ADS_WIDTH : integer;
C_PRH0_CSN_TSU : integer;
C_PRH0_CSN_TH : integer;
C_PRH0_WRN_WIDTH : integer;
C_PRH0_WR_CYCLE : integer;
C_PRH0_DATA_TSU : integer;
C_PRH0_DATA_TH : integer;
C_PRH0_RDN_WIDTH : integer;
C_PRH0_RD_CYCLE : integer;
C_PRH0_DATA_TOUT : integer;
C_PRH0_DATA_TINV : integer;
C_PRH0_RDY_TOUT : integer;
C_PRH0_RDY_WIDTH : integer;
---------------- -------------------------
C_PRH1_FIFO_ACCESS : integer;
C_PRH1_AWIDTH : integer;
C_PRH1_DWIDTH : integer;
C_PRH1_DWIDTH_MATCH : integer;
C_PRH1_SYNC : integer;
C_PRH1_BUS_MULTIPLEX : integer;
C_PRH1_ADDR_TSU : integer;
C_PRH1_ADDR_TH : integer;
C_PRH1_ADS_WIDTH : integer;
C_PRH1_CSN_TSU : integer;
C_PRH1_CSN_TH : integer;
C_PRH1_WRN_WIDTH : integer;
C_PRH1_WR_CYCLE : integer;
C_PRH1_DATA_TSU : integer;
C_PRH1_DATA_TH : integer;
C_PRH1_RDN_WIDTH : integer;
C_PRH1_RD_CYCLE : integer;
C_PRH1_DATA_TOUT : integer;
C_PRH1_DATA_TINV : integer;
C_PRH1_RDY_TOUT : integer;
C_PRH1_RDY_WIDTH : integer;
---------------- -------------------------
C_PRH2_FIFO_ACCESS : integer;
C_PRH2_AWIDTH : integer;
C_PRH2_DWIDTH : integer;
C_PRH2_DWIDTH_MATCH : integer;
C_PRH2_SYNC : integer;
C_PRH2_BUS_MULTIPLEX : integer;
C_PRH2_ADDR_TSU : integer;
C_PRH2_ADDR_TH : integer;
C_PRH2_ADS_WIDTH : integer;
C_PRH2_CSN_TSU : integer;
C_PRH2_CSN_TH : integer;
C_PRH2_WRN_WIDTH : integer;
C_PRH2_WR_CYCLE : integer;
C_PRH2_DATA_TSU : integer;
C_PRH2_DATA_TH : integer;
C_PRH2_RDN_WIDTH : integer;
C_PRH2_RD_CYCLE : integer;
C_PRH2_DATA_TOUT : integer;
C_PRH2_DATA_TINV : integer;
C_PRH2_RDY_TOUT : integer;
C_PRH2_RDY_WIDTH : integer;
---------------- -------------------------
C_PRH3_FIFO_ACCESS : integer;
C_PRH3_AWIDTH : integer;
C_PRH3_DWIDTH : integer;
C_PRH3_DWIDTH_MATCH : integer;
C_PRH3_SYNC : integer;
C_PRH3_BUS_MULTIPLEX : integer;
C_PRH3_ADDR_TSU : integer;
C_PRH3_ADDR_TH : integer;
C_PRH3_ADS_WIDTH : integer;
C_PRH3_CSN_TSU : integer;
C_PRH3_CSN_TH : integer;
C_PRH3_WRN_WIDTH : integer;
C_PRH3_WR_CYCLE : integer;
C_PRH3_DATA_TSU : integer;
C_PRH3_DATA_TH : integer;
C_PRH3_RDN_WIDTH : integer;
C_PRH3_RD_CYCLE : integer;
C_PRH3_DATA_TOUT : integer;
C_PRH3_DATA_TINV : integer;
C_PRH3_RDY_TOUT : integer;
C_PRH3_RDY_WIDTH : integer;
---------------- -------------------------
MAX_PERIPHERALS : integer;
PRH0_FIFO_ADDRESS : std_logic_vector;
PRH1_FIFO_ADDRESS : std_logic_vector;
PRH2_FIFO_ADDRESS : std_logic_vector;
PRH3_FIFO_ADDRESS : std_logic_vector
---------------- -------------------------
);
port (
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- IPIC interface
Bus2IP_CS : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Bus2IP_Addr : in std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
Bus2IP_RNW : in std_logic;
Bus2IP_BE : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
Bus2IP_Data : in std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
IP2Bus_Data : out std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH-1);
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
-- Clock and Reset for peripheral interface
Local_Clk : in std_logic;
Local_Rst : in std_logic;
-- Peripheral interface
PRH_CS_n : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
PRH_Addr : out std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
PRH_ADS : out std_logic;
PRH_BE : out std_logic_vector(0 to C_PRH_MAX_DWIDTH/8-1);
PRH_RNW : out std_logic;
PRH_Rd_n : out std_logic;
PRH_Wr_n : out std_logic;
PRH_Burst : out std_logic;
PRH_Rdy : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
PRH_Data_I : in std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1);
PRH_Data_O : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1);
PRH_Data_T : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1)
);
end entity epc_core;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of epc_core is
-------------------------------------------------------------------------------
-- Function Declaration
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- NAME: all_zeros
-----------------------------------------------------------------------------
-- Description: Given an array returns an integer value of '1' if all elements
-- of the array are zero. Returns '0' otherwise
-----------------------------------------------------------------------------
function all_zeros ( array_size : integer;
int_array : INTEGER_ARRAY_TYPE) return integer is
variable temp : integer := 1;
begin
for i in 0 to (array_size-1) loop
if int_array(i) = 1 then
temp := 0;
end if;
end loop;
return temp;
end function all_zeros;
-----------------------------------------------------------------------------
-- NAME: all_ones
-----------------------------------------------------------------------------
-- Description: Given an array returns an integer value of '1' if all elements
-- of the array are one. Returns '0' otherwise
-----------------------------------------------------------------------------
function all_ones ( array_size : integer;
int_array : INTEGER_ARRAY_TYPE) return integer is
variable temp : integer := 1;
begin
for i in 0 to (array_size-1) loop
if int_array(i) = 0 then
temp := 0;
end if;
end loop;
return temp;
end function all_ones;
-----------------------------------------------------------------------------
-- NAME: IntArray_to_StdLogicVec
-----------------------------------------------------------------------------
-- Description: Given an array returns an std_logic_vector, where each
-- element of the vector represents a value of '0' if the
-- corresponding integer in the array is 0. Else, the vector
-- value denotes a '1'
-----------------------------------------------------------------------------
function IntArray_to_StdLogicVec ( array_size : integer;
int_array : INTEGER_ARRAY_TYPE)
return std_logic_vector is
variable temp : std_logic_vector(0 to array_size-1);
begin
for i in 0 to (array_size - 1) loop
if int_array(i) = 0 then
temp(i) := '0';
else
temp(i) := '1';
end if;
end loop;
return temp;
end function IntArray_to_StdLogicVec;
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of
std_logic_vector(0 to C_SPLB_AWIDTH-1);
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ADDRCNT_WIDTH : integer := 2;
constant PRH_SYNC_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( C_PRH0_SYNC,
C_PRH1_SYNC,
C_PRH2_SYNC,
C_PRH3_SYNC
);
constant NO_PRH_SYNC : integer := all_zeros(C_NUM_PERIPHERALS, PRH_SYNC_ARRAY);
constant NO_PRH_ASYNC : integer := all_ones(C_NUM_PERIPHERALS, PRH_SYNC_ARRAY);
constant PRH_SYNC : std_logic_vector :=
IntArray_to_StdLogicVec(MAX_PERIPHERALS,
PRH_SYNC_ARRAY);
constant PRH_BUS_MULTIPLEX_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( C_PRH0_BUS_MULTIPLEX,
C_PRH1_BUS_MULTIPLEX,
C_PRH2_BUS_MULTIPLEX,
C_PRH3_BUS_MULTIPLEX
);
constant NO_PRH_BUS_MULTIPLEX : integer := all_zeros(C_NUM_PERIPHERALS,
PRH_BUS_MULTIPLEX_ARRAY);
constant PRH_BUS_MULTIPLEX : std_logic_vector :=
IntArray_to_StdLogicVec(MAX_PERIPHERALS,
PRH_BUS_MULTIPLEX_ARRAY);
constant PRH_DWIDTH_MATCH_ARRAY: INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( C_PRH0_DWIDTH_MATCH,
C_PRH1_DWIDTH_MATCH,
C_PRH2_DWIDTH_MATCH,
C_PRH3_DWIDTH_MATCH
);
constant NO_PRH_DWIDTH_MATCH : integer := all_zeros(C_NUM_PERIPHERALS,
PRH_DWIDTH_MATCH_ARRAY);
constant ALL_PRH_DWIDTH_MATCH : integer := all_ones(C_NUM_PERIPHERALS,
PRH_DWIDTH_MATCH_ARRAY);
constant PRH_DWIDTH_MATCH : std_logic_vector :=
IntArray_to_StdLogicVec(MAX_PERIPHERALS,
PRH_DWIDTH_MATCH_ARRAY);
constant PRH_FIFO_ACCESS_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( C_PRH0_FIFO_ACCESS,
C_PRH1_FIFO_ACCESS,
C_PRH2_FIFO_ACCESS,
C_PRH3_FIFO_ACCESS
);
constant PRH_FIFO_ADDRESS_ARRAY : SLV32_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( PRH0_FIFO_ADDRESS,
PRH1_FIFO_ADDRESS,
PRH2_FIFO_ADDRESS,
PRH3_FIFO_ADDRESS
);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal ipic_sync_req : std_logic;
signal ip_sync_req_rst : std_logic;
signal ipic_async_req : std_logic;
signal ip_sync_Wrack : std_logic;
signal ip_sync_Rdack : std_logic;
signal ipic_sync_ack_rst : std_logic;
signal ip_async_Wrack : std_logic;
signal ip_async_Rdack : std_logic;
signal ip_sync_error : std_logic;
signal ip_async_error : std_logic;
signal dev_id : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal dev_in_access : std_logic;
signal dev_sync_in_access : std_logic;
signal dev_async_in_access : std_logic;
signal dev_sync : std_logic;
signal dev_rnw : std_logic;
signal dev_bus_multiplex : std_logic;
signal dev_dwidth_match : std_logic;
signal dev_dbus_width : std_logic_vector(0 to 2);
signal async_addr_cnt_ld : std_logic;
signal async_addr_cnt_ce : std_logic;
signal sync_addr_cnt_ld : std_logic;
signal sync_addr_cnt_ce : std_logic;
signal async_en : std_logic;
signal async_ce : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
signal sync_en : std_logic;
signal sync_ce : std_logic_vector(0 to C_SPLB_NATIVE_DWIDTH/8-1);
signal addr_suffix : std_logic_vector(0 to ADDRCNT_WIDTH-1);
signal steer_index : std_logic_vector(0 to ADDRCNT_WIDTH-1);
signal dev_rdy : std_logic;
signal sync_ads : std_logic;
signal sync_cs_n : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal sync_rnw : std_logic;
signal sync_burst : std_logic;
signal sync_addr_ph : std_logic;
signal sync_data_oe : std_logic;
signal async_ads : std_logic;
signal async_cs_n : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
signal async_rd_n : std_logic;
signal async_wr_n : std_logic;
signal async_addr_ph : std_logic;
signal async_data_oe : std_logic;
signal addr_int : std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
signal data_int : std_logic_vector(0 to C_PRH_MAX_DWIDTH-1);
signal prh_data_in : std_logic_vector(0 to C_PRH_MAX_DWIDTH-1);
signal fifo_access : std_logic := '0';
signal dev_fifo_access : std_logic := '0';
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
IPIC_DECODE_I : entity axi_epc_v2_0.ipic_if_decode
generic map (
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_NUM_PERIPHERALS => C_NUM_PERIPHERALS,
C_PRH_CLK_SUPPORT => C_PRH_CLK_SUPPORT,
-----------------------------------------
C_PRH0_DWIDTH_MATCH => C_PRH0_DWIDTH_MATCH,
C_PRH1_DWIDTH_MATCH => C_PRH1_DWIDTH_MATCH,
C_PRH2_DWIDTH_MATCH => C_PRH2_DWIDTH_MATCH,
C_PRH3_DWIDTH_MATCH => C_PRH3_DWIDTH_MATCH,
-----------------------------------------
C_PRH0_DWIDTH => C_PRH0_DWIDTH,
C_PRH1_DWIDTH => C_PRH1_DWIDTH,
C_PRH2_DWIDTH => C_PRH2_DWIDTH,
C_PRH3_DWIDTH => C_PRH3_DWIDTH,
-----------------------------------------
MAX_PERIPHERALS => MAX_PERIPHERALS,
NO_PRH_SYNC => NO_PRH_SYNC,
NO_PRH_ASYNC => NO_PRH_ASYNC,
PRH_SYNC => PRH_SYNC,
-----------------------------------------
NO_PRH_BUS_MULTIPLEX => NO_PRH_BUS_MULTIPLEX,
PRH_BUS_MULTIPLEX => PRH_BUS_MULTIPLEX,
NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH,
PRH_DWIDTH_MATCH => PRH_DWIDTH_MATCH
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Rst => Bus2IP_Rst,
------------------------------------------
Local_Clk => Local_Clk,
Local_Rst => Local_Rst,
------------------------------------------
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RNW => Bus2IP_RNW,
------------------------------------------
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error,
------------------------------------------
FIFO_access => fifo_access,
------------------------------------------
Dev_id => dev_id,
Dev_fifo_access => dev_fifo_access,
Dev_in_access => dev_in_access,
Dev_sync_in_access => dev_sync_in_access,
Dev_async_in_access => dev_async_in_access,
Dev_sync => dev_sync,
Dev_rnw => dev_rnw,
Dev_bus_multiplex => dev_bus_multiplex,
Dev_dwidth_match => dev_dwidth_match,
Dev_dbus_width => dev_dbus_width,
------------------------------------------
IPIC_sync_req => ipic_sync_req,
IPIC_async_req => ipic_async_req,
IP_sync_req_rst => ip_sync_req_rst,
------------------------------------------
IP_sync_Wrack => ip_sync_Wrack,
IP_sync_Rdack => ip_sync_Rdack,
IPIC_sync_ack_rst => ipic_sync_ack_rst,
------------------------------------------
IP_async_Wrack => ip_async_Wrack,
IP_async_Rdack => ip_async_Rdack,
------------------------------------------
IP_sync_error => ip_sync_error,
IP_async_error => ip_async_error
);
SYNC_CNTL_I : entity axi_epc_v2_0.sync_cntl
generic map (
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_NUM_PERIPHERALS => C_NUM_PERIPHERALS,
C_PRH_CLK_SUPPORT => C_PRH_CLK_SUPPORT,
-----------------------------------------
C_PRH0_ADDR_TSU => C_PRH0_ADDR_TSU,
C_PRH1_ADDR_TSU => C_PRH1_ADDR_TSU,
C_PRH2_ADDR_TSU => C_PRH2_ADDR_TSU,
C_PRH3_ADDR_TSU => C_PRH3_ADDR_TSU,
-----------------------------------------
C_PRH0_ADDR_TH => C_PRH0_ADDR_TH,
C_PRH1_ADDR_TH => C_PRH1_ADDR_TH,
C_PRH2_ADDR_TH => C_PRH2_ADDR_TH,
C_PRH3_ADDR_TH => C_PRH3_ADDR_TH,
-----------------------------------------
C_PRH0_ADS_WIDTH => C_PRH0_ADS_WIDTH,
C_PRH1_ADS_WIDTH => C_PRH1_ADS_WIDTH,
C_PRH2_ADS_WIDTH => C_PRH2_ADS_WIDTH,
C_PRH3_ADS_WIDTH => C_PRH3_ADS_WIDTH,
-----------------------------------------
C_PRH0_RDY_WIDTH => C_PRH0_RDY_WIDTH,
C_PRH1_RDY_WIDTH => C_PRH1_RDY_WIDTH,
C_PRH2_RDY_WIDTH => C_PRH2_RDY_WIDTH,
C_PRH3_RDY_WIDTH => C_PRH3_RDY_WIDTH,
-----------------------------------------
LOCAL_CLK_PERIOD_PS => LOCAL_CLK_PERIOD_PS,
MAX_PERIPHERALS => MAX_PERIPHERALS,
ADDRCNT_WIDTH => ADDRCNT_WIDTH,
NO_PRH_SYNC => NO_PRH_SYNC,
PRH_SYNC => PRH_SYNC,
NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Rst => Bus2IP_Rst,
------------------------------------------
Local_Clk => Local_Clk,
Local_Rst => Local_Rst,
------------------------------------------
Bus2IP_BE => Bus2IP_BE,
------------------------------------------
Dev_id => dev_id,
Dev_fifo_access => dev_fifo_access,
Dev_in_access => dev_sync_in_access,
Dev_rnw => dev_rnw,
Dev_bus_multiplex => dev_bus_multiplex,
Dev_dwidth_match => dev_dwidth_match,
Dev_dbus_width => dev_dbus_width,
------------------------------------------
IPIC_sync_req => ipic_sync_req,
IP_sync_req_rst => ip_sync_req_rst,
------------------------------------------
IP_sync_Wrack => ip_sync_Wrack,
IP_sync_Rdack => ip_sync_Rdack,
IPIC_sync_ack_rst => ipic_sync_ack_rst,
------------------------------------------
IP_sync_errack => ip_sync_error,
------------------------------------------
Sync_addr_cnt_ld => sync_addr_cnt_ld,
Sync_addr_cnt_ce => sync_addr_cnt_ce,
------------------------------------------
Sync_en => sync_en,
Sync_ce => sync_ce,
------------------------------------------
Steer_index => steer_index,
------------------------------------------
Dev_Rdy => dev_rdy,
------------------------------------------
Sync_ADS => sync_ads,
Sync_CS_n => sync_cs_n,
Sync_RNW => sync_rnw,
Sync_Burst => sync_burst,
------------------------------------------
Sync_addr_ph => sync_addr_ph,
Sync_data_oe => sync_data_oe
);
ASYNC_CNTL_I : entity axi_epc_v2_0.async_cntl
generic map (
PRH_SYNC => PRH_SYNC,
NO_PRH_ASYNC => NO_PRH_ASYNC,
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
------------------------------------------
C_PRH0_ADDR_TSU => C_PRH0_ADDR_TSU,
C_PRH0_ADDR_TH => C_PRH0_ADDR_TH,
C_PRH0_WRN_WIDTH => C_PRH0_WRN_WIDTH,
C_PRH0_DATA_TSU => C_PRH0_DATA_TSU,
C_PRH0_RDN_WIDTH => C_PRH0_RDN_WIDTH,
C_PRH0_DATA_TOUT => C_PRH0_DATA_TOUT,
C_PRH0_DATA_TH => C_PRH0_DATA_TH,
C_PRH0_DATA_TINV => C_PRH0_DATA_TINV,
C_PRH0_RDY_TOUT => C_PRH0_RDY_TOUT,
C_PRH0_RDY_WIDTH => C_PRH0_RDY_WIDTH,
C_PRH0_ADS_WIDTH => C_PRH0_ADS_WIDTH,
C_PRH0_CSN_TSU => C_PRH0_CSN_TSU,
C_PRH0_CSN_TH => C_PRH0_CSN_TH,
C_PRH0_WR_CYCLE => C_PRH0_WR_CYCLE,
C_PRH0_RD_CYCLE => C_PRH0_RD_CYCLE,
------------------------------------------
C_PRH1_ADDR_TSU => C_PRH1_ADDR_TSU,
C_PRH1_ADDR_TH => C_PRH1_ADDR_TH,
C_PRH1_WRN_WIDTH => C_PRH1_WRN_WIDTH,
C_PRH1_DATA_TSU => C_PRH1_DATA_TSU,
C_PRH1_RDN_WIDTH => C_PRH1_RDN_WIDTH,
C_PRH1_DATA_TOUT => C_PRH1_DATA_TOUT,
C_PRH1_DATA_TH => C_PRH1_DATA_TH,
C_PRH1_DATA_TINV => C_PRH1_DATA_TINV,
C_PRH1_RDY_TOUT => C_PRH1_RDY_TOUT,
C_PRH1_RDY_WIDTH => C_PRH1_RDY_WIDTH,
C_PRH1_ADS_WIDTH => C_PRH1_ADS_WIDTH,
C_PRH1_CSN_TSU => C_PRH1_CSN_TSU,
C_PRH1_CSN_TH => C_PRH1_CSN_TH,
C_PRH1_WR_CYCLE => C_PRH1_WR_CYCLE,
C_PRH1_RD_CYCLE => C_PRH1_RD_CYCLE,
------------------------------------------
C_PRH2_ADDR_TSU => C_PRH2_ADDR_TSU,
C_PRH2_ADDR_TH => C_PRH2_ADDR_TH,
C_PRH2_WRN_WIDTH => C_PRH2_WRN_WIDTH,
C_PRH2_DATA_TSU => C_PRH2_DATA_TSU,
C_PRH2_RDN_WIDTH => C_PRH2_RDN_WIDTH,
C_PRH2_DATA_TOUT => C_PRH2_DATA_TOUT,
C_PRH2_DATA_TH => C_PRH2_DATA_TH,
C_PRH2_DATA_TINV => C_PRH2_DATA_TINV,
C_PRH2_RDY_TOUT => C_PRH2_RDY_TOUT,
C_PRH2_RDY_WIDTH => C_PRH2_RDY_WIDTH,
C_PRH2_ADS_WIDTH => C_PRH2_ADS_WIDTH,
C_PRH2_CSN_TSU => C_PRH2_CSN_TSU,
C_PRH2_CSN_TH => C_PRH2_CSN_TH,
C_PRH2_WR_CYCLE => C_PRH2_WR_CYCLE,
C_PRH2_RD_CYCLE => C_PRH2_RD_CYCLE,
------------------------------------------
C_PRH3_ADDR_TSU => C_PRH3_ADDR_TSU,
C_PRH3_ADDR_TH => C_PRH3_ADDR_TH,
C_PRH3_WRN_WIDTH => C_PRH3_WRN_WIDTH,
C_PRH3_DATA_TSU => C_PRH3_DATA_TSU,
C_PRH3_RDN_WIDTH => C_PRH3_RDN_WIDTH,
C_PRH3_DATA_TOUT => C_PRH3_DATA_TOUT,
C_PRH3_DATA_TH => C_PRH3_DATA_TH,
C_PRH3_DATA_TINV => C_PRH3_DATA_TINV,
C_PRH3_RDY_TOUT => C_PRH3_RDY_TOUT,
C_PRH3_RDY_WIDTH => C_PRH3_RDY_WIDTH,
C_PRH3_ADS_WIDTH => C_PRH3_ADS_WIDTH,
C_PRH3_CSN_TSU => C_PRH3_CSN_TSU,
C_PRH3_CSN_TH => C_PRH3_CSN_TH,
C_PRH3_WR_CYCLE => C_PRH3_WR_CYCLE,
C_PRH3_RD_CYCLE => C_PRH3_RD_CYCLE,
------------------------------------------
C_BUS_CLOCK_PERIOD_PS => C_SPLB_CLK_PERIOD_PS,
-- C_MAX_DWIDTH => C_PRH_MAX_DWIDTH,
C_NUM_PERIPHERALS => C_NUM_PERIPHERALS,
C_MAX_PERIPHERALS => MAX_PERIPHERALS
------------------------------------------
)
port map(
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
------------------------------------------
IPIC_Asynch_req => ipic_async_req,
Dev_FIFO_access => dev_fifo_access,
Dev_in_access => dev_async_in_access,
------------------------------------------
Asynch_prh_rdy => dev_rdy,
Dev_dwidth_match => dev_dwidth_match,
-- Dev_dbus_width => dev_dbus_width,
Dev_bus_multiplexed => dev_bus_multiplex,
Asynch_ce => async_ce,
------------------------------------------
Asynch_Wrack => ip_async_Wrack,
Asynch_Rdack => ip_async_Rdack,
Asynch_error => ip_async_error,
------------------------------------------
Asynch_Wr => async_wr_n,
Asynch_Rd => async_rd_n,
Asynch_en => async_en,
------------------------------------------
Asynch_addr_strobe => async_ads,
Asynch_addr_data_sel => async_addr_ph,
Asynch_data_sel => async_data_oe,
Asynch_chip_select => async_cs_n,
Asynch_addr_cnt_ld => async_addr_cnt_ld,
Asynch_addr_cnt_en => async_addr_cnt_ce,
------------------------------------------
Clk => Bus2IP_Clk,
Rst => Bus2IP_Rst
);
ADDRESS_GEN_I: entity axi_epc_v2_0.address_gen
generic map (
C_PRH_MAX_AWIDTH => C_PRH_MAX_AWIDTH,
NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH,
NO_PRH_SYNC => NO_PRH_SYNC,
NO_PRH_ASYNC => NO_PRH_ASYNC,
ADDRCNT_WIDTH => ADDRCNT_WIDTH
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Rst => Bus2IP_Rst,
------------------------------------------
Local_Clk => Local_Clk,
Local_Rst => Local_Rst,
------------------------------------------
Bus2IP_Addr => bus2ip_addr,
------------------------------------------
Dev_fifo_access => dev_fifo_access,
Dev_sync => dev_sync,
Dev_dwidth_match => dev_dwidth_match,
Dev_dbus_width => dev_dbus_width,
------------------------------------------
Async_addr_cnt_ld => async_addr_cnt_ld,
Async_addr_cnt_ce => async_addr_cnt_ce,
------------------------------------------
Sync_addr_cnt_ld => sync_addr_cnt_ld,
Sync_addr_cnt_ce => sync_addr_cnt_ce,
------------------------------------------
Addr_Int => addr_int,
Addr_suffix => addr_suffix
);
DATA_STEER_I: entity axi_epc_v2_0.data_steer
generic map (
C_SPLB_NATIVE_DWIDTH => C_SPLB_NATIVE_DWIDTH,
C_PRH_MAX_DWIDTH => C_PRH_MAX_DWIDTH,
ALL_PRH_DWIDTH_MATCH => ALL_PRH_DWIDTH_MATCH,
NO_PRH_DWIDTH_MATCH => NO_PRH_DWIDTH_MATCH,
NO_PRH_SYNC => NO_PRH_SYNC,
NO_PRH_ASYNC => NO_PRH_ASYNC,
ADDRCNT_WIDTH => ADDRCNT_WIDTH
)
port map (
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Rst => Bus2IP_Rst,
------------------------------------------
Local_Clk => Local_Clk,
Local_Rst => Local_Rst,
------------------------------------------
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_Data => Bus2IP_Data,
------------------------------------------
Dev_in_access => dev_in_access,
Dev_sync => dev_sync,
Dev_rnw => dev_rnw,
Dev_dwidth_match => dev_dwidth_match,
Dev_dbus_width => dev_dbus_width,
------------------------------------------
Addr_suffix => addr_suffix,
Steer_index => steer_index,
------------------------------------------
Async_en => async_en,
Async_ce => async_ce,
------------------------------------------
Sync_en => sync_en,
Sync_ce => sync_ce,
------------------------------------------
PRH_Data_In => prh_data_in,
PRH_BE => PRH_BE,
------------------------------------------
Data_Int => data_int,
IP2Bus_Data => IP2Bus_Data,
Dev_bus_multiplex => Dev_bus_multiplex
);
ACCESS_MUX_I : entity axi_epc_v2_0.access_mux
generic map (
C_NUM_PERIPHERALS => C_NUM_PERIPHERALS,
C_PRH_MAX_AWIDTH => C_PRH_MAX_AWIDTH,
C_PRH_MAX_DWIDTH => C_PRH_MAX_DWIDTH,
C_PRH_MAX_ADWIDTH => C_PRH_MAX_ADWIDTH,
------------------------------------------
C_PRH0_AWIDTH => C_PRH0_AWIDTH,
C_PRH1_AWIDTH => C_PRH1_AWIDTH,
C_PRH2_AWIDTH => C_PRH2_AWIDTH,
C_PRH3_AWIDTH => C_PRH3_AWIDTH,
------------------------------------------
C_PRH0_DWIDTH => C_PRH0_DWIDTH,
C_PRH1_DWIDTH => C_PRH1_DWIDTH,
C_PRH2_DWIDTH => C_PRH2_DWIDTH,
C_PRH3_DWIDTH => C_PRH3_DWIDTH,
------------------------------------------
C_PRH0_BUS_MULTIPLEX => C_PRH0_BUS_MULTIPLEX,
C_PRH1_BUS_MULTIPLEX => C_PRH1_BUS_MULTIPLEX,
C_PRH2_BUS_MULTIPLEX => C_PRH2_BUS_MULTIPLEX,
C_PRH3_BUS_MULTIPLEX => C_PRH3_BUS_MULTIPLEX,
------------------------------------------
MAX_PERIPHERALS => MAX_PERIPHERALS,
NO_PRH_SYNC => NO_PRH_SYNC,
NO_PRH_ASYNC => NO_PRH_ASYNC,
NO_PRH_BUS_MULTIPLEX => NO_PRH_BUS_MULTIPLEX
)
port map (
Local_Clk => Local_Clk,
Dev_id => dev_id,
------------------------------------------
Sync_CS_n => sync_cs_n,
Sync_ADS => sync_ads,
Sync_RNW => sync_rnw,
Sync_Burst => sync_burst,
Sync_addr_ph => sync_addr_ph,
Sync_data_oe => sync_data_oe,
------------------------------------------
Async_CS_n => async_cs_n,
Async_ADS => async_ads,
Async_Rd_n => async_rd_n,
Async_Wr_n => async_wr_n,
Async_addr_ph => async_addr_ph,
Async_data_oe => async_data_oe,
------------------------------------------
Addr_Int => addr_int,
Data_Int => data_int,
------------------------------------------
PRH_CS_n => PRH_CS_n,
PRH_ADS => PRH_ADS,
PRH_RNW => PRH_RNW,
PRH_Rd_n => PRH_Rd_n,
PRH_Wr_n => PRH_Wr_n,
PRH_Burst => PRH_Burst,
------------------------------------------
PRH_Rdy => PRH_Rdy,
Dev_Rdy => dev_rdy,
------------------------------------------
PRH_Addr => PRH_Addr,
PRH_Data_O => PRH_Data_O,
PRH_Data_T => PRH_Data_T
);
prh_data_in <= PRH_Data_I(0 to C_PRH_MAX_DWIDTH-1);
-------------------------------------------------------------------------------
-- NAME: DEV_FIFO_ACCESS_PROCESS
-------------------------------------------------------------------------------
-- Description: Generate an indication to the internal modules that the
-- current transaction is to a FIFO like structure
-------------------------------------------------------------------------------
DEV_FIFO_ACCESS_PROCESS: process (Bus2IP_CS, Bus2IP_Addr) is
begin
fifo_access <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Bus2IP_CS(i) = '1') then
if ( (PRH_FIFO_ACCESS_ARRAY(i) = 1) and
(Bus2IP_Addr = PRH_FIFO_ADDRESS_ARRAY(i)
(C_SPLB_AWIDTH-C_PRH_MAX_AWIDTH to C_SPLB_AWIDTH-1))
) then
fifo_access <= '1';
end if;
end if;
end loop;
end process DEV_FIFO_ACCESS_PROCESS;
end architecture imp;
--------------------------------end of file------------------------------------
| gpl-3.0 | be886feeb92744804554b4e849766547 | 0.443274 | 3.762263 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_rng.vhd | 1 | 3,908 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_rng.vhd
--
-- Description:
-- Used for generation of pseudo random numbers
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
ENTITY k7_sfifo_15x128_rng IS
GENERIC (
WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0));
END ENTITY;
ARCHITECTURE rg_arch OF k7_sfifo_15x128_rng IS
BEGIN
PROCESS (CLK,RESET)
VARIABLE rand_temp : STD_LOGIC_VECTOR(width-1 DOWNTO 0):=conv_std_logic_vector(SEED,width);
VARIABLE temp : STD_LOGIC := '0';
BEGIN
IF(RESET = '1') THEN
rand_temp := conv_std_logic_vector(SEED,width);
temp := '0';
ELSIF (CLK'event AND CLK = '1') THEN
IF (ENABLE = '1') THEN
temp := rand_temp(width-1) xnor rand_temp(width-3) xnor rand_temp(width-4) xnor rand_temp(width-5);
rand_temp(width-1 DOWNTO 1) := rand_temp(width-2 DOWNTO 0);
rand_temp(0) := temp;
END IF;
END IF;
RANDOM_NUM <= rand_temp;
END PROCESS;
END ARCHITECTURE;
| gpl-2.0 | 541fd45e2aa83b62a5e8b0b4e072df9d | 0.638434 | 4.303965 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp_sr.vhd | 1 | 4,647 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_sr.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-15
-- Last update: 2018-04-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display shift register
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-15 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity disp_sr is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_data : in std_logic_vector(255 downto 0);
disp_sclk : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic
);
end disp_sr;
architecture rtl of disp_sr is
signal trig : std_logic;
signal trig_arm : std_logic;
SIGNAL bit_sr : std_logic_vector(255 downto 0);
SIGNAL bit_cnt : std_logic_vector(8 downto 0);
signal finish : std_logic;
signal lat : std_logic;
signal sclk : std_logic;
signal sin : std_logic;
begin
--
-- __
-- disp_lat ____| |_____________ ______________________
-- _______ _____ _____ _ __ _____ _____ _______
-- disp_sin _______X_____X_____X_ __X_____X_____X_______
-- __ __ __ __ __
-- disp_sclk __________| |__| |_ |__| |__| |_______
--
-- Bit 255 254 .. 1 0
--
-- Start triggering
disp_trig:
process (rst_n, clk) is
begin
if (rst_n = '0') then
trig <= '0';
trig_arm <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
trig_arm <= '1';
elsif (tsc_1ppus = '1') then
trig_arm <= '0';
end if;
if (tsc_1ppus = '1' and trig_arm = '1') then
trig <= '1';
elsif (finish = '1') then
trig <= '0';
end if;
end if;
end process;
-- bit counter
disp_cnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_cnt <= (others => '0');
finish <= '0';
elsif (clk'event and clk = '1') then
if (trig = '0') then
bit_cnt <= (others => '0');
elsif (tsc_1ppus = '1' and trig = '1') then
bit_cnt <= bit_cnt + 1;
end if;
if (tsc_1ppus = '1' and bit_cnt = 511) then
finish <= '1';
else
finish <= '0';
end if;
end if;
end process;
-- Generate DISP control signals
disp_shift:
process (rst_n, clk) is
begin
if (rst_n = '0') then
bit_sr <= (others => '0');
bit_sr( 7 downto 0) <= x"1c";
bit_sr(15 downto 8) <= x"ce";
bit_sr(23 downto 16) <= x"bc";
lat <= '0';
sclk <= '0';
sin <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
bit_sr <= disp_data;
elsif (tsc_1ppus = '1' and bit_cnt(0) = '1') then
bit_sr <= bit_sr(bit_sr'left - 1 downto 0) & '0';
end if;
if (tsc_1ppus = '1') then
lat <= trig_arm;
sclk <= bit_cnt(0);
sin <= bit_sr(bit_sr'left);
end if;
end if;
end process;
-- Final output register
disp_olat: delay_sig generic map (1) port map (rst_n, clk, lat, disp_lat);
disp_osclk: delay_sig generic map (1) port map (rst_n, clk, sclk, disp_sclk);
disp_osin: delay_sig generic map (1) port map (rst_n, clk, sin, disp_sin);
end rtl;
| gpl-3.0 | 0badcbe1831de50143da7084da27428d | 0.375296 | 3.840496 | false | false | false | false |
tutkowskim/UART | uart_echo.vhd | 1 | 1,446 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity UART_ECHO is
port(
RX : in std_logic;
CLK : in std_logic;
RST : in std_logic;
TX : out std_logic;
CLK96OUT : out std_logic
);
end entity UART_ECHO;
architecture BEHAVORIAL of UART_ECHO is
signal CLKB,DR,DS,SS : std_logic;
signal DATAI,DATAO : std_logic_vector(7 downto 0);
signal counter : std_logic_vector(15 downto 0);
component uart_tx is
port(
SS : in std_logic;
DA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RST : in std_logic;
DS : out std_logic;
TX : out std_logic
);
end component UART_TX;
component uart_rx is
port(
RX : in std_logic;
CLK : in std_logic;
RST : in std_logic;
DR : out std_logic;
DA : out std_logic_vector(7 downto 0)
);
end component UART_RX;
begin
SLOWDOWN:process(CLK,RST)
begin
If (RST = '0') Then
counter <= X"0000";
Elsif rising_edge(CLK) Then
If counter = X"1400" then
counter <= X"0000";
Else
counter <= counter + 1;
End If;
End If;
If (DS = '1' and DR = '1') Then
DATAO <= DATAI;
end if;
If (DR = '0') Then
SS <= '0';
else
SS <= '1';
end if;
end process;
CLKB <= '1' when counter = X"1400" else
'0';
U0:uart_tx port map(SS,DATAO,CLKB,RST,DS,TX);
U1:uart_rx port map(RX,CLKB,RST,DR,DATAI);
CLK96OUT <= CLKB;
end architecture BEHAVORIAL;
| mit | 299ca1d6aed18364b58f1ba04988dc06 | 0.616874 | 2.591398 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/tx_Mem_Reader.vhd | 1 | 34,138 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity tx_Mem_Reader is
port (
-- DDR Read Interface
DDR_rdc_sof : OUT std_logic;
DDR_rdc_eof : OUT std_logic;
DDR_rdc_v : OUT std_logic;
DDR_rdc_FA : OUT std_logic;
DDR_rdc_Shift : OUT std_logic;
DDR_rdc_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : IN std_logic;
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : OUT std_logic;
DDR_FIFO_Empty : IN std_logic;
DDR_FIFO_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer read port
eb_FIFO_re : OUT std_logic;
eb_FIFO_empty : IN std_logic;
eb_FIFO_qout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register Read interface
Regs_RdAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Read Command interface
RdNumber : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
RdNumber_eq_One : IN std_logic;
RdNumber_eq_Two : IN std_logic;
StartAddr : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Shift_1st_QWord : IN std_logic;
FixedAddr : IN std_logic;
is_CplD : IN std_logic;
BAR_value : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
RdCmd_Req : IN std_logic;
RdCmd_Ack : OUT std_logic;
-- Output port of the memory buffer
mbuf_Din : OUT std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
mbuf_WE : OUT std_logic;
mbuf_Full : IN std_logic;
mbuf_aFull : IN std_logic;
mbuf_UserFull : IN std_logic; -- Test pin, intended for DDR flow interrupted
-- Common ports
Tx_TimeOut : OUT std_logic;
Tx_eb_TimeOut : OUT std_logic;
mReader_Rst_n : IN std_logic;
trn_clk : IN std_logic
);
end tx_Mem_Reader;
architecture Behavioral of tx_Mem_Reader is
type mReaderStates is ( St_mR_Idle -- Memory reader Idle
, St_mR_CmdLatch -- Capture the read command
, St_mR_Transfer -- Acknowlege the command request
, St_mR_DDR_A -- DDR access state A
-- , St_mR_DDR_B -- DDR access state B
, St_mR_DDR_C -- DDR access state C
, St_mR_Last -- Last word is reached
);
-- State variables
signal TxMReader_State : mReaderStates;
-- DDR Read Interface
signal DDR_rdc_sof_i : std_logic;
signal DDR_rdc_eof_i : std_logic;
signal DDR_rdc_v_i : std_logic;
signal DDR_rdc_Shift_i : std_logic;
signal DDR_rdc_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_rdc_full_i : std_logic;
-- Register read address
signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdEn : std_logic;
signal Regs_Hit : std_logic;
signal Regs_Write_mbuf_r1 : std_logic;
signal Regs_Write_mbuf_r2 : std_logic;
signal Regs_Write_mbuf_r3 : std_logic;
-- DDR FIFO read enable
signal DDR_FIFO_RdEn_i : std_logic;
signal DDR_FIFO_RdEn_Mask : std_logic;
signal DDR_FIFO_Hit : std_logic;
signal DDR_FIFO_Write_mbuf_r1 : std_logic;
signal DDR_FIFO_Write_mbuf_r2 : std_logic;
signal DDR_FIFO_Write_mbuf_r3 : std_logic;
-- Event Buffer
signal eb_FIFO_Hit : std_logic;
signal eb_FIFO_Write_mbuf : std_logic;
signal eb_FIFO_Write_mbuf_r1 : std_logic;
signal eb_FIFO_Write_mbuf_r2 : std_logic;
signal eb_FIFO_re_i : std_logic;
signal eb_FIFO_RdEn_Mask_rise : std_logic;
signal eb_FIFO_RdEn_Mask_rise_r1 : std_logic;
signal eb_FIFO_RdEn_Mask_rise_r2 : std_logic;
signal eb_FIFO_RdEn_Mask_rise_r3 : std_logic;
signal eb_FIFO_RdEn_Mask : std_logic;
signal eb_FIFO_RdEn_Mask_r1 : std_logic;
signal eb_FIFO_RdEn_Mask_r2 : std_logic;
signal ebFIFO_Rd_1DW : std_logic;
signal eb_FIFO_qout_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_qout_shift : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_qout_swapped : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Memory data outputs
signal eb_FIFO_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_Dout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_RdQout_wire : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal mbuf_Din_wire_OR : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Output port of the memory buffer
signal mbuf_Din_i : std_logic_vector(C_DBUS_WIDTH*9/8-1 downto 0);
signal mbuf_WE_i : std_logic;
signal mbuf_Full_i : std_logic;
signal mbuf_aFull_i : std_logic;
signal mbuf_UserFull_i : std_logic;
signal mbuf_aFull_r1 : std_logic;
-- Read command request and acknowledge
signal RdCmd_Req_i : std_logic;
signal RdCmd_Ack_i : std_logic;
signal Shift_1st_QWord_k : std_logic;
signal is_CplD_k : std_logic;
signal may_be_MWr_k : std_logic;
signal TRem_n_last_QWord : std_logic;
signal regs_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal regs_Rd_Cntr_eq_One : std_logic;
signal regs_Rd_Cntr_eq_Two : std_logic;
signal DDR_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal DDR_Rd_Cntr_eq_One : std_logic;
signal ebFIFO_Rd_Counter : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
signal ebFIFO_Rd_Cntr_eq_Two : std_logic;
signal Address_var : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Address_step : std_logic_vector(4-1 downto 0);
signal TxTLP_eof_n : std_logic;
signal TxTLP_eof_n_r1 : std_logic;
-- signal TxTLP_eof_n_r2 : std_logic;
signal TimeOut_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal TO_Cnt_Rst : std_logic;
signal Tx_TimeOut_i : std_logic;
signal Tx_eb_TimeOut_i : std_logic;
begin
-- read command REQ + ACK
RdCmd_Req_i <= RdCmd_Req;
RdCmd_Ack <= RdCmd_Ack_i;
-- Time out signal out
Tx_TimeOut <= Tx_TimeOut_i;
Tx_eb_TimeOut <= Tx_eb_TimeOut_i;
------------------------------------------------------------
--- Memory read control
------------------------------------------------------------
-- Event Buffer read
eb_FIFO_re <= eb_FIFO_re_i ;
-- DDR FIFO Read
DDR_rdc_sof <= DDR_rdc_sof_i ;
DDR_rdc_eof <= DDR_rdc_eof_i ;
DDR_rdc_v <= DDR_rdc_v_i ;
DDR_rdc_FA <= '0' ; -- DDR_rdc_FA_i ;
DDR_rdc_Shift <= DDR_rdc_Shift_i;
DDR_rdc_din <= DDR_rdc_din_i ;
DDR_rdc_full_i <= DDR_rdc_full ;
DDR_FIFO_RdEn <= DDR_FIFO_RdEn_i;
-- Register address for read
Regs_RdAddr <= Regs_RdAddr_i;
-- Memory buffer write port
mbuf_Din <= mbuf_Din_i;
mbuf_WE <= mbuf_WE_i;
mbuf_Full_i <= mbuf_Full;
mbuf_aFull_i <= mbuf_aFull;
mbuf_UserFull_i <= mbuf_UserFull;
--
Regs_RdAddr_i <= Address_var(C_EP_AWIDTH-1 downto 0);
-----------------------------------------------------
-- Synchronous Delay: mbuf_aFull
--
Synchron_Delay_mbuf_aFull:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
mbuf_aFull_r1 <= mbuf_aFull_i or mbuf_Full_i
or mbuf_UserFull_i;
end if;
end process;
-- ---------------------------------------------------
-- State Machine: Tx Memory read control
--
mR_FSM_Control:
process ( trn_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
DDR_rdc_sof_i <= '0';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '0';
DDR_rdc_Shift_i <= '0';
DDR_rdc_din_i <= (OTHERS=>'0');
eb_FIFO_Hit <= '0';
eb_FIFO_re_i <= '0';
eb_FIFO_RdEn_Mask <= '0';
DDR_FIFO_Hit <= '0';
DDR_FIFO_RdEn_i <= '0';
DDR_FIFO_RdEn_Mask <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
regs_Rd_Counter <= (Others=>'0');
DDR_Rd_Counter <= (Others=>'0');
DDR_Rd_Cntr_eq_One <= '0';
ebFIFO_Rd_Counter <= (Others=>'0');
ebFIFO_Rd_Cntr_eq_Two<= '0';
regs_Rd_Cntr_eq_One <= '0';
regs_Rd_Cntr_eq_Two <= '0';
Shift_1st_QWord_k <= '0';
is_CplD_k <= '0';
may_be_MWr_k <= '0';
TRem_n_last_QWord <= '0';
Address_var <= (Others=>'1');
TxTLP_eof_n <= '1';
TO_Cnt_Rst <= '0';
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
elsif trn_clk'event and trn_clk = '1' then
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i='0' then
TxMReader_State <= St_mR_Idle;
eb_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
TxTLP_eof_n <= '1';
Address_var <= (Others=>'1');
RdCmd_Ack_i <= '0';
is_CplD_k <= '0';
may_be_MWr_k <= '0';
else
RdCmd_Ack_i <= '1';
Shift_1st_QWord_k <= Shift_1st_QWord;
TRem_n_last_QWord <= Shift_1st_QWord xor RdNumber(0);
is_CplD_k <= is_CplD;
may_be_MWr_k <= not is_CplD;
TxTLP_eof_n <= '1';
if BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
eb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '1';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_DDR_A;
elsif BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
eb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '1';
Regs_RdEn <= '1';
if Shift_1st_QWord='1' then
Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0) - "100";
else
Address_var(C_EP_AWIDTH-1 downto 0) <= StartAddr(C_EP_AWIDTH-1 downto 0);
end if;
TxMReader_State <= St_mR_CmdLatch;
elsif BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
eb_FIFO_Hit <= '1';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_DDR_C;
else
eb_FIFO_Hit <= '0';
DDR_FIFO_Hit <= '0';
Regs_Hit <= '0';
Regs_RdEn <= '0';
Address_var <= Address_var;
TxMReader_State <= St_mR_CmdLatch;
end if;
end if;
when St_mR_DDR_A =>
DDR_rdc_sof_i <= '1';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '1';
DDR_rdc_Shift_i <= Shift_1st_QWord_k;
DDR_rdc_din_i <= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_TLP_FLD_WIDTH_OF_LENG+2+32)
& RdNumber & "00"
& StartAddr(C_DBUS_WIDTH-1-32 downto 0);
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '1';
TxMReader_State <= St_mR_DDR_C; -- St_mR_DDR_B;
when St_mR_DDR_C =>
DDR_rdc_sof_i <= '0';
DDR_rdc_eof_i <= '0';
DDR_rdc_v_i <= '0';
DDR_rdc_din_i <= DDR_rdc_din_i;
RdCmd_Ack_i <= '0';
TxTLP_eof_n <= '1';
-- if DDR_FIFO_Hit='1' and DDR_FIFO_Empty='1' then
if DDR_FIFO_Hit='1' and DDR_FIFO_Empty='1' and Tx_TimeOut_i='0' then
TxMReader_State <= St_mR_DDR_C;
-- elsif eb_FIFO_Hit='1' and eb_FIFO_empty='1' then
elsif eb_FIFO_Hit='1' and eb_FIFO_empty='1' and Tx_eb_TimeOut_i='0' then
TxMReader_State <= St_mR_DDR_C;
else
TxMReader_State <= St_mR_CmdLatch;
end if;
when St_mR_CmdLatch =>
RdCmd_Ack_i <= '0';
if regs_Rd_Cntr_eq_One = '1' then
Regs_RdEn <= '0';
Address_var <= Address_var;
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif regs_Rd_Cntr_eq_Two = '1' then
if Shift_1st_QWord_k='1' then
TxMReader_State <= St_mR_Transfer;
Regs_RdEn <= Regs_RdEn; -- '1';
TxTLP_eof_n <= '1';
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
else
TxMReader_State <= St_mR_Last;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
end if;
else
Regs_RdEn <= Regs_RdEn;
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
TxTLP_eof_n <= '1';
TxMReader_State <= St_mR_Transfer;
end if;
when St_mR_Transfer =>
RdCmd_Ack_i <= '0';
if DDR_FIFO_Hit='1' and DDR_FIFO_RdEn_Mask='1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif eb_FIFO_Hit='1' and eb_FIFO_RdEn_Mask='1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif eb_FIFO_Hit='0' and regs_Rd_Cntr_eq_One = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif eb_FIFO_Hit='0' and regs_Rd_Cntr_eq_Two = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= '0';
TxMReader_State <= St_mR_Last;
elsif mbuf_aFull_r1 = '1' then
Address_var <= Address_var;
Regs_RdEn <= '0';
TxTLP_eof_n <= TxTLP_eof_n;
TxMReader_State <= St_mR_Transfer;
else
Address_var(C_EP_AWIDTH-1 downto 0) <= Address_var(C_EP_AWIDTH-1 downto 0) + "1000";
Regs_RdEn <= Regs_Hit;
TxTLP_eof_n <= TxTLP_eof_n;
TxMReader_State <= St_mR_Transfer;
end if;
when St_mR_Last =>
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= (not DDR_FIFO_Hit) and (not eb_FIFO_Hit);
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
when Others =>
Address_var <= Address_var;
eb_FIFO_Hit <= '0';
Regs_RdEn <= '0';
DDR_FIFO_RdEn_i <= '0';
TxTLP_eof_n <= '1';
RdCmd_Ack_i <= '0';
TxMReader_State <= St_mR_Idle;
end case;
case TxMReader_State is
when St_mR_Idle =>
TO_Cnt_Rst <= '1';
when Others =>
TO_Cnt_Rst <= '0';
end case;
case TxMReader_State is
when St_mR_Idle =>
DDR_FIFO_RdEn_i <= '0';
DDR_FIFO_RdEn_Mask <= '0';
when Others =>
if DDR_Rd_Cntr_eq_One = '1'
and (DDR_FIFO_Empty='0' or Tx_TimeOut_i='1')
and DDR_FIFO_RdEn_i='1'
then
DDR_FIFO_RdEn_Mask <= '1';
DDR_FIFO_RdEn_i <= '0';
else
DDR_FIFO_RdEn_Mask <= DDR_FIFO_RdEn_Mask;
DDR_FIFO_RdEn_i <= DDR_FIFO_Hit
and not mbuf_aFull_r1
and not DDR_FIFO_RdEn_Mask;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
eb_FIFO_re_i <= '0';
eb_FIFO_RdEn_Mask <= '0';
when Others =>
if ebFIFO_Rd_Cntr_eq_Two = '1'
and (eb_FIFO_empty='0' or Tx_eb_TimeOut_i='1')
and eb_FIFO_re_i='1'
then
eb_FIFO_RdEn_Mask <= '1';
eb_FIFO_re_i <= '0';
else
eb_FIFO_RdEn_Mask <= eb_FIFO_RdEn_Mask;
eb_FIFO_re_i <= eb_FIFO_Hit
and not mbuf_aFull_r1
and not eb_FIFO_RdEn_Mask;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i='1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
/= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
regs_Rd_Counter <= RdNumber;
regs_Rd_Cntr_eq_One <= RdNumber_eq_One;
regs_Rd_Cntr_eq_Two <= RdNumber_eq_Two;
else
regs_Rd_Counter <= (Others=>'0');
regs_Rd_Cntr_eq_One <= '0';
regs_Rd_Cntr_eq_Two <= '0';
end if;
when St_mR_CmdLatch =>
if DDR_FIFO_Hit='0' then
if Shift_1st_QWord_k='1' then
regs_Rd_Counter <= regs_Rd_Counter - '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
else
regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
end if;
else
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end if;
when St_mR_Transfer =>
if DDR_FIFO_Hit='0'
and mbuf_aFull_r1 = '0'
then
regs_Rd_Counter <= regs_Rd_Counter - "10"; -- '1';
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
elsif regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(3, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_One <= '1';
else
regs_Rd_Cntr_eq_One <= '0';
end if;
if regs_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
regs_Rd_Cntr_eq_Two <= '1';
else
regs_Rd_Cntr_eq_Two <= '0';
end if;
else
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end if;
when Others =>
regs_Rd_Counter <= regs_Rd_Counter;
regs_Rd_Cntr_eq_One <= regs_Rd_Cntr_eq_One;
regs_Rd_Cntr_eq_Two <= regs_Rd_Cntr_eq_Two;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i='1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
if RdNumber(0)='1' then
DDR_Rd_Counter <= RdNumber + '1';
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
elsif Shift_1st_QWord='1' then
DDR_Rd_Counter <= RdNumber + "10";
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One;
else
DDR_Rd_Counter <= RdNumber;
DDR_Rd_Cntr_eq_One <= RdNumber_eq_One or RdNumber_eq_Two;
end if;
else
DDR_Rd_Counter <= (Others=>'0');
DDR_Rd_Cntr_eq_One <= '0';
end if;
when Others =>
if ((DDR_FIFO_Empty='0' or Tx_TimeOut_i='1') and DDR_FIFO_RdEn_i='1')
then
DDR_Rd_Counter <= DDR_Rd_Counter - "10"; -- '1';
if DDR_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
DDR_Rd_Cntr_eq_One <= '1';
else
DDR_Rd_Cntr_eq_One <= '0';
end if;
else
DDR_Rd_Counter <= DDR_Rd_Counter;
DDR_Rd_Cntr_eq_One <= DDR_Rd_Cntr_eq_One;
end if;
end case;
case TxMReader_State is
when St_mR_Idle =>
if RdCmd_Req_i='1' and
BAR_value(C_ENCODE_BAR_NUMBER-2 downto 0)
= CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER-1)
then
if RdNumber_eq_One='1' then
ebFIFO_Rd_Counter <= RdNumber + '1';
ebFIFO_Rd_Cntr_eq_Two <= '1';
ebFIFO_Rd_1DW <= '1';
else
ebFIFO_Rd_Counter <= RdNumber;
ebFIFO_Rd_Cntr_eq_Two <= RdNumber_eq_Two; -- or RdNumber_eq_One;
ebFIFO_Rd_1DW <= '0';
end if;
else
ebFIFO_Rd_Counter <= (Others=>'0');
ebFIFO_Rd_Cntr_eq_Two <= '0';
ebFIFO_Rd_1DW <= '0';
end if;
when Others =>
ebFIFO_Rd_1DW <= ebFIFO_Rd_1DW;
if (eb_FIFO_empty='0' or Tx_eb_TimeOut_i='1') and eb_FIFO_re_i='1'
then
ebFIFO_Rd_Counter <= ebFIFO_Rd_Counter - "10"; -- '1';
if ebFIFO_Rd_Counter = CONV_STD_LOGIC_VECTOR(4, C_TLP_FLD_WIDTH_OF_LENG) then
ebFIFO_Rd_Cntr_eq_Two <= '1';
else
ebFIFO_Rd_Cntr_eq_Two <= '0';
end if;
else
ebFIFO_Rd_Counter <= ebFIFO_Rd_Counter;
ebFIFO_Rd_Cntr_eq_Two <= ebFIFO_Rd_Cntr_eq_Two;
end if;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: mbuf_writes
--
Synchron_Delay_mbuf_writes:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Regs_Write_mbuf_r1 <= Regs_RdEn;
Regs_Write_mbuf_r2 <= Regs_Write_mbuf_r1;
Regs_Write_mbuf_r3 <= Regs_Write_mbuf_r2;
DDR_FIFO_Write_mbuf_r1 <= DDR_FIFO_RdEn_i and (not DDR_FIFO_Empty or Tx_TimeOut_i);
DDR_FIFO_Write_mbuf_r2 <= DDR_FIFO_Write_mbuf_r1;
DDR_FIFO_Write_mbuf_r3 <= DDR_FIFO_Write_mbuf_r2;
eb_FIFO_Write_mbuf <= eb_FIFO_re_i and (not eb_FIFO_empty or Tx_eb_TimeOut_i);
eb_FIFO_Write_mbuf_r1 <= eb_FIFO_Write_mbuf;
eb_FIFO_Write_mbuf_r2 <= eb_FIFO_Write_mbuf_r1;
eb_FIFO_RdEn_Mask_r1 <= eb_FIFO_RdEn_Mask;
eb_FIFO_RdEn_Mask_r2 <= eb_FIFO_RdEn_Mask_r1;
end if;
end process;
--------------------------------------------------------------------------
-- Wires to be OR'ed to build mbuf_Din
--------------------------------------------------------------------------
eb_FIFO_Dout_wire <= eb_FIFO_qout_r1 when (eb_FIFO_Hit='1' and Shift_1st_QWord_k='0')
else eb_FIFO_qout_shift when (eb_FIFO_Hit='1' and Shift_1st_QWord_k='1')
else (OTHERS=>'0');
DDR_Dout_wire <= DDR_FIFO_RdQout when DDR_FIFO_Hit='1' else (OTHERS=>'0');
Regs_RdQout_wire <= Regs_RdQout when Regs_Hit='1' else (OTHERS=>'0');
mbuf_Din_wire_OR <= eb_FIFO_Dout_wire or DDR_Dout_wire or Regs_RdQout_wire;
-----------------------------------------------------
-- Synchronous Delay: mbuf_WE
--
Synchron_Delay_mbuf_WE:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
mbuf_WE_i <= DDR_FIFO_Write_mbuf_r1
or Regs_Write_mbuf_r2
or (eb_FIFO_Write_mbuf_r1 or (Shift_1st_QWord_k and eb_FIFO_RdEn_Mask_rise_r1))
;
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: TxTLP_eof_n
--
Synchron_Delay_TxTLP_eof_n:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
TxTLP_eof_n_r1 <= TxTLP_eof_n;
-- TxTLP_eof_n_r2 <= TxTLP_eof_n_r1;
end if;
end process;
--S SIMONE BEGIN: Mi trovo in lettura dalla FIFO MSB<-->LSB Invertiti... Provo a togliere lo SWAP!!!
eb_FIFO_qout_swapped <= eb_FIFO_qout;
-- eb_FIFO_qout_swapped <= eb_FIFO_qout(C_DBUS_WIDTH/2+7 downto C_DBUS_WIDTH/2)
-- & eb_FIFO_qout(C_DBUS_WIDTH/2+15 downto C_DBUS_WIDTH/2+8)
-- & eb_FIFO_qout(C_DBUS_WIDTH/2+23 downto C_DBUS_WIDTH/2+16)
-- & eb_FIFO_qout(C_DBUS_WIDTH/2+31 downto C_DBUS_WIDTH/2+24)
--
-- & eb_FIFO_qout(7 downto 0)
-- & eb_FIFO_qout(15 downto 8)
-- & eb_FIFO_qout(23 downto 16)
-- & eb_FIFO_qout(31 downto 24)
-- ;
--S SIMONE END:
-- eb_FIFO_qout_swapped <= eb_FIFO_qout(C_DBUS_WIDTH/2-1 downto 0) & eb_FIFO_qout(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
-----------------------------------------------------
-- Synchronous Delay: eb_FIFO_qout
--
Synchron_Delay_eb_FIFO_qout:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
eb_FIFO_RdEn_Mask_rise <= eb_FIFO_RdEn_Mask and not eb_FIFO_RdEn_Mask_r1;
eb_FIFO_RdEn_Mask_rise_r1 <= eb_FIFO_RdEn_Mask_rise;
eb_FIFO_RdEn_Mask_rise_r2 <= eb_FIFO_RdEn_Mask_rise_r1;
eb_FIFO_qout_r1 <= eb_FIFO_qout_swapped;
eb_FIFO_qout_shift <= eb_FIFO_qout_r1(C_DBUS_WIDTH/2-1 downto 0)
& eb_FIFO_qout_swapped(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2);
end if;
end process;
-----------------------------------------------------
-- Synchronous Delay: mbuf_Din
--
Synchron_Delay_mbuf_Din:
process ( trn_clk, mReader_Rst_n)
begin
if mReader_Rst_n = '0' then
mbuf_Din_i <= (C_DBUS_WIDTH=>'1', Others=>'0');
elsif trn_clk'event and trn_clk = '1' then
if Tx_TimeOut_i='1' and DDR_FIFO_Hit='1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (OTHERS=>'1');
elsif Tx_eb_TimeOut_i='1' and eb_FIFO_Hit='1' and is_CplD_k='1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (OTHERS=>'1');
elsif Tx_eb_TimeOut_i='1' and eb_FIFO_Hit='1' and may_be_MWr_k='1' then
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= (OTHERS=>'1');
else
mbuf_Din_i(C_DBUS_WIDTH-1 downto 0) <= Endian_Invert_64(mbuf_Din_wire_OR);
end if;
if DDR_FIFO_Hit='1' then
mbuf_Din_i(C_DBUS_WIDTH) <= not DDR_FIFO_RdEn_Mask;
mbuf_Din_i(70) <= TRem_n_last_QWord;
elsif eb_FIFO_Hit='1' then
if Shift_1st_QWord_k='1' and ebFIFO_Rd_1DW='0' then
mbuf_Din_i(C_DBUS_WIDTH) <= not eb_FIFO_RdEn_Mask_r2;
else
mbuf_Din_i(C_DBUS_WIDTH) <= not eb_FIFO_RdEn_Mask_r1;
end if;
mbuf_Din_i(70) <= TRem_n_last_QWord;
else
mbuf_Din_i(C_DBUS_WIDTH) <= TxTLP_eof_n_r1;
mbuf_Din_i(70) <= TRem_n_last_QWord;
end if;
end if;
end process;
-----------------------------------------------------
-- Synchronous: Time-out counter
--
Synchron_TimeOut_Counter:
process ( trn_clk, TO_Cnt_Rst )
begin
if TO_Cnt_Rst='1' then
TimeOut_Counter <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
TimeOut_Counter(21 downto 0) <= TimeOut_Counter(21 downto 0) + '1';
end if;
end process;
-----------------------------------------------------
-- Synchronous: Tx_TimeOut
--
SynchOUT_Tx_TimeOut:
process ( trn_clk, mReader_Rst_n )
begin
if mReader_Rst_n='0' then
Tx_TimeOut_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if TimeOut_Counter(21 downto 6)=X"FFFF" then
-- if TimeOut_Counter(4 downto 1)=X"F" then
Tx_TimeOut_i <= '1';
else
Tx_TimeOut_i <= Tx_TimeOut_i;
end if;
end if;
end process;
-----------------------------------------------------
-- Synchronous: Tx_eb_TimeOut
--
SynchOUT_Tx_eb_TimeOut:
process ( trn_clk, mReader_Rst_n )
begin
if mReader_Rst_n='0' then
Tx_eb_TimeOut_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
-- if TimeOut_Counter(3 downto 0)=X"F" then
if TimeOut_Counter(6 downto 3)=X"F"
and is_CplD_k='1'
then
Tx_eb_TimeOut_i <= '1';
elsif TimeOut_Counter(8 downto 5)=X"F"
and may_be_MWr_k='1'
then
Tx_eb_TimeOut_i <= '1';
else
Tx_eb_TimeOut_i <= Tx_eb_TimeOut_i;
end if;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | 65058fac4b4cb2d75dec49d940c4da3b | 0.437753 | 3.573163 | false | false | false | false |
peteut/nvc | test/regress/issue338.vhd | 2 | 6,115 | entity issue338 is
end entity;
architecture a of issue338 is
signal pos : natural := 4;
signal divisor : natural := 0;
begin
pure_function : process
function fail return boolean is
begin
assert false report "Should never be reached" severity failure;
return true;
end;
procedure proc(value : boolean; expected : boolean) is
begin
assert value = expected severity failure;
end;
variable count : natural := 0;
variable value : boolean;
begin
while false and fail loop
assert false report "Should never happen" severity error;
count := count + 1;
end loop;
while true or fail loop
count := count + 2;
exit;
end loop;
if false and fail then
assert false report "Should never happen" severity error;
count := count + 4;
end if;
if true or fail then
count := count + 8;
end if;
loop
exit when true or fail;
count := count + 16;
end loop;
loop
exit when false and fail;
count := count + 32;
exit;
end loop;
proc(false and fail, false);
proc(true or fail, true);
value := true or fail;
assert value;
value := false and fail;
assert not value;
assert true or fail;
assert not (false and fail);
report integer'image(count);
assert count = 2+8+32 severity failure;
report "Finished";
wait;
end process;
impure_function : process
variable retval : boolean := false;
impure function fail return boolean is
begin
assert false report "Should never be reached" severity failure;
retval := not retval;
return retval;
end;
procedure proc(value : boolean; expected : boolean) is
begin
assert value = expected severity failure;
end;
variable count : natural := 0;
variable value : boolean;
begin
while false and fail loop
assert false report "Should never happen" severity error;
count := count + 1;
end loop;
while true or fail loop
count := count + 2;
exit;
end loop;
if false and fail then
assert false report "Should never happen" severity error;
count := count + 4;
end if;
if true or fail then
count := count + 8;
end if;
loop
exit when true or fail;
count := count + 16;
end loop;
loop
exit when false and fail;
count := count + 32;
exit;
end loop;
proc(false and fail, false);
proc(true or fail, true);
value := true or fail;
assert value;
value := false and fail;
assert not value;
assert true or fail;
assert not (false and fail);
report integer'image(count);
assert count = 2+8+32 severity failure;
report "Finished";
wait;
end process;
access_out_of_range : process
constant s : string := "123";
procedure proc(value : boolean; expected : boolean) is
begin
assert value = expected severity failure;
end;
variable count : natural := 0;
variable value : boolean;
begin
while false and s(pos) = '1' loop
assert false report "Should never happen" severity error;
count := count + 1;
end loop;
while true or s(pos) = '1' loop
count := count + 2;
exit;
end loop;
if false and s(pos) = '1' then
assert false report "Should never happen" severity error;
count := count + 4;
end if;
if true or s(pos) = '1' then
count := count + 8;
end if;
loop
exit when true or s(pos) = '1';
count := count + 16;
end loop;
loop
exit when false and s(pos) = '1';
count := count + 32;
exit;
end loop;
proc(false and s(pos) = '1', false);
proc(true or s(pos) = '1', true);
value := true or s(pos) = '1';
assert value;
value := false and s(pos) = '1';
assert not value;
assert true or s(pos) = '1';
assert not (false and s(pos) = '1');
report integer'image(count);
assert count = 2+8+32 severity failure;
report "Finished";
wait;
end process;
non_static_access_out_of_range : process
constant s : string := "123";
procedure proc(value : boolean; expected : boolean) is
begin
assert value = expected severity failure;
end;
variable count : natural := 0;
variable value : boolean;
variable pos : natural;
begin
pos := 4;
while pos < 4 and s(pos) = '1' loop
assert false report "Should never happen" severity error;
count := count + 1;
end loop;
while pos = 4 or s(pos) = '1' loop
count := count + 2;
exit;
end loop;
if pos < 4 and s(pos) = '1' then
assert false report "Should never happen" severity error;
count := count + 4;
end if;
if pos = 4 or s(pos) = '1' then
count := count + 8;
end if;
loop
exit when pos = 4 or s(pos) = '1';
count := count + 16;
end loop;
loop
exit when pos < 4 and s(pos) = '1';
count := count + 32;
exit;
end loop;
proc(pos < 4 and s(pos) = '1', false);
proc(pos = 4 or s(pos) = '1', true);
value := pos = 4 or s(pos) = '1';
assert value;
value := pos < 4 and s(pos) = '1';
assert not value;
assert pos = 4 or s(pos) = '1';
assert not (pos < 4 and s(pos) = '1');
report integer'image(count);
assert count = 2+8+32 severity failure;
report "Finished";
wait;
end process;
divide_by_zero : process
begin
assert true or 7/divisor = 1;
assert not (false and 7/divisor = 1);
wait;
end process;
pure_but_expensive : process
function expensive return boolean is
variable result : integer;
begin
for i in 0 to 2**29 loop
for j in 0 to 2**29 loop
for k in 0 to 2*29 loop
result := ((result+k-i+j) mod 2**19) * (k mod 2**10);
end loop;
end loop;
end loop;
return (result mod 16) = 0;
end;
begin
assert true or expensive;
assert not (false and expensive);
wait;
end process;
end;
| gpl-3.0 | 6ec491e383ca88a8cfcdcc547761d6a4 | 0.580213 | 3.86048 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/Tx_Output_Arbitor.vhd | 1 | 7,534 |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
----------- Top entity ---------------
entity Tx_Output_Arbitor is
port (
rst_n : IN std_logic;
clk : IN std_logic;
arbtake : IN std_logic; -- take a valid arbitration by the user
Req : IN std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0); -- similar to FIFO not-empty
bufread : OUT std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0); -- Read FIFO
Ack : OUT std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0) -- tells who is the winner
);
end Tx_Output_Arbitor;
architecture Behavioral of Tx_Output_Arbitor is
TYPE ArbStates is (
aSt_Reset
, aSt_Idle
, aSt_ReadOne
, aSt_Ready
);
signal Arb_FSM : ArbStates;
signal Arb_FSM_NS : ArbStates;
TYPE PriorMatrix is ARRAY (C_ARBITRATE_WIDTH-1 downto 0)
of std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0);
signal ChPriority : PriorMatrix;
signal Prior_Init_Value : PriorMatrix;
signal Wide_Req : PriorMatrix;
signal Wide_Req_turned : PriorMatrix;
signal take_i : std_logic;
signal Req_i : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
signal Req_r1 : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
signal read_prep : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
signal read_i : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
signal Indice_prep : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
signal Indice_i : std_logic_vector(C_ARBITRATE_WIDTH-1 downto 0);
signal Champion_Vector : std_logic_vector (C_ARBITRATE_WIDTH-1 downto 0);
begin
bufread <= read_i;
Ack <= Indice_i;
take_i <= arbtake;
Req_i <= Req;
-- ------------------------------------------------------------
Prior_Init_Value(0) <= C_LOWEST_PRIORITY;
Gen_Prior_Init_Values:
FOR i IN 1 TO C_ARBITRATE_WIDTH-1 generate
Prior_Init_Value(i) <= Prior_Init_Value(i-1)(C_ARBITRATE_WIDTH-2 downto 0) & '1';
end generate;
-- ------------------------------------------------------------
-- Mask the requests
--
Gen_Wide_Requests:
FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
Wide_Req(i) <= ChPriority(i) when Req_i(i)='1'
else C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
end generate;
-- ------------------------------------
-- Synchronous Delay: Req
--
Synch_Delay_Req:
process(clk)
begin
if clk'event and clk = '1' then
Req_r1 <= Req_i;
end if;
end process;
-- ------------------------------------
-- Synchronous: States
--
Seq_FSM_NextState:
process(clk, rst_n)
begin
if (rst_n = '0') then
Arb_FSM <= aSt_Reset;
elsif clk'event and clk = '1' then
Arb_FSM <= Arb_FSM_NS;
end if;
end process;
-- ------------------------------------
-- Combinatorial: Next States
--
Comb_FSM_NextState:
process (
Arb_FSM
, take_i
, Req_r1
)
begin
case Arb_FSM is
when aSt_Reset =>
Arb_FSM_NS <= aSt_Idle;
when aSt_Idle =>
if Req_r1 = C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then
Arb_FSM_NS <= aSt_Idle;
else
Arb_FSM_NS <= aSt_ReadOne;
end if;
when aSt_ReadOne =>
if Req_r1 = C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then -- Ghost Request !!!
Arb_FSM_NS <= aSt_Idle;
else
Arb_FSM_NS <= aSt_Ready;
end if;
when aSt_Ready =>
if take_i = '0' then
Arb_FSM_NS <= aSt_Ready;
elsif Req_r1 = C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then
Arb_FSM_NS <= aSt_Idle;
else
Arb_FSM_NS <= aSt_ReadOne;
end if;
when Others =>
Arb_FSM_NS <= aSt_Reset;
end case;
end process;
-- --------------------------------------------------
-- Turn the Request-Array Around
--
Turn_the_Request_Array_Around:
FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
Dimension_2nd:
FOR j IN 0 TO C_ARBITRATE_WIDTH-1 generate
Wide_Req_turned(i)(j) <= Wide_Req(j)(i);
END generate;
END generate;
-- --------------------------------------------------
-- Synchronous Calculation: Champion_Vector
--
Sync_Champion_Vector:
process(clk)
begin
if clk'event and clk = '1' then
FOR i IN 0 TO C_ARBITRATE_WIDTH-1 LOOP
if Wide_Req_turned(i)=C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0) then
Champion_Vector(i) <= '0';
else
Champion_Vector(i) <= '1';
end if;
END LOOP;
end if;
end process;
-- --------------------------------------------------
-- Prepare the buffer read signal: read_i
--
Gen_Read_Signals:
FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
read_prep(i) <= '1' when Champion_Vector=ChPriority(i) else '0';
end generate;
-- --------------------------------------------------
-- FSM Output : Buffer read_i and Indice_i
--
FSM_Output_read_Indice:
process (clk, rst_n)
begin
if (rst_n = '0') then
read_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
Indice_prep <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
elsif clk'event and clk = '1' then
case Arb_FSM is
when aSt_ReadOne =>
read_i <= read_prep;
Indice_prep <= read_prep;
Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
when aSt_Ready =>
read_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
Indice_prep <= Indice_prep;
if take_i ='1' then
Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
else
Indice_i <= Indice_prep;
end if;
when Others =>
read_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
Indice_prep <= Indice_prep;
Indice_i <= C_ALL_ZEROS(C_ARBITRATE_WIDTH-1 downto 0);
end case;
end if;
end process;
-- --------------------------------------------------
--
Gen_Modify_Priorities:
FOR i IN 0 TO C_ARBITRATE_WIDTH-1 generate
Proc_Priority_Cycling:
process (clk, rst_n)
begin
if (rst_n = '0') then
ChPriority(i) <= Prior_Init_Value(i);
elsif clk'event and clk = '1' then
case Arb_FSM is
when aSt_ReadOne =>
if ChPriority(i) = Champion_Vector then
ChPriority(i) <= C_LOWEST_PRIORITY;
elsif (ChPriority(i) and Champion_Vector) = Champion_Vector then
ChPriority(i) <= ChPriority(i);
else
ChPriority(i) <= ChPriority(i)(C_ARBITRATE_WIDTH-2 downto 0) & '1';
end if;
when Others =>
ChPriority(i) <= ChPriority(i);
end case;
end if;
end process;
end generate;
end architecture Behavioral;
| gpl-2.0 | 777d50e935d664ae6807167b419d68e0 | 0.496947 | 3.776441 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/fifo8to32/simulation/fifo8to32_synth.vhd | 1 | 10,975 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo8to32_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo8to32_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo8to32_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo8to32_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo8to32_dgen
GENERIC MAP (
C_DIN_WIDTH => 16,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo8to32_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 16,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo8to32_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 16,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 9,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo8to32_inst : fifo8to32_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | 087db34a115bb386ed88b0df02247c05 | 0.459226 | 3.957807 | false | false | false | false |
ObKo/USBCore | Extra/blk_ep_in_ctl.vhdl | 1 | 6,039 | --
-- USB Full-Speed/Hi-Speed Device Controller core - blk_ep_in_ctl.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.USBCore.all;
use work.USBExtra.all;
entity blk_ep_in_ctl is
generic (
USE_ASYNC_FIFO : boolean := false
);
port (
rst : in std_logic;
usb_clk : in std_logic;
axis_clk : in std_logic;
blk_in_xfer : in std_logic;
blk_xfer_in_has_data : out std_logic;
blk_xfer_in_data : out std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : out std_logic;
blk_xfer_in_data_ready : in std_logic;
blk_xfer_in_data_last : out std_logic;
axis_tdata : in std_logic_vector(7 downto 0);
axis_tvalid : in std_logic;
axis_tready : out std_logic;
axis_tlast : in std_logic
);
end blk_ep_in_ctl;
architecture blk_ep_in_ctl of blk_ep_in_ctl is
component blk_in_fifo
port (
m_aclk : in std_logic;
s_aclk : in std_logic;
s_aresetn : in std_logic;
s_axis_tvalid : in std_logic;
s_axis_tready : out std_logic;
s_axis_tdata : in std_logic_vector(7 downto 0);
s_axis_tlast : in std_logic;
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(7 downto 0);
m_axis_tlast : in std_logic;
axis_prog_full : out std_logic
);
end component;
type MACHINE is (S_Idle, S_Xfer);
signal state : MACHINE := S_Idle;
signal s_axis_tvalid : std_logic;
signal s_axis_tready : std_logic;
signal s_axis_tdata : std_logic_vector(7 downto 0);
signal s_axis_tlast : std_logic;
signal m_axis_tvalid : std_logic;
signal m_axis_tready : std_logic;
signal m_axis_tdata : std_logic_vector(7 downto 0);
signal m_axis_tlast : std_logic;
signal prog_full : std_logic;
signal was_last_usb : std_logic;
signal was_last : std_logic;
signal was_last_d : std_logic;
signal was_last_dd : std_logic;
begin
FSM: process(usb_clk) is
begin
if rst = '1' then
state <= S_Idle;
blk_xfer_in_has_data <= '0';
elsif rising_edge(usb_clk) then
case state is
when S_Idle =>
if was_last_usb = '1' OR prog_full = '1' then
blk_xfer_in_has_data <= '1';
end if;
if blk_in_xfer = '1' then
state <= S_Xfer;
end if;
when S_Xfer =>
if blk_in_xfer = '0' then
blk_xfer_in_has_data <= '0';
state <= S_Idle;
end if;
end case;
end if;
end process;
ASYNC: if USE_ASYNC_FIFO generate
-- 3 of data clk => axis_clk < 180 MHz if usb_clk = 60 MHz
was_last_usb <= was_last OR was_last_d OR was_last_dd;
FIFO: blk_in_fifo
port map (
m_aclk => usb_clk,
s_aclk => axis_clk,
s_aresetn => NOT rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
axis_prog_full => prog_full
);
end generate;
SYNC: if not USE_ASYNC_FIFO generate
was_last_usb <= was_last;
FIFO: sync_fifo
generic map (
FIFO_WIDTH => 8,
FIFO_DEPTH => 1024,
PROG_FULL_VALUE => 64
)
port map (
clk => usb_clk,
rst => rst,
s_axis_tvalid => s_axis_tvalid,
s_axis_tready => s_axis_tready,
s_axis_tdata => s_axis_tdata,
s_axis_tlast => s_axis_tlast,
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => m_axis_tready,
m_axis_tdata => m_axis_tdata,
m_axis_tlast => m_axis_tlast,
prog_full => prog_full
);
end generate;
WAS_LAST_LATCHER: process(axis_clk) is
begin
if rst = '1' then
was_last <= '0';
was_last_d <= '0';
was_last_dd <= '0';
elsif rising_edge(axis_clk) then
if s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '1' then
was_last <= '1';
elsif s_axis_tvalid = '1' AND s_axis_tready = '1' AND s_axis_tlast = '0' then
was_last <= '0';
end if;
was_last_d <= was_last;
was_last_dd <= was_last_d;
end if;
end process;
s_axis_tdata <= axis_tdata;
s_axis_tvalid <= axis_tvalid;
axis_tready <= s_axis_tready;
s_axis_tlast <= axis_tlast;
blk_xfer_in_data <= m_axis_tdata;
blk_xfer_in_data_valid <= m_axis_tvalid;
m_axis_tready <= blk_xfer_in_data_ready;
blk_xfer_in_data_last <= m_axis_tlast;
end blk_ep_in_ctl; | mit | 0a346e0adf5ce75a9deac892bbf8aa65 | 0.586687 | 3.260799 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/IIR_Biquad_II_v2.vhd | 4 | 22,166 | --////////////////////// IIR_Biquad_II /////////////////////////////////--
-- ***********************************************************************
-- FileName: IIR_Biquad_II.vhd
-- FPGA: Xilinx Spartan 6
-- IDE: Xilinx ISE 13.1
--
-- HDL IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
-- DIGI-KEY ALSO DISCLAIMS ANY LIABILITY FOR PATENT OR COPYRIGHT
-- INFRINGEMENT.
--
-- Version History
-- Version 1.0 7/31/2012 Tony Storey
-- Initial Public Releaselibrary ieee;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity IIR_Biquad_II_v2 is
Port (
Coef_b0 : std_logic_vector(31 downto 0);
Coef_b1 : std_logic_vector(31 downto 0);
Coef_b2 : std_logic_vector(31 downto 0);
Coef_a1 : std_logic_vector(31 downto 0);
Coef_a2 : std_logic_vector(31 downto 0);
clk : in STD_LOGIC;
clk_100M : in STD_LOGIC;
rst : in STD_LOGIC;
sample_trig : in STD_LOGIC;
X_in : in STD_LOGIC_VECTOR (15 downto 0);
filter_done : out STD_LOGIC;
Y_out : out STD_LOGIC_VECTOR (15 downto 0)
);
end IIR_Biquad_II_v2;
architecture arch of IIR_Biquad_II_v2 is
-- band stop butterworth 2nd order fo = 59.79, fl = 55Hz, fu = 65Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
--------------------------------------------------------------------------
--
-- b0 + b1*Z^-1 + b2*Z^-2
-- H[z] = -------------------------
-- 1 + a1*Z^-1 + a2*Z^-2
--
--------------------------------------------------------------------------
-- define biquad coefficients --WORKED WITH HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1101_1101_1011_0000_1001"; -- b0 ~ +0.999869117
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_00_0000_0000_0101_0100_1100_1000_1010"; -- b1 ~ -1.999676575
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1101_1101_1011_0000_1001"; -- b2 ~ +0.999869117
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0000_0000_0101_0100_1100_1000_1010"; -- a1 ~ -1.999676575
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_1111_1011_1011_0110_0001_0011"; -- a2 ~ +0.999738235
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- band pass 2nd order elliptical fl= 7200Hz, fu = 7400Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b0 ~ +0.9944543
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- b1 ~ -1.1479874
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b2 ~ +0.9944543
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- a1 ~ -1.1479874
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_0100_1010_0100_0111_0100_1011"; -- a2 ~ +0.9889086
-- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients -- WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients DID NOT WORK NO SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients --WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
--
-- -- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients WORKED WITH VERY HIGH SOUND
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b0 ~ +0.0010232
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0010_0001_1000_0111_0011_1001"; -- b1 ~ +0.0020464
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_00_0000_0001_0000_1100_0011_1001_1100"; -- b2 ~ +0.0010232
--
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_0101_1110_1011_0111_1110_0110_1000"; -- a1 ~ -1.9075016
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1010_0101_0111_1001_0000_0111_0101"; -- a2 ~ +0.9115945
-- define each pre gain sample flip flop
signal ZFF_X0, ZFF_X1, ZFF_X2, ZFF_Y1, ZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define each post gain 64 bit sample
signal pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad : std_logic_vector( 63 downto 0) := (others => '0');
-- define each post gain 32 but truncated sample
signal pgZFF_X0, pgZFF_X1, pgZFF_X2, pgZFF_Y1, pgZFF_Y2 : std_logic_vector(31 downto 0) := (others => '0');
-- define output double reg
signal Y_out_double : std_logic_vector(31 downto 0) := (others => '0');
-- state machine signals
type state_type is (idle, run);
signal state_reg, state_next : state_type;
-- counter signals
signal q_reg, q_next : unsigned(2 downto 0);
signal q_reset, q_add : std_logic;
-- data path flags
signal mul_coefs, trunc_prods, sum_stg_a, trunc_out : std_logic;
begin
-- process to shift samples
process(clk_100M, rst, Y_out_double, sample_trig)
begin
if(rst = '1') then
ZFF_X0 <= (others => '0');
ZFF_X1 <= (others => '0');
ZFF_X2 <= (others => '0');
ZFF_Y1 <= (others => '0');
ZFF_Y2 <= (others => '0');
elsif(rising_edge(clk_100M)) then
if clk = '1' then
if(sample_trig = '1' AND state_reg = idle) then
ZFF_X0 <= X_in(15) & X_in(15) & X_in(15) & X_in(15) & X_in & B"0000_0000_0000"; -- X_in(17) & X_in(17) & X_in & B"0000_0000_0000";
ZFF_X1 <= ZFF_X0;
ZFF_X2 <= ZFF_X1;
ZFF_Y1 <= Y_out_double;
ZFF_Y2 <= ZFF_Y1;
end if;
end if;
end if;
end process;
-- STATE UPDATE AND TIMING
process(clk_100M, rst)
begin
if(rst = '1') then
state_reg <= idle;
q_reg <= (others => '0'); -- reset counter
elsif (rising_edge(clk_100M)) then
if clk = '1' then
state_reg <= state_next; -- update the state
q_reg <= q_next;
end if;
end if;
end process;
-- COUNTER FOR TIMING
q_next <= (others => '0') when q_reset = '1' else -- resets the counter
q_reg + 1 when q_add = '1' else -- increment count if commanded
q_reg;
-- process for control of data path flags
process( q_reg, state_reg, sample_trig)
begin
-- defaults
q_reset <= '0';
q_add <= '0';
mul_coefs <= '0';
trunc_prods <= '0';
sum_stg_a <= '0';
trunc_out <= '0';
filter_done <= '0';
case state_reg is
when idle =>
if(sample_trig = '1') then
state_next <= run;
else
state_next <= idle;
end if;
when run =>
if( q_reg < B"001") then
q_add <= '1';
state_next <= run;
elsif( q_reg < "011") then
mul_coefs <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "100") then
trunc_prods <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "101") then
sum_stg_a <= '1';
q_add <= '1';
state_next <= run;
elsif( q_reg < "110") then
trunc_out <= '1';
q_add <= '1';
state_next <= run;
else
q_reset <= '1';
filter_done <= '1';
state_next <= idle;
end if;
end case;
end process;
-- add gain factors to numerator of biquad (feed forward path)
pgZFF_X0_quad <= std_logic_vector( signed(Coef_b0) * signed(ZFF_X0)) when mul_coefs = '1';
pgZFF_X1_quad <= std_logic_vector( signed(Coef_b1) * signed(ZFF_X1)) when mul_coefs = '1';
pgZFF_X2_quad <= std_logic_vector( signed(Coef_b2) * signed(ZFF_X2)) when mul_coefs = '1';
-- add gain factors to denominator of biquad (feed back path)
pgZFF_Y1_quad <= std_logic_vector( signed(Coef_a1) * signed(ZFF_Y1)) when mul_coefs = '1';
pgZFF_Y2_quad <= std_logic_vector( signed(Coef_a2) * signed(ZFF_Y2)) when mul_coefs = '1';
-- truncate the output to summation block
process(clk_100M, trunc_prods, pgZFF_X0_quad, pgZFF_X1_quad, pgZFF_X2_quad, pgZFF_Y1_quad, pgZFF_Y2_quad)
begin
if rising_edge(clk_100M) then
if clk = '1' then
if (trunc_prods = '1') then
pgZFF_X0 <= pgZFF_X0_quad(61 downto 30);
pgZFF_X2 <= pgZFF_X2_quad(61 downto 30);
pgZFF_X1 <= pgZFF_X1_quad(61 downto 30);
pgZFF_Y1 <= pgZFF_Y1_quad(61 downto 30);
pgZFF_Y2 <= pgZFF_Y2_quad(61 downto 30);
end if;
end if;
end if;
end process;
-- sum all post gain feedback and feedfoward paths
-- Y[z] = X[z]*bo + X[z]*b1*Z^-1 + X[z]*b2*Z^-2 - Y[z]*a1*z^-1 + Y[z]*a2*z^-2
process(clk_100M, sum_stg_a)
begin
if(rising_edge(clk_100M)) then
if clk = '1' then
if(sum_stg_a = '1') then
Y_out_double <= std_logic_vector(signed(pgZFF_X0) + signed(pgZFF_X1) + signed(pgZFF_X2) - signed(pgZFF_Y1) - signed(pgZFF_Y2));
end if;
end if;
end if;
end process;
-- output truncation block
process(clk_100M, trunc_out)
begin
if rising_edge(clk_100M) then
if clk = '1' then
if (trunc_out = '1') then
Y_out <= Y_out_double( 30 downto 15);
end if;
end if;
end if;
end process;
end arch;
-- Pre Generated Example IIR filters
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------
-- -- band pass 2nd order butterworth f0 = 2000Hz, fl = 1500Hz, fu = 2500 Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0011_1110_1111_1100_1111_0000_1111"; -- b0 ~ +0.061511769
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ 0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1100_0001_0000_0011_0000_1111_0001"; -- b0 ~ -0.061511769
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1011_1011_0111_1011_1110_0101_0111"; -- a1 ~ -1.816910185
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1000_0010_0000_0110_0001_1110_0010"; -- a2 ~ +0.876976463
-- -- band pass 2nd order elliptical fl= 7200Hz, fu = 7400Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b0 ~ +0.9944543
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- b1 ~ -1.1479874
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1111_1101_0010_0010_0011_1010_0101"; -- b2 ~ +0.9944543
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_11_0110_1000_0111_0101_1111_1101_1011"; -- a1 ~ -1.1479874
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_1111_0100_1010_0100_0111_0100_1011"; -- a2 ~ +0.9889086
-- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272
-- -- band pass 2nd order elliptical fl= 2000Hz, fu = 2500Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_00_0100_1001_0001_0011_0101_0100_0111"; -- b0 ~ +0.0713628
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- b1 ~ +0.0
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"11_11_1011_0110_1110_1100_1010_1011_1000"; -- b2 ~ -0.0713628
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_00_1110_0011_0001_0001_1010_1011_1111"; -- a1 ~ -1.7782529
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0110_1101_1101_1001_0101_0111_0001"; -- a2 ~ +0.8572744
-- -- Used Bilinear Z Transform
-- -- low pass 2nd order butterworth fc = 12000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b0 ~ +0.292893219
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"00_10_0101_0111_1101_1000_0110_0110_0110"; -- b1 ~ +0.585786438
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_01_0010_1011_1110_1100_0011_0011_0011"; -- b2 ~ +0.292893219
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0000_0000_0000_0000"; -- a1 ~ 0.0
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_00_0000_0000_0000_0101_0111_1101_1000"; -- a2 ~ +0.171572875
--
-- -- stop band 2nd order butterworth f0 = 3000Hz, fl = 2000Hz, fu = 4000Hz, Fs = 48000Hz, PBR = .08 dB, SBR = .03 dB
-- --------------------------------------------------------------------------
----
---- b0 + b1*Z^-1 + b2*Z^-2
---- H[z] = -------------------------
---- 1 + a1*Z^-1 + a2*Z^-2
----
-- --------------------------------------------------------------------------
--
---- define biquad coefficients
-- constant Coef_b0 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b0 ~ +0.8836636
-- constant Coef_b1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- b1 ~ -1.6468868
-- constant Coef_b2 : std_logic_vector(31 downto 0) := B"00_11_1000_1000_1101_1111_0001_1100_0110"; -- b2 ~ +0.8836636
-- constant Coef_a1 : std_logic_vector(31 downto 0) := B"10_01_0110_1001_1001_0110_1000_0001_1011"; -- a1 ~ -1.6468868
-- constant Coef_a2 : std_logic_vector(31 downto 0) := B"00_11_0001_0001_1011_1110_0011_1000_1011"; -- a2 ~ +0.7673272 | mit | eafc51ed8299b5de52ca93202f1b07a5 | 0.507805 | 2.778042 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_hid.vhd | 1 | 5,620 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file weight_hid.vhd when simulating
-- the core, weight_hid. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY weight_hid IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END weight_hid;
ARCHITECTURE weight_hid_a OF weight_hid IS
-- synthesis translate_off
COMPONENT wrapped_weight_hid
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_weight_hid USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 8,
c_addrb_width => 8,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "artix7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "weight_hid.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 230,
c_read_depth_b => 230,
c_read_width_a => 320,
c_read_width_b => 320,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 230,
c_write_depth_b => 230,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 320,
c_write_width_b => 320,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_weight_hid
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END weight_hid_a;
| bsd-2-clause | 850ddfca645544aa8d676108c8f3fef7 | 0.532918 | 3.957746 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_hid/simulation/weight_hid_tb.vhd | 1 | 4,334 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: weight_hid_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY weight_hid_tb IS
END ENTITY;
ARCHITECTURE weight_hid_tb_ARCH OF weight_hid_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
weight_hid_synth_inst:ENTITY work.weight_hid_synth
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-2-clause | a5815a8e7b0f92c67c57bada784f75cb | 0.620212 | 4.660215 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/adau1761_audio_v1_00_a/hdl/vhdl/clocking.vhd | 3 | 7,981 | -- file: clocking.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____48.000______0.000______50.0______273.634____296.868
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clocking is
port
(-- Clock in ports
CLK_100 : in std_logic;
-- Clock out ports
CLK_48 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end clocking;
architecture xilinx of clocking is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clocking,clk_wiz_v3_6,{component_name=clocking,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkfboutb_unused : std_logic;
signal clkout0 : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
-- clkin1_buf : IBUFG
-- port map
-- (O => clkin1,
-- I => CLK_100);
-- Clocking primitive
--------------------------------------
-- Instantiation of the MMCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 49.500,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 20.625,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.000,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clkout0,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN1 => CLK_100,--clkin1,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => LOCKED,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => RESET);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_48,
I => clkout0);
end xilinx;
| mit | 1d187b68e2797471e23c343282513edf | 0.570104 | 4.169801 | false | false | false | false |
peteut/nvc | test/regress/issue377.vhd | 2 | 708 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity issue377 is
end entity;
architecture test of issue377 is
signal sticky : std_logic;
signal shiftedFracY_d1 : std_logic_vector(49 downto 0);
begin
update: sticky <= '0' when (shiftedFracY_d1(23 downto 0)=CONV_STD_LOGIC_VECTOR(0,23)) else '1';
stim: process is
begin
wait for 1 ns;
assert sticky = '1';
shiftedFracY_d1(19 downto 0) <= X"00000";
wait for 1 ns;
assert sticky = '1';
shiftedFracY_d1(24 downto 20) <= "00000";
wait for 1 ns;
assert sticky = '0';
wait;
end process;
end architecture;
| gpl-3.0 | 12771640aa16e1faebad848b4a2f2305 | 0.625706 | 3.38756 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/synth/cpu_axi_iic_0_0.vhd | 1 | 10,035 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_iic:2.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_iic_v2_0;
USE axi_iic_v2_0.axi_iic;
ENTITY cpu_axi_iic_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_axi_iic_0_0;
ARCHITECTURE cpu_axi_iic_0_0_arch OF cpu_axi_iic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_iic IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_IIC_FREQ : INTEGER;
C_TEN_BIT_ADR : INTEGER;
C_GPO_WIDTH : INTEGER;
C_S_AXI_ACLK_FREQ_HZ : INTEGER;
C_SCL_INERTIAL_DELAY : INTEGER;
C_SDA_INERTIAL_DELAY : INTEGER;
C_SDA_LEVEL : INTEGER;
C_SMBUS_PMBUS_HOST : INTEGER;
C_DEFAULT_VALUE : STD_LOGIC_VECTOR(7 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
iic2intc_irpt : OUT STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
sda_i : IN STD_LOGIC;
sda_o : OUT STD_LOGIC;
sda_t : OUT STD_LOGIC;
scl_i : IN STD_LOGIC;
scl_o : OUT STD_LOGIC;
scl_t : OUT STD_LOGIC;
gpo : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT axi_iic;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "axi_iic,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_axi_iic_0_0_arch : ARCHITECTURE IS "cpu_axi_iic_0_0,axi_iic,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_axi_iic_0_0_arch: ARCHITECTURE IS "cpu_axi_iic_0_0,axi_iic,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_iic,x_ipVersion=2.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_S_AXI_ADDR_WIDTH=9,C_S_AXI_DATA_WIDTH=32,C_IIC_FREQ=100000,C_TEN_BIT_ADR=0,C_GPO_WIDTH=1,C_S_AXI_ACLK_FREQ_HZ=100000000,C_SCL_INERTIAL_DELAY=0,C_SDA_INERTIAL_DELAY=0,C_SDA_LEVEL=1,C_SMBUS_PMBUS_HOST=0,C_DEFAULT_VALUE=0x00}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF iic2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF sda_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF sda_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF sda_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF scl_i: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF scl_o: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF scl_t: SIGNAL IS "xilinx.com:interface:iic:1.0 IIC SCL_T";
BEGIN
U0 : axi_iic
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_IIC_FREQ => 100000,
C_TEN_BIT_ADR => 0,
C_GPO_WIDTH => 1,
C_S_AXI_ACLK_FREQ_HZ => 100000000,
C_SCL_INERTIAL_DELAY => 0,
C_SDA_INERTIAL_DELAY => 0,
C_SDA_LEVEL => 1,
C_SMBUS_PMBUS_HOST => 0,
C_DEFAULT_VALUE => X"00"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
iic2intc_irpt => iic2intc_irpt,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
sda_i => sda_i,
sda_o => sda_o,
sda_t => sda_t,
scl_i => scl_i,
scl_o => scl_o,
scl_t => scl_t,
gpo => gpo
);
END cpu_axi_iic_0_0_arch;
| gpl-3.0 | 9fc68fcba4ef6b9ab766f3cbee208cf6 | 0.683408 | 3.15864 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/alu.vhd | 1 | 6,028 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 09-04-2017
-- Package Name: alu
-- Module Name: ALU
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ALU is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OPERATION : in std_logic_vector(3 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
ZERO_OUT : out std_logic
);
end entity;
architecture ALU_ARCH of ALU is
component ADDER_SUBTRACTOR_COMPONENT is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
IS_SUB : in std_logic; -- 0 for add and 1 for subtraction
SUM : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
OVERFLOW : out std_logic
);
end component;
component VECTOR_NORER is
port(
INPUT : in std_logic_vector(15 downto 0);
OUTPUT : out std_logic
);
end component;
component AND_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component OR_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component XOR_COMPONENT is
port(
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component SHIFT_L_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component SHIFT_R_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component MULTIPLICATION_COMPONENT is
port(
INPUT1 : in std_logic_vector(16/2 - 1 downto 0);
INPUT2 : in std_logic_vector(16/2 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
component NOT_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end component;
signal UNKNOWN_SIG : std_logic_vector(16 - 1 downto 0);
signal ZERO_SIG : std_logic_vector(16 - 1 downto 0);
---------------- OUTPUT SIGNALS OF COMPONENTS ----------------
signal ADDER_SUB_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal ADDER_SUB_COMPONENT_CARRY : std_logic;
signal AND_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal OR_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal XOR_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal SHIFT_L_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal SHIFT_R_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal MULTIPLICATION_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal NOT_COMPONENT_OUT : std_logic_vector(16 - 1 downto 0);
signal OUTPUT_TEMP : std_logic_vector(16 - 1 downto 0);
begin
GENERATE_UNKNOWN_SIG : for I in UNKNOWN_SIG'range generate
UNKNOWN_SIG(I) <= 'U';
end generate GENERATE_UNKNOWN_SIG;
GENERATE_ZERO_SIG : for I in ZERO_SIG'range generate
ZERO_SIG(I) <= '0';
end generate GENERATE_ZERO_SIG;
---------------------------------- ALU COMPONENTS INSTANTIATION SECTION ----------------------------------
ADDER_SUB_COMPONENT_INS : component ADDER_SUBTRACTOR_COMPONENT
port map(
CARRY_IN => CARRY_IN,
INPUT1 => INPUT1,
INPUT2 => INPUT2,
IS_SUB => OPERATION(0),
SUM => ADDER_SUB_COMPONENT_OUT,
CARRY_OUT => ADDER_SUB_COMPONENT_CARRY,
OVERFLOW => open
);
AND_COMPONENT_INS : AND_COMPONENT
port map(
INPUT1 => INPUT1,
INPUT2 => INPUT2,
OUTPUT => AND_COMPONENT_OUT
);
OR_COMPONENT_INS : OR_COMPONENT
port map(
INPUT1 => INPUT1,
INPUT2 => INPUT2,
OUTPUT => OR_COMPONENT_OUT
);
XOR_COMPONENT_INS : XOR_COMPONENT
port map(
INPUT1 => INPUT1,
INPUT2 => INPUT2,
OUTPUT => XOR_COMPONENT_OUT
);
SHIFT_L_COMPONENT_INS : SHIFT_L_COMPONENT
port map(
INPUT => INPUT1,
OUTPUT => SHIFT_L_COMPONENT_OUT
);
SHIFT_R_COMPONENT_INS : SHIFT_R_COMPONENT
port map(
INPUT => INPUT1,
OUTPUT => SHIFT_R_COMPONENT_OUT
);
MULTIPLICATION_COMPONENT_INS : component MULTIPLICATION_COMPONENT
port map(
INPUT1 => INPUT1(16/2 - 1 downto 0),
INPUT2 => INPUT2(16/2 - 1 downto 0),
OUTPUT => MULTIPLICATION_COMPONENT_OUT
);
NOT_COMPONENT_INS : component NOT_COMPONENT
port map(
INPUT => INPUT1,
OUTPUT => NOT_COMPONENT_OUT
);
OUTPUT <= OUTPUT_TEMP;
---------------------------------- SELECTOR OUTPUTS SECTION ----------------------------------
OUTPUT_ASSIGNMENT : with OPERATION select
OUTPUT_TEMP <=
AND_COMPONENT_OUT when "0000",
OR_COMPONENT_OUT when "0001",
XOR_COMPONENT_OUT when "0010",
SHIFT_L_COMPONENT_OUT when "0100",
SHIFT_R_COMPONENT_OUT when "0101",
ADDER_SUB_COMPONENT_OUT when "0110",
ADDER_SUB_COMPONENT_OUT when "0111",
NOT_COMPONENT_OUT when "1000",
MULTIPLICATION_COMPONENT_OUT when "1001",
INPUT2 when "1010",
UNKNOWN_SIG when others;
CARRY_ASSIGNMENT : with OPERATION select
CARRY_OUT <=
'0' when "0000",
'0' when "0001",
'0' when "0010",
'0' when "0100",
'0' when "0101",
ADDER_SUB_COMPONENT_CARRY when "0110",
ADDER_SUB_COMPONENT_CARRY when "0111",
'0' when "1000",
'0' when "1001",
'0' when "1010",
'U' when others;
ZERO_OUT <= '0';
end architecture; | gpl-3.0 | 23ea1aa3738af1acbbab02bc9fa023f3 | 0.601194 | 3.083376 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/example_design/ram_16x8k_dp_prod.vhd | 1 | 10,701 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x8k_dp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x8k_dp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x8k_dp_prod;
ARCHITECTURE xilinx OF ram_16x8k_dp_prod IS
COMPONENT ram_16x8k_dp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x8k_dp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
| bsd-3-clause | 73b8bf0ef71db0d89eda9932e987f2fb | 0.489207 | 3.808185 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/register/register_file.vhd | 1 | 970 | library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity registerFile is
port (
CLK : in std_logic;
W_EN : in std_logic;
INPUT : in std_logic_vector(15 downto 0);
IN_ADR : in std_logic_vector(3 downto 0);
OUT1_ADR: in std_logic_vector(3 downto 0);
OUT2_ADR: in std_logic_vector(3 downto 0);
OUTPUT1 : out std_logic_vector(15 downto 0);
OUTPUT2 : out std_logic_vector(15 downto 0);
REG0_OUT: out std_logic_vector(15 downto 0)
);
end entity;
architecture registerFile_ARCH of registerFile is
type reg_64n16b is array (0 to 15) of STD_LOGIC_VECTOR(15 downto 0);
signal data : reg_64n16b;
begin
OUTPUT1 <= data(to_integer(unsigned(OUT1_ADR)));
OUTPUT2 <= data(to_integer(unsigned(OUT2_ADR)));
REG0_OUT <= data(0);
process(clk)
begin
if(CLK = '1' and CLK'event) then
if(W_EN = '1') then
data(to_integer(unsigned(IN_ADR))) <= INPUT;
end if;
end if;
end process;
end architecture; | gpl-3.0 | 4853e019bff61eb7a5a07f2224840081 | 0.663918 | 2.607527 | false | false | false | false |
peteut/nvc | test/elab/issue315.vhd | 2 | 807 | entity issue315 is
generic (
DATA_BITS : integer := 32
);
end entity;
architecture test of issue315 is
type INFO_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
BITS : integer;
end record;
function SET_INFO return INFO_TYPE is
variable info : INFO_TYPE;
variable index : integer;
begin
index := 0;
info.DATA_LO := index;
info.DATA_HI := index + DATA_BITS - 1;
index := index + DATA_BITS;
info.BITS := index;
return info;
end function;
constant INFO : INFO_TYPE := SET_INFO;
signal i_info : bit_vector(INFO.BITS-1 downto 0);
signal o_info : bit_vector(INFO.BITS-1 downto 0);
begin
end architecture;
| gpl-3.0 | e4746bf97e925a13252db0df20bbd966 | 0.539033 | 3.824645 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/Registers.vhd | 1 | 173,989 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity Regs_Group is
port (
-- DCB protocol interface
protocol_link_act : IN std_logic_vector(2-1 downto 0);
protocol_rst : OUT std_logic;
-- Fabric side: CTL Rx
ctl_rv : OUT std_logic;
ctl_rd : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: CTL Tx
ctl_ttake : OUT std_logic;
ctl_tv : IN std_logic;
ctl_td : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
ctl_tstop : OUT std_logic;
ctl_reset : OUT std_logic;
ctl_status : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Rx
dlm_tv : OUT std_logic;
dlm_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Fabric side: DLM Tx
dlm_rv : IN std_logic;
dlm_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- Event Buffer status + reset
eb_FIFO_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_Rst : OUT std_logic;
eb_FIFO_ow : IN std_logic;
H2B_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
B2H_FIFO_Status : IN std_logic_VECTOR(C_DBUS_WIDTH-1 downto 0);
-- Write interface
Regs_WrEnA : IN std_logic;
Regs_WrMaskA : IN std_logic_vector(2-1 downto 0);
Regs_WrAddrA : IN std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEnB : IN std_logic;
Regs_WrMaskB : IN std_logic_vector(2-1 downto 0);
Regs_WrAddrB : IN std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDinB : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register Read interface
Regs_RdAddr : IN std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : IN std_logic;
ds_DMA_Bytes : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers to/from Downstream Engine
DMA_ds_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : OUT std_logic; -- obsolete
DMA_ds_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : IN std_logic;
DMA_ds_Tout : IN std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : OUT std_logic;
dsBDA_is_64b : OUT std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : OUT std_logic;
dsLeng_Lo7b_True : OUT std_logic;
-- Downstream Control Signals
dsDMA_Start : OUT std_logic;
dsDMA_Stop : OUT std_logic;
dsDMA_Start2 : OUT std_logic;
dsDMA_Stop2 : OUT std_logic;
dsDMA_Channel_Rst : OUT std_logic;
dsDMA_Cmd_Ack : IN std_logic;
-- Upstream DMA transferred bytes count up
us_DMA_Bytes_Add : IN std_logic;
us_DMA_Bytes : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Registers to/from Upstream Engine
DMA_us_PA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : OUT std_logic; -- obsolete
us_MWr_Param_Vec : OUT std_logic_vector(6-1 downto 0);
DMA_us_Status : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : IN std_logic;
DMA_us_Tout : IN std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : OUT std_logic;
usBDA_is_64b : OUT std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : OUT std_logic;
usLeng_Lo7b_True : OUT std_logic;
-- Upstream Control Signals
usDMA_Start : OUT std_logic;
usDMA_Stop : OUT std_logic;
usDMA_Start2 : OUT std_logic;
usDMA_Stop2 : OUT std_logic;
usDMA_Channel_Rst : OUT std_logic;
usDMA_Cmd_Ack : IN std_logic;
-- MRd Channel Reset
MRd_Channel_Rst : OUT std_logic;
-- Tx module reset
Tx_Reset : OUT std_logic;
-- to Interrupts Module
Sys_IRQ : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
Sys_Int_Enable : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System error and info
Tx_TimeOut : IN std_logic;
Tx_eb_TimeOut : IN std_logic;
Msg_Routing : OUT std_logic_vector(C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT downto 0);
pcie_link_width : IN std_logic_vector(CINT_BIT_LWIDTH_IN_GSR_TOP-CINT_BIT_LWIDTH_IN_GSR_BOT downto 0);
cfg_dcommand : IN std_logic_vector(16-1 downto 0);
-- Interrupt Generation Signals
IG_Reset : OUT std_logic;
IG_Host_Clear : OUT std_logic;
IG_Latency : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : IN std_logic;
-- Data generator control
DG_is_Running : IN std_logic;
DG_Reset : OUT std_logic;
DG_Mask : OUT std_logic;
-- SIMONE Register: PC-->FPGA
reg01_tv : OUT std_logic;
reg01_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_tv : OUT std_logic;
reg02_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_tv : OUT std_logic;
reg03_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_tv : OUT std_logic;
reg04_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_tv : OUT std_logic;
reg05_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_tv : OUT std_logic;
reg06_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_tv : OUT std_logic;
reg07_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_tv : OUT std_logic;
reg08_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_tv : OUT std_logic;
reg09_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_tv : OUT std_logic;
reg10_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_tv : OUT std_logic;
reg11_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_tv : OUT std_logic;
reg12_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_tv : OUT std_logic;
reg13_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_tv : OUT std_logic;
reg14_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg15_tv : OUT std_logic;
reg15_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg16_tv : OUT std_logic;
reg16_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg17_tv : OUT std_logic;
reg17_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg18_tv : OUT std_logic;
reg18_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg19_tv : OUT std_logic;
reg19_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg20_tv : OUT std_logic;
reg20_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg21_tv : OUT std_logic;
reg21_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg22_tv : OUT std_logic;
reg22_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg23_tv : OUT std_logic;
reg23_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg24_tv : OUT std_logic;
reg24_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg25_tv : OUT std_logic;
reg25_td : OUT std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: FPGA-->PC
reg01_rv : IN std_logic;
reg01_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg02_rv : IN std_logic;
reg02_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg03_rv : IN std_logic;
reg03_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg04_rv : IN std_logic;
reg04_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg05_rv : IN std_logic;
reg05_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg06_rv : IN std_logic;
reg06_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg07_rv : IN std_logic;
reg07_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg08_rv : IN std_logic;
reg08_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg09_rv : IN std_logic;
reg09_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg10_rv : IN std_logic;
reg10_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg11_rv : IN std_logic;
reg11_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg12_rv : IN std_logic;
reg12_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg13_rv : IN std_logic;
reg13_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg14_rv : IN std_logic;
reg14_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg15_rv : IN std_logic;
reg15_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg16_rv : IN std_logic;
reg16_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg17_rv : IN std_logic;
reg17_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg18_rv : IN std_logic;
reg18_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg19_rv : IN std_logic;
reg19_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg20_rv : IN std_logic;
reg20_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg21_rv : IN std_logic;
reg21_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg22_rv : IN std_logic;
reg22_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg23_rv : IN std_logic;
reg23_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg24_rv : IN std_logic;
reg24_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
reg25_rv : IN std_logic;
reg25_rd : IN std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--SIMONE debug signals
debug_in_1i : OUT std_logic_vector(31 downto 0);
debug_in_2i : OUT std_logic_vector(31 downto 0);
debug_in_3i : OUT std_logic_vector(31 downto 0);
debug_in_4i : OUT std_logic_vector(31 downto 0);
-- Clock and reset
trn_clk : IN std_logic;
trn_lnk_up_n : IN std_logic;
trn_reset_n : IN std_logic
);
end Regs_Group;
architecture Behavioral of Regs_Group is
type icapStates is ( icapST_Reset
, icapST_Idle
, icapST_Access
, icapST_Abort
);
-- State variables of ICAP
signal FSM_icap : icapStates;
----------------------------------------------------------------------------
----------------------------------------------------------------------------
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
------ Delay signals
signal Regs_WrEn_r1 : std_logic;
signal Regs_WrAddr_r1 : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrMask_r1 : std_logic_vector(2-1 downto 0);
signal Regs_WrDin_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_WrEn_r2 : std_logic;
signal Regs_WrDin_r2 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Regs_Wr_dma_V_hi_r2 : std_logic;
signal Regs_Wr_dma_nV_hi_r2 : std_logic;
signal Regs_Wr_dma_V_nE_hi_r2 : std_logic;
signal Regs_Wr_dma_V_lo_r2 : std_logic;
signal Regs_Wr_dma_nV_lo_r2 : std_logic;
signal Regs_Wr_dma_V_nE_lo_r2 : std_logic;
signal WrDin_r1_not_Zero_Hi : std_logic_vector(4-1 downto 0);
signal WrDin_r2_not_Zero_Hi : std_logic;
signal WrDin_r1_not_Zero_Lo : std_logic_vector(4-1 downto 0);
signal WrDin_r2_not_Zero_Lo : std_logic;
-- Calculation in advance, just for better timing
signal Regs_WrDin_Hi19b_True_hq_r2 : std_logic;
signal Regs_WrDin_Lo7b_True_hq_r2 : std_logic;
signal Regs_WrDin_Hi19b_True_lq_r2 : std_logic;
signal Regs_WrDin_Lo7b_True_lq_r2 : std_logic;
signal Regs_WrEnA_r1 : std_logic;
signal Regs_WrEnB_r1 : std_logic;
signal Regs_WrEnA_r2 : std_logic;
signal Regs_WrEnB_r2 : std_logic;
-- Register write mux signals
signal Reg_WrMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_WrMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Signals for Tx reading
signal Regs_RdAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_RdQout_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register read mux signals
signal Reg_RdMuxer_Hi : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
signal Reg_RdMuxer_Lo : std_logic_vector(C_NUM_OF_ADDRESSES-1 downto 0);
-- Optical Link status
signal Opto_Link_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Opto_Link_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Opto_Link_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer
signal eb_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal H2B_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal H2B_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal H2B_FIFO_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal B2H_FIFO_Status_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal B2H_FIFO_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal B2H_FIFO_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal eb_FIFO_Rst_i : std_logic;
signal eb_FIFO_Rst_b1 : std_logic;
signal eb_FIFO_Rst_b2 : std_logic;
signal eb_FIFO_Rst_b3 : std_logic;
signal eb_FIFO_OverWritten : std_logic;
-- Downstream DMA registers
signal DMA_ds_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Upstream DMA registers
signal DMA_us_PA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_PA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- System Interrupt Status/Control
signal Sys_IRQ_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Int_Enable_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Data generator control
signal DG_Reset_i : std_logic;
signal DG_Mask_i : std_logic;
signal DG_is_Available : std_logic;
signal DG_Rst_Counter : std_logic_vector(8-1 downto 0);
signal DG_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DG_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DG_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- General Control and Status
signal Sys_Error_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Error_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Sys_Error_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Control_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal General_Status_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Hardward version
signal HW_Version_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal HW_Version_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Signal as the source of interrupts
signal IG_Host_Clear_i : std_logic;
signal IG_Reset_i : std_logic;
-- Interrupt Generator Control
signal IG_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Latency
signal IG_Latency_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Latency_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Latency_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Assert number
signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Assert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Deassert number
signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal IG_Num_Deassert_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- IntClr character is written
signal Command_is_Host_iClr_Hi : std_logic;
signal Command_is_Host_iClr_Lo : std_logic;
-- Downstream Registers
signal DMA_ds_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_ds_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Last_Ctrl_Word_ds : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
signal dsHA_is_64b_i : std_logic;
signal dsBDA_is_64b_i : std_logic;
-- Calculation in advance, for better timing
signal dsLeng_Hi19b_True_i : std_logic;
signal dsLeng_Lo7b_True_i : std_logic;
-- Downstream Control Signals
signal dsDMA_Start_i : std_logic;
signal dsDMA_Stop_i : std_logic;
signal dsDMA_Start2_i : std_logic;
signal dsDMA_Start2_r1 : std_logic;
signal dsDMA_Stop2_i : std_logic;
signal dsDMA_Channel_Rst_i : std_logic;
signal ds_Param_Modified : std_logic;
-- Upstream Registers
signal DMA_us_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_us_Transf_Bytes_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal Last_Ctrl_Word_us : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
signal usHA_is_64b_i : std_logic;
signal usBDA_is_64b_i : std_logic;
-- Calculation in advance, for better timing
signal usLeng_Hi19b_True_i : std_logic;
signal usLeng_Lo7b_True_i : std_logic;
-- Upstream Control Signals
signal usDMA_Start_i : std_logic;
signal usDMA_Stop_i : std_logic;
signal usDMA_Start2_i : std_logic;
signal usDMA_Start2_r1 : std_logic;
signal usDMA_Stop2_i : std_logic;
signal usDMA_Channel_Rst_i : std_logic;
signal us_Param_Modified : std_logic;
-- Reset character is written
signal Command_is_Reset_Hi : std_logic;
signal Command_is_Reset_Lo : std_logic;
-- MRd channel reset
signal MRd_Channel_Rst_i : std_logic;
-- Tx module reset
signal Tx_Reset_i : std_logic;
-- ICAP
signal icap_CLK : std_logic;
signal icap_I : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal icap_CE : std_logic;
signal icap_Write : std_logic;
signal icap_O : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal icap_O_o_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal icap_O_o_Lo : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal icap_BUSY : std_logic;
-- DCB protocol interface
signal protocol_rst_i : std_logic;
signal protocol_rst_b1 : std_logic;
signal protocol_rst_b2 : std_logic;
-- Protocol : CTL
signal ctl_rv_i : std_logic;
signal ctl_rd_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal class_CTL_Status_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal class_CTL_Status_o_Hi: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal class_CTL_Status_o_Lo: std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal ctl_td_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal ctl_td_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal ctl_td_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal ctl_reset_i : std_logic;
signal ctl_ttake_i : std_logic;
signal ctl_tstop_i : std_logic;
signal ctl_t_read_Hi_r1 : std_logic;
signal ctl_t_read_Lo_r1 : std_logic;
signal CTL_read_counter : std_logic_vector(6-1 downto 0);
-- Protocol : DLM
signal dlm_tv_i : std_logic;
signal dlm_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal dlm_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal dlm_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal dlm_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: PC-->FPGA
signal reg01_tv_i : std_logic;
signal reg01_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg02_tv_i : std_logic;
signal reg02_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg03_tv_i : std_logic;
signal reg03_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg04_tv_i : std_logic;
signal reg04_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg05_tv_i : std_logic;
signal reg05_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg06_tv_i : std_logic;
signal reg06_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg07_tv_i : std_logic;
signal reg07_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg08_tv_i : std_logic;
signal reg08_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg09_tv_i : std_logic;
signal reg09_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg10_tv_i : std_logic;
signal reg10_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg11_tv_i : std_logic;
signal reg11_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg12_tv_i : std_logic;
signal reg12_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg13_tv_i : std_logic;
signal reg13_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg14_tv_i : std_logic;
signal reg14_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg15_tv_i : std_logic;
signal reg15_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg16_tv_i : std_logic;
signal reg16_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg17_tv_i : std_logic;
signal reg17_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg18_tv_i : std_logic;
signal reg18_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg19_tv_i : std_logic;
signal reg19_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg20_tv_i : std_logic;
signal reg20_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg21_tv_i : std_logic;
signal reg21_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg22_tv_i : std_logic;
signal reg22_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg23_tv_i : std_logic;
signal reg23_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg24_tv_i : std_logic;
signal reg24_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg25_tv_i : std_logic;
signal reg25_td_i : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
-- SIMONE Register: FPGA-->PC
signal reg01_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg01_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg01_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg02_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg02_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg02_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg03_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg03_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg03_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg04_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg04_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg04_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg05_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg05_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg05_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg06_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg06_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg06_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg07_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg07_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg07_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg08_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg08_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg08_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg09_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg09_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg09_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg10_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg10_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg10_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg11_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg11_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg11_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg12_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg12_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg12_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg13_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg13_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg13_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg14_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg14_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg14_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg15_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg15_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg15_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg16_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg16_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg16_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg17_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg17_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg17_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg18_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg18_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg18_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg19_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg19_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg19_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg20_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg20_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg20_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg21_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg21_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg21_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg22_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg22_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg22_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg23_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg23_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg23_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg24_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg24_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg24_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg25_rd_o_Hi : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg25_rd_o_Lo : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal reg25_rd_r : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
--signal debug_in_1i : std_logic_vector(31 downto 0);
--signal debug_in_2i : std_logic_vector(31 downto 0);
--signal debug_in_3i : std_logic_vector(31 downto 0);
begin
DG_Available_Bit: if IMP_DATA_GENERATOR generate
DG_is_Available <= '1';
end generate;
DG_Unavailable_Bit: if not IMP_DATA_GENERATOR generate
DG_is_Available <= '0';
end generate;
-- SIMONE Register: PC-->FPGA
reg01_tv <= reg01_tv_i;
reg01_td <= reg01_td_i;
reg02_tv <= reg02_tv_i;
reg02_td <= reg02_td_i;
reg03_tv <= reg03_tv_i;
reg03_td <= reg03_td_i;
reg04_tv <= reg04_tv_i;
reg04_td <= reg04_td_i;
reg05_tv <= reg05_tv_i;
reg05_td <= reg05_td_i;
reg06_tv <= reg06_tv_i;
reg06_td <= reg06_td_i;
reg07_tv <= reg07_tv_i;
reg07_td <= reg07_td_i;
reg08_tv <= reg08_tv_i;
reg08_td <= reg08_td_i;
reg09_tv <= reg09_tv_i;
reg09_td <= reg09_td_i;
reg10_tv <= reg10_tv_i;
reg10_td <= reg10_td_i;
reg11_tv <= reg11_tv_i;
reg11_td <= reg11_td_i;
reg12_tv <= reg12_tv_i;
reg12_td <= reg12_td_i;
reg13_tv <= reg13_tv_i;
reg13_td <= reg13_td_i;
reg14_tv <= reg14_tv_i;
reg14_td <= reg14_td_i;
reg15_tv <= reg15_tv_i;
reg15_td <= reg15_td_i;
reg16_tv <= reg16_tv_i;
reg16_td <= reg16_td_i;
reg17_tv <= reg17_tv_i;
reg17_td <= reg17_td_i;
reg18_tv <= reg18_tv_i;
reg18_td <= reg18_td_i;
reg19_tv <= reg19_tv_i;
reg19_td <= reg19_td_i;
reg20_tv <= reg20_tv_i;
reg20_td <= reg20_td_i;
reg21_tv <= reg21_tv_i;
reg21_td <= reg21_td_i;
reg22_tv <= reg22_tv_i;
reg22_td <= reg22_td_i;
reg23_tv <= reg23_tv_i;
reg23_td <= reg23_td_i;
reg24_tv <= reg24_tv_i;
reg24_td <= reg24_td_i;
reg25_tv <= reg25_tv_i;
reg25_td <= reg25_td_i;
-- protocol interface reset
protocol_rst <= protocol_rst_i;
ctl_rv <= ctl_rv_i;
ctl_rd <= ctl_rd_i;
ctl_ttake <= ctl_ttake_i;
ctl_tstop <= ctl_tstop_i;
ctl_reset <= ctl_reset_i;
ctl_tstop_i <= '0'; -- ???
dlm_tv <= dlm_tv_i;
dlm_td <= dlm_td_i;
-- Data generator control
DG_Reset <= DG_Reset_i;
DG_Mask <= DG_Mask_i;
-- Event buffer reset
eb_FIFO_Rst <= eb_FIFO_Rst_i;
-- MRd channel reset
MRd_Channel_Rst <= MRd_Channel_Rst_i;
-- Tx module reset
Tx_Reset <= Tx_Reset_i;
-- Upstream DMA engine reset
usDMA_Channel_Rst <= usDMA_Channel_Rst_i;
-- Downstream DMA engine reset
dsDMA_Channel_Rst <= dsDMA_Channel_Rst_i;
-- Upstream DMA registers
DMA_us_PA <= DMA_us_PA_i;
DMA_us_HA <= DMA_us_HA_i;
DMA_us_BDA <= DMA_us_BDA_i;
DMA_us_Length <= DMA_us_Length_i;
DMA_us_Control <= DMA_us_Control_i;
usDMA_BDA_eq_Null <= '0';
DMA_us_Status_i <= DMA_us_Status;
usHA_is_64b <= usHA_is_64b_i;
usBDA_is_64b <= usBDA_is_64b_i;
usLeng_Hi19b_True <= usLeng_Hi19b_True_i;
usLeng_Lo7b_True <= usLeng_Lo7b_True_i;
usDMA_Start <= usDMA_Start_i;
usDMA_Stop <= usDMA_Stop_i;
usDMA_Start2 <= usDMA_Start2_r1;
-- usDMA_Start2 <= usDMA_Start2_i;
usDMA_Stop2 <= usDMA_Stop2_i;
-- Downstream DMA registers
DMA_ds_PA <= DMA_ds_PA_i;
DMA_ds_HA <= DMA_ds_HA_i;
DMA_ds_BDA <= DMA_ds_BDA_i;
DMA_ds_Length <= DMA_ds_Length_i;
DMA_ds_Control <= DMA_ds_Control_i;
dsDMA_BDA_eq_Null <= '0';
DMA_ds_Status_i <= DMA_ds_Status;
dsHA_is_64b <= dsHA_is_64b_i;
dsBDA_is_64b <= dsBDA_is_64b_i;
dsLeng_Hi19b_True <= dsLeng_Hi19b_True_i;
dsLeng_Lo7b_True <= dsLeng_Lo7b_True_i;
dsDMA_Start <= dsDMA_Start_i;
dsDMA_Stop <= dsDMA_Stop_i;
dsDMA_Start2 <= dsDMA_Start2_r1;
-- dsDMA_Start2 <= dsDMA_Start2_i;
dsDMA_Stop2 <= dsDMA_Stop2_i;
-- Register to Interrupt handler module
Sys_IRQ <= Sys_IRQ_i;
Sys_Int_Enable <= Sys_Int_Enable_i;
-- Message routing method
Msg_Routing <= General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT);
-- us_MWr_TLP_Param
us_MWr_Param_Vec <= General_Control_i(13 downto 8);
-- ------------- Interrupt generator generation ----------------------
Gen_IG: if IMP_INT_GENERATOR generate
IG_Reset <= IG_Reset_i;
IG_Host_Clear <= IG_Host_Clear_i; -- and Sys_Int_Enable_i(CINT_BIT_INTGEN_IN_ISR);
IG_Latency <= IG_Latency_i;
IG_Num_Assert_i <= IG_Num_Assert;
IG_Num_Deassert_i <= IG_Num_Deassert;
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
IG_Control_i <= (OTHERS => '0');
IG_Reset_i <= '1';
IG_Host_Clear_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
IG_Reset_i <= Command_is_Reset_Hi;
IG_Host_Clear_i <= Command_is_Host_iClr_Hi;
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
IG_Reset_i <= Command_is_Reset_Lo;
IG_Host_Clear_i <= Command_is_Host_iClr_Lo;
else
IG_Control_i <= IG_Control_i;
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Latency_i
SysReg_IntGen_Latency:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
IG_Latency_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset_i='1' then
IG_Latency_i <= (OTHERS => '0');
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
IG_Latency_i <= IG_Latency_i;
end if;
end if;
end process;
end generate;
NotGen_IG: if not IMP_INT_GENERATOR generate
IG_Reset <= '0';
IG_Host_Clear <= '0';
IG_Latency <= (OTHERS=>'0');
IG_Num_Assert_i <= (OTHERS=>'0');
IG_Num_Deassert_i <= (OTHERS=>'0');
IG_Control_i <= (OTHERS=>'0');
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
IG_Latency_i <= (OTHERS=>'0');
end generate;
-- ----------------------------------------------
-- Synchronous Delay : Sys_IRQ_i
--
Synch_Delay_Sys_IRQ:
process ( trn_clk, trn_lnk_up_n )
begin
if trn_lnk_up_n = '1' then
Sys_IRQ_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
Sys_IRQ_i(C_NUM_OF_INTERRUPTS-1 downto 0)
<= Sys_Int_Enable_i(C_NUM_OF_INTERRUPTS-1 downto 0)
and Sys_Int_Status_i(C_NUM_OF_INTERRUPTS-1 downto 0);
end if;
end process;
-- ----------------------------------------------
-- Registers writing
--
Regs_WrAddr_i <= Regs_WrAddrA and Regs_WrAddrB;
Regs_WrMask_i <= Regs_WrMaskA or Regs_WrMaskB;
Regs_WrDin_i <= Regs_WrDinA or Regs_WrDinB;
-- ----------------------------------------------
-- Registers reading
--
Regs_RdAddr_i <= Regs_RdAddr;
Regs_RdQout <= Regs_RdQout_i;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrEn
--
Synch_Delay_Regs_WrEn:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Regs_WrEn_r1 <= Regs_WrEnA or Regs_WrEnB;
Regs_WrEn_r2 <= Regs_WrEn_r1;
Regs_WrEnA_r1 <= Regs_WrEnA;
Regs_WrEnA_r2 <= Regs_WrEnA_r1;
Regs_WrEnB_r1 <= Regs_WrEnB;
Regs_WrEnB_r2 <= Regs_WrEnB_r1;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Opto_Link_Status
--
Synch_Delay_Opto_Link_Status:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Opto_Link_Status_i(C_DBUS_WIDTH-1 downto 2) <= (OTHERS=>'0');
Opto_Link_Status_i(2-1 downto 0) <= protocol_link_act;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : eb_FIFO_Status
--
Synch_Delay_eb_FIFO_Status:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
eb_FIFO_Status_r1 <= eb_FIFO_Status;
end if;
end process;
Synch_Delay_H2B_FIFO_Status:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
H2B_FIFO_Status_r1 <= H2B_FIFO_Status;
end if;
end process;
Synch_Delay_B2H_FIFO_Status:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
B2H_FIFO_Status_r1 <= B2H_FIFO_Status;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrAddr
--
Synch_Delay_Regs_WrAddr:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Regs_WrAddr_r1 <= Regs_WrAddr_i;
Regs_WrMask_r1 <= Regs_WrMask_i;
end if;
end process;
-- ----------------------------------------------------
-- Synchronous Delay : dsDMA_Start2
-- usDMA_Start2
-- (Special recipe for 64-bit successive descriptors)
--
Synch_Delay_DMA_Start2:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
dsDMA_Start2_r1 <= dsDMA_Start2_i and not dsDMA_Cmd_Ack;
usDMA_Start2_r1 <= usDMA_Start2_i and not usDMA_Cmd_Ack;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Delay : Regs_WrDin_i
--
Synch_Delay_Regs_WrDin:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Regs_WrDin_r1 <= Regs_WrDin_i;
Regs_WrDin_r2 <= Regs_WrDin_r1;
if Regs_WrDin_i(31+32 downto 24+32) = C_ALL_ZEROS(31+32 downto 24+32) then
WrDin_r1_not_Zero_Hi(3) <= '0';
else
WrDin_r1_not_Zero_Hi(3) <= '1';
end if;
if Regs_WrDin_i(23+32 downto 16+32) = C_ALL_ZEROS(23+32 downto 16+32) then
WrDin_r1_not_Zero_Hi(2) <= '0';
else
WrDin_r1_not_Zero_Hi(2) <= '1';
end if;
if Regs_WrDin_i(15+32 downto 8+32) = C_ALL_ZEROS(15+32 downto 8+32) then
WrDin_r1_not_Zero_Hi(1) <= '0';
else
WrDin_r1_not_Zero_Hi(1) <= '1';
end if;
if Regs_WrDin_i(7+32 downto 0+32) = C_ALL_ZEROS(7+32 downto 0+32) then
WrDin_r1_not_Zero_Hi(0) <= '0';
else
WrDin_r1_not_Zero_Hi(0) <= '1';
end if;
if WrDin_r1_not_Zero_Hi = C_ALL_ZEROS(3 downto 0) then
WrDin_r2_not_Zero_Hi <= '0';
else
WrDin_r2_not_Zero_Hi <= '1';
end if;
if Regs_WrDin_i(31 downto 24) = C_ALL_ZEROS(31 downto 24) then
WrDin_r1_not_Zero_Lo(3) <= '0';
else
WrDin_r1_not_Zero_Lo(3) <= '1';
end if;
if Regs_WrDin_i(23 downto 16) = C_ALL_ZEROS(23 downto 16) then
WrDin_r1_not_Zero_Lo(2) <= '0';
else
WrDin_r1_not_Zero_Lo(2) <= '1';
end if;
if Regs_WrDin_i(15 downto 8) = C_ALL_ZEROS(15 downto 8) then
WrDin_r1_not_Zero_Lo(1) <= '0';
else
WrDin_r1_not_Zero_Lo(1) <= '1';
end if;
if Regs_WrDin_i(7 downto 0) = C_ALL_ZEROS(7 downto 0) then
WrDin_r1_not_Zero_Lo(0) <= '0';
else
WrDin_r1_not_Zero_Lo(0) <= '1';
end if;
if WrDin_r1_not_Zero_Lo = C_ALL_ZEROS(3 downto 0) then
WrDin_r2_not_Zero_Lo <= '0';
else
WrDin_r2_not_Zero_Lo <= '1';
end if;
end if;
end process;
-- -----------------------------------------------------------
-- Synchronous Delay : DMA Commands Write Valid and not End
--
Synch_Delay_dmaCmd_Wr_Valid_and_End:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Regs_Wr_dma_V_hi_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
;
Regs_Wr_dma_nV_hi_r2 <= Regs_WrEn_r1
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
;
Regs_Wr_dma_V_nE_hi_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID+32)
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END+32)
;
Regs_Wr_dma_V_lo_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
;
Regs_Wr_dma_nV_lo_r2 <= Regs_WrEn_r1
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
;
Regs_Wr_dma_V_nE_lo_r2 <= Regs_WrEn_r1
and Regs_WrDin_r1(CINT_BIT_DMA_CTRL_VALID)
and not Regs_WrDin_r1(CINT_BIT_DMA_CTRL_END)
;
end if;
end process;
-- ------------------------------------------------
-- Synchronous Delay : Regs_WrDin_Hi19b_True_r2 x2
-- Regs_WrDin_Lo7b_True_r2 x2
--
Synch_Delay_Regs_WrDin_Hi19b_and_Lo7b_True:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
if Regs_WrDin_r1(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
= C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1+32)
then
Regs_WrDin_Hi19b_True_hq_r2 <= '0';
else
Regs_WrDin_Hi19b_True_hq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1+32 downto 2+32)
then -- ! Lowest 2 bits ignored !
Regs_WrDin_Lo7b_True_hq_r2 <= '0';
else
Regs_WrDin_Lo7b_True_hq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
= C_ALL_ZEROS(C_DBUS_WIDTH-1-32 downto C_MAXSIZE_FLD_BIT_TOP+1)
then
Regs_WrDin_Hi19b_True_lq_r2 <= '0';
else
Regs_WrDin_Hi19b_True_lq_r2 <= '1';
end if;
if Regs_WrDin_r1(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
then -- ! Lowest 2 bits ignored !
Regs_WrDin_Lo7b_True_lq_r2 <= '0';
else
Regs_WrDin_Lo7b_True_lq_r2 <= '1';
end if;
end if;
end process;
-- ---------------------------------------
--
Write_DMA_Registers_Mux:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Reg_WrMuxer_Hi <= (Others => '0');
Reg_WrMuxer_Lo <= (Others => '0');
elsif trn_clk'event and trn_clk = '1' then
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(0, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Hi(0) <= not Regs_WrMask_r1(1);
else
Reg_WrMuxer_Hi(0) <= '0';
end if;
FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Hi(k) <= not Regs_WrMask_r1(1);
else
Reg_WrMuxer_Hi(k) <= '0';
end if;
if -- Regs_WrAddr_r1(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)=C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
-- and
Regs_WrAddr_r1(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
-- and Regs_WrAddr_r1(2-1 downto 0)="00"
then
Reg_WrMuxer_Lo(k) <= not Regs_WrMask_r1(0);
else
Reg_WrMuxer_Lo(k) <= '0';
end if;
END LOOP;
end if;
end process;
-- -----------------------------------------------
-- System Interrupt Status Control
-- -----------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: Sys_Int_Enable_i
SysReg_Sys_Int_Enable:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Sys_Int_Enable_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
then
Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
then
Sys_Int_Enable_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
Sys_Int_Enable_i <= Sys_Int_Enable_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- System General Control Register
-- -----------------------------------------------
-- -----------------------------------------------
-- Synchronous Registered: General_Control
SysReg_General_Control:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
General_Control_i <= (OTHERS => '0');
General_Control_i(C_GCR_MSG_ROUT_BIT_TOP downto C_GCR_MSG_ROUT_BIT_BOT)
<= C_TYPE_OF_MSG(C_TLP_TYPE_BIT_BOT+C_GCR_MSG_ROUT_BIT_TOP-C_GCR_MSG_ROUT_BIT_BOT
downto C_TLP_TYPE_BIT_BOT);
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_CONTROL)='1'
then
General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_CONTROL)='1'
then
General_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
General_Control_i <= General_Control_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: DG_Reset_i
SysReg_DGen_Reset:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DG_Reset_i <= '1';
DG_Rst_Counter <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if DG_Rst_Counter=X"FF" then
DG_Rst_Counter <= DG_Rst_Counter;
else
DG_Rst_Counter <= DG_Rst_Counter + '1';
end if;
if DG_Rst_Counter(7)='0' then
DG_Reset_i <= '1';
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
then
DG_Reset_i <= Command_is_Reset_Hi;
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
then
DG_Reset_i <= Command_is_Reset_Lo;
else
DG_Reset_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: DG_Mask_i
SysReg_DGen_Mask:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DG_Mask_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
then
DG_Mask_i <= Regs_WrDin_r2(32+CINT_BIT_DG_MASK);
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
then
DG_Mask_i <= Regs_WrDin_r2(CINT_BIT_DG_MASK);
else
DG_Mask_i <= DG_Mask_i;
end if;
end if;
end process;
--------------------------------------------------------------------------
-- Data generator status
--
Synch_DG_Status_i:
process ( trn_clk, DG_Reset_i )
begin
if DG_Reset_i = '1' then
DG_Status_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
DG_Status_i(CINT_BIT_DG_MASK) <= DG_Mask_i;
DG_Status_i(CINT_BIT_DG_BUSY) <= DG_is_Running;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Control_i
SysReg_IntGen_Control:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
IG_Control_i <= (OTHERS => '0');
IG_Reset_i <= '1';
IG_Host_Clear_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_CONTROL)='1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
IG_Reset_i <= Command_is_Reset_Hi;
IG_Host_Clear_i <= Command_is_Host_iClr_Hi;
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_CONTROL)='1'
then
IG_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
IG_Reset_i <= Command_is_Reset_Lo;
IG_Host_Clear_i <= Command_is_Host_iClr_Lo;
else
IG_Control_i <= IG_Control_i;
IG_Reset_i <= '0';
IG_Host_Clear_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: IG_Latency_i
SysReg_IntGen_Latency:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
IG_Latency_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset_i='1' then
IG_Latency_i <= (OTHERS => '0');
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
then
IG_Latency_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
IG_Latency_i <= IG_Latency_i;
end if;
end if;
end process;
-- ------------------------------------------------------
-- Protocol CTL interface
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: ctl_rd
Syn_CTL_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_rd_i <= (OTHERS => '0');
ctl_rv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_CTL_CLASS)='1' then
ctl_rd_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
ctl_rv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_CTL_CLASS)='1' then
ctl_rd_i <= Regs_WrDin_r2(32-1 downto 0);
ctl_rv_i <= '1';
else
ctl_rd_i <= ctl_rd_i;
ctl_rv_i <= '0';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Registered: ctl_reset
SysReg_ctl_reset:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_reset_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
then
ctl_reset_i <= Command_is_Reset_Hi;
elsif Regs_WrEn_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
then
ctl_reset_i <= Command_is_Reset_Lo;
else
ctl_reset_i <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: ctl_td
-- ++++++++++++ INT triggering ++++++++++++++++++
Syn_CTL_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_td_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if ctl_tv='1' then
ctl_td_r <= ctl_td;
else
ctl_td_r <= ctl_td_r;
end if;
end if;
end process;
-- ------------------------------------------------------
-- SIMONE USER REGISTER td
-- ------------------------------------------------------
SIMONE_Reg01_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg01_td_i <= (OTHERS => '0');
reg01_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG01)='1' then
reg01_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg01_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG01)='1' then
reg01_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg01_tv_i <= '1';
else
reg01_td_i <= reg01_td_i;
reg01_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg02_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg02_td_i <= (OTHERS => '0');
reg02_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG02)='1' then
reg02_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg02_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG02)='1' then
reg02_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg02_tv_i <= '1';
else
reg02_td_i <= reg02_td_i;
reg02_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg03_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg03_td_i <= (OTHERS => '0');
reg03_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG03)='1' then
reg03_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg03_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG03)='1' then
reg03_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg03_tv_i <= '1';
else
reg03_td_i <= reg03_td_i;
reg03_tv_i <= '0';
end if;
end if;
end process;
--------
SIMONE_Reg04_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg04_td_i <= (OTHERS => '0');
reg04_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG04)='1' then
reg04_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg04_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG04)='1' then
reg04_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg04_tv_i <= '1';
else
reg04_td_i <= reg04_td_i;
reg04_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg05_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg05_td_i <= (OTHERS => '0');
reg05_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG05)='1' then
reg05_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg05_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG05)='1' then
reg05_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg05_tv_i <= '1';
else
reg05_td_i <= reg05_td_i;
reg05_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg06_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg06_td_i <= (OTHERS => '0');
reg06_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG06)='1' then
reg06_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg06_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG06)='1' then
reg06_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg06_tv_i <= '1';
else
reg06_td_i <= reg06_td_i;
reg06_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg07_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg07_td_i <= (OTHERS => '0');
reg07_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG07)='1' then
reg07_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg07_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG07)='1' then
reg07_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg07_tv_i <= '1';
else
reg07_td_i <= reg07_td_i;
reg07_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg08_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg08_td_i <= (OTHERS => '0');
reg08_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG08)='1' then
reg08_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg08_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG08)='1' then
reg08_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg08_tv_i <= '1';
else
reg08_td_i <= reg08_td_i;
reg08_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg09_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg09_td_i <= (OTHERS => '0');
reg09_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG09)='1' then
reg09_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg09_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG09)='1' then
reg09_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg09_tv_i <= '1';
else
reg09_td_i <= reg09_td_i;
reg09_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg10_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg10_td_i <= (OTHERS => '0');
reg10_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG10)='1' then
reg10_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg10_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG10)='1' then
reg10_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg10_tv_i <= '1';
else
reg10_td_i <= reg10_td_i;
reg10_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg11_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg11_td_i <= (OTHERS => '0');
reg11_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG11)='1' then
reg11_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg11_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG11)='1' then
reg11_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg11_tv_i <= '1';
else
reg11_td_i <= reg11_td_i;
reg11_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg12_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg12_td_i <= (OTHERS => '0');
reg12_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG12)='1' then
reg12_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg12_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG12)='1' then
reg12_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg12_tv_i <= '1';
else
reg12_td_i <= reg12_td_i;
reg12_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg13_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg13_td_i <= (OTHERS => '0');
reg13_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG13)='1' then
reg13_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg13_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG13)='1' then
reg13_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg13_tv_i <= '1';
else
reg13_td_i <= reg13_td_i;
reg13_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg14_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg14_td_i <= (OTHERS => '0');
reg14_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG14)='1' then
reg14_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg14_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG14)='1' then
reg14_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg14_tv_i <= '1';
else
reg14_td_i <= reg14_td_i;
reg14_tv_i <= '0';
end if;
end if;
end process;
---------------------------------------------------------------------------
SIMONE_Reg15_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg15_td_i <= (OTHERS => '0');
reg15_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG15)='1' then
reg15_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg15_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG15)='1' then
reg15_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg15_tv_i <= '1';
else
reg15_td_i <= reg15_td_i;
reg15_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg16_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg16_td_i <= (OTHERS => '0');
reg16_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG16)='1' then
reg16_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg16_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG16)='1' then
reg16_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg16_tv_i <= '1';
else
reg16_td_i <= reg16_td_i;
reg16_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg17_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg17_td_i <= (OTHERS => '0');
reg17_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG17)='1' then
reg17_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg17_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG17)='1' then
reg17_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg17_tv_i <= '1';
else
reg17_td_i <= reg17_td_i;
reg17_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg18_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg18_td_i <= (OTHERS => '0');
reg18_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG18)='1' then
reg18_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg18_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG18)='1' then
reg18_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg18_tv_i <= '1';
else
reg18_td_i <= reg18_td_i;
reg18_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg19_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg19_td_i <= (OTHERS => '0');
reg19_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG19)='1' then
reg19_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg19_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG19)='1' then
reg19_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg19_tv_i <= '1';
else
reg19_td_i <= reg19_td_i;
reg19_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg20_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg20_td_i <= (OTHERS => '0');
reg20_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG20)='1' then
reg20_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg20_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG20)='1' then
reg20_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg20_tv_i <= '1';
else
reg20_td_i <= reg20_td_i;
reg20_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg21_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg21_td_i <= (OTHERS => '0');
reg21_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG21)='1' then
reg21_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg21_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG21)='1' then
reg21_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg21_tv_i <= '1';
else
reg21_td_i <= reg21_td_i;
reg21_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg22_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg22_td_i <= (OTHERS => '0');
reg22_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG22)='1' then
reg22_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg22_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG22)='1' then
reg22_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg22_tv_i <= '1';
else
reg22_td_i <= reg22_td_i;
reg22_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg23_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg23_td_i <= (OTHERS => '0');
reg23_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG23)='1' then
reg23_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg23_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG23)='1' then
reg23_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg23_tv_i <= '1';
else
reg23_td_i <= reg23_td_i;
reg23_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg24_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg24_td_i <= (OTHERS => '0');
reg24_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG24)='1' then
reg24_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg24_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG24)='1' then
reg24_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg24_tv_i <= '1';
else
reg24_td_i <= reg24_td_i;
reg24_tv_i <= '0';
end if;
end if;
end process;
SIMONE_Reg25_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg25_td_i <= (OTHERS => '0');
reg25_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_REG25)='1' then
reg25_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
reg25_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_REG25)='1' then
reg25_td_i <= Regs_WrDin_r2(32-1 downto 0);
reg25_tv_i <= '1';
else
reg25_td_i <= reg25_td_i;
reg25_tv_i <= '0';
end if;
end if;
end process;
--------
-- -------------------------------------------------------
-- -------------------------------------------------------
-- SIMONE USER REGISTER rd
-- ------------------------------------------------------
SIMONE_Reg01_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg01_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg01_rv='1' then
reg01_rd_r <= reg01_rd;
else
reg01_rd_r <= reg01_rd_r;
end if;
end if;
end process;
SIMONE_Reg02_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg02_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg02_rv='1' then
reg02_rd_r <= reg02_rd;
else
reg02_rd_r <= reg02_rd_r;
end if;
end if;
end process;
SIMONE_Reg03_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg03_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg03_rv='1' then
reg03_rd_r <= reg03_rd;
else
reg03_rd_r <= reg03_rd_r;
end if;
end if;
end process;
---
SIMONE_Reg04_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg04_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg04_rv='1' then
reg04_rd_r <= reg04_rd;
else
reg04_rd_r <= reg04_rd_r;
end if;
end if;
end process;
SIMONE_Reg05_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg05_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg05_rv='1' then
reg05_rd_r <= reg05_rd;
else
reg05_rd_r <= reg05_rd_r;
end if;
end if;
end process;
SIMONE_Reg06_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg06_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg06_rv='1' then
reg06_rd_r <= reg06_rd;
else
reg06_rd_r <= reg06_rd_r;
end if;
end if;
end process;
SIMONE_Reg07_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg07_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg07_rv='1' then
reg07_rd_r <= reg07_rd;
else
reg07_rd_r <= reg07_rd_r;
end if;
end if;
end process;
SIMONE_Reg08_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg08_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg08_rv='1' then
reg08_rd_r <= reg08_rd;
else
reg08_rd_r <= reg08_rd_r;
end if;
end if;
end process;
SIMONE_Reg09_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg09_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg09_rv='1' then
reg09_rd_r <= reg09_rd;
else
reg09_rd_r <= reg09_rd_r;
end if;
end if;
end process;
SIMONE_Reg10_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg10_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg10_rv='1' then
reg10_rd_r <= reg10_rd;
else
reg10_rd_r <= reg10_rd_r;
end if;
end if;
end process;
SIMONE_Reg11_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg11_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg11_rv='1' then
reg11_rd_r <= reg11_rd;
else
reg11_rd_r <= reg11_rd_r;
end if;
end if;
end process;
SIMONE_Reg12_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg12_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg12_rv='1' then
reg12_rd_r <= reg12_rd;
else
reg12_rd_r <= reg12_rd_r;
end if;
end if;
end process;
SIMONE_Reg13_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg13_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg13_rv='1' then
reg13_rd_r <= reg13_rd;
else
reg13_rd_r <= reg13_rd_r;
end if;
end if;
end process;
SIMONE_Reg14_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg14_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg14_rv='1' then
reg14_rd_r <= reg14_rd;
else
reg14_rd_r <= reg14_rd_r;
end if;
end if;
end process;
----------------------------------------------------------------------------------------
SIMONE_Reg15_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg15_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg15_rv='1' then
reg15_rd_r <= reg15_rd;
else
reg15_rd_r <= reg15_rd_r;
end if;
end if;
end process;
SIMONE_Reg16_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg16_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg16_rv='1' then
reg16_rd_r <= reg16_rd;
else
reg16_rd_r <= reg16_rd_r;
end if;
end if;
end process;
SIMONE_Reg17_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg17_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg17_rv='1' then
reg17_rd_r <= reg17_rd;
else
reg17_rd_r <= reg17_rd_r;
end if;
end if;
end process;
SIMONE_Reg18_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg18_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg18_rv='1' then
reg18_rd_r <= reg18_rd;
else
reg18_rd_r <= reg18_rd_r;
end if;
end if;
end process;
SIMONE_Reg19_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg19_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg19_rv='1' then
reg19_rd_r <= reg19_rd;
else
reg19_rd_r <= reg19_rd_r;
end if;
end if;
end process;
SIMONE_Reg20_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg20_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg20_rv='1' then
reg20_rd_r <= reg20_rd;
else
reg20_rd_r <= reg20_rd_r;
end if;
end if;
end process;
SIMONE_Reg21_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg21_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg21_rv='1' then
reg21_rd_r <= reg21_rd;
else
reg21_rd_r <= reg21_rd_r;
end if;
end if;
end process;
SIMONE_Reg22_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg22_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg22_rv='1' then
reg22_rd_r <= reg22_rd;
else
reg22_rd_r <= reg22_rd_r;
end if;
end if;
end process;
SIMONE_Reg23_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg23_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg23_rv='1' then
reg23_rd_r <= reg23_rd;
else
reg23_rd_r <= reg23_rd_r;
end if;
end if;
end process;
SIMONE_Reg24_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg24_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg24_rv='1' then
reg24_rd_r <= reg24_rd;
else
reg24_rd_r <= reg24_rd_r;
end if;
end if;
end process;
SIMONE_Reg25_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
reg25_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if reg25_rv='1' then
reg25_rd_r <= reg25_rd;
else
reg25_rd_r <= reg25_rd_r;
end if;
end if;
end process;
---
-- -------------------------------------------------------
-- ------------------------------------------------------
-- Protocol DLM interface
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: dlm_td
Syn_DLM_td:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dlm_td_i <= (OTHERS => '0');
dlm_tv_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DLM_CLASS)='1' then
dlm_td_i <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dlm_tv_i <= '1';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DLM_CLASS)='1' then
dlm_td_i <= Regs_WrDin_r2(32-1 downto 0);
dlm_tv_i <= '1';
else
dlm_td_i <= dlm_td_i;
dlm_tv_i <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: dlm_rd
-- ++++++++++++ INT triggering ++++++++++++++++++
Syn_DLM_rd:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dlm_rd_r <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if dlm_rv='1' then
dlm_rd_r <= dlm_rd;
else
dlm_rd_r <= dlm_rd_r;
end if;
end if;
end process;
-- ------------------------------------------------------
-- DMA Upstream Registers
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_PA_i
RxTrn_DMA_us_PA:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_us_PA_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_PA_i <= (OTHERS => '0');
else
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1' then
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1' then
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_PA_i(C_DBUS_WIDTH-1 downto 32);
end if;
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1' then
DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1' then
DMA_us_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_PA_i(32-1 downto 0) <= DMA_us_PA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_HA_i
RxTrn_DMA_us_HA:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_us_HA_i <= (OTHERS => '1');
usHA_is_64b_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_HA_i <= (OTHERS => '1');
usHA_is_64b_i <= '0';
else
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1' then
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(64-1 downto 32);
usHA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1' then
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
usHA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_HA_i(C_DBUS_WIDTH-1 downto 32);
usHA_is_64b_i <= usHA_is_64b_i;
end if;
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1' then
DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1' then
DMA_us_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_HA_i(32-1 downto 0) <= DMA_us_HA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_BDA_i
Syn_Output_DMA_us_BDA:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_us_BDA_i <= (OTHERS =>'0');
usBDA_is_64b_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_BDA_i <= (OTHERS => '0');
usBDA_is_64b_i <= '0';
else
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1' then
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
usBDA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1' then
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
usBDA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto 32);
usBDA_is_64b_i <= usBDA_is_64b_i;
end if;
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1' then
DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1' then
DMA_us_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_us_BDA_i(32-1 downto 0) <= DMA_us_BDA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_us_Length_i
RxTrn_DMA_us_Length:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_us_Length_i <= (OTHERS => '0');
usLeng_Hi19b_True_i <= '0';
usLeng_Lo7b_True_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
DMA_us_Length_i <= (OTHERS => '0');
usLeng_Hi19b_True_i <= '0';
usLeng_Lo7b_True_i <= '0';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1' then
DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(64-1 downto 32);
usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2;
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1' then
DMA_us_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
usLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
usLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2;
else
DMA_us_Length_i <= DMA_us_Length_i;
usLeng_Hi19b_True_i <= usLeng_Hi19b_True_i;
usLeng_Lo7b_True_i <= usLeng_Lo7b_True_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous us_Param_Modified
SynReg_us_Param_Modified:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
us_Param_Modified <= '0';
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i = '1'
or usDMA_Start_i = '1'
or usDMA_Start2_i = '1'
then
us_Param_Modified <= '0';
elsif Regs_WrEn_r2='1' and
(
Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_PAL) ='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_PAL) ='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAH) ='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAH) ='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_HAL) ='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_HAL) ='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
)
then
us_Param_Modified <= '1';
else
us_Param_Modified <= us_Param_Modified;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Control_i
Syn_Output_DMA_us_Control:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_us_Control_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
if Regs_Wr_dma_V_nE_Hi_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified='1'
and usDMA_Stop_i='0'
then
DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified='1'
and usDMA_Stop_i='0'
then
DMA_us_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
elsif Regs_Wr_dma_nV_Hi_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
elsif Regs_Wr_dma_nV_Lo_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_us_Control_i(32-1 downto 0) <= Last_Ctrl_Word_us(32-1 downto 0);
else
DMA_us_Control_i <= DMA_us_Control_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Register: Last_Ctrl_Word_us
Hold_Last_Ctrl_Word_us:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i = '1' then
Last_Ctrl_Word_us <= C_DEF_DMA_CTRL_WORD;
elsif Regs_Wr_dma_V_nE_Hi_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified='1'
and usDMA_Stop_i='0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified='1'
and usDMA_Stop_i='0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
elsif Regs_Wr_dma_V_nE_Hi_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified='1'
and usDMA_Stop_i='0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and us_Param_Modified='1'
and usDMA_Stop_i='0'
then
Last_Ctrl_Word_us(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
else
Last_Ctrl_Word_us <= Last_Ctrl_Word_us;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Start_Stop
Syn_Output_DMA_us_Start_Stop:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
usDMA_Start_i <= '0';
usDMA_Stop_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEnA_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
then
usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not usDMA_Stop_i
and not Command_is_Reset_Hi
and us_Param_Modified
;
usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not Command_is_Reset_Hi
;
elsif Regs_WrEnA_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
then
usDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not usDMA_Stop_i
and not Command_is_Reset_Lo
and us_Param_Modified
;
usDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not Command_is_Reset_Lo
;
elsif Regs_WrEnA_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
and us_Param_Modified;
usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnA_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
usDMA_Start_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END)
and us_Param_Modified;
usDMA_Stop_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif usDMA_Cmd_Ack='1'
then
usDMA_Start_i <= '0';
usDMA_Stop_i <= usDMA_Stop_i;
else
usDMA_Start_i <= usDMA_Start_i;
usDMA_Stop_i <= usDMA_Stop_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_us_Start2_Stop2
Syn_Output_DMA_us_Start2_Stop2:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i='1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= '0';
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
then
usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
then
usDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
usDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
then
usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
usDMA_Start2_i <= not Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
usDMA_Stop2_i <= Last_Ctrl_Word_us(CINT_BIT_DMA_CTRL_END);
elsif usDMA_Cmd_Ack='1' then
usDMA_Start2_i <= '0';
usDMA_Stop2_i <= usDMA_Stop2_i;
else
usDMA_Start2_i <= usDMA_Start2_i;
usDMA_Stop2_i <= usDMA_Stop2_i;
end if;
end if;
end process;
-- ------------------------------------------------------
-- DMA Downstream Registers
-- ------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Registered: DMA_ds_PA_i
RxTrn_DMA_ds_PA:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_ds_PA_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_PA_i <= (OTHERS => '0');
else
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1' then
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1' then
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto 32);
end if;
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1' then
DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1' then
DMA_ds_PA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_PA_i(32-1 downto 0) <= DMA_ds_PA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Registered: DMA_ds_HA_i
RxTrn_DMA_ds_HA:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_ds_HA_i <= (OTHERS => '1');
dsHA_is_64b_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_HA_i <= (OTHERS => '1');
dsHA_is_64b_i <= '0';
else
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1' then
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsHA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1' then
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
dsHA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto 32);
dsHA_is_64b_i <= dsHA_is_64b_i;
end if;
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1' then
DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1' then
DMA_ds_HA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_HA_i(32-1 downto 0) <= DMA_ds_HA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_BDA_i
Syn_Output_DMA_ds_BDA:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_ds_BDA_i <= (OTHERS =>'0');
dsBDA_is_64b_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_BDA_i <= (OTHERS => '0');
dsBDA_is_64b_i <= '0';
else
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1' then
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsBDA_is_64b_i <= WrDin_r2_not_Zero_Hi;
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1' then
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= Regs_WrDin_r2(32-1 downto 0);
dsBDA_is_64b_i <= WrDin_r2_not_Zero_Lo;
else
DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32) <= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto 32);
dsBDA_is_64b_i <= dsBDA_is_64b_i;
end if;
if Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1' then
DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1' then
DMA_ds_BDA_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
else
DMA_ds_BDA_i(32-1 downto 0) <= DMA_ds_BDA_i(32-1 downto 0);
end if;
end if;
end if;
end process;
-- Synchronous Registered: DMA_ds_Length_i
RxTrn_DMA_ds_Length:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_ds_Length_i <= (OTHERS => '0');
dsLeng_Hi19b_True_i <= '0';
dsLeng_Lo7b_True_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
DMA_ds_Length_i <= (OTHERS => '0');
dsLeng_Hi19b_True_i <= '0';
dsLeng_Lo7b_True_i <= '0';
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1' then
DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 32);
dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_hq_r2;
dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_hq_r2;
elsif Regs_WrEn_r2='1' and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1' then
DMA_ds_Length_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 0);
dsLeng_Hi19b_True_i <= Regs_WrDin_Hi19b_True_lq_r2;
dsLeng_Lo7b_True_i <= Regs_WrDin_Lo7b_True_lq_r2;
else
DMA_ds_Length_i <= DMA_ds_Length_i;
dsLeng_Hi19b_True_i <= dsLeng_Hi19b_True_i;
dsLeng_Lo7b_True_i <= dsLeng_Lo7b_True_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous ds_Param_Modified
SynReg_ds_Param_Modified:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ds_Param_Modified <= '0';
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i = '1'
or dsDMA_Start_i = '1'
or dsDMA_Start2_i = '1'
then
ds_Param_Modified <= '0';
elsif Regs_WrEn_r2='1' and
(
-- Reg_WrMuxer(CINT_ADDR_DMA_DS_PAH) ='1'
-- or
Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_PAL) ='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_PAL) ='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAH) ='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAH) ='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_HAL) ='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_HAL) ='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
or Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
)
then
ds_Param_Modified <= '1';
else
ds_Param_Modified <= ds_Param_Modified;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Control_i
Syn_Output_DMA_ds_Control:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_ds_Control_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
if Regs_Wr_dma_V_nE_Hi_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
and ds_Param_Modified='1'
and dsDMA_Stop_i='0'
then
DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32)& X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and ds_Param_Modified='1'
and dsDMA_Stop_i='0'
then
DMA_ds_Control_i(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8)& X"00";
elsif Regs_Wr_dma_nV_Hi_r2='1'
and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
DMA_ds_Control_i <= Last_Ctrl_Word_ds;
else
DMA_ds_Control_i <= DMA_ds_Control_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous Register: Last_Ctrl_Word_ds
Hold_Last_Ctrl_Word_ds:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i = '1' then
Last_Ctrl_Word_ds <= C_DEF_DMA_CTRL_WORD;
elsif Regs_Wr_dma_V_nE_Hi_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)='0'
and ds_Param_Modified='1'
and dsDMA_Stop_i='0'
then
Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(C_DBUS_WIDTH-1 downto 8+32) & X"00";
elsif Regs_Wr_dma_V_nE_Lo_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)='0'
and ds_Param_Modified='1'
and dsDMA_Stop_i='0'
then
Last_Ctrl_Word_ds(32-1 downto 0) <= Regs_WrDin_r2(32-1 downto 8) & X"00";
else
Last_Ctrl_Word_ds <= Last_Ctrl_Word_ds;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Start_Stop
Syn_Output_DMA_ds_Start_Stop:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dsDMA_Start_i <= '0';
dsDMA_Stop_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrEnA_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
then
dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not dsDMA_Stop_i
and not Command_is_Reset_Hi
and ds_Param_Modified
;
dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32)
and not Command_is_Reset_Hi
;
elsif Regs_WrEnA_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
then
dsDMA_Start_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not dsDMA_Stop_i
and not Command_is_Reset_Lo
and ds_Param_Modified
;
dsDMA_Stop_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END)
and not Command_is_Reset_Lo
;
elsif Regs_WrEnA_r2='1'
and (Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1' or Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1')
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
then
dsDMA_Start_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END)
and ds_Param_Modified
;
dsDMA_Stop_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif dsDMA_Cmd_Ack='1'
then
dsDMA_Start_i <= '0';
dsDMA_Stop_i <= dsDMA_Stop_i;
else
dsDMA_Start_i <= dsDMA_Start_i;
dsDMA_Stop_i <= dsDMA_Stop_i;
end if;
end if;
end process;
-- -------------------------------------------------------
-- Synchronous output: DMA_ds_Start2_Stop2
Syn_Output_DMA_ds_Start2_Stop2:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i='1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= '0';
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='1'
then
dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END+32) and not Command_is_Reset_Hi;
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='1'
then
dsDMA_Start2_i <= not Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
dsDMA_Stop2_i <= Regs_WrDin_r2(CINT_BIT_DMA_CTRL_END) and not Command_is_Reset_Lo;
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)='0'
then
dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif Regs_WrEnB_r2='1'
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)='0'
then
dsDMA_Start2_i <= not Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
dsDMA_Stop2_i <= Last_Ctrl_Word_ds(CINT_BIT_DMA_CTRL_END);
elsif dsDMA_Cmd_Ack='1' then
dsDMA_Start2_i <= '0';
dsDMA_Stop2_i <= dsDMA_Stop2_i;
else
dsDMA_Start2_i <= dsDMA_Start2_i;
dsDMA_Stop2_i <= dsDMA_Stop2_i;
end if;
end if;
end process;
------------------------------------------------------------------------
-- Reset signals --
------------------------------------------------------------------------
-- --------------------------------------
-- Identification: Command_is_Reset
--
Synch_Capture_Command_is_Reset:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Command_is_Reset_Hi <= '0';
Command_is_Reset_Lo <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_CHANNEL_RST_BITS then
Command_is_Reset_Hi <= '1';
else
Command_is_Reset_Hi <= '0';
end if;
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_CHANNEL_RST_BITS then
Command_is_Reset_Lo <= '1';
else
Command_is_Reset_Lo <= '0';
end if;
end if;
end process;
-- --------------------------------------
-- Identification: Command_is_Host_iClr
--
Synch_Capture_Command_is_Host_iClr:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Command_is_Host_iClr_Hi <= '0';
Command_is_Host_iClr_Lo <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1+32 downto 32)=C_HOST_ICLR_BITS then
Command_is_Host_iClr_Hi <= '1';
else
Command_is_Host_iClr_Hi <= '0';
end if;
if Regs_WrDin_r1(C_FEAT_BITS_WIDTH-1 downto 0)=C_HOST_ICLR_BITS then
Command_is_Host_iClr_Lo <= '1';
else
Command_is_Host_iClr_Lo <= '0';
end if;
end if;
end process;
-------------------------------------------
-- Synchronous output: usDMA_Channel_Rst_i
--
Syn_Output_usDMA_Channel_Rst:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
usDMA_Channel_Rst_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
usDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_US_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
and Command_is_Reset_Hi
)
or (Regs_Wr_dma_V_LO_r2
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_US_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
and Command_is_Reset_Lo
)
;
end if;
end process;
-------------------------------------------
-- Synchronous output: dsDMA_Channel_Rst_i
--
Syn_Output_dsDMA_Channel_Rst:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
dsDMA_Channel_Rst_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
dsDMA_Channel_Rst_i <= (Regs_Wr_dma_V_Hi_r2
and Reg_WrMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID+32)
and Command_is_Reset_Hi
)
or
(Regs_Wr_dma_V_Lo_r2
and Reg_WrMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)
-- and Regs_WrDin_r2(CINT_BIT_DMA_CTRL_VALID)
and Command_is_Reset_Lo
)
;
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: MRd_Channel_Rst_i
--
Syn_Output_MRd_Channel_Rst:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
MRd_Channel_Rst_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
MRd_Channel_Rst_i <= Regs_WrEn_r2
and (
(Reg_WrMuxer_Hi(CINT_ADDR_MRD_CTRL)
and Command_is_Reset_Hi)
or
(Reg_WrMuxer_Lo(CINT_ADDR_MRD_CTRL)
and Command_is_Reset_Lo)
)
;
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: Tx_Reset_i
--
Syn_Output_Tx_Reset:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Tx_Reset_i <= '1';
elsif trn_clk'event and trn_clk = '1' then
Tx_Reset_i <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_TX_CTRL)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_TX_CTRL)
and Command_is_Reset_Lo))
;
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: eb_FIFO_Rst_i
--
Syn_Output_eb_FIFO_Rst:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
eb_FIFO_Rst_i <= '1';
eb_FIFO_Rst_b3 <= '1';
eb_FIFO_Rst_b2 <= '1';
eb_FIFO_Rst_b1 <= '1';
elsif trn_clk'event and trn_clk = '1' then
eb_FIFO_Rst_i <= eb_FIFO_Rst_b1 or eb_FIFO_Rst_b2 or eb_FIFO_Rst_b3;
eb_FIFO_Rst_b3 <= eb_FIFO_Rst_b2;
eb_FIFO_Rst_b2 <= eb_FIFO_Rst_b1;
eb_FIFO_Rst_b1 <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_EB_STACON)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_EB_STACON)
and Command_is_Reset_Lo))
;
end if;
end process;
-- -----------------------------------------------
-- Synchronous output: protocol_rst
--
-- !!! reset by trn_reset_n !!!
--
Syn_Output_protocol_rst:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
protocol_rst_i <= '1';
protocol_rst_b1 <= '1';
protocol_rst_b2 <= '1';
elsif trn_clk'event and trn_clk = '1' then
protocol_rst_i <= protocol_rst_b1 or protocol_rst_b2;
protocol_rst_b1 <= protocol_rst_b2;
protocol_rst_b2 <= Regs_WrEn_r2
and ((Reg_WrMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)
and Command_is_Reset_Hi)
or (Reg_WrMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)
and Command_is_Reset_Lo))
;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Calculation: DMA_us_Transf_Bytes
--
Syn_Calc_DMA_us_Transf_Bytes:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_us_Transf_Bytes_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if usDMA_Channel_Rst_i='1' then
DMA_us_Transf_Bytes_i <= (OTHERS=>'0');
elsif us_DMA_Bytes_Add='1' then
DMA_us_Transf_Bytes_i(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0)
+ us_DMA_Bytes;
else
DMA_us_Transf_Bytes_i <= DMA_us_Transf_Bytes_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Calculation: DMA_ds_Transf_Bytes
--
Syn_Calc_DMA_ds_Transf_Bytes:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
DMA_ds_Transf_Bytes_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if dsDMA_Channel_Rst_i='1' then
DMA_ds_Transf_Bytes_i <= (OTHERS=>'0');
elsif ds_DMA_Bytes_Add='1' then
DMA_ds_Transf_Bytes_i(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0)
+ ds_DMA_Bytes;
else
DMA_ds_Transf_Bytes_i <= DMA_ds_Transf_Bytes_i;
end if;
end if;
end process;
---- -------------------------------------------------------
---- Synchronous Registers: icap_Write_i
-- RxTrn_icap_Write:
-- process ( trn_clk, trn_lnk_up_n)
-- begin
-- if trn_lnk_up_n = '1' then
-- icap_CLK <= '0';
-- icap_I <= (OTHERS => '0');
-- icap_Write <= '1';
-- icap_CE <= '1';
-- FSM_icap <= icapST_Reset;
--
-- elsif trn_clk'event and trn_clk = '1' then
--
-- case FSM_icap is
--
-- when icapST_Reset =>
-- icap_CLK <= '0';
-- icap_I <= (OTHERS => '0');
-- icap_Write <= '1';
-- icap_CE <= '1';
-- FSM_icap <= icapST_Idle;
--
-- when icapST_Idle =>
--
-- if Regs_WrEn_r2='1' and Reg_WrMuxer(CINT_ADDR_ICAP)='1' then
-- icap_CLK <= '1';
-- icap_I <= Regs_WrDin_r2;
-- icap_Write <= '0';
-- icap_CE <= '0';
-- FSM_icap <= icapST_Access;
-- elsif Reg_RdMuxer(CINT_ADDR_ICAP)='1' then
-- icap_CLK <= '1';
-- icap_I <= icap_I;
-- icap_Write <= '1';
-- icap_CE <= '0';
-- FSM_icap <= icapST_Access;
-- else
-- icap_CLK <= icap_CLK;
-- icap_I <= icap_I;
-- icap_Write <= icap_Write;
-- icap_CE <= icap_CE;
-- FSM_icap <= icapST_Idle;
-- end if;
--
--
-- when icapST_Access =>
-- icap_CLK <= '1';
-- icap_I <= icap_I;
-- icap_Write <= icap_Write;
-- icap_CE <= icap_CE;
-- FSM_icap <= icapST_Abort;
--
-- when icapST_Abort =>
-- icap_CLK <= '0';
-- icap_I <= icap_I;
-- icap_Write <= icap_Write;
-- icap_CE <= icap_CE;
-- FSM_icap <= icapST_Idle;
--
-- when Others =>
-- icap_CLK <= '0';
-- icap_I <= (OTHERS => '0');
-- icap_Write <= '1';
-- icap_CE <= '1';
-- FSM_icap <= icapST_Idle;
--
-- end case;
--
-- end if;
-- end process;
--
----------------------------------------------------------
--------------- Tx reading registers -------------------
----------------------------------------------------------
----------------------------------------------------------
-- Synch Register: Read Selection
--
Tx_DMA_Reg_RdMuxer:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Reg_RdMuxer_Hi <= (Others =>'0');
Reg_RdMuxer_Lo <= (Others =>'0');
elsif trn_clk'event and trn_clk = '1' then
FOR k IN 0 TO C_NUM_OF_ADDRESSES-1 LOOP
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k, C_DECODE_BIT_BOT-2)
and Regs_RdAddr_i(2-1 downto 0)="00"
then
Reg_RdMuxer_Hi(k) <= '1';
else
Reg_RdMuxer_Hi(k) <= '0';
end if;
END LOOP;
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_ALL_ONES(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=C_ALL_ONES(C_DECODE_BIT_BOT-1 downto 2)
and Regs_RdAddr_i(2-1 downto 0)="00"
then
Reg_RdMuxer_Lo(0) <= '1';
else
Reg_RdMuxer_Lo(0) <= '0';
end if;
FOR k IN 1 TO C_NUM_OF_ADDRESSES-1 LOOP
if Regs_RdAddr_i(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)= C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT)
and Regs_RdAddr_i(C_DECODE_BIT_BOT-1 downto 2)=CONV_STD_LOGIC_VECTOR(k-1, C_DECODE_BIT_BOT-2)
and Regs_RdAddr_i(2-1 downto 0)="00"
then
Reg_RdMuxer_Lo(k) <= '1';
else
Reg_RdMuxer_Lo(k) <= '0';
end if;
END LOOP;
end if;
end process;
----------------------------------------------------------
-- Synch Register: CTL_TTake
--
Syn_CTL_ttake:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
ctl_ttake_i <= '0';
ctl_t_read_Hi_r1 <= '0';
ctl_t_read_Lo_r1 <= '0';
CTL_read_counter <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
ctl_t_read_Hi_r1 <= Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS);
ctl_t_read_Lo_r1 <= Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS);
ctl_ttake_i <= (Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Hi_r1)
or (Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS) and not ctl_t_read_Lo_r1)
;
if ctl_reset_i='1' then
CTL_read_counter <= (OTHERS=>'0');
else
CTL_read_counter <= CTL_read_counter + ctl_ttake_i;
end if;
end if;
end process;
----------------------------------------------------------
-- Synch Register: class_CTL_Status
--
Syn_class_CTL_Status:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
class_CTL_Status_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
class_CTL_Status_i(C_DBUS_WIDTH/2-1 downto 0) <= ctl_status;
end if;
end process;
-- -------------------------------------------------------
--
Sys_Int_Status_i <= (
CPOLL_BIT_DLMTOUT_IN_ISR => DLMTOUT_irq , --12 + 16
CPOLL_BIT_CTLTOUT_IN_ISR => CTLTOUT_irq , --11 + 16
CPOLL_BIT_DAQTOUT_IN_ISR => DAQTOUT_irq , --10 + 16
CPOLL_BIT_DLM_IN_ISR => DLM_irq , --8 + 16
CPOLL_BIT_CTL_IN_ISR => CTL_irq , --7 + 16
CPOLL_BIT_DAQ_IN_ISR => DAQ_irq , --6 + 16
CPOLL_BIT_DSTOUT_IN_ISR => DMA_ds_Tout , --5 + 16
CPOLL_BIT_USTOUT_IN_ISR => DMA_us_Tout , --4 + 16
CPOLL_BIT_INTGEN_IN_ISR => IG_Asserting, --2 + 16
CPOLL_BIT_DS_DONE_IN_ISR => DMA_ds_Done , --1 + 16
CPOLL_BIT_US_DONE_IN_ISR => DMA_us_Done , --0 + 16
CINT_BIT_DSTOUT_IN_ISR => DMA_ds_Tout , --5
CINT_BIT_USTOUT_IN_ISR => DMA_us_Tout , --4
CINT_BIT_INTGEN_IN_ISR => IG_Asserting, --2
CINT_BIT_DS_DONE_IN_ISR => DMA_ds_Done , --1
CINT_BIT_US_DONE_IN_ISR => DMA_us_Done , --0
OTHERS => '0'
);
--------------------------------------------------------------------------
-- Upstream Registers
--------------------------------------------------------------------------
-- Peripheral Address Start point
DMA_us_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAH)='1'
else (Others=>'0');
DMA_us_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_PAL)='1'
else (Others=>'0');
-- Host Address Start point
DMA_us_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAH)='1'
else (Others=>'0');
DMA_us_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_HAL)='1'
else (Others=>'0');
-- Next Descriptor Address
DMA_us_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAH)='1'
else (Others=>'0');
DMA_us_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_BDAL)='1'
else (Others=>'0');
-- Length
DMA_us_Length_o_Hi(32-1 downto 0)
<= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_LENG)='1'
else (Others=>'0');
-- Control word
DMA_us_Control_o_Hi(32-1 downto 0)
<= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_CTRL)='1'
else (Others=>'0');
-- Status (Read only)
DMA_us_Status_o_Hi(32-1 downto 0)
<= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_US_STA)='1'
else (Others=>'0');
-- Tranferred bytes (Read only)
DMA_us_Transf_Bytes_o_Hi(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_US_TRANSF_BC)='1'
else (Others=>'0');
-- Peripheral Address Start point
DMA_us_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAH)='1'
else (Others=>'0');
DMA_us_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_PAL)='1'
else (Others=>'0');
-- Host Address Start point
DMA_us_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAH)='1'
else (Others=>'0');
DMA_us_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_HAL)='1'
else (Others=>'0');
-- Next Descriptor Address
DMA_us_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_us_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAH)='1'
else (Others=>'0');
DMA_us_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_us_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_BDAL)='1'
else (Others=>'0');
-- Length
DMA_us_Length_o_Lo(32-1 downto 0)
<= DMA_us_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_LENG)='1'
else (Others=>'0');
-- Control word
DMA_us_Control_o_Lo(32-1 downto 0)
<= DMA_us_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_CTRL)='1'
else (Others=>'0');
-- Status (Read only)
DMA_us_Status_o_Lo(32-1 downto 0)
<= DMA_us_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_US_STA)='1'
else (Others=>'0');
-- Tranferred bytes (Read only)
DMA_us_Transf_Bytes_o_Lo(32-1 downto 0)
<= DMA_us_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_US_TRANSF_BC)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- Downstream Registers
--------------------------------------------------------------------------
-- Peripheral Address Start point
DMA_ds_PA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAH)='1'
else (Others=>'0');
DMA_ds_PA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_PAL)='1'
else (Others=>'0');
-- Host Address Start point
DMA_ds_HA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAH)='1'
else (Others=>'0');
DMA_ds_HA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_HAL)='1'
else (Others=>'0');
-- Next Descriptor Address
DMA_ds_BDA_o_Hi(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAH)='1'
else (Others=>'0');
DMA_ds_BDA_o_Hi(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_BDAL)='1'
else (Others=>'0');
-- Length
DMA_ds_Length_o_Hi(32-1 downto 0)
<= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_LENG)='1'
else (Others=>'0');
-- Control word
DMA_ds_Control_o_Hi(32-1 downto 0)
<= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_CTRL)='1'
else (Others=>'0');
-- Status (Read only)
DMA_ds_Status_o_Hi(32-1 downto 0)
<= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DMA_DS_STA)='1'
else (Others=>'0');
-- Tranferred bytes (Read only)
DMA_ds_Transf_Bytes_o_Hi(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DS_TRANSF_BC)='1'
else (Others=>'0');
-- Peripheral Address Start point
DMA_ds_PA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_PA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAH)='1'
else (Others=>'0');
DMA_ds_PA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_PA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_PAL)='1'
else (Others=>'0');
-- Host Address Start point
DMA_ds_HA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_HA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAH)='1'
else (Others=>'0');
DMA_ds_HA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_HA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_HAL)='1'
else (Others=>'0');
-- Next Descriptor Address
DMA_ds_BDA_o_Lo(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
<= DMA_ds_BDA_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAH)='1'
else (Others=>'0');
DMA_ds_BDA_o_Lo(C_DBUS_WIDTH/2-1 downto 0)
<= DMA_ds_BDA_i(C_DBUS_WIDTH/2-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_BDAL)='1'
else (Others=>'0');
-- Length
DMA_ds_Length_o_Lo(32-1 downto 0)
<= DMA_ds_Length_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_LENG)='1'
else (Others=>'0');
-- Control word
DMA_ds_Control_o_Lo(32-1 downto 0)
<= DMA_ds_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_CTRL)='1'
else (Others=>'0');
-- Status (Read only)
DMA_ds_Status_o_Lo(32-1 downto 0)
<= DMA_ds_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DMA_DS_STA)='1'
else (Others=>'0');
-- Tranferred bytes (Read only)
DMA_ds_Transf_Bytes_o_Lo(32-1 downto 0)
<= DMA_ds_Transf_Bytes_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DS_TRANSF_BC)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- CTL
--------------------------------------------------------------------------
ctl_td_o_Hi(32-1 downto 0)
<= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CTL_CLASS)='1'
else (Others=>'0');
ctl_td_o_Lo(32-1 downto 0)
<= ctl_td_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CTL_CLASS)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- DLM
--------------------------------------------------------------------------
dlm_rd_o_Hi(32-1 downto 0)
<= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DLM_CLASS)='1'
else (Others=>'0');
dlm_rd_o_Lo(32-1 downto 0)
<= dlm_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DLM_CLASS)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- SIMONE USER REGISTERs
--------------------------------------------------------------------------
reg01_rd_o_Hi(32-1 downto 0)
<= reg01_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG01)='1'
else (Others=>'0');
reg01_rd_o_Lo(32-1 downto 0)
<= reg01_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG01)='1'
else (Others=>'0');
reg02_rd_o_Hi(32-1 downto 0)
<= reg02_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG02)='1'
else (Others=>'0');
reg02_rd_o_Lo(32-1 downto 0)
<= reg02_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG02)='1'
else (Others=>'0');
reg03_rd_o_Hi(32-1 downto 0)
<= reg03_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG03)='1'
else (Others=>'0');
reg03_rd_o_Lo(32-1 downto 0)
<= reg03_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG03)='1'
else (Others=>'0');
reg04_rd_o_Hi(32-1 downto 0)
<= reg04_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG04)='1'
else (Others=>'0');
reg04_rd_o_Lo(32-1 downto 0)
<= reg04_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG04)='1'
else (Others=>'0');
reg05_rd_o_Hi(32-1 downto 0)
<= reg05_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG05)='1'
else (Others=>'0');
reg05_rd_o_Lo(32-1 downto 0)
<= reg05_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG05)='1'
else (Others=>'0');
reg06_rd_o_Hi(32-1 downto 0)
<= reg06_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG06)='1'
else (Others=>'0');
reg06_rd_o_Lo(32-1 downto 0)
<= reg06_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG06)='1'
else (Others=>'0');
reg07_rd_o_Hi(32-1 downto 0)
<= reg07_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG07)='1'
else (Others=>'0');
reg07_rd_o_Lo(32-1 downto 0)
<= reg07_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG07)='1'
else (Others=>'0');
reg08_rd_o_Hi(32-1 downto 0)
<= reg08_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG08)='1'
else (Others=>'0');
reg08_rd_o_Lo(32-1 downto 0)
<= reg08_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG08)='1'
else (Others=>'0');
reg09_rd_o_Hi(32-1 downto 0)
<= reg09_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG09)='1'
else (Others=>'0');
reg09_rd_o_Lo(32-1 downto 0)
<= reg09_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG09)='1'
else (Others=>'0');
reg10_rd_o_Hi(32-1 downto 0)
<= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG10)='1'
else (Others=>'0');
reg10_rd_o_Lo(32-1 downto 0)
<= reg10_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG10)='1'
else (Others=>'0');
reg11_rd_o_Hi(32-1 downto 0)
<= reg11_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG11)='1'
else (Others=>'0');
reg11_rd_o_Lo(32-1 downto 0)
<= reg11_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG11)='1'
else (Others=>'0');
reg12_rd_o_Hi(32-1 downto 0)
<= reg12_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG12)='1'
else (Others=>'0');
reg12_rd_o_Lo(32-1 downto 0)
<= reg12_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG12)='1'
else (Others=>'0');
reg13_rd_o_Hi(32-1 downto 0)
<= reg13_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG13)='1'
else (Others=>'0');
reg13_rd_o_Lo(32-1 downto 0)
<= reg13_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG13)='1'
else (Others=>'0');
reg14_rd_o_Hi(32-1 downto 0)
<= reg14_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG14)='1'
else (Others=>'0');
reg14_rd_o_Lo(32-1 downto 0)
<= reg14_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG14)='1'
else (Others=>'0');
reg15_rd_o_Hi(32-1 downto 0)
<= reg15_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG15)='1'
else (Others=>'0');
reg15_rd_o_Lo(32-1 downto 0)
<= reg15_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG15)='1'
else (Others=>'0');
reg16_rd_o_Hi(32-1 downto 0)
<= reg16_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG16)='1'
else (Others=>'0');
reg16_rd_o_Lo(32-1 downto 0)
<= reg16_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG16)='1'
else (Others=>'0');
reg17_rd_o_Hi(32-1 downto 0)
<= reg17_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG17)='1'
else (Others=>'0');
reg17_rd_o_Lo(32-1 downto 0)
<= reg17_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG17)='1'
else (Others=>'0');
reg18_rd_o_Hi(32-1 downto 0)
<= reg18_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG18)='1'
else (Others=>'0');
reg18_rd_o_Lo(32-1 downto 0)
<= reg18_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG18)='1'
else (Others=>'0');
reg19_rd_o_Hi(32-1 downto 0)
<= reg19_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG19)='1'
else (Others=>'0');
reg19_rd_o_Lo(32-1 downto 0)
<= reg19_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG19)='1'
else (Others=>'0');
reg20_rd_o_Hi(32-1 downto 0)
<= reg20_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG20)='1'
else (Others=>'0');
reg20_rd_o_Lo(32-1 downto 0)
<= reg20_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG20)='1'
else (Others=>'0');
reg21_rd_o_Hi(32-1 downto 0)
<= reg21_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG21)='1'
else (Others=>'0');
reg21_rd_o_Lo(32-1 downto 0)
<= reg21_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG21)='1'
else (Others=>'0');
reg22_rd_o_Hi(32-1 downto 0)
<= reg22_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG22)='1'
else (Others=>'0');
reg22_rd_o_Lo(32-1 downto 0)
<= reg22_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG22)='1'
else (Others=>'0');
reg23_rd_o_Hi(32-1 downto 0)
<= reg23_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG23)='1'
else (Others=>'0');
reg23_rd_o_Lo(32-1 downto 0)
<= reg23_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG23)='1'
else (Others=>'0');
reg24_rd_o_Hi(32-1 downto 0)
<= reg24_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG24)='1'
else (Others=>'0');
reg24_rd_o_Lo(32-1 downto 0)
<= reg24_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG24)='1'
else (Others=>'0');
reg25_rd_o_Hi(32-1 downto 0)
<= reg25_rd_r(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_REG25)='1'
else (Others=>'0');
reg25_rd_o_Lo(32-1 downto 0)
<= reg25_rd_r(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_REG25)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- System Interrupt Status
--------------------------------------------------------------------------
Sys_Int_Status_o_Hi(32-1 downto 0)
<= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_STAT)='1'
else (Others=>'0');
Sys_Int_Enable_o_Hi(32-1 downto 0)
<= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IRQ_EN)='1'
else (Others=>'0');
Sys_Int_Status_o_Lo(32-1 downto 0)
<= (Sys_Int_Status_i(32-1 downto 0) and Sys_Int_Enable_i(32-1 downto 0)) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_STAT)='1'
else (Others=>'0');
Sys_Int_Enable_o_Lo(32-1 downto 0)
<= Sys_Int_Enable_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IRQ_EN)='1'
else (Others=>'0');
--debug_in_1i <= Sys_Int_Status_i(32-1 downto 0);
--debug_in_2i <= Sys_Int_Enable_i(32-1 downto 0);
--debug_in_3i <= "0000000000000000000000000000000" & DAQ_irq;
debug_in_1i <= "0000000000000000000000000000000" & DMA_ds_Done;
debug_in_2i <= "0000000000000000000000000000000" & DMA_us_Done;
debug_in_3i <= "0000000000000000" & Sys_IRQ_i(15 downto 0);
debug_in_4i <= Sys_Int_Enable_i(32-1 downto 0);
-- ----------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------------
Gen_IG_Read: if IMP_INT_GENERATOR generate
--------------------------------------------------------------------------
-- Interrupt Generator Latency
--------------------------------------------------------------------------
IG_Latency_o_Hi(32-1 downto 0)
<= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_LATENCY)='1'
else (Others=>'0');
IG_Latency_o_Lo(32-1 downto 0)
<= IG_Latency_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_LATENCY)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- Interrupt Generator Statistics
--------------------------------------------------------------------------
IG_Num_Assert_o_Hi(32-1 downto 0)
<= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_ASSERT)='1'
else (Others=>'0');
IG_Num_Deassert_o_Hi(32-1 downto 0)
<= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_IG_NUM_DEASSERT)='1'
else (Others=>'0');
IG_Num_Assert_o_Lo(32-1 downto 0)
<= IG_Num_Assert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_ASSERT)='1'
else (Others=>'0');
IG_Num_Deassert_o_Lo(32-1 downto 0)
<= IG_Num_Deassert_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_IG_NUM_DEASSERT)='1'
else (Others=>'0');
end generate;
NotGen_IG_Read: if not IMP_INT_GENERATOR generate
IG_Latency_o_Hi(32-1 downto 0) <= (Others=>'0');
IG_Latency_o_Lo(32-1 downto 0) <= (Others=>'0');
IG_Num_Assert_o_Hi(32-1 downto 0) <= (Others=>'0');
IG_Num_Deassert_o_Hi(32-1 downto 0) <= (Others=>'0');
IG_Num_Assert_o_Lo(32-1 downto 0) <= (Others=>'0');
IG_Num_Deassert_o_Lo(32-1 downto 0) <= (Others=>'0');
end generate;
--------------------------------------------------------------------------
-- System Error
--------------------------------------------------------------------------
Synch_Sys_Error_i:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Sys_Error_i <= (OTHERS => '0');
eb_FIFO_OverWritten <= '0';
elsif trn_clk'event and trn_clk = '1' then
Sys_Error_i(CINT_BIT_TX_TOUT_IN_SER) <= Tx_TimeOut;
Sys_Error_i(CINT_BIT_EB_TOUT_IN_SER) <= Tx_eb_TimeOut;
Sys_Error_i(CINT_BIT_EB_OVERWRITTEN) <= eb_FIFO_OverWritten;
-- !!!!!!!!!!!!!! capture eb_FIFO overflow, temp cleared by MRd_Channel_Rst_i
eb_FIFO_OverWritten <= (not MRd_Channel_Rst_i) and (eb_FIFO_ow or eb_FIFO_OverWritten);
end if;
end process;
--------------------------------------------------------------------------
-- General Status and Control
--------------------------------------------------------------------------
Synch_General_Status_i:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
General_Status_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
General_Status_i(32-1 downto 32-16)
<= cfg_dcommand;
General_Status_i(CINT_BIT_LWIDTH_IN_GSR_TOP downto CINT_BIT_LWIDTH_IN_GSR_BOT)
<= pcie_link_width;
General_Status_i(CINT_BIT_ICAP_BUSY_IN_GSR)
<= icap_Busy;
General_Status_i(CINT_BIT_DG_AVAIL_IN_GSR)
<= DG_is_Available;
General_Status_i(CINT_BIT_LINK_ACT_IN_GSR+1 downto CINT_BIT_LINK_ACT_IN_GSR)
<= protocol_link_act;
-- General_Status_i(8) <= CTL_read_counter(6-1); ---- DEBUG !!!
end if;
end process;
Sys_Error_o_Hi(32-1 downto 0)
<= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ERROR)='1'
else (Others=>'0');
General_Status_o_Hi(32-1 downto 0)
<= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_STATUS)='1'
else (Others=>'0');
General_Control_o_Hi(32-1 downto 0)
<= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_CONTROL)='1'
else (Others=>'0');
Sys_Error_o_Lo(32-1 downto 0)
<= Sys_Error_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ERROR)='1'
else (Others=>'0');
General_Status_o_Lo(32-1 downto 0)
<= General_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_STATUS)='1'
else (Others=>'0');
General_Control_o_Lo(32-1 downto 0)
<= General_Control_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_CONTROL)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- ICAP
--------------------------------------------------------------------------
icap_O_o_Hi(32-1 downto 0)
<= icap_O(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_ICAP)='1'
else (Others=>'0');
icap_O_o_Lo(32-1 downto 0)
<= icap_O(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_ICAP)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- FIFO Statuses (read only)
--------------------------------------------------------------------------
eb_FIFO_Status_o_Hi(32-1 downto 0)
<= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_EB_STACON)='1'
else (Others=>'0');
eb_FIFO_Status_o_Lo(32-1 downto 0)
<= eb_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_EB_STACON)='1'
else (Others=>'0');
H2B_FIFO_Status_o_Hi(32-1 downto 0)
<= H2B_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_H2B_STACON)='1'
else (Others=>'0');
H2B_FIFO_Status_o_Lo(32-1 downto 0)
<= H2B_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_H2B_STACON)='1'
else (Others=>'0');
B2H_FIFO_Status_o_Hi(32-1 downto 0)
<= B2H_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_B2H_STACON)='1'
else (Others=>'0');
B2H_FIFO_Status_o_Lo(32-1 downto 0)
<= B2H_FIFO_Status_r1(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_B2H_STACON)='1'
else (Others=>'0');
--S debug_in_4i <= B2H_FIFO_Status_r1(32-1 downto 0);
--------------------------------------------------------------------------
-- Optical Link Status
--------------------------------------------------------------------------
Opto_Link_Status_o_Hi(32-1 downto 0)
<= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_PROTOCOL_STACON)='1'
else (Others=>'0');
Opto_link_Status_o_Lo(32-1 downto 0)
<= Opto_Link_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_PROTOCOL_STACON)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- Class CTL status
--------------------------------------------------------------------------
class_CTL_Status_o_Hi(32-1 downto 0)
<= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_TC_STATUS)='1'
else (Others=>'0');
class_CTL_Status_o_Lo(32-1 downto 0)
<= class_CTL_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_TC_STATUS)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- Data generator Status
--------------------------------------------------------------------------
DG_Status_o_Hi(32-1 downto 0)
<= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_DG_CTRL)='1'
else (Others=>'0');
DG_Status_o_Lo(32-1 downto 0)
<= DG_Status_i(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_DG_CTRL)='1'
else (Others=>'0');
--------------------------------------------------------------------------
-- Hardware version
--------------------------------------------------------------------------
HW_Version_o_Hi(32-1 downto 0)
<= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Hi(CINT_ADDR_VERSION)='1'
else (Others=>'0');
HW_Version_o_Lo(32-1 downto 0)
<= C_DESIGN_ID(32-1 downto 0) when Reg_RdMuxer_Lo(CINT_ADDR_VERSION)='1'
else (Others=>'0');
-----------------------------------------------------
-- Sequential : Regs_RdQout_i
--
Synch_Regs_RdQout:
process ( trn_clk, trn_lnk_up_n)
begin
if trn_lnk_up_n = '1' then
Regs_RdQout_i <= (OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
Regs_RdQout_i(64-1 downto 32) <=
HW_Version_o_Hi (32-1 downto 0)
or Sys_Error_o_Hi (32-1 downto 0)
or General_Status_o_Hi (32-1 downto 0)
or General_Control_o_Hi(32-1 downto 0)
or Sys_Int_Status_o_Hi (32-1 downto 0)
or Sys_Int_Enable_o_Hi (32-1 downto 0)
-- or DMA_us_PA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_PA_o_Hi (32-1 downto 0)
or DMA_us_HA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_HA_o_Hi (32-1 downto 0)
or DMA_us_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_us_BDA_o_Hi (32-1 downto 0)
or DMA_us_Length_o_Hi (32-1 downto 0)
or DMA_us_Control_o_Hi (32-1 downto 0)
or DMA_us_Status_o_Hi (32-1 downto 0)
or DMA_us_Transf_Bytes_o_Hi (32-1 downto 0)
-- or DMA_ds_PA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_PA_o_Hi (32-1 downto 0)
or DMA_ds_HA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_HA_o_Hi (32-1 downto 0)
or DMA_ds_BDA_o_Hi (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_BDA_o_Hi (32-1 downto 0)
or DMA_ds_Length_o_Hi (32-1 downto 0)
or DMA_ds_Control_o_Hi (32-1 downto 0)
or DMA_ds_Status_o_Hi (32-1 downto 0)
or DMA_ds_Transf_Bytes_o_Hi (32-1 downto 0)
or IG_Latency_o_Hi (32-1 downto 0)
or IG_Num_Assert_o_Hi (32-1 downto 0)
or IG_Num_Deassert_o_Hi(32-1 downto 0)
or DG_Status_o_Hi (32-1 downto 0)
or class_CTL_Status_o_Hi (32-1 downto 0)
-- or icap_O_o_Hi (32-1 downto 0)
or Opto_Link_Status_o_Hi (32-1 downto 0)
or eb_FIFO_Status_o_Hi (32-1 downto 0)
or H2B_FIFO_Status_o_Hi (32-1 downto 0)
or B2H_FIFO_Status_o_Hi (32-1 downto 0)
or dlm_rd_o_Hi
or ctl_td_o_Hi
or reg01_rd_o_Hi
or reg02_rd_o_Hi
or reg03_rd_o_Hi
or reg04_rd_o_Hi
or reg05_rd_o_Hi
or reg06_rd_o_Hi
or reg07_rd_o_Hi
or reg08_rd_o_Hi
or reg09_rd_o_Hi
or reg10_rd_o_Hi
or reg11_rd_o_Hi
or reg12_rd_o_Hi
or reg13_rd_o_Hi
or reg14_rd_o_Hi
or reg15_rd_o_Hi
or reg16_rd_o_Hi
or reg17_rd_o_Hi
or reg18_rd_o_Hi
or reg19_rd_o_Hi
or reg20_rd_o_Hi
or reg21_rd_o_Hi
or reg22_rd_o_Hi
or reg23_rd_o_Hi
or reg24_rd_o_Hi
or reg25_rd_o_Hi
;
Regs_RdQout_i(32-1 downto 0) <=
HW_Version_o_Lo (32-1 downto 0)
or Sys_Error_o_Lo (32-1 downto 0)
or General_Status_o_Lo (32-1 downto 0)
or General_Control_o_Lo(32-1 downto 0)
or Sys_Int_Status_o_Lo (32-1 downto 0)
or Sys_Int_Enable_o_Lo (32-1 downto 0)
-- or DMA_us_PA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_PA_o_Lo (32-1 downto 0)
or DMA_us_HA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_HA_o_Lo (32-1 downto 0)
or DMA_us_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_us_BDA_o_Lo (32-1 downto 0)
or DMA_us_Length_o_Lo (32-1 downto 0)
or DMA_us_Control_o_Lo (32-1 downto 0)
or DMA_us_Status_o_Lo (32-1 downto 0)
or DMA_us_Transf_Bytes_o_Lo (32-1 downto 0)
-- or DMA_ds_PA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_PA_o_Lo (32-1 downto 0)
or DMA_ds_HA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_HA_o_Lo (32-1 downto 0)
or DMA_ds_BDA_o_Lo (C_DBUS_WIDTH-1 downto 32)
or DMA_ds_BDA_o_Lo (32-1 downto 0)
or DMA_ds_Length_o_Lo (32-1 downto 0)
or DMA_ds_Control_o_Lo (32-1 downto 0)
or DMA_ds_Status_o_Lo (32-1 downto 0)
or DMA_ds_Transf_Bytes_o_Lo (32-1 downto 0)
or IG_Latency_o_Lo (32-1 downto 0)
or IG_Num_Assert_o_Lo (32-1 downto 0)
or IG_Num_Deassert_o_Lo(32-1 downto 0)
or DG_Status_o_Lo (32-1 downto 0)
or class_CTL_Status_o_Lo (32-1 downto 0)
-- or icap_O_o_Lo(32-1 downto 0)
or Opto_Link_Status_o_Lo (32-1 downto 0)
or eb_FIFO_Status_o_Lo (32-1 downto 0)
or H2B_FIFO_Status_o_Lo (32-1 downto 0)
or B2H_FIFO_Status_o_Lo (32-1 downto 0)
or dlm_rd_o_Lo
or ctl_td_o_Lo
or reg01_rd_o_Lo
or reg02_rd_o_Lo
or reg03_rd_o_Lo
or reg04_rd_o_Lo
or reg05_rd_o_Lo
or reg06_rd_o_Lo
or reg07_rd_o_Lo
or reg08_rd_o_Lo
or reg09_rd_o_Lo
or reg10_rd_o_Lo
or reg11_rd_o_Lo
or reg12_rd_o_Lo
or reg13_rd_o_Lo
or reg14_rd_o_Lo
or reg15_rd_o_Lo
or reg16_rd_o_Lo
or reg17_rd_o_Lo
or reg18_rd_o_Lo
or reg19_rd_o_Lo
or reg20_rd_o_Lo
or reg21_rd_o_Lo
or reg22_rd_o_Lo
or reg23_rd_o_Lo
or reg24_rd_o_Lo
or reg25_rd_o_Lo
;
end if;
end process;
-- -----------------------------------------------------------------------------
-- -- Implementation codes
-- -----------------------------------------------------------------------------
-- Gen_ICAP_width_8:
-- if C_ICAP_WIDTH=8 generate
--
-- ICAP_VIRTEX4_pcie :
-- ICAP_VIRTEX4
-- generic map (
-- ICAP_WIDTH => "X8" -- "X8" or "X32"
-- )
-- port map (
-- BUSY => icap_BUSY , -- Busy output
-- O => icap_O , -- 8-bit data output
-- CE => icap_CE , -- Clock enable input
-- CLK => icap_CLK , -- Clock input
-- I => icap_I , -- 8-bit data input
-- WRITE => icap_WRITE -- Write input
-- );
--
-- end generate;
--
-- Gen_ICAP_width_32:
-- if C_ICAP_WIDTH=32 generate
--
-- ICAP_VIRTEX4_pcie :
-- ICAP_VIRTEX4
-- generic map (
-- ICAP_WIDTH => "X32" -- "X8" or "X32"
-- )
-- port map (
-- BUSY => icap_BUSY , -- Busy output
-- O => icap_O , -- 32-bit data output
-- CE => icap_CE , -- Clock enable input
-- CLK => icap_CLK , -- Clock input
-- I => icap_I , -- 32-bit data input
-- WRITE => icap_WRITE -- Write input
-- );
--
-- end generate;
--
end Behavioral;
| gpl-2.0 | 0c9ffe716f94f447fa819985e4c675ee | 0.489439 | 3.081906 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_tb.vhd | 1 | 6,109 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.wr_fifo32to256_pkg.ALL;
ENTITY wr_fifo32to256_tb IS
END ENTITY;
ARCHITECTURE wr_fifo32to256_arch OF wr_fifo32to256_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from wr_fifo32to256_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of wr_fifo32to256_synth
wr_fifo32to256_synth_inst:wr_fifo32to256_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 4
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | 4dfea085421db5e6e26914ee988396ec | 0.61745 | 4.078104 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_out.vhd | 1 | 5,616 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file weight_out.vhd when simulating
-- the core, weight_out. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY weight_out IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END weight_out;
ARCHITECTURE weight_out_a OF weight_out IS
-- synthesis translate_off
COMPONENT wrapped_weight_out
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(319 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_weight_out USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 6,
c_addrb_width => 6,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "artix7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "weight_out.mif",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 1,
c_mem_type => 0,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 45,
c_read_depth_b => 45,
c_read_width_a => 320,
c_read_width_b => 320,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 45,
c_write_depth_b => 45,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 320,
c_write_width_b => 320,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_weight_out
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- synthesis translate_on
END weight_out_a;
| bsd-2-clause | e2e771c0875b03996e34ccb5c9d132ca | 0.532585 | 3.95493 | false | false | false | false |
UnofficialRepos/OSVVM | SortListPkg_int.vhd | 2 | 13,651 | --
-- File Name: SortListPkg_int.vhd
-- Design Unit Name: SortListPkg_int
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
-- Description:
-- Sorting utility for array of scalars
-- Uses protected type so as to shrink and expand the data structure
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
-- 02/2009: 1.0 First Public Released Version
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference to
-- ieee_proposed.standard_additions.all ;
-- 06/16/2010 1.2 Added EraseList parameter to to_array
-- 3/2011 2.0 added inside as non protected type
-- 6/2011 2.1 added sort as non protected type
-- 4/2013 2013.04 No Changes
-- 5/2013 2013.05 No changes of substance.
-- Deleted extra variable declaration in procedure remove
-- 1/2014 2014.01 Added RevSort. Added AllowDuplicate paramter to Add procedure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 11/2016 2016.11 Revised Add. When AllowDuplicate, add a matching value last.
-- 01/2020 2020.01 Updated Licenses to Apache
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_textio.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package SortListPkg_int is
-- with VHDL-2008, convert package to generic package
-- convert subtypes ElementType and ArrayofElementType to generics
-- package SortListGenericPkg is
subtype ElementType is integer ;
subtype ArrayofElementType is integer_vector ;
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType ;
type SortListPType is protected
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) ;
procedure add ( constant A : in ArrayofElementType ) ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) ;
procedure add ( variable A : inout SortListPType ) ;
-- Count items in list
impure function count return integer ;
impure function find_index ( constant A : ElementType) return integer ;
impure function inside (constant A : ElementType) return boolean ;
procedure insert ( constant A : in ElementType; constant index : in integer := 1 ) ;
impure function get ( constant index : in integer := 1 ) return ElementType ;
procedure erase ;
impure function Empty return boolean ;
procedure print ;
procedure remove ( constant A : in ElementType ) ;
procedure remove ( constant A : in ArrayofElementType ) ;
procedure remove ( variable A : inout SortListPType ) ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType ;
end protected SortListPType ;
end SortListPkg_int ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body SortListPkg_int is
impure function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is
begin
for i in A'range loop
if E = A(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
type SortListPType is protected body
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
A : ElementType ;
-- item_num : integer ;
NextPtr : ListPointerType ;
-- PrevPtr : ListPointerType ;
end record ;
variable HeadPointer : ListPointerType := NULL ;
-- variable TailPointer : ListPointerType := NULL ;
procedure add ( constant A : in ElementType ; constant AllowDuplicate : Boolean := FALSE ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
HeadPointer := new ListType'(A, NULL) ;
elsif A = HeadPointer.A then -- ignore duplicates
if AllowDuplicate then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
end if ;
elsif A < HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
AddLoop : loop
exit AddLoop when CurPtr.NextPtr = NULL ;
exit AddLoop when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
-- if AllowDuplicate then -- changed s.t. insert at after match rather than before
-- exit AddLoop ; -- insert
-- else
if not AllowDuplicate then
return ; -- return without insert
end if;
end if ;
CurPtr := CurPtr.NextPtr ;
end loop AddLoop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
add(A(i)) ;
end loop ;
end procedure add ;
procedure add ( constant A : in ArrayofElementType ; Min, Max : ElementType ) is
begin
for i in A'range loop
if A(i) >= Min and A(i) <= Max then
add(A(i)) ;
end if ;
end loop ;
end procedure add ;
procedure add ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
add(A.Get(i)) ;
end loop ;
end procedure add ;
-- Count items in list
impure function count return integer is
variable result : positive := 1 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function count ;
impure function find_index (constant A : ElementType) return integer is
variable result : positive := 2 ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return 0 ;
elsif A <= HeadPointer.A then
return 1 ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A <= CurPtr.NextPtr.A ;
result := result + 1 ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return result ;
end if ;
end function find_index ;
impure function inside (constant A : ElementType) return boolean is
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return FALSE ;
end if ;
if A = HeadPointer.A then
return TRUE ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
exit when A < CurPtr.NextPtr.A ;
if A = CurPtr.NextPtr.A then
return TRUE ; -- exit
end if;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
return FALSE ;
end function inside ;
procedure insert( constant A : in ElementType; constant index : in integer := 1 ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if index <= 1 then
tempPtr := HeadPointer ;
HeadPointer := new ListType'(A, tempPtr) ;
else
CurPtr := HeadPointer ;
for i in 3 to index loop
exit when CurPtr.NextPtr = NULL ; -- end of list
CurPtr := CurPtr.NextPtr ;
end loop ;
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := new ListType'(A, tempPtr) ;
end if;
end procedure insert ;
impure function get ( constant index : in integer := 1 ) return ElementType is
variable CurPtr : ListPointerType ;
begin
if index > Count then
Alert(OSVVM_ALERTLOG_ID, "SortLIstPkg_int.get index out of range", FAILURE) ;
return ElementType'left ;
elsif HeadPointer = NULL then
return ElementType'left ;
elsif index <= 1 then
return HeadPointer.A ;
else
CurPtr := HeadPointer ;
for i in 2 to index loop
CurPtr := CurPtr.NextPtr ;
end loop ;
return CurPtr.A ;
end if;
end function get ;
procedure erase (variable CurPtr : inout ListPointerType ) is
begin
if CurPtr.NextPtr /= NULL then
erase (CurPtr.NextPtr) ;
end if ;
deallocate (CurPtr) ;
end procedure erase ;
procedure erase is
begin
if HeadPointer /= NULL then
erase(HeadPointer) ;
-- deallocate (HeadPointer) ;
HeadPointer := NULL ;
end if;
end procedure erase ;
impure function Empty return boolean is
begin
return HeadPointer = NULL ;
end Empty ;
procedure print is
variable buf : line ;
variable CurPtr : ListPointerType ;
begin
if HeadPointer = NULL then
write (buf, string'("( )")) ;
else
CurPtr := HeadPointer ;
write (buf, string'("(")) ;
loop
write (buf, CurPtr.A) ;
exit when CurPtr.NextPtr = NULL ;
write (buf, string'(", ")) ;
CurPtr := CurPtr.NextPtr ;
end loop ;
write (buf, string'(")")) ;
end if ;
writeline(OUTPUT, buf) ;
end procedure print ;
procedure remove ( constant A : in ElementType ) is
variable CurPtr, tempPtr : ListPointerType ;
begin
if HeadPointer = NULL then
return ;
elsif A = HeadPointer.A then
tempPtr := HeadPointer ;
HeadPointer := HeadPointer.NextPtr ;
deallocate (tempPtr) ;
else
CurPtr := HeadPointer ;
loop
exit when CurPtr.NextPtr = NULL ;
if A = CurPtr.NextPtr.A then
tempPtr := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
deallocate (tempPtr) ;
exit ;
end if ;
exit when A < CurPtr.NextPtr.A ;
CurPtr := CurPtr.NextPtr ;
end loop ;
end if ;
end procedure remove ;
procedure remove ( constant A : in ArrayofElementType ) is
begin
for i in A'range loop
remove(A(i)) ;
end loop ;
end procedure remove ;
procedure remove ( variable A : inout SortListPType ) is
begin
for i in 1 to A.Count loop
remove(A.Get(i)) ;
end loop ;
end procedure remove ;
impure function to_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(1 to Count) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_array ;
impure function to_rev_array (constant EraseList : boolean := FALSE) return ArrayofElementType is
variable result : ArrayofElementType(Count downto 1) ;
begin
for i in 1 to Count loop
result(i) := Get(i) ;
end loop ;
if EraseList then
erase ;
end if ;
return result ;
end function to_rev_array ;
end protected body SortListPType ;
impure function sort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_array(EraseList => TRUE) ;
end function sort ;
impure function revsort (constant A : in ArrayofElementType) return ArrayofElementType is
variable Result : SortListPType ;
begin
for i in A'range loop
Result.Add(A(i), TRUE) ;
end loop ;
return Result.to_rev_array(EraseList => TRUE) ;
end function revsort ;
end SortListPkg_int ;
| artistic-2.0 | c504e5f33fd8bd7784e478021c1926df | 0.601934 | 4.529197 | false | false | false | false |
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