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peteut/nvc | test/regress/arith1.vhd | 1 | 794 | entity arith1 is
end entity;
architecture test of arith1 is
begin
proc1: process is
variable x, y : integer;
begin
x := 3;
y := 12;
wait for 1 ns;
assert x + y = 15;
assert x - y = -9;
assert x * y = 36;
assert x / 12 = 0;
assert x = 3;
assert y = 12;
assert x /= y;
assert x < y;
assert y > x;
assert x <= y;
assert y >= x;
assert (- x) = -3;
assert x ** y = 531441;
x := -34;
assert abs x = 34;
assert abs y = 12;
y := 3;
assert 5 mod y = 2;
assert 5 rem y = 2;
assert (-5) rem y = -2;
assert (-5) mod y = 2;
assert x = +x;
wait;
end process;
end architecture;
| gpl-3.0 | adf85095a2aea52f87cd3602f2a8fbf5 | 0.424433 | 3.528889 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_14/Lab_14_3_1/synk_JK.vhd | 1 | 663 | library ieee;
use ieee.std_logic_1164.all;
entity synk_JK is
PORT (J: in std_logic;
K: in std_logic;
CLK: in std_logic;
PRST: in std_logic;
CLR: in std_logic;
Q: out std_logic;
QB: out std_logic);
end synk_JK;
Architecture Arch_synk_JK of synk_JK is
begin
JK: process (CLK, CLR, PRST)
variable x: std_logic;
begin
if (CLR='0') then
x:='0';
elsif (PRST='0') then
x:='1';
elsif (CLK='1' and CLK'EVENT) then
if (J='0' and K='0') then
x:=x;
elsif (J='1' and K='1') then
x:= not x;
elsif (J='0' and K='1') then
x:='0';
else
x:='1';
end if;
end if;
Q <= x;
QB <= not x;
end process JK;
end Arch_synk_JK; | gpl-2.0 | ca560f33fcf39b6ebcab83aa8cb7135e | 0.573152 | 2.310105 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/hdl/cpu.vhd | 1 | 185,946 | --Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
--Date : Fri Sep 30 18:09:05 2016
--Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
--Command : generate_target cpu.bd
--Design : cpu
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_ZVW4AE is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end m00_couplers_imp_ZVW4AE;
architecture STRUCTURE of m00_couplers_imp_ZVW4AE is
signal m00_couplers_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
begin
M_AXI_araddr(8 downto 0) <= m00_couplers_to_m00_couplers_ARADDR(8 downto 0);
M_AXI_arvalid(0) <= m00_couplers_to_m00_couplers_ARVALID(0);
M_AXI_awaddr(8 downto 0) <= m00_couplers_to_m00_couplers_AWADDR(8 downto 0);
M_AXI_awvalid(0) <= m00_couplers_to_m00_couplers_AWVALID(0);
M_AXI_bready(0) <= m00_couplers_to_m00_couplers_BREADY(0);
M_AXI_rready(0) <= m00_couplers_to_m00_couplers_RREADY(0);
M_AXI_wdata(31 downto 0) <= m00_couplers_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_couplers_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid(0) <= m00_couplers_to_m00_couplers_WVALID(0);
S_AXI_arready(0) <= m00_couplers_to_m00_couplers_ARREADY(0);
S_AXI_awready(0) <= m00_couplers_to_m00_couplers_AWREADY(0);
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_couplers_BRESP(1 downto 0);
S_AXI_bvalid(0) <= m00_couplers_to_m00_couplers_BVALID(0);
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_couplers_RRESP(1 downto 0);
S_AXI_rvalid(0) <= m00_couplers_to_m00_couplers_RVALID(0);
S_AXI_wready(0) <= m00_couplers_to_m00_couplers_WREADY(0);
m00_couplers_to_m00_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m00_couplers_to_m00_couplers_ARREADY(0) <= M_AXI_arready(0);
m00_couplers_to_m00_couplers_ARVALID(0) <= S_AXI_arvalid(0);
m00_couplers_to_m00_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m00_couplers_to_m00_couplers_AWREADY(0) <= M_AXI_awready(0);
m00_couplers_to_m00_couplers_AWVALID(0) <= S_AXI_awvalid(0);
m00_couplers_to_m00_couplers_BREADY(0) <= S_AXI_bready(0);
m00_couplers_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_couplers_to_m00_couplers_BVALID(0) <= M_AXI_bvalid(0);
m00_couplers_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_couplers_to_m00_couplers_RREADY(0) <= S_AXI_rready(0);
m00_couplers_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_couplers_to_m00_couplers_RVALID(0) <= M_AXI_rvalid(0);
m00_couplers_to_m00_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_couplers_WREADY(0) <= M_AXI_wready(0);
m00_couplers_to_m00_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_couplers_WVALID(0) <= S_AXI_wvalid(0);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_PQKNCJ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_PQKNCJ;
architecture STRUCTURE of m01_couplers_imp_PQKNCJ is
signal m01_couplers_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(8 downto 0) <= m01_couplers_to_m01_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m01_couplers_to_m01_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m01_couplers_to_m01_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m01_couplers_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_couplers_to_m01_couplers_BREADY;
M_AXI_rready <= m01_couplers_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_couplers_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m01_couplers_to_m01_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m01_couplers_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_couplers_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_couplers_RVALID;
S_AXI_wready <= m01_couplers_to_m01_couplers_WREADY;
m01_couplers_to_m01_couplers_ARADDR(8 downto 0) <= S_AXI_araddr(8 downto 0);
m01_couplers_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_couplers_to_m01_couplers_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_couplers_AWADDR(8 downto 0) <= S_AXI_awaddr(8 downto 0);
m01_couplers_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_couplers_to_m01_couplers_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_couplers_BREADY <= S_AXI_bready;
m01_couplers_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_couplers_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_couplers_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_couplers_to_m01_couplers_RREADY <= S_AXI_rready;
m01_couplers_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_couplers_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_couplers_to_m01_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_couplers_WREADY <= M_AXI_wready;
m01_couplers_to_m01_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m02_couplers_imp_1QFTZ3X is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m02_couplers_imp_1QFTZ3X;
architecture STRUCTURE of m02_couplers_imp_1QFTZ3X is
signal m02_couplers_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_m02_couplers_ARREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_ARVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_m02_couplers_AWREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_AWVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_BVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_RREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_m02_couplers_RVALID : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_m02_couplers_WREADY : STD_LOGIC;
signal m02_couplers_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_m02_couplers_WVALID : STD_LOGIC;
begin
M_AXI_araddr(10 downto 0) <= m02_couplers_to_m02_couplers_ARADDR(10 downto 0);
M_AXI_arvalid <= m02_couplers_to_m02_couplers_ARVALID;
M_AXI_awaddr(10 downto 0) <= m02_couplers_to_m02_couplers_AWADDR(10 downto 0);
M_AXI_awvalid <= m02_couplers_to_m02_couplers_AWVALID;
M_AXI_bready <= m02_couplers_to_m02_couplers_BREADY;
M_AXI_rready <= m02_couplers_to_m02_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m02_couplers_to_m02_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m02_couplers_to_m02_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m02_couplers_to_m02_couplers_WVALID;
S_AXI_arready <= m02_couplers_to_m02_couplers_ARREADY;
S_AXI_awready <= m02_couplers_to_m02_couplers_AWREADY;
S_AXI_bresp(1 downto 0) <= m02_couplers_to_m02_couplers_BRESP(1 downto 0);
S_AXI_bvalid <= m02_couplers_to_m02_couplers_BVALID;
S_AXI_rdata(31 downto 0) <= m02_couplers_to_m02_couplers_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m02_couplers_to_m02_couplers_RRESP(1 downto 0);
S_AXI_rvalid <= m02_couplers_to_m02_couplers_RVALID;
S_AXI_wready <= m02_couplers_to_m02_couplers_WREADY;
m02_couplers_to_m02_couplers_ARADDR(10 downto 0) <= S_AXI_araddr(10 downto 0);
m02_couplers_to_m02_couplers_ARREADY <= M_AXI_arready;
m02_couplers_to_m02_couplers_ARVALID <= S_AXI_arvalid;
m02_couplers_to_m02_couplers_AWADDR(10 downto 0) <= S_AXI_awaddr(10 downto 0);
m02_couplers_to_m02_couplers_AWREADY <= M_AXI_awready;
m02_couplers_to_m02_couplers_AWVALID <= S_AXI_awvalid;
m02_couplers_to_m02_couplers_BREADY <= S_AXI_bready;
m02_couplers_to_m02_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m02_couplers_to_m02_couplers_BVALID <= M_AXI_bvalid;
m02_couplers_to_m02_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m02_couplers_to_m02_couplers_RREADY <= S_AXI_rready;
m02_couplers_to_m02_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m02_couplers_to_m02_couplers_RVALID <= M_AXI_rvalid;
m02_couplers_to_m02_couplers_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m02_couplers_to_m02_couplers_WREADY <= M_AXI_wready;
m02_couplers_to_m02_couplers_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m02_couplers_to_m02_couplers_WVALID <= S_AXI_wvalid;
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1AHKP6S is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1AHKP6S;
architecture STRUCTURE of s00_couplers_imp_1AHKP6S is
component cpu_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component cpu_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
signal NLW_auto_pc_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_auto_pc_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component cpu_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => NLW_auto_pc_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => NLW_auto_pc_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_B67PN0 is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_B67PN0;
architecture STRUCTURE of s00_couplers_imp_B67PN0 is
component cpu_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component cpu_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component cpu_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu_processing_system7_0_axi_periph_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_arready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_arvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M00_AXI_awready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_awvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M01_AXI_wvalid : out STD_LOGIC;
M02_ACLK : in STD_LOGIC;
M02_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M02_AXI_araddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M02_AXI_arready : in STD_LOGIC;
M02_AXI_arvalid : out STD_LOGIC;
M02_AXI_awaddr : out STD_LOGIC_VECTOR ( 10 downto 0 );
M02_AXI_awready : in STD_LOGIC;
M02_AXI_awvalid : out STD_LOGIC;
M02_AXI_bready : out STD_LOGIC;
M02_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_bvalid : in STD_LOGIC;
M02_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_rready : out STD_LOGIC;
M02_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M02_AXI_rvalid : in STD_LOGIC;
M02_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M02_AXI_wready : in STD_LOGIC;
M02_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M02_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end cpu_processing_system7_0_axi_periph_0;
architecture STRUCTURE of cpu_processing_system7_0_axi_periph_0 is
component cpu_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 95 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 2 downto 0 )
);
end component cpu_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M02_ACLK_1 : STD_LOGIC;
signal M02_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m01_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_ARREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_ARVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_AWREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_AWVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_BVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_RVALID : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WREADY : STD_LOGIC;
signal m02_couplers_to_processing_system7_0_axi_periph_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m02_couplers_to_processing_system7_0_axi_periph_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m02_couplers_ARADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m02_couplers_ARVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_AWADDR : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m02_couplers_AWVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_BVALID : STD_LOGIC;
signal xbar_to_m02_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m02_couplers_RREADY : STD_LOGIC_VECTOR ( 2 to 2 );
signal xbar_to_m02_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m02_couplers_RVALID : STD_LOGIC;
signal xbar_to_m02_couplers_WDATA : STD_LOGIC_VECTOR ( 95 downto 64 );
signal xbar_to_m02_couplers_WREADY : STD_LOGIC;
signal xbar_to_m02_couplers_WSTRB : STD_LOGIC_VECTOR ( 11 downto 8 );
signal xbar_to_m02_couplers_WVALID : STD_LOGIC_VECTOR ( 2 to 2 );
signal NLW_xbar_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
signal NLW_xbar_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 8 downto 0 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M00_AXI_arvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0);
M00_AXI_awaddr(8 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M00_AXI_awvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0);
M00_AXI_bready(0) <= m00_couplers_to_processing_system7_0_axi_periph_BREADY(0);
M00_AXI_rready(0) <= m00_couplers_to_processing_system7_0_axi_periph_RREADY(0);
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M00_AXI_wvalid(0) <= m00_couplers_to_processing_system7_0_axi_periph_WVALID(0);
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(8 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0);
M01_AXI_arvalid <= m01_couplers_to_processing_system7_0_axi_periph_ARVALID;
M01_AXI_awaddr(8 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0);
M01_AXI_awvalid <= m01_couplers_to_processing_system7_0_axi_periph_AWVALID;
M01_AXI_bready <= m01_couplers_to_processing_system7_0_axi_periph_BREADY;
M01_AXI_rready <= m01_couplers_to_processing_system7_0_axi_periph_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M01_AXI_wstrb(3 downto 0) <= m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M01_AXI_wvalid <= m01_couplers_to_processing_system7_0_axi_periph_WVALID;
M02_ACLK_1 <= M02_ACLK;
M02_ARESETN_1(0) <= M02_ARESETN(0);
M02_AXI_araddr(10 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_ARADDR(10 downto 0);
M02_AXI_arvalid <= m02_couplers_to_processing_system7_0_axi_periph_ARVALID;
M02_AXI_awaddr(10 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_AWADDR(10 downto 0);
M02_AXI_awvalid <= m02_couplers_to_processing_system7_0_axi_periph_AWVALID;
M02_AXI_bready <= m02_couplers_to_processing_system7_0_axi_periph_BREADY;
M02_AXI_rready <= m02_couplers_to_processing_system7_0_axi_periph_RREADY;
M02_AXI_wdata(31 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0);
M02_AXI_wstrb(3 downto 0) <= m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0);
M02_AXI_wvalid <= m02_couplers_to_processing_system7_0_axi_periph_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_to_s00_couplers_WREADY;
m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0) <= M00_AXI_arready(0);
m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0) <= M00_AXI_awready(0);
m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_BVALID(0) <= M00_AXI_bvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_processing_system7_0_axi_periph_RVALID(0) <= M00_AXI_rvalid(0);
m00_couplers_to_processing_system7_0_axi_periph_WREADY(0) <= M00_AXI_wready(0);
m01_couplers_to_processing_system7_0_axi_periph_ARREADY <= M01_AXI_arready;
m01_couplers_to_processing_system7_0_axi_periph_AWREADY <= M01_AXI_awready;
m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_BVALID <= M01_AXI_bvalid;
m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_processing_system7_0_axi_periph_RVALID <= M01_AXI_rvalid;
m01_couplers_to_processing_system7_0_axi_periph_WREADY <= M01_AXI_wready;
m02_couplers_to_processing_system7_0_axi_periph_ARREADY <= M02_AXI_arready;
m02_couplers_to_processing_system7_0_axi_periph_AWREADY <= M02_AXI_awready;
m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0) <= M02_AXI_bresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_BVALID <= M02_AXI_bvalid;
m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0) <= M02_AXI_rdata(31 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0) <= M02_AXI_rresp(1 downto 0);
m02_couplers_to_processing_system7_0_axi_periph_RVALID <= M02_AXI_rvalid;
m02_couplers_to_processing_system7_0_axi_periph_WREADY <= M02_AXI_wready;
processing_system7_0_axi_periph_ACLK_net <= ACLK;
processing_system7_0_axi_periph_ARESETN_net(0) <= ARESETN(0);
processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers: entity work.m00_couplers_imp_ZVW4AE
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready(0) => m00_couplers_to_processing_system7_0_axi_periph_ARREADY(0),
M_AXI_arvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_ARVALID(0),
M_AXI_awaddr(8 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready(0) => m00_couplers_to_processing_system7_0_axi_periph_AWREADY(0),
M_AXI_awvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_AWVALID(0),
M_AXI_bready(0) => m00_couplers_to_processing_system7_0_axi_periph_BREADY(0),
M_AXI_bresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_BVALID(0),
M_AXI_rdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready(0) => m00_couplers_to_processing_system7_0_axi_periph_RREADY(0),
M_AXI_rresp(1 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_RVALID(0),
M_AXI_wdata(31 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready(0) => m00_couplers_to_processing_system7_0_axi_periph_WREADY(0),
M_AXI_wstrb(3 downto 0) => m00_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid(0) => m00_couplers_to_processing_system7_0_axi_periph_WVALID(0),
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m00_couplers_ARADDR(8 downto 0),
S_AXI_arready(0) => xbar_to_m00_couplers_ARREADY(0),
S_AXI_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(8 downto 0) => xbar_to_m00_couplers_AWADDR(8 downto 0),
S_AXI_awready(0) => xbar_to_m00_couplers_AWREADY(0),
S_AXI_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready(0) => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready(0) => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready(0) => xbar_to_m00_couplers_WREADY(0),
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid(0) => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_PQKNCJ
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_ARADDR(8 downto 0),
M_AXI_arready => m01_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m01_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(8 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_AWADDR(8 downto 0),
M_AXI_awready => m01_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m01_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m01_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m01_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m01_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(8 downto 0) => xbar_to_m01_couplers_ARADDR(40 downto 32),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(8 downto 0) => xbar_to_m01_couplers_AWADDR(40 downto 32),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
m02_couplers: entity work.m02_couplers_imp_1QFTZ3X
port map (
M_ACLK => M02_ACLK_1,
M_ARESETN(0) => M02_ARESETN_1(0),
M_AXI_araddr(10 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_ARADDR(10 downto 0),
M_AXI_arready => m02_couplers_to_processing_system7_0_axi_periph_ARREADY,
M_AXI_arvalid => m02_couplers_to_processing_system7_0_axi_periph_ARVALID,
M_AXI_awaddr(10 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_AWADDR(10 downto 0),
M_AXI_awready => m02_couplers_to_processing_system7_0_axi_periph_AWREADY,
M_AXI_awvalid => m02_couplers_to_processing_system7_0_axi_periph_AWVALID,
M_AXI_bready => m02_couplers_to_processing_system7_0_axi_periph_BREADY,
M_AXI_bresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_BRESP(1 downto 0),
M_AXI_bvalid => m02_couplers_to_processing_system7_0_axi_periph_BVALID,
M_AXI_rdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RDATA(31 downto 0),
M_AXI_rready => m02_couplers_to_processing_system7_0_axi_periph_RREADY,
M_AXI_rresp(1 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_RRESP(1 downto 0),
M_AXI_rvalid => m02_couplers_to_processing_system7_0_axi_periph_RVALID,
M_AXI_wdata(31 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WDATA(31 downto 0),
M_AXI_wready => m02_couplers_to_processing_system7_0_axi_periph_WREADY,
M_AXI_wstrb(3 downto 0) => m02_couplers_to_processing_system7_0_axi_periph_WSTRB(3 downto 0),
M_AXI_wvalid => m02_couplers_to_processing_system7_0_axi_periph_WVALID,
S_ACLK => processing_system7_0_axi_periph_ACLK_net,
S_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
S_AXI_araddr(10 downto 0) => xbar_to_m02_couplers_ARADDR(74 downto 64),
S_AXI_arready => xbar_to_m02_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m02_couplers_ARVALID(2),
S_AXI_awaddr(10 downto 0) => xbar_to_m02_couplers_AWADDR(74 downto 64),
S_AXI_awready => xbar_to_m02_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m02_couplers_AWVALID(2),
S_AXI_bready => xbar_to_m02_couplers_BREADY(2),
S_AXI_bresp(1 downto 0) => xbar_to_m02_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m02_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m02_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m02_couplers_RREADY(2),
S_AXI_rresp(1 downto 0) => xbar_to_m02_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m02_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m02_couplers_WDATA(95 downto 64),
S_AXI_wready => xbar_to_m02_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m02_couplers_WSTRB(11 downto 8),
S_AXI_wvalid => xbar_to_m02_couplers_WVALID(2)
);
s00_couplers: entity work.s00_couplers_imp_B67PN0
port map (
M_ACLK => processing_system7_0_axi_periph_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_to_s00_couplers_WVALID
);
xbar: component cpu_xbar_0
port map (
aclk => processing_system7_0_axi_periph_ACLK_net,
aresetn => processing_system7_0_axi_periph_ARESETN_net(0),
m_axi_araddr(95 downto 64) => xbar_to_m02_couplers_ARADDR(95 downto 64),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(8 downto 0) => NLW_xbar_m_axi_arprot_UNCONNECTED(8 downto 0),
m_axi_arready(2) => xbar_to_m02_couplers_ARREADY,
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY(0),
m_axi_arvalid(2) => xbar_to_m02_couplers_ARVALID(2),
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(95 downto 64) => xbar_to_m02_couplers_AWADDR(95 downto 64),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(8 downto 0) => NLW_xbar_m_axi_awprot_UNCONNECTED(8 downto 0),
m_axi_awready(2) => xbar_to_m02_couplers_AWREADY,
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY(0),
m_axi_awvalid(2) => xbar_to_m02_couplers_AWVALID(2),
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(2) => xbar_to_m02_couplers_BREADY(2),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(5 downto 4) => xbar_to_m02_couplers_BRESP(1 downto 0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(2) => xbar_to_m02_couplers_BVALID,
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID(0),
m_axi_rdata(95 downto 64) => xbar_to_m02_couplers_RDATA(31 downto 0),
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(2) => xbar_to_m02_couplers_RREADY(2),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(5 downto 4) => xbar_to_m02_couplers_RRESP(1 downto 0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(2) => xbar_to_m02_couplers_RVALID,
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID(0),
m_axi_wdata(95 downto 64) => xbar_to_m02_couplers_WDATA(95 downto 64),
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(2) => xbar_to_m02_couplers_WREADY,
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY(0),
m_axi_wstrb(11 downto 8) => xbar_to_m02_couplers_WSTRB(11 downto 8),
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(2) => xbar_to_m02_couplers_WVALID(2),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu_processing_system7_0_axi_periph_1_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end cpu_processing_system7_0_axi_periph_1_0;
architecture STRUCTURE of cpu_processing_system7_0_axi_periph_1_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_1_ACLK_net : STD_LOGIC;
signal processing_system7_0_axi_periph_1_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_RLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_WLAST : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_BREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_BVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_RREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_RVALID : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_WREADY : STD_LOGIC;
signal s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_processing_system7_0_axi_periph_1_WVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR(31 downto 0);
M00_AXI_arvalid <= s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID;
M00_AXI_awaddr(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR(31 downto 0);
M00_AXI_awvalid <= s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID;
M00_AXI_bready <= s00_couplers_to_processing_system7_0_axi_periph_1_BREADY;
M00_AXI_rready <= s00_couplers_to_processing_system7_0_axi_periph_1_RREADY;
M00_AXI_wdata(31 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB(3 downto 0);
M00_AXI_wvalid <= s00_couplers_to_processing_system7_0_axi_periph_1_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY;
S00_AXI_awready <= processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= processing_system7_0_axi_periph_1_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= processing_system7_0_axi_periph_1_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= processing_system7_0_axi_periph_1_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= processing_system7_0_axi_periph_1_to_s00_couplers_RVALID;
S00_AXI_wready <= processing_system7_0_axi_periph_1_to_s00_couplers_WREADY;
processing_system7_0_axi_periph_1_ACLK_net <= M00_ACLK;
processing_system7_0_axi_periph_1_ARESETN_net(0) <= M00_ARESETN(0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
processing_system7_0_axi_periph_1_to_s00_couplers_BREADY <= S00_AXI_bready;
processing_system7_0_axi_periph_1_to_s00_couplers_RREADY <= S00_AXI_rready;
processing_system7_0_axi_periph_1_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_WLAST <= S00_AXI_wlast;
processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
processing_system7_0_axi_periph_1_to_s00_couplers_WVALID <= S00_AXI_wvalid;
s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY <= M00_AXI_arready;
s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY <= M00_AXI_awready;
s00_couplers_to_processing_system7_0_axi_periph_1_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_1_BVALID <= M00_AXI_bvalid;
s00_couplers_to_processing_system7_0_axi_periph_1_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_1_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_processing_system7_0_axi_periph_1_RVALID <= M00_AXI_rvalid;
s00_couplers_to_processing_system7_0_axi_periph_1_WREADY <= M00_AXI_wready;
s00_couplers: entity work.s00_couplers_imp_1AHKP6S
port map (
M_ACLK => processing_system7_0_axi_periph_1_ACLK_net,
M_ARESETN(0) => processing_system7_0_axi_periph_1_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_ARADDR(31 downto 0),
M_AXI_arready => s00_couplers_to_processing_system7_0_axi_periph_1_ARREADY,
M_AXI_arvalid => s00_couplers_to_processing_system7_0_axi_periph_1_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_AWADDR(31 downto 0),
M_AXI_awready => s00_couplers_to_processing_system7_0_axi_periph_1_AWREADY,
M_AXI_awvalid => s00_couplers_to_processing_system7_0_axi_periph_1_AWVALID,
M_AXI_bready => s00_couplers_to_processing_system7_0_axi_periph_1_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_processing_system7_0_axi_periph_1_BVALID,
M_AXI_rdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_processing_system7_0_axi_periph_1_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_processing_system7_0_axi_periph_1_RVALID,
M_AXI_wdata(31 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_processing_system7_0_axi_periph_1_WREADY,
M_AXI_wstrb(3 downto 0) => s00_couplers_to_processing_system7_0_axi_periph_1_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_processing_system7_0_axi_periph_1_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => processing_system7_0_axi_periph_1_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => processing_system7_0_axi_periph_1_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => processing_system7_0_axi_periph_1_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => processing_system7_0_axi_periph_1_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => processing_system7_0_axi_periph_1_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => processing_system7_0_axi_periph_1_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => processing_system7_0_axi_periph_1_to_s00_couplers_RLAST,
S_AXI_rready => processing_system7_0_axi_periph_1_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => processing_system7_0_axi_periph_1_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => processing_system7_0_axi_periph_1_to_s00_couplers_WLAST,
S_AXI_wready => processing_system7_0_axi_periph_1_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_1_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => processing_system7_0_axi_periph_1_to_s00_couplers_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity cpu is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
EPC_INTF_addr : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_ads : out STD_LOGIC;
EPC_INTF_be : out STD_LOGIC_VECTOR ( 0 to 3 );
EPC_INTF_burst : out STD_LOGIC;
EPC_INTF_clk : in STD_LOGIC;
EPC_INTF_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_data_i : in STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_data_o : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_data_t : out STD_LOGIC_VECTOR ( 0 to 31 );
EPC_INTF_rd_n : out STD_LOGIC;
EPC_INTF_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
EPC_INTF_rnw : out STD_LOGIC;
EPC_INTF_rst : in STD_LOGIC;
EPC_INTF_wr_n : out STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
GPIO_tri_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_tri_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
GPIO_tri_t : out STD_LOGIC_VECTOR ( 15 downto 0 );
IIC_0_scl_i : in STD_LOGIC;
IIC_0_scl_o : out STD_LOGIC;
IIC_0_scl_t : out STD_LOGIC;
IIC_0_sda_i : in STD_LOGIC;
IIC_0_sda_o : out STD_LOGIC;
IIC_0_sda_t : out STD_LOGIC;
IIC_1_scl_i : in STD_LOGIC;
IIC_1_scl_o : out STD_LOGIC;
IIC_1_scl_t : out STD_LOGIC;
IIC_1_sda_i : in STD_LOGIC;
IIC_1_sda_o : out STD_LOGIC;
IIC_1_sda_t : out STD_LOGIC;
IIC_scl_i : in STD_LOGIC;
IIC_scl_o : out STD_LOGIC;
IIC_scl_t : out STD_LOGIC;
IIC_sda_i : in STD_LOGIC;
IIC_sda_o : out STD_LOGIC;
IIC_sda_t : out STD_LOGIC;
Int0 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int1 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int2 : in STD_LOGIC_VECTOR ( 0 to 0 );
Int3 : in STD_LOGIC_VECTOR ( 0 to 0 );
OCXO_CLK100 : in STD_LOGIC;
OCXO_RESETN : out STD_LOGIC_VECTOR ( 0 to 0 );
UART_0_rxd : in STD_LOGIC;
UART_0_txd : out STD_LOGIC;
Vp_Vn_v_n : in STD_LOGIC;
Vp_Vn_v_p : in STD_LOGIC
);
end cpu;
architecture STRUCTURE of cpu is
component cpu_processing_system7_0_0 is
port (
ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC;
ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC;
ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC;
ENET0_SOF_RX : out STD_LOGIC;
ENET0_SOF_TX : out STD_LOGIC;
I2C0_SDA_I : in STD_LOGIC;
I2C0_SDA_O : out STD_LOGIC;
I2C0_SDA_T : out STD_LOGIC;
I2C0_SCL_I : in STD_LOGIC;
I2C0_SCL_O : out STD_LOGIC;
I2C0_SCL_T : out STD_LOGIC;
I2C1_SDA_I : in STD_LOGIC;
I2C1_SDA_O : out STD_LOGIC;
I2C1_SDA_T : out STD_LOGIC;
I2C1_SCL_I : in STD_LOGIC;
I2C1_SCL_O : out STD_LOGIC;
I2C1_SCL_T : out STD_LOGIC;
UART0_TX : out STD_LOGIC;
UART0_RX : in STD_LOGIC;
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARVALID : out STD_LOGIC;
M_AXI_GP1_AWVALID : out STD_LOGIC;
M_AXI_GP1_BREADY : out STD_LOGIC;
M_AXI_GP1_RREADY : out STD_LOGIC;
M_AXI_GP1_WLAST : out STD_LOGIC;
M_AXI_GP1_WVALID : out STD_LOGIC;
M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP1_ACLK : in STD_LOGIC;
M_AXI_GP1_ARREADY : in STD_LOGIC;
M_AXI_GP1_AWREADY : in STD_LOGIC;
M_AXI_GP1_BVALID : in STD_LOGIC;
M_AXI_GP1_RLAST : in STD_LOGIC;
M_AXI_GP1_RVALID : in STD_LOGIC;
M_AXI_GP1_WREADY : in STD_LOGIC;
M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 5 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component cpu_processing_system7_0_0;
component cpu_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 15 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component cpu_axi_gpio_0_0;
component cpu_rst_processing_system7_0_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu_rst_processing_system7_0_100M_0;
component cpu_axi_iic_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
iic2intc_irpt : out STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
sda_i : in STD_LOGIC;
sda_o : out STD_LOGIC;
sda_t : out STD_LOGIC;
scl_i : in STD_LOGIC;
scl_o : out STD_LOGIC;
scl_t : out STD_LOGIC;
gpo : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu_axi_iic_0_0;
component cpu_axi_epc_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
prh_clk : in STD_LOGIC;
prh_rst : in STD_LOGIC;
prh_cs_n : out STD_LOGIC_VECTOR ( 0 to 0 );
prh_addr : out STD_LOGIC_VECTOR ( 0 to 31 );
prh_ads : out STD_LOGIC;
prh_be : out STD_LOGIC_VECTOR ( 0 to 3 );
prh_rnw : out STD_LOGIC;
prh_rd_n : out STD_LOGIC;
prh_wr_n : out STD_LOGIC;
prh_burst : out STD_LOGIC;
prh_rdy : in STD_LOGIC_VECTOR ( 0 to 0 );
prh_data_i : in STD_LOGIC_VECTOR ( 0 to 31 );
prh_data_o : out STD_LOGIC_VECTOR ( 0 to 31 );
prh_data_t : out STD_LOGIC_VECTOR ( 0 to 31 )
);
end component cpu_axi_epc_0_0;
component cpu_rst_M_AXI_GP1_ACLK_100M_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component cpu_rst_M_AXI_GP1_ACLK_100M_0;
component cpu_xlconcat_0_0 is
port (
In0 : in STD_LOGIC_VECTOR ( 0 to 0 );
In1 : in STD_LOGIC_VECTOR ( 0 to 0 );
In2 : in STD_LOGIC_VECTOR ( 0 to 0 );
In3 : in STD_LOGIC_VECTOR ( 0 to 0 );
In4 : in STD_LOGIC_VECTOR ( 0 to 0 );
In5 : in STD_LOGIC_VECTOR ( 0 to 0 );
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component cpu_xlconcat_0_0;
component cpu_xadc_wiz_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 10 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
vp_in : in STD_LOGIC;
vn_in : in STD_LOGIC;
user_temp_alarm_out : out STD_LOGIC;
vccint_alarm_out : out STD_LOGIC;
vccaux_alarm_out : out STD_LOGIC;
vccpint_alarm_out : out STD_LOGIC;
vccpaux_alarm_out : out STD_LOGIC;
vccddro_alarm_out : out STD_LOGIC;
ot_out : out STD_LOGIC;
channel_out : out STD_LOGIC_VECTOR ( 4 downto 0 );
eoc_out : out STD_LOGIC;
alarm_out : out STD_LOGIC;
eos_out : out STD_LOGIC;
busy_out : out STD_LOGIC
);
end component cpu_xadc_wiz_0_0;
signal GND_1 : STD_LOGIC;
signal In4_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal In5_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal Int0_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal Int1_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M_AXI_GP0_ACLK_1 : STD_LOGIC;
signal M_AXI_GP1_ACLK_1 : STD_LOGIC;
signal VCC_1 : STD_LOGIC;
signal Vp_Vn_1_V_N : STD_LOGIC;
signal Vp_Vn_1_V_P : STD_LOGIC;
signal axi_epc_0_EPC_INTF_ADDR : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_ADS : STD_LOGIC;
signal axi_epc_0_EPC_INTF_BE : STD_LOGIC_VECTOR ( 0 to 3 );
signal axi_epc_0_EPC_INTF_BURST : STD_LOGIC;
signal axi_epc_0_EPC_INTF_CLK : STD_LOGIC;
signal axi_epc_0_EPC_INTF_CS_N : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_epc_0_EPC_INTF_DATA_I : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_DATA_O : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_DATA_T : STD_LOGIC_VECTOR ( 0 to 31 );
signal axi_epc_0_EPC_INTF_RDY : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_epc_0_EPC_INTF_RD_N : STD_LOGIC;
signal axi_epc_0_EPC_INTF_RNW : STD_LOGIC;
signal axi_epc_0_EPC_INTF_RST : STD_LOGIC;
signal axi_epc_0_EPC_INTF_WR_N : STD_LOGIC;
signal axi_gpio_0_GPIO_TRI_I : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_0_GPIO_TRI_O : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_gpio_0_GPIO_TRI_T : STD_LOGIC_VECTOR ( 15 downto 0 );
signal axi_iic_0_IIC_SCL_I : STD_LOGIC;
signal axi_iic_0_IIC_SCL_O : STD_LOGIC;
signal axi_iic_0_IIC_SCL_T : STD_LOGIC;
signal axi_iic_0_IIC_SDA_I : STD_LOGIC;
signal axi_iic_0_IIC_SDA_O : STD_LOGIC;
signal axi_iic_0_IIC_SDA_T : STD_LOGIC;
signal axi_iic_0_iic2intc_irpt : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_0_SDA_T : STD_LOGIC;
signal processing_system7_0_IIC_1_SCL_I : STD_LOGIC;
signal processing_system7_0_IIC_1_SCL_O : STD_LOGIC;
signal processing_system7_0_IIC_1_SCL_T : STD_LOGIC;
signal processing_system7_0_IIC_1_SDA_I : STD_LOGIC;
signal processing_system7_0_IIC_1_SDA_O : STD_LOGIC;
signal processing_system7_0_IIC_1_SDA_T : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP1_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP1_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP1_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP1_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP1_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP1_WVALID : STD_LOGIC;
signal processing_system7_0_UART_0_RxD : STD_LOGIC;
signal processing_system7_0_UART_0_TxD : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_1_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_1_M00_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M00_AXI_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M01_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M01_AXI_WVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_ARREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_ARVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWADDR : STD_LOGIC_VECTOR ( 10 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_AWREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_AWVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_BVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_RVALID : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WREADY : STD_LOGIC;
signal processing_system7_0_axi_periph_M02_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_axi_periph_M02_AXI_WVALID : STD_LOGIC;
signal rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal rst_processing_system7_0_100M_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal xadc_wiz_0_ip2intc_irpt : STD_LOGIC;
signal xlconcat_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_iic_0_gpo_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_rst_M_AXI_GP1_ACLK_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_M_AXI_GP1_ACLK_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_M_AXI_GP1_ACLK_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_xadc_wiz_0_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_busy_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eoc_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_eos_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_ot_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccddro_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccpaux_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_vccpint_alarm_out_UNCONNECTED : STD_LOGIC;
signal NLW_xadc_wiz_0_channel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
begin
EPC_INTF_addr(0 to 31) <= axi_epc_0_EPC_INTF_ADDR(0 to 31);
EPC_INTF_ads <= axi_epc_0_EPC_INTF_ADS;
EPC_INTF_be(0 to 3) <= axi_epc_0_EPC_INTF_BE(0 to 3);
EPC_INTF_burst <= axi_epc_0_EPC_INTF_BURST;
EPC_INTF_cs_n(0) <= axi_epc_0_EPC_INTF_CS_N(0);
EPC_INTF_data_o(0 to 31) <= axi_epc_0_EPC_INTF_DATA_O(0 to 31);
EPC_INTF_data_t(0 to 31) <= axi_epc_0_EPC_INTF_DATA_T(0 to 31);
EPC_INTF_rd_n <= axi_epc_0_EPC_INTF_RD_N;
EPC_INTF_rnw <= axi_epc_0_EPC_INTF_RNW;
EPC_INTF_wr_n <= axi_epc_0_EPC_INTF_WR_N;
FCLK_CLK0 <= M_AXI_GP0_ACLK_1;
FCLK_RESET0_N <= processing_system7_0_FCLK_RESET0_N;
GPIO_tri_o(15 downto 0) <= axi_gpio_0_GPIO_TRI_O(15 downto 0);
GPIO_tri_t(15 downto 0) <= axi_gpio_0_GPIO_TRI_T(15 downto 0);
IIC_0_scl_o <= processing_system7_0_IIC_0_SCL_O;
IIC_0_scl_t <= processing_system7_0_IIC_0_SCL_T;
IIC_0_sda_o <= processing_system7_0_IIC_0_SDA_O;
IIC_0_sda_t <= processing_system7_0_IIC_0_SDA_T;
IIC_1_scl_o <= processing_system7_0_IIC_1_SCL_O;
IIC_1_scl_t <= processing_system7_0_IIC_1_SCL_T;
IIC_1_sda_o <= processing_system7_0_IIC_1_SDA_O;
IIC_1_sda_t <= processing_system7_0_IIC_1_SDA_T;
IIC_scl_o <= axi_iic_0_IIC_SCL_O;
IIC_scl_t <= axi_iic_0_IIC_SCL_T;
IIC_sda_o <= axi_iic_0_IIC_SDA_O;
IIC_sda_t <= axi_iic_0_IIC_SDA_T;
In4_1(0) <= Int2(0);
In5_1(0) <= Int3(0);
Int0_1(0) <= Int0(0);
Int1_1(0) <= Int1(0);
M_AXI_GP1_ACLK_1 <= OCXO_CLK100;
OCXO_RESETN(0) <= rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0);
UART_0_txd <= processing_system7_0_UART_0_TxD;
Vp_Vn_1_V_N <= Vp_Vn_v_n;
Vp_Vn_1_V_P <= Vp_Vn_v_p;
axi_epc_0_EPC_INTF_CLK <= EPC_INTF_clk;
axi_epc_0_EPC_INTF_DATA_I(0 to 31) <= EPC_INTF_data_i(0 to 31);
axi_epc_0_EPC_INTF_RDY(0) <= EPC_INTF_rdy(0);
axi_epc_0_EPC_INTF_RST <= EPC_INTF_rst;
axi_gpio_0_GPIO_TRI_I(15 downto 0) <= GPIO_tri_i(15 downto 0);
axi_iic_0_IIC_SCL_I <= IIC_scl_i;
axi_iic_0_IIC_SDA_I <= IIC_sda_i;
processing_system7_0_IIC_0_SCL_I <= IIC_0_scl_i;
processing_system7_0_IIC_0_SDA_I <= IIC_0_sda_i;
processing_system7_0_IIC_1_SCL_I <= IIC_1_scl_i;
processing_system7_0_IIC_1_SDA_I <= IIC_1_sda_i;
processing_system7_0_UART_0_RxD <= UART_0_rxd;
GND: unisim.vcomponents.GND
port map (
G => GND_1
);
VCC: unisim.vcomponents.VCC
port map (
P => VCC_1
);
axi_epc_0: component cpu_axi_epc_0_0
port map (
prh_addr(0 to 31) => axi_epc_0_EPC_INTF_ADDR(0 to 31),
prh_ads => axi_epc_0_EPC_INTF_ADS,
prh_be(0 to 3) => axi_epc_0_EPC_INTF_BE(0 to 3),
prh_burst => axi_epc_0_EPC_INTF_BURST,
prh_clk => axi_epc_0_EPC_INTF_CLK,
prh_cs_n(0) => axi_epc_0_EPC_INTF_CS_N(0),
prh_data_i(0 to 31) => axi_epc_0_EPC_INTF_DATA_I(0 to 31),
prh_data_o(0 to 31) => axi_epc_0_EPC_INTF_DATA_O(0 to 31),
prh_data_t(0 to 31) => axi_epc_0_EPC_INTF_DATA_T(0 to 31),
prh_rd_n => axi_epc_0_EPC_INTF_RD_N,
prh_rdy(0) => axi_epc_0_EPC_INTF_RDY(0),
prh_rnw => axi_epc_0_EPC_INTF_RNW,
prh_rst => axi_epc_0_EPC_INTF_RST,
prh_wr_n => axi_epc_0_EPC_INTF_WR_N,
s_axi_aclk => M_AXI_GP1_ACLK_1,
s_axi_araddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_ARADDR(31 downto 0),
s_axi_aresetn => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_1_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_1_M00_AXI_ARVALID,
s_axi_awaddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_AWADDR(31 downto 0),
s_axi_awready => processing_system7_0_axi_periph_1_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_1_M00_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_1_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_1_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_1_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_1_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_1_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_1_M00_AXI_WVALID
);
axi_gpio_0: component cpu_axi_gpio_0_0
port map (
gpio_io_i(15 downto 0) => axi_gpio_0_GPIO_TRI_I(15 downto 0),
gpio_io_o(15 downto 0) => axi_gpio_0_GPIO_TRI_O(15 downto 0),
gpio_io_t(15 downto 0) => axi_gpio_0_GPIO_TRI_T(15 downto 0),
s_axi_aclk => M_AXI_GP0_ACLK_1,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M00_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M00_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
s_axi_bready => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M00_AXI_WVALID(0)
);
axi_iic_0: component cpu_axi_iic_0_0
port map (
gpo(0) => NLW_axi_iic_0_gpo_UNCONNECTED(0),
iic2intc_irpt => axi_iic_0_iic2intc_irpt,
s_axi_aclk => M_AXI_GP0_ACLK_1,
s_axi_araddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(8 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
s_axi_awaddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(8 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
scl_i => axi_iic_0_IIC_SCL_I,
scl_o => axi_iic_0_IIC_SCL_O,
scl_t => axi_iic_0_IIC_SCL_T,
sda_i => axi_iic_0_IIC_SDA_I,
sda_o => axi_iic_0_IIC_SDA_O,
sda_t => axi_iic_0_IIC_SDA_T
);
processing_system7_0: component cpu_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
ENET0_PTP_DELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_DELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED,
ENET0_PTP_PDELAY_REQ_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_RX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED,
ENET0_PTP_PDELAY_RESP_TX => NLW_processing_system7_0_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_RX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED,
ENET0_PTP_SYNC_FRAME_TX => NLW_processing_system7_0_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED,
ENET0_SOF_RX => NLW_processing_system7_0_ENET0_SOF_RX_UNCONNECTED,
ENET0_SOF_TX => NLW_processing_system7_0_ENET0_SOF_TX_UNCONNECTED,
FCLK_CLK0 => M_AXI_GP0_ACLK_1,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
I2C0_SCL_I => processing_system7_0_IIC_0_SCL_I,
I2C0_SCL_O => processing_system7_0_IIC_0_SCL_O,
I2C0_SCL_T => processing_system7_0_IIC_0_SCL_T,
I2C0_SDA_I => processing_system7_0_IIC_0_SDA_I,
I2C0_SDA_O => processing_system7_0_IIC_0_SDA_O,
I2C0_SDA_T => processing_system7_0_IIC_0_SDA_T,
I2C1_SCL_I => processing_system7_0_IIC_1_SCL_I,
I2C1_SCL_O => processing_system7_0_IIC_1_SCL_O,
I2C1_SCL_T => processing_system7_0_IIC_1_SCL_T,
I2C1_SDA_I => processing_system7_0_IIC_1_SDA_I,
I2C1_SDA_O => processing_system7_0_IIC_1_SDA_O,
I2C1_SDA_T => processing_system7_0_IIC_1_SDA_T,
IRQ_F2P(5 downto 0) => xlconcat_0_dout(5 downto 0),
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => M_AXI_GP0_ACLK_1,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
M_AXI_GP1_ACLK => M_AXI_GP1_ACLK_1,
M_AXI_GP1_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP1_ARADDR(31 downto 0),
M_AXI_GP1_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP1_ARBURST(1 downto 0),
M_AXI_GP1_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP1_ARCACHE(3 downto 0),
M_AXI_GP1_ARID(11 downto 0) => processing_system7_0_M_AXI_GP1_ARID(11 downto 0),
M_AXI_GP1_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP1_ARLEN(3 downto 0),
M_AXI_GP1_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP1_ARLOCK(1 downto 0),
M_AXI_GP1_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP1_ARPROT(2 downto 0),
M_AXI_GP1_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP1_ARQOS(3 downto 0),
M_AXI_GP1_ARREADY => processing_system7_0_M_AXI_GP1_ARREADY,
M_AXI_GP1_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP1_ARSIZE(2 downto 0),
M_AXI_GP1_ARVALID => processing_system7_0_M_AXI_GP1_ARVALID,
M_AXI_GP1_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP1_AWADDR(31 downto 0),
M_AXI_GP1_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP1_AWBURST(1 downto 0),
M_AXI_GP1_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP1_AWCACHE(3 downto 0),
M_AXI_GP1_AWID(11 downto 0) => processing_system7_0_M_AXI_GP1_AWID(11 downto 0),
M_AXI_GP1_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP1_AWLEN(3 downto 0),
M_AXI_GP1_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP1_AWLOCK(1 downto 0),
M_AXI_GP1_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP1_AWPROT(2 downto 0),
M_AXI_GP1_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP1_AWQOS(3 downto 0),
M_AXI_GP1_AWREADY => processing_system7_0_M_AXI_GP1_AWREADY,
M_AXI_GP1_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP1_AWSIZE(2 downto 0),
M_AXI_GP1_AWVALID => processing_system7_0_M_AXI_GP1_AWVALID,
M_AXI_GP1_BID(11 downto 0) => processing_system7_0_M_AXI_GP1_BID(11 downto 0),
M_AXI_GP1_BREADY => processing_system7_0_M_AXI_GP1_BREADY,
M_AXI_GP1_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP1_BRESP(1 downto 0),
M_AXI_GP1_BVALID => processing_system7_0_M_AXI_GP1_BVALID,
M_AXI_GP1_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP1_RDATA(31 downto 0),
M_AXI_GP1_RID(11 downto 0) => processing_system7_0_M_AXI_GP1_RID(11 downto 0),
M_AXI_GP1_RLAST => processing_system7_0_M_AXI_GP1_RLAST,
M_AXI_GP1_RREADY => processing_system7_0_M_AXI_GP1_RREADY,
M_AXI_GP1_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP1_RRESP(1 downto 0),
M_AXI_GP1_RVALID => processing_system7_0_M_AXI_GP1_RVALID,
M_AXI_GP1_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP1_WDATA(31 downto 0),
M_AXI_GP1_WID(11 downto 0) => processing_system7_0_M_AXI_GP1_WID(11 downto 0),
M_AXI_GP1_WLAST => processing_system7_0_M_AXI_GP1_WLAST,
M_AXI_GP1_WREADY => processing_system7_0_M_AXI_GP1_WREADY,
M_AXI_GP1_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP1_WSTRB(3 downto 0),
M_AXI_GP1_WVALID => processing_system7_0_M_AXI_GP1_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
UART0_RX => processing_system7_0_UART_0_RxD,
UART0_TX => processing_system7_0_UART_0_TxD,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => GND_1,
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
processing_system7_0_axi_periph: entity work.cpu_processing_system7_0_axi_periph_0
port map (
ACLK => M_AXI_GP0_ACLK_1,
ARESETN(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
M00_ACLK => M_AXI_GP0_ACLK_1,
M00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M00_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_ARADDR(8 downto 0),
M00_AXI_arready(0) => processing_system7_0_axi_periph_M00_AXI_ARREADY,
M00_AXI_arvalid(0) => processing_system7_0_axi_periph_M00_AXI_ARVALID(0),
M00_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M00_AXI_AWADDR(8 downto 0),
M00_AXI_awready(0) => processing_system7_0_axi_periph_M00_AXI_AWREADY,
M00_AXI_awvalid(0) => processing_system7_0_axi_periph_M00_AXI_AWVALID(0),
M00_AXI_bready(0) => processing_system7_0_axi_periph_M00_AXI_BREADY(0),
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid(0) => processing_system7_0_axi_periph_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready(0) => processing_system7_0_axi_periph_M00_AXI_RREADY(0),
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid(0) => processing_system7_0_axi_periph_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready(0) => processing_system7_0_axi_periph_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid(0) => processing_system7_0_axi_periph_M00_AXI_WVALID(0),
M01_ACLK => M_AXI_GP0_ACLK_1,
M01_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M01_AXI_araddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_ARADDR(8 downto 0),
M01_AXI_arready => processing_system7_0_axi_periph_M01_AXI_ARREADY,
M01_AXI_arvalid => processing_system7_0_axi_periph_M01_AXI_ARVALID,
M01_AXI_awaddr(8 downto 0) => processing_system7_0_axi_periph_M01_AXI_AWADDR(8 downto 0),
M01_AXI_awready => processing_system7_0_axi_periph_M01_AXI_AWREADY,
M01_AXI_awvalid => processing_system7_0_axi_periph_M01_AXI_AWVALID,
M01_AXI_bready => processing_system7_0_axi_periph_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => processing_system7_0_axi_periph_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => processing_system7_0_axi_periph_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => processing_system7_0_axi_periph_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => processing_system7_0_axi_periph_M01_AXI_WREADY,
M01_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M01_AXI_WSTRB(3 downto 0),
M01_AXI_wvalid => processing_system7_0_axi_periph_M01_AXI_WVALID,
M02_ACLK => M_AXI_GP0_ACLK_1,
M02_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
M02_AXI_araddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(10 downto 0),
M02_AXI_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
M02_AXI_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
M02_AXI_awaddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(10 downto 0),
M02_AXI_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
M02_AXI_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
M02_AXI_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
M02_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
M02_AXI_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
M02_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
M02_AXI_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
M02_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
M02_AXI_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
M02_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
M02_AXI_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
M02_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
M02_AXI_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
S00_ACLK => M_AXI_GP0_ACLK_1,
S00_ARESETN(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
processing_system7_0_axi_periph_1: entity work.cpu_processing_system7_0_axi_periph_1_0
port map (
ACLK => M_AXI_GP1_ACLK_1,
ARESETN(0) => rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn(0),
M00_ACLK => M_AXI_GP1_ACLK_1,
M00_ARESETN(0) => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arready => processing_system7_0_axi_periph_1_M00_AXI_ARREADY,
M00_AXI_arvalid => processing_system7_0_axi_periph_1_M00_AXI_ARVALID,
M00_AXI_awaddr(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_AWADDR(31 downto 0),
M00_AXI_awready => processing_system7_0_axi_periph_1_M00_AXI_AWREADY,
M00_AXI_awvalid => processing_system7_0_axi_periph_1_M00_AXI_AWVALID,
M00_AXI_bready => processing_system7_0_axi_periph_1_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => processing_system7_0_axi_periph_1_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => processing_system7_0_axi_periph_1_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => processing_system7_0_axi_periph_1_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => processing_system7_0_axi_periph_1_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => processing_system7_0_axi_periph_1_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => processing_system7_0_axi_periph_1_M00_AXI_WVALID,
S00_ACLK => M_AXI_GP1_ACLK_1,
S00_ARESETN(0) => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP1_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP1_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP1_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP1_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP1_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP1_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP1_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP1_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP1_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP1_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP1_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP1_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP1_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP1_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP1_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP1_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP1_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP1_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP1_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP1_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP1_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP1_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP1_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP1_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP1_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP1_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP1_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP1_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP1_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP1_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP1_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP1_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP1_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP1_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP1_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP1_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP1_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP1_WVALID
);
rst_M_AXI_GP1_ACLK_100M: component cpu_rst_M_AXI_GP1_ACLK_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_M_AXI_GP1_ACLK_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_M_AXI_GP1_ACLK_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_M_AXI_GP1_ACLK_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_M_AXI_GP1_ACLK_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_M_AXI_GP1_ACLK_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => M_AXI_GP1_ACLK_1
);
rst_processing_system7_0_100M: component cpu_rst_processing_system7_0_100M_0
port map (
aux_reset_in => VCC_1,
bus_struct_reset(0) => NLW_rst_processing_system7_0_100M_bus_struct_reset_UNCONNECTED(0),
dcm_locked => VCC_1,
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => rst_processing_system7_0_100M_interconnect_aresetn(0),
mb_debug_sys_rst => GND_1,
mb_reset => NLW_rst_processing_system7_0_100M_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => rst_processing_system7_0_100M_peripheral_aresetn(0),
peripheral_reset(0) => NLW_rst_processing_system7_0_100M_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => M_AXI_GP0_ACLK_1
);
xadc_wiz_0: component cpu_xadc_wiz_0_0
port map (
alarm_out => NLW_xadc_wiz_0_alarm_out_UNCONNECTED,
busy_out => NLW_xadc_wiz_0_busy_out_UNCONNECTED,
channel_out(4 downto 0) => NLW_xadc_wiz_0_channel_out_UNCONNECTED(4 downto 0),
eoc_out => NLW_xadc_wiz_0_eoc_out_UNCONNECTED,
eos_out => NLW_xadc_wiz_0_eos_out_UNCONNECTED,
ip2intc_irpt => xadc_wiz_0_ip2intc_irpt,
ot_out => NLW_xadc_wiz_0_ot_out_UNCONNECTED,
s_axi_aclk => M_AXI_GP0_ACLK_1,
s_axi_araddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_ARADDR(10 downto 0),
s_axi_aresetn => rst_processing_system7_0_100M_peripheral_aresetn(0),
s_axi_arready => processing_system7_0_axi_periph_M02_AXI_ARREADY,
s_axi_arvalid => processing_system7_0_axi_periph_M02_AXI_ARVALID,
s_axi_awaddr(10 downto 0) => processing_system7_0_axi_periph_M02_AXI_AWADDR(10 downto 0),
s_axi_awready => processing_system7_0_axi_periph_M02_AXI_AWREADY,
s_axi_awvalid => processing_system7_0_axi_periph_M02_AXI_AWVALID,
s_axi_bready => processing_system7_0_axi_periph_M02_AXI_BREADY,
s_axi_bresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_BRESP(1 downto 0),
s_axi_bvalid => processing_system7_0_axi_periph_M02_AXI_BVALID,
s_axi_rdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_RDATA(31 downto 0),
s_axi_rready => processing_system7_0_axi_periph_M02_AXI_RREADY,
s_axi_rresp(1 downto 0) => processing_system7_0_axi_periph_M02_AXI_RRESP(1 downto 0),
s_axi_rvalid => processing_system7_0_axi_periph_M02_AXI_RVALID,
s_axi_wdata(31 downto 0) => processing_system7_0_axi_periph_M02_AXI_WDATA(31 downto 0),
s_axi_wready => processing_system7_0_axi_periph_M02_AXI_WREADY,
s_axi_wstrb(3 downto 0) => processing_system7_0_axi_periph_M02_AXI_WSTRB(3 downto 0),
s_axi_wvalid => processing_system7_0_axi_periph_M02_AXI_WVALID,
user_temp_alarm_out => NLW_xadc_wiz_0_user_temp_alarm_out_UNCONNECTED,
vccaux_alarm_out => NLW_xadc_wiz_0_vccaux_alarm_out_UNCONNECTED,
vccddro_alarm_out => NLW_xadc_wiz_0_vccddro_alarm_out_UNCONNECTED,
vccint_alarm_out => NLW_xadc_wiz_0_vccint_alarm_out_UNCONNECTED,
vccpaux_alarm_out => NLW_xadc_wiz_0_vccpaux_alarm_out_UNCONNECTED,
vccpint_alarm_out => NLW_xadc_wiz_0_vccpint_alarm_out_UNCONNECTED,
vn_in => Vp_Vn_1_V_N,
vp_in => Vp_Vn_1_V_P
);
xlconcat_0: component cpu_xlconcat_0_0
port map (
In0(0) => axi_iic_0_iic2intc_irpt,
In1(0) => xadc_wiz_0_ip2intc_irpt,
In2(0) => Int0_1(0),
In3(0) => Int1_1(0),
In4(0) => In4_1(0),
In5(0) => In5_1(0),
dout(5 downto 0) => xlconcat_0_dout(5 downto 0)
);
end STRUCTURE;
| gpl-3.0 | 15a5830dd5b02b3261abaf2774552406 | 0.682413 | 2.769526 | false | false | false | false |
peteut/nvc | test/regress/issue309.vhd | 2 | 1,149 | -- test_ng.vhd
use std.textio.all;
entity issue309 is
end issue309;
architecture MODEL of issue309 is
begin
process
constant org_data : bit_vector(31 downto 0) := "01110110010101000011001000010000";
variable val_data : bit_vector(31 downto 0);
variable text_line : LINE;
begin
val_data := (others => '0');
for i in 7 downto 0 loop
write(text_line, string'("val_data="));
write(text_line, val_data);
val_data(31 downto 4) := val_data(27 downto 0);
val_data( 3 downto 0) := org_data(i*4+3 downto i*4);
write(text_line, string'("=>"));
write(text_line, val_data);
writeline(OUTPUT, text_line);
end loop;
if (val_data /= org_data) then
write(text_line, string'("NG:org_data="));
write(text_line, org_data);
writeline(OUTPUT, text_line);
write(text_line, string'(" val_data="));
write(text_line, val_data);
writeline(OUTPUT, text_line);
assert false;
end if;
wait;
end process;
end MODEL;
| gpl-3.0 | 3d55468896c5b0909fc9a6f4ca211292 | 0.543951 | 3.754902 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/example_design/counter_fifo_exdes.vhd | 1 | 5,098 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity counter_fifo_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end counter_fifo_exdes;
architecture xilinx of counter_fifo_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component counter_fifo is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : counter_fifo
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | 6312b0e99aecb33c797948fb8eed16fe | 0.521185 | 4.836812 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/io.vhd | 1 | 8,386 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : io.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-21
-- Last update: 2016-08-17
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: GPIO tri-state buffer and clock domain transfer
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-21 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
--
-- Address range: 0x412_0000 - 0x4120_0004
-- | 1 | 0 |
-- |5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
-- default T T T T T T T T 0 0 T 1 T T 1 1
--
-- 0x4120_0000 | gpio |d|a| |g| |l|p|o| Read/Write
-- | | | | | |
-- | | | | | OCXO enable (power) R/W
-- | | | | PLL reset bar R/W
-- | | | PLL Locked R
-- | | GPS enable (power) R/W
-- | DAC Controller enable R/W
-- Display controller enable R/W
--
-- 0x4120_0004 | | | Tri state control
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
entity io is
port (
fclk_rst_n : in std_logic;
fclk : in std_logic;
rst_n : in std_logic;
clk : in std_logic;
-- fclk
GPIO_tri_i : out std_logic_vector (15 downto 0);
GPIO_tri_o : in std_logic_vector (15 downto 0);
GPIO_tri_t : in std_logic_vector (15 downto 0);
-- clk
locked : in std_logic;
dac_ena : out std_logic;
dac_tri : out std_logic;
disp_ena : out std_logic;
-- fclk
pll_rst_n : out std_logic;
ocxo_ena : inout std_logic;
gps_ena : inout std_logic;
gps_tri : out std_logic;
gpio : inout std_logic_vector (7 DOWNTO 0)
);
end io;
architecture rtl of io is
component IOBUF is
port (
I : in STD_LOGIC;
O : out STD_LOGIC;
T : in STD_LOGIC;
IO : inout STD_LOGIC
);
end component IOBUF;
signal gpio_o_d : std_logic_vector (15 downto 0);
signal gpio_t_d : std_logic_vector (15 downto 0);
signal reset_n : std_logic;
signal ocxo_ena_tri : std_logic;
signal ocxo_pwr_ena : std_logic;
signal ocxo_pwr_on : std_logic;
signal ocxo_on_ctr : std_logic_vector(12 downto 0); -- 25 us turn on
signal gps_ena_tri : std_logic;
signal gps_pwr_ena : std_logic;
signal gps_pwr_on : std_logic;
signal gps_on_ctr : std_logic_vector(12 downto 0);
attribute keep : string;
attribute keep of gps_pwr_ena : signal is "true";
begin
-- Generic gpio interface output register
io_oreg: delay_vec generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_o, gpio_o_d);
io_treg: delay_vec generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_t, gpio_t_d);
-- gpio control interface
-- gpio(0)
ocxo_ena <= gpio_o_d(0) when gpio_t_d(0) = '0' else 'Z';
xtal_ena: delay_sig generic map (1) port map (fclk_rst_n, fclk, ocxo_ena, GPIO_tri_i(0));
xtal_pwr: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(0), ocxo_pwr_ena);
-- gpio(1)
reset_n <= gpio_o_d(1) and fclk_rst_n;
GPIO_tri_i(1) <= reset_n;
pll_rst_n <= reset_n;
-- gpio(2)
pll_lock: delay_sig generic map (2) port map (fclk_rst_n, fclk, locked, GPIO_tri_i(2));
-- gpio(3)
GPIO_tri_i(3) <= '0';
-- gpio(4)
gps_ena <= gpio_o_d(4) when gpio_t_d(4) = '0' else 'Z';
loc_ena: delay_sig generic map (1) port map (fclk_rst_n, fclk, gps_ena, GPIO_tri_i(4));
-- gpio(5)
GPIO_tri_i(5) <= '0';
-- gpio(6)
gpio_dac_ena: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(6), dac_ena);
GPIO_tri_i(6) <= GPIO_tri_o(6);
-- gpio(7)
gpio_disp_ena: delay_sig generic map (2) port map (rst_n, clk, GPIO_tri_o(7), disp_ena);
GPIO_tri_i(7) <= GPIO_tri_o(7);
-- gpio(15 downto 8)
io_tri: for i in 8 to 15 generate
begin
--io_tri_iobuf: component IOBUF
-- port map (
-- I => GPIO_tri_o(i),
-- IO => gpio(i),
-- O => GPIO_tri_i(i),
-- T => GPIO_tri_t(i)
-- );
gpio(i - 8) <= gpio_o_d(i) when gpio_t_d(i) = '0' else 'Z';
end generate;
io_ireg: delay_vec generic map (1) port map (fclk_rst_n, fclk, gpio, GPIO_tri_i(15 downto 8));
--gpio(0) <= gpio_o_d(8) when gpio_t_d(8) = '0' else 'Z';
--gpio(1) <= gpio_o_d(9) when gpio_t_d(9) = '0' else 'Z';
--gpio(2) <= gpio_o_d(10) when gpio_t_d(10) = '0' else 'Z';
--gpio(3) <= gpio_o_d(11) when gpio_t_d(11) = '0' else 'Z';
--gpio(4) <= gpio_o_d(12) when gpio_t_d(12) = '0' else 'Z';
--gpio(5) <= gpio_o_d(13) when gpio_t_d(13) = '0' else 'Z';
--gpio(6) <= gpio_o_d(14) when gpio_t_d(14) = '0' else 'Z';
--gpio(7) <= gpio_o_d(15) when gpio_t_d(15) = '0' else 'Z';
-- The ocxo dac 50 us tristate enable delay
ocxo_tristate:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ocxo_on_ctr <= conv_std_logic_vector(5000, ocxo_on_ctr'length);
ocxo_pwr_on <= '0';
dac_tri <= '1';
elsif (clk'event and clk = '1') then
if (ocxo_pwr_ena = '0' or ocxo_pwr_on = '1') then
ocxo_on_ctr <= conv_std_logic_vector(5000, ocxo_on_ctr'length);
else
ocxo_on_ctr <= ocxo_on_ctr - 1;
end if;
if (ocxo_pwr_ena = '0') then
ocxo_pwr_on <= '0';
elsif (ocxo_on_ctr = 1) then
ocxo_pwr_on <= '1';
else
ocxo_pwr_on <= '0';
end if;
if (ocxo_pwr_ena = '0') then
dac_tri <= '1';
elsif (ocxo_pwr_on = '1') then
dac_tri <= '0';
end if;
end if;
end process;
--loc_pwr: delay_sig generic map (1) port map (fclk_rst_n, fclk, GPIO_tri_o(4), gps_pwr_ena);
-- Duplicate output buffer for enable
gps_ena_dup:
process (fclk_rst_n, fclk) is
begin
if (fclk_rst_n = '0') then
gps_pwr_ena <= '0';
elsif (fclk'event and fclk = '1') then
gps_pwr_ena <= GPIO_tri_o(4);
end if;
end process;
-- The gps rs232 tx 50 us tristate enable delay
gps_tristate:
process (fclk_rst_n, fclk) is
begin
if (fclk_rst_n = '0') then
gps_on_ctr <= conv_std_logic_vector(5000, gps_on_ctr'length);
gps_pwr_on <= '0';
gps_tri <= '1';
elsif (fclk'event and fclk = '1') then
if (gps_pwr_ena = '0' or gps_pwr_on = '1') then
gps_on_ctr <= conv_std_logic_vector(5000, gps_on_ctr'length);
else
gps_on_ctr <= gps_on_ctr - 1;
end if;
if (gps_pwr_ena = '0') then
gps_pwr_on <= '0';
elsif (gps_on_ctr = 1) then
gps_pwr_on <= '1';
else
gps_pwr_on <= '0';
end if;
if (gps_pwr_ena = '0') then
gps_tri <= '1';
elsif (gps_pwr_on = '1') then
gps_tri <= '0';
end if;
end if;
end process;
end rtl;
| gpl-3.0 | 68463726975757e7a8e83f078a81b6f6 | 0.437038 | 3.19345 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/rx_CplD_Channel.vhd | 1 | 62,074 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_CplD_Transact is
port (
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rdst_rdy_n : IN std_logic; -- !!
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
CplD_Type : IN std_logic_vector(3 downto 0);
Req_ID_Match : IN std_logic;
usDex_Tag_Matched : IN std_logic;
dsDex_Tag_Matched : IN std_logic;
Tlp_has_4KB : IN std_logic;
Tlp_has_1DW : IN std_logic;
CplD_on_Pool : IN std_logic;
CplD_on_EB : IN std_logic;
CplD_is_the_Last : IN std_logic;
CplD_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
FC_pop : OUT std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : OUT std_logic;
ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Tag output to downstream DMA channel
dsDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Handshake Signals with ds Channel for Busy/Done
Tag_Map_Clear : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-- Downstream tRAM port A write request
tRAM_weB : IN std_logic;
tRAM_addrB : IN std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : IN std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- Tag output to upstream DMA channel
usDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : OUT std_logic;
Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
end entity rx_CplD_Transact;
architecture Behavioral of rx_CplD_Transact is
type RxCplDEBStates is ( ST_EBWR_IDLE
, ST_EBWR_TAG
, ST_EBWR_DATA
);
signal EB_Write_State : RxCplDEBStates;
type RxCplDTrnStates is ( ST_CplD_RESET
, ST_CplD_IDLE
-- , ST_Cpl_HEAD1 -- Cpl Header #1 (not used)
-- , ST_CplD_HEAD1 -- CplD Header #1
, ST_Cpl_HEAD2 -- Cpl Header #2 (not used)
, ST_CplD_HEAD2 -- CplD Header #2
, ST_CplD_AFetch_Special --
, ST_CplD_AFetch_Special_Tail --
, ST_CplD_AFetch -- Target address fetch from tRAM/registers
, ST_CplD_AFetch_THROTTLE -- Target address fetch throttled
, ST_CplD_ONLY_1DW -- Current CplD has only 1 DW
-- , ST_CplD_ONLY_1DW_THROTTLE -- Current CplD has only 1 DW, throttled
, ST_CplD_1ST_DATA -- 1st data payload of the CplD
, ST_CplD_1ST_DATA_THROTTLE -- 1st data payload of the CplD
, ST_CplD_DATA -- data receiving
, ST_CplD_DATA_THROTTLE -- data receiving throttled
, ST_CplD_LAST_DATA -- Last data payload of the CplD
);
-- State variables
signal RxCplDTrn_NextState : RxCplDTrnStates;
signal RxCplDTrn_State : RxCplDTrnStates;
-- State delay
signal RxCplDTrn_State_r1 : RxCplDTrnStates;
signal RxCplDTrn_State_r2 : RxCplDTrnStates;
signal CplD_State_is_AFetch : std_logic;
signal CplD_State_is_after_AFetch : std_logic;
signal CplD_State_is_AFetch_r1 : std_logic;
-- Shifted-glued payload
signal concat_rd : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- trn_rx stubs
signal trn_rd_i : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- trn_rd_* in little endian
signal trn_rd_Little : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r1 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r2 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r3 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
signal trn_rd_Little_r4 : std_logic_vector (C_DBUS_WIDTH-1 downto 0);
-- signal trn_rbar_hit_n_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
signal trn_rerrfwd_n_i : std_logic;
signal trn_rsrc_dsc_n_i : std_logic;
signal trn_rsof_n_i : std_logic;
signal trn_reof_n_i : std_logic;
signal trn_reof_n_r1 : std_logic;
signal trn_reof_n_r2 : std_logic;
signal trn_reof_n_r3 : std_logic;
signal trn_reof_n_r4 : std_logic;
-- signal Tlp_has_4KB_r1 : std_logic;
signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r1 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r2 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r3 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rrem_n_r4 : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-- Whether address increases
signal Addr_Inc : std_logic;
-- Spaces hit
-- signal FIFO_Space_Hit : std_logic;
signal DDR_Space_Hit : std_logic;
-- DDR write port
signal DDR_wr_sof_i : std_logic;
signal DDR_wr_eof_i : std_logic;
signal DDR_wr_v_i : std_logic;
signal DDR_wr_FA_i : std_logic;
signal DDR_wr_Shift_i : std_logic;
signal DDR_wr_Mask_i : std_logic_vector(2-1 downto 0);
signal DDR_wr_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_wr_full_i : std_logic;
-- Event Buffer write port
signal eb_FIFO_we_i : std_logic;
signal eb_FIFO_wsof_i : std_logic;
signal eb_FIFO_weof_i : std_logic;
signal eb_FIFO_sof_marker : std_logic;
signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Register write port
signal Regs_WrEn_i : std_logic;
signal Regs_WrMask_i : std_logic_vector(2-1 downto 0);
signal Regs_WrAddr_i : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Regs_WrDin_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation @ trn_rsof_n=0
signal Dex_CplD_Illegal : std_logic;
signal Reg_WrAddr_if_last_us: std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal Reg_WrAddr_if_last_ds: std_logic_vector(C_EP_AWIDTH-1 downto 0);
-- Flow control signals
signal trn_rdst_rdy_n_i : std_logic;
signal trn_rsrc_rdy_n_i : std_logic;
signal trn_rsrc_rdy_n_r1 : std_logic;
signal trn_rsrc_rdy_n_r2 : std_logic;
signal trn_rsrc_rdy_n_r3 : std_logic;
signal trn_rsrc_rdy_n_r4 : std_logic;
signal trn_rx_throttle : std_logic;
signal trn_rx_throttle_r1 : std_logic;
signal trn_rx_throttle_r2 : std_logic;
signal trn_rx_throttle_r3 : std_logic;
signal trn_rx_throttle_r4 : std_logic;
-- Downstream DMA transferred bytes count up
signal ds_DMA_Bytes_Add_i : std_logic;
signal ds_DMA_Bytes_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
signal CplD_is_Payloaded : std_logic;
-- Alias for header resolution
signal CplD_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG downto 0);
signal CplD_Leng_in_Bytes : std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_Leng_in_Bytes_r1: std_logic_vector(C_DBUS_WIDTH/2-1 downto 0);
signal CplD_is_1DW : std_logic;
-- Small_CplD means CplD with less than 4 DW payload
signal Small_CplD : std_logic;
signal Small_CplD_r1 : std_logic;
signal RegAddr_us_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal RegAddr_ds_Dex : std_logic_vector(C_EP_AWIDTH-1 downto 0);
signal CplD_Tag_on_Dex : std_logic;
-- ----------------------------------------------------------------------
signal Req_ID_Match_i : std_logic;
signal Dex_Tag_Matched_i : std_logic;
-- The top bit of the CplD_Tag is for distinguishing data CplD or descriptor CplD
signal MSB_DSP_Tag : std_logic;
signal MSB_DSP_Tag_r1 : std_logic;
signal DSP_Tag_on_RAM : std_logic;
signal DSP_Tag_on_RAM_r1 : std_logic;
signal DSP_Tag_on_RAM_r2 : std_logic;
signal DSP_Tag_on_RAM_r3 : std_logic;
signal DSP_Tag_on_RAM_r4p : std_logic;
signal DSP_Tag_on_FIFO : std_logic;
-- ----------------------------------------------------------------------
signal FC_pop_i : std_logic;
signal Tag_Map_Clear_i : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal Local_Reset_i : std_logic;
-- upstream Descriptors' tags
signal usDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- downstream Descriptors' tags
signal dsDMA_dex_Tag_i : std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- --- ------------------------------------------
-- --- Dual port Block Memory, used as tag RAM
-- component
-- v5tagram64x36
-- port (
-- clka : IN std_logic;
-- addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
-- wea : IN std_logic_vector(0 downto 0);
-- dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
-- douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
-- clkb : IN std_logic;
-- addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
-- web : IN std_logic_vector(0 downto 0);
-- dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
-- doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
-- );
-- end component;
--- ------------------------------------------
--- Dual port Block Memory, used as tag RAM
component
FF_TagRam64x36
port (
clk : IN std_logic;
addra : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
wea : IN std_logic;
dina : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
douta : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
addrb : IN std_logic_VECTOR(C_TAGRAM_AWIDTH-1 downto 0);
web : IN std_logic;
dinb : IN std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0);
doutb : OUT std_logic_VECTOR(C_TAGRAM_DWIDTH-1 downto 0)
);
end component;
signal tRAM_wea : std_logic_vector(0 downto 0);
signal tRAM_addra : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_dina : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_doutA : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_weB_i : std_logic_vector(0 downto 0);
signal tRAM_DoutA_r1 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_r2 : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_dina_aInc : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tRAM_DoutA_latch : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- updates the tag RAM as soon as possible
signal CplD_is_the_Last_r1 : std_logic;
signal Updates_tRAM : std_logic;
signal Updates_tRAM_r1 : std_logic;
signal Update_was_too_late : std_logic;
signal hazard_update : std_logic;
signal hazard_update_r1 : std_logic;
signal hazard_update_r2 : std_logic;
signal hazard_update_r3 : std_logic;
signal hazard_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal hazard_content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal tag_matches_hazard : std_logic;
-- aka TLB unit
signal TLB_Addr : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal TLB_Content : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
signal TLB_cnt : std_logic_vector(4-1 downto 0);
signal TLB_Valid : std_logic;
signal TLB_Hit : std_logic;
Constant C_TLB_VALID_CNT : std_logic_vector(4-1 downto 0) := X"6";
begin
-- Event Buffer write
eb_FIFO_we <= eb_FIFO_we_i ;
eb_FIFO_wsof <= eb_FIFO_wsof_i ;
eb_FIFO_weof <= eb_FIFO_weof_i ;
eb_FIFO_din <= eb_FIFO_din_i ;
-- DDR
DDR_wr_sof <= DDR_wr_sof_i ;
DDR_wr_eof <= DDR_wr_eof_i ;
DDR_wr_v <= DDR_wr_v_i ;
DDR_wr_FA <= DDR_wr_FA_i ;
DDR_wr_Shift <= DDR_wr_Shift_i ;
DDR_wr_Mask <= DDR_wr_Mask_i ;
DDR_wr_din <= DDR_wr_din_i ;
DDR_wr_full_i <= DDR_wr_full ;
ds_DMA_Bytes_Add <= ds_DMA_Bytes_Add_i ;
ds_DMA_Bytes <= ds_DMA_Bytes_i ;
--
Tag_Map_Clear <= Tag_Map_Clear_i;
--
FC_pop <= FC_pop_i;
-- ----------------------------------------------
--
Syn_FC_pop:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
FC_pop_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
FC_pop_i <= (CplD_on_Pool or CplD_on_EB)
and CplD_is_the_Last
and not MSB_DSP_Tag
and not trn_reof_n_i
and trn_reof_n_r1 -- Catch the falling edge of trn_reof_n
-- and not trn_rx_throttle
;
end if;
end process;
-- ----------------------------------------------
-- Synchronous: CplD_is_Payloaded
--
Syn_CplD_is_Payloaded:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_is_Payloaded <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' and trn_rx_throttle='0' then
CplD_is_Payloaded <= CplD_Type(3) or CplD_Type(1);
else
CplD_is_Payloaded <= CplD_is_Payloaded;
end if;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Accumulation: us_DMA_Bytes
--
Syn_ds_DMA_Bytes_Add:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
ds_DMA_Bytes_Add_i <= '0' ;
ds_DMA_Bytes_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if trn_reof_n_i='0' and trn_rx_throttle='0'
and CplD_is_Payloaded='1' and MSB_DSP_Tag='0'
then
ds_DMA_Bytes_Add_i <= '1' ;
ds_DMA_Bytes_i <= CplD_Leng_in_Bytes(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
else
ds_DMA_Bytes_Add_i <= '0' ;
ds_DMA_Bytes_i <= (OTHERS=>'0');
end if;
end if;
end process;
-- Registers writing
Regs_WrEn <= Regs_WrEn_i;
Regs_WrMask <= Regs_WrMask_i;
Regs_WrAddr <= Regs_WrAddr_i;
Regs_WrDin <= Regs_WrDin_i;
--- Dex Tag output to us DMA channel
usDMA_dex_Tag <= usDMA_dex_Tag_i;
--- Dex Tag output to ds DMA channel
dsDMA_dex_Tag <= dsDMA_dex_Tag_i;
---------------------------------------------------
Req_ID_Match_i <= Req_ID_Match;
Dex_Tag_Matched_i <= usDex_Tag_Matched or dsDex_Tag_Matched;
-- positive reset
Local_Reset_i <= not trn_reset_n;
-- Frame signals
trn_rsof_n_i <= trn_rsof_n;
trn_reof_n_i <= trn_reof_n;
trn_rd_i <= trn_rd;
trn_rrem_n_i <= trn_rrem_n;
trn_rsrc_rdy_n_i <= trn_rsrc_rdy_n;
trn_rdst_rdy_n_i <= trn_rdst_rdy_n;
-- BC of the current TLP payloads
CplD_Leng_in_Bytes <= C_ALL_ZEROS(C_DBUS_WIDTH/2-1 downto C_TLP_FLD_WIDTH_OF_LENG+3)
& CplD_Length & "00";
-- Exception signals
trn_rerrfwd_n_i <= trn_rerrfwd_n;
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
trn_rx_throttle <= trn_rsrc_rdy_n_i or trn_rdst_rdy_n_i;
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_AFetch
--
RxFSM_CplD_State_is_AFetch:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
CplD_State_is_AFetch_r1 <= CplD_State_is_AFetch;
case RxCplDTrn_State is
when ST_CplD_AFetch =>
CplD_State_is_AFetch <= '1';
when ST_CplD_AFetch_Special =>
CplD_State_is_AFetch <= '1';
when OTHERS =>
CplD_State_is_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Synchronous bit: CplD_State_is_after_AFetch
--
RxFSM_CplD_State_is_after_AFetch:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch_Special_Tail =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_ONLY_1DW =>
CplD_State_is_after_AFetch <= '1';
when ST_CplD_1ST_DATA =>
CplD_State_is_after_AFetch <= '1';
when OTHERS =>
CplD_State_is_after_AFetch <= '0';
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: trn_r*
--
Syn_Delay_trn_r_x:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_reof_n_r1 <= trn_reof_n_i;
trn_reof_n_r2 <= trn_reof_n_r1;
trn_reof_n_r3 <= trn_reof_n_r2;
trn_reof_n_r4 <= trn_reof_n_r3;
trn_rsrc_rdy_n_r1 <= trn_rx_throttle; -- trn_rsrc_rdy_n_i;
trn_rsrc_rdy_n_r2 <= trn_rsrc_rdy_n_r1;
trn_rsrc_rdy_n_r3 <= trn_rsrc_rdy_n_r2;
trn_rsrc_rdy_n_r4 <= trn_rsrc_rdy_n_r3;
trn_rx_throttle_r1 <= trn_rx_throttle;
trn_rx_throttle_r2 <= trn_rx_throttle_r1;
trn_rx_throttle_r3 <= trn_rx_throttle_r2;
trn_rx_throttle_r4 <= trn_rx_throttle_r3;
-- DDR_wr_full_r1 <= DDR_wr_full_i;
-- DDR_wr_full_r2 <= DDR_wr_full_r1;
trn_rd_r1 <= trn_rd_i;
trn_rd_r2 <= trn_rd_r1;
trn_rd_r3 <= trn_rd_r2;
trn_rd_r4 <= trn_rd_r3;
trn_rrem_n_r1 <= trn_rrem_n_i;
trn_rrem_n_r2 <= trn_rrem_n_r1;
trn_rrem_n_r3 <= trn_rrem_n_r2;
trn_rrem_n_r4 <= trn_rrem_n_r3;
end if;
end process;
-- Endian reversed
trn_rd_Little <= Endian_Invert_64 (trn_rd_i);
trn_rd_Little_r1 <= Endian_Invert_64 (trn_rd_r1);
trn_rd_Little_r2 <= Endian_Invert_64 (trn_rd_r2);
trn_rd_Little_r3 <= Endian_Invert_64 (trn_rd_r3);
trn_rd_Little_r4 <= Endian_Invert_64 (trn_rd_r4);
-- ---------------------------------------------
MSB_DSP_Tag <= CplD_Tag(C_TAG_WIDTH-1);
DSP_Tag_on_RAM <= not CplD_Tag(C_TAG_WIDTH-1) and not CplD_Tag(C_TAG_WIDTH-2);
DSP_Tag_on_FIFO <= not CplD_Tag(C_TAG_WIDTH-1) and CplD_Tag(C_TAG_WIDTH-2);
--
-- Delay Synchronous: MSB_DSP_Tag_r1
--
Syn_Delay_MSB_DSP_Tag_r1:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
MSB_DSP_Tag_r1 <= MSB_DSP_Tag;
DSP_Tag_on_RAM_r1 <= DSP_Tag_on_RAM;
DSP_Tag_on_RAM_r2 <= DSP_Tag_on_RAM_r1;
DSP_Tag_on_RAM_r3 <= DSP_Tag_on_RAM_r2;
DSP_Tag_on_RAM_r4p <= DSP_Tag_on_RAM_r2 or DSP_Tag_on_RAM_r3;
end if;
end process;
--
-- Delay Synchronous: CplD_Leng_in_Bytes
--
Syn_Delay_CplD_Leng_in_Bytes:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
CplD_Leng_in_Bytes_r1 <= CplD_Leng_in_Bytes;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: RxCplDTrn_State
--
RxFSM_Delay_RxTrn_State:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
RxCplDTrn_State_r1 <= RxCplDTrn_State;
RxCplDTrn_State_r2 <= RxCplDTrn_State_r1;
end if;
end process;
-- ----------------------------------------------
-- States synchronous
--
Syn_RxTrn_States:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RxCplDTrn_State <= ST_CplD_RESET;
elsif trn_clk'event and trn_clk = '1' then
RxCplDTrn_State <= RxCplDTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates:
process (
RxCplDTrn_State
, CplD_Type
, MSB_DSP_Tag
, trn_reof_n_i
, trn_rx_throttle
, Req_ID_Match_i
, Dex_Tag_Matched_i
)
begin
case RxCplDTrn_State is
when ST_CplD_RESET =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_IDLE =>
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_Cpl_HEAD2 => -- further processing to be done ...
RxCplDTrn_NextState <= ST_CplD_IDLE;
when ST_CplD_HEAD2 =>
if trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_HEAD2;
elsif Req_ID_Match_i='1' and Dex_Tag_Matched_i='1' then
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
elsif Req_ID_Match_i='1' and MSB_DSP_Tag='0' then
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_AFetch_Special;
else
RxCplDTrn_NextState <= ST_CplD_AFetch;
end if;
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_AFetch_Special =>
-- !!!!!!!!!!!!!!
-- Suppose 1DW CplD (sof-eof TLP) is not followed back-to-back
-- !!!!!!!!!!!!!!
RxCplDTrn_NextState <= ST_CplD_AFetch_Special_Tail;
when ST_CplD_AFetch_Special_Tail =>
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_AFetch_THROTTLE =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_ONLY_1DW;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_AFetch_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_1ST_DATA;
end if;
when ST_CplD_ONLY_1DW =>
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when ST_CplD_1ST_DATA =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_1ST_DATA_THROTTLE =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_1ST_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_DATA_THROTTLE =>
if trn_reof_n_i='0' then
RxCplDTrn_NextState <= ST_CplD_LAST_DATA;
elsif trn_rx_throttle = '1' then
RxCplDTrn_NextState <= ST_CplD_DATA_THROTTLE;
else
RxCplDTrn_NextState <= ST_CplD_DATA;
end if;
when ST_CplD_LAST_DATA => -- Same as IDLE, to support
-- back-to-back transactions
if trn_rx_throttle='0' then
case CplD_Type is
when C_TLP_TYPE_IS_CPLD =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPL =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when C_TLP_TYPE_IS_CPLDLK =>
RxCplDTrn_NextState <= ST_CplD_HEAD2;
when C_TLP_TYPE_IS_CPLLK =>
RxCplDTrn_NextState <= ST_Cpl_HEAD2;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_IDLE;
end case; -- CplD_Type
else
RxCplDTrn_NextState <= ST_CplD_IDLE;
end if;
when OTHERS =>
RxCplDTrn_NextState <= ST_CplD_RESET;
end case;
end process;
-- -------------------------------------------------
-- Synchronous Registered: Tag_Map_Clear_i
--
RxTrn_Tag_Map_Clear:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Tag_Map_Clear_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
FOR j IN 0 TO C_TAG_MAP_WIDTH-1 LOOP
-- CplD_Tag(C_TAG_WIDTH-2) used as token of BAR
if CplD_Tag(C_TAG_WIDTH-1)='0'
and CplD_Tag(C_TAG_WIDTH-2-1 downto 0)=CONV_STD_LOGIC_VECTOR(j, C_TAG_WIDTH-2)
and CplD_is_the_Last='1' then
Tag_Map_Clear_i(j) <= '1';
else
Tag_Map_Clear_i(j) <= '0';
end if;
END LOOP;
end if;
end process;
-- -------------------------------------------------
-- Synchronous Registered: CplD_Length
--
RxTrn_CplD_Length:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Length <= (OTHERS => '0');
CplD_is_1DW <= '0';
Small_CplD <= '0';
Small_CplD_r1 <= '0';
elsif trn_clk'event and trn_clk = '1' then
Small_CplD_r1 <= Small_CplD;
if trn_rsof_n_i='0' then
CplD_Length <= Tlp_has_4KB & trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
CplD_is_1DW <= Tlp_has_1DW;
if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)=C_ALL_ZEROS(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT+2)
and trn_rd_i(C_TLP_LENG_BIT_BOT+1 downto C_TLP_LENG_BIT_BOT)/="00"
and trn_rd_i(C_TLP_TYPE_BIT_TOP downto C_TLP_TYPE_BIT_TOP-1)="01" -- Cpl/D
then
Small_CplD <= '1';
else
Small_CplD <= '0';
end if;
else
CplD_Length <= CplD_Length;
CplD_is_1DW <= CplD_is_1DW;
Small_CplD <= Small_CplD;
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: Addr_Inc
--
RxFSM_Output_Addr_Inc:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Addr_Inc <= '1';
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
Addr_Inc <= '1';
when ST_CplD_1ST_DATA =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when ST_CplD_ONLY_1DW =>
Addr_Inc <= tRAM_DoutA_r1(CBIT_AINC_IN_TAGRAM);
when OTHERS =>
Addr_Inc <= Addr_Inc;
end case;
end if;
end process;
-------------------------------------------------
-- Calculation at trn_rsof_n
--
Syn_Dex_wrAddress:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Dex_CplD_Illegal <= '0';
Reg_WrAddr_if_last_us <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
Reg_WrAddr_if_last_ds <= (OTHERS=>'0'); -- C_REGS_BASE_ADDR;
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i = '0' then
Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_CTRL, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
-- Reg_WrAddr_if_last_us(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
-- Reg_WrAddr_if_last_ds(C_EP_AWIDTH-2-1 downto 2) <= CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_STA, C_EP_AWIDTH-2-2) - trn_rd_i(C_NEXT_BD_LENG_MSB+32 downto 32);
else
Reg_WrAddr_if_last_us <= Reg_WrAddr_if_last_us;
Reg_WrAddr_if_last_ds <= Reg_WrAddr_if_last_ds;
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous: RegAddr_?s_Dex
--
RxFSM_Reg_RegAddr_xs_Dex:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
RegAddr_us_Dex <= (Others=>'1');
RegAddr_ds_Dex <= (Others=>'1');
elsif trn_clk'event and trn_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_us_Dex <= (Others=>'1');
elsif CplD_is_the_Last = '1' then -- us last/2nd dex
RegAddr_us_Dex <= Reg_WrAddr_if_last_us;
else -- us 1st/unique dex
RegAddr_us_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_US_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)/=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
RegAddr_ds_Dex <= (Others=>'1');
elsif CplD_is_the_Last = '1' then -- ds last/2nd dex
RegAddr_ds_Dex <= Reg_WrAddr_if_last_ds;
else -- ds 1st/unique dex
RegAddr_ds_Dex <= -- C_REGS_BASE_ADDR(C_DECODE_BIT_TOP downto C_DECODE_BIT_BOT) & ,(C_DECODE_BIT_BOT-2)
-- CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH, C_DECODE_BIT_BOT) & "00";
CONV_STD_LOGIC_VECTOR(CINT_ADDR_DMA_DS_PAH-1, C_DECODE_BIT_BOT) & "00";
end if;
end if;
end process;
-- ---------------------------------------------
-- Reg Synchronous Delay: CplD_Tag_on_Dex
--
RxFSM_Delay_CplD_Tag_on_Dex:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
CplD_Tag_on_Dex <= '0';
elsif trn_clk'event and trn_clk = '1' then
if CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_USB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
elsif CplD_Tag(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS)=C_TAG0_DMA_DSB(C_TAG_WIDTH-1 downto C_TAG_WIDTH-C_TAG_DECODE_BITS) then
CplD_Tag_on_Dex <= '1';
else
CplD_Tag_on_Dex <= '0';
end if;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers
--
RxFSM_Output_DMA_Registers:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_AFetch_Special =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= "10";
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_1ST_DATA =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_ONLY_1DW =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_DATA =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when ST_CplD_LAST_DATA =>
if CplD_Tag_on_Dex='1' then
Regs_WrEn_i <= '1';
Regs_WrMask_i <= '0' & (trn_rrem_n_r1(3) or trn_rrem_n_r1(0));
Regs_WrDin_i <= trn_rd_Little_r1;
else
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end if;
when OTHERS =>
Regs_WrEn_i <= '0';
Regs_WrMask_i <= (OTHERS=>'0');
Regs_WrDin_i <= (Others=>'0');
end case;
end if;
end process;
-------------------------------------------------------
-- Synchronous outputs: DMA_Registers write Address
--
RxFSM_Output_DMA_Registers_WrAddr:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Regs_WrAddr_i <= (OTHERS => '1');
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_IDLE =>
Regs_WrAddr_i <= (OTHERS => '1');
when ST_CplD_AFetch =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_AFetch_Special =>
Regs_WrAddr_i <= RegAddr_us_Dex and RegAddr_ds_Dex;
when ST_CplD_1ST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_ONLY_1DW =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when ST_CplD_LAST_DATA =>
Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0)
<= Regs_WrAddr_i(C_DECODE_BIT_BOT-1 downto 0) + CONV_STD_LOGIC_VECTOR(8, C_DECODE_BIT_BOT);
when OTHERS =>
Regs_WrAddr_i <= Regs_WrAddr_i;
end case;
end if;
end process;
-----------------------------------------------------
-- Synchronous Register:
-- dsDMA_dex_Tag_i
-- usDMA_dex_Tag_i
--
FSM_Reg_DMA_dex_Tags:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
usDMA_dex_Tag_i <= C_TAG0_DMA_USB;
dsDMA_dex_Tag_i <= C_TAG0_DMA_DSB;
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State is
when ST_CplD_AFetch =>
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when ST_CplD_AFetch_Special =>
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=usDMA_dex_Tag_i and CplD_is_the_Last = '1' then
usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= usDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
end if;
if trn_rd_r1(C_CPLD_TAG_BIT_TOP downto C_CPLD_TAG_BIT_BOT)=dsDMA_dex_Tag_i and CplD_is_the_Last = '1' then
dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) <= dsDMA_dex_Tag_i(C_TAG_WIDTH-C_TAG_DECODE_BITS-1 downto 0) + X"1";
else
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end if;
when Others =>
usDMA_dex_Tag_i <= usDMA_dex_Tag_i;
dsDMA_dex_Tag_i <= dsDMA_dex_Tag_i;
end case;
end if;
end process;
-- -------------------------------------------------------------
-- RAM holding downstream Tags of packet MRd requests
-- -------------------------------------------------------------
tRAM_addra <= CplD_Tag(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_weB_i(0) <= tRAM_weB;
dspTag_BRAM:
FF_TagRam64x36
port map(
clk => trn_clk ,
wea => tRAM_wea(0) ,
addra => tRAM_addra ,
dina => tRAM_dina ,
douta => tRAM_doutA ,
web => tRAM_weB_i(0) ,
addrb => tRAM_addrB ,
dinb => tRAM_dinB ,
doutb => open
);
-- dspTag_BRAM:
-- v5tagram64x36
-- port map(
-- clka => trn_clk ,
-- addra => tRAM_addra ,
-- wea => tRAM_wea ,
-- dina => tRAM_dina ,
-- douta => tRAM_doutA ,
-- clkb => trn_clk ,
-- addrb => tRAM_addrB ,
-- web => tRAM_weB_i ,
-- dinb => tRAM_dinB ,
-- doutb => open
-- );
-- -----------------------------------------------------------------------------------
-- Synchronous delay: CplD_is_the_Last
--
Syn_Delay_CplD_is_the_Last:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
CplD_is_the_Last_r1 <= CplD_is_the_Last;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Updates_tRAM
-- Update happens only at data TLP
-- The last CplD of one MRd does not trigger tRAM update,
-- to enable back-to-back transactions.
--
RxFSM_Output_Updates_tRAM:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Updates_tRAM <= '0';
elsif trn_clk'event and trn_clk = '1' then
Updates_tRAM <= CplD_State_is_AFetch
and DSP_Tag_on_RAM_r1
-- and not trn_rx_throttle -- trn_rsrc_rdy_n_r1
and not CplD_is_the_Last_r1
;
end if;
end process;
-- -----------------------------------------------------------------------------------
-- Synchronous output: Update_was_too_late
-- For 1DW CplD the update might be too late for the
-- next CplD with the same TAG
--
RxFSM_Output_Update_was_too_late:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
Update_was_too_late <= '0';
hazard_tag <= (OTHERS=>'1');
tag_matches_hazard <= '0';
hazard_update <= '0';
hazard_update_r1 <= '0';
hazard_update_r2 <= '0';
hazard_update_r3 <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Small_CplD_r1='1' and CplD_State_is_after_AFetch='1' then
hazard_update <= '1';
hazard_tag <= CplD_Tag;
else
hazard_update <= '0';
hazard_tag <= hazard_tag;
end if;
if CplD_Tag=hazard_tag then
tag_matches_hazard <= '1';
else
tag_matches_hazard <= '0';
end if;
hazard_update_r1 <= hazard_update;
hazard_update_r2 <= hazard_update_r1;
hazard_update_r3 <= hazard_update_r2;
-- Update_was_too_late <= hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
Update_was_too_late <= hazard_update or hazard_update_r1 or hazard_update_r2 or hazard_update_r3;
end if;
end process;
-- ---------------------------------------------
-- Delay Synchronous Delay: Updates_tRAM
--
RxFSM_Delay_Updates_tRAM:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
Updates_tRAM_r1 <= Updates_tRAM;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Delay: tRAM_DoutA_r2
--
Delay_tRAM_DoutA:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
---- if CplD_State_is_AFetch='1' then -- [ avoid confilict in simulation, can be removed ]
-- if TLB_Hit='1'
-- and TLB_Valid='1' -- [ only for simulation. can be removed for imp.]
-- then
-- tRAM_DoutA_r1 <= TLB_Content;
-- else
-- tRAM_DoutA_r1 <= tRAM_doutA;
-- end if;
---- else
---- tRAM_DoutA_r1 <= tRAM_DoutA_r1;
---- end if;
if Update_was_too_late='1' and tag_matches_hazard='1' then
tRAM_DoutA_r1 <= hazard_content;
else
tRAM_DoutA_r1 <= tRAM_doutA;
end if;
-- tRAM_DoutA_r1 <= tRAM_doutA;
tRAM_DoutA_r2 <= tRAM_DoutA_r1;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Output: hazard_content
--
Syn_Reg_hazard_content:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
hazard_content <= (OTHERS =>'1');
elsif trn_clk'event and trn_clk = '1' then
if tRAM_wea(0)='1' then
hazard_content <= tRAM_dina;
else
hazard_content <= hazard_content;
end if;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_dina_aInc
--
Syn_Calc_tRAM_dina_aInc:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_dina_aInc <= (CBIT_AINC_IN_TAGRAM=>'1',
OTHERS =>'0'
);
elsif trn_clk'event and trn_clk = '1' then
tRAM_dina_aInc(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT)
<= tRAM_DoutA_r1(C_TAGBAR_BIT_TOP downto C_TAGBAR_BIT_BOT);
tRAM_dina_aInc(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
<= tRAM_DoutA_r1(C_TAGBAR_BIT_BOT-1 downto 0) --C_EP_AWIDTH !!!!!
+ CplD_Leng_in_Bytes_r1(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0) ;
end if;
end process;
tRAM_wea(0) <= Updates_tRAM_r1;
tRAM_dina <= tRAM_dina_aInc;
-- tRAM_dina <= ('1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0))
-- when Addr_Inc='1'
-- else ('0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0));
-- ---------------------------------------------
-- Synchronous Calculation: tRAM_DoutA_latch
--
Syn_tRAM_DoutA_latch:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
tRAM_DoutA_latch <= (CBIT_AINC_IN_TAGRAM=>'1',OTHERS =>'0');
elsif trn_clk'event and trn_clk = '1' then
if CplD_State_is_AFetch_r1='0' then
tRAM_DoutA_latch <= tRAM_DoutA_latch;
elsif Update_was_too_late='1' then
tRAM_DoutA_latch <= tRAM_DoutA_r1;
else
tRAM_DoutA_latch <= tRAM_DoutA;
end if;
end if;
end process;
-- ---------------------------------------------
-- Synchronous Output: TLB (not used)
--
Syn_Reg_TLB_Operation:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
TLB_Addr <= (OTHERS =>'1');
TLB_Content <= (OTHERS =>'0');
TLB_cnt <= (OTHERS =>'0');
TLB_Valid <= '0';
TLB_Hit <= '0';
elsif trn_clk'event and trn_clk = '1' then
if Updates_tRAM_r1='0' then
TLB_Content <= TLB_Content;
TLB_Addr <= TLB_Addr;
if TLB_cnt=C_ALL_ZEROS(3 downto 0) then
TLB_cnt <= TLB_cnt;
TLB_Valid <= '0';
else
TLB_cnt <= TLB_cnt - '1';
TLB_Valid <= '1';
end if;
else
TLB_Addr <= tRAM_addra;
TLB_cnt <= C_TLB_VALID_CNT;
TLB_Valid <= '0';
if Addr_Inc='1' then
TLB_Content <= '1' & tRAM_dina_aInc(C_TAGRAM_DWIDTH-1-1 downto 0);
else
TLB_Content <= '0' & tRAM_DoutA_r2(C_TAGRAM_DWIDTH-1-1 downto 0);
end if;
end if;
if TLB_Addr=tRAM_addra then
TLB_Hit <= '1';
else
TLB_Hit <= '0';
end if;
end if;
end process;
-- -------------------------------------------------
-- Synchronous outputs: DDR_Space_Hit
--
RxFSM_Output_DDR_Space_Hit:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
case RxCplDTrn_State_r1 is
when ST_CplD_RESET =>
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
when ST_CplD_AFetch =>
if trn_reof_n_r4='0' then
DDR_Space_Hit <= DSP_Tag_on_RAM_r1;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= DSP_Tag_on_RAM_r4p;
DDR_wr_v_i <= DSP_Tag_on_RAM_r4p; -- DSP_Tag_on_RAM; -- and not (trn_rx_throttle_r4 and trn_reof_n_r4);
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= trn_rd_Little_r4;
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
elsif DSP_Tag_on_RAM_r1 ='1' then
DDR_Space_Hit <= '1';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
else
DDR_Space_Hit <= '0';
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= (OTHERS=>'0');
end if;
when ST_CplD_AFetch_Special =>
if DSP_Tag_on_RAM_r1 ='1' then
DDR_Space_Hit <= '1';
-- DDR_wr_sof_i <= '0';
-- DDR_wr_eof_i <= '0';
-- DDR_wr_v_i <= '0'; -- not trn_rx_throttle_r1;
-- DDR_wr_FA_i <= '0';
-- DDR_wr_Shift_i <= '0';
-- DDR_wr_Mask_i <= (OTHERS=>'0');
-- DDR_wr_din_i <= (OTHERS=>'0');
else
DDR_Space_Hit <= '0';
-- DDR_wr_sof_i <= '0';
-- DDR_wr_eof_i <= '0';
-- DDR_wr_v_i <= '0';
-- DDR_wr_FA_i <= '0';
-- DDR_wr_Shift_i <= '0';
-- DDR_wr_Mask_i <= (OTHERS=>'0');
-- DDR_wr_din_i <= (OTHERS=>'0');
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= not trn_reof_n_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= trn_rd_Little_r4;
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
when ST_CplD_AFetch_Special_Tail =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
if Update_was_too_late='1' and tag_matches_hazard='1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_AFetch_THROTTLE =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= '0';
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
DDR_wr_din_i <= DDR_wr_din_i;
when ST_CplD_1ST_DATA =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
if Update_was_too_late='1' and tag_matches_hazard='1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when ST_CplD_ONLY_1DW =>
DDR_Space_Hit <= DDR_Space_Hit;
DDR_wr_sof_i <= DDR_Space_Hit; -- '1';
DDR_wr_eof_i <= '0';
DDR_wr_v_i <= DDR_Space_Hit; -- '1'; -- not trn_rx_throttle_r1;
DDR_wr_FA_i <= '0';
DDR_wr_Mask_i <= (OTHERS=>'0');
if Update_was_too_late='1' and tag_matches_hazard='1' then
DDR_wr_Shift_i <= not hazard_content(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & hazard_content(32-1 downto 0);
elsif CplD_State_is_AFetch_r1 = '0' then
DDR_wr_Shift_i <= not tRAM_DoutA_latch(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_latch(32-1 downto 0);
else
DDR_wr_Shift_i <= not tRAM_DoutA_r1(2);
DDR_wr_din_i <= CplD_Leng_in_Bytes_r1(32-1 downto 0) & tRAM_DoutA_r1(32-1 downto 0);
end if;
when OTHERS =>
if trn_reof_n_r4='0' then
DDR_Space_Hit <= '0';
else
DDR_Space_Hit <= DDR_Space_Hit;
end if;
DDR_wr_sof_i <= '0';
DDR_wr_eof_i <= not trn_reof_n_r4 and DDR_Space_Hit;
DDR_wr_v_i <= (DDR_wr_sof_i or not (trn_rx_throttle_r4 and trn_reof_n_r4)) and DDR_Space_Hit;
DDR_wr_FA_i <= '0';
DDR_wr_Shift_i <= '0';
DDR_wr_din_i <= trn_rd_Little_r4;
if DDR_wr_sof_i='1' then
DDR_wr_Mask_i <= "10";
else
DDR_wr_Mask_i <= '0' & (trn_rrem_n_r4(3) or trn_rrem_n_r4(0));
end if;
end case;
end if;
end process;
concat_rd <= trn_rd_r1(32-1 downto 0) & trn_rd_i(64-1 downto 32);
-- -------------------------------------------------
-- Synchronous outputs: eb_FIFO_Write
--
RxFSM_Output_FIFO_Space_Hit:
process ( trn_clk, Local_Reset_i)
begin
if Local_Reset_i = '1' then
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_sof_marker <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
EB_Write_State <= ST_EBWR_IDLE;
elsif trn_clk'event and trn_clk = '1' then
case EB_Write_State is
when ST_EBWR_IDLE =>
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_sof_marker <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
if trn_rx_throttle='0'
and CplD_Type=C_TLP_TYPE_IS_CPLD
and trn_rd_i(0)='0' -- Odd-DW CplD is illegal
then
EB_Write_State <= ST_EBWR_TAG;
else
EB_Write_State <= ST_EBWR_IDLE;
end if;
when ST_EBWR_TAG =>
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
if trn_rsof_n_i='0' then
eb_FIFO_sof_marker <= '0';
EB_Write_State <= ST_EBWR_TAG;
elsif trn_rx_throttle='0' and DSP_Tag_on_FIFO='1' then
eb_FIFO_sof_marker <= '1';
EB_Write_State <= ST_EBWR_DATA;
else
eb_FIFO_sof_marker <= '0';
EB_Write_State <= ST_EBWR_IDLE;
end if;
when ST_EBWR_DATA =>
eb_FIFO_we_i <= not trn_rx_throttle;
eb_FIFO_wsof_i <= eb_FIFO_sof_marker and not trn_rx_throttle;
eb_FIFO_sof_marker <= eb_FIFO_sof_marker and trn_rx_throttle;
eb_FIFO_din_i <= Endian_Invert_64(concat_rd);
if trn_rx_throttle='0' and trn_reof_n_i='0' then
eb_FIFO_weof_i <= '1';
EB_Write_State <= ST_EBWR_IDLE;
else
eb_FIFO_weof_i <= '0';
EB_Write_State <= ST_EBWR_DATA;
end if;
when OTHERS =>
eb_FIFO_we_i <= '0';
eb_FIFO_wsof_i <= '0';
eb_FIFO_weof_i <= '0';
eb_FIFO_sof_marker <= '0';
eb_FIFO_din_i <= (OTHERS=>'0');
EB_Write_State <= ST_EBWR_IDLE;
end case;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | 99a1c72bcf39b01997c6e9f5b97ad340 | 0.480265 | 3.31238 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_mBuf_128x72/simulation/k7_mBuf_128x72_dgen.vhd | 1 | 4,555 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_mBuf_128x72_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_mBuf_128x72_pkg.ALL;
ENTITY k7_mBuf_128x72_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF k7_mBuf_128x72_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:k7_mBuf_128x72_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 1bc536490d76ed0195fe3950d4f808ad | 0.601098 | 4.137148 | false | false | false | false |
UnofficialRepos/OSVVM | ResolutionPkg.vhd | 1 | 16,067 | --
-- File Name: ResolutionPkg.vhd
-- Design Unit Name: ResolutionPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
-- Package Defines
-- resolved resolution functions for integer, real, and time
-- types resolved_integer, resolved_real, resolved_time
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2021 2021.06 Moved To/FromTransaction and SafeResize to Resize package
-- 12/2020 2020.12 Updated ToTransaction and FromTransaction with length parameter.
-- Downsizing now permitted when it does not change the value.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Removed Asserts as they are not working as intended.
-- See ResolutionPkg_debug as it uses Alerts to correctly detect errors
-- 05/2015 2015.05 Added Alerts
-- -- Replaced Alerts with asserts as alerts are illegal in pure functions
-- 02/2009 1.0 VHDL-2008 STANDARD VERSION
-- 09/2006 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2005 - 2021 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
package ResolutionPkg is
constant MULTIPLE_DRIVER_SEVERITY : severity_level := ERROR ;
--
-- Note that not all simulators support resolution functions of the form:
-- subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
--
-- Hence, types of the form are offered as a temporary workaround until they do:
-- std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
--
-- resolved_max
-- return maximum value.
-- No initializations required on ports, default of type'left is ok
function resolved_max ( s : std_ulogic_vector) return std_ulogic ;
subtype std_logic_max is resolved_max std_ulogic ;
subtype std_logic_vector_max is (resolved_max) std_ulogic_vector ;
type std_logic_vector_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype unsigned_max is (resolved_max) unresolved_unsigned ;
type unsigned_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
subtype signed_max is (resolved_max) unresolved_signed ;
type signed_max_c is array (natural range <>) of std_logic_max ; -- for non VHDL-2008
function resolved_max ( s : bit_vector) return bit ;
subtype bit_max is resolved_max bit ;
subtype bit_vector_max is (resolved_max) bit_vector ;
type bit_vector_max_c is array (natural range <>) of bit_max ; -- for non VHDL-2008
function resolved_max ( s : integer_vector ) return integer ;
subtype integer_max is resolved_max integer ;
subtype integer_vector_max is (resolved_max) integer_vector ;
type integer_vector_max_c is array (natural range <>) of integer_max ; -- for non VHDL-2008
function resolved_max ( s : time_vector ) return time ;
subtype time_max is resolved_max time ;
subtype time_vector_max is (resolved_max) time_vector ;
type time_vector_max_c is array (natural range <>) of time_max ; -- for non VHDL-2008
function resolved_max ( s : real_vector ) return real ;
subtype real_max is resolved_max real ;
subtype real_vector_max is (resolved_max) real_vector ;
type real_vector_max_c is array (natural range <>) of real_max ; -- for non VHDL-2008
function resolved_max ( s : string) return character ;
subtype character_max is resolved_max character ;
subtype string_max is (resolved_max) string ;
type string_max_c is array (positive range <>) of character_max ; -- for non VHDL-2008
function resolved_max ( s : boolean_vector) return boolean ;
subtype boolean_max is resolved_max boolean ;
subtype boolean_vector_max is (resolved_max) boolean_vector ;
type boolean_vector_max_c is array (natural range <>) of boolean_max ; -- for non VHDL-2008
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
function resolved_sum ( s : integer_vector ) return integer ;
subtype integer_sum is resolved_sum integer ;
subtype integer_vector_sum is (resolved_sum) integer_vector ;
type integer_vector_sum_c is array (natural range <>) of integer_sum ; -- for non VHDL-2008
function resolved_sum ( s : time_vector ) return time ;
subtype time_sum is resolved_sum time ;
subtype time_vector_sum is (resolved_sum) time_vector ;
type time_vector_sum_c is array (natural range <>) of time_sum ; -- for non VHDL-2008
function resolved_sum ( s : real_vector ) return real ;
subtype real_sum is resolved_sum real ;
subtype real_vector_sum is (resolved_sum) real_vector ;
type real_vector_sum_c is array (natural range <>) of real_sum ; -- for non VHDL-2008
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
function resolved_weak (s : std_ulogic_vector) return std_ulogic ; -- no init, type'left
subtype std_logic_weak is resolved_weak std_ulogic ;
subtype std_logic_vector_weak is (resolved_weak) std_ulogic_vector ;
-- legacy stuff
-- requires ports to be initialized to 0 in the appropriate type.
function resolved ( s : integer_vector ) return integer ;
subtype resolved_integer is resolved integer ;
function resolved ( s : time_vector ) return time ;
subtype resolved_time is resolved time ;
function resolved ( s : real_vector ) return real ;
subtype resolved_real is resolved real ;
function resolved (s : string) return character ; -- same as resolved_max
subtype resolved_character is resolved character ;
-- subtype resolved_string is (resolved) string ; -- subtype will replace type later
type resolved_string is array (positive range <>) of resolved_character; -- will change to subtype -- assert but no init
function resolved ( s : boolean_vector) return boolean ; --same as resolved_max
subtype resolved_boolean is resolved boolean ;
end package ResolutionPkg ;
package body ResolutionPkg is
-- resolved_max
-- return maximum value. Assert FAILURE if more than 1 /= type'left
-- No initializations required on ports, default of type'left is ok
-- Optimized version is just the following:
-- ------------------------------------------------------------
-- function resolved_max ( s : <array_type> ) return <element_type> is
-- ------------------------------------------------------------
-- begin
-- return maximum(s) ;
-- end function resolved_max ;
------------------------------------------------------------
function resolved_max (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : bit_vector ) return bit is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : integer_vector ) return integer is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : time_vector ) return time is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : real_vector ) return real is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : string ) return character is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
------------------------------------------------------------
function resolved_max ( s : boolean_vector) return boolean is
------------------------------------------------------------
begin
return maximum(s) ;
end function resolved_max ;
-- resolved_sum - appropriate for numeric types
-- return sum of values that /= type'left
-- No initializations required on ports, default of type'left is ok
------------------------------------------------------------
function resolved_sum ( s : integer_vector ) return integer is
------------------------------------------------------------
variable result : integer := 0 ;
begin
for i in s'RANGE loop
if s(i) /= integer'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : time_vector ) return time is
------------------------------------------------------------
variable result : time := 0 sec ;
begin
for i in s'RANGE loop
if s(i) /= time'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
------------------------------------------------------------
function resolved_sum ( s : real_vector ) return real is
------------------------------------------------------------
variable result : real := 0.0 ;
begin
for i in s'RANGE loop
if s(i) /= real'left then
result := s(i) + result;
end if ;
end loop ;
return result ;
end function resolved_sum ;
-- resolved_weak
-- Special just for std_ulogic
-- No initializations required on ports, default of type'left is ok
type stdlogic_table is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
constant weak_resolution_table : stdlogic_table := (
-- Resolution order: Z < U < W < X < - < L < H < 0 < 1
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
('U', 'X', '0', '1', 'U', 'W', 'L', 'H', '-'), -- | U |
('X', 'X', '0', '1', 'X', 'X', 'L', 'H', '-'), -- | X |
('0', '0', '0', '1', '0', '0', '0', '0', '0'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'), -- | Z |
('W', 'X', '0', '1', 'W', 'W', 'L', 'H', '-'), -- | W |
('L', 'L', '0', '1', 'L', 'L', 'L', 'H', 'L'), -- | L |
('H', 'H', '0', '1', 'H', 'H', 'W', 'H', 'H'), -- | H |
('-', '-', '0', '1', '-', '-', 'L', 'H', '-') -- | - |
);
------------------------------------------------------------
function resolved_weak (s : std_ulogic_vector) return std_ulogic is
------------------------------------------------------------
variable result : std_ulogic := 'Z' ;
begin
for i in s'RANGE loop
result := weak_resolution_table(result, s(i)) ;
end loop ;
return result ;
end function resolved_weak ;
-- legacy stuff.
-- requires ports to be initialized to 0 in the appropriate type.
------------------------------------------------------------
function resolved ( s : integer_vector ) return integer is
-- requires interface to be initialized to 0
------------------------------------------------------------
variable result : integer := 0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0 then
failed := failed or (result /= 0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on integer" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on integer") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : time_vector ) return time is
-- requires interface to be initialized to 0 ns
------------------------------------------------------------
variable result : time := 0 ns ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) > 0 ns then
failed := failed or (result /= 0 ns) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on time" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on time") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : real_vector ) return real is
-- requires interface to be initialized to 0.0
------------------------------------------------------------
variable result : real := 0.0 ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= 0.0 then
failed := failed or (result /= 0.0) ;
result := maximum(s(i),result);
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on real" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on real") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved (s : string) return character is
-- same as resolved_max
------------------------------------------------------------
variable result : character := NUL ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) /= NUL then
failed := failed or (result /= NUL) ;
result := maximum(result, s(i)) ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on character" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on character") ;
return result ;
end function resolved ;
------------------------------------------------------------
function resolved ( s : boolean_vector) return boolean is
-- same as resolved_max
------------------------------------------------------------
variable result : boolean := FALSE ;
variable failed : boolean := FALSE ;
begin
for i in s'RANGE loop
if s(i) then
failed := failed or result ;
result := TRUE ;
end if ;
end loop ;
assert not failed report "ResolutionPkg.resolved: multiple drivers on boolean" severity MULTIPLE_DRIVER_SEVERITY ;
-- AlertIf(OSVVM_ALERTLOG_ID, failed, "ResolutionPkg.resolved: multiple drivers on boolean") ;
return result ;
end function resolved ;
end package body ResolutionPkg ;
| artistic-2.0 | 59abfa8eb5e03bac61e7c0ede8ce0ee7 | 0.554553 | 4.361292 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_dverif.vhd | 1 | 5,873 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF k7_prime_fifo_plain_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
PROCESS (RD_CLK,RESET)
BEGIN
IF (RESET = '1') THEN
rd_en_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
rd_en_d1 <= '1';
END IF;
END IF;
END PROCESS;
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:k7_prime_fifo_plain_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | d19e0b2b9b2ee46693460b8e65a3a610 | 0.569726 | 3.978997 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/Multiplier.vhd | 4 | 9,379 | library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiplier is
generic ( MultiplierIsShiftAdd: boolean:=true;
BIT_WIDTH : positive := 16; --Size on input/output vectors
COUNT_WIDTH : positive := 5); --Size of the counter signal
--COUNT_WIDTH needs to be the exact size required to fit Output signal
-- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- The size of the output vector is 2 times the size of the input vector.
Port ( CLK : in std_logic; --clock
TRIGGER : in std_logic; --RESET signal (pulse)
A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
READY : out std_logic := '0'); --Calculation ready signal (pulse)
end multiplier;
architecture Behavioral of multiplier is
type reg_type is record
counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
EN : std_logic;
tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
end record;
signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
signal s_RES, r_late : signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0');
signal s_READY, sr_READY, sr_recalc: std_logic;
constant c_trigger: std_logic:='0';
begin
--Control logic of the multiplication algorithm
ShiftAdd: if MultiplierIsShiftAdd = true generate
READY <= sr_READY;
combinational : process(A, B, r, TRIGGER,sr_recalc,r_late)
variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
begin
s_RES <= r_late;
rin <= r;
s_READY <= '0';
if sr_recalc = '1' then
if (TRIGGER = c_trigger) then
v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
s_RES <= (others => '0');
s_READY <= '0';
else
v := r;
v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
--Initialisation. Copy inputs to variables for manipulation and protection
--against the changing of the inputs while calculating. We also reset the counter.
s_RES <= v.tmp1;
if (v.counter = 2*BIT_WIDTH-1) then
s_READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
v.EN := '1';
v.tmpA := A;
v.tmp1 := RESIZE(B,RES'LENGTH);
v.tmp2 := (others => '0');
else
s_READY <= '0';
end if;
--check if we have to add
if (v.tmp1(0) = '1') then
v.tmp2 := v.tmp2 + v.tmpA;
end if;
--Next we are going to arithmetically shift tmp2 to the right so, that
--the bit that gets shifted out of it will shift into tmp1 from right
v.tmp1 := shift_right(v.tmp1, 1);
v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
v.tmp2 := shift_right(v.tmp2, 1);
end if;
rin <= v;
end if;
end process combinational;
sequential : process (CLK)
begin
if rising_edge(CLK) then
r <= rin;
if s_READY = '1' then
r_late <= r.tmp1; --
end if;
end if;
end process sequential;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
RES <= (others => '0');
sr_READY <='0';
elsif rising_edge(clk) then
if s_READY = '1' then
RES <= s_RES; --rin.tmp1;--
sr_READY <= '1';-- registered Ready signal. the ready signal we remain high until the multplier is reset again
end if;
end if;
end process;
process(clk,TRIGGER,s_READY)begin
if TRIGGER = c_trigger then
sr_recalc <= '1';
elsif rising_edge(clk) then
if s_READY = '1' then
sr_recalc <= '0';
end if;
end if;
end process;
end generate;
DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
P_Multiply: process(TRIGGER,A,B)
variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
variable v_en: std_logic:='0';
begin
if (TRIGGER = c_trigger) then
v_mul_res := (others => '0');
v_A := (others => '0');
v_B := (others => '0');
RES <= (others => '0');
READY <= '0';
v_en := '0';
else
v_A := A;
v_B := B;
v_mul_res := v_A * v_B;
v_en := '1';
end if;
RES <= v_mul_res;
READY <= '1' and v_en;
end process;
end generate;
end Behavioral;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use ieee.numeric_std.all;
--
--entity multiplier is
-- generic ( MultiplierIsShiftAdd: boolean:=true;
-- BIT_WIDTH : positive := 16; --Size on input/output vectors
-- COUNT_WIDTH : positive := 5); --Size of the counter signal
-- --COUNT_WIDTH needs to be the exact size required to fit Output signal
-- -- for example if BIT_WIDHT is 16, COUNT_WIDHT needs to be 5.
-- -- The size of the output vector is 2 times the size of the input vector.
--
-- Port ( CLK : in std_logic; --clock
-- TRIGGER : in std_logic; --RESET signal (pulse)
-- A : in signed ((BIT_WIDTH - 1) downto 0); --multiplicand
-- B : in signed ((BIT_WIDTH - 1) downto 0); --mutiplier
-- RES : out signed ((BIT_WIDTH*2 - 1) downto 0) := (others => '0'); --result
-- READY : out std_logic := '0'); --Calculation ready signal (pulse)
--end multiplier;
--
--
--architecture Behavioral of multiplier is
-- type reg_type is record
-- counter : unsigned ( (COUNT_WIDTH-1) downto 0 );
-- EN : std_logic;
-- tmp1 : signed ((BIT_WIDTH*2 - 1) downto 0); -- B
-- tmp2 : signed ((BIT_WIDTH*2 - 1) downto 0);
-- tmpA : signed ((BIT_WIDTH - 1) downto 0); -- A
-- end record;
-- signal r, rin : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--begin
--
-- --Control logic of the multiplication algorithm
--ShiftAdd: if MultiplierIsShiftAdd = true generate
-- combinational : process(A, B, r, TRIGGER)
-- variable v : reg_type := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
--
-- begin
-- if (TRIGGER = '0') then
-- v := ((others => '0'), '0', (others => '0'), (others => '0'), (others => '0'));
-- RES <= (others => '0');
-- READY <= '0';
-- else
-- v := r;
-- v.counter := v.counter -1; --At first cycle the counter ovwerflows and sets all bits to '1'-s giving the value of BIT_WIDTH - 1
-- --Initialisation. Copy inputs to variables for manipulation and protection
-- --against the changing of the inputs while calculating. We also TRIGGER the counter.
-- RES <= v.tmp1;
-- if (v.counter = 2*BIT_WIDTH-1) then
-- READY <= '1' and v.EN; --Output the READY signal only when we have a real answer
-- v.EN := '1';
-- v.tmpA := A;
-- v.tmp1 := RESIZE(B,RES'LENGTH);
-- v.tmp2 := (others => '0');
-- else
-- READY <= '0';
-- end if;
--
-- --check if we have to add
-- if (v.tmp1(0) = '1') then
-- v.tmp2 := v.tmp2 + v.tmpA;
-- end if;
--
-- --Next we are going to arithmetically shift tmp2 to the right so, that
-- --the bit that gets shifted out of it will shift into tmp1 from right
-- v.tmp1 := shift_right(v.tmp1, 1);
-- v.tmp1(2*BIT_WIDTH-1) := v.tmp2(0);
-- v.tmp2 := shift_right(v.tmp2, 1);
-- end if;
-- rin <= v;
-- end process combinational;
--
-- sequential : process (CLK)
-- begin
-- if rising_edge(CLK) then
-- r <= rin;
-- end if;
-- end process sequential;
--end generate;
--
-- DedicatedMultiplier: if MultiplierIsShiftAdd = false generate
-- P_Multiply: process(TRIGGER,A,B)
-- variable v_mul_res: signed ((BIT_WIDTH*2 - 1) downto 0);
-- variable v_A, v_B: signed ((BIT_WIDTH - 1) downto 0);
-- variable v_en: std_logic:='0';
-- begin
-- if (TRIGGER = '0') then
-- v_mul_res := (others => '0');
-- v_A := (others => '0');
-- v_B := (others => '0');
-- RES <= (others => '0');
-- READY <= '0';
-- v_en := '0';
-- else
-- v_A := A;
-- v_B := B;
-- v_mul_res := v_A * v_B;
-- v_en := '1';
-- end if;
-- RES <= v_mul_res;
-- READY <= '1' and v_en;
-- end process;
-- end generate;
--end Behavioral;
--
| mit | 8edf15afe46b5892a321c6f14f1c06b8 | 0.502292 | 3.248701 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/synth/cpu_axi_epc_0_0.vhd | 1 | 19,427 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_epc:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_epc_v2_0;
USE axi_epc_v2_0.axi_epc;
ENTITY cpu_axi_epc_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END cpu_axi_epc_0_0;
ARCHITECTURE cpu_axi_epc_0_0_arch OF cpu_axi_epc_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_epc IS
GENERIC (
C_S_AXI_CLK_PERIOD_PS : INTEGER;
C_PRH_CLK_PERIOD_PS : INTEGER;
C_FAMILY : STRING;
C_INSTANCE : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_NUM_PERIPHERALS : INTEGER;
C_PRH_MAX_AWIDTH : INTEGER;
C_PRH_MAX_DWIDTH : INTEGER;
C_PRH_MAX_ADWIDTH : INTEGER;
C_PRH_CLK_SUPPORT : INTEGER;
C_PRH0_BASEADDR : STD_LOGIC_VECTOR;
C_PRH0_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH0_FIFO_ACCESS : INTEGER;
C_PRH0_FIFO_OFFSET : INTEGER;
C_PRH0_AWIDTH : INTEGER;
C_PRH0_DWIDTH : INTEGER;
C_PRH0_DWIDTH_MATCH : INTEGER;
C_PRH0_SYNC : INTEGER;
C_PRH0_BUS_MULTIPLEX : INTEGER;
C_PRH0_ADDR_TSU : INTEGER;
C_PRH0_ADDR_TH : INTEGER;
C_PRH0_ADS_WIDTH : INTEGER;
C_PRH0_CSN_TSU : INTEGER;
C_PRH0_CSN_TH : INTEGER;
C_PRH0_WRN_WIDTH : INTEGER;
C_PRH0_WR_CYCLE : INTEGER;
C_PRH0_DATA_TSU : INTEGER;
C_PRH0_DATA_TH : INTEGER;
C_PRH0_RDN_WIDTH : INTEGER;
C_PRH0_RD_CYCLE : INTEGER;
C_PRH0_DATA_TOUT : INTEGER;
C_PRH0_DATA_TINV : INTEGER;
C_PRH0_RDY_TOUT : INTEGER;
C_PRH0_RDY_WIDTH : INTEGER;
C_PRH1_BASEADDR : STD_LOGIC_VECTOR;
C_PRH1_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH1_FIFO_ACCESS : INTEGER;
C_PRH1_FIFO_OFFSET : INTEGER;
C_PRH1_AWIDTH : INTEGER;
C_PRH1_DWIDTH : INTEGER;
C_PRH1_DWIDTH_MATCH : INTEGER;
C_PRH1_SYNC : INTEGER;
C_PRH1_BUS_MULTIPLEX : INTEGER;
C_PRH1_ADDR_TSU : INTEGER;
C_PRH1_ADDR_TH : INTEGER;
C_PRH1_ADS_WIDTH : INTEGER;
C_PRH1_CSN_TSU : INTEGER;
C_PRH1_CSN_TH : INTEGER;
C_PRH1_WRN_WIDTH : INTEGER;
C_PRH1_WR_CYCLE : INTEGER;
C_PRH1_DATA_TSU : INTEGER;
C_PRH1_DATA_TH : INTEGER;
C_PRH1_RDN_WIDTH : INTEGER;
C_PRH1_RD_CYCLE : INTEGER;
C_PRH1_DATA_TOUT : INTEGER;
C_PRH1_DATA_TINV : INTEGER;
C_PRH1_RDY_TOUT : INTEGER;
C_PRH1_RDY_WIDTH : INTEGER;
C_PRH2_BASEADDR : STD_LOGIC_VECTOR;
C_PRH2_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH2_FIFO_ACCESS : INTEGER;
C_PRH2_FIFO_OFFSET : INTEGER;
C_PRH2_AWIDTH : INTEGER;
C_PRH2_DWIDTH : INTEGER;
C_PRH2_DWIDTH_MATCH : INTEGER;
C_PRH2_SYNC : INTEGER;
C_PRH2_BUS_MULTIPLEX : INTEGER;
C_PRH2_ADDR_TSU : INTEGER;
C_PRH2_ADDR_TH : INTEGER;
C_PRH2_ADS_WIDTH : INTEGER;
C_PRH2_CSN_TSU : INTEGER;
C_PRH2_CSN_TH : INTEGER;
C_PRH2_WRN_WIDTH : INTEGER;
C_PRH2_WR_CYCLE : INTEGER;
C_PRH2_DATA_TSU : INTEGER;
C_PRH2_DATA_TH : INTEGER;
C_PRH2_RDN_WIDTH : INTEGER;
C_PRH2_RD_CYCLE : INTEGER;
C_PRH2_DATA_TOUT : INTEGER;
C_PRH2_DATA_TINV : INTEGER;
C_PRH2_RDY_TOUT : INTEGER;
C_PRH2_RDY_WIDTH : INTEGER;
C_PRH3_BASEADDR : STD_LOGIC_VECTOR;
C_PRH3_HIGHADDR : STD_LOGIC_VECTOR;
C_PRH3_FIFO_ACCESS : INTEGER;
C_PRH3_FIFO_OFFSET : INTEGER;
C_PRH3_AWIDTH : INTEGER;
C_PRH3_DWIDTH : INTEGER;
C_PRH3_DWIDTH_MATCH : INTEGER;
C_PRH3_SYNC : INTEGER;
C_PRH3_BUS_MULTIPLEX : INTEGER;
C_PRH3_ADDR_TSU : INTEGER;
C_PRH3_ADDR_TH : INTEGER;
C_PRH3_ADS_WIDTH : INTEGER;
C_PRH3_CSN_TSU : INTEGER;
C_PRH3_CSN_TH : INTEGER;
C_PRH3_WRN_WIDTH : INTEGER;
C_PRH3_WR_CYCLE : INTEGER;
C_PRH3_DATA_TSU : INTEGER;
C_PRH3_DATA_TH : INTEGER;
C_PRH3_RDN_WIDTH : INTEGER;
C_PRH3_RD_CYCLE : INTEGER;
C_PRH3_DATA_TOUT : INTEGER;
C_PRH3_DATA_TINV : INTEGER;
C_PRH3_RDY_TOUT : INTEGER;
C_PRH3_RDY_WIDTH : INTEGER
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
prh_clk : IN STD_LOGIC;
prh_rst : IN STD_LOGIC;
prh_cs_n : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_addr : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_ads : OUT STD_LOGIC;
prh_be : OUT STD_LOGIC_VECTOR(0 TO 3);
prh_rnw : OUT STD_LOGIC;
prh_rd_n : OUT STD_LOGIC;
prh_wr_n : OUT STD_LOGIC;
prh_burst : OUT STD_LOGIC;
prh_rdy : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
prh_data_i : IN STD_LOGIC_VECTOR(0 TO 31);
prh_data_o : OUT STD_LOGIC_VECTOR(0 TO 31);
prh_data_t : OUT STD_LOGIC_VECTOR(0 TO 31)
);
END COMPONENT axi_epc;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "axi_epc,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_axi_epc_0_0_arch : ARCHITECTURE IS "cpu_axi_epc_0_0,axi_epc,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_axi_epc_0_0_arch: ARCHITECTURE IS "cpu_axi_epc_0_0,axi_epc,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_epc,x_ipVersion=2.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_S_AXI_CLK_PERIOD_PS=10000,C_PRH_CLK_PERIOD_PS=10000,C_FAMILY=zynq,C_INSTANCE=axi_epc_inst,C_S_AXI_ADDR_WIDTH=32,C_S_AXI_DATA_WIDTH=32,C_NUM_PERIPHERALS=1,C_PRH_MAX_AWIDTH=32,C_PRH_MAX_DWIDTH=32,C_PRH_MAX_ADWIDTH=32,C_PRH_CLK_SUPPORT=0,C_PRH0_BASEADDR=0x80600000,C_PRH0_HIGHADDR=0x8060FFFF,C_PRH0_FIFO_ACCESS=0,C_PRH0_FIFO_OFFSET=0,C_PRH0_AWIDTH=32,C_PRH0_DWIDTH=32,C_PRH0_DWIDTH_MATCH=0,C_PRH0_SYNC=1,C_PRH0_BUS_MULTIPLEX=0,C_PRH0_ADDR_TSU=0,C_PRH0_ADDR_TH=0,C_PRH0_ADS_WIDTH=0,C_PRH0_CSN_TSU=0,C_PRH0_CSN_TH=0,C_PRH0_WRN_WIDTH=0,C_PRH0_WR_CYCLE=0,C_PRH0_DATA_TSU=0,C_PRH0_DATA_TH=0,C_PRH0_RDN_WIDTH=0,C_PRH0_RD_CYCLE=0,C_PRH0_DATA_TOUT=0,C_PRH0_DATA_TINV=0,C_PRH0_RDY_TOUT=0,C_PRH0_RDY_WIDTH=100000,C_PRH1_BASEADDR=0xB000FFFF,C_PRH1_HIGHADDR=0xBFFFFFFF,C_PRH1_FIFO_ACCESS=0,C_PRH1_FIFO_OFFSET=0,C_PRH1_AWIDTH=32,C_PRH1_DWIDTH=32,C_PRH1_DWIDTH_MATCH=0,C_PRH1_SYNC=0,C_PRH1_BUS_MULTIPLEX=0,C_PRH1_ADDR_TSU=0,C_PRH1_ADDR_TH=0,C_PRH1_ADS_WIDTH=0,C_PRH1_CSN_TSU=0,C_PRH1_CSN_TH=0,C_PRH1_WRN_WIDTH=0,C_PRH1_WR_CYCLE=0,C_PRH1_DATA_TSU=0,C_PRH1_DATA_TH=0,C_PRH1_RDN_WIDTH=0,C_PRH1_RD_CYCLE=0,C_PRH1_DATA_TOUT=0,C_PRH1_DATA_TINV=0,C_PRH1_RDY_TOUT=0,C_PRH1_RDY_WIDTH=0,C_PRH2_BASEADDR=0xC000FFFF,C_PRH2_HIGHADDR=0xCFFFFFFF,C_PRH2_FIFO_ACCESS=0,C_PRH2_FIFO_OFFSET=0,C_PRH2_AWIDTH=32,C_PRH2_DWIDTH=32,C_PRH2_DWIDTH_MATCH=0,C_PRH2_SYNC=0,C_PRH2_BUS_MULTIPLEX=0,C_PRH2_ADDR_TSU=0,C_PRH2_ADDR_TH=0,C_PRH2_ADS_WIDTH=0,C_PRH2_CSN_TSU=0,C_PRH2_CSN_TH=0,C_PRH2_WRN_WIDTH=0,C_PRH2_WR_CYCLE=0,C_PRH2_DATA_TSU=0,C_PRH2_DATA_TH=0,C_PRH2_RDN_WIDTH=0,C_PRH2_RD_CYCLE=0,C_PRH2_DATA_TOUT=0,C_PRH2_DATA_TINV=0,C_PRH2_RDY_TOUT=0,C_PRH2_RDY_WIDTH=0,C_PRH3_BASEADDR=0xD000FFFF,C_PRH3_HIGHADDR=0xDFFFFFFF,C_PRH3_FIFO_ACCESS=0,C_PRH3_FIFO_OFFSET=0,C_PRH3_AWIDTH=32,C_PRH3_DWIDTH=32,C_PRH3_DWIDTH_MATCH=0,C_PRH3_SYNC=0,C_PRH3_BUS_MULTIPLEX=0,C_PRH3_ADDR_TSU=0,C_PRH3_ADDR_TH=0,C_PRH3_ADS_WIDTH=0,C_PRH3_CSN_TSU=0,C_PRH3_CSN_TH=0,C_PRH3_WRN_WIDTH=0,C_PRH3_WR_CYCLE=0,C_PRH3_DATA_TSU=0,C_PRH3_DATA_TH=0,C_PRH3_RDN_WIDTH=0,C_PRH3_RD_CYCLE=0,C_PRH3_DATA_TOUT=0,C_PRH3_DATA_TINV=0,C_PRH3_RDY_TOUT=0,C_PRH3_RDY_WIDTH=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_RST RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF prh_clk: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CLK";
ATTRIBUTE X_INTERFACE_INFO OF prh_rst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RST";
ATTRIBUTE X_INTERFACE_INFO OF prh_cs_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF CS_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_addr: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADDR";
ATTRIBUTE X_INTERFACE_INFO OF prh_ads: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF ADS";
ATTRIBUTE X_INTERFACE_INFO OF prh_be: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BE";
ATTRIBUTE X_INTERFACE_INFO OF prh_rnw: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RNW";
ATTRIBUTE X_INTERFACE_INFO OF prh_rd_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RD_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_wr_n: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF WR_N";
ATTRIBUTE X_INTERFACE_INFO OF prh_burst: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF BURST";
ATTRIBUTE X_INTERFACE_INFO OF prh_rdy: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF RDY";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_i: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_I";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_o: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_O";
ATTRIBUTE X_INTERFACE_INFO OF prh_data_t: SIGNAL IS "xilinx.com:interface:epc:1.0 EPC_INTF DATA_T";
BEGIN
U0 : axi_epc
GENERIC MAP (
C_S_AXI_CLK_PERIOD_PS => 10000,
C_PRH_CLK_PERIOD_PS => 10000,
C_FAMILY => "zynq",
C_INSTANCE => "axi_epc_inst",
C_S_AXI_ADDR_WIDTH => 32,
C_S_AXI_DATA_WIDTH => 32,
C_NUM_PERIPHERALS => 1,
C_PRH_MAX_AWIDTH => 32,
C_PRH_MAX_DWIDTH => 32,
C_PRH_MAX_ADWIDTH => 32,
C_PRH_CLK_SUPPORT => 0,
C_PRH0_BASEADDR => X"80600000",
C_PRH0_HIGHADDR => X"8060FFFF",
C_PRH0_FIFO_ACCESS => 0,
C_PRH0_FIFO_OFFSET => 0,
C_PRH0_AWIDTH => 32,
C_PRH0_DWIDTH => 32,
C_PRH0_DWIDTH_MATCH => 0,
C_PRH0_SYNC => 1,
C_PRH0_BUS_MULTIPLEX => 0,
C_PRH0_ADDR_TSU => 0,
C_PRH0_ADDR_TH => 0,
C_PRH0_ADS_WIDTH => 0,
C_PRH0_CSN_TSU => 0,
C_PRH0_CSN_TH => 0,
C_PRH0_WRN_WIDTH => 0,
C_PRH0_WR_CYCLE => 0,
C_PRH0_DATA_TSU => 0,
C_PRH0_DATA_TH => 0,
C_PRH0_RDN_WIDTH => 0,
C_PRH0_RD_CYCLE => 0,
C_PRH0_DATA_TOUT => 0,
C_PRH0_DATA_TINV => 0,
C_PRH0_RDY_TOUT => 0,
C_PRH0_RDY_WIDTH => 100000,
C_PRH1_BASEADDR => X"B000FFFF",
C_PRH1_HIGHADDR => X"BFFFFFFF",
C_PRH1_FIFO_ACCESS => 0,
C_PRH1_FIFO_OFFSET => 0,
C_PRH1_AWIDTH => 32,
C_PRH1_DWIDTH => 32,
C_PRH1_DWIDTH_MATCH => 0,
C_PRH1_SYNC => 0,
C_PRH1_BUS_MULTIPLEX => 0,
C_PRH1_ADDR_TSU => 0,
C_PRH1_ADDR_TH => 0,
C_PRH1_ADS_WIDTH => 0,
C_PRH1_CSN_TSU => 0,
C_PRH1_CSN_TH => 0,
C_PRH1_WRN_WIDTH => 0,
C_PRH1_WR_CYCLE => 0,
C_PRH1_DATA_TSU => 0,
C_PRH1_DATA_TH => 0,
C_PRH1_RDN_WIDTH => 0,
C_PRH1_RD_CYCLE => 0,
C_PRH1_DATA_TOUT => 0,
C_PRH1_DATA_TINV => 0,
C_PRH1_RDY_TOUT => 0,
C_PRH1_RDY_WIDTH => 0,
C_PRH2_BASEADDR => X"C000FFFF",
C_PRH2_HIGHADDR => X"CFFFFFFF",
C_PRH2_FIFO_ACCESS => 0,
C_PRH2_FIFO_OFFSET => 0,
C_PRH2_AWIDTH => 32,
C_PRH2_DWIDTH => 32,
C_PRH2_DWIDTH_MATCH => 0,
C_PRH2_SYNC => 0,
C_PRH2_BUS_MULTIPLEX => 0,
C_PRH2_ADDR_TSU => 0,
C_PRH2_ADDR_TH => 0,
C_PRH2_ADS_WIDTH => 0,
C_PRH2_CSN_TSU => 0,
C_PRH2_CSN_TH => 0,
C_PRH2_WRN_WIDTH => 0,
C_PRH2_WR_CYCLE => 0,
C_PRH2_DATA_TSU => 0,
C_PRH2_DATA_TH => 0,
C_PRH2_RDN_WIDTH => 0,
C_PRH2_RD_CYCLE => 0,
C_PRH2_DATA_TOUT => 0,
C_PRH2_DATA_TINV => 0,
C_PRH2_RDY_TOUT => 0,
C_PRH2_RDY_WIDTH => 0,
C_PRH3_BASEADDR => X"D000FFFF",
C_PRH3_HIGHADDR => X"DFFFFFFF",
C_PRH3_FIFO_ACCESS => 0,
C_PRH3_FIFO_OFFSET => 0,
C_PRH3_AWIDTH => 32,
C_PRH3_DWIDTH => 32,
C_PRH3_DWIDTH_MATCH => 0,
C_PRH3_SYNC => 0,
C_PRH3_BUS_MULTIPLEX => 0,
C_PRH3_ADDR_TSU => 0,
C_PRH3_ADDR_TH => 0,
C_PRH3_ADS_WIDTH => 0,
C_PRH3_CSN_TSU => 0,
C_PRH3_CSN_TH => 0,
C_PRH3_WRN_WIDTH => 0,
C_PRH3_WR_CYCLE => 0,
C_PRH3_DATA_TSU => 0,
C_PRH3_DATA_TH => 0,
C_PRH3_RDN_WIDTH => 0,
C_PRH3_RD_CYCLE => 0,
C_PRH3_DATA_TOUT => 0,
C_PRH3_DATA_TINV => 0,
C_PRH3_RDY_TOUT => 0,
C_PRH3_RDY_WIDTH => 0
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
prh_clk => prh_clk,
prh_rst => prh_rst,
prh_cs_n => prh_cs_n,
prh_addr => prh_addr,
prh_ads => prh_ads,
prh_be => prh_be,
prh_rnw => prh_rnw,
prh_rd_n => prh_rd_n,
prh_wr_n => prh_wr_n,
prh_burst => prh_burst,
prh_rdy => prh_rdy,
prh_data_i => prh_data_i,
prh_data_o => prh_data_o,
prh_data_t => prh_data_t
);
END cpu_axi_epc_0_0_arch;
| gpl-3.0 | 4fa80eaf990f626afef648757c568ecd | 0.645236 | 2.62102 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_out/example_design/weight_out_exdes.vhd | 1 | 4,629 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: weight_out_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weight_out_exdes IS
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END weight_out_exdes;
ARCHITECTURE xilinx OF weight_out_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT weight_out IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(319 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : weight_out
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
| bsd-2-clause | 2ff5db3aeed5aa4cf4ec665667a4631a | 0.568157 | 4.737973 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_soft_reset.vhd | 1 | 13,837 | -------------------------------------------------------------------------------
--soft_reset.vhd v1.01a
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2006-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: soft_reset.vhd
-- Version: v1_00_a
-- Description: This VHDL design file is the Soft Reset Service
--
-------------------------------------------------------------------------------
-- Structure:
--
-- soft_reset.vhd
--
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
--
-- History:
-- GAB Aug 2, 2006 v1.00a (initial release)
--
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_soft_reset is
generic (
C_SIPIF_DWIDTH : integer := 32;
-- Width of the write data bus
C_RESET_WIDTH : integer := 4
-- Width of triggered reset in Bus Clocks
);
port (
-- Inputs From the IPIF Bus
Bus2IP_Reset : in std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_WrCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SIPIF_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to (C_SIPIF_DWIDTH/8)-1);
-- Final Device Reset Output
Reset2IP_Reset : out std_logic;
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end cpu_xadc_wiz_0_0_soft_reset ;
-------------------------------------------------------------------------------
architecture implementation of cpu_xadc_wiz_0_0_soft_reset is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-- Module Software Reset screen value for write data
-- This requires a Hex 'A' to be written to ativate the S/W reset port
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
-- Required BE index to be active during Reset activation
constant BE_MATCH : integer := 3;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal sm_reset : std_logic;
signal error_reply : std_logic;
signal reset_wrack : std_logic;
signal reset_error : std_logic;
signal reset_trig : std_logic;
signal wrack : std_logic;
signal wrack_ff_chain : std_logic;
signal flop_q_chain : std_logic_vector(0 to C_RESET_WIDTH);
--signal bus2ip_wrce_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-- Misc assignments
Reset2Bus_WrAck <= reset_wrack;
Reset2Bus_Error <= reset_error;
Reset2Bus_ToutSup <= sm_reset; -- Suppress a data phase timeout when
-- a commanded reset is active.
reset_wrack <= (reset_error or wrack);-- and Bus2IP_WrCE;
reset_error <= data_is_non_reset_match and Bus2IP_WrCE;
Reset2IP_Reset <= Bus2IP_Reset or sm_reset;
---------------------------------------------------------------------------------
---- Register WRCE for use in creating a strobe pulse
---------------------------------------------------------------------------------
--REG_WRCE : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1')then
-- if(Bus2IP_Reset = '1')then
-- bus2ip_wrce_d1 <= '0';
-- else
-- bus2ip_wrce_d1 <= Bus2IP_WrCE;
-- end if;
-- end if;
-- end process REG_WRCE;
--
-------------------------------------------------------------------------------
-- Start the S/W reset state machine as a result of an IPIF Bus write to
-- the Reset port and the data on the DBus inputs matching the Reset
-- match value. If the value on the data bus input does not match the
-- designated reset key, an error acknowledge is generated.
-------------------------------------------------------------------------------
--DETECT_SW_RESET : process (Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') then
-- if (Bus2IP_Reset = '1') then
-- error_reply <= '0';
-- reset_trig <= '0';
-- elsif (Bus2IP_WrCE = '1'
-- and Bus2IP_BE(BE_MATCH) = '1'
-- and Bus2IP_Data(28 to 31) = RESET_MATCH) then
-- error_reply <= '0';
-- reset_trig <= Bus2IP_WrCE and not bus2ip_wrce_d1;
-- elsif (Bus2IP_WrCE = '1') then
-- error_reply <= '1';
-- reset_trig <= '0';
-- else
-- error_reply <= '0';
-- reset_trig <= '0';
-- end if;
-- end if;
-- end process DETECT_SW_RESET;
data_is_non_reset_match <=
'0' when (Bus2IP_Data(C_SIPIF_DWIDTH-4 to C_SIPIF_DWIDTH-1) = RESET_MATCH
and Bus2IP_BE(BE_MATCH) = '1')
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
----------------------------------------------------------------------------
sw_rst_cond <= Bus2IP_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Bus2IP_Reset = '1') Then
sw_rst_cond_d1 <= '0';
reset_trig <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
reset_trig <= sw_rst_cond and not sw_rst_cond_d1;
end if;
end if;
End process;
-------------------------------------------------------------------------------
-- RESET_FLOPS:
-- This FORGEN implements the register chain used to create
-- the parameterizable reset pulse width.
-------------------------------------------------------------------------------
RESET_FLOPS : for index in 0 to C_RESET_WIDTH-1 generate
flop_q_chain(0) <= '0';
RST_FLOPS : FDRSE
port map(
Q => flop_q_chain(index+1), -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => flop_q_chain(index), -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => reset_trig -- : in std_logic
);
end generate RESET_FLOPS;
-- Use the last flop output for the commanded reset pulse
sm_reset <= flop_q_chain(C_RESET_WIDTH);
wrack_ff_chain <= flop_q_chain(C_RESET_WIDTH) and
not(flop_q_chain(C_RESET_WIDTH-1));
-- Register the Write Acknowledge for the Reset write
-- This is generated at the end of the reset pulse. This
-- keeps the Slave busy until the commanded reset completes.
FF_WRACK : FDRSE
port map(
Q => wrack, -- : out std_logic;
C => Bus2IP_Clk, -- : in std_logic;
CE => '1', -- : in std_logic;
D => wrack_ff_chain, -- : in std_logic;
R => Bus2IP_Reset, -- : in std_logic;
S => '0' -- : in std_logic
);
end implementation;
| gpl-3.0 | 53017b1928bbe137b2ab1e26d4f50a19 | 0.403556 | 4.853385 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp_tb.vhd | 1 | 7,252 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_tb.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-19
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controller test bench
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-19 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity disp_tb is
end disp_tb;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
use work.tb_pkg.all;
architecture STRUCTURE of disp_tb is
component disp
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
-- Display memory
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
-- Time of day
cur_time : in time_ty;
-- Output to tlc59282 LED driver
disp_sclk : OUT std_logic;
disp_blank : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic;
disp_status : OUT std_logic
);
end component;
SIGNAL rst_n : std_logic;
SIGNAL clk : std_logic;
SIGNAL tsc_1pps : std_logic;
SIGNAL tsc_1ppms : std_logic;
SIGNAL tsc_1ppus : std_logic;
SIGNAL disp_ena : std_logic;
SIGNAL disp_page : std_logic_vector(7 downto 0);
SIGNAL disp_pdm : std_logic_vector(7 downto 0);
SIGNAL stat_src : std_logic_vector(3 downto 0);
SIGNAL stat : std_logic_vector(15 downto 0);
-- Display memory
SIGNAL sram_addr : std_logic_vector(9 downto 0);
SIGNAL sram_we : std_logic;
SIGNAL sram_datao : std_logic_vector(31 downto 0);
SIGNAL sram_datai : std_logic_vector(31 downto 0);
-- Time of day
SIGNAL cur_time : time_ty;
-- Output to tlc59282 LED driver
SIGNAL disp_sclk : std_logic;
SIGNAL disp_blank : std_logic;
SIGNAL disp_lat : std_logic;
SIGNAL disp_sin : std_logic;
SIGNAL disp_status : std_logic;
begin
disp_i: disp
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus,
disp_ena => disp_ena,
disp_page => disp_page,
disp_pdm => disp_pdm,
stat_src => stat_src,
stat => stat,
-- Display memory
sram_addr => sram_addr,
sram_we => sram_we,
sram_datao => sram_datao,
sram_datai => sram_datai,
-- Time of day
cur_time => cur_time,
-- Output to tlc59282 LED driver
disp_sclk => disp_sclk,
disp_blank => disp_blank,
disp_lat => disp_lat,
disp_sin => disp_sin,
disp_status => disp_status
);
clk_100MHZ: clk_gen(10 ns, 50, clk);
reset: rst_n_gen(1 us, rst_n);
-- 1 second pulse
process
begin
tsc_1pps <= '0';
run_clk(clk, 1000);
loop
tsc_1pps <= '1';
run_clk(clk, 1);
tsc_1pps <= '0';
run_clk(clk, 1999999);
end loop;
end process;
-- 1 milli second pulse
process
begin
tsc_1ppms <= '0';
run_clk(clk, 1000);
loop
tsc_1ppms <= '1';
run_clk(clk, 1);
tsc_1ppms <= '0';
run_clk(clk, 1999);
end loop;
end process;
-- 1 micro second pulse
process
begin
tsc_1ppus <= '0';
run_clk(clk, 1000);
loop
tsc_1ppus <= '1';
run_clk(clk, 1);
tsc_1ppus <= '0';
run_clk(clk, 1);
end loop;
end process;
-- pdm setting
process
begin
disp_pdm <= (others =>'0');
run_clk(clk, 2000);
disp_pdm <= x"aa";
run_clk(clk, 12800);
disp_pdm <= x"ff";
run_clk(clk, 12800);
disp_pdm <= x"fe";
run_clk(clk, 12800);
disp_pdm <= x"fd";
run_clk(clk, 12800);
disp_pdm <= x"7f";
run_clk(clk, 12800);
disp_pdm <= x"80";
run_clk(clk, 12800);
disp_pdm <= x"81";
run_clk(clk, 12800);
disp_pdm <= x"00";
run_clk(clk, 12800);
disp_pdm <= x"01";
run_clk(clk, 12800);
disp_pdm <= x"02";
run_clk(clk, 12800);
disp_pdm <= x"03";
run_clk(clk, 12800);
wait;
end process;
-- input
process
begin
disp_ena <= '1';
disp_page <= (others => '0');
sram_addr <= (others => '0');
sram_we <= '0';
sram_datao <= (others => '0');
stat_src <= (others => '0');
stat <= (others => '0');
cur_time.t_1ms <= (others => '0');
cur_time.t_10ms <= (others => '0');
cur_time.t_100ms <= (others => '0');
cur_time.t_1s <= (others => '0');
cur_time.t_10s <= (others => '0');
cur_time.t_1m <= (others => '0');
cur_time.t_10m <= (others => '0');
cur_time.t_1h <= (others => '0');
cur_time.t_10h <= (others => '0');
run_clk(clk, 2000);
run_clk(clk, 10000);
disp_page <= x"1f";
run_clk(clk, 2000);
wait;
end process;
end STRUCTURE;
| gpl-3.0 | 06c871d0e5c617d2a2c41023db4080c9 | 0.412576 | 3.786945 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_15/lab15_1/lab15_1.vhd | 1 | 890 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity lab_15_1 is
generic ( r: integer :=4;
b: integer :=4 );
port ( p1,p2,p3,p4: in signed (b-1 downto 0);
w: in signed (b-1 downto 0);
clk: in STD_LOGIC;
a: out signed (2*b-1 downto 0) );
end lab_15_1;
architecture Arch_neuron_one of lab_15_1 is
type weights is array (1 to r) of signed (b-1 downto 0);
type inputs is array (1 to r) of signed (b-1 downto 0);
begin
process (clk, w, p1, p2, p3,p4)
variable weight: weights; variable input: inputs;
variable prod, acc: signed (2*b-1 downto 0);
begin
if (clk'event and clk='1') then
weight :=w & weight (1 to r-1);
end if;
input(1) :=p1; input(2) :=p2; input(3) :=p3; input(4) := p4;
acc := (others => '0');
l1: for j in 1 to r loop
prod := input(j)*weight(j); acc := acc + prod;
end loop l1;
a <= acc;
end process;
end Arch_neuron_one; | gpl-2.0 | 76c07b6790fc32959a8f043eb54cfc37 | 0.633708 | 2.458564 | false | false | false | false |
ObKo/USBCore | Core/usb_xfer.vhdl | 1 | 17,162 | --
-- USB Full-Speed/Hi-Speed Device Controller core - usb_xfer.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
entity usb_xfer is
generic (
HIGH_SPEED: boolean := true
);
port (
rst : in std_logic;
clk : in std_logic;
trn_type : in std_logic_vector(1 downto 0);
trn_address : in std_logic_vector(6 downto 0);
trn_endpoint : in std_logic_vector(3 downto 0);
trn_start : in std_logic;
-- DATA0/1/2 MDATA
rx_trn_data_type : in std_logic_vector(1 downto 0);
rx_trn_end : in std_logic;
rx_trn_data : in std_logic_vector(7 downto 0);
rx_trn_valid : in std_logic;
rx_trn_hsk_type : in std_logic_vector(1 downto 0);
rx_trn_hsk_received : in std_logic;
-- 00 - ACK, 10 - NAK, 11 - STALL, 01 - NYET
tx_trn_hsk_type : out std_logic_vector(1 downto 0);
tx_trn_send_hsk : out std_logic;
tx_trn_hsk_sended : in std_logic;
tx_trn_data_type : out std_logic_vector(1 downto 0);
tx_trn_data_start : out std_logic;
tx_trn_data : out std_logic_vector(7 downto 0);
tx_trn_data_valid : out std_logic;
tx_trn_data_ready : in std_logic;
tx_trn_data_last : out std_logic;
crc_error : in std_logic;
ctl_xfer_endpoint : out std_logic_vector(3 downto 0);
ctl_xfer_type : out std_logic_vector(7 downto 0);
ctl_xfer_request : out std_logic_vector(7 downto 0);
ctl_xfer_value : out std_logic_vector(15 downto 0);
ctl_xfer_index : out std_logic_vector(15 downto 0);
ctl_xfer_length : out std_logic_vector(15 downto 0);
ctl_xfer_accept : in std_logic;
-- '1' when processing control transfer
ctl_xfer : out std_logic;
-- '1' when control request completed
ctl_xfer_done : in std_logic;
ctl_xfer_data_out : out std_logic_vector(7 downto 0);
ctl_xfer_data_out_valid : out std_logic;
ctl_xfer_data_in : in std_logic_vector(7 downto 0);
ctl_xfer_data_in_valid : in std_logic;
ctl_xfer_data_in_last : in std_logic;
ctl_xfer_data_in_ready : out std_logic;
blk_xfer_endpoint : out std_logic_vector(3 downto 0);
blk_in_xfer : out std_logic;
blk_out_xfer : out std_logic;
-- Has complete packet
blk_xfer_in_has_data : in std_logic;
blk_xfer_in_data : in std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : in std_logic;
blk_xfer_in_data_ready : out std_logic;
blk_xfer_in_data_last : in std_logic;
-- Can accept full packet
blk_xfer_out_ready_read : in std_logic;
blk_xfer_out_data : out std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : out std_logic
);
end usb_xfer;
architecture usb_xfer of usb_xfer is
type MACHINE is (S_Idle, S_ControlSetup, S_ControlSetupACK, S_ControlWaitDataIN,
S_ControlDataIN, S_ControlDataIN_Z, S_ControlDataIN_ACK, S_ControlWaitDataOUT,
S_ControlDataOUT, S_ControlDataOUT_MyACK, S_ControlStatusOUT, S_ControlStatusOUT_D,
S_ControlStatusOUT_ACK, S_ControlStatusIN, S_ControlStatusIN_MyACK, S_ControlStatusIN_D,
S_ControlStatusIN_ACK, S_BulkIN, S_BulkIN_MyACK, S_BulkIN_ACK, S_BulkOUT,
S_BulkOUT_ACK);
signal state : MACHINE := S_Idle;
signal rx_counter : std_logic_vector(10 downto 0);
signal tx_counter : std_logic_vector(15 downto 0);
signal ctl_xfer_length_int : std_logic_vector(15 downto 0);
signal ctl_xfer_type_int : std_logic_vector(7 downto 0);
signal data_types : std_logic_vector(15 downto 0);
signal current_endpoint : std_logic_vector(3 downto 0);
signal ctl_status : std_logic_vector(1 downto 0);
signal ctl_xfer_eop : std_logic;
signal tx_counter_over : std_logic;
begin
RX_DATA_COUNT : process(clk) is
begin
if rising_edge(clk) then
if state = S_Idle or state = S_ControlSetupACK then
rx_counter <= (others => '0');
elsif rx_trn_valid = '1' then
rx_counter <= rx_counter + 1;
end if;
end if;
end process;
BIT_TOGGLING : process(clk) is
variable i : integer;
begin
if rising_edge(clk) then
if rst = '1' then
data_types <= (others => '0');
else
i := to_integer(unsigned(current_endpoint));
if state = S_ControlSetupACK then
data_types(i) <= '1';
elsif state = S_ControlDataIN_ACK then
if rx_trn_hsk_received = '1' and rx_trn_hsk_type = "00" then
data_types(i) <= not data_types(i);
end if;
elsif state = S_ControlStatusIN_ACK then
if rx_trn_hsk_received = '1' and rx_trn_hsk_type = "00" then
data_types(i) <= not data_types(i);
end if;
elsif state = S_BulkIN_ACK then
if rx_trn_hsk_received = '1' and rx_trn_hsk_type = "00" then
data_types(i) <= not data_types(i);
end if;
elsif state = S_BulkOUT_ACK then
if tx_trn_hsk_sended = '1' and ctl_status = "00" then
data_types(i) <= not data_types(i);
end if;
end if;
end if;
end if;
end process;
FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
state <= S_Idle;
ctl_xfer <= '0';
else
case state is
when S_Idle =>
ctl_xfer <= '0';
blk_in_xfer <= '0';
blk_out_xfer <= '0';
if trn_start = '1' then
if trn_type = "11" then
state <= S_ControlSetup;
current_endpoint <= trn_endpoint;
elsif trn_type = "10" then
current_endpoint <= trn_endpoint;
if blk_xfer_in_has_data = '1' then
blk_in_xfer <= '1';
tx_trn_data_start <= '1';
tx_counter <= (others => '0');
state <= S_BulkIN;
else
ctl_status <= "11";
state <= S_BulkIN_MyACK;
end if;
elsif trn_type = "00" then
blk_out_xfer <= '1';
current_endpoint <= trn_endpoint;
if blk_xfer_out_ready_read = '1' then
ctl_status <= "00";
else
ctl_status <= "11";
end if;
state <= S_BulkOUT;
end if;
end if;
when S_ControlSetup =>
if rx_trn_valid = '1' then
if rx_counter = 0 then
ctl_xfer_type_int <= rx_trn_data;
elsif rx_counter = 1 then
ctl_xfer_request <= rx_trn_data;
elsif rx_counter = 2 then
ctl_xfer_value(7 downto 0) <= rx_trn_data;
elsif rx_counter = 3 then
ctl_xfer_value(15 downto 8) <= rx_trn_data;
elsif rx_counter = 4 then
ctl_xfer_index(7 downto 0) <= rx_trn_data;
elsif rx_counter = 5 then
ctl_xfer_index(15 downto 8) <= rx_trn_data;
elsif rx_counter = 6 then
ctl_xfer_length_int(7 downto 0) <= rx_trn_data;
elsif rx_counter = 7 then
ctl_xfer_length_int(15 downto 8) <= rx_trn_data;
state <= S_ControlSetupACK;
ctl_xfer <= '1';
end if;
end if;
when S_ControlSetupACK =>
if tx_trn_hsk_sended = '1' then
if ctl_xfer_length_int = 0 then
if ctl_xfer_type_int(7) = '1' then
state <= S_ControlStatusOUT;
else
state <= S_ControlStatusIN;
end if;
elsif ctl_xfer_type_int(7) = '1' then
state <= S_ControlWaitDataIN;
tx_counter <= (others => '0');
elsif ctl_xfer_type_int(7) = '0' then
state <= S_ControlWaitDataOUT;
end if;
end if;
when S_ControlWaitDataIN =>
-- IN Token
if trn_start = '1' and trn_type = "10" then
if ctl_xfer_accept = '1' then
state <= S_ControlDataIN;
else
state <= S_ControlDataIN_Z;
end if;
tx_trn_data_start <= '1';
end if;
when S_ControlWaitDataOUT =>
-- OUT Token
if trn_start = '1' and trn_type = "00" then
if ctl_xfer_accept = '1' then
ctl_status <= "00";
else
ctl_status <= "10";
end if;
state <= S_ControlDataOUT;
end if;
when S_ControlDataOUT =>
if rx_trn_valid = '1' or rx_trn_end = '1' then
if rx_counter(5 downto 0) = 63 or rx_counter = ctl_xfer_length_int - 1 or rx_trn_end = '1' then
state <= S_ControlDataOUT_MyACK;
end if;
end if;
when S_ControlDataOUT_MyACK =>
if tx_trn_hsk_sended = '1' then
if rx_counter = ctl_xfer_length_int then
state <= S_ControlStatusIN;
else
state <= S_ControlWaitDataOUT;
end if;
end if;
when S_ControlDataIN =>
if ctl_xfer_data_in_valid = '1' and tx_trn_data_ready = '1' then
if tx_counter(5 downto 0) = 63 or tx_counter = ctl_xfer_length_int - 1 or
ctl_xfer_data_in_last = '1' then
tx_trn_data_start <= '0';
state <= S_ControlDataIN_ACK;
if ctl_xfer_data_in_last = '1' then
ctl_xfer_eop <= '1';
end if;
end if;
tx_counter <= tx_counter + 1;
end if;
when S_ControlDataIN_Z =>
tx_trn_data_start <= '0';
ctl_xfer_eop <= '1';
state <= S_ControlDataIN_ACK;
when S_ControlDataIN_ACK =>
if rx_trn_hsk_received = '1' then
if rx_trn_hsk_type = "00" then
if tx_counter = ctl_xfer_length_int or ctl_xfer_eop = '1' then
ctl_xfer_eop <= '0';
state <= S_ControlStatusOUT;
else
state <= S_ControlWaitDataIN;
end if;
else
state <= S_Idle;
end if;
end if;
when S_ControlStatusOUT =>
-- OUT Token
if trn_start = '1' and trn_type = "00" then
state <= S_ControlStatusOUT_D;
end if;
when S_ControlStatusOUT_D =>
if rx_trn_end = '1' then
state <= S_ControlStatusOUT_ACK;
if ctl_xfer_done = '1' then
ctl_status <= "00";
else
ctl_status <= "10";
end if;
end if;
when S_ControlStatusOUT_ACK =>
if tx_trn_hsk_sended = '1' then
if ctl_status = "10" then
state <= S_ControlStatusOUT;
else
state <= S_Idle;
end if;
end if;
when S_ControlStatusIN =>
-- IN Token
if trn_start = '1' and trn_type = "10" then
if ctl_xfer_done = '1' then
tx_trn_data_start <= '1';
state <= S_ControlStatusIN_D;
else
ctl_status <= "10";
state <= S_ControlStatusIN_MyACK;
end if;
end if;
when S_ControlStatusIN_MyACK =>
if tx_trn_hsk_sended = '1' then
state <= S_ControlStatusIN;
end if;
when S_ControlStatusIN_D =>
tx_trn_data_start <= '0';
state <= S_ControlStatusIN_ACK;
when S_ControlStatusIN_ACK =>
if rx_trn_hsk_received = '1' then
state <= S_Idle;
end if;
when S_BulkIN =>
if blk_xfer_in_data_valid = '1' and tx_trn_data_ready = '1' then
if tx_counter_over = '1' or blk_xfer_in_data_last = '1' then
tx_trn_data_start <= '0';
state <= S_BulkIN_ACK;
end if;
tx_counter <= tx_counter + 1;
elsif blk_xfer_in_data_valid = '0' then
tx_trn_data_start <= '0';
state <= S_BulkIN_ACK;
end if;
when S_BulkIN_ACK =>
if rx_trn_hsk_received = '1' then
state <= S_Idle;
end if;
when S_BulkIN_MyACK =>
if tx_trn_hsk_sended = '1' then
state <= S_Idle;
end if;
when S_BulkOUT =>
if rx_trn_end = '1' then
state <= S_BulkOUT_ACK;
end if;
when S_BulkOUT_ACK =>
if tx_trn_hsk_sended = '1' then
state <= S_Idle;
end if;
end case;
end if;
end if;
end process;
ctl_xfer_endpoint <= current_endpoint;
blk_xfer_endpoint <= current_endpoint;
tx_trn_hsk_type <= "00" when state = S_ControlSetupACK else
ctl_status;
tx_trn_send_hsk <= '1' when state = S_ControlSetupACK else
'1' when state = S_ControlStatusOUT_ACK else
'1' when state = S_ControlStatusIN_MyACK else
'1' when state = S_BulkIN_MyACK else
'1' when state = S_BulkOUT_ACK else
'1' when state = S_ControlDataOUT_MyACK else
'0';
ctl_xfer_length <= ctl_xfer_length_int;
ctl_xfer_type <= ctl_xfer_type_int;
ctl_xfer_data_in_ready <= tx_trn_data_ready when state = S_ControlDataIN else
'0';
blk_xfer_in_data_ready <= tx_trn_data_ready when state = S_BulkIN else
'0';
tx_trn_data_type <= data_types(to_integer(unsigned(current_endpoint))) & '0';
tx_trn_data <= ctl_xfer_data_in when state = S_ControlDataIN else
blk_xfer_in_data;
tx_trn_data_valid <= ctl_xfer_data_in_valid when state = S_ControlDataIN else
blk_xfer_in_data_valid when state = S_BulkIN else
'0';
tx_counter_over <= '1' when tx_counter(5 downto 0) = 63 AND HIGH_SPEED = false else
'1' when tx_counter(8 downto 0) = 511 AND HIGH_SPEED = true else
'0';
tx_trn_data_last <= '1' when state = S_ControlDataIN and (tx_counter(5 downto 0) = 63 or tx_counter = ctl_xfer_length_int - 1) else
'1' when state = S_BulkIN and (tx_counter_over = '1' or blk_xfer_in_data_last = '1') else
'1' when state = S_ControlStatusIN_D else
'1' when state = S_ControlDataIN_Z else
ctl_xfer_data_in_last when state = S_ControlDataIN else
'0';
blk_xfer_out_data <= rx_trn_data;
blk_xfer_out_data_valid <= rx_trn_valid when state = S_BulkOUT else
'0';
ctl_xfer_data_out <= rx_trn_data;
ctl_xfer_data_out_valid <= rx_trn_valid;
end usb_xfer;
| mit | fd334fc47277e4a2bbf25de8fa99278b | 0.501457 | 3.714719 | false | false | false | false |
peteut/nvc | test/sem/issue311.vhd | 1 | 830 | package TEST is
type EVENT_TYPE is (EVENT_1, EVENT_2);
end TEST;
use WORK.TEST;
entity TEST_NG is
end TEST_NG;
architecture MODEL of TEST_NG is
constant init_event : TEST.EVENT_TYPE := TEST.EVENT_1; -- OK
begin
end MODEL;
-------------------------------------------------------------------------------
package p1 is
type EVENT_TYPE is (EVENT_1, EVENT_2);
end package;
package p2 is
type EVENT_TYPE is (EVENT_1, EVENT_2);
end package;
use work.p1.all;
use work.p2.all;
entity e is
end entity;
architecture a of e is
constant event1 : P1.EVENT_TYPE := P1.EVENT_1; -- OK
constant event2 : P2.EVENT_TYPE := P2.EVENT_1; -- OK
--constant event3 : EVENT_TYPE := EVENT_1; -- Error (not currently caught)
constant event4 : P1.EVENT_TYPE := P2.EVENT_1; -- Error
begin
end architecture;
| gpl-3.0 | 5d08c9f0ce36fa2d1e80321c84087538 | 0.601205 | 3.120301 | false | true | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/test_image/simulation/bmg_stim_gen.vhd | 1 | 7,562 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(8,8);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(7 DOWNTO 0) <= WRITE_ADDR(7 DOWNTO 0);
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 230
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 230 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 8,
DOUT_WIDTH => 8,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| bsd-2-clause | 1a7198f8bde3118a303865add9391b66 | 0.557657 | 3.771571 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weight_hid/simulation/bmg_stim_gen.vhd | 1 | 7,574 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(320,320);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(319 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(7 DOWNTO 0) <= WRITE_ADDR(7 DOWNTO 0);
READ_ADDR_INT(7 DOWNTO 0) <= READ_ADDR(7 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 230
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 230 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 320,
DOUT_WIDTH => 320,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| bsd-2-clause | e71c8f2e65c7ae5efbdbcfe960df0f32 | 0.558358 | 3.777556 | false | false | false | false |
peteut/nvc | test/lower/issue347.vhd | 1 | 2,367 | -- test_ng.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TEST_SUB is
generic (
SIZE_BITS : integer := 32;
COUNT_BITS : integer := 32
);
port (
POOL_SIZE : in std_logic_vector(SIZE_BITS -1 downto 0);
READY_SIZE : in std_logic_vector(SIZE_BITS -1 downto 0);
COUNT : out std_logic_vector(COUNT_BITS-1 downto 0)
);
end TEST_SUB;
architecture RTL of TEST_SUB is
begin
process (POOL_SIZE, READY_SIZE)
variable reserve_size : unsigned(SIZE_BITS-1 downto 0);
constant MAX_COUNT : integer := 2**(COUNT'high);
begin
reserve_size := to_01(unsigned(POOL_SIZE)) - to_01(unsigned(READY_SIZE));
if (reserve_size'length > COUNT'length) then
if (reserve_size > MAX_COUNT) then
COUNT <= std_logic_vector(to_unsigned(MAX_COUNT , COUNT'length));
else
COUNT <= std_logic_vector(resize (reserve_size , COUNT'length));
end if;
else
COUNT <= std_logic_vector(resize (reserve_size , COUNT'length));
end if;
end process;
end RTL;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TEST_NG is
end TEST_NG;
architecture RTL of TEST_NG is
constant SIZE_BITS : integer := 8;
constant COUNT_BITS : integer := 8;
signal POOL_SIZE : std_logic_vector(SIZE_BITS -1 downto 0);
signal READY_SIZE : std_logic_vector(SIZE_BITS -1 downto 0);
signal COUNT : std_logic_vector(COUNT_BITS-1 downto 0);
component TEST_SUB
generic (
SIZE_BITS : integer := 32;
COUNT_BITS : integer := 32
);
port (
POOL_SIZE : in std_logic_vector(SIZE_BITS -1 downto 0);
READY_SIZE : in std_logic_vector(SIZE_BITS -1 downto 0);
COUNT : out std_logic_vector(COUNT_BITS-1 downto 0)
);
end component;
begin
U: TEST_SUB
generic map (
SIZE_BITS => SIZE_BITS ,
COUNT_BITS => COUNT_BITS
)
port map (
POOL_SIZE => POOL_SIZE ,
READY_SIZE => READY_SIZE ,
-- COUNT => COUNT -- OK when COUNT
COUNT => open -- NG when open
);
end RTL;
| gpl-3.0 | 148bf4915631292eda8aa7afbddc9f08 | 0.547106 | 3.624809 | false | true | false | false |
peteut/nvc | test/parse/based.vhd | 1 | 696 | PACKAGE p IS
CONSTANT a : INTEGER := 2#1101#;
CONSTANT b : INTEGER := 3#20#;
CONSTANT c : INTEGER := 8#7#;
CONSTANT d : INTEGER := 10#1234#;
CONSTANT e : INTEGER := 16#beef01#;
CONSTANT f : INTEGER := 2#1_0#;
CONSTANT g : INTEGER := 2:1_0:;
CONSTANT h : INTEGER := 16#abababab#;
CONSTANT i : INTEGER := 16#1A#;
CONSTANT j : INTEGER := 2#1111_1111#;
CONSTANT k : INTEGER := 16#FF#;
CONSTANT l : INTEGER := 016#0FF#;
CONSTANT m : INTEGER := 16#E#E1;
CONSTANT n : INTEGER := 2#1110_0000#;
CONSTANT o : REAL := 16#F.FF#E+2;
CONSTANT p : REAL := 2#1.1111_1111_111#E11;
CONSTANT n : INTEGER := 2:1110_0000:;
CONSTANT o : REAL := 16:F.FF:E+2;
END PACKAGE;
| gpl-3.0 | 1a4a168cd021253bc768694fd919847d | 0.596264 | 3.012987 | false | false | false | false |
peteut/nvc | test/regress/record6.vhd | 2 | 1,343 | entity record6 is
end entity;
architecture test of record6 is
type rec is record
x : bit_vector(1 to 3);
y : integer;
end record;
type rec_array is array (natural range <>) of rec;
function make_rec(x : bit_vector(1 to 3); y : integer) return rec is
variable r : rec;
begin
r.x := x;
r.y := y;
return r;
end function;
function make_rec_array(x : rec; l, r : natural) return rec_array is
variable ra : rec_array(l to r) := (others => x);
begin
return ra;
end function;
function get_bit(v : in rec) return bit is
begin
return v.x(v.y);
end function;
begin
process is
variable r : rec;
variable one : integer := 1; -- Prevent constant folding
begin
r.x := "101";
r.y := 1;
assert get_bit(r) = '1';
r.y := 2;
assert get_bit(r) = '0';
assert get_bit(make_rec("011", one + 1)) = '1';
r.x := make_rec("010", one).x;
assert r.x = "010";
r.y := make_rec("010", one).y;
assert r.y = 1;
r := make_rec("010", one);
assert make_rec_array(r, 1, 2) = ( ("010", 1), ("010", 1) );
assert make_rec_array(("111", 5), one, 2) = ( ("111", 5), ("111", 5) );
wait;
end process;
end architecture;
| gpl-3.0 | f0170697b1621b32b46e889e9de13516 | 0.504095 | 3.283619 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/syspll.vhd | 1 | 2,843 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : syspll.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-06
-- Last update: 2016-05-06
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: System PLL
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-06 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--library work;
--use work.util_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity syspll is
port (
-- Clock in ports
ocxo_clk : IN std_logic;
fclk : IN std_logic;
clk_sel : in std_logic;
-- Clock out ports
clk : out std_logic;
-- Status and control signals
pll_rst_n : in std_logic;
locked : out std_logic
);
end syspll;
architecture structure of syspll is
component ocxo_clk_pll
port (
-- Clock in ports
clk_in1 : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
resetn : in std_logic;
locked : out std_logic
);
end component;
attribute SYN_BLACK_BOX : boolean;
attribute SYN_BLACK_BOX of ocxo_clk_pll : component is true;
attribute BLACK_BOX_PAD_PIN : string;
attribute BLACK_BOX_PAD_PIN of ocxo_clk_pll : component is "clk_in1,clk_out1,resetn,locked";
signal pll_clk0 : std_logic;
signal pll_locked : std_logic;
begin
syspll : ocxo_clk_pll
port map (
-- Clock in ports
clk_in1 => ocxo_clk,
-- Clock out ports
clk_out1 => pll_clk0,
-- Status and control signals
resetn => pll_rst_n,
locked => pll_locked
);
clkmux: BUFGMUX_CTRL
port map (
O => clk,
I0 => fclk,
I1 => pll_clk0,
S => pll_locked
);
--clkbuf: BUFG
-- port map (
-- O => clk,
-- I => pll_clk0
-- );
locked<= pll_locked;
end structure;
| gpl-3.0 | dc344431d848d5ac2f5615a64b6265bf | 0.414351 | 4.414596 | false | false | false | false |
peteut/nvc | test/regress/issue351.vhd | 2 | 1,460 | use std.textio.all;
entity ISSUE351 is
end ISSUE351;
architecture RTL of ISSUE351 is
type WORD_TYPE is record
KEY : integer;
VALUE : integer;
end record;
constant WORD_NULL : WORD_TYPE := (KEY => 0, VALUE => 0);
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
procedure dump_words(WORDS: in WORD_VECTOR)
is
variable text_line : LINE;
begin
for i in WORDS'range loop
WRITE(text_line, string'(" | "));
WRITE(text_line, i, LEFT, 5);
WRITE(text_line, string'(" | "));
WRITE(text_line, WORDS(i).KEY , LEFT, 10);
WRITE(text_line, string'(" | "));
WRITE(text_line, WORDS(i).VALUE, LEFT, 10);
WRITELINE(OUTPUT, text_line);
end loop;
end procedure;
begin
process
variable curr_queue : WORD_VECTOR(0 to 3);
variable text_line : LINE;
begin
for i in curr_queue'range loop
curr_queue(i).KEY := i;
curr_queue(i).VALUE := i;
end loop;
for i in curr_queue'range loop
WRITE(text_line, i);
WRITE(text_line, string'(" to "));
WRITE(text_line, curr_queue'length-1);
WRITELINE(OUTPUT, text_line);
dump_words(curr_queue(i to curr_queue'length-1)); -- Bug?
end loop;
wait;
end process;
end RTL;
| gpl-3.0 | 224922695f307140dd5fdeeb89f15528 | 0.521918 | 3.792208 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/regs.vhd | 1 | 24,569 | -------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : regs.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-03-13
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Register interface to the EPC bus
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-13 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
--
-- Address range: 0x8060_0000 - 0x8060_FFFF
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0000 | GIT Abbreviated Commit Hash |
--
-- 0x8060_0004 | Hr 10 | Hr 1 | Min 10| Min 1 | Build |
--
-- 0x8060_0008 | Year | Year | Year | Year | Mon 10| Mon 1 | Day 10| Day 1 |
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0100 | TSC LSB |
--
-- 0x8060_0104 | TSC MSB |
--
-- 0x8060_0108 | TSC LSB @ last second |
--
-- 0x8060_010c | TSC MSB @ last second |
--
-- 0x8060_0110 | 1PPS Phase Error |
--
-- 0x8060_0114 | 1PPS Frequency Error |
--
-- 0x8060_0118 | GPS 1PPS Count |
--
-- 0x8060_011c | 10 h | 1 h | 10 m | 1 m | 10 s | 1 s | 100 ms| 10 ms |
--
-- 0x8060_0120 | | 10 h | 1 h | 10 m | 1 m | 10 s | 1 s |
--
-- 0x8060_0124 | | | | | | | | DAC value |
-- | | | |
-- GPS 3D Fix | | Sync clock
-- | Sync PFD
-- |
-- PFD Status
--
-- 0x8060_0128 | | | |
-- | |
-- GPS PPS IRQ ENA |
-- TSC PPS IRQ ENA
--
-- 0x8060_012c | | | | |
-- | | |
-- PPS IRQ Status GPS PPS IRQ |
-- TSC PPS IRQ
--
-- 0x8060_0130 | | | | |
-- | | |
-- PFD trigger IRQ ENA | |
-- PFD GPS PPS IRQ ENA |
-- PFD TSC PPS IRQ ENA
--
-- 0x8060_0134 | | | | | |
-- | | | |
-- PLL IRQ Status PFD trigger IRQ | |
-- PFD GPS PPS IRQ |
-- PFD TSC PPS IRQ
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0200 | uSPR | | Fan pwm |
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_0300 | | disp page | | stat | disp pdm |
--
--
-- -----------------------------------------------------------------------------
-- | 3 | 2 | 1 | 0 |
-- |1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|9|8|7|6|5|4|3|2|1|0|
--
-- 0x8060_1000 | xor 1 | digit 1 | xor 0 | digit 0 |
--
-- 0x8060_1004 | xor 3 | digit 3 | xor 2 | digit 2 |
--
-- 0x8060_1008 | xor 5 | digit 5 | xor 4 | digit 4 |
--
-- 0x8060_100c | xor 7 | digit 7 | xor 6 | digit 6 |
--
-- 0x8060_1010 | xor 9 | digit 9 | xor 8 | digit 8 |
--
-- 0x8060_1014 | xor 11 | digit 11 | xor 10 | digit 10 |
--
-- 0x8060_1018 | xor 13 | digit 13 | xor 12 | digit 12 |
--
-- 0x8060_101c | xor 15 | digit 15 | xor 14 | digit 14 |
--
-- 0x8060_1020 | xor 17 | digit 17 | xor 16 | digit 16 |
--
-- 0x8060_1024 | xor 19 | digit 19 | xor 18 | digit 18 |
--
-- 0x8060_1028 | xor 21 | digit 21 | xor 20 | digit 20 |
--
-- 0x8060_102c | xor 23 | digit 23 | xor 22 | digit 22 |
--
-- 0x8060_1030 | xor 25 | digit 25 | xor 24 | digit 24 |
--
-- 0x8060_1034 | xor 27 | digit 27 | xor 26 | digit 26 |
--
-- 0x8060_1038 | xor 29 | digit 29 | xor 28 | digit 28 |
--
-- 0x8060_103c | xor 31 | digit 31 | xor 30 | digit 30 |
--
-- 0x8060_1040 | RAM Page 1 |
-- 0x8060_1080 | RAM Page 2 |
-- | ... |
-- 0x8060_1080 | RAM Page 1f |
-- 0x8060_17FC | RAM |
--
-- 0x8060_1800 | lut 3 | lut 2 | lut 1 | lut 0 |
--
-- 0x8060_1804 | lut 7 | lut 6 | lut 5 | lut 4 |
--
-- 0x8060_1808 | lut 11 | lut 10 | lut 9 | lut 8 |
--
-- 0x8060_180c | lut 15 | lut 14 | lut 13 | lut 12 |
--
-- 0x8060_1810 | lut 19 | lut 18 | lut 17 | lut 16 |
--
--
-- 0x8060_187C | lut 127 | lut 126 | lut 125 | lut 124 |
--
-- 0x8060_1880 | RAM |
-- 0x8060_1FFC | RAM |
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
use work.version_pkg.all;
entity regs is
port (
rst_n : in std_logic;
clk : in std_logic;
EPC_INTF_addr : in std_logic_vector(0 to 31);
EPC_INTF_be : in std_logic_vector(0 to 3);
EPC_INTF_burst : in std_logic;
EPC_INTF_cs_n : in std_logic;
EPC_INTF_data_i : out std_logic_vector(0 to 31);
EPC_INTF_data_o : in std_logic_vector(0 to 31);
EPC_INTF_rdy : out std_logic;
EPC_INTF_rnw : in std_logic; -- Write when '0'
-- Time stamp counter
tsc_cnt : in std_logic_vector(63 downto 0);
tsc_cnt1 : in std_logic_vector(63 downto 0);
tsc_read : out std_logic;
-- Time setting
cur_time : in time_ty;
set : out std_logic;
set_time : out time_ty;
-- PLL control
gps_3dfix_d : in std_logic;
gps_1pps_d : in std_logic;
tsc_1pps_d : in std_logic;
pll_trig : in std_logic;
pfd_status : in std_logic;
pdiff_1pps : in std_logic_vector(31 downto 0);
fdiff_1pps : in std_logic_vector(31 downto 0);
tsc_sync : out std_logic;
pfd_resync : out std_logic;
dac_val : out std_logic_vector(15 downto 0);
pps_irq : out std_logic;
pll_irq : out std_logic;
-- Fan us per revolution, percent speed
fan_uspr : in std_logic_vector(19 downto 0);
fan_pct : out std_logic_vector(7 downto 0);
-- Display memory
sram_addr : out std_logic_vector(9 downto 0);
sram_we : out std_logic;
sram_datao : out std_logic_vector(31 downto 0);
sram_datai : in std_logic_vector(31 downto 0);
stat_src : out std_logic_vector(3 downto 0);
disp_page : out std_logic_vector(7 downto 0);
disp_pdm : out std_logic_vector(7 downto 0)
);
end regs;
architecture rtl of regs is
type reg_arr is array (natural range <>) of std_logic_vector(31 downto 0);
signal time_regs : reg_arr(13 downto 0);
signal fan_regs : reg_arr(0 downto 0);
signal disp_regs : reg_arr(0 downto 0);
signal addr : std_logic_vector(31 downto 0);
signal be : std_logic_vector(3 downto 0);
signal data_i : std_logic_vector(31 downto 0);
signal data_o : std_logic_vector(31 downto 0);
signal cs_n_d : std_logic;
signal cs_dp_r : std_logic;
signal cs_dp_w : std_logic;
signal rnw : std_logic;
signal rdy_d : std_logic_vector(2 downto 0);
signal decode : std_logic_vector(3 downto 0);
signal sram : std_logic;
SIGNAL gps_1pps_cnt : std_logic_vector(31 downto 0);
signal ver_regs_mux : std_logic_vector(31 downto 0);
signal time_regs_mux : std_logic_vector(31 downto 0);
signal fan_regs_mux : std_logic_vector(31 downto 0);
signal disp_regs_mux : std_logic_vector(31 downto 0);
signal sram_regs_mux : std_logic_vector(31 downto 0);
begin
-- Big endian to little endian
addr <= EPC_INTF_addr;
be <= EPC_INTF_be;
data_o <= EPC_INTF_data_o;
-- Little endian to big endian
EPC_INTF_data_i <= data_i;
-- Chip select falling edge detect
process (rst_n, clk) is
begin
if (rst_n = '0') then
rnw <= '0';
cs_n_d <= '1';
cs_dp_r <= '0'; -- Chip select read pulse
cs_dp_w <= '0'; -- Chip select write pulse
decode <= (others => '0');
sram <= '0';
elsif (clk'event and clk = '1') then
rnw <= not EPC_INTF_rnw;
cs_n_d <= EPC_INTF_cs_n;
cs_dp_r <= not EPC_INTF_cs_n and cs_n_d and EPC_INTF_rnw;
cs_dp_w <= not EPC_INTF_cs_n and cs_n_d and not EPC_INTF_rnw;
-- First level decode
if (EPC_INTF_cs_n = '0') then
if (addr(12) = '1') then
decode <= (others => '0');
sram <= '1';
else
decode(conv_integer(addr(9 downto 8))) <= '1';
sram <= '0';
end if;
else
decode <= (others => '0');
sram <= '0';
end if;
end if;
end process;
-- Ready signal generator, 4 cycles after delayed chip select
-- Hold ready active until the chip select goes inactive
process (rst_n, clk) is
begin
if (rst_n = '0') then
rdy_d <= (others => '1');
EPC_INTF_rdy <= '0';
elsif (clk'event and clk = '1') then
rdy_d(0) <= cs_dp_r or cs_dp_w;
rdy_d(1) <= rdy_d(0);
rdy_d(2) <= rdy_d(1);
if (EPC_INTF_cs_n = '1') then
EPC_INTF_rdy <= '0';
elsif (rdy_d(2) = '1') then
EPC_INTF_rdy <= '1';
end if;
end if;
end process;
-- Top decode read mux
process (rst_n, clk) is
begin
if (rst_n = '0') then
data_i <= (others => '0');
elsif (clk'event and clk = '1') then
if (sram = '1') then
data_i <= sram_regs_mux;
elsif (decode(0) = '1') then
data_i <= ver_regs_mux;
elsif (decode(1) = '1') then
data_i <= time_regs_mux;
elsif (decode(2) = '1') then
data_i <= fan_regs_mux;
elsif (decode(3) = '1') then
data_i <= disp_regs_mux;
end if;
end if;
end process;
-- Read Mux
process (rst_n, clk) is
begin
if (rst_n = '0') then
ver_regs_mux <= (others => '0');
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
sram_regs_mux <= (others => '0');
elsif (clk'event and clk = '1') then
if (cs_n_d = '0') then
sram_regs_mux <= sram_datai;
case addr(5 downto 2) is
when "0000" =>
ver_regs_mux <= GIT_COMMIT;
fan_regs_mux <= fan_regs(0);
fan_regs_mux(31 downto 12) <= fan_uspr;
disp_regs_mux <= disp_regs(0);
when "0001" =>
ver_regs_mux <= TIME_CODE;
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
when "0010" =>
ver_regs_mux <= DATE_CODE;
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
when others =>
ver_regs_mux <= (others => '0');
fan_regs_mux <= (others => '0');
disp_regs_mux <= (others => '0');
end case;
end if;
end if;
end process;
-- Read Mux (time_regs)
process (rst_n, clk) is
begin
if (rst_n = '0') then
time_regs_mux <= (others => '0');
tsc_read <= '0';
elsif (clk'event and clk = '1') then
if (cs_n_d = '0') then
case addr(5 downto 2) is
when "0000" =>
time_regs_mux <= tsc_cnt(31 downto 0);
when "0001" =>
time_regs_mux <= tsc_cnt(63 downto 32);
when "0010" =>
time_regs_mux <= tsc_cnt1(31 downto 0);
when "0011" =>
time_regs_mux <= tsc_cnt1(63 downto 32);
when "0100" =>
time_regs_mux <= pdiff_1pps;
when "0101" =>
time_regs_mux <= fdiff_1pps;
when "0110" =>
time_regs_mux <= gps_1pps_cnt;
when "0111" =>
time_regs_mux <= cur_time.t_10h & cur_time.t_1h &
cur_time.t_10m & cur_time.t_1m &
cur_time.t_10s & cur_time.t_1s &
cur_time.t_100ms & cur_time.t_10ms;
when "1000" =>
time_regs_mux <= time_regs(8);
when "1001" =>
time_regs_mux <= time_regs(9);
time_regs_mux(31) <= gps_3dfix_d;
time_regs_mux(23) <= pfd_status;
when "1010" =>
time_regs_mux <= time_regs(10);
when "1011" =>
time_regs_mux <= time_regs(11);
when "1100" =>
time_regs_mux <= time_regs(12);
when "1101" =>
time_regs_mux <= time_regs(13);
when others =>
time_regs_mux <= (others => '0');
end case;
end if;
-- Latch tsc value on LSW read
if (cs_dp_r = '1' and decode(1) = '1' and addr(5 downto 2) = "0000") then
tsc_read <= '1';
else
tsc_read <= '0';
end if;
end if;
end process;
-- time control registers
process (rst_n, clk) is
variable pps_irq_status : std_logic;
variable pll_irq_status : std_logic;
begin
if (rst_n = '0') then
for i in time_regs'range loop
time_regs(i) <= (others => '0');
end loop;
pps_irq <= '0';
pll_irq <= '0';
set <= '0';
time_regs(9)(15 downto 0) <= x"8000";
elsif (clk'event and clk = '1') then
if (cs_dp_w = '1' and decode(1) = '1') then
case addr(5 downto 2) is
when "0000" =>
time_regs(0) <= data_o;
when "0001" =>
time_regs(1) <= data_o;
when "0010" =>
time_regs(2) <= data_o;
when "0011" =>
time_regs(3) <= data_o;
when "0100" =>
time_regs(4) <= data_o;
when "0101" =>
time_regs(5) <= data_o;
when "0110" =>
time_regs(6) <= data_o;
when "0111" =>
time_regs(7) <= data_o;
when "1000" =>
time_regs(8) <= data_o;
when "1001" =>
time_regs(9) <= data_o;
when "1010" =>
time_regs(10) <= data_o;
when "1011" =>
time_regs(11)(30 downto 2) <= data_o(30 downto 2);
-- Clear interrupt with 1 is written back
if (data_o(1) = '1') then
time_regs(11)(1) <= '0';
end if;
if (data_o(0) = '1') then
time_regs(11)(0) <= '0';
end if;
when "1100" =>
time_regs(12) <= data_o;
when "1101" =>
time_regs(13)(30 downto 3) <= data_o(30 downto 3);
-- Clear interrupt with 1 is written back
if (data_o(2) = '1') then
time_regs(13)(2) <= '0';
end if;
if (data_o(1) = '1') then
time_regs(13)(1) <= '0';
end if;
if (data_o(0) = '1') then
time_regs(13)(0) <= '0';
end if;
when others =>
null;
end case;
end if;
pps_irq_status := (time_regs(10)(1) and time_regs(11)(1)) or
(time_regs(10)(0) and time_regs(11)(0));
pps_irq <= pps_irq_status;
time_regs(11)(31) <= pps_irq_status;
-- Set interrupt on incoming pps pulses
-- Higher priority than clear (above)
if (gps_1pps_d = '1') then
time_regs(11)(1) <= '1';
end if;
if (tsc_1pps_d = '1') then
time_regs(11)(0) <= '1';
end if;
pll_irq_status := (time_regs(12)(2) and time_regs(13)(2)) or
(time_regs(12)(1) and time_regs(13)(1)) or
(time_regs(12)(0) and time_regs(13)(0));
pll_irq <= pll_irq_status;
time_regs(13)(31) <= pll_irq_status;
-- Set interrupt on incoming pps pulses and pll trigger
-- Higher priority than clear (above)
if (pll_trig = '1') then
time_regs(13)(2) <= '1';
end if;
if (gps_1pps_d = '1') then
time_regs(13)(1) <= '1';
end if;
if (tsc_1pps_d = '1') then
time_regs(13)(0) <= '1';
end if;
-- Trigger time set
if (cs_dp_w = '1' and decode(1) = '1' and addr(5 downto 2) = "1000") then
set <= '1';
else
set <= '0';
end if;
-- Clear the sync flag after its done
if (gps_1pps_d = '1' and time_regs(9)(20) = '1') then
time_regs(9)(20) <= '0';
end if;
-- Clear the pfd sync control when the PFD is in the sync state
if (pfd_status = '1') then
time_regs(9)(21) <= '0';
end if;
end if;
end process;
set_time.t_1ms <= (others => '0');
set_time.t_10ms <= (others => '0');
set_time.t_100ms <= (others => '0');
set_time.t_1s <= time_regs(8)(3 downto 0);
set_time.t_10s <= time_regs(8)(7 downto 4);
set_time.t_1m <= time_regs(8)(11 downto 8);
set_time.t_10m <= time_regs(8)(15 downto 12);
set_time.t_1h <= time_regs(8)(19 downto 16);
set_time.t_10h <= time_regs(8)(23 downto 20);
dac_val <= time_regs(9)(15 downto 0);
tsc_sync <= time_regs(9)(20);
pfd_resync <= time_regs(9)(21);
-- Fan control registers
process (rst_n, clk) is
begin
if (rst_n = '0') then
for i in 0 to 0 loop
fan_regs(i) <= (others => '0');
end loop;
fan_regs(0)(7 downto 0) <= x"ff";
elsif (clk'event and clk = '1') then
if (cs_dp_w = '1' and decode(2) = '1') then
case addr(5 downto 2) is
when "0000" =>
fan_regs(0) <= data_o;
when others =>
null;
end case;
end if;
end if;
end process;
fan_pct <= fan_regs(0)(7 downto 0);
-- disp control registers
process (rst_n, clk) is
begin
if (rst_n = '0') then
for i in 0 to 0 loop
disp_regs(i) <= (others => '0');
end loop;
disp_regs(0)(7 downto 0) <= x"ff";
sram_addr <= (others => '0');
sram_we <= '0';
sram_datao <= (others => '0');
elsif (clk'event and clk = '1') then
if (cs_dp_w = '1' and decode(3) = '1') then
case addr(5 downto 2) is
when "0000" =>
disp_regs(0) <= data_o;
when others =>
null;
end case;
end if;
sram_addr <= addr(11 downto 2);
sram_we <= sram and cs_dp_w;
sram_datao <= data_o;
end if;
end process;
disp_pdm <= disp_regs(0)(7 downto 0);
stat_src <= disp_regs(0)(11 downto 8);
disp_page <= disp_regs(0)(23 downto 16);
-- GPS 1pps count register
process (rst_n, clk) is
begin
if (rst_n = '0') then
gps_1pps_cnt <= (others => '0');
elsif (clk'event and clk = '1') then
if (gps_1pps_d = '1') then
gps_1pps_cnt <= gps_1pps_cnt + 1;
end if;
end if;
end process;
end rtl;
| gpl-3.0 | e592342d1d04482b595cd35acebc1ad6 | 0.358134 | 3.728225 | false | false | false | false |
UnofficialRepos/OSVVM | NameStorePkg.vhd | 1 | 14,815 | --
-- File Name: NameStorePkg.vhd
-- Design Unit Name: NameStorePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for name.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated NewID for Updated NewID and Find with ParentID and Search.
-- Supports searching in CoveragePkg, ScoreboardGenericPkg, and MemoryPkg.
-- 06/2021 2021.06 Initial revision. Derrived from NamePkg.vhd
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2021-2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
use work.ResolutionPkg.all ;
use work.AlertLogPkg.all ;
package NameStorePkg is
type NameIDType is record
ID : integer_max ;
end record NameIDType ;
alias NameStoreIDType is NameIDType ;
type NameIDArrayType is array (integer range <>) of NameIDType ;
type NameSearchType is (PRIVATE, NAME, NAME_AND_PARENT, NAME_AND_PARENT_ELSE_PRIVATE) ;
constant ID_NOT_FOUND : NameIDType := (ID => -1) ;
------------------------------------------------------------
impure function NewID (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType ;
------------------------------------------------------------
procedure Set (
ID : NameIDType ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) ;
impure function Get (ID : NameIDType ; DefaultName : string := "") return string ;
------------------------------------------------------------
impure function Find (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType ;
impure function GetOpt (ID : NameIDType) return string ;
impure function IsSet (ID : NameIDType) return boolean ;
procedure Clear (ID : NameIDType) ; -- clear name
procedure Deallocate(ID : NameIDType) ; -- effectively alias to clear name
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolveSearch (
UniqueParent : boolean ;
Search : NameSearchType
) return NameSearchType ;
type NameStorePType is protected
------------------------------------------------------------
impure function NewID (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer ;
------------------------------------------------------------
procedure Set (
ID : integer ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) ;
impure function Get (ID : integer ; DefaultName : string := "") return string ;
------------------------------------------------------------
impure function Find (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer ;
impure function GetOpt (ID : integer) return string ;
impure function IsSet (ID : integer) return boolean ;
procedure Clear (ID : integer) ; -- clear name
procedure Deallocate(ID : integer) ; -- effectively alias to clear name
end protected NameStorePType ;
end package NameStorePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body NameStorePkg is
type NameStorePType is protected body
type NameItemRecType is record
Name : Line ;
ParentID : AlertLogIDType ;
Search : NameSearchType ;
end record NameItemRecType ;
type NameArrayType is array (integer range <>) of NameItemRecType ;
type NameArrayPtrType is access NameArrayType ;
-- type LineArrayType is array (integer range <>) of Line ;
-- type LineArrayPtrType is access LineArrayType ;
-- variable NameArrayPtr : LineArrayPtrType ;
variable NameArrayPtr : NameArrayPtrType ;
variable NumItems : integer := 0 ;
-- constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer ;
variable ModNumItems : integer ;
begin
NormNumItems := NewNumItems ;
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable ItemArrayPtr : InOut NameArrayPtrType ;
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
-- constant NewNumItems : in integer ;
-- constant CurNumItems : in integer ;
constant MinNumItems : in integer
) is
variable oldItemArrayPtr : NameArrayPtrType ;
constant NewNumItems : integer := NumItems + GrowAmount ;
constant NewSize : integer := NormalizeArraySize(NewNumItems, MinNumItems) ;
begin
if ItemArrayPtr = NULL then
ItemArrayPtr := new NameArrayType(1 to NewSize) ;
elsif NewNumItems > ItemArrayPtr'length then
oldItemArrayPtr := ItemArrayPtr ;
ItemArrayPtr := new NameArrayType(1 to NewSize) ;
ItemArrayPtr(1 to NumItems) := oldItemArrayPtr(1 to NumItems) ;
deallocate(oldItemArrayPtr) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer is
begin
GrowNumberItems(NameArrayPtr, NumItems, 1, MIN_NUM_ITEMS) ;
Set(NumItems, iName, ParentID, Search) ;
return NumItems ;
end function NewID ;
------------------------------------------------------------
procedure Set (
------------------------------------------------------------
ID : integer ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) is
begin
deallocate(NameArrayPtr(ID).Name) ;
NameArrayPtr(ID).Name := new string'(iName) ;
NameArrayPtr(ID).Search := Search ;
NameArrayPtr(ID).ParentID := ParentID ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ID : integer ; DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NameArrayPtr(ID).Name = NULL then
return DefaultName ;
else
return NameArrayPtr(ID).Name.all ;
end if ;
end function Get ;
------------------------------------------------------------
-- Local
impure function FindName (iName : String) return integer is
------------------------------------------------------------
begin
for ID in 1 to NumItems loop
-- skip if private
next when NameArrayPtr(ID).Search = PRIVATE ;
-- find Name
if iName = NameArrayPtr(ID).Name.all then
return ID ;
end if ;
end loop ;
return ID_NOT_FOUND.ID ;
end function FindName ;
------------------------------------------------------------
-- Local
impure function FindNameAndParent (iName : String; ParentID : AlertLogIdType) return integer is
------------------------------------------------------------
begin
for ID in 1 to NumItems loop
-- skip if private
next when NameArrayPtr(ID).Search = PRIVATE ;
-- find Name and Parent
if iName = NameArrayPtr(ID).Name.all and (ParentID = NameArrayPtr(ID).ParentID or NameArrayPtr(ID).Search = NAME) then
return ID ;
end if ;
end loop ;
return ID_NOT_FOUND.ID ;
end function FindNameAndParent ;
------------------------------------------------------------
impure function Find (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer is
begin
case Search is
when PRIVATE => return ID_NOT_FOUND.ID ;
when NAME => return FindName(iName) ;
when others => return FindNameAndParent(iName, ParentID) ;
end case ;
end function Find ;
------------------------------------------------------------
impure function GetOpt (ID : integer) return string is
------------------------------------------------------------
begin
if NameArrayPtr(ID).Name = NULL then
return NUL & "" ;
else
return NameArrayPtr(ID).Name.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet (ID : integer) return boolean is
------------------------------------------------------------
begin
return NameArrayPtr(ID).Name /= NULL ;
end function IsSet ;
------------------------------------------------------------
procedure Clear (ID : integer) is
------------------------------------------------------------
begin
deallocate(NameArrayPtr(ID).Name) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate(ID : integer) is
------------------------------------------------------------
begin
Clear(ID) ;
end procedure Deallocate ;
end protected body NameStorePType ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Singleton Data Structure
-- /////////////////////////////////////////
-- /////////////////////////////////////////
shared variable NameStore : NameStorePType ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType is
variable Result : NameIDType ;
begin
Result.ID := NameStore.NewID(iName) ;
return Result ;
end function NewID ;
------------------------------------------------------------
procedure Set (
------------------------------------------------------------
ID : NameIDType ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) is
begin
NameStore.set(ID.ID, iName) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ID : NameIDType ; DefaultName : string := "") return string is
------------------------------------------------------------
begin
return NameStore.Get(ID.ID, DefaultName) ;
end function Get ;
------------------------------------------------------------
impure function Find (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType is
begin
return NameIDType'(ID => NameStore.Find(iName)) ;
end function Find ;
------------------------------------------------------------
impure function GetOpt (ID : NameIDType) return string is
------------------------------------------------------------
begin
return NameStore.Get(ID.ID) ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet (ID : NameIDType) return boolean is
------------------------------------------------------------
begin
return NameStore.IsSet(ID.ID) ;
end function IsSet ;
------------------------------------------------------------
procedure Clear (ID : NameIDType) is
------------------------------------------------------------
begin
NameStore.Clear(ID.ID) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate(ID : NameIDType) is
------------------------------------------------------------
begin
NameStore.Clear(ID.ID) ;
end procedure Deallocate ;
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolveSearch (
------------------------------------------------------------
UniqueParent : boolean ;
Search : NameSearchType
) return NameSearchType is
variable result : NameSearchType ;
begin
if search = NAME_AND_PARENT_ELSE_PRIVATE then
result := NAME_AND_PARENT when UniqueParent else PRIVATE ;
else
result := Search ;
end if ;
return result ;
end function ResolveSearch ;
end package body NameStorePkg ; | artistic-2.0 | ff7f904f34f9a027f19c18f5e46cb2bc | 0.483361 | 5.178259 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_dverif.vhd | 1 | 5,521 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
ENTITY counter_fifo_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF counter_fifo_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:counter_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
| gpl-2.0 | 8522f936899f1145b5756f9f35fae949 | 0.576345 | 4.117077 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/address_unit/address_logic.vhd | 1 | 844 |
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY ADDRESS_LOGIC IS
PORT (
PCside: IN std_logic_vector (7 DOWNTO 0);
Iside : IN std_logic_vector (7 DOWNTO 0);
ALout : OUT std_logic_vector (7 DOWNTO 0);
ResetPC, Im, PCplus1 : IN std_logic
);
END ADDRESS_LOGIC;
ARCHITECTURE ADDRESS_LOGIC_ARCH of ADDRESS_LOGIC IS
BEGIN
PROCESS (PCside, Iside, ResetPC,
Im, PCplus1)
VARIABLE temp : std_logic_vector (2 DOWNTO 0);
BEGIN
temp := (ResetPC & Im & PCplus1);
CASE temp IS
WHEN "100" => ALout <= (OTHERS => '0');
WHEN "010" => ALout <= Iside;
WHEN "001" => ALout <= std_logic_vector(unsigned(PCside) + 1);
WHEN OTHERS => ALout <= PCside;
END CASE;
END PROCESS;
END ADDRESS_LOGIC_ARCH; | gpl-3.0 | b7e2b6e2065ac21cfd660622ed9c3c0d | 0.584123 | 3.417004 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_eb_fifo_counted_resized/example_design/k7_eb_fifo_counted_resized_exdes.vhd | 1 | 6,066 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_eb_fifo_counted_resized_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity k7_eb_fifo_counted_resized_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
VALID : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end k7_eb_fifo_counted_resized_exdes;
architecture xilinx of k7_eb_fifo_counted_resized_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component k7_eb_fifo_counted_resized is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(15-1 DOWNTO 0);
VALID : OUT std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
PROG_EMPTY : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(64-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : k7_eb_fifo_counted_resized
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
VALID => valid,
RST => rst,
PROG_FULL => prog_full,
PROG_EMPTY => prog_empty,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | 1061fcae25761419774db1fe85a16c90 | 0.506594 | 4.680556 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/proc_common_v3_00_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_ipif_pkg.vhd | 1 | 53,549 | -------------------------------------------------------------------------------
-- IPIF Common Library Package
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2002-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_ipif_pkg.vhd
-- Version: Intital
-- Description: This file contains the constants and functions used in the
-- ipif common library components.
--
-------------------------------------------------------------------------------
-- Structure:
--
-------------------------------------------------------------------------------
-- Author: DET
-- History:
-- DET 02/21/02 -- Created from proc_common_pkg.vhd
--
-- DET 03/13/02 -- PLB IPIF development updates
-- ^^^^^^
-- - Commented out string types and string functions due to an XST
-- problem with string arrays and functions. THe string array
-- processing functions were replaced with comperable functions
-- operating on integer arrays.
-- ~~~~~~
--
--
-- DET 4/30/2002 Initial
-- ~~~~~~
-- - Added three functions: rebuild_slv32_array, rebuild_slv64_array, and
-- rebuild_int_array to support removal of unused elements from the
-- ARD arrays.
-- ^^^^^^ --
--
-- FLO 8/12/2002
-- ~~~~~~
-- - Added three functions: bits_needed_for_vac, bits_needed_for_occ,
-- and get_id_index_iboe.
-- (Removed provisional functions bits_needed_for_vacancy,
-- bits needed_for_occupancy, and bits_needed_for.)
-- ^^^^^^
--
-- FLO 3/24/2003
-- ~~~~~~
-- - Added dependent property paramters for channelized DMA.
-- - Added common property parameter array type.
-- - Definded the KEYHOLD_BURST common-property parameter.
-- ^^^^^^
--
-- FLO 10/22/2003
-- ~~~~~~
-- - Some adjustment to CHDMA parameterization.
-- - Cleanup of obsolete code and comments. (The former "XST workaround"
-- has become the officially deployed method.)
-- ^^^^^^
--
-- LSS 03/24/2004
-- ~~~~~~
-- - Added 5 functions
-- ^^^^^^
--
-- ALS 09/03/04
-- ^^^^^^
-- -- Added constants to describe the channel protocols used in MCH_OPB_IPIF
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Changed proc_common library version to v3_00_a
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- need conversion function to convert reals/integers to std logic vectors
use ieee.std_logic_arith.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
package cpu_xadc_wiz_0_0_ipif_pkg is
-------------------------------------------------------------------------------
-- Type Declarations
-------------------------------------------------------------------------------
type SLV32_ARRAY_TYPE is array (natural range <>) of std_logic_vector(0 to 31);
subtype SLV64_TYPE is std_logic_vector(0 to 63);
type SLV64_ARRAY_TYPE is array (natural range <>) of SLV64_TYPE;
type INTEGER_ARRAY_TYPE is array (natural range <>) of integer;
-------------------------------------------------------------------------------
-- Function and Procedure Declarations
-------------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean;
function equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN;
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer;
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer;
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer;
function S32 (in_string : string) return string;
--------------------------------------------------------------------------------
-- ARD support functions.
-- These function can be useful when operating with the ARD parameterization.
--------------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer)
return integer;
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean;
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer)
return integer;
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE) return integer;
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer ;
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE;
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE;
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE;
-- 5 Functions Added 3/24/04
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE ;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Channel Protocols
-- The constant declarations below give symbolic-name aliases for values that
-- can be used in the C_MCH_PROTOCOL_ARRAY generic of the MCH_OPB_IPIF.
-------------------------------------------------------------------------------
constant XCL : integer := 0;
constant DAG : integer := 1;
--------------------------------------------------------------------------------
-- Address range types.
-- The constant declarations, below, give symbolic-name aliases for values
-- that can be used in the C_ARD_ID_ARRAY generic of IPIFs. The first set
-- gives aliases that are used to include IPIF services.
--------------------------------------------------------------------------------
-- IPIF module aliases
Constant IPIF_INTR : integer := 1;
Constant IPIF_RST : integer := 2;
Constant IPIF_SESR_SEAR : integer := 3;
Constant IPIF_DMA_SG : integer := 4;
Constant IPIF_WRFIFO_REG : integer := 5;
Constant IPIF_WRFIFO_DATA : integer := 6;
Constant IPIF_RDFIFO_REG : integer := 7;
Constant IPIF_RDFIFO_DATA : integer := 8;
Constant IPIF_CHDMA_CHANNELS : integer := 9;
Constant IPIF_CHDMA_GLOBAL_REGS : integer := 10;
Constant CHDMA_STATUS_FIFO : integer := 90;
-- Some predefined user module aliases
Constant USER_00 : integer := 100;
Constant USER_01 : integer := 101;
Constant USER_02 : integer := 102;
Constant USER_03 : integer := 103;
Constant USER_04 : integer := 104;
Constant USER_05 : integer := 105;
Constant USER_06 : integer := 106;
Constant USER_07 : integer := 107;
Constant USER_08 : integer := 108;
Constant USER_09 : integer := 109;
Constant USER_10 : integer := 110;
Constant USER_11 : integer := 111;
Constant USER_12 : integer := 112;
Constant USER_13 : integer := 113;
Constant USER_14 : integer := 114;
Constant USER_15 : integer := 115;
Constant USER_16 : integer := 116;
---( Start of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Dependent Properties (properties that depend on the type of
-- the address range, or in other words, address-range-specific parameters).
-- There is one property, i.e. one parameter, encoded as an integer at
-- each index of the properties array. There is one properties array for
-- each address range.
--
-- The C_ARD_DEPENDENT_PROPS_ARRAY generic parameter in (most) IPIFs is such
-- a properties array and it is usually giving its (static) value using a
-- VHDL aggregate construct. (--ToDo, give an example of this.)
--
-- The the "assigned" default value of a dependent property is zero. This value
-- is usually specified the aggregate by leaving its (index) name out so that
-- it is covered by an "others => 0" choice in the aggregate. Some parameters,
-- as noted in the definitions, below, have an "effective" default value that is
-- different from the assigned default value of zero. In such cases, the
-- function, eff_dp, given below, can be used to get the effective value of
-- the dependent property.
--------------------------------------------------------------------------------
constant DEPENDENT_PROPS_SIZE : integer := 32;
subtype DEPENDENT_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to DEPENDENT_PROPS_SIZE-1);
type DEPENDENT_PROPS_ARRAY_TYPE
is array (natural range <>) of DEPENDENT_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of dependent properties for the different types of
-- address ranges.
--
-- Example: Let C_ARD_DEPENDENT_PROPS_ARRAY hold the dependent properites
-- for a set of address ranges. Then, e.g.,
--
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(FIFO_CAPACITY_BITS)
--
-- gives the fifo capacity in bits, provided that the i'th address range
-- is of type IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals. (The right to change numerical index assignments
-- is reserved; applications using the names will not be affected by such
-- reassignments.)
--------------------------------------------------------------------------------
--
--ToDo, if the interrupt controller parameterization is ever moved to
-- C_ARD_DEPENDENT_PROPS_ARRAY, then the following declarations
-- could be uncommented and used.
---- IPIF_INTR IDX
---------------------------------------------------------------------------- ---
constant EXCLUDE_DEV_ISC : integer := 0;
-- 1 specifies that only the global interrupt
-- enable is present in the device interrupt source
-- controller and that the only source of interrupts
-- in the device is the IP interrupt source controller.
-- 0 specifies that the full device interrupt
-- source controller structure will be included.
constant INCLUDE_DEV_PENCODER : integer := 1;
-- 1 will include the Device IID in the device interrupt
-- source controller, 0 will exclude it.
--
-- IPIF_WRFIFO_DATA or IPIF_RDFIFO_DATA IDX
---------------------------------------------------------------------------- ---
constant FIFO_CAPACITY_BITS : integer := 0;
constant WR_WIDTH_BITS : integer := 1;
constant RD_WIDTH_BITS : integer := 2;
constant EXCLUDE_PACKET_MODE : integer := 3;
-- 1 Don't include packet mode features
-- 0 Include packet mode features
constant EXCLUDE_VACANCY : integer := 4;
-- 1 Don't include vacancy calculation
-- 0 Include vacancy calculation
-- See also the functions
-- bits_needed_for_vac and
-- bits_needed_for_occ that are declared below.
constant INCLUDE_DRE : integer := 5;
constant INCLUDE_AUTOPUSH_POP : integer := 6;
constant AUTOPUSH_POP_CE : integer := 7;
constant INCLUDE_CSUM : integer := 8;
--------------------------------------------------------------------------------
--
-- DMA_SG IDX
---------------------------------------------------------------------------- ---
--------------------------------------------------------------------------------
-- IPIF_CHDMA_CHANNELS IDX
---------------------------------------------------------------------------- ---
constant NUM_SUBS_FOR_PHYS_0 : integer :=0;
constant NUM_SUBS_FOR_PHYS_1 : integer :=1;
constant NUM_SUBS_FOR_PHYS_2 : integer :=2;
constant NUM_SUBS_FOR_PHYS_3 : integer :=3;
constant NUM_SUBS_FOR_PHYS_4 : integer :=4;
constant NUM_SUBS_FOR_PHYS_5 : integer :=5;
constant NUM_SUBS_FOR_PHYS_6 : integer :=6;
constant NUM_SUBS_FOR_PHYS_7 : integer :=7;
constant NUM_SUBS_FOR_PHYS_8 : integer :=8;
constant NUM_SUBS_FOR_PHYS_9 : integer :=9;
constant NUM_SUBS_FOR_PHYS_10 : integer :=10;
constant NUM_SUBS_FOR_PHYS_11 : integer :=11;
constant NUM_SUBS_FOR_PHYS_12 : integer :=12;
constant NUM_SUBS_FOR_PHYS_13 : integer :=13;
constant NUM_SUBS_FOR_PHYS_14 : integer :=14;
constant NUM_SUBS_FOR_PHYS_15 : integer :=15;
-- Gives the number of sub-channels for physical channel i.
--
-- These constants, which will be MAX_NUM_PHYS_CHANNELS in number (see
-- below), have consecutive values starting with 0 for
-- NUM_SUBS_FOR_PHYS_0. (The constants serve the purpose of giving symbolic
-- names for use in the dependent-properties aggregates that parameterize
-- an IPIF_CHDMA_CHANNELS address range.)
--
-- [Users can ignore this note for developers
-- If the number of physical channels changes, both the
-- IPIF_CHDMA_CHANNELS constants and MAX_NUM_PHYS_CHANNELS,
-- below, must be adjusted.
-- (Use of an array constant or a function of the form
-- NUM_SUBS_FOR_PHYS(i) to define the indices
-- runs afoul of LRM restrictions on non-locally static aggregate
-- choices. (Further, the LRM imposes perhaps unnecessarily
-- strict limits on what qualifies as a locally static primary.)
-- Note: This information is supplied for the benefit of anyone seeking
-- to improve the way that these NUM_SUBS_FOR_PHYS parameter
-- indices are defined.)
-- End of note for developers ]
--
-- The value associated with any index NUM_SUBS_FOR_PHYS_i in the
-- dependent-properties array must be even since TX and RX channels
-- come in pairs with the TX followed immediately by
-- the corresponding RX.
--
constant NUM_SIMPLE_DMA_CHANS : integer :=16;
-- The number of simple DMA channels.
constant NUM_SIMPLE_SG_CHANS : integer :=17;
-- The number of simple SG channels.
constant INTR_COALESCE : integer :=18;
-- 0 Interrupt coalescing is disabled
-- 1 Interrupt coalescing is enabled
constant CLK_PERIOD_PS : integer :=19;
-- The period of the OPB Bus clock in ps.
-- The default value of 0 is a special value that
-- is synonymous with 10000 ps (10 ns).
-- The value for CLK_PERIOD_PS is relevant only if (INTR_COALESCE = 1).
constant PACKET_WAIT_UNIT_NS : integer :=20;
-- Gives the unit for used for timing of pack-wait bounds.
-- The default value of 0 is a special value that
-- is synonymous with 1,000,000 ns (1 ms) and a non-default
-- value is typically only used for testing.
-- Relevant only if (INTR_COALESCE = 1).
constant BURST_SIZE : integer :=21;
-- 1, 2, 4, 8 or 16
-- The default value of 0 is a special value that
-- is synonymous with a burst size of 16.
-- Setting the BURST_SIZE to 1 effectively disables
-- bursts.
constant REMAINDER_AS_SINGLES : integer :=22;
-- 0 Remainder handled as a short burst
-- 1 Remainder handled as a series of singles
--------------------------------------------------------------------------------
-- The constant below is not the index of a dependent-properties
-- parameter (and, as such, would never appear as a choice in a
-- dependent-properties aggregate). Rather, it is fixed to the maximum
-- number of physical channels that an Address Range of type
-- IPIF_CHDMA_CHANNELS supports. It must be maintained in conjuction with
-- the constants named, e.g., NUM_SUBS_FOR_PHYS_15, above.
--------------------------------------------------------------------------------
constant MAX_NUM_PHYS_CHANNELS : natural := 16;
--------------------------------------------------------------------------
-- EXAMPLE: Here is an example dependent-properties aggregate for an
-- address range of type IPIF_CHDMA_CHANNELS.
-- To have a compact list of all of the CHDMA parameters, all are
-- shown, however three are commented out and the unneeded
-- MUM_SUBS_FOR_PHYS_x are excluded. The "OTHERS => 0" association
-- gives these parameters their default values, such that, for the example
--
-- - All physical channels above 2 have zero subchannels (effectively,
-- these physical channels are not used)
-- - There are no simple SG channels
-- - The packet-wait time unit is 1 ms
-- - Burst size is 16
--------------------------------------------------------------------------
-- (
-- NUM_SUBS_FOR_PHYS_0 => 8,
-- NUM_SUBS_FOR_PHYS_1 => 4,
-- NUM_SUBS_FOR_PHYS_2 => 14,
-- NUM_SIMPLE_DMA_CHANS => 1,
-- --NUM_SIMPLE_SG_CHANS => 5,
-- INTR_COALESCE => 1,
-- CLK_PERIOD_PS => 20000,
-- --PACKET_WAIT_UNIT_NS => 50000,
-- --BURST_SIZE => 1,
-- REMAINDER_AS_SINGLES => 1,
-- OTHERS => 0
-- )
--
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the vacancy (emptiness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Calculates the number of bits needed to convey the occupancy (fullness) of
-- the fifo described by dependent_props, if fifo_present. If not fifo_present,
-- returns 0 (or the smallest value allowed by tool limitations on null arrays)
-- without making reference to dependent_props.
--------------------------------------------------------------------------------
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer;
--------------------------------------------------------------------------------
-- Function eff_dp.
--
-- For some of the dependent properties, the default value of zero is meant
-- to imply an effective default value of other than zero (see e.g.
-- PKT_WAIT_UNIT_NS for the IPIF_CHDMA_CHANNELS address-range type). The
-- following function is used to get the (possibly default-adjusted)
-- value for a dependent property.
--
-- Example call:
--
-- eff_value_of_param :=
-- eff_dp(
-- C_IPIF_CHDMA_CHANNELS,
-- PACKET_WAIT_UNIT_NS,
-- C_ARD_DEPENDENT_PROPS_ARRAY(i)(PACKET_WAIT_UNIT_NS)
-- );
--
-- where C_ARD_DEPENDENT_PROPS_ARRAY(i) is an object of type
-- DEPENDENT_PROPS_ARRAY_TYPE, that was parameterized for an address range of
-- type C_IPIF_CHDMA_CHANNELS.
--------------------------------------------------------------------------------
function eff_dp(id : integer; -- The type of address range.
dep_prop : integer; -- The index of the dependent prop.
value : integer -- The value at that index.
) return integer; -- The effective value, possibly adjusted
-- if value has the default value of 0.
---) End of Dependent Properties declarations
--------------------------------------------------------------------------------
-- Declarations for Common Properties (properties that apply regardless of the
-- type of the address range). Structurally, these work the same as
-- the dependent properties.
--------------------------------------------------------------------------------
constant COMMON_PROPS_SIZE : integer := 2;
subtype COMMON_PROPS_TYPE
is INTEGER_ARRAY_TYPE(0 to COMMON_PROPS_SIZE-1);
type COMMON_PROPS_ARRAY_TYPE
is array (natural range <>) of COMMON_PROPS_TYPE;
--------------------------------------------------------------------------------
-- Below are the indices of the common properties.
--
-- These indices should be referenced only by the names below and never
-- by numerical literals.
-- IDX
---------------------------------------------------------------------------- ---
constant KEYHOLE_BURST : integer := 0;
-- 1 All addresses of a burst are forced to the initial
-- address of the burst.
-- 0 Burst addresses follow the bus protocol.
-- IP interrupt mode array constants
Constant INTR_PASS_THRU : integer := 1;
Constant INTR_PASS_THRU_INV : integer := 2;
Constant INTR_REG_EVENT : integer := 3;
Constant INTR_REG_EVENT_INV : integer := 4;
Constant INTR_POS_EDGE_DETECT : integer := 5;
Constant INTR_NEG_EDGE_DETECT : integer := 6;
end cpu_xadc_wiz_0_0_ipif_pkg;
library work;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.log2;
package body cpu_xadc_wiz_0_0_ipif_pkg is
-------------------------------------------------------------------------------
-- Function Definitions
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function "="
--
-- This function can be used to overload the "=" operator when comparing
-- strings.
-----------------------------------------------------------------------------
function "=" (s1: in string; s2: in string) return boolean is
constant tc: character := ' '; -- string termination character
variable i: integer := 1;
variable v1 : string(1 to s1'length) := s1;
variable v2 : string(1 to s2'length) := s2;
begin
while (i <= v1'length) and (v1(i) /= tc) and
(i <= v2'length) and (v2(i) /= tc) and
(v1(i) = v2(i))
loop
i := i+1;
end loop;
return ((i > v1'length) or (v1(i) = tc)) and
((i > v2'length) or (v2(i) = tc));
end;
----------------------------------------------------------------------------
-- Function equaluseCase
--
-- This function returns true if case sensitive string comparison determines
-- that str1 and str2 are the same.
-----------------------------------------------------------------------------
FUNCTION equaluseCase( str1, str2 : STRING ) RETURN BOOLEAN IS
CONSTANT len1 : INTEGER := str1'length;
CONSTANT len2 : INTEGER := str2'length;
VARIABLE equal : BOOLEAN := TRUE;
BEGIN
IF NOT (len1=len2) THEN
equal := FALSE;
ELSE
FOR i IN str1'range LOOP
IF NOT (str1(i) = str2(i)) THEN
equal := FALSE;
END IF;
END LOOP;
END IF;
RETURN equal;
END equaluseCase;
-----------------------------------------------------------------------------
-- Function calc_num_ce
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The array is input to
-- the function and an integer is returned reflecting the total number of
-- Chip Enables required for the CE, RdCE, and WrCE Buses
-----------------------------------------------------------------------------
function calc_num_ce (ce_num_array : INTEGER_ARRAY_TYPE) return integer is
Variable ce_num_sum : integer := 0;
begin
for i in 0 to (ce_num_array'length)-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
return(ce_num_sum);
end function calc_num_ce;
-----------------------------------------------------------------------------
-- Function calc_start_ce_index
--
-- This function is used to process the array specifying the number of Chip
-- Enables required for a Base Address specification. The CE Size array is
-- input to the function and an integer index representing the index of the
-- target module in the ce_num_array. An integer is returned reflecting the
-- starting index of the assigned Chip Enables within the CE, RdCE, and
-- WrCE Buses.
-----------------------------------------------------------------------------
function calc_start_ce_index (ce_num_array : INTEGER_ARRAY_TYPE;
index : integer) return integer is
Variable ce_num_sum : integer := 0;
begin
If (index = 0) Then
ce_num_sum := 0;
else
for i in 0 to index-1 loop
ce_num_sum := ce_num_sum + ce_num_array(i);
End loop;
End if;
return(ce_num_sum);
end function calc_start_ce_index;
-----------------------------------------------------------------------------
-- Function get_min_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the smallest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_min_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_min : Integer := 1024;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) < temp_min) Then
temp_min := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_min);
end function get_min_dwidth;
-----------------------------------------------------------------------------
-- Function get_max_dwidth
--
-- This function is used to process the array specifying the data bus width
-- for each of the target modules. The dwidth_array is input to the function
-- and an integer is returned that is the largest value found of all the
-- entries in the array.
-----------------------------------------------------------------------------
function get_max_dwidth (dwidth_array: INTEGER_ARRAY_TYPE) return integer is
Variable temp_max : Integer := 0;
begin
for i in 0 to dwidth_array'length-1 loop
If (dwidth_array(i) > temp_max) Then
temp_max := dwidth_array(i);
else
null;
End if;
End loop;
return(temp_max);
end function get_max_dwidth;
-----------------------------------------------------------------------------
-- Function S32
--
-- This function is used to expand an input string to 32 characters by
-- padding with spaces. If the input string is larger than 32 characters,
-- it will truncate to 32 characters.
-----------------------------------------------------------------------------
function S32 (in_string : string) return string is
constant OUTPUT_STRING_LENGTH : integer := 32;
Constant space : character := ' ';
variable new_string : string(1 to 32);
Variable start_index : Integer := in_string'length+1;
begin
If (in_string'length < OUTPUT_STRING_LENGTH) Then
for i in 1 to in_string'length loop
new_string(i) := in_string(i);
End loop;
for j in start_index to OUTPUT_STRING_LENGTH loop
new_string(j) := space;
End loop;
else -- use first 32 chars of in_string (truncate the rest)
for k in 1 to OUTPUT_STRING_LENGTH loop
new_string(k) := in_string(k);
End loop;
End if;
return(new_string);
end function S32;
-----------------------------------------------------------------------------
-- Function get_id_index
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- id number is input to the function. A integer is returned reflecting the
-- array index of the id matching the id input number. This function
-- should only be called if the id number is known to exist in the
-- name_array input. This can be detirmined by using the find_ard_id
-- function.
-----------------------------------------------------------------------------
function get_id_index (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := 10000; -- a really big number!
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then
match_index := array_index;
else
null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index;
--------------------------------------------------------------------------------
-- get_id_index but return a value in bounds on error (iboe).
--
-- This function is the same as get_id_index, except that when id does
-- not exist in id_array, the value returned is any index that is
-- within the index range of id_array.
--
-- This function would normally only be used where function find_ard_id
-- is used to establish the existence of id but, even when non-existent,
-- an element of one of the ARD arrays will be computed from the
-- returned get_id_index_iboe value. See, e.g., function bits_needed_for_vac
-- and the example call, below
--
-- bits_needed_for_vac(
-- find_ard_id(C_ARD_ID_ARRAY, IPIF_RDFIFO_DATA),
-- C_ARD_DEPENDENT_PROPS_ARRAY(get_id_index_iboe(C_ARD_ID_ARRAY,
-- IPIF_RDFIFO_DATA))
-- )
--------------------------------------------------------------------------------
function get_id_index_iboe (id_array :INTEGER_ARRAY_TYPE;
id : integer) return integer is
Variable match : Boolean := false;
Variable match_index : Integer := id_array'left; -- any valid array index
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
If (match) Then match_index := array_index;
else null;
End if;
End if;
End loop;
return(match_index);
end function get_id_index_iboe;
-----------------------------------------------------------------------------
-- Function find_ard_id
--
-- This function is used to process the array specifying the target function
-- assigned to a Base Address pair address range. The id_array and a
-- integer id is input to the function. A boolean is returned reflecting the
-- presence (or not) of a number in the array matching the id input number.
-----------------------------------------------------------------------------
function find_ard_id (id_array : INTEGER_ARRAY_TYPE;
id : integer) return boolean is
Variable match : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
If (match = true) Then -- match already found so do nothing
null;
else -- compare the numbers one by one
match := (id_array(array_index) = id);
End if;
End loop;
return(match);
end function find_ard_id;
-----------------------------------------------------------------------------
-- Function find_id_dwidth
--
-- This function is used to find the data width of a target module. If the
-- target module exists, the data width is extracted from the input dwidth
-- array. If the module is not in the ID array, the default input is
-- returned. This function is needed to assign data port size constraints on
-- unconstrained port widths.
-----------------------------------------------------------------------------
function find_id_dwidth (id_array : INTEGER_ARRAY_TYPE;
dwidth_array: INTEGER_ARRAY_TYPE;
id : integer;
default : integer) return integer is
Variable id_present : Boolean := false;
Variable array_index : Integer := 0;
Variable dwidth : Integer := default;
begin
id_present := find_ard_id(id_array, id);
If (id_present) Then
array_index := get_id_index (id_array, id);
dwidth := dwidth_array(array_index);
else
null; -- use default input
End if;
Return (dwidth);
end function find_id_dwidth;
-----------------------------------------------------------------------------
-- Function cnt_ipif_id_blks
--
-- This function is used to detirmine the number of IPIF components specified
-- in the ARD ID Array. An integer is returned representing the number
-- of elements counted. User IDs are ignored in the counting process.
-----------------------------------------------------------------------------
function cnt_ipif_id_blks (id_array : INTEGER_ARRAY_TYPE)
return integer is
Variable blk_count : integer := 0;
Variable temp_id : integer;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_count := blk_count+1;
else -- go to next loop iteration
null;
End if;
End loop;
return(blk_count);
end function cnt_ipif_id_blks;
-----------------------------------------------------------------------------
-- Function get_ipif_id_dbus_index
--
-- This function is used to detirmine the IPIF relative index of a given
-- ID value. User IDs are ignored in the index detirmination.
-----------------------------------------------------------------------------
function get_ipif_id_dbus_index (id_array : INTEGER_ARRAY_TYPE;
id : integer)
return integer is
Variable blk_index : integer := 0;
Variable temp_id : integer;
Variable id_found : Boolean := false;
begin
for array_index in 0 to id_array'length-1 loop
temp_id := id_array(array_index);
If (id_found) then
null;
elsif (temp_id = id) then
id_found := true;
elsif (temp_id = IPIF_WRFIFO_DATA or
temp_id = IPIF_RDFIFO_DATA or
temp_id = IPIF_RST or
temp_id = IPIF_INTR or
temp_id = IPIF_DMA_SG or
temp_id = IPIF_SESR_SEAR
) Then -- IPIF block found
blk_index := blk_index+1;
else -- user block so do nothing
null;
End if;
End loop;
return(blk_index);
end function get_ipif_id_dbus_index;
------------------------------------------------------------------------------
-- Function: rebuild_slv32_array
--
-- Description:
-- This function takes an input slv32 array and rebuilds an output slv32
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv32_array (slv32_array : SLV32_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV32_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr32_array : SLV32_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr32_array(array_index) := slv32_array(array_index);
end loop;
return(temp_baseaddr32_array);
end function rebuild_slv32_array;
------------------------------------------------------------------------------
-- Function: rebuild_slv64_array
--
-- Description:
-- This function takes an input slv64 array and rebuilds an output slv64
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_slv64_array (slv64_array : SLV64_ARRAY_TYPE;
num_valid_pairs : integer)
return SLV64_ARRAY_TYPE is
--Constants
constant num_elements : Integer := num_valid_pairs * 2;
-- Variables
variable temp_baseaddr64_array : SLV64_ARRAY_TYPE( 0 to num_elements-1);
begin
for array_index in 0 to num_elements-1 loop
temp_baseaddr64_array(array_index) := slv64_array(array_index);
end loop;
return(temp_baseaddr64_array);
end function rebuild_slv64_array;
------------------------------------------------------------------------------
-- Function: rebuild_int_array
--
-- Description:
-- This function takes an input integer array and rebuilds an output integer
-- array composed of the first "num_valid_entry" elements from the input
-- array.
------------------------------------------------------------------------------
function rebuild_int_array (int_array : INTEGER_ARRAY_TYPE;
num_valid_entry : integer)
return INTEGER_ARRAY_TYPE is
-- Variables
variable temp_int_array : INTEGER_ARRAY_TYPE( 0 to num_valid_entry-1);
begin
for array_index in 0 to num_valid_entry-1 loop
temp_int_array(array_index) := int_array(array_index);
end loop;
return(temp_int_array);
end function rebuild_int_array;
function bits_needed_for_vac(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(RD_WIDTH_BITS)
);
end if;
end function bits_needed_for_vac;
function bits_needed_for_occ(
fifo_present: boolean;
dependent_props : DEPENDENT_PROPS_TYPE
) return integer is
begin
if not fifo_present then
return 1; -- Zero would be better but leads to "0 to -1" null
-- ranges that are not handled by XST Flint or earlier
-- because of the negative index.
else
return
log2(1 + dependent_props(FIFO_CAPACITY_BITS) /
dependent_props(WR_WIDTH_BITS)
);
end if;
end function bits_needed_for_occ;
function eff_dp(id : integer;
dep_prop : integer;
value : integer) return integer is
variable dp : integer := dep_prop;
type bo2na_type is array (boolean) of natural;
constant bo2na : bo2na_type := (0, 1);
begin
if value /= 0 then return value; end if; -- Not default
case id is
when IPIF_CHDMA_CHANNELS =>
-------------------
return( bo2na(dp = CLK_PERIOD_PS ) * 10000
+ bo2na(dp = PACKET_WAIT_UNIT_NS ) * 1000000
+ bo2na(dp = BURST_SIZE ) * 16
);
when others => return 0;
end case;
end eff_dp;
function populate_intr_mode_array (num_user_intr : integer;
intr_capture_mode : integer)
return INTEGER_ARRAY_TYPE is
variable intr_mode_array : INTEGER_ARRAY_TYPE(0 to num_user_intr-1);
begin
for i in 0 to num_user_intr-1 loop
intr_mode_array(i) := intr_capture_mode;
end loop;
return intr_mode_array;
end function populate_intr_mode_array;
function add_intr_ard_id_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_id_array : INTEGER_ARRAY_TYPE(0 to ard_id_array'length);
begin
intr_ard_id_array(0 to ard_id_array'length-1) := ard_id_array;
if include_intr then
intr_ard_id_array(ard_id_array'length) := IPIF_INTR;
return intr_ard_id_array;
else
return ard_id_array;
end if;
end function add_intr_ard_id_array;
function add_intr_ard_addr_range_array(include_intr : boolean;
ZERO_ADDR_PAD : std_logic_vector;
intr_baseaddr : std_logic_vector;
intr_highaddr : std_logic_vector;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_addr_range_array : SLV64_ARRAY_TYPE)
return SLV64_ARRAY_TYPE is
variable intr_ard_addr_range_array : SLV64_ARRAY_TYPE(0 to ard_addr_range_array'length+1);
begin
intr_ard_addr_range_array(0 to ard_addr_range_array'length-1) := ard_addr_range_array;
if include_intr then
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR))
:= ZERO_ADDR_PAD & intr_baseaddr;
intr_ard_addr_range_array(2*get_id_index(ard_id_array,IPIF_INTR)+1)
:= ZERO_ADDR_PAD & intr_highaddr;
return intr_ard_addr_range_array;
else
return ard_addr_range_array;
end if;
end function add_intr_ard_addr_range_array;
function add_intr_ard_dwidth_array(include_intr : boolean;
intr_dwidth : integer;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_dwidth_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_dwidth_array : INTEGER_ARRAY_TYPE(0 to ard_dwidth_array'length);
begin
intr_ard_dwidth_array(0 to ard_dwidth_array'length-1) := ard_dwidth_array;
if include_intr then
intr_ard_dwidth_array(get_id_index(ard_id_array, IPIF_INTR)) := intr_dwidth;
return intr_ard_dwidth_array;
else
return ard_dwidth_array;
end if;
end function add_intr_ard_dwidth_array;
function add_intr_ard_num_ce_array(include_intr : boolean;
ard_id_array : INTEGER_ARRAY_TYPE;
ard_num_ce_array : INTEGER_ARRAY_TYPE)
return INTEGER_ARRAY_TYPE is
variable intr_ard_num_ce_array : INTEGER_ARRAY_TYPE(0 to ard_num_ce_array'length);
begin
intr_ard_num_ce_array(0 to ard_num_ce_array'length-1) := ard_num_ce_array;
if include_intr then
intr_ard_num_ce_array(get_id_index(ard_id_array, IPIF_INTR)) := 16;
return intr_ard_num_ce_array;
else
return ard_num_ce_array;
end if;
end function add_intr_ard_num_ce_array;
end package body cpu_xadc_wiz_0_0_ipif_pkg;
| gpl-3.0 | b2d2ef1805baa15f4bd83bd8a781f444 | 0.49084 | 4.843433 | false | false | false | false |
peteut/nvc | test/regress/ieee4.vhd | 2 | 2,314 | entity ieee4 is
end entity;
library ieee;
use ieee.math_real.all;
architecture test of ieee4 is
function approx(x, y : real; t : real := 0.001) return boolean is
begin
return abs(x - y) < t;
end function;
begin
process is
variable s1, s2 : integer;
variable r : real;
begin
r := 6.8;
wait for 0 ns; -- Prevent constant folding
assert approx(sign(r), 1.0);
r := 5.7;
wait for 0 ns;
assert approx(ceil(r), 6.0);
r := 0.6;
wait for 0 ns;
assert approx(floor(r), 0.0);
r := 0.5;
wait for 0 ns;
assert approx(round(r), 1.0);
r := 6.4999;
wait for 0 ns;
assert approx(round(r), 6.0);
r := 0.999;
wait for 0 ns;
assert approx(trunc(r), 0.0);
r := 4.6;
wait for 0 ns;
assert approx(r mod 2.7, 1.9);
s1 := 6;
s2 := 883;
uniform(s1, s2, r);
assert approx(r, 0.983380);
uniform(s1, s2, r);
assert approx(r, 0.627369);
uniform(s1, s2, r);
assert approx(r, 0.883711);
uniform(s1, s2, r);
assert approx(r, 0.472620);
uniform(s1, s2, r);
assert approx(r, 0.582179);
r := 4.0;
wait for 0 ns;
assert approx(sqrt(r), 2.0);
r := 4.3;
wait for 0 ns;
assert approx(sqrt(r), 2.0736);
r := 612.8;
wait for 0 ns;
assert approx(cbrt(r), 8.49388);
r := 1.2;
wait for 0 ns;
assert approx(5 ** r, 6.8986);
r := 2.0;
wait for 0 ns;
assert approx(r ** (-1.0), 0.5);
r := 2.0;
wait for 0 ns;
assert approx(exp(r), 7.389056);
r := 1.0;
wait for 0 ns;
assert approx(log(r), 0.0);
r := MATH_E;
wait for 0 ns;
assert approx(log(r), 1.0);
r := 5216.72;
wait for 0 ns;
assert approx(log(r), 8.5596);
r := MATH_PI;
wait for 0 ns;
assert approx(sin(r), 0.0);
r := 1.15251;
wait for 0 ns;
assert approx(cos(r), 0.406195);
r := 0.5;
wait for 0 ns;
assert approx(arctan(r), 0.463648);
wait;
end process;
end architecture;
| gpl-3.0 | b400b38efa62630aef9a0fbb5c8461d0 | 0.463267 | 3.204986 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weights/example_design/weights_prod.vhd | 1 | 10,065 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: weights_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : artix7
-- C_XDEVICEFAMILY : artix7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : weights.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 24
-- C_READ_WIDTH_A : 24
-- C_WRITE_DEPTH_A : 24
-- C_READ_DEPTH_A : 24
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 24
-- C_READ_WIDTH_B : 24
-- C_WRITE_DEPTH_B : 24
-- C_READ_DEPTH_B : 24
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY weights_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END weights_prod;
ARCHITECTURE xilinx OF weights_prod IS
COMPONENT weights_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : weights_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| bsd-2-clause | 26e82513b2c1877f9f78bf897ed9702e | 0.492598 | 3.840137 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/mul_hid.vhd | 1 | 4,225 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file mul_hid.vhd when simulating
-- the core, mul_hid. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY mul_hid IS
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sclr : IN STD_LOGIC;
bypass : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END mul_hid;
ARCHITECTURE mul_hid_a OF mul_hid IS
-- synthesis translate_off
COMPONENT wrapped_mul_hid
PORT (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
sclr : IN STD_LOGIC;
bypass : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_mul_hid USE ENTITY XilinxCoreLib.xbip_multaccum_v2_0(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 8,
c_accum_mode => 0,
c_accum_width => 16,
c_b_type => 0,
c_b_width => 8,
c_bypass_low => 0,
c_ce_overrides_sclr => 0,
c_has_bypass => 1,
c_latency => 1,
c_out_width => 16,
c_round_type => 0,
c_use_dsp48 => 1,
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_mul_hid
PORT MAP (
clk => clk,
ce => ce,
sclr => sclr,
bypass => bypass,
a => a,
b => b,
s => s
);
-- synthesis translate_on
END mul_hid_a;
| bsd-2-clause | f8b63980c1aa7443083da1abfd53e274 | 0.535858 | 4.567568 | false | false | false | false |
esar/hdmilight-v1 | fpga/resultDistributor.vhd | 2 | 2,421 | ----------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Stephen Robinson
--
-- This file is part of HDMI-Light
--
-- HDMI-Light is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 2 of the License, or
-- (at your option) any later version.
--
-- HDMI-Light is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file names COPING).
-- If not, see <http://www.gnu.org/licenses/>.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity resultDistributor is
Port ( clk : in STD_LOGIC;
vblank : in STD_LOGIC;
resultAddr : out STD_LOGIC_VECTOR (8 downto 0);
resultData : in STD_LOGIC_VECTOR (31 downto 0);
busy : in STD_LOGIC;
outputReady : out STD_LOGIC;
outputAddr : out STD_LOGIC_VECTOR (7 downto 0);
outputData : out STD_LOGIC_VECTOR (23 downto 0));
end resultDistributor;
architecture Behavioral of resultDistributor is
signal lastbusy : std_logic;
signal lastvblank : std_logic;
signal count : std_logic_vector(7 downto 0) := (others => '0');
begin
process(clk)
begin
if(rising_edge(clk)) then
outputReady <= '0';
if(vblank = '1' and lastvblank = '0') then
count <= (others => '0');
outputReady <= '1';
elsif(busy = '0' and lastbusy = '1' and count /= "11111111") then --"11111111") then
count <= std_logic_vector(unsigned(count) + 1);
outputReady <= '1';
end if;
lastbusy <= busy;
lastvblank <= vblank;
end if;
end process;
resultAddr <= "0" & count;
outputAddr <= resultData(31 downto 24);
outputData <= resultData(23 downto 0);
end Behavioral;
| gpl-2.0 | 54bf068d33046090ea4f47ffa3b25f87 | 0.643536 | 3.955882 | false | false | false | false |
ObKo/USBCore | Core/usb_tlp.vhdl | 1 | 15,906 | --
-- USB Full-Speed/Hi-Speed Device Controller core - usb_tlp.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
entity usb_tlp is
generic (
VENDOR_ID : std_logic_vector(15 downto 0) := X"DEAD";
PRODUCT_ID : std_logic_vector(15 downto 0) := X"BEEF";
MANUFACTURER : string := "";
PRODUCT : string := "";
SERIAL : string := "";
CONFIG_DESC : BYTE_ARRAY := (
-- Configuration descriptor
X"09", -- bLength = 9
X"02", -- bDescriptionType = Configuration Descriptor
X"12", X"00", -- wTotalLength = 18
X"01", -- bNumInterfaces = 1
X"01", -- bConfigurationValue
X"00", -- iConfiguration
X"C0", -- bmAttributes = Self-powered
X"32", -- bMaxPower = 100 mA
-- Interface descriptor
X"09", -- bLength = 9
X"04", -- bDescriptorType = Interface Descriptor
X"00", -- bInterfaceNumber = 0
X"00", -- bAlternateSetting
X"00", -- bNumEndpoints = 0
X"00", -- bInterfaceClass
X"00", -- bInterfaceSubClass
X"00", -- bInterfaceProtocol
X"00" -- iInterface
);
HIGH_SPEED : boolean := true
);
port (
ulpi_data_in : in std_logic_vector(7 downto 0);
ulpi_data_out : out std_logic_vector(7 downto 0);
ulpi_dir : in std_logic;
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_reset : out std_logic;
ulpi_clk60 : in std_logic;
usb_clk : out std_logic;
usb_reset : out std_logic;
usb_idle : out std_logic;
usb_suspend : out std_logic;
usb_configured : out std_logic;
usb_crc_error : out std_logic;
-- Pulse when SOF packet received
usb_sof : out std_logic;
-- Control transfer signals
ctl_xfer_endpoint : out std_logic_vector(3 downto 0);
ctl_xfer_type : out std_logic_vector(7 downto 0);
ctl_xfer_request : out std_logic_vector(7 downto 0);
ctl_xfer_value : out std_logic_vector(15 downto 0);
ctl_xfer_index : out std_logic_vector(15 downto 0);
ctl_xfer_length : out std_logic_vector(15 downto 0);
ctl_xfer_accept : in std_logic;
ctl_xfer : out std_logic;
ctl_xfer_done : in std_logic;
ctl_xfer_data_out : out std_logic_vector(7 downto 0);
ctl_xfer_data_out_valid : out std_logic;
ctl_xfer_data_in : in std_logic_vector(7 downto 0);
ctl_xfer_data_in_valid : in std_logic;
ctl_xfer_data_in_last : in std_logic;
ctl_xfer_data_in_ready : out std_logic;
-- Bulk transfer signals
blk_xfer_endpoint : out std_logic_vector(3 downto 0);
blk_in_xfer : out std_logic;
blk_out_xfer : out std_logic;
-- Has complete packet
blk_xfer_in_has_data : in std_logic;
blk_xfer_in_data : in std_logic_vector(7 downto 0);
blk_xfer_in_data_valid : in std_logic;
blk_xfer_in_data_ready : out std_logic;
blk_xfer_in_data_last : in std_logic;
-- Can accept full packet
blk_xfer_out_ready_read : in std_logic;
blk_xfer_out_data : out std_logic_vector(7 downto 0);
blk_xfer_out_data_valid : out std_logic
);
end usb_tlp;
architecture usb_tlp of usb_tlp is
signal axis_rx_tvalid : std_logic;
signal axis_rx_tready : std_logic;
signal axis_rx_tlast : std_logic;
signal axis_rx_tdata : std_logic_vector(7 downto 0);
signal axis_tx_tvalid : std_logic;
signal axis_tx_tready : std_logic;
signal axis_tx_tlast : std_logic;
signal axis_tx_tdata : std_logic_vector(7 downto 0);
signal usb_vbus_valid : std_logic;
signal trn_type : std_logic_vector(1 downto 0);
signal trn_address : std_logic_vector(6 downto 0);
signal trn_endpoint : std_logic_vector(3 downto 0);
signal trn_start : std_logic;
signal rx_trn_data_type : std_logic_vector(1 downto 0);
signal rx_trn_end : std_logic;
signal rx_trn_data : std_logic_vector(7 downto 0);
signal rx_trn_valid : std_logic;
signal rx_trn_hsk_type : std_logic_vector(1 downto 0);
signal rx_trn_hsk_received : std_logic;
signal tx_trn_hsk_type : std_logic_vector(1 downto 0);
signal tx_trn_send_hsk : std_logic;
signal tx_trn_hsk_sended : std_logic;
signal tx_trn_data_type : std_logic_vector(1 downto 0);
signal tx_trn_data_start : std_logic;
signal tx_trn_data : std_logic_vector(7 downto 0);
signal tx_trn_data_valid : std_logic;
signal tx_trn_data_ready : std_logic;
signal tx_trn_data_last : std_logic;
signal ctl_xfer_endpoint_int : std_logic_vector(3 downto 0);
signal ctl_xfer_type_int : std_logic_vector(7 downto 0);
signal ctl_xfer_request_int : std_logic_vector(7 downto 0);
signal ctl_xfer_value_int : std_logic_vector(15 downto 0);
signal ctl_xfer_index_int : std_logic_vector(15 downto 0);
signal ctl_xfer_length_int : std_logic_vector(15 downto 0);
signal ctl_xfer_accept_int : std_logic;
signal ctl_xfer_int : std_logic;
signal ctl_xfer_done_int : std_logic;
signal ctl_xfer_accept_std : std_logic;
signal ctl_xfer_std : std_logic;
signal ctl_xfer_done_std : std_logic;
signal ctl_xfer_data_out_int : std_logic_vector(7 downto 0);
signal ctl_xfer_data_out_valid_int : std_logic;
signal ctl_xfer_data_in_int : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid_int : std_logic;
signal ctl_xfer_data_in_last_int : std_logic;
signal ctl_xfer_data_in_ready_int : std_logic;
signal ctl_xfer_data_in_std : std_logic_vector(7 downto 0);
signal ctl_xfer_data_in_valid_std : std_logic;
signal ctl_xfer_data_in_last_std : std_logic;
signal current_configuration : std_logic_vector(7 downto 0);
signal usb_reset_int : std_logic;
signal usb_crc_error_int : std_logic;
signal standart_request : std_logic;
signal device_address : std_logic_vector(6 downto 0);
begin
ULPI : ulpi_port
generic map (
HIGH_SPEED => HIGH_SPEED
)
port map (
rst => '0',
ulpi_data_in => ulpi_data_in,
ulpi_data_out => ulpi_data_out,
ulpi_dir => ulpi_dir,
ulpi_nxt => ulpi_nxt,
ulpi_stp => ulpi_stp,
ulpi_reset => ulpi_reset,
ulpi_clk => ulpi_clk60,
axis_rx_tvalid => axis_rx_tvalid,
axis_rx_tready => axis_rx_tready,
axis_rx_tlast => axis_rx_tlast,
axis_rx_tdata => axis_rx_tdata,
axis_tx_tvalid => axis_tx_tvalid,
axis_tx_tready => axis_tx_tready,
axis_tx_tlast => axis_tx_tlast,
axis_tx_tdata => axis_tx_tdata,
usb_vbus_valid => usb_vbus_valid,
usb_reset => usb_reset_int,
usb_idle => usb_idle,
usb_suspend => usb_suspend
);
PACKET_CONTROLLER : usb_packet
port map (
rst => usb_reset_int,
clk => ulpi_clk60,
axis_rx_tvalid => axis_rx_tvalid,
axis_rx_tready => axis_rx_tready,
axis_rx_tlast => axis_rx_tlast,
axis_rx_tdata => axis_rx_tdata,
axis_tx_tvalid => axis_tx_tvalid,
axis_tx_tready => axis_tx_tready,
axis_tx_tlast => axis_tx_tlast,
axis_tx_tdata => axis_tx_tdata,
trn_type => trn_type,
trn_address => trn_address,
trn_endpoint => trn_endpoint,
trn_start => trn_start,
rx_trn_data_type => rx_trn_data_type,
rx_trn_end => rx_trn_end,
rx_trn_data => rx_trn_data,
rx_trn_valid => rx_trn_valid,
rx_trn_hsk_type => rx_trn_hsk_type,
rx_trn_hsk_received => rx_trn_hsk_received,
tx_trn_hsk_type => tx_trn_hsk_type,
tx_trn_send_hsk => tx_trn_send_hsk,
tx_trn_hsk_sended => tx_trn_hsk_sended,
tx_trn_data_type => tx_trn_data_type,
tx_trn_data_start => tx_trn_data_start,
tx_trn_data => tx_trn_data,
tx_trn_data_valid => tx_trn_data_valid,
tx_trn_data_ready => tx_trn_data_ready,
tx_trn_data_last => tx_trn_data_last,
start_of_frame => usb_sof,
crc_error => usb_crc_error_int,
device_address => device_address
);
TRANSFER_CONTROLLER : usb_xfer
generic map (
HIGH_SPEED => HIGH_SPEED
)
port map (
rst => usb_reset_int,
clk => ulpi_clk60,
trn_type => trn_type,
trn_address => trn_address,
trn_endpoint => trn_endpoint,
trn_start => trn_start,
rx_trn_data_type => rx_trn_data_type,
rx_trn_end => rx_trn_end,
rx_trn_data => rx_trn_data,
rx_trn_valid => rx_trn_valid,
rx_trn_hsk_type => rx_trn_hsk_type,
rx_trn_hsk_received => rx_trn_hsk_received,
tx_trn_hsk_type => tx_trn_hsk_type,
tx_trn_send_hsk => tx_trn_send_hsk,
tx_trn_hsk_sended => tx_trn_hsk_sended,
tx_trn_data_type => tx_trn_data_type,
tx_trn_data_start => tx_trn_data_start,
tx_trn_data => tx_trn_data,
tx_trn_data_valid => tx_trn_data_valid,
tx_trn_data_ready => tx_trn_data_ready,
tx_trn_data_last => tx_trn_data_last,
crc_error => usb_crc_error_int,
ctl_xfer_endpoint => ctl_xfer_endpoint_int,
ctl_xfer_type => ctl_xfer_type_int,
ctl_xfer_request => ctl_xfer_request_int,
ctl_xfer_value => ctl_xfer_value_int,
ctl_xfer_index => ctl_xfer_index_int,
ctl_xfer_length => ctl_xfer_length_int,
ctl_xfer_accept => ctl_xfer_accept_int,
ctl_xfer => ctl_xfer_int,
ctl_xfer_done => ctl_xfer_done_int,
ctl_xfer_data_out => ctl_xfer_data_out_int,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid_int,
ctl_xfer_data_in => ctl_xfer_data_in_int,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid_int,
ctl_xfer_data_in_last => ctl_xfer_data_in_last_int,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready_int,
blk_xfer_endpoint => blk_xfer_endpoint,
blk_in_xfer => blk_in_xfer,
blk_out_xfer => blk_out_xfer,
blk_xfer_in_has_data => blk_xfer_in_has_data,
blk_xfer_in_data => blk_xfer_in_data,
blk_xfer_in_data_valid => blk_xfer_in_data_valid,
blk_xfer_in_data_ready => blk_xfer_in_data_ready,
blk_xfer_in_data_last => blk_xfer_in_data_last,
blk_xfer_out_ready_read => blk_xfer_out_ready_read,
blk_xfer_out_data => blk_xfer_out_data,
blk_xfer_out_data_valid => blk_xfer_out_data_valid
);
STD_REQ_CONTROLLER : usb_std_request
generic map (
VENDOR_ID => VENDOR_ID,
PRODUCT_ID => PRODUCT_ID,
MANUFACTURER => MANUFACTURER,
PRODUCT => PRODUCT,
SERIAL => SERIAL,
CONFIG_DESC => CONFIG_DESC,
HIGH_SPEED => HIGH_SPEED
)
port map (
rst => usb_reset_int,
clk => ulpi_clk60,
ctl_xfer_endpoint => ctl_xfer_endpoint_int,
ctl_xfer_type => ctl_xfer_type_int,
ctl_xfer_request => ctl_xfer_request_int,
ctl_xfer_value => ctl_xfer_value_int,
ctl_xfer_index => ctl_xfer_index_int,
ctl_xfer_length => ctl_xfer_length_int,
ctl_xfer_accept => ctl_xfer_accept_std,
ctl_xfer => ctl_xfer_int,
ctl_xfer_done => ctl_xfer_done_std,
ctl_xfer_data_out => ctl_xfer_data_out_int,
ctl_xfer_data_out_valid => ctl_xfer_data_out_valid_int,
ctl_xfer_data_in => ctl_xfer_data_in_std,
ctl_xfer_data_in_valid => ctl_xfer_data_in_valid_std,
ctl_xfer_data_in_last => ctl_xfer_data_in_last_std,
ctl_xfer_data_in_ready => ctl_xfer_data_in_ready_int,
device_address => device_address,
current_configuration => current_configuration,
configured => usb_configured,
standart_request => standart_request
);
usb_clk <= ulpi_clk60;
usb_reset <= usb_reset_int;
usb_crc_error <= usb_crc_error_int;
ctl_xfer_endpoint <= ctl_xfer_endpoint_int;
ctl_xfer_type <= ctl_xfer_type_int;
ctl_xfer_request <= ctl_xfer_request_int;
ctl_xfer_value <= ctl_xfer_value_int;
ctl_xfer_index <= ctl_xfer_index_int;
ctl_xfer_length <= ctl_xfer_length_int;
ctl_xfer_accept_int <= ctl_xfer_accept_std when standart_request = '1' else
ctl_xfer_accept;
ctl_xfer <= ctl_xfer_int when standart_request = '0' else
'0';
ctl_xfer_done_int <= ctl_xfer_done_std when standart_request = '1' else
ctl_xfer_done;
ctl_xfer_data_out <= ctl_xfer_data_out_int;
ctl_xfer_data_out_valid <= ctl_xfer_data_out_valid_int when standart_request = '0' else
'0';
ctl_xfer_data_in_int <= ctl_xfer_data_in_std when standart_request = '1' else
ctl_xfer_data_in;
ctl_xfer_data_in_valid_int <= ctl_xfer_data_in_valid_std when standart_request = '1' else
ctl_xfer_data_in_valid;
ctl_xfer_data_in_last_int <= ctl_xfer_data_in_last_std when standart_request = '1' else
ctl_xfer_data_in_last;
ctl_xfer_data_in_ready <= ctl_xfer_data_in_ready_int when standart_request = '0' else
'0';
end usb_tlp;
| mit | 29de1cf7d12ec1ee9cc1577cffc4d9a4 | 0.550107 | 3.400898 | false | false | false | false |
peteut/nvc | test/sem/access.vhd | 1 | 2,613 | package p is
type int_ptr is access integer; -- OK
type bad1 is access foo; -- Error
type rec;
type rec_ptr is access rec;
type rec is record
value : integer;
link : rec_ptr;
end record;
type int_vec is array (integer range <>) of integer;
type int_vec_ptr is access int_vec;
type string_ptr is access string;
end package;
package body p is
procedure test is
variable v : int_ptr;
variable i : integer;
variable r : rec_ptr;
variable a : int_vec_ptr;
variable s : string_ptr;
begin
v := null; -- OK
i := null; -- Error
deallocate(v); -- OK
v := new integer; -- OK
v := new integer'(5); -- OK
v := new 5; -- Error
v := new i; -- Error
v.all := 5; -- OK
v := 5; -- Error
i := v.all + 5; -- OK
r := new rec; -- OK
r.all.value := 1; -- OK
r.value := 1; -- OK
r.link := r; -- OK
r.link := r.all; -- Error
i := r.value; -- OK
r := r.all.link; -- OK
a := new int_vec(1 to 3); -- OK
a.all(5) := 2; -- OK
a(5) := 2; -- OK
a(1 to 2) := (1, 2); -- OK
s := new string'(""); -- OK
s := new integer'(1); -- Error
s := new s(1 to 3); -- Error
end procedure;
procedure test2(x : inout rec_ptr) is
begin
x.value := x.value + 1;
end procedure;
procedure test3 is
type a;
type a is access integer; -- OK
variable v : a; -- OK
begin
end procedure;
type int_ptr_array is array (integer range <>) of int_ptr;
type int_ptr_array_ptr is access int_ptr_array;
procedure alloc_ptr_array(x : out int_ptr_array_ptr) is
begin
x := new int_ptr_array; -- Error
x := new int_ptr_array(1 to 3); -- OK
x.all := (null, null, null); -- OK
end procedure;
procedure tets4 is
type bvp is access bit_vector;
variable x : bvp(1 to 4) := new bit_vector'("1010"); -- OK
variable y : int_ptr(1 to 3) := int_ptr'(null); -- Error
begin
end procedure;
end package body;
| gpl-3.0 | 9d4379051465c6e195a8286cb76ebf03 | 0.414466 | 3.983232 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/ip/ocxo_clk_pll/ocxo_clk_pll_funcsim.vhdl | 1 | 7,823 | -- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
-- Date : Fri May 6 14:51:06 2016
-- Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
-- Command : write_vhdl -force -mode funcsim /home/guest/cae/fpga/ntpserver/ip/ocxo_clk_pll/ocxo_clk_pll_funcsim.vhdl
-- Design : ocxo_clk_pll
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ocxo_clk_pll_ocxo_clk_pll_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ocxo_clk_pll_ocxo_clk_pll_clk_wiz : entity is "ocxo_clk_pll_clk_wiz";
end ocxo_clk_pll_ocxo_clk_pll_clk_wiz;
architecture STRUCTURE of ocxo_clk_pll_ocxo_clk_pll_clk_wiz is
signal RST : STD_LOGIC;
signal clk_in1_ocxo_clk_pll : STD_LOGIC;
signal clkfbout_ocxo_clk_pll : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute box_type : string;
attribute box_type of clkin1_ibufg : label is "PRIMITIVE";
attribute box_type of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_ocxo_clk_pll
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 63.750000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 100.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 6.375000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.000000,
REF_JITTER2 => 0.000000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_ocxo_clk_pll,
CLKFBOUT => clkfbout_ocxo_clk_pll,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_ocxo_clk_pll,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => RST
);
mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => resetn,
O => RST
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ocxo_clk_pll is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ocxo_clk_pll : entity is true;
attribute core_generation_info : string;
attribute core_generation_info of ocxo_clk_pll : entity is "ocxo_clk_pll,clk_wiz_v5_1,{component_name=ocxo_clk_pll,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_ONCHIP,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=100.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end ocxo_clk_pll;
architecture STRUCTURE of ocxo_clk_pll is
begin
U0: entity work.ocxo_clk_pll_ocxo_clk_pll_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked,
resetn => resetn
);
end STRUCTURE;
| gpl-3.0 | 9832e2ad1afbb70403ddeb32fd8bd6d8 | 0.624313 | 3.2009 | false | false | false | false |
tutkowskim/UART | uart_tx.vhd | 1 | 1,221 | library ieee;
use ieee.std_logic_1164.all;
entity UART_TX is
port(
SS : in std_logic;
DA : in std_logic_vector(7 downto 0);
CLK : in std_logic;
RST : in std_logic;
DS : out std_logic;
TX : out std_logic
);
end entity UART_TX;
architecture BEHAVORIAL of UART_TX is
type STATES is (IDLE,START,DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,STOP);
signal Q, D : STATES;
begin
SEND: process(DA,CLK,RST)
begin
if RST = '0' Then
Q <= IDLE;
DS <= '1';
elsif rising_edge(CLK) then
Q <= D;
end if;
case Q is
when IDLE =>
TX <= '1';
if SS = '1' then
D <= START;
else
D <= IDLE;
end if;
when START =>
TX <= '0';
D <= DATA0;
DS <= '0';
when DATA0 =>
TX <= DA(0);
D <= DATA1;
when DATA1 =>
TX <= DA(1);
D <= DATA2;
when DATA2 =>
TX <= DA(2);
D <= DATA3;
when DATA3 =>
TX <= DA(3);
D <= DATA4;
when DATA4 =>
TX <= DA(4);
D <= DATA5;
when DATA5 =>
TX <= DA(5);
D <= DATA6;
when DATA6 =>
TX <= DA(6);
D <= DATA7;
when DATA7 =>
TX <= DA(7);
D <= STOP;
when STOP =>
TX <= '0';
D <= IDLE;
DS <= '1';
end case;
end process;
end architecture BEHAVORIAL;
| mit | 0648e36ba17e5be267a3ec1285e6f003 | 0.51679 | 2.466667 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_prime_fifo_plain/simulation/k7_prime_fifo_plain_dgen.vhd | 1 | 4,581 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_prime_fifo_plain_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_prime_fifo_plain_pkg.ALL;
ENTITY k7_prime_fifo_plain_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF k7_prime_fifo_plain_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 100 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:k7_prime_fifo_plain_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
| gpl-2.0 | 8f2d96db49072cf8ecc721d2652a535a | 0.60227 | 4.179745 | false | false | false | false |
olgirard/openmsp430 | core/synthesis/xilinx/src/coregen/spartan3a_dmem.vhd | 1 | 5,171 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file spartan3a_dmem.vhd when simulating
-- the core, spartan3a_dmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY spartan3a_dmem IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END spartan3a_dmem;
ARCHITECTURE spartan3a_dmem_a OF spartan3a_dmem IS
-- synthesis translate_off
component wrapped_spartan3a_dmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_spartan3a_dmem use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "spartan3",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "spartan3a",
c_write_depth_b => 1024,
c_write_depth_a => 1024,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 10,
c_addrb_width => 10,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 1024,
c_read_depth_a => 1024,
c_byte_size => 8,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 2,
c_has_enb => 0,
c_web_width => 2,
c_has_ena => 1,
c_use_byte_web => 1,
c_use_byte_wea => 1,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_spartan3a_dmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END spartan3a_dmem_a;
| bsd-3-clause | d247328f1623b0b1c42ab1b72e8221a5 | 0.561207 | 3.669979 | false | false | false | false |
UnofficialRepos/OSVVM | ScoreboardPkg_slv_c.vhd | 1 | 137,840 | --
-- File Name: ScoreBoardPkg_slv.vhd
-- Design Unit Name: ScoreBoardPkg_slv
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Removed deprecated SetAlertLogID in Singleton API
-- 02/2022 2022.02 Added WriteScoreboardYaml and GotScoreboards. Updated NewID with ParentID,
-- ReportMode, Search, PrintParent. Supports searching for Scoreboard models..
-- 01/2022 2022.01 Added CheckExpected. Added SetCheckCountZero to ScoreboardPType
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 10/2020 2020.10 Added Peek
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 11/2016 2016.11 Released as part of OSVVM
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2010 2010.08 Added Tailpointer
-- 12/2006 2006.12 Initial revision
--
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package ScoreBoardPkg_slv is
-- generic (
-- type ExpectedType ;
-- type ActualType ;
-- function Match(Actual : ActualType ; -- defaults
-- Expected : ExpectedType) return boolean ; -- is "=" ;
-- function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
-- function actual_to_string (A : ActualType) return string -- is to_string ;
-- ) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
subtype ExpectedType is std_ulogic_vector ;
subtype ActualType is std_ulogic_vector ;
alias Match is work.AlertLogPkg.MetaMatch [std_ulogic_vector, std_ulogic_vector return boolean] ; -- for std_logic_vector
alias expected_to_string is to_hstring [std_logic_vector return string]; -- VHDL-2008
alias actual_to_string is to_hstring [std_logic_vector return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreboardIdType is record
Id : integer_max ;
end record ScoreboardIdType ;
type ScoreboardIdArrayType is array (integer range <>) of ScoreboardIdType ;
type ScoreboardIdMatrixType is array (integer range <>, integer range <>) of ScoreboardIdType ;
-- Preparation for refactoring - if that ever happens.
subtype FifoIdType is ScoreboardIdType ;
subtype FifoIdArrayType is ScoreboardIdArrayType ;
subtype FifoIdMatrixType is ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) ; -- Deletes all allocated items
procedure Initialize (
constant ID : in ScoreboardIDType
) ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType ;
type ScoreBoardPType is protected
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-------------------------------
-- Array of Tagged Scoreboards
impure function CheckExpected (
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
-- ReportMode := ENABLED when not DoNotReport else DISABLED ;
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
-- Clear check counter. Caution does not change AffirmationCounters
procedure SetCheckCountZero ; -- Simple, with or without tags
procedure SetCheckCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
------------------------------------------------------------
------------------------------------------------------------
-- -- Deprecated Interface to NewID
-- impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- -- Vector: 1 to Size
-- impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Vector: X(X'Left) to X(X'Right)
-- impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Matrix: 1 to X, 1 to Y
-- impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
-- impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end protected ScoreBoardPType ;
------------------------------------------------------------
-- Deprecated Interface to NewID
impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- Vector: 1 to Size
impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end ScoreBoardPkg_slv ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreBoardPkg_slv is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
--!! Replace the following with
-- type ScoreboardRecType is record
-- HeadPointer : ListPointerType ;
-- TailPointer : ListPointerType ;
-- PopListPointer : ListPointerType ;
--
-- ErrCnt : integer ;
-- DropCount : integer ;
-- ItemNumber : integer ;
-- PopCount : integer ;
-- CheckCount : integer ;
-- AlertLogID : AlertLogIDType ;
-- Name : NameStoreIDType ;
-- ReportMode : ScoreboardReportType ;
-- end record ScoreboardRecType ;
--
-- type ScoreboardRecArrayType is array (integer range <>) of ScoreboardRecType ;
-- type ScoreboardRecArrayPointerType is access ScoreboardRecArrayType ;
-- variable ScoreboardPointer : ScoreboardRecArrayPointerType ;
--
-- -- Alas unfortunately aliases don't word as follows:
-- -- alias HeadPointer(I) is ScoreboardPointer(I).HeadPointer ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
-- Original Code
-- variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
--
-- Legal, but crashes simulator more thoroughly
-- variable HeadPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- Working work around for QS 2020.04 and 2021.02
variable Template : ListArrayType(1 to 1) ; -- Work around for QS 2020.04 and 2021.02
variable HeadPointer : ListArrayPointerType := new ListArrayType'(Template) ;
variable TailPointer : ListArrayPointerType := new ListArrayType'(Template) ;
-- PopListPointer needed for Pop to be a function - alternately need 2019 features
variable PopListPointer : ListArrayPointerType := new ListArrayType'(Template) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
variable PrintIndexVar : boolean := TRUE ;
variable CalledNewID : boolean := FALSE ;
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Used by ScoreboardStore
variable NumItems : integer := 0 ;
constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
-- constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
procedure SetPrintIndex (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
PrintIndexVar := Enable ;
end procedure SetPrintIndex ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
constant MinNumItems : in integer
) is
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if NewNumItems > HeadPointer'length then
SetArrayIndex(1, NormalizeArraySize(NewNumItems, MinNumItems)) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- Local/Private to package
impure function LocalNewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable NameID : integer ;
begin
NameID := LocalNameStore.find(Name, ParentID, Search) ;
-- Share the scoreboards if they match
if NameID /= ID_NOT_FOUND.ID then
return ScoreboardIDType'(ID => NameID) ;
else
-- Resize Data Structure as necessary
GrowNumberItems(NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
AlertLogIDVar(NumItems) := NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, Search) ;
AlertIfNotEqual(AlertLogIDVar(NumItems), NameID, NumItems, "ScoreboardPkg: Index of LocalNameStore /= ScoreboardID") ;
return ScoreboardIDType'(ID => NumItems) ;
end if ;
end function LocalNewID ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
return LocalNewID(Name, ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector. Assumes valid range (done by NewID)
impure function LocalNewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
variable Result : ScoreboardIDArrayType(X(X'left) to X(X'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in Result'range loop
Result(i) := LocalNewID(Name & "(" & to_string(i) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1, Size) , ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Array parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Array parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
return LocalNewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix. Assumes valid indices (done by NewID)
impure function LocalNewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable Result : ScoreboardIdMatrixType(X(X'left) to X(X'right), Y(Y'left) to Y(Y'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ;
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in X(X'left) to X(X'right) loop
for j in Y(Y'left) to Y(Y'right) loop
Result(i, j) := LocalNewID(Name & "(" & to_string(i) & ", " & to_string(j) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1,X), (1,Y), ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Matrix parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, Y'length /= 2, "ScoreboardPkg.NewID Matrix parameter Y has " & to_string(Y'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Matrix parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
AlertIf(ParentID, Y(Y'Left) > Y(Y'right), "ScoreboardPkg.NewID Matrix parameter Y(Y'left): " & to_string(Y'Left) & " must be <= Y(Y'right): " & to_string(Y(Y'right)), FAILURE) ;
return LocalNewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
NumItems := 0 ;
CalledNewID := FALSE ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(Index) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(FirstIndexVar) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean ;
constant ExpectedInFIFO : in boolean := TRUE
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 and PrintIndexVar then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
if ExpectedInFIFO then
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
else
write(WriteBuf, " Received: " & expected_to_string(ExpectedPtr.all)) ;
if FoundError then
write(WriteBuf, " Expected: " & actual_to_string(ActualData)) ;
end if ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Scoreboard Store. Index. Tag.
impure function CheckExpected (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ExpectedData, FoundError, ExpectedInFIFO => FALSE) ;
return not FoundError ;
end function CheckExpected ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero (Index : integer) is
------------------------------------------------------------
begin
CheckCountVar(Index) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero is
------------------------------------------------------------
begin
CheckCountVar(FirstIndexVar) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
impure function GotScoreboards return boolean is
------------------------------------------------------------
begin
return CalledNewID ;
end function GotScoreboards ;
------------------------------------------------------------
-- pt local
procedure WriteScoreboardYaml (Index : integer; file CovYamlFile : text) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
write(buf, NAME_PREFIX & "- Name: " & '"' & string'(GetAlertLogName(AlertLogIDVar(Index))) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemCount: " & '"' & to_string(ItemNumberVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ErrorCount: " & '"' & to_string(ErrCntVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsChecked: " & '"' & to_string(CheckCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsPopped: " & '"' & to_string(PopCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsDropped: " & '"' & to_string(DropCountVar(Index)) & '"' & LF) ;
writeline(CovYamlFile, buf) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_sb.yml", FileName) ;
file SbYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
if AlertLogIDVar = NULL or AlertLogIDVar'length <= 0 then
Alert("Scoreboard.WriteScoreboardYaml: no scoreboards defined ", ERROR) ;
return ;
end if ;
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "TestCase: " & '"' & GetAlertLogName & '"' & LF) ;
swrite(buf, "Scoreboards: ") ;
writeline(SbYamlFile, buf) ;
if CalledNewID then
-- Used by singleton
for i in 1 to NumItems loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
else
-- Used by PT method, but not singleton
for i in AlertLogIDVar'range loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
end if ;
file_close(SbYamlFile) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: 1 to Size
--!! impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, (1, Size) , ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: X(X'Left) to X(X'Right)
--!! impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: 1 to X, 1 to Y
--!! impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
--!! impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
end protected body ScoreBoardPType ;
shared variable ScoreboardStore : ScoreBoardPType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, Size, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (
------------------------------------------------------------
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Item) ;
end procedure Push ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, ActualData) ;
end procedure Check ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end procedure Check ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, ActualData) ;
end function Check ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end function Check ;
-------------
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end procedure CheckExpected ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end procedure CheckExpected ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end function CheckExpected ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end function CheckExpected ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Item) ;
end procedure Pop ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Tag, Item) ;
end procedure Pop ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID) ;
end function Pop ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID, Tag) ;
end function Pop ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Tag, Item) ;
end procedure Peek ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Item) ;
end procedure Peek ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
-- return ScoreboardStore.Peek(Tag) ;
log("Issues compiling return later");
return ScoreboardStore.Peek(Index => ID.ID, Tag => Tag) ;
end function Peek ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Peek(Index => ID.ID) ;
end function Peek ;
------------------------------------------------------------
-- ScoreboardEmpty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function ScoreboardEmpty ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function ScoreboardEmpty ;
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function Empty ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function Empty ;
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, Name, ParentID, CreateHierarchy, DoNotReport) ;
--!! end procedure SetAlertLogID ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, A) ;
--!! end procedure SetAlertLogID ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType is
begin
return ScoreboardStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetItemCount(ID.ID) ;
end function GetItemCount ;
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPushCount(ID.ID) ;
end function GetPushCount ;
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPopCount(ID.ID) ;
end function GetPopCount ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetFifoCount(ID.ID) ;
end function GetFifoCount ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetCheckCount(ID.ID) ;
end function GetCheckCount ;
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetDropCount(ID.ID) ;
end function GetDropCount ;
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, ActualData) ;
end function Find ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, ItemNumber) ;
end procedure Flush ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Scoreboard YAML Reports
impure function GotScoreboards return boolean is
begin
return ScoreboardStore.GotScoreboards ;
end function GotScoreboards ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
begin
ScoreboardStore.WriteScoreboardYaml(FileName, OpenKind) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Deallocate ;
end procedure Deallocate ;
procedure Initialize (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Initialize ;
end procedure Initialize ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer is
begin
return GetAlertCount(ScoreboardStore.GetAlertLogID(ID.ID)) ;
end function GetErrorCount ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
ScoreboardStore.CheckFinish(ID.ID, FinishCheckCount, FinishEmpty) ;
end procedure CheckFinish ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) is
begin
-- ScoreboardStore.SetReportMode(ID.ID, ReportModeIn) ;
ScoreboardStore.SetReportMode(ReportModeIn) ;
end procedure SetReportMode ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType is
begin
-- return ScoreboardStore.GetReportMode(ID.ID) ;
return ScoreboardStore.GetReportMode ;
end function GetReportMode ;
--==========================================================
--!! Deprecated Subprograms
--==========================================================
------------------------------------------------------------
-- Deprecated interface to NewID
impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, Size, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
end ScoreBoardPkg_slv ; | artistic-2.0 | 6c3e9922c03d276eae5f7a60aef5ebe5 | 0.535186 | 5.354465 | false | false | false | false |
UnofficialRepos/OSVVM | ScoreboardGenericPkg.vhd | 1 | 135,946 | --
-- File Name: ScoreBoardGenericPkg.vhd
-- Design Unit Name: ScoreBoardGenericPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Defines types and methods to implement a FIFO based Scoreboard
-- Defines type ScoreBoardPType
-- Defines methods for putting values the scoreboard
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 03/2022 2022.03 Removed deprecated SetAlertLogID in Singleton API
-- 02/2022 2022.02 Added WriteScoreboardYaml and GotScoreboards. Updated NewID with ParentID,
-- ReportMode, Search, PrintParent. Supports searching for Scoreboard models..
-- 01/2022 2022.01 Added CheckExpected. Added SetCheckCountZero to ScoreboardPType
-- 08/2021 2021.08 Removed SetAlertLogID from singleton public interface - set instead by NewID
-- 06/2021 2021.06 Updated Data Structure, IDs for new use model, and Wrapper Subprograms
-- 10/2020 2020.10 Added Peek
-- 05/2020 2020.05 Updated calls to IncAffirmCount
-- Overloaded Check with functions that return pass/fail (T/F)
-- Added GetFifoCount. Added GetPushCount which is same as GetItemCount
-- 01/2020 2020.01 Updated Licenses to Apache
-- 04/2018 2018.04 Made Pop Functions Visible. Prep for AlertLogIDType being a type.
-- 05/2017 2017.05 First print Actual then only print Expected if mis-match
-- 11/2016 2016.11 Released as part of OSVVM
-- 06/2015 2015.06 Added Alerts, SetAlertLogID, Revised LocalPush, GetDropCount,
-- Deprecated SetFinish and ReportMode - REPORT_NONE, FileOpen
-- Deallocate, Initialized, Function SetName
-- 09/2013 2013.09 Added file handling, Check Count, Finish Status
-- Find, Flush
-- 08/2013 2013.08 Generics: to_string replaced write, Match replaced check
-- Added Tags - Experimental
-- Added Array of Scoreboards
-- 08/2012 2012.08 Added Type and Subprogram Generics
-- 05/2012 2012.05 Changed FIFO to store pointers to ExpectedType
-- Allows usage of unconstrained arrays
-- 08/2010 2010.08 Added Tailpointer
-- 12/2006 2006.12 Initial revision
--
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TranscriptPkg.all ;
use work.TextUtilPkg.all ;
use work.AlertLogPkg.all ;
use work.NamePkg.all ;
use work.NameStorePkg.all ;
use work.ResolutionPkg.all ;
package ScoreboardGenericPkg is
generic (
type ExpectedType ;
type ActualType ;
function Match(Actual : ActualType ; -- defaults
Expected : ExpectedType) return boolean ; -- is "=" ;
function expected_to_string(A : ExpectedType) return string ; -- is to_string ;
function actual_to_string (A : ActualType) return string -- is to_string ;
) ;
-- -- For a VHDL-2002 package, comment out the generics and
-- -- uncomment the following, it replaces a generic instance of the package.
-- -- As a result, you will have multiple copies of the entire package.
-- -- Inconvenient, but ok as it still works the same.
-- subtype ExpectedType is std_logic_vector ;
-- subtype ActualType is std_logic_vector ;
-- alias Match is std_match [ActualType, ExpectedType return boolean] ; -- for std_logic_vector
-- alias expected_to_string is to_hstring [ExpectedType return string]; -- VHDL-2008
-- alias actual_to_string is to_hstring [ActualType return string]; -- VHDL-2008
-- ScoreboardReportType is deprecated
-- Replaced by Affirmations. ERROR is the default. ALL turns on PASSED flag
type ScoreboardReportType is (REPORT_ERROR, REPORT_ALL, REPORT_NONE) ; -- replaced by affirmations
type ScoreboardIdType is record
Id : integer_max ;
end record ScoreboardIdType ;
type ScoreboardIdArrayType is array (integer range <>) of ScoreboardIdType ;
type ScoreboardIdMatrixType is array (integer range <>, integer range <>) of ScoreboardIdType ;
-- Preparation for refactoring - if that ever happens.
subtype FifoIdType is ScoreboardIdType ;
subtype FifoIdArrayType is ScoreboardIdArrayType ;
subtype FifoIdMatrixType is ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean ; -- Simple, Tagged
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer ; -- Simple, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) ; -- Deletes all allocated items
procedure Initialize (
constant ID : in ScoreboardIDType
) ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType ;
type ScoreBoardPType is protected
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType ;
------------------------------------------------------------
-- Emulate arrays of scoreboards
procedure SetArrayIndex(L, R : integer) ; -- supports integer indices
procedure SetArrayIndex(R : natural) ; -- indicies 1 to R
impure function GetArrayIndex return integer_vector ;
impure function GetArrayLength return natural ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Push (
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Push (
constant Index : in integer ;
constant Item : in ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Push (
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) ;
-- ------------------------------------------------------------
-- -- Push items into the scoreboard/FIFO
-- -- Function form supports chaining of operations
-- -- In 2013, this caused overloading issues in some simulators, will retest later
--
-- -- Simple Scoreboard, no tag
-- impure function Push (Item : ExpectedType) return ExpectedType ;
--
-- -- Simple Tagged Scoreboard
-- impure function Push (
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Scoreboards, no tag
-- impure function Push (
-- constant Index : in integer ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ;
--
-- -- Array of Tagged Scoreboards
-- impure function Push (
-- constant Index : in integer ;
-- constant Tag : in string ;
-- constant Item : in ExpectedType
-- ) return ExpectedType ; -- for chaining of operations
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) ;
-- Simple Tagged Scoreboard
procedure Check (
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Array of Scoreboards, no tag
procedure Check (
constant Index : in integer ;
constant ActualData : in ActualType
) ;
-- Array of Tagged Scoreboards
procedure Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) ;
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean ;
-- Simple Tagged Scoreboard
impure function Check (
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Scoreboards, no tag
impure function Check (
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean ;
-- Array of Tagged Scoreboards
impure function Check (
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean ;
-------------------------------
-- Array of Tagged Scoreboards
impure function CheckExpected (
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) ;
-- Simple Tagged Scoreboard
procedure Pop (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Pop (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Array of Tagged Scoreboards
procedure Pop (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Pop (
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType ;
-- Array of Tagged Scoreboards
impure function Pop (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Array of Tagged Scoreboards
procedure Peek (
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Array of Scoreboards, no tag
procedure Peek (
constant Index : in integer ;
variable Item : out ExpectedType
) ;
-- Simple Tagged Scoreboard
procedure Peek (
constant Tag : in string ;
variable Item : out ExpectedType
) ;
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Array of Tagged Scoreboards
impure function Peek (
constant Index : in integer ;
constant Tag : in string
) return ExpectedType ;
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType ;
-- Simple Tagged Scoreboard
impure function Peek (
constant Tag : in string
) return ExpectedType ;
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType ;
------------------------------------------------------------
-- Empty - check to see if scoreboard is empty
impure function Empty return boolean ; -- Simple
impure function Empty (Tag : String) return boolean ; -- Simple, Tagged
impure function Empty (Index : integer) return boolean ; -- Array
impure function Empty (Index : integer; Tag : String) return boolean ; -- Array, Tagged
------------------------------------------------------------
-- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
-- ReportMode := ENABLED when not DoNotReport else DISABLED ;
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) ;
-- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) ;
procedure SetAlertLogID (A : AlertLogIDType) ;
impure function GetAlertLogID(Index : Integer) return AlertLogIDType ;
impure function GetAlertLogID return AlertLogIDType ;
------------------------------------------------------------
-- Set a scoreboard name.
-- Used when scoreboard AlertLogID is shared between different sources.
procedure SetName (Name : String) ;
impure function SetName (Name : String) return string ;
impure function GetName (DefaultName : string := "Scoreboard") return string ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount return integer ; -- Simple, with or without tags
impure function GetItemCount (Index : integer) return integer ; -- Arrays, with or without tags
impure function GetPushCount return integer ; -- Simple, with or without tags
impure function GetPushCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (Index : integer) return integer ;
impure function GetPopCount return integer ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (Index : integer) return integer ;
impure function GetFifoCount return integer ;
-- Number of items checked by scoreboard
impure function GetCheckCount return integer ; -- Simple, with or without tags
impure function GetCheckCount (Index : integer) return integer ; -- Arrays, with or without tags
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount return integer ; -- Simple, with or without tags
impure function GetDropCount (Index : integer) return integer ; -- Arrays, with or without tags
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ActualData : in ActualType
) return integer ;
-- Tagged Scoreboard
impure function Find (
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
-- Array of Simple Scoreboards
impure function Find (
constant Index : in integer ;
constant ActualData : in ActualType
) return integer ;
-- Array of Tagged Scoreboards
impure function Find (
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboard
procedure Flush (
constant ItemNumber : in integer
) ;
-- Tagged Scoreboard - only removes items that also match the tag
procedure Flush (
constant Tag : in string ;
constant ItemNumber : in integer
) ;
-- Array of Simple Scoreboards
procedure Flush (
constant Index : in integer ;
constant ItemNumber : in integer
) ;
-- Array of Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) ;
------------------------------------------------------------
-- Writing YAML Reports
impure function GotScoreboards return boolean ;
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate ; -- Deletes all allocated items
procedure Initialize ; -- Creates initial data structure if it was destroyed with Deallocate
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Use alerts directly instead.
-- AlertIF(SB.GetCheckCount < 10, ....) ;
-- AlertIf(Not SB.Empty, ...) ;
------------------------------------------------------------
-- Set alerts if scoreboard not empty or if CheckCount <
-- Use if need to check empty or CheckCount for a specific scoreboard.
-- Simple Scoreboards, with or without tag
procedure CheckFinish (
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
-- Array of Scoreboards, with or without tag
procedure CheckFinish (
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Simple Scoreboards, with or without tag
impure function GetErrorCount return integer ;
-- Array of Scoreboards, with or without tag
impure function GetErrorCount(Index : integer) return integer ;
------------------------------------------------------------
-- Error count manipulation
-- IncErrorCount - not recommended, use alerts instead - may be deprecated in the future
procedure IncErrorCount ; -- Simple, with or without tags
procedure IncErrorCount (Index : integer) ; -- Arrays, with or without tags
-- Clear error counter. Caution does not change AlertCounts, must also use AlertLogPkg.ClearAlerts
procedure SetErrorCountZero ; -- Simple, with or without tags
procedure SetErrorCountZero (Index : integer) ; -- Arrays, with or without tags
-- Clear check counter. Caution does not change AffirmationCounters
procedure SetCheckCountZero ; -- Simple, with or without tags
procedure SetCheckCountZero (Index : integer) ; -- Arrays, with or without tags
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Names changed. Maintained for backward compatibility - would prefer an alias
------------------------------------------------------------
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) ; -- Replaced by TranscriptPkg.TranscriptOpen
procedure PutExpectedData (ExpectedData : ExpectedType) ; -- Replaced by push
procedure CheckActualData (ActualData : ActualType) ; -- Replaced by Check
impure function GetItemNumber return integer ; -- Replaced by GetItemCount
procedure SetMessage (MessageIn : String) ; -- Replaced by SetName
impure function GetMessage return string ; -- Replaced by GetName
-- Deprecated and may be deleted in a future revision
procedure SetFinish ( -- Replaced by CheckFinish
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
procedure SetFinish ( -- Replaced by CheckFinish
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (ReportModeIn : ScoreboardReportType) ;
impure function GetReportMode return ScoreboardReportType ;
------------------------------------------------------------
------------------------------------------------------------
-- -- Deprecated Interface to NewID
-- impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- -- Vector: 1 to Size
-- impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Vector: X(X'Left) to X(X'Right)
-- impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- -- Matrix: 1 to X, 1 to Y
-- impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
-- impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end protected ScoreBoardPType ;
------------------------------------------------------------
-- Deprecated Interface to NewID
impure function NewID (Name : String; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType ;
-- Vector: 1 to Size
impure function NewID (Name : String; Size : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String; X : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType ;
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String; X, Y : positive; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String; X, Y : integer_vector; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType ;
end ScoreboardGenericPkg ;
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
package body ScoreboardGenericPkg is
type ScoreBoardPType is protected body
type ExpectedPointerType is access ExpectedType ;
type ListType ;
type ListPointerType is access ListType ;
type ListType is record
ItemNumber : integer ;
TagPtr : line ;
ExpectedPtr : ExpectedPointerType ;
NextPtr : ListPointerType ;
end record ;
--!! Replace the following with
-- type ScoreboardRecType is record
-- HeadPointer : ListPointerType ;
-- TailPointer : ListPointerType ;
-- PopListPointer : ListPointerType ;
--
-- ErrCnt : integer ;
-- DropCount : integer ;
-- ItemNumber : integer ;
-- PopCount : integer ;
-- CheckCount : integer ;
-- AlertLogID : AlertLogIDType ;
-- Name : NameStoreIDType ;
-- ReportMode : ScoreboardReportType ;
-- end record ScoreboardRecType ;
--
-- type ScoreboardRecArrayType is array (integer range <>) of ScoreboardRecType ;
-- type ScoreboardRecArrayPointerType is access ScoreboardRecArrayType ;
-- variable ScoreboardPointer : ScoreboardRecArrayPointerType ;
--
-- -- Alas unfortunately aliases don't word as follows:
-- -- alias HeadPointer(I) is ScoreboardPointer(I).HeadPointer ;
type ListArrayType is array (integer range <>) of ListPointerType ;
type ListArrayPointerType is access ListArrayType ;
variable ArrayLengthVar : integer := 1 ;
-- Original Code
-- variable HeadPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType(1 to 1) ;
--
-- Legal, but crashes simulator more thoroughly
-- variable HeadPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- variable TailPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- -- PopListPointer needed for Pop to be a function - alternately need 2019 features
-- variable PopListPointer : ListArrayPointerType := new ListArrayType'(1 => NULL) ;
-- Working work around for QS 2020.04 and 2021.02
variable Template : ListArrayType(1 to 1) ; -- Work around for QS 2020.04 and 2021.02
variable HeadPointer : ListArrayPointerType := new ListArrayType'(Template) ;
variable TailPointer : ListArrayPointerType := new ListArrayType'(Template) ;
-- PopListPointer needed for Pop to be a function - alternately need 2019 features
variable PopListPointer : ListArrayPointerType := new ListArrayType'(Template) ;
type IntegerArrayType is array (integer range <>) of Integer ;
type IntegerArrayPointerType is access IntegerArrayType ;
type AlertLogIDArrayType is array (integer range <>) of AlertLogIDType ;
type AlertLogIDArrayPointerType is access AlertLogIDArrayType ;
variable ErrCntVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable DropCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable ItemNumberVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable PopCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable CheckCountVar : IntegerArrayPointerType := new IntegerArrayType'(1 => 0) ;
variable AlertLogIDVar : AlertLogIDArrayPointerType := new AlertLogIDArrayType'(1 => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
variable NameVar : NamePType ;
variable ReportModeVar : ScoreboardReportType ;
variable FirstIndexVar : integer := 1 ;
variable PrintIndexVar : boolean := TRUE ;
variable CalledNewID : boolean := FALSE ;
variable LocalNameStore : NameStorePType ;
------------------------------------------------------------
-- Used by ScoreboardStore
variable NumItems : integer := 0 ;
constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
-- constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
procedure SetPrintIndex (Enable : boolean := TRUE) is
------------------------------------------------------------
begin
PrintIndexVar := Enable ;
end procedure SetPrintIndex ;
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer := NewNumItems ;
variable ModNumItems : integer := 0;
begin
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
constant MinNumItems : in integer
) is
variable NewNumItems : integer ;
begin
NewNumItems := NumItems + GrowAmount ;
if NewNumItems > HeadPointer'length then
SetArrayIndex(1, NormalizeArraySize(NewNumItems, MinNumItems)) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
-- Local/Private to package
impure function LocalNewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable NameID : integer ;
begin
NameID := LocalNameStore.find(Name, ParentID, Search) ;
-- Share the scoreboards if they match
if NameID /= ID_NOT_FOUND.ID then
return ScoreboardIDType'(ID => NameID) ;
else
-- Resize Data Structure as necessary
GrowNumberItems(NumItems, GrowAmount => 1, MinNumItems => MIN_NUM_ITEMS) ;
-- Create AlertLogID
AlertLogIDVar(NumItems) := NewID(Name, ParentID, ReportMode, PrintParent, CreateHierarchy => FALSE) ;
-- Add item to NameStore
NameID := LocalNameStore.NewID(Name, ParentID, Search) ;
AlertIfNotEqual(AlertLogIDVar(NumItems), NameID, NumItems, "ScoreboardPkg: Index of LocalNameStore /= ScoreboardID") ;
return ScoreboardIDType'(ID => NumItems) ;
end if ;
end function LocalNewID ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
return LocalNewID(Name, ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector. Assumes valid range (done by NewID)
impure function LocalNewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
variable Result : ScoreboardIDArrayType(X(X'left) to X(X'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ; -- historic, but needed
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in Result'range loop
Result(i) := LocalNewID(Name & "(" & to_string(i) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1, Size) , ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Array parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Array parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
return LocalNewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix. Assumes valid indices (done by NewID)
impure function LocalNewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable Result : ScoreboardIdMatrixType(X(X'left) to X(X'right), Y(Y'left) to Y(Y'right)) ;
variable ResolvedSearch : NameSearchType ;
variable ResolvedPrintParent : AlertLogPrintParentType ;
-- variable ArrayParentID : AlertLogIDType ;
begin
CalledNewID := TRUE ;
SetPrintIndex(FALSE) ;
ResolvedSearch := ResolveSearch (ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, Search) ;
ResolvedPrintParent := ResolvePrintParent(ParentID /= OSVVM_SCOREBOARD_ALERTLOG_ID, PrintParent) ;
-- ArrayParentID := NewID(Name, ParentID, ReportMode, ResolvedPrintParent, CreateHierarchy => FALSE) ;
for i in X(X'left) to X(X'right) loop
for j in Y(Y'left) to Y(Y'right) loop
Result(i, j) := LocalNewID(Name & "(" & to_string(i) & ", " & to_string(j) & ")", ParentID, ReportMode, ResolvedSearch, ResolvedPrintParent) ;
end loop ;
end loop ;
return Result ;
end function LocalNewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return LocalNewID(Name, (1,X), (1,Y), ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
AlertIf(ParentID, X'length /= 2, "ScoreboardPkg.NewID Matrix parameter X has " & to_string(X'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, Y'length /= 2, "ScoreboardPkg.NewID Matrix parameter Y has " & to_string(Y'length) & "dimensions. Required to be 2", FAILURE) ;
AlertIf(ParentID, X(X'Left) > X(X'right), "ScoreboardPkg.NewID Matrix parameter X(X'left): " & to_string(X'Left) & " must be <= X(X'right): " & to_string(X(X'right)), FAILURE) ;
AlertIf(ParentID, Y(Y'Left) > Y(Y'right), "ScoreboardPkg.NewID Matrix parameter Y(Y'left): " & to_string(Y'Left) & " must be <= Y(Y'right): " & to_string(Y(Y'right)), FAILURE) ;
return LocalNewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
procedure SetName (Name : String) is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
end procedure SetName ;
------------------------------------------------------------
impure function SetName (Name : String) return string is
------------------------------------------------------------
begin
NameVar.Set(Name) ;
return Name ;
end function SetName ;
------------------------------------------------------------
impure function GetName (DefaultName : string := "Scoreboard") return string is
------------------------------------------------------------
begin
return NameVar.Get(DefaultName) ;
end function GetName ;
------------------------------------------------------------
procedure SetReportMode (ReportModeIn : ScoreboardReportType) is
------------------------------------------------------------
begin
ReportModeVar := ReportModeIn ;
if ReportModeVar = REPORT_ALL then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: To turn off REPORT_ALL, use osvvm.AlertLogPkg.SetLogEnable(PASSED, FALSE)", WARNING) ;
for i in AlertLogIDVar'range loop
SetLogEnable(AlertLogIDVar(i), PASSED, TRUE) ;
end loop ;
end if ;
if ReportModeVar = REPORT_NONE then
Alert(OSVVM_SCOREBOARD_ALERTLOG_ID, "ScoreboardGenericPkg.SetReportMode: ReportMode REPORT_NONE has been deprecated and will be removed in next revision. Please contact OSVVM architect Jim Lewis if you need this capability.", WARNING) ;
end if ;
end procedure SetReportMode ;
------------------------------------------------------------
impure function GetReportMode return ScoreboardReportType is
------------------------------------------------------------
begin
return ReportModeVar ;
end function GetReportMode ;
------------------------------------------------------------
procedure SetArrayIndex(L, R : integer) is
------------------------------------------------------------
variable OldHeadPointer, OldTailPointer, OldPopListPointer : ListArrayPointerType ;
variable OldErrCnt, OldDropCount, OldItemNumber, OldPopCount, OldCheckCount : IntegerArrayPointerType ;
variable OldAlertLogIDVar : AlertLogIDArrayPointerType ;
variable Min, Max, Len, OldLen, OldMax : integer ;
begin
Min := minimum(L, R) ;
Max := maximum(L, R) ;
OldLen := ArrayLengthVar ;
OldMax := Min + ArrayLengthVar - 1 ;
Len := Max - Min + 1 ;
ArrayLengthVar := Len ;
if Len >= OldLen then
FirstIndexVar := Min ;
OldHeadPointer := HeadPointer ;
HeadPointer := new ListArrayType(Min to Max) ;
if OldHeadPointer /= NULL then
HeadPointer(Min to OldMax) := OldHeadPointer.all ; -- (OldHeadPointer'range) ;
Deallocate(OldHeadPointer) ;
end if ;
OldTailPointer := TailPointer ;
TailPointer := new ListArrayType(Min to Max) ;
if OldTailPointer /= NULL then
TailPointer(Min to OldMax) := OldTailPointer.all ;
Deallocate(OldTailPointer) ;
end if ;
OldPopListPointer := PopListPointer ;
PopListPointer := new ListArrayType(Min to Max) ;
if OldPopListPointer /= NULL then
PopListPointer(Min to OldMax) := OldPopListPointer.all ;
Deallocate(OldPopListPointer) ;
end if ;
OldErrCnt := ErrCntVar ;
ErrCntVar := new IntegerArrayType'(Min to Max => 0) ;
if OldErrCnt /= NULL then
ErrCntVar(Min to OldMax) := OldErrCnt.all ;
Deallocate(OldErrCnt) ;
end if ;
OldDropCount := DropCountVar ;
DropCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldDropCount /= NULL then
DropCountVar(Min to OldMax) := OldDropCount.all ;
Deallocate(OldDropCount) ;
end if ;
OldItemNumber := ItemNumberVar ;
ItemNumberVar := new IntegerArrayType'(Min to Max => 0) ;
if OldItemNumber /= NULL then
ItemNumberVar(Min to OldMax) := OldItemNumber.all ;
Deallocate(OldItemNumber) ;
end if ;
OldPopCount := PopCountVar ;
PopCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldPopCount /= NULL then
PopCountVar(Min to OldMax) := OldPopCount.all ;
Deallocate(OldPopCount) ;
end if ;
OldCheckCount := CheckCountVar ;
CheckCountVar := new IntegerArrayType'(Min to Max => 0) ;
if OldCheckCount /= NULL then
CheckCountVar(Min to OldMax) := OldCheckCount.all ;
Deallocate(OldCheckCount) ;
end if ;
OldAlertLogIDVar := AlertLogIDVar ;
AlertLogIDVar := new AlertLogIDArrayType'(Min to Max => OSVVM_SCOREBOARD_ALERTLOG_ID) ;
if OldAlertLogIDVar /= NULL then
AlertLogIDVar(Min to OldMax) := OldAlertLogIDVar.all ;
Deallocate(OldAlertLogIDVar) ;
end if ;
elsif Len < OldLen then
report "ScoreboardGenericPkg: SetArrayIndex, new array Length <= current array length"
severity failure ;
end if ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure SetArrayIndex(R : natural) is
------------------------------------------------------------
begin
SetArrayIndex(1, R) ;
end procedure SetArrayIndex ;
------------------------------------------------------------
procedure Deallocate is
------------------------------------------------------------
variable CurListPtr, LastListPtr : ListPointerType ;
begin
for Index in HeadPointer'range loop
-- Deallocate contents in the scoreboards
CurListPtr := HeadPointer(Index) ;
while CurListPtr /= Null loop
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
LastListPtr := CurListPtr ;
CurListPtr := CurListPtr.NextPtr ;
Deallocate(LastListPtr) ;
end loop ;
end loop ;
for Index in PopListPointer'range loop
-- Deallocate PopListPointer - only has single element
CurListPtr := PopListPointer(Index) ;
if CurListPtr /= NULL then
deallocate(CurListPtr.TagPtr) ;
deallocate(CurListPtr.ExpectedPtr) ;
deallocate(CurListPtr) ;
end if ;
end loop ;
-- Deallocate arrays of pointers
Deallocate(HeadPointer) ;
Deallocate(TailPointer) ;
Deallocate(PopListPointer) ;
-- Deallocate supporting arrays
Deallocate(ErrCntVar) ;
Deallocate(DropCountVar) ;
Deallocate(ItemNumberVar) ;
Deallocate(PopCountVar) ;
Deallocate(CheckCountVar) ;
Deallocate(AlertLogIDVar) ;
-- Deallocate NameVar - NamePType
NameVar.Deallocate ;
ArrayLengthVar := 0 ;
NumItems := 0 ;
CalledNewID := FALSE ;
end procedure Deallocate ;
------------------------------------------------------------
-- Construct initial data structure
procedure Initialize is
------------------------------------------------------------
begin
SetArrayIndex(1, 1) ;
end procedure Initialize ;
------------------------------------------------------------
impure function GetArrayIndex return integer_vector is
------------------------------------------------------------
begin
return (1 => HeadPointer'left, 2 => HeadPointer'right) ;
end function GetArrayIndex ;
------------------------------------------------------------
impure function GetArrayLength return natural is
------------------------------------------------------------
begin
return ArrayLengthVar ; -- HeadPointer'length ;
end function GetArrayLength ;
------------------------------------------------------------
procedure SetAlertLogID (Index : Integer ; A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(Index) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID (A : AlertLogIDType) is
------------------------------------------------------------
begin
AlertLogIDVar(FirstIndexVar) := A ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Index : Integer; Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(Index) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
procedure SetAlertLogID(Name : string; ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID; CreateHierarchy : Boolean := TRUE; DoNotReport : Boolean := FALSE) is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
AlertLogIDVar(FirstIndexVar) := NewID(Name, ParentID, ReportMode => ReportMode, PrintParent => PRINT_NAME, CreateHierarchy => CreateHierarchy) ;
end procedure SetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID(Index : Integer) return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(Index) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function GetAlertLogID return AlertLogIDType is
------------------------------------------------------------
begin
return AlertLogIDVar(FirstIndexVar) ;
end function GetAlertLogID ;
------------------------------------------------------------
impure function LocalOutOfRange(
------------------------------------------------------------
constant Index : in integer ;
constant Name : in string
) return boolean is
begin
return AlertIf(OSVVM_SCOREBOARD_ALERTLOG_ID, Index < HeadPointer'Low or Index > HeadPointer'High,
GetName & " " & Name & " Index: " & to_string(Index) &
"is not in the range (" & to_string(HeadPointer'Low) &
"to " & to_string(HeadPointer'High) & ")",
FAILURE ) ;
end function LocalOutOfRange ;
------------------------------------------------------------
procedure LocalPush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
ItemNumberVar(Index) := ItemNumberVar(Index) + 1 ;
ExpectedPtr := new ExpectedType'(Item) ;
TagPtr := new string'(Tag) ;
if HeadPointer(Index) = NULL then
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- HeadPointer(Index) := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
HeadPointer(Index) := new ListType ;
HeadPointer(Index).ItemNumber := ItemNumberVar(Index) ;
HeadPointer(Index).TagPtr := TagPtr ;
HeadPointer(Index).ExpectedPtr := ExpectedPtr ;
HeadPointer(Index).NextPtr := NULL ;
TailPointer(Index) := HeadPointer(Index) ;
else
-- 2015.05: allocation using ListTtype'(...) in a protected type does not work in some simulators
-- TailPointer(Index).NextPtr := new ListType'(ItemNumberVar(Index), TagPtr, ExpectedPtr, NULL) ;
TailPointer(Index).NextPtr := new ListType ;
TailPointer(Index).NextPtr.ItemNumber := ItemNumberVar(Index) ;
TailPointer(Index).NextPtr.TagPtr := TagPtr ;
TailPointer(Index).NextPtr.ExpectedPtr := ExpectedPtr ;
TailPointer(Index).NextPtr.NextPtr := NULL ;
TailPointer(Index) := TailPointer(Index).NextPtr ;
end if ;
end procedure LocalPush ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
variable ExpectedPtr : ExpectedPointerType ;
variable TagPtr : line ;
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) is
begin
if LocalOutOfRange(Index, "Push") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (Item : in ExpectedType) is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
end procedure Push ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Push (
------------------------------------------------------------
constant Index : in integer ;
constant Item : in ExpectedType
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Push") then
return Item ; -- error reporting in LocalOutOfRange
end if ;
LocalPush(Index, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Push (
------------------------------------------------------------
constant Tag : in string ;
constant Item : in ExpectedType
) return ExpectedType is
begin
LocalPush(FirstIndexVar, Tag, Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Push (Item : ExpectedType) return ExpectedType is
------------------------------------------------------------
begin
LocalPush(FirstIndexVar, "", Item) ;
return Item ;
end function Push ;
------------------------------------------------------------
-- Local Only
-- Pops highest element matching Tag into PopListPointer(Index)
procedure LocalPop (Index : integer ; Tag : string; Name : string) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Pop/Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during " & Name, FAILURE) ;
return ;
end if ;
PopCountVar(Index) := PopCountVar(Index) + 1 ;
-- deallocate previous pointer
if PopListPointer(Index) /= NULL then
deallocate(PopListPointer(Index).TagPtr) ;
deallocate(PopListPointer(Index).ExpectedPtr) ;
deallocate(PopListPointer(Index)) ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
PopListPointer(Index) := HeadPointer(Index) ;
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Pop/Check (" & Name & "), tag: " & Tag & " not found", FAILURE) ;
exit ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
PopListPointer(Index) := CurPtr.NextPtr ;
CurPtr.NextPtr := CurPtr.NextPtr.NextPtr ;
if CurPtr.NextPtr = NULL then
TailPointer(Index) := CurPtr ;
end if ;
exit ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end procedure LocalPop ;
------------------------------------------------------------
-- Local Only
procedure LocalCheck (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType ;
variable FoundError : inout boolean ;
constant ExpectedInFIFO : in boolean := TRUE
) is
variable ExpectedPtr : ExpectedPointerType ;
variable CurrentItem : integer ;
variable WriteBuf : line ;
variable PassedFlagEnabled : boolean ;
begin
CheckCountVar(Index) := CheckCountVar(Index) + 1 ;
ExpectedPtr := PopListPointer(Index).ExpectedPtr ;
CurrentItem := PopListPointer(Index).ItemNumber ;
PassedFlagEnabled := GetLogEnable(AlertLogIDVar(Index), PASSED) ;
if not Match(ActualData, ExpectedPtr.all) then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
FoundError := TRUE ;
IncAffirmCount(AlertLogIDVar(Index)) ;
else
FoundError := FALSE ;
if not PassedFlagEnabled then
IncAffirmPassedCount(AlertLogIDVar(Index)) ;
end if ;
end if ;
-- IncAffirmCount(AlertLogIDVar(Index)) ;
-- if FoundError or ReportModeVar = REPORT_ALL then
if FoundError or PassedFlagEnabled then
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 and PrintIndexVar then
write(WriteBuf, " (" & to_string(Index) & ") ") ;
end if ;
if ExpectedInFIFO then
write(WriteBuf, " Received: " & actual_to_string(ActualData)) ;
if FoundError then
write(WriteBuf, " Expected: " & expected_to_string(ExpectedPtr.all)) ;
end if ;
else
write(WriteBuf, " Received: " & expected_to_string(ExpectedPtr.all)) ;
if FoundError then
write(WriteBuf, " Expected: " & actual_to_string(ActualData)) ;
end if ;
end if ;
if PopListPointer(Index).TagPtr.all /= "" then
write(WriteBuf, " Tag: " & PopListPointer(Index).TagPtr.all) ;
end if;
write(WriteBuf, " Item Number: " & to_string(CurrentItem)) ;
if FoundError then
if ReportModeVar /= REPORT_NONE then
-- Affirmation Failed
Alert(AlertLogIDVar(Index), WriteBuf.all, ERROR) ;
else
-- Affirmation Failed, but silent, unless in DEBUG mode
Log(AlertLogIDVar(Index), "ERROR " & WriteBuf.all, DEBUG) ;
IncAlertCount(AlertLogIDVar(Index)) ; -- Silent Counted Alert
end if ;
else
-- Affirmation passed, PASSED flag increments AffirmCount
Log(AlertLogIDVar(Index), WriteBuf.all, PASSED) ;
end if ;
deallocate(WriteBuf) ;
end if ;
end procedure LocalCheck ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Check") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Check (ActualData : ActualType) is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
end procedure Check ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Check (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Check") ;
LocalCheck(Index, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Check (
------------------------------------------------------------
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, Tag, "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Check (ActualData : ActualType) return boolean is
------------------------------------------------------------
variable FoundError : boolean ;
begin
LocalPop(FirstIndexVar, "", "Check") ;
LocalCheck(FirstIndexVar, ActualData, FoundError) ;
return not FoundError ;
end function Check ;
------------------------------------------------------------
-- Scoreboard Store. Index. Tag.
impure function CheckExpected (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
variable FoundError : boolean ;
begin
if LocalOutOfRange(Index, "Function Check") then
return FALSE ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Check") ;
LocalCheck(Index, ExpectedData, FoundError, ExpectedInFIFO => FALSE) ;
return not FoundError ;
end function CheckExpected ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, Tag, "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Pop (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
begin
if LocalOutOfRange(Index, "Pop") then
return ; -- error reporting in LocalOutOfRange
end if ;
LocalPop(Index, "", "Pop") ;
Item := PopListPointer(Index).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Pop (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Pop (variable Item : out ExpectedType) is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
Item := PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end procedure Pop ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Pop (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, Tag, "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Pop (Index : integer) return ExpectedType is
------------------------------------------------------------
begin
if LocalOutOfRange(Index, "Pop") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
LocalPop(Index, "", "Pop") ;
return PopListPointer(Index).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Pop (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
begin
LocalPop(FirstIndexVar, Tag, "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Pop return ExpectedType is
------------------------------------------------------------
begin
LocalPop(FirstIndexVar, "", "Pop") ;
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end function Pop ;
------------------------------------------------------------
-- Local Only similar to LocalPop
-- Returns a pointer to the highest element matching Tag
impure function LocalPeek (Index : integer ; Tag : string) return ListPointerType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
--!! LocalPeek does this, but so do each of the indexed calls
--!! if LocalOutOfRange(Index, "Peek") then
--!! return NULL ; -- error reporting in LocalOutOfRange
--!! end if ;
if HeadPointer(Index) = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Empty during Peek", FAILURE) ;
return NULL ;
end if ;
-- Descend to find Tag field and extract
CurPtr := HeadPointer(Index) ;
if CurPtr.TagPtr.all = Tag then
-- Non-tagged scoreboards find this one.
return CurPtr ;
else
loop
if CurPtr.NextPtr = NULL then
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
Alert(AlertLogIDVar(Index), GetName & " Peek, tag: " & Tag & " not found", FAILURE) ;
return NULL ;
elsif CurPtr.NextPtr.TagPtr.all = Tag then
return CurPtr ;
else
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end if ;
end function LocalPeek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
procedure Peek (
------------------------------------------------------------
constant Index : in integer ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
procedure Peek (
------------------------------------------------------------
constant Tag : in string ;
variable Item : out ExpectedType
) is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Peek (variable Item : out ExpectedType) is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
Item := CurPtr.ExpectedPtr.all ;
end if ;
end procedure Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Peek (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Peek (Index : integer) return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Peek") then
-- error reporting in LocalOutOfRange
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
CurPtr := LocalPeek(Index, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Peek (
------------------------------------------------------------
constant Tag : in string
) return ExpectedType is
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, Tag) ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Peek return ExpectedType is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := LocalPeek(FirstIndexVar, "") ;
if CurPtr /= NULL then
return CurPtr.ExpectedPtr.all ;
else
-- Already issued failure, continuing for debug only
return PopListPointer(FirstIndexVar).ExpectedPtr.all ;
end if ;
end function Peek ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
impure function Empty (Index : integer; Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
CurPtr := HeadPointer(Index) ;
while CurPtr /= NULL loop
if CurPtr.TagPtr.all = Tag then
return FALSE ; -- Found Tag
end if ;
CurPtr := CurPtr.NextPtr ;
end loop ;
return TRUE ; -- Tag not found
end function Empty ;
------------------------------------------------------------
-- Array of Scoreboards, no tag
impure function Empty (Index : integer) return boolean is
------------------------------------------------------------
begin
return HeadPointer(Index) = NULL ;
end function Empty ;
------------------------------------------------------------
-- Simple Tagged Scoreboard
impure function Empty (Tag : String) return boolean is
------------------------------------------------------------
variable CurPtr : ListPointerType ;
begin
return Empty(FirstIndexVar, Tag) ;
end function Empty ;
------------------------------------------------------------
-- Simple Scoreboard, no tag
impure function Empty return boolean is
------------------------------------------------------------
begin
return HeadPointer(FirstIndexVar) = NULL ;
end function Empty ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
Index : integer ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
variable EmptyError : Boolean ;
variable WriteBuf : line ;
begin
if AlertLogIDVar(Index) = OSVVM_SCOREBOARD_ALERTLOG_ID then
write(WriteBuf, GetName(DefaultName => "Scoreboard")) ;
else
write(WriteBuf, GetName(DefaultName => "")) ;
end if ;
if ArrayLengthVar > 1 then
if WriteBuf.all /= "" then
swrite(WriteBuf, " ") ;
end if ;
write(WriteBuf, "Index(" & to_string(Index) & "), ") ;
else
if WriteBuf.all /= "" then
swrite(WriteBuf, ", ") ;
end if ;
end if ;
if FinishEmpty then
AffirmIf(AlertLogIDVar(Index), Empty(Index), WriteBuf.all & "Checking Empty: " & to_string(Empty(Index)) &
" FinishEmpty: " & to_string(FinishEmpty)) ;
if not Empty(Index) then
-- Increment internal count on FinishEmpty Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
end if ;
AffirmIf(AlertLogIDVar(Index), CheckCountVar(Index) >= FinishCheckCount, WriteBuf.all &
"Checking CheckCount: " & to_string(CheckCountVar(Index)) &
" >= Expected: " & to_string(FinishCheckCount)) ;
if not (CheckCountVar(Index) >= FinishCheckCount) then
-- Increment internal count on FinishCheckCount Error
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
end if ;
deallocate(WriteBuf) ;
end procedure CheckFinish ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
for AlertLogID in AlertLogIDVar'range loop
CheckFinish(AlertLogID, FinishCheckCount, FinishEmpty) ;
end loop ;
end procedure CheckFinish ;
------------------------------------------------------------
impure function GetErrorCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ErrCntVar(Index) ;
end function GetErrorCount ;
------------------------------------------------------------
impure function GetErrorCount return integer is
------------------------------------------------------------
variable TotalErrorCount : integer := 0 ;
begin
for Index in AlertLogIDVar'range loop
TotalErrorCount := TotalErrorCount + GetErrorCount(Index) ;
end loop ;
return TotalErrorCount ;
end function GetErrorCount ;
------------------------------------------------------------
procedure IncErrorCount (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
IncAlertCount(AlertLogIDVar(Index), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure IncErrorCount is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := ErrCntVar(FirstIndexVar) + 1 ;
IncAlertCount(AlertLogIDVar(FirstIndexVar), ERROR) ;
end IncErrorCount ;
------------------------------------------------------------
procedure SetErrorCountZero (Index : integer) is
------------------------------------------------------------
begin
ErrCntVar(Index) := 0;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetErrorCountZero is
------------------------------------------------------------
begin
ErrCntVar(FirstIndexVar) := 0 ;
end procedure SetErrorCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero (Index : integer) is
------------------------------------------------------------
begin
CheckCountVar(Index) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
procedure SetCheckCountZero is
------------------------------------------------------------
begin
CheckCountVar(FirstIndexVar) := 0;
end procedure SetCheckCountZero ;
------------------------------------------------------------
impure function GetItemCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetItemCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetItemCount ;
------------------------------------------------------------
impure function GetPushCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPushCount return integer is
------------------------------------------------------------
begin
return ItemNumberVar(FirstIndexVar) ;
end function GetPushCount ;
------------------------------------------------------------
impure function GetPopCount (Index : integer) return integer is
------------------------------------------------------------
begin
return PopCountVar(Index) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetPopCount return integer is
------------------------------------------------------------
begin
return PopCountVar(FirstIndexVar) ;
end function GetPopCount ;
------------------------------------------------------------
impure function GetFifoCount (Index : integer) return integer is
------------------------------------------------------------
begin
return ItemNumberVar(Index) - PopCountVar(Index) - DropCountVar(Index) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetFifoCount return integer is
------------------------------------------------------------
begin
return GetFifoCount(FirstIndexVar) ;
end function GetFifoCount ;
------------------------------------------------------------
impure function GetCheckCount (Index : integer) return integer is
------------------------------------------------------------
begin
return CheckCountVar(Index) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetCheckCount return integer is
------------------------------------------------------------
begin
return CheckCountVar(FirstIndexVar) ;
end function GetCheckCount ;
------------------------------------------------------------
impure function GetDropCount (Index : integer) return integer is
------------------------------------------------------------
begin
return DropCountVar(Index) ;
end function GetDropCount ;
------------------------------------------------------------
impure function GetDropCount return integer is
------------------------------------------------------------
begin
return DropCountVar(FirstIndexVar) ;
end function GetDropCount ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
Index : integer ;
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
Alert(AlertLogIDVar(Index), "OSVVM.ScoreboardGenericPkg.SetFinish: Deprecated and removed. See CheckFinish", ERROR) ;
end procedure SetFinish ;
------------------------------------------------------------
procedure SetFinish (
------------------------------------------------------------
FCheckCount : integer ;
FEmpty : boolean := TRUE;
FStatus : boolean := TRUE
) is
begin
SetFinish(FirstIndexVar, FCheckCount, FEmpty, FStatus) ;
end procedure SetFinish ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Find Element with Matching Tag and ActualData
-- Returns integer'left if no match found
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return integer'left ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Failed to find it
ErrCntVar(Index) := ErrCntVar(Index) + 1 ;
if Tag /= "" then
Alert(AlertLogIDVar(Index),
GetName & " Did not find Tag: " & Tag & " and Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
else
Alert(AlertLogIDVar(Index),
GetName & " Did not find Actual Data: " & actual_to_string(ActualData),
FAILURE ) ;
end if ;
return integer'left ;
elsif CurPtr.TagPtr.all = Tag and
Match(ActualData, CurPtr.ExpectedPtr.all) then
-- Found it. Return Index.
return CurPtr.ItemNumber ;
else -- Descend
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end function Find ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Index : in integer ;
constant ActualData : in ActualType
) return integer is
begin
return Find(Index, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Simple Scoreboard
-- Find Element with Matching ActualData
impure function Find (
------------------------------------------------------------
constant ActualData : in ActualType
) return integer is
begin
return Find(FirstIndexVar, "", ActualData) ;
end function Find ;
------------------------------------------------------------
-- Array of Tagged Scoreboards
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
variable CurPtr, RemovePtr, LastPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
LastPtr := NULL ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif CurPtr.TagPtr.all = Tag then
if ItemNumber >= CurPtr.ItemNumber then
-- remove it
RemovePtr := CurPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := LastPtr ;
end if ;
if CurPtr = HeadPointer(Index) then
HeadPointer(Index) := CurPtr.NextPtr ;
else -- if LastPtr /= NULL then
LastPtr.NextPtr := LastPtr.NextPtr.NextPtr ;
end if ;
CurPtr := CurPtr.NextPtr ;
-- LastPtr := LastPtr ; -- no change
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(RemovePtr.TagPtr) ;
deallocate(RemovePtr.ExpectedPtr) ;
deallocate(RemovePtr) ;
else
-- Done
return ;
end if ;
else
-- Descend
LastPtr := CurPtr ;
CurPtr := CurPtr.NextPtr ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Tagged Scoreboard
-- Flush Remove elements with tag whose itemNumber is <= ItemNumber parameter
procedure Flush (
------------------------------------------------------------
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Array of Simple Scoreboards
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant Index : in integer ;
constant ItemNumber : in integer
) is
variable CurPtr : ListPointerType ;
begin
if LocalOutOfRange(Index, "Find") then
return ; -- error reporting in LocalOutOfRange
end if ;
CurPtr := HeadPointer(Index) ;
loop
if CurPtr = NULL then
-- Done
return ;
elsif ItemNumber >= CurPtr.ItemNumber then
-- Descend, Check Tail, Deallocate
HeadPointer(Index) := HeadPointer(Index).NextPtr ;
if CurPtr = TailPointer(Index) then
TailPointer(Index) := NULL ;
end if ;
DropCountVar(Index) := DropCountVar(Index) + 1 ;
deallocate(CurPtr.TagPtr) ;
deallocate(CurPtr.ExpectedPtr) ;
deallocate(CurPtr) ;
CurPtr := HeadPointer(Index) ;
else
-- Done
return ;
end if ;
end loop ;
end procedure Flush ;
------------------------------------------------------------
-- Simple Scoreboard
-- Flush - Remove Elements upto and including the one with ItemNumber
procedure Flush (
------------------------------------------------------------
constant ItemNumber : in integer
) is
begin
Flush(FirstIndexVar, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
impure function GotScoreboards return boolean is
------------------------------------------------------------
begin
return CalledNewID ;
end function GotScoreboards ;
------------------------------------------------------------
-- pt local
procedure WriteScoreboardYaml (Index : integer; file CovYamlFile : text) is
------------------------------------------------------------
variable buf : line ;
constant NAME_PREFIX : string := " " ;
begin
write(buf, NAME_PREFIX & "- Name: " & '"' & string'(GetAlertLogName(AlertLogIDVar(Index))) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemCount: " & '"' & to_string(ItemNumberVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ErrorCount: " & '"' & to_string(ErrCntVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsChecked: " & '"' & to_string(CheckCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsPopped: " & '"' & to_string(PopCountVar(Index)) & '"' & LF) ;
write(buf, NAME_PREFIX & " ItemsDropped: " & '"' & to_string(DropCountVar(Index)) & '"' & LF) ;
writeline(CovYamlFile, buf) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
------------------------------------------------------------
constant RESOLVED_FILE_NAME : string := IfElse(FileName = "", REPORTS_DIRECTORY & GetAlertLogName & "_sb.yml", FileName) ;
file SbYamlFile : text open OpenKind is RESOLVED_FILE_NAME ;
variable buf : line ;
begin
if AlertLogIDVar = NULL or AlertLogIDVar'length <= 0 then
Alert("Scoreboard.WriteScoreboardYaml: no scoreboards defined ", ERROR) ;
return ;
end if ;
swrite(buf, "Version: 1.0" & LF) ;
swrite(buf, "TestCase: " & '"' & GetAlertLogName & '"' & LF) ;
swrite(buf, "Scoreboards: ") ;
writeline(SbYamlFile, buf) ;
if CalledNewID then
-- Used by singleton
for i in 1 to NumItems loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
else
-- Used by PT method, but not singleton
for i in AlertLogIDVar'range loop
WriteScoreboardYaml(i, SbYamlFile) ;
end loop ;
end if ;
file_close(SbYamlFile) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
------------------------------------------------------------
-- Remaining Deprecated.
------------------------------------------------------------
------------------------------------------------------------
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
-- Use TranscriptPkg.TranscriptOpen
procedure FileOpen (FileName : string; OpenKind : File_Open_Kind ) is
------------------------------------------------------------
begin
-- WriteFileInit := TRUE ;
-- file_open( WriteFile , FileName , OpenKind );
TranscriptOpen(FileName, OpenKind) ;
end procedure FileOpen ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure PutExpectedData (ExpectedData : ExpectedType) is
------------------------------------------------------------
begin
Push(ExpectedData) ;
end procedure PutExpectedData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure CheckActualData (ActualData : ActualType) is
------------------------------------------------------------
begin
Check(ActualData) ;
end procedure CheckActualData ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetItemNumber return integer is
------------------------------------------------------------
begin
return GetItemCount(FirstIndexVar) ;
end GetItemNumber ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
procedure SetMessage (MessageIn : String) is
------------------------------------------------------------
begin
-- deallocate(Message) ;
-- Message := new string'(MessageIn) ;
SetName(MessageIn) ;
end procedure SetMessage ;
------------------------------------------------------------
-- Deprecated. Maintained for backward compatibility.
impure function GetMessage return string is
------------------------------------------------------------
begin
-- return Message.all ;
return GetName("Scoreboard") ;
end function GetMessage ;
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: 1 to Size
--!! impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, (1, Size) , ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Vector: X(X'Left) to X(X'Right)
--!! impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: 1 to X, 1 to Y
--!! impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
--!!
--!! ------------------------------------------------------------
--!! -- Deprecated Call to NewID, refactored to call new version of NewID
--!! -- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
--!! impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
--!! ------------------------------------------------------------
--!! variable ReportMode : AlertLogReportModeType ;
--!! begin
--!! ReportMode := ENABLED when not DoNotReport else DISABLED ;
--!! return NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
--!! end function NewID ;
end protected body ScoreBoardPType ;
shared variable ScoreboardStore : ScoreBoardPType ;
------------------------------------------------------------
-- Used by Scoreboard Store
impure function NewID (
Name : String ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (
Name : String ;
Size : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, Size, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (
Name : String ;
X : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIDArrayType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (
Name : String ;
X, Y : positive ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (
Name : String ;
X, Y : integer_vector ;
ParentID : AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
ReportMode : AlertLogReportModeType := ENABLED ;
Search : NameSearchType := NAME_AND_PARENT_ELSE_PRIVATE ;
PrintParent : AlertLogPrintParentType := PRINT_NAME_AND_PARENT
) return ScoreboardIdMatrixType is
------------------------------------------------------------
begin
return ScoreboardStore.NewID(Name, X, Y, ParentID, ReportMode, Search, PrintParent) ;
end function NewID ;
------------------------------------------------------------
-- Push items into the scoreboard/FIFO
------------------------------------------------------------
-- Simple Scoreboard, no tag
procedure Push (
------------------------------------------------------------
constant ID : in ScoreboardIDType ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Item) ;
end procedure Push ;
-- Simple Tagged Scoreboard
procedure Push (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant Item : in ExpectedType
) is
begin
ScoreboardStore.Push(ID.ID, Tag, Item) ;
end procedure Push ;
------------------------------------------------------------
-- Check received item with item in the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, ActualData) ;
end procedure Check ;
-- Simple Tagged Scoreboard
procedure Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) is
begin
ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end procedure Check ;
-- Simple Scoreboard, no tag
impure function Check (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, ActualData) ;
end function Check ;
-- Simple Tagged Scoreboard
impure function Check (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ActualData : in ActualType
) return boolean is
begin
return ScoreboardStore.Check(ID.ID, Tag, ActualData) ;
end function Check ;
-------------
----------------------------------------------
-- Simple Scoreboard, no tag
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end procedure CheckExpected ;
-- Simple Tagged Scoreboard
procedure CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) is
variable Passed : boolean ;
begin
Passed := ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end procedure CheckExpected ;
-- Simple Scoreboard, no tag
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, "", ExpectedData) ;
end function CheckExpected ;
-- Simple Tagged Scoreboard
impure function CheckExpected (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ExpectedData : in ActualType
) return boolean is
begin
return ScoreboardStore.CheckExpected(ID.ID, Tag, ExpectedData) ;
end function CheckExpected ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Simple Scoreboard, no tag
procedure Pop (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Item) ;
end procedure Pop ;
-- Simple Tagged Scoreboard
procedure Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Pop(ID.ID, Tag, Item) ;
end procedure Pop ;
------------------------------------------------------------
-- Pop the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Simple Scoreboard, no tag
impure function Pop (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID) ;
end function Pop ;
-- Simple Tagged Scoreboard
impure function Pop (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
return ScoreboardStore.Pop(ID.ID, Tag) ;
end function Pop ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Simple Tagged Scoreboard
procedure Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Tag, Item) ;
end procedure Peek ;
-- Simple Scoreboard, no tag
procedure Peek (
constant ID : in ScoreboardIDType ;
variable Item : out ExpectedType
) is
begin
ScoreboardStore.Peek(ID.ID, Item) ;
end procedure Peek ;
------------------------------------------------------------
-- Peek at the top item (FIFO) from the scoreboard/FIFO
-- Caution: this did not work in older simulators (@2013)
-- Tagged Scoreboards
impure function Peek (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return ExpectedType is
begin
-- return ScoreboardStore.Peek(Tag) ;
-- log("Issues compiling return later");
return ScoreboardStore.Peek(Index => ID.ID, Tag => Tag) ;
end function Peek ;
-- Simple Scoreboard
impure function Peek (
constant ID : in ScoreboardIDType
) return ExpectedType is
begin
return ScoreboardStore.Peek(Index => ID.ID) ;
end function Peek ;
------------------------------------------------------------
-- ScoreboardEmpty - check to see if scoreboard is empty
-- Simple
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function ScoreboardEmpty ;
-- Tagged
impure function ScoreboardEmpty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function ScoreboardEmpty ;
impure function Empty (
constant ID : in ScoreboardIDType
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID) ;
end function Empty ;
-- Tagged
impure function Empty (
constant ID : in ScoreboardIDType ;
constant Tag : in string
) return boolean is
begin
return ScoreboardStore.Empty(ID.ID, Tag) ;
end function Empty ;
--!! ------------------------------------------------------------
--!! -- SetAlertLogID - associate an AlertLogID with a scoreboard to allow integrated error reporting
--!! procedure SetAlertLogID(
--!! constant ID : in ScoreboardIDType ;
--!! constant Name : in string ;
--!! constant ParentID : in AlertLogIDType := OSVVM_SCOREBOARD_ALERTLOG_ID ;
--!! constant CreateHierarchy : in Boolean := TRUE ;
--!! constant DoNotReport : in Boolean := FALSE
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, Name, ParentID, CreateHierarchy, DoNotReport) ;
--!! end procedure SetAlertLogID ;
--!!
--!! -- Use when an AlertLogID is used by multiple items (Model or other Scoreboards). See also AlertLogPkg.GetAlertLogID
--!! procedure SetAlertLogID (
--!! constant ID : in ScoreboardIDType ;
--!! constant A : AlertLogIDType
--!! ) is
--!! begin
--!! ScoreboardStore.SetAlertLogID(ID.ID, A) ;
--!! end procedure SetAlertLogID ;
impure function GetAlertLogID (
constant ID : in ScoreboardIDType
) return AlertLogIDType is
begin
return ScoreboardStore.GetAlertLogID(ID.ID) ;
end function GetAlertLogID ;
------------------------------------------------------------
-- Scoreboard Introspection
-- Number of items put into scoreboard
impure function GetItemCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetItemCount(ID.ID) ;
end function GetItemCount ;
impure function GetPushCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPushCount(ID.ID) ;
end function GetPushCount ;
-- Number of items removed from scoreboard by pop or check
impure function GetPopCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetPopCount(ID.ID) ;
end function GetPopCount ;
-- Number of items currently in the scoreboard (= PushCount - PopCount - DropCount)
impure function GetFifoCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetFifoCount(ID.ID) ;
end function GetFifoCount ;
-- Number of items checked by scoreboard
impure function GetCheckCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetCheckCount(ID.ID) ;
end function GetCheckCount ;
-- Number of items dropped by scoreboard. See Find/Flush
impure function GetDropCount (
constant ID : in ScoreboardIDType
) return integer is
begin
return ScoreboardStore.GetDropCount(ID.ID) ;
end function GetDropCount ;
------------------------------------------------------------
-- Find - Returns the ItemNumber for a value and tag (if applicable) in a scoreboard.
-- Find returns integer'left if no match found
-- Also See Flush. Flush will drop items up through the ItemNumber
-- Simple Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, ActualData) ;
end function Find ;
-- Tagged Scoreboard
impure function Find (
constant ID : in ScoreboardIDType ;
constant Tag : in string;
constant ActualData : in ActualType
) return integer is
begin
return ScoreboardStore.Find(ID.ID, Tag, ActualData) ;
end function Find ;
------------------------------------------------------------
-- Flush - Remove elements in the scoreboard upto and including the one with ItemNumber
-- See Find to identify an ItemNumber of a particular value and tag (if applicable)
-- Simple Scoreboards
procedure Flush (
constant ID : in ScoreboardIDType ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, ItemNumber) ;
end procedure Flush ;
-- Tagged Scoreboards - only removes items that also match the tag
procedure Flush (
constant ID : in ScoreboardIDType ;
constant Tag : in string ;
constant ItemNumber : in integer
) is
begin
ScoreboardStore.Flush(ID.ID, Tag, ItemNumber) ;
end procedure Flush ;
------------------------------------------------------------
-- Scoreboard YAML Reports
impure function GotScoreboards return boolean is
begin
return ScoreboardStore.GotScoreboards ;
end function GotScoreboards ;
------------------------------------------------------------
procedure WriteScoreboardYaml (FileName : string := ""; OpenKind : File_Open_Kind := WRITE_MODE) is
begin
ScoreboardStore.WriteScoreboardYaml(FileName, OpenKind) ;
end procedure WriteScoreboardYaml ;
------------------------------------------------------------
-- Generally these are not required. When a simulation ends and
-- another simulation is started, a simulator will release all allocated items.
procedure Deallocate (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Deallocate ;
end procedure Deallocate ;
procedure Initialize (
constant ID : in ScoreboardIDType
) is
begin
ScoreboardStore.Initialize ;
end procedure Initialize ;
------------------------------------------------------------
-- Get error count
-- Deprecated, replaced by usage of Alerts
-- AlertFLow: Instead use AlertLogPkg.ReportAlerts or AlertLogPkg.GetAlertCount
-- Not AlertFlow: use GetErrorCount to get total error count
-- Scoreboards, with or without tag
impure function GetErrorCount(
constant ID : in ScoreboardIDType
) return integer is
begin
return GetAlertCount(ScoreboardStore.GetAlertLogID(ID.ID)) ;
end function GetErrorCount ;
------------------------------------------------------------
procedure CheckFinish (
------------------------------------------------------------
ID : ScoreboardIDType ;
FinishCheckCount : integer ;
FinishEmpty : boolean
) is
begin
ScoreboardStore.CheckFinish(ID.ID, FinishCheckCount, FinishEmpty) ;
end procedure CheckFinish ;
------------------------------------------------------------
-- SetReportMode
-- Not AlertFlow
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(PASSED, FALSE)
-- REPORT_NONE: Deprecated, do not use.
-- AlertFlow:
-- REPORT_ALL: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, TRUE)
-- REPORT_ERROR: Replaced by AlertLogPkg.SetLogEnable(AlertLogID, PASSED, FALSE)
-- REPORT_NONE: Replaced by AlertLogPkg.SetAlertEnable(AlertLogID, ERROR, FALSE)
procedure SetReportMode (
constant ID : in ScoreboardIDType ;
constant ReportModeIn : in ScoreboardReportType
) is
begin
-- ScoreboardStore.SetReportMode(ID.ID, ReportModeIn) ;
ScoreboardStore.SetReportMode(ReportModeIn) ;
end procedure SetReportMode ;
impure function GetReportMode (
constant ID : in ScoreboardIDType
) return ScoreboardReportType is
begin
-- return ScoreboardStore.GetReportMode(ID.ID) ;
return ScoreboardStore.GetReportMode ;
end function GetReportMode ;
--==========================================================
--!! Deprecated Subprograms
--==========================================================
------------------------------------------------------------
-- Deprecated interface to NewID
impure function NewID (Name : String ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: 1 to Size
impure function NewID (Name : String ; Size : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, Size, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Vector: X(X'Left) to X(X'Right)
impure function NewID (Name : String ; X : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIDArrayType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: 1 to X, 1 to Y
impure function NewID (Name : String ; X, Y : positive ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
------------------------------------------------------------
-- Matrix: X(X'Left) to X(X'Right), Y(Y'Left) to Y(Y'Right)
impure function NewID (Name : String ; X, Y : integer_vector ; ParentAlertLogID : AlertLogIDType; DoNotReport : Boolean) return ScoreboardIdMatrixType is
------------------------------------------------------------
variable ReportMode : AlertLogReportModeType ;
begin
ReportMode := ENABLED when not DoNotReport else DISABLED ;
return ScoreboardStore.NewID(Name, X, Y, ParentAlertLogID, ReportMode => ReportMode) ;
end function NewID ;
end ScoreboardGenericPkg ; | artistic-2.0 | 9e0c92888b6aabed3eb77b3e8b35c874 | 0.542583 | 5.301279 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_12/Lab_12_3/nxor.vhd | 1 | 572 | Library IEEE;
use IEEE.std_logic_1164.all;
entity nxor is
port( A: in std_logic_vector (2 downto 0);
Q: out std_logic_vector (0 downto 0));
end entity nxor;
architecture Behave of nxor is
begin
process (A)
begin
case A is
when "000" => Q <= "0";
when "001" => Q <= "1";
when "010" => Q <= "1";
when "011" => Q <= "0";
when "100" => Q <= "1";
when "101" => Q <= "0";
when "110" => Q <= "0";
when "111" => Q <= "1";
when others => Q <= "0";
end case;
end process;
end Behave; | gpl-2.0 | fee64d789ecb48116877e0ba00a0a75f | 0.479021 | 2.736842 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/simulation/wr_fifo32to256_synth.vhd | 1 | 11,294 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.wr_fifo32to256_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY wr_fifo32to256_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF wr_fifo32to256_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(13-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: wr_fifo32to256_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 256,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: wr_fifo32to256_dverif
GENERIC MAP (
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: wr_fifo32to256_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 256,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 13,
C_RD_PNTR_WIDTH => 10,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
wr_fifo32to256_inst : wr_fifo32to256_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | 940df89c8b745b44f93d9f3e8fc17bc8 | 0.46113 | 3.944813 | false | false | false | false |
peteut/nvc | test/regress/issue217.vhd | 5 | 863 | entity SUB is
port (
USER_I : in bit_vector(1 downto 0);
RESULT : out boolean
);
end SUB;
architecture MODEL of SUB is
procedure match(user:in bit_vector; ok: out boolean) is begin
ok := (user(USER_I'range) = USER_I);
end procedure;
begin
process(USER_I)
variable ok : boolean;
constant user : bit_vector(1 downto 0) := "01";
begin
match(user, ok);
RESULT <= ok;
end process;
end MODEL;
entity issue217 is
end issue217;
architecture MODEL of issue217 is
signal USER : bit_vector(1 downto 0);
signal OK : boolean;
begin
U: entity WORK.SUB port map (
USER_I => USER,
RESULT => OK
);
user <= "01";
process is
begin
assert not ok;
wait on ok;
assert ok;
wait;
end process;
end MODEL;
| gpl-3.0 | 640b15ea36ed5fdc96d3c4d5f382348f | 0.559676 | 3.688034 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/simulation/rd_fifo_256to64_synth.vhd | 1 | 11,411 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.rd_fifo_256to64_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rd_fifo_256to64_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF rd_fifo_256to64_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL wr_data_count : STD_LOGIC_VECTOR(10-1 DOWNTO 0);
SIGNAL rd_data_count : STD_LOGIC_VECTOR(12-1 DOWNTO 0);
SIGNAL rst : STD_LOGIC;
SIGNAL prog_full : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(256-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(64-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_i <= WR_CLK;
rd_clk_i <= RD_CLK;
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: rd_fifo_256to64_dgen
GENERIC MAP (
C_DIN_WIDTH => 256,
C_DOUT_WIDTH => 64,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: rd_fifo_256to64_dverif
GENERIC MAP (
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 256,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: rd_fifo_256to64_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 64,
C_DIN_WIDTH => 256,
C_WR_PNTR_WIDTH => 10,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
rd_fifo_256to64_inst : rd_fifo_256to64_exdes
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
| gpl-2.0 | d74155122f2e350d1796cb2f774d4323 | 0.459732 | 3.942985 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/cpu_xadc_wiz_0_0_axi_xadc.vhd | 1 | 45,959 | -------------------------------------------------------------------------------
-- cpu_xadc_wiz_0_0_axi_xadc.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010, 2013 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : cpu_xadc_wiz_0_0_axi_xadc.vhd
-- Version : v3.0
-- Description : XADC macro with AXI bus interface
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_xadc.vhd
-- -cpu_xadc_wiz_0_0_xadc_core_drp.vhd
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.conv_std_logic_vector;
use IEEE.std_logic_arith.unsigned;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_misc.and_reduce;
use IEEE.std_logic_misc.or_reduce;
library work;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
use work.cpu_xadc_wiz_0_0_soft_reset;
use work.cpu_xadc_wiz_0_0_ipif_pkg.calc_num_ce;
use work.cpu_xadc_wiz_0_0_ipif_pkg.INTEGER_ARRAY_TYPE;
use work.cpu_xadc_wiz_0_0_ipif_pkg.SLV64_ARRAY_TYPE;
use work.cpu_xadc_wiz_0_0_ipif_pkg.INTR_POS_EDGE_DETECT;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
--------------------
-- AXI LITE Generics
--------------------
-- C_BASEADDR -- Base Address
-- C_HIGHADDR -- high address
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_FAMILY -- Target FPGA family, Virtex 6 only
-- C_INCLUDE_INTR -- inclusion of interrupt
-- C_SIM_MONITOR_FILE -- simulation file
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-------------------------------------------------------------------------------
-- Note: the unused signals in the port name lists are not listed here.
-------------------------------------------------------------------------------
-- SYSMON EXTERNAL INTERFACE -- INPUT Signals
-------------------------------------------------------------------------------
-- VAUXN -- Sixteen auxiliary analog input pairs
-- VAUXP -- low bandwidth differential analog inputs
-- CONVST -- Conversion start signal for event-driven sampling mode
-------------------------------------------------------------------------------
-- SYSMON EXTERNAL INTERFACE -- OUTPUT Signals
-------------------------------------------------------------------------------
-- ip2intc_irpt -- Interrupt to processor
-- alarm_out -- SYSMON alarm output signals of the hard macro
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_axi_xadc is
generic
(
-----------------------------------------
-- C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
-- C_HIGHADDR : std_logic_vector := X"0000_0000";
-----------------------------------------
-- AXI slave single block generics
C_INSTANCE : string := "cpu_xadc_wiz_0_0_axi_xadc";
C_FAMILY : string := "virtex7";
C_S_AXI_ADDR_WIDTH : integer range 2 to 32 := 11;
C_S_AXI_DATA_WIDTH : integer range 32 to 128 := 32;
-----------------------------------------
-- SYSMON Generics
C_INCLUDE_INTR : integer range 0 to 1 := 1;
C_SIM_MONITOR_FILE : string := "design.txt"
);
port
(
-- System interface
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
-- AXI Write address channel signals
s_axi_awaddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- AXI Write data channel signals
s_axi_wdata : in std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_wstrb : in std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- AXI Write response channel signals
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- AXI Read address channel signals
s_axi_araddr : in std_logic_vector((C_S_AXI_ADDR_WIDTH-1) downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- AXI Read address channel signals
s_axi_rdata : out std_logic_vector((C_S_AXI_DATA_WIDTH-1) downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Input to the system from the axi_xadc core
ip2intc_irpt : out std_logic;
-- XADC External interface signals
-- Conversion start control signal for Event driven mode
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
ot_out : out STD_LOGIC;
alarm_out : out STD_LOGIC_VECTOR (7 downto 0); -- OR'ed output of all the Alarms
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
-------------------------------------------------------------------------------
-- Attributes
-------------------------------------------------------------------------------
-- Fan-Out attributes for XST
ATTRIBUTE MAX_FANOUT : string;
ATTRIBUTE MAX_FANOUT of s_axi_aclk : signal is "10000";
ATTRIBUTE MAX_FANOUT of s_axi_aresetn : signal is "10000";
-----------------------------------------------------------------
-- Start of PSFUtil MPD attributes
-----------------------------------------------------------------
ATTRIBUTE HDL : string;
ATTRIBUTE HDL of cpu_xadc_wiz_0_0_axi_xadc : entity is "VHDL";
ATTRIBUTE IPTYPE : string;
ATTRIBUTE IPTYPE of cpu_xadc_wiz_0_0_axi_xadc : entity is "PERIPHERAL";
ATTRIBUTE IP_GROUP : string;
ATTRIBUTE IP_GROUP of cpu_xadc_wiz_0_0_axi_xadc : entity is "LOGICORE";
ATTRIBUTE SIGIS : string;
ATTRIBUTE SIGIS of s_axi_aclk : signal is "Clk";
ATTRIBUTE SIGIS of s_axi_aresetn : signal is "Rst";
ATTRIBUTE SIGIS of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
-----------------------------------------------------------------
-- end of PSFUtil MPD attributes
-----------------------------------------------------------------
end entity cpu_xadc_wiz_0_0_axi_xadc;
-------------------------------------------------------------------------------
-- Architecture Section
-------------------------------------------------------------------------------
architecture imp of cpu_xadc_wiz_0_0_axi_xadc is
component cpu_xadc_wiz_0_0_xadc_core_drp
generic
(
----------------
C_S_AXI_ADDR_WIDTH : integer;
C_S_AXI_DATA_WIDTH : integer;
C_FAMILY : string;
----------------
CE_NUMBERS : integer;
IP_INTR_NUM : integer;
C_SIM_MONITOR_FILE : string ;
----------------
MUX_ADDR_NO : integer
);
port
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk : in std_logic;
Bus2IP_Rst : in std_logic;
-- Bus 2 IP IPIC interface
Bus2IP_RdCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_WrCE : in std_logic_vector(0 to CE_NUMBERS-1);
Bus2IP_Addr : in std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
Bus2IP_Data : in std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- IP 2 Bus IPIC interface
Sysmon_IP2Bus_Data : out std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
Sysmon_IP2Bus_WrAck : out std_logic;
Sysmon_IP2Bus_RdAck : out std_logic;
---------------- interrupt interface with the system -----------
Interrupt_status : out std_logic_vector(0 to IP_INTR_NUM-1);
---------------- sysmon macro interface -------------------
busy_out : out STD_LOGIC; -- ADC Busy signal
channel_out : out STD_LOGIC_VECTOR (4 downto 0); -- Channel Selection Outputs
eoc_out : out STD_LOGIC; -- End of Conversion Signal
eos_out : out STD_LOGIC; -- End of Sequence Signal
ot_out : out STD_LOGIC;
alarm_out : out STD_LOGIC_VECTOR (7 downto 0);
vp_in : in STD_LOGIC; -- Dedicated Analog Input Pair
vn_in : in STD_LOGIC
);
end component;
-------------------------------------------------------------------------------
-- Function Declarations starts
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function: add_intr_ard_addr_range_array
-------------------------------------------------------------------------------
-- Add the interrupt base and high address to ARD_ADDR_RANGE_ARRAY, if
-- C_INCLUDE_INTR is = 1
-------------------------------------------------------------------------------
function add_intr_ard_addr_range_array
(include_intr : integer;
USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE;
INTR_USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE
)
return SLV64_ARRAY_TYPE is
begin
if include_intr = 1 then
return INTR_USER_ARD_ADDR_RANGE_ARRAY;
else
return USER_ARD_ADDR_RANGE_ARRAY;
end if;
end function add_intr_ard_addr_range_array;
-------------------------------------------------------------------------------
-- Function: add_intr_ce_range_array
-------------------------------------------------------------------------------
-- This function is used to add the 16 interrupts in the NUM_CE range array, if
-- C_INCLUDE_INTR is = 1
-------------------------------------------------------------------------------
function add_intr_ce_range_array
(include_intr : integer;
USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE;
INTR_USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE
)
return INTEGER_ARRAY_TYPE is
begin
if include_intr = 1 then
return INTR_USER_ARD_NUM_CE_ARRAY;
else
return USER_ARD_NUM_CE_ARRAY;
end if;
end function add_intr_ce_range_array;
-------------------------------------------------------------------------------
-- Function Declaration ends
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Type Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Constant Declaration Starts
-------------------------------------------------------------------------------
-- AXI lite parameters
constant C_BASEADDR : std_logic_vector := X"0000_0000";
--constant C_BASEADDR : std_logic_vector := X"FFFF_FFFF";
constant C_HIGHADDR : std_logic_vector := X"0000_0000";
constant C_S_AXI_SYSMON_MIN_SIZE : std_logic_vector(31 downto 0):= X"000003FF";
constant C_USE_WSTRB : integer := 1;
constant C_DPHASE_TIMEOUT : integer := 64;
--constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-C_S_AXI_ADDR_WIDTH-1)
-- := (others => '0');
constant ZERO_ADDR_PAD : std_logic_vector(0 to 64-32-1) := (others => '0');
constant INTERRUPT_NO : natural := 17; -- changed from 10 to 17 for adding
-- falling edge interrupts
constant C_INTR_CE_NUM : integer := 16; -- this is fixed for interrupt controller
constant MUX_ADDR_NO : integer := 5; -- added for XADC
-------------------------------------------------------------------------------
-- The local register array contains
-- 1. Software Reset Register (SRR), -- address C_BASEADDR + 0x00
-- 2. Status Register (SR), -- address C_BASEADDR + 0x04
-- 3. Alarm Output Status Register (AOSR), -- address C_BASEADDR + 0x08
-- 4. CONVST Register (CONVSTR), -- address C_BASEADDR + 0x0C
-- 5. SYSMON Reset Register (SYSMONRR). -- address C_BASEADDR + 0x10
-- All registers are 32 bit width and their addresses are at word boundry.
-------------------------------------------------------------------------------
constant LOCAL_REG_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant LOCAL_REG_HIGHADDR : std_logic_vector := C_BASEADDR or X"0000001F";
-------------------------------------------------------------------------------
-- The interrupt registers to be added if C_INCLUDE_INTR = 1
-------------------------------------------------------------------------------
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000040";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or x"0000007F";
-------------------------------------------------------------------------------
-- The address range is devided in the range of Status & Control registers
-- there are total 128 registers. First 64 are the status and remaning 64 are
-- control registers
-------------------------------------------------------------------------------
constant REG_FILE_BASEADDR : std_logic_vector := C_BASEADDR or X"00000200";
constant REG_FILE_HIGHADDR : std_logic_vector := C_BASEADDR or X"000003FF";
-------------------------------------------------------------------------------
--The address ranges for the registers are defined in USER_ARD_ADDR_RANGE_ARRAY
-------------------------------------------------------------------------------
constant USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & LOCAL_REG_BASEADDR,
ZERO_ADDR_PAD & LOCAL_REG_HIGHADDR,
ZERO_ADDR_PAD & REG_FILE_BASEADDR,
ZERO_ADDR_PAD & REG_FILE_HIGHADDR
);
constant INTR_USER_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & LOCAL_REG_BASEADDR,
ZERO_ADDR_PAD & LOCAL_REG_HIGHADDR,
ZERO_ADDR_PAD & INTR_BASEADDR,
ZERO_ADDR_PAD & INTR_HIGHADDR,
ZERO_ADDR_PAD & REG_FILE_BASEADDR,
ZERO_ADDR_PAD & REG_FILE_HIGHADDR
);
-------------------------------------------------------------------------------
-- The USER_ARD_ADDR_RANGE_ARRAY is subset of ARD_ADDR_RANGE_ARRAY based on the
-- C_INCLUDE_INTR parameter value.
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
add_intr_ard_addr_range_array(
C_INCLUDE_INTR,
USER_ARD_ADDR_RANGE_ARRAY,
INTR_USER_ARD_ADDR_RANGE_ARRAY
);
-------------------------------------------------------------------------------
--The total 128 DRP register address space is divided in two 64 register arrays
--The status and control registers are equally divided in the range to generate
--the chip enable signals.
--There are some local alarm registers, conversion start registers, ip reset
--registers present in the design.
--the no. of CE's required is defined in USER_ARD_NUM_CE_ARRAY array
-------------------------------------------------------------------------------
constant USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8, -- 5 chip enable + 3 dummy
-- CS_0 & CE_0 => SRR -- Addr = 00
-- CS_0 & CE_1 => SR -- Addr = 04
-- CS_0 & CE_2 => AOSR -- Addr = 08
-- CS_0 & CE_3 => CONVSTR -- Addr = 0C
-- CS_0 & CE_4 => SYSMONRR -- Addr = 10
-- CS_0 & CE_5 => dummy -- Addr = 14
-- CS_0 & CE_6 => dummy -- Addr = 18
-- CS_0 & CE_7 => dummy -- Addr = 1C
1 => 1--, -- 1 chip enable
-- CS_1 & CE_8 => 1 CE required to access DRP
);
constant INTR_USER_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => 8, -- 5 chip enable + 3 dummy
-- CS_0 & CE_0 => SRR -- Addr = 00
-- CS_0 & CE_1 => SR -- Addr = 04
-- CS_0 & CE_2 => AOSR -- Addr = 08
-- CS_0 & CE_3 => CONVSTR -- Addr = 0C
-- CS_0 & CE_4 => SYSMONRR -- Addr = 10
-- CS_0 & CE_5 => dummy -- Addr = 14
-- CS_0 & CE_6 => dummy -- Addr = 18
-- CS_0 & CE_7 => dummy -- Addr = 1C
1 => 16, -- 16 chip enable
-- CS_1 & CE_15 => GIER -- Addr = 5C
-- CS_1 & CE_16 => IPISR -- Addr = 60
-- CS_1 & CE_18 => IPIER -- Addr = 68
-- Following commented code is for reference with execution of above function
2 => 1 -- 1 chip enable -- addr = 200 to 3FF
-- CS_2 & CE_24 => 1 CE required to access DRP
);
-------------------------------------------------------------------------------
-- The USER_ARD_NUM_CE_ARRAY is subset of ARD_NUM_CE_ARRAY based on the
-- C_INCLUDE_INTR parameter value.
-------------------------------------------------------------------------------
constant ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
add_intr_ce_range_array(
C_INCLUDE_INTR,
USER_ARD_NUM_CE_ARRAY,
INTR_USER_ARD_NUM_CE_ARRAY
);
-------------------------------------------------------------------------------
-- Eight interrupts
-------------------------------------------------------------------------------
constant IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE(0 to INTERRUPT_NO-1):=
(
others => INTR_POS_EDGE_DETECT
);
-------------------------------------------------------------------------------
-- Calculating index for interrupt logic
-------------------------------------------------------------------------------
constant SWRESET : natural := 0;
constant INTR_LO : natural := 0;
constant INTR_HI : natural := 15;
constant CS_NUMBERS : integer :=((ARD_ADDR_RANGE_ARRAY'LENGTH/2));
constant RD_CE_NUMBERS : integer :=(calc_num_ce(ARD_NUM_CE_ARRAY));
constant WR_CE_NUMBERS : integer :=(calc_num_ce(ARD_NUM_CE_ARRAY));
constant IP_INTR_MODE_ARRAY_NUM : integer := IP_INTR_MODE_ARRAY'length;
constant RDCE_WRCE_SYSMON_CORE : integer := 9;
--------------------------------------------------------------------------------
-- Constant Declaration Ends
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Signal and Type Declarations
--------------------------------------------------------------------------------
--bus2ip signals
signal bus2ip_clk : std_logic;
signal bus2ip_reset : std_logic;
---
signal bus2ip_rdce : std_logic_vector((RD_CE_NUMBERS-1)downto 0);
signal bus2ip_rdce_int : std_logic_vector(0 to (RD_CE_NUMBERS-1));
signal bus2ip_rdce_xadc_core : std_logic_vector(0 to (RDCE_WRCE_SYSMON_CORE-1));
---
signal bus2ip_wrce : std_logic_vector((WR_CE_NUMBERS-1)downto 0);
signal bus2ip_wrce_int : std_logic_vector(0 to (WR_CE_NUMBERS-1));
signal bus2ip_wrce_xadc_core : std_logic_vector(0 to (RDCE_WRCE_SYSMON_CORE-1));
---
signal bus2ip_addr : std_logic_vector((C_S_AXI_ADDR_WIDTH-1)downto 0);
signal bus2ip_addr_int : std_logic_vector(0 to (C_S_AXI_ADDR_WIDTH-1));
---
signal bus2ip_be : std_logic_vector(((C_S_AXI_DATA_WIDTH/8)-1)downto 0);
signal bus2ip_be_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH/8)-1);
---
signal bus2ip_data : std_logic_vector(((C_S_AXI_DATA_WIDTH)-1)downto 0);
signal bus2ip_data_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
-- ip2bus signals
signal ip2bus_data : std_logic_vector((C_S_AXI_DATA_WIDTH-1)downto 0)
:= (others => '0');
signal ip2bus_data_int : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal ip2bus_data_int1 : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
---
signal ip2bus_wrack : std_logic;
signal ip2bus_rdack : std_logic;
signal ip2bus_error : std_logic;
signal ip2bus_wrack_int1 : std_logic;
signal ip2bus_rdack_int1 : std_logic;
signal ip2bus_error_int1 : std_logic;
signal xadc_ip2bus_data : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal xadc_ip2bus_wrack : std_logic;
signal xadc_ip2bus_rdack : std_logic;
-- signal xadc_ip2bus_error : std_logic;
signal interrupt_status_i : std_logic_vector(0 to (IP_INTR_MODE_ARRAY_NUM-1));
signal intr_ip2bus_data : std_logic_vector(0 to (C_S_AXI_DATA_WIDTH-1));
signal intr_ip2bus_wrack : std_logic;
signal intr_ip2bus_rdack : std_logic;
signal intr_ip2bus_error : std_logic;
-- Software Reset Signals
signal reset2ip_reset : std_logic := '0';
signal rst_ip2bus_wrack : std_logic;
signal rst_ip2bus_error : std_logic;
signal rst_ip2bus_rdack : std_logic;
signal rst_ip2bus_rdack_d1 : std_logic;
-- following signals are used to impleemnt the register access rule
signal and_reduce_be : std_logic;
signal partial_reg_access_error : std_logic;
signal bus2ip_reset_active_low : std_logic;
signal bus2ip_reset_active_high: std_logic;
--------------------------------------------
signal dummy_local_reg_rdack_d1 : std_logic;
signal dummy_local_reg_rdack : std_logic;
signal dummy_local_reg_wrack_d1 : std_logic;
signal dummy_local_reg_wrack : std_logic;
signal bus2ip_rdce_intr : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_wrce_intr : std_logic_vector(INTR_LO to INTR_HI);
-------------------------------------------------------------------------------
-- Architecture begins
-------------------------------------------------------------------------------
begin
--------------------------------------------
-- INSTANTIATE AXI SLAVE SINGLE
--------------------------------------------
AXI_LITE_IPIF_I : entity work.cpu_xadc_wiz_0_0_axi_lite_ipif
generic map
(
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_SYSMON_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
s_axi_aclk => s_axi_aclk, -- in
s_axi_aresetn => s_axi_aresetn, -- in
s_axi_awaddr => s_axi_awaddr, -- in
s_axi_awvalid => s_axi_awvalid, -- in
s_axi_awready => s_axi_awready, -- out
s_axi_wdata => s_axi_wdata, -- in
s_axi_wstrb => s_axi_wstrb, -- in
s_axi_wvalid => s_axi_wvalid, -- in
s_axi_wready => s_axi_wready, -- out
s_axi_bresp => s_axi_bresp, -- out
s_axi_bvalid => s_axi_bvalid, -- out
s_axi_bready => s_axi_bready, -- in
s_axi_araddr => s_axi_araddr, -- in
s_axi_arvalid => s_axi_arvalid, -- in
s_axi_arready => s_axi_arready, -- out
s_axi_rdata => s_axi_rdata, -- out
s_axi_rresp => s_axi_rresp, -- out
s_axi_rvalid => s_axi_rvalid, -- out
s_axi_rready => s_axi_rready, -- in
-- IP Interconnect (IPIC) port signals
Bus2IP_Clk => bus2ip_clk, -- out
Bus2IP_Resetn => bus2ip_reset_active_low, -- out
Bus2IP_Addr => bus2ip_addr, -- out
Bus2IP_RNW => open, -- out
Bus2IP_BE => bus2ip_be, -- out
Bus2IP_CS => open, -- out
Bus2IP_RdCE => bus2ip_rdce, -- out
Bus2IP_WrCE => bus2ip_wrce, -- out
Bus2IP_Data => bus2ip_data, -- out
IP2Bus_Data => ip2bus_data, -- in
IP2Bus_WrAck => ip2bus_wrack, -- in
IP2Bus_RdAck => ip2bus_rdack, -- in
IP2Bus_Error => ip2bus_error -- in
);
-------------------------------------------------------------------------------
-------------------------------
bus2ip_rdce_int <= bus2ip_rdce;
-------------------------------
bus2ip_wrce_int <= bus2ip_wrce;
-------------------------------
ip2bus_data <= ip2bus_data_int;
-------------------------------
----------------------
--REG_RESET_FROM_IPIF: convert active low to active hig reset to rest of
-- the core.
----------------------
REG_RESET_FROM_IPIF: process (s_axi_aclk) is
begin
if(s_axi_aclk'event and s_axi_aclk = '1') then
bus2ip_reset_active_high <= not(bus2ip_reset_active_low);
end if;
end process REG_RESET_FROM_IPIF;
----------------------
-------------------------------------------------------------------------------
-------------------- when interrupt is used.
RDCE_WRCE_GEN_I: if (C_INCLUDE_INTR = 1) generate
-----------------
--------
begin
--------
bus2ip_rdce_intr <= bus2ip_rdce_int -- (25-16=8) to (25-2=23)
(((RD_CE_NUMBERS-C_INTR_CE_NUM)-1)to (RD_CE_NUMBERS-2));
bus2ip_wrce_intr <= bus2ip_wrce_int -- (25-16=8) to (25-2=23)
(((WR_CE_NUMBERS-C_INTR_CE_NUM)-1)to (WR_CE_NUMBERS-2));
bus2ip_rdce_xadc_core <= bus2ip_rdce_int -- 0 to ((25-16=8)-2)=7
((RD_CE_NUMBERS-RD_CE_NUMBERS)to
((RD_CE_NUMBERS-C_INTR_CE_NUM)-2)
)
& -- 24 = last rdce
bus2ip_rdce_int(RD_CE_NUMBERS-1);
bus2ip_wrce_xadc_core <= bus2ip_wrce_int -- 0 to ((25-16=8)-1)=7
((WR_CE_NUMBERS-WR_CE_NUMBERS)to
((WR_CE_NUMBERS-C_INTR_CE_NUM)-2)
)
& -- 24 = last wrce
bus2ip_wrce_int(WR_CE_NUMBERS-1);
end generate RDCE_WRCE_GEN_I;
-----------------------------
-------------------------------------------------------------------------------
-------------------- when interrupt is NOT used.
RDCE_WRCE_NOT_GEN_I: if (C_INCLUDE_INTR = 0) generate
-----------------
--------
begin
--------
bus2ip_rdce_xadc_core <= bus2ip_rdce_int;
bus2ip_wrce_xadc_core <= bus2ip_wrce_int;
end generate RDCE_WRCE_NOT_GEN_I;
---------------------------------
-------------------------------------------------------------------------------
--------------------------------------------
-- XADC_CORE_I: INSTANTIATE XADC CORE
--------------------------------------------
AXI_XADC_CORE_I : cpu_xadc_wiz_0_0_xadc_core_drp
generic map
(
---------------- -------------------------
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
C_FAMILY => C_FAMILY,
---------------- -------------------------
CE_NUMBERS => RDCE_WRCE_SYSMON_CORE,
IP_INTR_NUM => IP_INTR_MODE_ARRAY_NUM,
C_SIM_MONITOR_FILE => C_SIM_MONITOR_FILE,
------------------ -------------------------
MUX_ADDR_NO => MUX_ADDR_NO
)
port map
(
-- IP Interconnect (IPIC) port signals ---------
Bus2IP_Clk => bus2ip_clk,
Bus2IP_Rst => reset2ip_reset,
Bus2IP_RdCE => bus2ip_rdce_xadc_core,
Bus2IP_WrCE => bus2ip_wrce_xadc_core,
Bus2IP_Addr => bus2ip_addr,
Bus2IP_Data => bus2ip_data,
-- ip2bus signals ------------------------------
Sysmon_IP2Bus_Data => xadc_ip2bus_data,
Sysmon_IP2Bus_WrAck => xadc_ip2bus_wrack,
Sysmon_IP2Bus_RdAck => xadc_ip2bus_rdack,
Interrupt_status => interrupt_status_i,
--- external interface signals ------------------
busy_out => busy_out,
channel_out => channel_out,
eoc_out => eoc_out,
eos_out => eos_out,
ot_out => ot_out,
alarm_out => alarm_out,
vp_in => vp_in,
vn_in => vn_in
);
----------------------------------------------------------
-- SOFT_RESET_I: INSTANTIATE SOFTWARE RESET REGISTER (SRR)
----------------------------------------------------------
SOFT_RESET_I: entity work.cpu_xadc_wiz_0_0_soft_reset
generic map
(
C_SIPIF_DWIDTH => C_S_AXI_DATA_WIDTH,
-- Width of triggered reset in Bus Clocks
C_RESET_WIDTH => 16
)
port map
(
-- Inputs From the AXI Slave Single Bus
Bus2IP_Reset => bus2ip_reset_active_high, -- in
Bus2IP_Clk => bus2ip_clk, -- in
Bus2IP_WrCE => bus2ip_wrce_int(SWRESET), -- in
Bus2IP_Data => bus2ip_data, -- in
Bus2IP_BE => bus2ip_be, -- in
-- Final Device Reset Output
Reset2IP_Reset => reset2ip_reset, -- out
-- Status Reply Outputs to the Bus
Reset2Bus_WrAck => rst_ip2bus_wrack, -- out
Reset2Bus_Error => rst_ip2bus_error, -- out
Reset2Bus_ToutSup => open -- out
);
------------------------------------------------------------
-- INSTANTIATE INTERRUPT CONTROLLER MODULE (IPISR,IPIER,GIER)
------------------------------------------------------------
-- INTR_CTRLR_GEN_I: Generate logic to be used to pass signals,
-------------------- when interrupt is used.
INTR_CTRLR_GEN_I: if (C_INCLUDE_INTR = 1) generate
-----------------
--------
signal bus2ip_rdce_intr_int : std_logic_vector(INTR_LO to INTR_HI);
signal bus2ip_wrce_intr_int : std_logic_vector(INTR_LO to INTR_HI);
signal dummy_bus2ip_rdce_intr : std_logic;
signal dummy_bus2ip_wrce_intr : std_logic;
signal dummy_intr_reg_rdack_d1: std_logic;
signal dummy_intr_reg_rdack : std_logic;
signal dummy_intr_reg_wrack_d1: std_logic;
signal dummy_intr_reg_wrack : std_logic;
--------
begin
--------
bus2ip_rdce_intr_int <= "0000000" &
bus2ip_rdce_intr(7 to 8) &
"0" &
bus2ip_rdce_intr(10) &
"00000";
bus2ip_wrce_intr_int <= "0000000" &
bus2ip_wrce_intr(7 to 8) &
"0" &
bus2ip_wrce_intr(10) &
"00000";
dummy_bus2ip_rdce_intr <= or_reduce(bus2ip_rdce_intr(0 to 6)) or
bus2ip_rdce_intr(9) or
or_reduce(bus2ip_rdce_intr(11 to 15));
dummy_bus2ip_wrce_intr <= or_reduce(bus2ip_wrce_intr(0 to 6)) or
bus2ip_wrce_intr(9) or
or_reduce(bus2ip_wrce_intr(11 to 15));
---------------------------------------------
DUMMY_INTR_RD_WR_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
dummy_intr_reg_rdack_d1 <= '0';
dummy_intr_reg_rdack <= '0';
dummy_intr_reg_wrack_d1 <= '0';
dummy_intr_reg_wrack <= '0';
else
dummy_intr_reg_rdack_d1 <= dummy_bus2ip_rdce_intr;
dummy_intr_reg_rdack <= dummy_bus2ip_rdce_intr and
(not dummy_intr_reg_rdack_d1);
dummy_intr_reg_wrack_d1 <= dummy_bus2ip_wrce_intr;
dummy_intr_reg_wrack <= dummy_bus2ip_wrce_intr and
(not dummy_intr_reg_wrack_d1);
end if;
end if;
end process DUMMY_INTR_RD_WR_ACK_GEN_PROCESS;
---------------------------------------------
INTERRUPT_CONTROL_I: entity work.cpu_xadc_wiz_0_0_interrupt_control
generic map
(
C_NUM_CE => C_INTR_CE_NUM,
C_NUM_IPIF_IRPT_SRC => 1, -- Set to 1 to avoid null array
C_IP_INTR_MODE_ARRAY => IP_INTR_MODE_ARRAY,
-- Specifies device Priority Encoder function
C_INCLUDE_DEV_PENCODER => FALSE,
-- Specifies device ISC hierarchy
C_INCLUDE_DEV_ISC => FALSE,
C_IPIF_DWIDTH => C_S_AXI_DATA_WIDTH
)
port map
(
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Reset => reset2ip_reset,
Bus2IP_Data => bus2ip_data,
Bus2IP_BE => bus2ip_be,
Interrupt_RdCE => bus2ip_rdce_intr_int,
Interrupt_WrCE => bus2ip_wrce_intr_int,
IPIF_Reg_Interrupts => "00", -- Tie off the unused reg intr's
IPIF_Lvl_Interrupts => "0", -- Tie off the dummy lvl intr
IP2Bus_IntrEvent => interrupt_status_i,
Intr2Bus_DevIntr => ip2intc_irpt,
Intr2Bus_DBus => intr_ip2bus_data,
Intr2Bus_WrAck => intr_ip2bus_wrack,
Intr2Bus_RdAck => intr_ip2bus_rdack,
Intr2Bus_Error => intr_ip2bus_error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
ip2bus_wrack_int1 <= xadc_ip2bus_wrack or
rst_ip2bus_wrack or
intr_ip2bus_wrack or
dummy_intr_reg_wrack or
dummy_local_reg_wrack;
ip2bus_rdack_int1 <= xadc_ip2bus_rdack or
rst_ip2bus_rdack or
intr_ip2bus_rdack or
dummy_intr_reg_rdack or
dummy_local_reg_rdack;
ip2bus_error_int1 <= rst_ip2bus_error or
intr_ip2bus_error or
partial_reg_access_error;
ip2bus_data_int1 <= xadc_ip2bus_data or
intr_ip2bus_data;
process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset = '1') then
ip2bus_wrack <= '0';
ip2bus_rdack <= '0';
ip2bus_error <= '0';
ip2bus_data_int <= (others => '0');
else
ip2bus_wrack <= ip2bus_wrack_int1;
ip2bus_rdack <= ip2bus_rdack_int1;
ip2bus_error <= ip2bus_error_int1;
ip2bus_data_int <= ip2bus_data_int1;
end if;
end if;
end process;
end generate INTR_CTRLR_GEN_I;
------------------------------
-------------------------------------------------------------------------------
-- NO_INTR_CTRLR_GEN_I: Generate logic to be used to pass signals,
----------------------- when interrupt is not used.
NO_INTR_CTRLR_GEN_I : if (C_INCLUDE_INTR = 0) generate
-----
begin
-----
ip2bus_wrack_int1 <= xadc_ip2bus_wrack or
rst_ip2bus_wrack or
dummy_local_reg_wrack;
ip2bus_rdack_int1 <= xadc_ip2bus_rdack or
rst_ip2bus_rdack or
dummy_local_reg_rdack;
ip2bus_error_int1 <= rst_ip2bus_error or
partial_reg_access_error;
ip2bus_data_int1 <= xadc_ip2bus_data;
ip2intc_irpt <= '0';
process (Bus2IP_Clk)
begin
if (Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (reset2ip_reset = '1') then
ip2bus_wrack <= '0';
ip2bus_rdack <= '0';
ip2bus_error <= '0';
ip2bus_data_int <= (others => '0');
else
ip2bus_wrack <= ip2bus_wrack_int1;
ip2bus_rdack <= ip2bus_rdack_int1;
ip2bus_error <= ip2bus_error_int1;
ip2bus_data_int <= ip2bus_data_int1;
end if;
end if;
end process;
end generate NO_INTR_CTRLR_GEN_I;
---------------------------------
-------------------------------------------------------------------------------
------------------------------------------------------------
-- SW_RESET_REG_READ_ACK_GEN_PROCESS:IMPLEMENT READ ACK LOGIC FOR SOFTWARE
-- RESET MODULE. This is dummy read as read is
-- not allowed on reset core.
------------------------------------------------------------
SW_RESET_REG_READ_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
rst_ip2bus_rdack_d1 <= '0';
rst_ip2bus_rdack <= '0';
else
rst_ip2bus_rdack_d1 <= bus2ip_rdce_int(SWRESET);
rst_ip2bus_rdack <= bus2ip_rdce_int(SWRESET) and
(not rst_ip2bus_rdack_d1);
end if;
end if;
end process SW_RESET_REG_READ_ACK_GEN_PROCESS;
---------------------------------------------
-------------------------------------------------------------------------------
-- Logic for generation of error signal for partial word access byte enables
and_reduce_be <= and_reduce(bus2ip_be);
partial_reg_access_error <= (not and_reduce_be) and
(xadc_ip2bus_rdack or
xadc_ip2bus_wrack);
-------------------------------------------------------------------------------
--------------------------------------------------------------
---- SW_RESET_REG_READ_ACK_GEN_PROCESS:Implement read ack logic for dummy register
---- holes. This is dummy read as read/write is
---- not returning any value. In local registers.
--------------------------------------------------------------
DUMMY_REG_READ_WRITE_ACK_GEN_PROCESS:process(Bus2IP_Clk) is
begin
if (bus2ip_clk'event and bus2ip_clk = '1') then
if (reset2ip_reset = RESET_ACTIVE) then
dummy_local_reg_rdack_d1 <= '0';
dummy_local_reg_rdack <= '0';
dummy_local_reg_wrack_d1 <= '0';
dummy_local_reg_wrack <= '0';
else
dummy_local_reg_rdack_d1 <= or_reduce(bus2ip_rdce_int(5 to 7));
dummy_local_reg_rdack <= or_reduce(bus2ip_rdce_int(5 to 7)) and
(not dummy_local_reg_rdack_d1);
dummy_local_reg_wrack_d1 <= or_reduce(bus2ip_wrce_int(5 to 7));
dummy_local_reg_wrack <= or_reduce(bus2ip_wrce_int(5 to 7)) and
(not dummy_local_reg_wrack_d1);
end if;
end if;
end process DUMMY_REG_READ_WRITE_ACK_GEN_PROCESS;
-----------------------------------------------
end architecture imp;
| gpl-3.0 | debd2bc1f8062392daf86608519ca11a | 0.438869 | 4.190663 | false | false | false | false |
ErikAndren/VGA3BitTestPattern | VGAGen.vhd | 1 | 2,896 | library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.Types.all;
use work.VgaPack.all;
entity VGAGen is
generic (
ClkDiv : boolean
);
port (
RstN : in bit1;
Clk : in bit1;
--
RedOut : out word(3-1 downto 0);
GreenOut : out word(3-1 downto 0);
BlueOut : out word(3-1 downto 0);
HSync : out bit1;
VSync : out bit1;
--
InView : out bit1
);
end entity;
architecture rtl of VGAGen is
signal hCount : word(10-1 downto 0);
signal vCount : word(10-1 downto 0);
signal data : word(3-1 downto 0);
signal h_dat : word(3-1 downto 0);
signal v_dat : word(3-1 downto 0);
signal hCount_ov : bit1;
signal vCount_ov : bit1;
--
signal dat_act : bit1;
signal DivClk : bit1;
--
signal Cnt_D : word(9-1 downto 0);
begin
HasClkDiv : if ClkDiv generate
ClkDivProc : process (RstN, Clk)
begin
if RstN = '0' then
DivClk <= '0';
elsif rising_edge(Clk) then
DivClk <= not DivClk;
end if;
end process;
end generate;
NoClkDiv : if not ClkDiv generate
DivClk <= Clk;
end generate;
hcount_ov <= '1' when hcount = hpixel_end else '0';
HCnt : process (DivClk)
begin
if rising_edge(DivClk) then
if (hcount_ov = '1') then
hcount <= (others => '0');
else
hcount <= hcount + 1;
end if;
end if;
end process;
vcount_ov <= '1' when vcount = vline_end else '0';
VCnt : process (DivClk)
begin
if rising_edge(DivClk) then
if (hcount_ov = '1') then
if (vcount_ov = '1') then
vcount <= (others => '0');
else
vcount <= vcount + 1;
end if;
end if;
end if;
end process;
InView <= dat_act;
dat_act <= '1' when ((hcount >= hdat_begin) and (hcount < hdat_end)) and ((vcount >= vdat_begin) and (vcount < vdat_end)) else '0';
Hsync <= '1' when hcount > hsync_end else '0';
Vsync <= '1' when vcount > vsync_end else '0';
--
OutputGen : process (RstN, DivClk)
begin
if RstN = '0' then
RedOut <= (others => '0');
GreenOut <= (others => '0');
BlueOut <= (others => '0');
Cnt_D <= (others => '0');
elsif rising_edge(DivClk) then
RedOut <= (others => '0');
GreenOut <= (others => '0');
BlueOut <= (others => '0');
if (vcount = vdat_begin and hcount = hdat_begin) then
Cnt_D <= Cnt_D + 1;
end if;
if dat_act = '1' then
RedOut <= Cnt_D(3-1 downto 0);
GreenOut <= Cnt_D(6-1 downto 3);
BlueOut <= Cnt_D(9-1 downto 6);
end if;
end if;
end process;
end architecture rtl;
| gpl-2.0 | 03ae77e9fe6753f8c2be4a192c2b87f3 | 0.514503 | 3.375291 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/clock.vhd | 1 | 28,379 | ------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : clock.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-03-13
-- Last update: 2018-04-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Clock structure
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-03-13 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.util_pkg.all;
use work.types_pkg.all;
architecture STRUCTURE of clock is
component cpu is
port (
DDR_cas_n : inout std_logic;
DDR_cke : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_we_n : inout std_logic;
DDR_ba : inout std_logic_vector (2 downto 0);
DDR_addr : inout std_logic_vector (14 downto 0);
DDR_dm : inout std_logic_vector (3 downto 0);
DDR_dq : inout std_logic_vector (31 downto 0);
DDR_dqs_n : inout std_logic_vector (3 downto 0);
DDR_dqs_p : inout std_logic_vector (3 downto 0);
FIXED_IO_mio : inout std_logic_vector (53 downto 0);
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
Vp_Vn_v_n : in std_logic;
Vp_Vn_v_p : in std_logic;
UART_0_txd : out std_logic;
UART_0_rxd : in std_logic;
IIC_0_sda_i : in std_logic;
IIC_0_sda_o : out std_logic;
IIC_0_sda_t : out std_logic;
IIC_0_scl_i : in std_logic;
IIC_0_scl_o : out std_logic;
IIC_0_scl_t : out std_logic;
IIC_1_sda_i : in std_logic;
IIC_1_sda_o : out std_logic;
IIC_1_sda_t : out std_logic;
IIC_1_scl_i : in std_logic;
IIC_1_scl_o : out std_logic;
IIC_1_scl_t : out std_logic;
GPIO_tri_i : in std_logic_vector (15 downto 0);
GPIO_tri_o : out std_logic_vector (15 downto 0);
GPIO_tri_t : out std_logic_vector (15 downto 0);
IIC_scl_i : in std_logic;
IIC_scl_o : out std_logic;
IIC_scl_t : out std_logic;
IIC_sda_i : in std_logic;
IIC_sda_o : out std_logic;
IIC_sda_t : out std_logic;
EPC_INTF_addr : out std_logic_vector (0 to 31);
EPC_INTF_ads : out std_logic;
EPC_INTF_be : out std_logic_vector (0 to 3);
EPC_INTF_burst : out std_logic;
EPC_INTF_clk : in std_logic;
EPC_INTF_cs_n : out std_logic_vector (0 to 0);
EPC_INTF_data_i : in std_logic_vector (0 to 31);
EPC_INTF_data_o : out std_logic_vector (0 to 31);
EPC_INTF_data_t : out std_logic_vector (0 to 31);
EPC_INTF_rd_n : out std_logic;
EPC_INTF_rdy : in std_logic_vector (0 to 0);
EPC_INTF_rnw : out std_logic;
EPC_INTF_rst : in std_logic;
EPC_INTF_wr_n : out std_logic;
OCXO_CLK100 : in std_logic;
FCLK_CLK0 : out std_logic;
FCLK_RESET0_N : out std_logic;
OCXO_RESETN : out std_logic_vector (0 to 0);
Int0 : in std_logic_vector (0 to 0);
Int1 : in std_logic_vector (0 to 0);
Int2 : in std_logic_vector (0 to 0);
Int3 : in std_logic_vector (0 to 0)
);
end component cpu;
component io
port (
fclk_rst_n : in std_logic;
fclk : in std_logic;
rst_n : in std_logic;
clk : in std_logic;
-- fclk
GPIO_tri_i : out std_logic_vector (15 downto 0);
GPIO_tri_o : in std_logic_vector (15 downto 0);
GPIO_tri_t : in std_logic_vector (15 downto 0);
-- clk
locked : in std_logic;
dac_ena : out std_logic;
dac_tri : out std_logic;
disp_ena : out std_logic;
-- fclk
pll_rst_n : out std_logic;
ocxo_ena : inout std_logic;
gps_ena : inout std_logic;
gps_tri : out std_logic;
gpio : inout std_logic_vector (7 DOWNTO 0)
);
end component;
component syspll
port (
-- Clock in ports
ocxo_clk : in std_logic;
fclk : in std_logic;
clk_sel : in std_logic;
-- Clock out ports
clk : out std_logic;
-- Status and control signals
pll_rst_n : in std_logic;
locked : out std_logic
);
end component;
component regs
port (
rst_n : in std_logic;
clk : in std_logic;
EPC_INTF_addr : in std_logic_vector(0 to 31);
EPC_INTF_be : in std_logic_vector(0 to 3);
EPC_INTF_burst : in std_logic;
EPC_INTF_cs_n : in std_logic;
EPC_INTF_data_i : out std_logic_vector(0 to 31);
EPC_INTF_data_o : in std_logic_vector(0 to 31);
EPC_INTF_rdy : out std_logic;
EPC_INTF_rnw : in std_logic; -- Write when '0'
-- Time stamp counter
tsc_cnt : in std_logic_vector(63 downto 0);
tsc_cnt1 : in std_logic_vector(63 downto 0);
tsc_read : out std_logic;
-- Time setting
cur_time : in time_ty;
set : out std_logic;
set_time : out time_ty;
-- PLL control
gps_3dfix_d : in std_logic;
gps_1pps_d : in std_logic;
tsc_1pps_d : in std_logic;
pll_trig : in std_logic;
pfd_status : in std_logic;
pdiff_1pps : in std_logic_vector(31 downto 0);
fdiff_1pps : in std_logic_vector(31 downto 0);
tsc_sync : out std_logic;
pfd_resync : out std_logic;
dac_val : out std_logic_vector(15 downto 0);
pps_irq : out std_logic;
pll_irq : out std_logic;
-- Fan ms per revolution, percent speed
fan_uspr : in std_logic_vector(19 downto 0);
fan_pct : out std_logic_vector(7 downto 0);
-- Display memory
sram_addr : out std_logic_vector(9 downto 0);
sram_we : out std_logic;
sram_datao : out std_logic_vector(31 downto 0);
sram_datai : in std_logic_vector(31 downto 0);
stat_src : out std_logic_vector(3 downto 0);
disp_page : out std_logic_vector(7 downto 0);
disp_pdm : out std_logic_vector(7 downto 0)
);
end component regs;
component fan
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
fan_pct : in std_logic_vector(7 downto 0);
fan_tach : in std_logic;
fan_pwm : out std_logic;
fan_uspr : out std_logic_vector(19 downto 0)
);
end component fan;
component tsc
port (
rst_n : in std_logic;
clk : in std_logic;
gps_1pps : in std_logic;
gps_3dfix_d : in std_logic;
tsc_read : in std_logic;
tsc_sync : in std_logic;
pfd_resync : in std_logic;
gps_1pps_d : out std_logic;
tsc_1pps_d : out std_logic;
pll_trig : out std_logic;
pfd_status : out std_logic;
pdiff_1pps : out std_logic_vector(31 downto 0);
fdiff_1pps : out std_logic_vector(31 downto 0);
tsc_cnt : out std_logic_vector(63 downto 0);
tsc_cnt1 : out std_logic_vector(63 downto 0);
tsc_1pps : out std_logic;
tsc_1ppms : out std_logic;
tsc_1ppus : out std_logic
);
end component tsc;
component bcdtime
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
set : in std_logic;
set_time : in time_ty;
cur_time : out time_ty
);
end component;
component dac
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
dac_ena : in std_logic;
dac_tri : in std_logic;
dac_val : in std_logic_vector(15 downto 0);
dac_sclk : out std_logic;
dac_cs_n : out std_logic;
dac_sin : out std_logic
);
end component;
component disp
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
-- Display memory
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
-- Time of day
cur_time : in time_ty;
-- Output to tlc59282 LED driver
disp_sclk : out std_logic;
disp_blank : out std_logic;
disp_lat : out std_logic;
disp_sin : out std_logic;
disp_status : OUT std_logic
);
end component;
signal EPC_INTF_addr : std_logic_vector (0 to 31);
signal EPC_INTF_ads : std_logic;
signal EPC_INTF_be : std_logic_vector (0 to 3);
signal EPC_INTF_burst : std_logic;
signal EPC_INTF_cs_n : std_logic;
signal EPC_INTF_data_i : std_logic_vector (0 to 31);
signal EPC_INTF_data_o : std_logic_vector (0 to 31);
signal EPC_INTF_data_t : std_logic_vector (0 to 31);
signal EPC_INTF_rd_n : std_logic;
signal EPC_INTF_rdy : std_logic;
signal EPC_INTF_rnw : std_logic;
signal EPC_INTF_wr_n : std_logic;
signal GPIO_tri_i : std_logic_vector (15 downto 0);
signal GPIO_tri_o : std_logic_vector (15 downto 0);
signal GPIO_tri_t : std_logic_vector (15 downto 0);
SIGNAL dac_ena : std_logic;
SIGNAL dac_tri : std_logic;
SIGNAL disp_ena : std_logic;
SIGNAL gps_tri : std_logic;
SIGNAL gps_uart_rxd : std_logic;
SIGNAL gps_uart_txd : std_logic;
SIGNAL gps_uart_txd_o : std_logic;
SIGNAL gps_uart_txd_t : std_logic;
signal iic_0_scl_i : std_logic;
signal iic_0_scl_o : std_logic;
signal iic_0_scl_t : std_logic;
signal iic_0_sda_i : std_logic;
signal iic_0_sda_o : std_logic;
signal iic_0_sda_t : std_logic;
signal iic_1_scl_i : std_logic;
signal iic_1_scl_o : std_logic;
signal iic_1_scl_t : std_logic;
signal iic_1_sda_i : std_logic;
signal iic_1_sda_o : std_logic;
signal iic_1_sda_t : std_logic;
signal iic_scl_i : std_logic;
signal iic_scl_o : std_logic;
signal iic_scl_t : std_logic;
signal iic_sda_i : std_logic;
signal iic_sda_o : std_logic;
signal iic_sda_t : std_logic;
signal int : std_logic_vector (3 downto 0);
signal irq : std_logic_vector (3 downto 0);
signal fclk : std_logic;
signal fclk_rst_n : std_logic;
signal rst_n : std_logic;
signal pll_rst_n : std_logic;
signal clk_sel : std_logic;
signal clk : std_logic;
signal locked : std_logic;
signal rtc_int_n_d : std_logic;
signal temp_int1_n_d : std_logic;
signal temp_int2_n_d : std_logic;
signal fan_pct : std_logic_vector(7 downto 0);
signal fan_uspr : std_logic_vector(19 downto 0);
signal gps_3dfix_d : std_logic;
signal tsc_read : std_logic;
signal tsc_sync : std_logic;
SIGNAL pfd_resync : std_logic;
signal gps_1pps_d : std_logic;
SIGNAL tsc_1pps_d : std_logic;
SIGNAL pll_trig : std_logic;
SIGNAL pfd_status : std_logic;
SIGNAL pdiff_1pps : std_logic_vector(31 downto 0);
SIGNAL fdiff_1pps : std_logic_vector(31 downto 0);
signal tsc_cnt : std_logic_vector(63 downto 0);
SIGNAL tsc_cnt1 : std_logic_vector(63 downto 0);
signal tsc_1pps : std_logic;
signal tsc_1ppms : std_logic;
signal tsc_1ppus : std_logic;
signal set : std_logic;
signal set_time : time_ty;
signal dac_val : std_logic_vector(15 downto 0);
signal cur_time : time_ty;
signal sram_addr : std_logic_vector(9 downto 0);
signal sram_we : std_logic;
signal sram_datao : std_logic_vector(31 downto 0);
signal sram_datai : std_logic_vector(31 downto 0);
signal stat_src : std_logic_vector(3 downto 0);
SIGNAL disp_page : std_logic_vector(7 downto 0);
signal disp_pdm : std_logic_vector(7 downto 0);
begin
cpu_i : component cpu
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
Vp_Vn_v_n => Vp_Vn_v_n,
Vp_Vn_v_p => Vp_Vn_v_p,
EPC_INTF_addr => EPC_INTF_addr,
EPC_INTF_ads => EPC_INTF_ads,
EPC_INTF_be => EPC_INTF_be,
EPC_INTF_burst => EPC_INTF_burst,
EPC_INTF_clk => clk,
EPC_INTF_cs_n(0) => EPC_INTF_cs_n,
EPC_INTF_data_i => EPC_INTF_data_i,
EPC_INTF_data_o => EPC_INTF_data_o,
EPC_INTF_data_t => EPC_INTF_data_t,
EPC_INTF_rd_n => EPC_INTF_rd_n,
EPC_INTF_rdy(0) => EPC_INTF_rdy,
EPC_INTF_rnw => EPC_INTF_rnw,
EPC_INTF_rst => rst_n,
EPC_INTF_wr_n => EPC_INTF_wr_n,
GPIO_tri_i => GPIO_tri_i,
GPIO_tri_o => GPIO_tri_o,
GPIO_tri_t => GPIO_tri_t,
IIC_0_scl_i => iic_0_scl_i,
IIC_0_scl_o => iic_0_scl_o,
IIC_0_scl_t => iic_0_scl_t,
IIC_0_sda_i => iic_0_sda_i,
IIC_0_sda_o => iic_0_sda_o,
IIC_0_sda_t => iic_0_sda_t,
IIC_1_scl_i => iic_1_scl_i,
IIC_1_scl_o => iic_1_scl_o,
IIC_1_scl_t => iic_1_scl_t,
IIC_1_sda_i => iic_1_sda_i,
IIC_1_sda_o => iic_1_sda_o,
IIC_1_sda_t => iic_1_sda_t,
IIC_scl_i => iic_scl_i,
IIC_scl_o => iic_scl_o,
IIC_scl_t => iic_scl_t,
IIC_sda_i => iic_sda_i,
IIC_sda_o => iic_sda_o,
IIC_sda_t => iic_sda_t,
UART_0_rxd => gps_uart_rxd,
UART_0_txd => gps_uart_txd,
OCXO_CLK100 => clk,
FCLK_CLK0 => fclk,
FCLK_RESET0_N => fclk_rst_n,
OCXO_RESETN(0) => rst_n,
Int0(0) => int(0), -- id# 63, hw# 31
Int1(0) => int(1), -- id# 64, hw# 32
Int2(0) => int(2), -- id# 65, hw# 33
Int3(0) => int(3) -- id# 66, hw# 34
);
-- rtc I2C interface
rtc_scl <= iic_0_scl_o when iic_0_scl_t = '0' else 'Z';
iic_0_scl_i <= rtc_scl;
rtc_sda <= iic_0_sda_o when iic_0_sda_t = '0' else 'Z';
iic_0_sda_i <= rtc_sda;
-- ocxo I2C interface
ocxo_scl <= iic_1_scl_o when iic_1_scl_t = '0' else 'Z';
iic_1_scl_i <= ocxo_scl;
ocxo_sda <= iic_1_sda_o when iic_1_sda_t = '0' else 'Z';
iic_1_sda_i <= ocxo_sda;
-- Temperature sensor I2C interface
temp_scl <= iic_scl_o when iic_scl_t = '0' else 'Z';
iic_scl_i <= temp_scl;
temp_sda <= iic_sda_o when iic_sda_t = '0' else 'Z';
iic_sda_i <= temp_sda;
-- GPS uart IOB and tristate
gps_rx_i: delay_sig generic map (1) port map (fclk_rst_n, fclk, gps_rxd, gps_uart_rxd);
gps_tx_t: delay_sig generic map (1, '1') port map (fclk_rst_n, fclk, gps_tri, gps_uart_txd_t);
gps_tx_o: delay_sig generic map (1, '1') port map (fclk_rst_n, fclk, gps_uart_txd, gps_uart_txd_o);
gps_txd <= gps_uart_txd_o when gps_uart_txd_t = '0' else 'Z';
io_i : io
port map (
fclk_rst_n => fclk_rst_n,
fclk => fclk,
rst_n => rst_n,
clk => clk,
-- fclk
GPIO_tri_i => GPIO_tri_i,
GPIO_tri_o => GPIO_tri_o,
GPIO_tri_t => GPIO_tri_t,
-- clk
locked => locked,
dac_ena => dac_ena,
dac_tri => dac_tri,
disp_ena => disp_ena,
-- fclk
pll_rst_n => pll_rst_n,
ocxo_ena => ocxo_ena,
gps_ena => gps_ena,
gps_tri => gps_tri,
gpio => gpio
);
-- Interrupts, clock domain transfer to cpu clock domain
rtc_irq : delay_sig generic map (1, '1') port map (fclk_rst_n, fclk, rtc_int_n, rtc_int_n_d);
temp_irq1 : delay_sig generic map (1, '1') port map (fclk_rst_n, fclk, temp_int1_n, temp_int1_n_d);
temp_irq2 : delay_sig generic map (1, '1') port map (fclk_rst_n, fclk, temp_int2_n, temp_int2_n_d);
irq(0) <= not rtc_int_n_d; -- RTC
--irq(1) <= '0'; -- 1pps
--irq(2) <= '0'; -- PLL
irq(3) <= not temp_int1_n_d or not temp_int2_n_d; -- temp sensors
irq_i : delay_vec generic map (2) port map (fclk_rst_n, fclk, irq, int);
clk_sel <= '0';
syspll_i : syspll
port map (
-- Clock in ports
ocxo_clk => ocxo_clk,
fclk => fclk,
clk_sel => clk_sel,
-- Clock out ports
clk => clk,
-- Status and control signals
pll_rst_n => pll_rst_n,
locked => locked
);
gps_3dfix_i: delay_sig generic map (2) port map (rst_n, clk, gps_3dfix, gps_3dfix_d);
regs_i: regs
port map (
rst_n => rst_n,
clk => clk,
EPC_INTF_addr => EPC_INTF_addr,
EPC_INTF_be => EPC_INTF_be,
EPC_INTF_burst => EPC_INTF_burst,
EPC_INTF_cs_n => EPC_INTF_cs_n,
EPC_INTF_data_i => EPC_INTF_data_i,
EPC_INTF_data_o => EPC_INTF_data_o,
EPC_INTF_rdy => EPC_INTF_rdy,
EPC_INTF_rnw => EPC_INTF_rnw,
-- Time stamp counter
tsc_cnt => tsc_cnt,
tsc_cnt1 => tsc_cnt1,
tsc_read => tsc_read,
-- Time setting
cur_time => cur_time,
set => set,
set_time => set_time,
-- PLL control
gps_3dfix_d => gps_3dfix_d,
gps_1pps_d => gps_1pps_d,
tsc_1pps_d => tsc_1pps_d,
pll_trig => pll_trig,
pfd_status => pfd_status,
pdiff_1pps => pdiff_1pps,
fdiff_1pps => fdiff_1pps,
tsc_sync => tsc_sync,
pfd_resync => pfd_resync,
dac_val => dac_val,
pps_irq => irq(1),
pll_irq => irq(2),
-- Fan ms per revolution, percent speed
fan_uspr => fan_uspr,
fan_pct => fan_pct,
-- Display memory
sram_addr => sram_addr,
sram_we => sram_we,
sram_datao => sram_datao,
sram_datai => sram_datai,
stat_src => stat_src,
disp_page => disp_page,
disp_pdm => disp_pdm
);
fan_i: fan
port map (
rst_n => rst_n,
clk => clk,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus,
fan_pct => fan_pct,
fan_tach => fan_tach,
fan_pwm => fan_pwm,
fan_uspr => fan_uspr
);
tsc_i: tsc
port map (
rst_n => rst_n,
clk => clk,
gps_1pps => gps_1pps,
gps_3dfix_d => gps_3dfix_d,
tsc_read => tsc_read,
tsc_sync => tsc_sync,
pfd_resync => pfd_resync,
gps_1pps_d => gps_1pps_d,
tsc_1pps_d => tsc_1pps_d,
pll_trig => pll_trig,
pfd_status => pfd_status,
pdiff_1pps => pdiff_1pps,
fdiff_1pps => fdiff_1pps,
tsc_cnt => tsc_cnt,
tsc_cnt1 => tsc_cnt1,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus
);
bcdtime_i: bcdtime
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
set => set,
set_time => set_time,
cur_time => cur_time
);
dac_i: dac
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
dac_ena => dac_ena,
dac_tri => dac_tri,
dac_val => dac_val,
dac_sclk => dac_sclk,
dac_cs_n => dac_cs_n,
dac_sin => dac_sin
);
disp_i : disp
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus,
disp_ena => disp_ena,
disp_page => disp_page,
disp_pdm => disp_pdm,
stat_src => stat_src,
stat(0) => '0',
stat(1) => '1',
stat(2) => gps_3dfix_d,
stat(3) => gps_1pps_d,
stat(4) => tsc_1pps_d,
stat(5) => pll_trig,
stat(6) => pfd_status,
stat(15 downto 7) => (others => '0'),
-- Display memory
sram_addr => sram_addr,
sram_we => sram_we,
sram_datao => sram_datao,
sram_datai => sram_datai,
-- Time of day
cur_time => cur_time,
-- Output to tlc59282 LED driver
disp_sclk => disp_sclk,
disp_blank => disp_blank,
disp_lat => disp_lat,
disp_sin => disp_sin,
disp_status => disp_status
);
end STRUCTURE;
| gpl-3.0 | 871f9db2eb4bf48721a819a53329310f | 0.406815 | 3.564305 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/weights/simulation/bmg_stim_gen.vhd | 1 | 7,566 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For Single Port Ram
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For SRAM
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_SRAM IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_SRAM;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_SRAM IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC:='0'
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A: INTEGER:= DIVROUNDUP(24,24);
SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
SIGNAL DO_WRITE : STD_LOGIC := '0';
SIGNAL DO_READ : STD_LOGIC := '0';
SIGNAL COUNT_NO : INTEGER :=0;
SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
BEGIN
WRITE_ADDR_INT(4 DOWNTO 0) <= WRITE_ADDR(4 DOWNTO 0);
READ_ADDR_INT(4 DOWNTO 0) <= READ_ADDR(4 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE='1',WRITE_ADDR_INT,READ_ADDR_INT) ;
DINA <= DINA_INT ;
CHECK_DATA <= DO_READ;
RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 24
)
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_READ,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR
);
WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN
GENERIC MAP(
C_MAX_DEPTH => 24 )
PORT MAP(
CLK => CLK,
RST => RST,
EN => DO_WRITE,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR
);
WR_DATA_GEN_INST:ENTITY work.DATA_GEN
GENERIC MAP (
DATA_GEN_WIDTH => 24,
DOUT_WIDTH => 24,
DATA_PART_CNT => DATA_PART_CNT_A,
SEED => 2
)
PORT MAP (
CLK => CLK,
RST => RST,
EN => DO_WRITE,
DATA_OUT => DINA_INT
);
WR_RD_PROCESS: PROCESS (CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST='1') THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
ELSIF(COUNT_NO < 4) THEN
DO_WRITE <= '1';
DO_READ <= '0';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO< 8) THEN
DO_WRITE <= '0';
DO_READ <= '1';
COUNT_NO <= COUNT_NO + 1;
ELSIF(COUNT_NO=8) THEN
DO_WRITE <= '0';
DO_READ <= '0';
COUNT_NO <= 0 ;
END IF;
END IF;
END PROCESS;
BEGIN_SHIFT_REG: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(0),
CLK => CLK,
RST => RST,
D => DO_READ
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_SRAM
PORT MAP(
Q => DO_READ_REG(I),
CLK => CLK,
RST => RST,
D => DO_READ_REG(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG;
WEA(0) <= IF_THEN_ELSE(DO_WRITE='1','1','0') ;
END ARCHITECTURE;
| bsd-2-clause | eed4f27ace34018d0cf43da2b9e437f3 | 0.557891 | 3.773566 | false | false | false | false |
esar/hdmilight-v1 | fpga/avr/data_path.vhd | 2 | 10,103 | -------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: data_path - Behavioral
-- Create Date: 13:24:10 10/29/2009
-- Description: the data path of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
use work.common.ALL;
entity data_path is
port( I_CLK : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector( 7 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic);
end data_path;
architecture Behavioral of data_path is
component alu
port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_D : in std_logic_vector(15 downto 0);
I_D0 : in std_logic;
I_DIN : in std_logic_vector( 7 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector( 7 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_R : in std_logic_vector(15 downto 0);
I_R0 : in std_logic;
I_RSEL : in std_logic_vector( 1 downto 0);
Q_FLAGS : out std_logic_vector( 9 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal A_DOUT : std_logic_vector(15 downto 0);
signal A_FLAGS : std_logic_vector( 9 downto 0);
component register_file
port ( I_CLK : in std_logic;
I_AMOD : in std_logic_vector( 5 downto 0);
I_COND : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_RRRR : in std_logic_vector( 4 downto 1);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic;
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_CC : out std_logic;
Q_D : out std_logic_vector(15 downto 0);
Q_FLAGS : out std_logic_vector( 7 downto 0);
Q_R : out std_logic_vector(15 downto 0);
Q_S : out std_logic_vector( 7 downto 0);
Q_Z : out std_logic_vector(15 downto 0));
end component;
signal F_ADR : std_logic_vector(15 downto 0);
signal F_CC : std_logic;
signal F_D : std_logic_vector(15 downto 0);
signal F_FLAGS : std_logic_vector( 7 downto 0);
signal F_R : std_logic_vector(15 downto 0);
signal F_S : std_logic_vector( 7 downto 0);
signal F_Z : std_logic_vector(15 downto 0);
component data_mem
port ( I_CLK : in std_logic;
I_ADR : in std_logic_vector(10 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_WE : in std_logic_vector( 1 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal M_DOUT : std_logic_vector(15 downto 0);
signal L_DIN : std_logic_vector( 7 downto 0);
signal L_WE_SRAM : std_logic_vector( 1 downto 0);
signal L_FLAGS_98 : std_logic_vector( 9 downto 8);
begin
alui : alu
port map( I_ALU_OP => I_ALU_OP,
I_BIT => I_BIT,
I_D => F_D,
I_D0 => I_DDDDD(0),
I_DIN => L_DIN,
I_FLAGS => F_FLAGS,
I_IMM => I_IMM(7 downto 0),
I_PC => I_PC,
I_R => F_R,
I_R0 => I_RRRRR(0),
I_RSEL => I_RSEL,
Q_FLAGS => A_FLAGS,
Q_DOUT => A_DOUT);
regs : register_file
port map( I_CLK => I_CLK,
I_AMOD => I_AMOD,
I_COND(3) => I_OPC(10),
I_COND(2 downto 0)=> I_OPC(2 downto 0),
I_DDDDD => I_DDDDD,
I_DIN => A_DOUT,
I_FLAGS => A_FLAGS(7 downto 0),
I_IMM => I_IMM,
I_RRRR => I_RRRRR(4 downto 1),
I_WE_01 => I_WE_01,
I_WE_D => I_WE_D,
I_WE_F => I_WE_F,
I_WE_M => I_WE_M(0),
I_WE_XYZS => I_WE_XYZS,
Q_ADR => F_ADR,
Q_CC => F_CC,
Q_D => F_D,
Q_FLAGS => F_FLAGS,
Q_R => F_R,
Q_S => F_S, -- Q_Rxx(F_ADR)
Q_Z => F_Z);
sram : data_mem
port map( I_CLK => I_CLK,
I_ADR => F_ADR(10 downto 0),
I_DIN => A_DOUT,
I_WE => L_WE_SRAM,
Q_DOUT => M_DOUT);
-- remember A_FLAGS(9 downto 8) (within the current instruction).
--
flg98: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
L_FLAGS_98 <= A_FLAGS(9 downto 8);
end if;
end process;
-- whether PC shall be loaded with NEW_PC or not.
-- I.e. if a branch shall be taken or not.
--
process(I_PC_OP, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)
when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR
when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z
when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack
when others => Q_LOAD_PC <= '0'; -- no.
end case;
end process;
-- whether the next instruction shall be skipped or not.
--
process(I_PC_OP, L_FLAGS_98, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_SKIP <= F_CC; -- if cond met
when PC_LD_I => Q_SKIP <= '1'; -- yes
when PC_LD_Z => Q_SKIP <= '1'; -- yes
when PC_LD_S => Q_SKIP <= '1'; -- yes
when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set
when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set
when others => Q_SKIP <= '0'; -- no.
end case;
end process;
Q_ADR <= F_ADR;
Q_DOUT <= A_DOUT(7 downto 0);
Q_INT_ENA <= A_FLAGS(7);
Q_OPC <= I_OPC;
Q_PC <= I_PC;
Q_RD_IO <= '0' when (F_ADR < X"20")
else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
else '0';
Q_WE_IO <= '0' when (F_ADR < X"20")
else I_WE_M(0) when (F_ADR < X"5D")
else '0';
L_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;
L_DIN <= I_DIN when (I_PMS = '1')
else F_S when (F_ADR < X"0020")
else I_DIN when (F_ADR < X"005D")
else F_S when (F_ADR < X"0060")
else M_DOUT(7 downto 0);
-- compute potential new PC value from Z, (SP), or IMM.
--
Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL
else M_DOUT when I_PC_OP = PC_LD_S -- RET, RETI
else I_JADR; -- JMP adr
end Behavioral;
| gpl-2.0 | 2d0ab086ec1742be4cc66a7f0d391b76 | 0.445313 | 3.371038 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_16/Lab_16_1/PZP_CONST.vhd | 1 | 1,003 | library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PZP_CONST is
port(clk : in std_logic;
cs : in std_logic;
rd : in std_logic;
address : in std_logic_vector(3 downto 0);
data_out: out std_logic_vector(7 downto 0));
end PZP_CONST;
architecture behav of PZP_CONST is
type PZP_CONST_array is array(0 to 31)
of std_logic_vector(7 downto 0);
constant content: PZP_CONST_array := (
0=> "00000000",
1=> "00000001",
2=> "00000010",
3=> "00000100",
4=> "00000101",
5=> "00000110",
6=> "00000110",
7=> "00000111",
8=> "00001000",
9=> "00001001",
10=> "00001010",
11=> "00001011",
12=> "00001100",
13=> "00001101",
14=> "00001110",
15=> "00001111",
others=> "11111111");
begin
process(clk, cs)
begin
if(cs = '1') then
data_out <= "ZZZZZZZZ";
elsif(clk'event and clk = '1') then
if rd = '1' then
data_out <= content(to_integer (unsigned(address)));
else
data_out <= "ZZZZZZZZ";
end if;
end if;
end process;
end behav; | gpl-2.0 | ead476cf7310f6b95975a8548fe56d18 | 0.62014 | 2.817416 | false | false | false | false |
esar/hdmilight-v1 | fpga/ipcore_dir/configRam.vhd | 2 | 6,113 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file configRam.vhd when simulating
-- the core, configRam. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY configRam IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END configRam;
ARCHITECTURE configRam_a OF configRam IS
-- synthesis translate_off
COMPONENT wrapped_configRam
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_configRam USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 9,
c_addrb_width => 9,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan3",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 512,
c_read_depth_b => 512,
c_read_width_a => 32,
c_read_width_b => 32,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 512,
c_write_depth_b => 512,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 32,
c_write_width_b => 32,
c_xdevicefamily => "spartan3e"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_configRam
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END configRam_a;
| gpl-2.0 | cd2ef8f50d93fbb52c9997644a3fd353 | 0.539342 | 3.903576 | false | true | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/controller-risotto-2.vhd | 1 | 4,736 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.custom_pkg.all;
entity controller is
port ( clk : in std_logic;
rst : in std_logic;
wea : in std_logic_vector(0 downto 0);
dina_image : in std_logic_vector(7 downto 0);
dina_weights : in std_logic_vector(23 downto 0);
addra_image : in std_logic_vector(4 downto 0);
addra_weights : in std_logic_vector(4 downto 0)
);
end controller;
architecture Behavioral of controller is
signal'
num_neurons, input : std_logic_vector(7 downto 0);
signal layer : layer_type;
constant num_hidden_neurons : Integer := 3;
signal weight_hid, weight : eight_bit(num_hidden_neurons-1 downto 0);
signal output_hid : std_logic_vector(7 downto 0);
signal shift_over_flag, active_activation, rst_layer : std_logic := '0';
signal curr_state,next_state : layer_type;
COMPONENT test_image
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT weight_hid
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT weight_out
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT;
COMPONENT hidden_layer
port ( clk : in std_logic ;
num_neurons : in std_logic_vector(7 downto 0);
layer : in layer_type;
rst : in std_logic ;
image : in std_logic_vector(7 downto 0);
weight_hid : in eight_bit(num_hidden_neurons-1 downto 0);
shift_over_flag : out std_logic;
active_ativation : out std_logic;
output_hid : out std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
test_image_map : test_image
PORT MAP (clk, wea, addra_image, dina_image, image);
layer_map : hidden_layer
PORT MAP (clk, num_neurons, layer, rst_layer, image, weight, shift_over_flag, active_activation, output_hid);
weight_hid_map: weight_hid
PORT MAP (clk, "0", addr_weight_hid, in_weight_hid, out_weight_hid);
weight_out_map: weight_out
PORT MAP (clk, "0", addr_weight_out, in_weight_out, out_weight_out);
transition : process (clk,reset)
begin
if rst ='1' then
curr_state <= idle; --default state on reset.
elsif (rising_edge(clk)) then
if curr_state = weighted_sum_layer1 and active_activation = '0' then
curr_state <= next_state; --state change.
end if;
end process;
next_state_logic : process (curr_state, shift_over_flag, active_activation) begin
case curr_state is
when idle =>
if active_activation = '0' then
next_state <= weighted_sum_layer1;
else
next_state <= idle;
end if;
when weighted_sum_layer1 =>
if active_activation = '1' then
next_state <= activate_layer1;
else
next_state <= weighted_sum_layer1;
end if;
when activate_layer1 =>
if shift_over_flag = '1' then
next_state <= rst_layer;
else
next_state <= activate_layer1;
end if;
when reset_layer =>
if active_activation = '0' then
next_state <= weighted_sum_layer2;
else
next_state <= rst_layer;
end if;
when weighted_sum_layer2 =>
if active_activation = '1' then
next_state <= activate_layer2;
else
next_state <= weighted_sum_layer2;
end if;
when activate_layer2 =>
if shift_over_flag = '1' then
next_state <= idle;
else
next_state <= activate_layer2;
end if;
end case;
end process;
Output: process (curr_state) begin
case curr_state is
when idle =>
rst_layer <= '1';
num_neurons <= (others=>'0');
layer <= idle;
image <= (others=>'0');
weight <= (others=>'0');
when weighted_sum_layer1 =>
rst_layer <= '0';
num_neurons <= "00000100";
layer <= weighted_sum_layer1;
image <= douta_image;
weight <= "00001";
when activate_layer1 =>
rst_layer <= '0';
num_neurons <= "00000100";
layer <= activate_layer1;
image <= (others=>'0');
weight <= (others=>'0');
when reset_layer =>
rst_layer <= '1';
num_neurons <= (others=>'0');
layer <= idle;
image <= (others=>'0');
weight <= (others=>'0');
when weighted_sum_layer2 =>
rst_layer <= '0';
num_neurons <= "00000011";
layer <= weighted_sum_layer2;
image <= douta_image;
weight <= "00010";
end case;
end process;
end process;
end Behavioral;
| bsd-2-clause | 9732b9abc9402feef4442022bfa5b778 | 0.628378 | 3.103539 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/iic.vhd | 2 | 29,173 | -------------------------------------------------------------------------------
-- iic.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2011 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic.vhd
-- Version: v1.01.b
-- Description:
-- This file contains the top level file for the iic Bus
-- Interface.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- - Fixed the CR#613282
-- ~~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library axi_iic_v2_0;
use axi_iic_v2_0.iic_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- C_NUM_IIC_REGS -- Number of IIC Registers
-- C_S_AXI_ACLK_FREQ_HZ -- Specifies AXI clock frequency
-- C_IIC_FREQ -- Maximum frequency of Master Mode in Hz
-- C_TEN_BIT_ADR -- 10 bit slave addressing
-- C_GPO_WIDTH -- Width of General purpose output vector
-- C_SCL_INERTIAL_DELAY -- SCL filtering
-- C_SDA_INERTIAL_DELAY -- SDA filtering
-- C_SDA_LEVEL -- SDA level
-- C_TX_FIFO_EXIST -- IIC transmit FIFO exist
-- C_RC_FIFO_EXIST -- IIC receive FIFO exist
-- C_S_AXI_ADDR_WIDTH -- Width of AXI Address Bus (in bits)
-- C_S_AXI_DATA_WIDTH -- Width of the AXI Data Bus (in bits)
-- C_FAMILY -- XILINX FPGA family
-------------------------------------------------------------------------------
-- Definition of ports:
--
-- System Signals
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESETN -- AXI Reset
-- IP2INTC_Irpt -- System interrupt output
--
-- AXI signals
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
--
-- IIC Signals
-- Sda_I -- IIC serial data input
-- Sda_O -- IIC serial data output
-- Sda_T -- IIC seral data output enable
-- Scl_I -- IIC serial clock input
-- Scl_O -- IIC serial clock output
-- Scl_T -- IIC serial clock output enable
-- Gpo -- General purpose outputs
--
-------------------------------------------------------------------------------
-- Entity section
-------------------------------------------------------------------------------
entity iic is
generic (
-- System Generics
C_NUM_IIC_REGS : integer := 10;
--IIC Generics to be set by user
C_S_AXI_ACLK_FREQ_HZ : integer := 100000000;
C_IIC_FREQ : integer := 100000;
C_TEN_BIT_ADR : integer := 0;
C_GPO_WIDTH : integer := 0;
C_SCL_INERTIAL_DELAY : integer := 0;
C_SDA_INERTIAL_DELAY : integer := 0;
C_SDA_LEVEL : integer := 1;
C_SMBUS_PMBUS_HOST : integer := 0; -- SMBUS/PMBUS support
C_TX_FIFO_EXIST : boolean := TRUE;
C_RC_FIFO_EXIST : boolean := TRUE;
C_S_AXI_ADDR_WIDTH : integer := 9;
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_FAMILY : string := "virtex7";
C_DEFAULT_VALUE : std_logic_vector(7 downto 0) := X"FF"
);
port
(
-- System signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
IIC2INTC_Irpt : out std_logic;
-- AXI signals
S_AXI_AWADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- IIC Bus Signals
Sda_I : in std_logic;
Sda_O : out std_logic;
Sda_T : out std_logic;
Scl_I : in std_logic;
Scl_O : out std_logic;
Scl_T : out std_logic;
Gpo : out std_logic_vector(0 to C_GPO_WIDTH-1)
);
end entity iic;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture RTL of iic is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of RTL : architecture is "yes";
-- Calls the function from the iic_pkg.vhd
constant C_SIZE : integer := num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ, C_IIC_FREQ);
signal Msms_rst : std_logic;
signal Msms_set : std_logic;
signal Rsta_rst : std_logic;
signal Dtc : std_logic;
signal Rdy_new_xmt : std_logic;
signal New_rcv_dta : std_logic;
signal Ro_prev : std_logic;
signal Dtre : std_logic;
signal Bb : std_logic;
signal Aas : std_logic;
signal Al : std_logic;
signal Srw : std_logic;
signal Txer : std_logic;
signal Tx_under_prev : std_logic;
signal Abgc : std_logic;
signal Data_i2c : std_logic_vector(0 to 7);
signal Adr : std_logic_vector(0 to 7);
signal Ten_adr : std_logic_vector(5 to 7);
signal Cr : std_logic_vector(0 to 7);
signal Drr : std_logic_vector(0 to 7);
signal Dtr : std_logic_vector(0 to 7);
signal Tx_fifo_data : std_logic_vector(0 to 7);
signal Tx_data_exists : std_logic;
signal Tx_fifo_wr : std_logic;
signal Tx_fifo_wr_i : std_logic;
signal Tx_fifo_wr_d : std_logic;
signal Tx_fifo_rd : std_logic;
signal Tx_fifo_rd_i : std_logic;
signal Tx_fifo_rd_d : std_logic;
signal Tx_fifo_rst : std_logic;
signal Tx_fifo_full : std_logic;
signal Tx_addr : std_logic_vector(0 to TX_FIFO_BITS - 1);
signal Rc_fifo_data : std_logic_vector(0 to 7);
signal Rc_fifo_wr : std_logic;
signal Rc_fifo_wr_i : std_logic;
signal Rc_fifo_wr_d : std_logic;
signal Rc_fifo_rd : std_logic;
signal Rc_fifo_rd_i : std_logic;
signal Rc_fifo_rd_d : std_logic;
signal Rc_fifo_full : std_logic;
signal Rc_Data_Exists : std_logic;
signal Rc_addr : std_logic_vector(0 to RC_FIFO_BITS -1);
signal Bus2IIC_Clk : std_logic;
signal Bus2IIC_Reset : std_logic;
signal IIC2Bus_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1) :=
(others => '0');
signal IIC2Bus_IntrEvent : std_logic_vector(0 to 7) := (others => '0');
signal Bus2IIC_Addr : std_logic_vector(0 to C_S_AXI_ADDR_WIDTH - 1);
signal Bus2IIC_Data : std_logic_vector(0 to C_S_AXI_DATA_WIDTH - 1);
signal Bus2IIC_RNW : std_logic;
signal Bus2IIC_RdCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
signal Bus2IIC_WrCE : std_logic_vector(0 to C_NUM_IIC_REGS - 1);
-- signals for dynamic start/stop
signal ctrlFifoDin : std_logic_vector(0 to 1);
signal dynamic_MSMS : std_logic_vector(0 to 1);
signal dynRstaSet : std_logic;
signal dynMsmsSet : std_logic;
signal txak : std_logic;
signal earlyAckDataState : std_logic;
signal ackDataState : std_logic;
signal earlyAckHdr : std_logic;
signal cr_txModeSelect_set : std_logic;
signal cr_txModeSelect_clr : std_logic;
signal txFifoRd : std_logic;
signal Msms_rst_r : std_logic;
signal ctrl_fifo_wr_i : std_logic;
-- Cleaned up inputs
signal scl_clean : std_logic;
signal sda_clean : std_logic;
-- Timing Parameters
signal Timing_param_tsusta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsusto : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thdsta : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tsudat : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tbuf : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thigh : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_tlow : std_logic_vector(C_SIZE-1 downto 0);
signal Timing_param_thddat : std_logic_vector(C_SIZE-1 downto 0);
----------Mathew
-- signal transfer_done : std_logic;
signal reg_empty : std_logic;
----------Mathew
begin
----------------------------------------------------------------------------
-- axi_ipif_ssp1 instantiation
----------------------------------------------------------------------------
X_AXI_IPIF_SSP1 : entity axi_iic_v2_0.axi_ipif_ssp1
generic map (
C_NUM_IIC_REGS => C_NUM_IIC_REGS,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
-- width of the AXI Address Bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH,
-- Width of AXI Data Bus (in bits) Must be 32
C_FAMILY => C_FAMILY)
port map (
-- System signals ----------------------------------------------------
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent, -- IIC Interrupt events
IIC2INTC_Irpt => IIC2INTC_Irpt,
-- AXI Interface signals --------------
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_RREADY => S_AXI_RREADY,
-- IP Interconnect (IPIC) port signals used by the IIC registers. ----
Bus2IIC_Clk => Bus2IIC_Clk,
Bus2IIC_Reset => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data,
Bus2IIC_RNW => Bus2IIC_RNW,
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data
);
----------------------------------------------------------------------------
-- reg_interface instantiation
----------------------------------------------------------------------------
REG_INTERFACE_I : entity axi_iic_v2_0.reg_interface
generic map (
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST,
C_TX_FIFO_EXIST => C_TX_FIFO_EXIST ,
C_TX_FIFO_BITS => 4 ,
C_RC_FIFO_EXIST => C_RC_FIFO_EXIST ,
C_RC_FIFO_BITS => 4 ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR ,
C_GPO_WIDTH => C_GPO_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
C_SIZE => C_SIZE ,
C_NUM_IIC_REGS => C_NUM_IIC_REGS ,
C_DEFAULT_VALUE => C_DEFAULT_VALUE
)
port map (
Clk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Bus2IIC_Addr => Bus2IIC_Addr,
Bus2IIC_Data => Bus2IIC_Data(0 to C_S_AXI_DATA_WIDTH - 1),
Bus2IIC_RdCE => Bus2IIC_RdCE,
Bus2IIC_WrCE => Bus2IIC_WrCE,
IIC2Bus_Data => IIC2Bus_Data(0 to C_S_AXI_DATA_WIDTH - 1),
IIC2Bus_IntrEvent => IIC2Bus_IntrEvent,
Gpo => Gpo(0 to C_GPO_WIDTH-1),
Cr => Cr,
Dtr => Dtr,
Drr => Drr,
Adr => Adr,
Ten_adr => Ten_adr,
Msms_set => Msms_set,
Msms_rst => Msms_rst,
DynMsmsSet => dynMsmsSet,
DynRstaSet => dynRstaSet,
Cr_txModeSelect_set => cr_txModeSelect_set,
Cr_txModeSelect_clr => cr_txModeSelect_clr,
Rsta_rst => Rsta_rst,
Rdy_new_xmt => Rdy_new_xmt,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Aas => Aas,
Bb => Bb,
Srw => Srw,
Al => Al,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Tx_fifo_data => Tx_fifo_data(0 to 7),
Tx_data_exists => Tx_data_exists,
Tx_fifo_wr => Tx_fifo_wr,
Tx_fifo_rd => Tx_fifo_rd,
Tx_fifo_full => Tx_fifo_full,
Tx_fifo_rst => Tx_fifo_rst,
Tx_addr => Tx_addr(0 to TX_FIFO_BITS - 1),
Rc_fifo_data => Rc_fifo_data(0 to 7),
Rc_fifo_wr => Rc_fifo_wr,
Rc_fifo_rd => Rc_fifo_rd,
Rc_fifo_full => Rc_fifo_full,
Rc_Data_Exists => Rc_Data_Exists,
Rc_addr => Rc_addr(0 to RC_FIFO_BITS - 1),
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- The V5 inputs are so fast that they typically create glitches longer then
-- the clock period due to the extremely slow rise/fall times on SDA/SCL
-- signals. The inertial delay filter removes these.
----------------------------------------------------------------------------
FILTER_I: entity axi_iic_v2_0.filter
generic map (
SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY, -- [range 0 to 255]
SDA_INERTIAL_DELAY => C_SDA_INERTIAL_DELAY -- [range 0 to 255]
)
port map
(
Sysclk => Bus2IIC_Clk,
Rst => Bus2IIC_Reset,
Scl_noisy => Scl_I,
Scl_clean => scl_clean,
Sda_noisy => Sda_I,
Sda_clean => sda_clean
);
----------------------------------------------------------------------------
-- iic_control instantiation
----------------------------------------------------------------------------
IIC_CONTROL_I : entity axi_iic_v2_0.iic_control
generic map
(
C_SCL_INERTIAL_DELAY => C_SCL_INERTIAL_DELAY,
C_S_AXI_ACLK_FREQ_HZ => C_S_AXI_ACLK_FREQ_HZ,
C_IIC_FREQ => C_IIC_FREQ,
C_SIZE => C_SIZE ,
C_TEN_BIT_ADR => C_TEN_BIT_ADR,
C_SDA_LEVEL => C_SDA_LEVEL,
C_SMBUS_PMBUS_HOST => C_SMBUS_PMBUS_HOST
)
port map
(
Sys_clk => Bus2IIC_Clk,
Reset => Cr(7),
Sda_I => sda_clean,
Sda_O => Sda_O,
Sda_T => Sda_T,
Scl_I => scl_clean,
Scl_O => Scl_O,
Scl_T => Scl_T,
Timing_param_tsusta => Timing_param_tsusta,
Timing_param_tsusto => Timing_param_tsusto,
Timing_param_thdsta => Timing_param_thdsta,
Timing_param_tsudat => Timing_param_tsudat,
Timing_param_tbuf => Timing_param_tbuf ,
Timing_param_thigh => Timing_param_thigh ,
Timing_param_tlow => Timing_param_tlow ,
Timing_param_thddat => Timing_param_thddat,
Txak => txak,
Msms => Cr(5),
Msms_set => Msms_set,
Msms_rst => Msms_rst_r,
Rsta => Cr(2),
Rsta_rst => Rsta_rst,
Tx => Cr(4),
Gc_en => Cr(1),
Dtr => Dtr,
Adr => Adr,
Ten_adr => Ten_adr,
Bb => Bb,
Dtc => Dtc,
Aas => Aas,
Al => Al,
Srw => Srw,
Txer => Txer,
Tx_under_prev => Tx_under_prev,
Abgc => Abgc,
Data_i2c => Data_i2c,
New_rcv_dta => New_rcv_dta,
Ro_prev => Ro_prev,
Dtre => Dtre,
Rdy_new_xmt => Rdy_new_xmt,
EarlyAckHdr => earlyAckHdr,
EarlyAckDataState => earlyAckDataState,
AckDataState => ackDataState,
reg_empty => reg_empty
);
----------------------------------------------------------------------------
-- Transmitter FIFO instantiation
----------------------------------------------------------------------------
WRITE_FIFO_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => Tx_fifo_wr_i,
Data_In => Bus2IIC_Data(24 to 31),
FIFO_Read => txFifoRd,
Data_Out => Tx_fifo_data(0 to 7),
FIFO_Full => Tx_fifo_full,
Data_Exists => Tx_data_exists,
Addr => Tx_addr(0 to TX_FIFO_BITS - 1)
);
-------Mathew
-- transfer_done <= '1' when Tx_data_exists = '0' and reg_empty ='1' else '0';
-------Mathew
----------------------------------------------------------------------------
-- Receiver FIFO instantiation
----------------------------------------------------------------------------
READ_FIFO_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => DATA_BITS,
C_DEPTH => RC_FIFO_BITS
)
port map (
Clk => Bus2IIC_Clk,
Reset => Bus2IIC_Reset,
FIFO_Write => Rc_fifo_wr_i,
Data_In => Data_i2c(0 to 7),
FIFO_Read => Rc_fifo_rd_i,
Data_Out => Rc_fifo_data(0 to 7),
FIFO_Full => Rc_fifo_full,
Data_Exists => Rc_Data_Exists,
Addr => Rc_addr(0 to RC_FIFO_BITS - 1)
);
----------------------------------------------------------------------------
-- PROCESS: TX_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
TX_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Tx_fifo_wr_d <= '0';
Tx_fifo_rd_d <= '0';
else
Tx_fifo_wr_d <= Tx_fifo_wr;
Tx_fifo_rd_d <= Tx_fifo_rd;
end if;
end if;
end process TX_FIFO_WR_GEN;
----------------------------------------------------------------------------
-- PROCESS: RC_FIFO_WR_GEN
-- purpose: generate TX FIFO write control signals
----------------------------------------------------------------------------
RC_FIFO_WR_GEN : process(Bus2IIC_Clk)
begin
if(Bus2IIC_Clk'event and Bus2IIC_Clk = '1') then
if(Bus2IIC_Reset = '1') then
Rc_fifo_wr_d <= '0';
Rc_fifo_rd_d <= '0';
else
Rc_fifo_wr_d <= Rc_fifo_wr;
Rc_fifo_rd_d <= Rc_fifo_rd;
end if;
end if;
end process RC_FIFO_WR_GEN;
Tx_fifo_wr_i <= Tx_fifo_wr and (not Tx_fifo_wr_d);
Rc_fifo_wr_i <= Rc_fifo_wr and (not Rc_fifo_wr_d);
Tx_fifo_rd_i <= Tx_fifo_rd and (not Tx_fifo_rd_d);
Rc_fifo_rd_i <= Rc_fifo_rd and (not Rc_fifo_rd_d);
----------------------------------------------------------------------------
-- Dynamic master interface
-- Dynamic master start/stop and control logic
----------------------------------------------------------------------------
DYN_MASTER_I : entity axi_iic_v2_0.dynamic_master
port map (
Clk => Bus2IIC_Clk ,
Rst => Tx_fifo_rst ,
dynamic_MSMS => dynamic_MSMS ,
Cr => Cr ,
Tx_fifo_rd_i => Tx_fifo_rd_i ,
Tx_data_exists => Tx_data_exists ,
ackDataState => ackDataState ,
Tx_fifo_data => Tx_fifo_data ,
earlyAckHdr => earlyAckHdr ,
earlyAckDataState => earlyAckDataState ,
Bb => Bb ,
Msms_rst_r => Msms_rst_r ,
dynMsmsSet => dynMsmsSet ,
dynRstaSet => dynRstaSet ,
Msms_rst => Msms_rst ,
txFifoRd => txFifoRd ,
txak => txak ,
cr_txModeSelect_set => cr_txModeSelect_set,
cr_txModeSelect_clr => cr_txModeSelect_clr
);
-- virtual reset. Since srl fifo address is rst at the same time, only the
-- first entry in the srl fifo needs to have a value of '00' to appear
-- reset. Also, force data to 0 if a byte write is done to the txFifo.
ctrlFifoDin <= Bus2IIC_Data(22 to 23) when (Tx_fifo_rst = '0' and
Bus2IIC_Reset = '0') else
"00";
-- continuously write srl fifo while reset active
ctrl_fifo_wr_i <= Tx_fifo_rst or Bus2IIC_Reset or Tx_fifo_wr_i;
----------------------------------------------------------------------------
-- Control FIFO instantiation
-- fifo used to set/reset MSMS bit in control register to create automatic
-- START/STOP conditions
----------------------------------------------------------------------------
WRITE_FIFO_CTRL_I : entity axi_iic_v2_0.srl_fifo
generic map (
C_DATA_BITS => 2,
C_DEPTH => TX_FIFO_BITS
)
port map
(
Clk => Bus2IIC_Clk,
Reset => Tx_fifo_rst,
FIFO_Write => ctrl_fifo_wr_i,
Data_In => ctrlFifoDin,
FIFO_Read => txFifoRd,
Data_Out => dynamic_MSMS,
FIFO_Full => open,
Data_Exists => open,
Addr => open
);
end architecture RTL;
| gpl-3.0 | c584c2312b2c4fb16723d178174cac3d | 0.437528 | 4.014449 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_bram4096x64/simulation/k7_bram4096x64_synth.vhd | 1 | 10,410 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_bram4096x64_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY k7_bram4096x64_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE k7_bram4096x64_synth_ARCH OF k7_bram4096x64_synth IS
COMPONENT k7_bram4096x64_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 63 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(63 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 64,
READ_WIDTH => 64 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: k7_bram4096x64_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| gpl-2.0 | 2336723b6f2905dc75d7f9221daf7098 | 0.556964 | 3.581011 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_rst_M_AXI_GP1_ACLK_100M_0/synth/cpu_rst_M_AXI_GP1_ACLK_100M_0.vhd | 1 | 6,707 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY cpu_rst_M_AXI_GP1_ACLK_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_rst_M_AXI_GP1_ACLK_100M_0;
ARCHITECTURE cpu_rst_M_AXI_GP1_ACLK_100M_0_arch OF cpu_rst_M_AXI_GP1_ACLK_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_rst_M_AXI_GP1_ACLK_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF cpu_rst_M_AXI_GP1_ACLK_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF cpu_rst_M_AXI_GP1_ACLK_100M_0_arch : ARCHITECTURE IS "cpu_rst_M_AXI_GP1_ACLK_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF cpu_rst_M_AXI_GP1_ACLK_100M_0_arch: ARCHITECTURE IS "cpu_rst_M_AXI_GP1_ACLK_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END cpu_rst_M_AXI_GP1_ACLK_100M_0_arch;
| gpl-3.0 | 6dd45c3dc3555c4cd77520b986abf617 | 0.712241 | 3.37544 | false | false | false | false |
olgirard/openmsp430 | core/synthesis/xilinx/src/coregen/virtex6_dmem.vhd | 1 | 5,148 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file virtex6_dmem.vhd when simulating
-- the core, virtex6_dmem. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY virtex6_dmem IS
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
END virtex6_dmem;
ARCHITECTURE virtex6_dmem_a OF virtex6_dmem IS
-- synthesis translate_off
component wrapped_virtex6_dmem
port (
clka: IN std_logic;
ena: IN std_logic;
wea: IN std_logic_VECTOR(1 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
dina: IN std_logic_VECTOR(15 downto 0);
douta: OUT std_logic_VECTOR(15 downto 0));
end component;
-- Configuration specification
for all : wrapped_virtex6_dmem use entity XilinxCoreLib.blk_mem_gen_v3_3(behavioral)
generic map(
c_has_regceb => 0,
c_has_regcea => 0,
c_mem_type => 0,
c_rstram_b => 0,
c_rstram_a => 0,
c_has_injecterr => 0,
c_rst_type => "SYNC",
c_prim_type => 1,
c_read_width_b => 16,
c_initb_val => "0",
c_family => "virtex6",
c_read_width_a => 16,
c_disable_warn_bhv_coll => 0,
c_write_mode_b => "WRITE_FIRST",
c_init_file_name => "no_coe_file_loaded",
c_write_mode_a => "WRITE_FIRST",
c_mux_pipeline_stages => 0,
c_has_mem_output_regs_b => 0,
c_has_mem_output_regs_a => 0,
c_load_init_file => 0,
c_xdevicefamily => "virtex6",
c_write_depth_b => 1024,
c_write_depth_a => 1024,
c_has_rstb => 0,
c_has_rsta => 0,
c_has_mux_output_regs_b => 0,
c_inita_val => "0",
c_has_mux_output_regs_a => 0,
c_addra_width => 10,
c_addrb_width => 10,
c_default_data => "0",
c_use_ecc => 0,
c_algorithm => 1,
c_disable_warn_bhv_range => 0,
c_write_width_b => 16,
c_write_width_a => 16,
c_read_depth_b => 1024,
c_read_depth_a => 1024,
c_byte_size => 8,
c_sim_collision_check => "ALL",
c_common_clk => 0,
c_wea_width => 2,
c_has_enb => 0,
c_web_width => 2,
c_has_ena => 1,
c_use_byte_web => 1,
c_use_byte_wea => 1,
c_rst_priority_b => "CE",
c_rst_priority_a => "CE",
c_use_default_data => 0);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_virtex6_dmem
port map (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta);
-- synthesis translate_on
END virtex6_dmem_a;
| bsd-3-clause | d5699c077d7dd26ad4db702e4913fac8 | 0.559246 | 3.682403 | false | false | false | false |
peteut/nvc | test/regress/record13.vhd | 1 | 1,152 | entity record13 is
end entity;
architecture test of record13 is
type rec is record
t : character; -- This struct must be packed
x, y : integer;
end record;
type rec_array is array (positive range <>) of rec;
function resolve(x : rec_array) return rec is
variable r : rec := ('0', 0, 0);
begin
assert x'left = 1;
assert x'right = x'length;
for i in x'range loop
report "x(" & integer'image(i) & ") = (" & integer'image(x(i).x)
& ", " & integer'image(x(i).y) & ")";
r.x := r.x + x(i).x;
r.y := r.y + x(i).y;
end loop;
return r;
end function;
subtype resolved_rec is resolve rec;
signal sig : resolved_rec := ('0', 0, 0);
begin
p1: process is
begin
sig <= ('a', 1, 2);
wait for 1 ns;
sig.x <= 5;
wait;
end process;
p2: process is
begin
sig <= ('b', 4, 5);
wait for 1 ns;
assert sig = ('0', 5, 7);
wait for 1 ns;
assert sig = ('0', 9, 7);
wait;
end process;
end architecture;
| gpl-3.0 | c021dd21baa740abaf8082a61890156f | 0.477431 | 3.522936 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/adder_subtractor_component.vhd | 1 | 5,618 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 09-04-2017
-- Package Name: alu/components
-- Module Name: ADDER_SUBTRACTOR_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ADDER_SUBTRACTOR_COMPONENT is
port(
CARRY_IN : in std_logic;
INPUT1 : in std_logic_vector(16 - 1 downto 0);
INPUT2 : in std_logic_vector(16 - 1 downto 0);
IS_SUB : in std_logic; -- 0 for add and 1 for subtraction
SUM : out std_logic_vector(16 - 1 downto 0);
CARRY_OUT : out std_logic;
OVERFLOW : out std_logic
);
end entity;
architecture ADDER_SUBTRACTOR_COMPONENT_ARCH of ADDER_SUBTRACTOR_COMPONENT is
component FULL_ADDER is
port(
CIN : in std_logic;
A : in std_logic;
B : in std_logic;
SUM : out std_logic;
CARRY : out std_logic
);
end component;
signal CARRIES : std_logic_vector(16 downto 0);
signal B_MUXED : std_logic_vector(16 - 1 downto 0);
begin
CARRIES(0) <= IS_SUB xor CARRY_IN;
with IS_SUB select B_MUXED(0) <=
INPUT2(0) when '0',
not INPUT2(0) when '1',
INPUT2(0) when others;
with IS_SUB select B_MUXED(1) <=
INPUT2(1) when '0',
not INPUT2(1) when '1',
INPUT2(1) when others;
with IS_SUB select B_MUXED(2) <=
INPUT2(2) when '0',
not INPUT2(2) when '1',
INPUT2(2) when others;
with IS_SUB select B_MUXED(3) <=
INPUT2(3) when '0',
not INPUT2(3) when '1',
INPUT2(3) when others;
with IS_SUB select B_MUXED(4) <=
INPUT2(4) when '0',
not INPUT2(4) when '1',
INPUT2(4) when others;
with IS_SUB select B_MUXED(5) <=
INPUT2(5) when '0',
not INPUT2(5) when '1',
INPUT2(5) when others;
with IS_SUB select B_MUXED(6) <=
INPUT2(6) when '0',
not INPUT2(6) when '1',
INPUT2(6) when others;
with IS_SUB select B_MUXED(7) <=
INPUT2(7) when '0',
not INPUT2(7) when '1',
INPUT2(7) when others;
with IS_SUB select B_MUXED(8) <=
INPUT2(8) when '0',
not INPUT2(8) when '1',
INPUT2(8) when others;
with IS_SUB select B_MUXED(9) <=
INPUT2(9) when '0',
not INPUT2(9) when '1',
INPUT2(9) when others;
with IS_SUB select B_MUXED(10) <=
INPUT2(10) when '0',
not INPUT2(10) when '1',
INPUT2(10) when others;
with IS_SUB select B_MUXED(11) <=
INPUT2(11) when '0',
not INPUT2(11) when '1',
INPUT2(11) when others;
with IS_SUB select B_MUXED(12) <=
INPUT2(12) when '0',
not INPUT2(12) when '1',
INPUT2(12) when others;
with IS_SUB select B_MUXED(13) <=
INPUT2(13) when '0',
not INPUT2(13) when '1',
INPUT2(13) when others;
with IS_SUB select B_MUXED(14) <=
INPUT2(14) when '0',
not INPUT2(14) when '1',
INPUT2(14) when others;
with IS_SUB select B_MUXED(15) <=
INPUT2(15) when '0',
not INPUT2(15) when '1',
INPUT2(15) when others;
ADDER_0: FULL_ADDER
port map(
CIN => CARRIES(0),
A => INPUT1(0),
B => B_MUXED(0),
SUM => SUM(0),
CARRY => CARRIES(1)
);
ADDER_1: FULL_ADDER
port map(
CIN => CARRIES(1),
A => INPUT1(1),
B => B_MUXED(1),
SUM => SUM(1),
CARRY => CARRIES(2)
);
ADDER_2: FULL_ADDER
port map(
CIN => CARRIES(2),
A => INPUT1(2),
B => B_MUXED(2),
SUM => SUM(2),
CARRY => CARRIES(3)
);
ADDER_3: FULL_ADDER
port map(
CIN => CARRIES(3),
A => INPUT1(3),
B => B_MUXED(3),
SUM => SUM(3),
CARRY => CARRIES(4)
);
ADDER_4: FULL_ADDER
port map(
CIN => CARRIES(4),
A => INPUT1(4),
B => B_MUXED(4),
SUM => SUM(4),
CARRY => CARRIES(5)
);
ADDER_5: FULL_ADDER
port map(
CIN => CARRIES(5),
A => INPUT1(5),
B => B_MUXED(5),
SUM => SUM(5),
CARRY => CARRIES(6)
);
ADDER_6: FULL_ADDER
port map(
CIN => CARRIES(6),
A => INPUT1(6),
B => B_MUXED(6),
SUM => SUM(6),
CARRY => CARRIES(7)
);
ADDER_7: FULL_ADDER
port map(
CIN => CARRIES(7),
A => INPUT1(7),
B => B_MUXED(7),
SUM => SUM(7),
CARRY => CARRIES(8)
);
ADDER_8: FULL_ADDER
port map(
CIN => CARRIES(8),
A => INPUT1(8),
B => B_MUXED(8),
SUM => SUM(8),
CARRY => CARRIES(9)
);
ADDER_9: FULL_ADDER
port map(
CIN => CARRIES(9),
A => INPUT1(9),
B => B_MUXED(9),
SUM => SUM(9),
CARRY => CARRIES(10)
);
ADDER_10: FULL_ADDER
port map(
CIN => CARRIES(10),
A => INPUT1(10),
B => B_MUXED(10),
SUM => SUM(10),
CARRY => CARRIES(11)
);
ADDER_11: FULL_ADDER
port map(
CIN => CARRIES(11),
A => INPUT1(11),
B => B_MUXED(11),
SUM => SUM(11),
CARRY => CARRIES(12)
);
ADDER_12: FULL_ADDER
port map(
CIN => CARRIES(12),
A => INPUT1(12),
B => B_MUXED(12),
SUM => SUM(12),
CARRY => CARRIES(13)
);
ADDER_13: FULL_ADDER
port map(
CIN => CARRIES(13),
A => INPUT1(13),
B => B_MUXED(13),
SUM => SUM(13),
CARRY => CARRIES(14)
);
ADDER_14: FULL_ADDER
port map(
CIN => CARRIES(14),
A => INPUT1(14),
B => B_MUXED(14),
SUM => SUM(14),
CARRY => CARRIES(15)
);
ADDER_15: FULL_ADDER
port map(
CIN => CARRIES(15),
A => INPUT1(15),
B => B_MUXED(15),
SUM => SUM(15),
CARRY => CARRIES(16)
);
CARRY_OUT <= CARRIES(15) xor CARRIES(16);
end architecture; | gpl-3.0 | 0b473868ba0d34a1b3287e2d152ada11 | 0.51513 | 2.492458 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/prediction_tb.vhd | 1 | 1,601 | -- TestBench Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use work.custom_pkg.all;
ENTITY prediction_tb IS
END prediction_tb;
ARCHITECTURE behavior OF prediction_tb IS
-- Component Declaration
COMPONENT prediction
port
(clk : in std_logic;
enable : in std_logic;
output_hid : in eight_bit(num_neurons-1 downto 0);
predict : out std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL enable : std_logic := '0';
SIGNAL output_hid : eight_bit(num_neurons-1 downto 0) := ((others=> (others=>'0')));
--Outputs
SIGNAL predict : std_logic_vector(7 downto 0);
--Clock
constant clk_period : time := 10 ns;
BEGIN
-- Component Instantiation
uut: prediction PORT MAP(
clk => clk,
enable => enable,
output_hid => output_hid,
predict => predict
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
enable <= '0';
wait for clk_period*5;
enable <= '1';
for i in num_neurons-1 to 0 loop
output_hid(i) <= (others=>'0');
end loop;
output_hid(0) <= "10000111";
output_hid(1) <= "00010111";
output_hid(2) <= "00000001";
output_hid(3) <= "00000111";
wait;
end process;
END;
| bsd-2-clause | 8835a2b8adeabc9206d12beb6abc10f9 | 0.571518 | 3.565702 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/Lab_13/lab13_6/lab13_6.vhd | 1 | 703 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity binary_subractor_top is
Port ( CLK : in STD_LOGIC;
LED : out STD_LOGIC_VECTOR (3 downto 0));
end binary_subractor_top;
architecture Behavioral of binary_subractor_top is
signal CLK_DIV : std_logic_vector (2 downto 0);
signal COUNT : std_logic_vector (3 downto 0);
begin
process (CLK)
begin
if (CLK'Event and CLK = '1') then
CLK_DIV <= CLK_DIV - '1';
end if;
end process;
process (CLK_DIV(2))
begin
if (CLK_DIV(2)'Event and CLK_DIV(2) = '1') then
COUNT <= COUNT - '1';
end if;
end process;
LED <= COUNT;
end Behavioral; | gpl-2.0 | 134dfd6117e9c02ed773796656f77487 | 0.605974 | 3.25463 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/activation_mul.vhd | 1 | 4,152 | --------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2015 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file activation_mul.vhd when simulating
-- the core, activation_mul. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY activation_mul IS
PORT (
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
);
END activation_mul;
ARCHITECTURE activation_mul_a OF activation_mul IS
-- synthesis translate_off
COMPONENT wrapped_activation_mul
PORT (
a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(35 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_activation_mul USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral)
GENERIC MAP (
c_a_type => 0,
c_a_width => 18,
c_b_type => 0,
c_b_value => "10000001",
c_b_width => 18,
c_ccm_imp => 0,
c_ce_overrides_sclr => 0,
c_has_ce => 0,
c_has_sclr => 0,
c_has_zero_detect => 0,
c_latency => 0,
c_model_type => 0,
c_mult_type => 1,
c_optimize_goal => 1,
c_out_high => 35,
c_out_low => 0,
c_round_output => 0,
c_round_pt => 0,
c_verbosity => 0,
c_xdevicefamily => "artix7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_activation_mul
PORT MAP (
a => a,
b => b,
p => p
);
-- synthesis translate_on
END activation_mul_a;
| bsd-2-clause | e7a680e4253fd1b13e80a886920b94fe | 0.540944 | 4.68623 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp_ctl.vhd | 1 | 10,466 | -------------------------------------------------------------------------------
-- Title : Clock
-- Project :
-------------------------------------------------------------------------------
-- File : disp_ctl.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-19
-- Last update: 2018-04-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controler
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-19 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
entity disp_ctl is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
-- Time of day
cur_time : in time_ty;
-- Block memory display buffer and lut
lut_addr : out std_logic_vector(11 downto 0);
lut_data : in std_logic_vector(7 downto 0);
-- Segment driver data
disp_data : out std_logic_vector(255 downto 0)
);
end disp_ctl;
architecture rtl of disp_ctl is
signal ce : std_logic;
signal cnt : std_logic_vector(5 downto 0);
signal cnt_term : std_logic;
signal char : std_logic_vector(7 downto 0);
signal dchar : std_logic_vector(7 downto 0);
SIGNAL page : std_logic_vector(7 downto 0);
signal seg : std_logic_vector(7 downto 0);
signal mask : std_logic_vector(7 downto 0);
type out_arr_t is array (natural range <>) of std_logic_vector(7 downto 0);
signal disp_sr : out_arr_t(31 downto 0);
signal rst_addr : std_logic;
signal inc_addr : std_logic;
signal disp_mem : std_logic;
signal data_val : std_logic;
signal mask_val : std_logic;
signal lut_val : std_logic;
signal out_reg : std_logic;
type ctl_t is (ctl_idle,
ctl_rd,
ctl_mux,
ctl_disp,
ctl_mask,
ctl_proc0,
ctl_proc1,
ctl_lut,
ctl_ins
);
signal curr_state : ctl_t;
signal next_state : ctl_t;
begin
-- Clock enable generator
-- Once every other clock synchronized to ms pulse.
disp_ctl_ce:
process (rst_n, clk) is
begin
if (rst_n = '0') then
ce <= '0';
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1') then
ce <= '0';
else
ce <= not ce;
end if;
ce <= '1'; -- leave enabled for now
end if;
end process;
-- Character counter
disp_cnt:
process (rst_n, clk) is
begin
if (rst_n = '0') then
cnt <= (others => '0');
cnt_term <= '0';
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (rst_addr = '1') then
cnt <= (others => '0');
elsif (inc_addr = '1') then
cnt <= cnt + 1;
end if;
if (rst_addr = '1') then
cnt_term <= '0';
elsif (inc_addr = '1') then
if (cnt = 62) then
cnt_term <= '1';
else
cnt_term <= '0';
end if;
end if;
end if;
end if;
end process;
-- Display data for lookup table
disp_lut_data:
process (rst_n, clk) is
variable digit : std_logic_vector(3 downto 0);
begin
if (rst_n = '0') then
char <= (others => '0');
mask <= (others => '0');
dchar <= (others => '0');
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (data_val = '1') then
char <= lut_data;
end if;
if (mask_val = '1') then
mask <= lut_data;
end if;
case char(3 downto 0) is
when "0000" =>
digit := cur_time.t_1ms;
when "0001" =>
digit := cur_time.t_10ms;
when "0010" =>
digit := cur_time.t_100ms;
when "0011" =>
digit := cur_time.t_1s;
when "0100" =>
digit := cur_time.t_10s;
when "0101" =>
digit := cur_time.t_1m;
when "0110" =>
digit := cur_time.t_10m;
when "0111" =>
digit := cur_time.t_1h;
when "1000" =>
digit := cur_time.t_10h;
when others =>
digit := (others => '0');
end case;
if (char(7) = '1') then
dchar <= digit + x"30";
else
dchar <= '0' & char(6 downto 0);
end if;
end if;
end if;
end process;
-- Display page register, Updated every 1ms
disp_mem_page:
process (rst_n, clk) is
begin
if (rst_n = '0') then
page <= (others => '0');
elsif (clk'event and clk = '1') then
if (tsc_1ppms = '1' ) then
page <= disp_page;
end if;
end if;
end process;
-- Address mux, select character to be displayed or character genrator lut
disp_amux:
process (rst_n, clk) is
begin
if (rst_n = '0') then
lut_addr <= (others => '0');
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (disp_mem = '1') then
lut_addr <= "0" & page(4 downto 0) & cnt;
else
lut_addr <= "1000" & dchar;
end if;
end if;
end if;
end process;
-- Output register
disp_out:
process (rst_n, clk) is
begin
if (rst_n = '0') then
seg <= (others => '0');
disp_sr(0) <= x"1c";
disp_sr(1) <= x"ce";
disp_sr(2) <= x"bc";
for i in 3 to 31 loop
disp_sr(i) <= (others => '0');
end loop;
elsif (clk'event and clk = '1') then
if (ce = '1') then
if (lut_val = '1') then
seg <= lut_data;
end if;
-- Xor in second byte of the display memory register
-- bits with the lut data
if (out_reg = '1') then
disp_sr(conv_integer(cnt(cnt'left downto 1))) <= seg xor mask;
end if;
end if;
end if;
end process;
-- Clock enable generator
-- Once every other clock synchronized to ms pulse.
disp_ctl_st:
process (rst_n, clk) is
begin
if (rst_n = '0') then
curr_state <= ctl_idle;
elsif (clk'event and clk = '1') then
if (ce = '1') then
curr_state <= next_state;
end if;
end if;
end process;
-- State diagram
-- For now just a shift register, use a state machine in case a more
-- complex sequence is needed.
disp_ctl_next:
process (curr_state, tsc_1ppms, cnt_term, disp_ena) is
begin
-- outputs
rst_addr <= '0';
inc_addr <= '0';
disp_mem <= '0';
data_val <= '0';
mask_val <= '0';
lut_val <= '0';
out_reg <= '0';
inc_addr <= '0';
case curr_state is
when ctl_idle =>
-- Start building the shift register data every ms
rst_addr <= '1';
if (tsc_1ppms = '1' and disp_ena = '1') then
next_state <= ctl_rd;
else
next_state <= ctl_idle;
end if;
when ctl_rd =>
-- Read the display memory
disp_mem <= '1';
inc_addr <= '1';
next_state <= ctl_mux;
when ctl_mux =>
-- Address mux state
disp_mem <= '1';
next_state <= ctl_disp;
when ctl_disp =>
-- Register the display memory data
data_val <= '1';
next_state <= ctl_mask;
when ctl_mask =>
-- Process char data
-- Register the display memory xor data
mask_val <= '1';
next_state <= ctl_proc0;
when ctl_proc0 =>
-- Processing
next_state <= ctl_proc1;
when ctl_proc1 =>
-- Processing
next_state <= ctl_lut;
when ctl_lut =>
-- Lookup 7 seg output
lut_val <= '1';
next_state <= ctl_ins;
when ctl_ins =>
-- Insert data into output register
-- Increment display memory address
out_reg <= '1';
inc_addr <= '1';
if (cnt_term = '1') then
next_state <= ctl_idle;
else
next_state <= ctl_rd;
end if;
when others =>
next_state <= ctl_idle;
end case;
end process;
out_map:
for i in 0 to 31 generate
disp_data(i * 8 + 7 downto i * 8) <= disp_sr(i)(7 downto 0);
end generate;
end rtl;
| gpl-3.0 | 62716b79e05d0946a8ec8557c6df82e2 | 0.395567 | 4.237247 | false | false | false | false |
ObKo/USBCore | Core/usb_packet.vhdl | 1 | 13,636 | --
-- USB Full-Speed/Hi-Speed Device Controller core - usb_packet.vhdl
--
-- Copyright (c) 2015 Konstantin Oblaukhov
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.USBCore.all;
entity usb_packet is
port (
rst : in std_logic;
clk : in std_logic;
axis_rx_tvalid : in std_logic;
axis_rx_tready : out std_logic;
axis_rx_tlast : in std_logic;
axis_rx_tdata : in std_logic_vector(7 downto 0);
axis_tx_tvalid : out std_logic;
axis_tx_tready : in std_logic;
axis_tx_tlast : out std_logic;
axis_tx_tdata : out std_logic_vector(7 downto 0);
trn_type : out std_logic_vector(1 downto 0);
trn_address : out std_logic_vector(6 downto 0);
trn_endpoint : out std_logic_vector(3 downto 0);
trn_start : out std_logic;
-- DATA0/1/2 MDATA
rx_trn_data_type : out std_logic_vector(1 downto 0);
rx_trn_end : out std_logic;
rx_trn_data : out std_logic_vector(7 downto 0);
rx_trn_valid : out std_logic;
rx_trn_hsk_type : out std_logic_vector(1 downto 0);
rx_trn_hsk_received : out std_logic;
-- 00 - ACK, 10 - NAK, 11 - STALL, 01 - NYET
tx_trn_hsk_type : in std_logic_vector(1 downto 0);
tx_trn_send_hsk : in std_logic;
tx_trn_hsk_sended : out std_logic;
-- DATA0/1/2 MDATA
tx_trn_data_type : in std_logic_vector(1 downto 0);
-- Set tx_trn_data_last to '1' when start for zero packet
tx_trn_data_start : in std_logic;
tx_trn_data : in std_logic_vector(7 downto 0);
tx_trn_data_valid : in std_logic;
tx_trn_data_ready : out std_logic;
tx_trn_data_last : in std_logic;
start_of_frame : out std_logic;
crc_error : out std_logic;
device_address : in std_logic_vector(6 downto 0)
);
end usb_packet;
architecture usb_packet of usb_packet is
type RX_MACHINE is (S_Idle, S_SOF, S_SOFCRC, S_Token, S_TokenCRC, S_Data, S_DataCRC);
type TX_MACHINE is (S_Idle, S_HSK, S_HSK_Wait, S_DataPID, S_Data, S_DataCRC1, S_DataCRC2);
function crc5(data : std_logic_vector) return std_logic_vector is
variable crc : std_logic_vector(4 downto 0);
begin
crc(4) := not ('1' xor data(10) xor data(7) xor data(5) xor data(4) xor data(1) xor data(0));
crc(3) := not ('1' xor data(9) xor data(6) xor data(4) xor data(3) xor data(0));
crc(2) := not ('1' xor data(10) xor data(8) xor data(7) xor data(4) xor data(3) xor data(2) xor data(1) xor data(0));
crc(1) := not ('0' xor data(9) xor data(7) xor data(6) xor data(3) xor data(2) xor data(1) xor data(0));
crc(0) := not ('1' xor data(8) xor data(6) xor data(5) xor data(2) xor data(1) xor data(0));
return crc;
end;
function crc16(d : std_logic_vector; c : std_logic_vector) return std_logic_vector is
variable crc : std_logic_vector(15 downto 0);
begin
crc(0) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
crc(1) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
crc(2) := d(6) xor d(7) xor c(8) xor c(9);
crc(3) := d(5) xor d(6) xor c(9) xor c(10);
crc(4) := d(4) xor d(5) xor c(10) xor c(11);
crc(5) := d(3) xor d(4) xor c(11) xor c(12);
crc(6) := d(2) xor d(3) xor c(12) xor c(13);
crc(7) := d(1) xor d(2) xor c(13) xor c(14);
crc(8) := d(0) xor d(1) xor c(0) xor c(14) xor c(15);
crc(9) := d(0) xor c(1) xor c(15);
crc(10) := c(2);
crc(11) := c(3);
crc(12) := c(4);
crc(13) := c(5);
crc(14) := c(6);
crc(15) := d(0) xor d(1) xor d(2) xor d(3) xor d(4) xor d(5) xor d(6) xor d(7) xor c(7) xor c(8) xor c(9) xor c(10) xor c(11) xor c(12) xor c(13) xor c(14) xor c(15);
return crc;
end;
signal rx_state : RX_MACHINE := S_Idle;
signal tx_state : TX_MACHINE := S_Idle;
signal rx_crc5 : std_logic_vector(4 downto 0);
signal rx_pid : std_logic_vector(3 downto 0);
signal rx_counter : std_logic_vector(10 downto 0);
signal token_data : std_logic_vector(10 downto 0);
signal token_crc5 : std_logic_vector(4 downto 0);
signal rx_crc16 : std_logic_vector(15 downto 0);
signal rx_data_crc : std_logic_vector(15 downto 0);
signal tx_crc16 : std_logic_vector(15 downto 0);
signal tx_crc16_r : std_logic_vector(15 downto 0);
signal rx_buf1 : std_logic_vector(7 downto 0);
signal rx_buf2 : std_logic_vector(7 downto 0);
signal tx_zero_packet : std_logic;
begin
RX_COUNT : process(clk) is
begin
if rising_edge(clk) then
if rx_state = S_Idle then
rx_counter <= (others => '0');
elsif axis_rx_tvalid = '1' then
rx_counter <= rx_counter + 1;
end if;
end if;
end process;
DATA_CRC_CALC : process(clk) is
begin
if rising_edge(clk) then
if rx_state = S_Idle then
rx_crc16 <= (others => '1');
elsif rx_state = S_Data and axis_rx_tvalid = '1' and rx_counter > 1 then
rx_crc16 <= crc16(rx_buf1, rx_crc16);
end if;
end if;
end process;
TX_DATA_CRC_CALC : process(clk) is
begin
if rising_edge(clk) then
if tx_state = S_Idle then
tx_crc16 <= (others => '1');
elsif tx_state = S_Data and axis_tx_tready = '1' and tx_trn_data_valid = '1' then
tx_crc16 <= crc16(tx_trn_data, tx_crc16);
end if;
end if;
end process;
rx_trn_data <= rx_buf1;
rx_trn_valid <= '1' when rx_state = S_Data and axis_rx_tvalid = '1' and rx_counter > 1 else
'0';
rx_crc5 <= crc5(token_data);
rx_data_crc <= rx_buf2 & rx_buf1;
trn_address <= token_data(6 downto 0);
trn_endpoint <= token_data(10 downto 7);
RX_FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
start_of_frame <= '0';
crc_error <= '0';
trn_start <= '0';
rx_trn_end <= '0';
rx_trn_hsk_received <= '0';
rx_state <= S_Idle;
else
case rx_state is
when S_Idle =>
start_of_frame <= '0';
crc_error <= '0';
trn_start <= '0';
rx_trn_end <= '0';
rx_trn_hsk_received <= '0';
if axis_rx_tvalid = '1' and rx_pid = (not axis_rx_tdata(7 downto 4)) then
if rx_pid = "0101" then
rx_state <= S_SOF;
elsif rx_pid(1 downto 0) = "01" then
trn_type <= rx_pid(3 downto 2);
rx_state <= S_Token;
elsif rx_pid(1 downto 0) = "11" then
rx_trn_data_type <= rx_pid(3 downto 2);
rx_state <= S_Data;
elsif rx_pid(1 downto 0) = "10" then
rx_trn_hsk_type <= rx_pid(3 downto 2);
rx_trn_hsk_received <= '1';
end if;
end if;
when S_SOF =>
if axis_rx_tvalid = '1' then
if rx_counter = 0 then
token_data(7 downto 0) <= axis_rx_tdata;
elsif rx_counter = 1 then
token_data(10 downto 8) <= axis_rx_tdata(2 downto 0);
token_crc5 <= axis_rx_tdata(7 downto 3);
end if;
if axis_rx_tlast = '1' then
rx_state <= S_SOFCRC;
end if;
end if;
when S_SOFCRC =>
if token_crc5 /= rx_crc5 then
crc_error <= '1';
else
start_of_frame <= '1';
end if;
rx_state <= S_Idle;
when S_Token =>
if axis_rx_tvalid = '1' then
if rx_counter = 0 then
token_data(7 downto 0) <= axis_rx_tdata;
elsif rx_counter = 1 then
token_data(10 downto 8) <= axis_rx_tdata(2 downto 0);
token_crc5 <= axis_rx_tdata(7 downto 3);
end if;
if axis_rx_tlast = '1' then
rx_state <= S_TokenCRC;
end if;
end if;
when S_TokenCRC =>
if device_address = token_data(6 downto 0) then
if token_crc5 = rx_crc5 then
trn_start <= '1';
else
crc_error <= '1';
end if;
end if;
rx_state <= S_Idle;
when S_Data =>
if axis_rx_tvalid = '1' then
if rx_counter = 0 then
rx_buf1 <= axis_rx_tdata;
elsif rx_counter = 1 then
rx_buf2 <= axis_rx_tdata;
else
rx_buf1 <= rx_buf2;
rx_buf2 <= axis_rx_tdata;
end if;
if axis_rx_tlast = '1' then
rx_state <= S_DataCRC;
end if;
end if;
when S_DataCRC =>
rx_trn_end <= '1';
if rx_data_crc /= rx_crc16 then
crc_error <= '1';
end if;
rx_state <= S_Idle;
end case;
end if;
end if;
end process;
TX_FSM : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
tx_state <= S_Idle;
else
case tx_state is
when S_Idle =>
if tx_trn_send_hsk = '1' then
tx_state <= S_HSK;
elsif tx_trn_data_start = '1' then
if tx_trn_data_last = '1' and tx_trn_data_valid = '0' then
tx_zero_packet <= '1';
else
tx_zero_packet <= '0';
end if;
tx_state <= S_DataPID;
end if;
when S_HSK =>
if axis_tx_tready = '1' then
tx_state <= S_HSK_Wait;
end if;
when S_HSK_Wait =>
if tx_trn_send_hsk = '0' then
tx_state <= S_Idle;
end if;
when S_DataPID =>
if axis_tx_tready = '1' then
if tx_zero_packet = '1' then
tx_state <= S_DataCRC1;
else
tx_state <= S_Data;
end if;
end if;
when S_Data =>
if axis_tx_tready = '1' and tx_trn_data_valid = '1' then
if tx_trn_data_last = '1' then
tx_state <= S_DataCRC1;
end if;
elsif tx_trn_data_valid = '0' then
tx_state <= S_DataCRC2;
end if;
when S_DataCRC1 =>
if axis_tx_tready = '1' then
tx_state <= S_DataCRC2;
end if;
when S_DataCRC2 =>
if axis_tx_tready = '1' then
tx_state <= S_Idle;
end if;
end case;
end if;
end if;
end process;
axis_tx_tdata <= (not (tx_trn_data_type & "11")) & tx_trn_data_type & "11" when tx_state = S_DataPID else
(not (tx_trn_hsk_type & "10")) & tx_trn_hsk_type & "10" when tx_state = S_HSK else
tx_crc16_r(7 downto 0) when tx_state = S_DataCRC1 or (tx_state = S_Data and tx_trn_data_valid = '0') else
tx_crc16_r(15 downto 8) when tx_state = S_DataCRC2 else
tx_trn_data;
axis_tx_tvalid <= '1' when tx_state = S_DataPID or tx_state = S_HSK or tx_state = S_DataCRC1 or tx_state = S_DataCRC2 else
'1' when tx_state = S_Data else
'0';
axis_tx_tlast <= '1' when tx_state = S_HSK else
'1' when tx_state = S_DataCRC2 else
'0';
tx_trn_data_ready <= axis_tx_tready when tx_state = S_Data else
'0';
tx_trn_hsk_sended <= '1' when tx_state = S_HSK_Wait else
'0';
tx_crc16_r <= (not (tx_crc16(0) & tx_crc16(1) & tx_crc16(2) & tx_crc16(3) &
tx_crc16(4) & tx_crc16(5) & tx_crc16(6) & tx_crc16(7) &
tx_crc16(8) & tx_crc16(9) & tx_crc16(10) & tx_crc16(11) &
tx_crc16(12) & tx_crc16(13) & tx_crc16(14) & tx_crc16(15)));
rx_pid <= axis_rx_tdata(3 downto 0);
axis_rx_tready <= '1';
end usb_packet;
| mit | 3e8f480a0b3ffed4f523e957a9f50ad4 | 0.5132 | 3.190454 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_iic_0_0/axi_iic_v2_0/hdl/src/vhdl/iic_pkg.vhd | 2 | 10,337 | -------------------------------------------------------------------------------
-- iic_pkg.vhd - Package
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX is PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS is" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT to NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
-------------------------------------------------------------------------------
-- Filename: iic_pkg.vhd
-- Version: v1.01.b
-- Description: This file contains the constants used in the design of the
-- iic bus interface.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_iic.vhd
-- -- iic.vhd
-- -- axi_ipif_ssp1.vhd
-- -- axi_lite_ipif.vhd
-- -- interrupt_control.vhd
-- -- soft_reset.vhd
-- -- reg_interface.vhd
-- -- filter.vhd
-- -- debounce.vhd
-- -- iic_control.vhd
-- -- upcnt_n.vhd
-- -- shift8.vhd
-- -- dynamic_master.vhd
-- -- iic_pkg.vhd
--
-------------------------------------------------------------------------------
-- Author: USM
--
-- USM 10/15/09
-- ^^^^^^
-- - Initial release of v1.00.a
-- ~~~~~~
--
-- USM 09/06/10
-- ^^^^^^
-- - Release of v1.01.a
-- ~~~~~~
--
-- NLR 01/07/11
-- ^^^^^^
-- - Release of v1.01.b
-- ~~~~~~
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package iic_pkg is
----------------------------------------------------------------------------
-- Constant Declarations
----------------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1'; -- Reset Constant
constant NUM_IIC_REGS : integer := 11; -- should be same as C_NUM_IIC_REGS in axi_iic top
constant DATA_BITS : natural := 8; -- FIFO Width Generic
constant TX_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits
constant RC_FIFO_BITS : integer range 0 to 256 := 4; -- Number of addr bits
--IPIF Generics that must remain at these values for the IIC
constant INCLUDE_DEV_PENCODER : BOOLEAN := False;
constant IPIF_ABUS_WIDTH : INTEGER := 32;
constant INCLUDE_DEV_ISC : Boolean := false;
type STD_LOGIC_VECTOR_ARRAY is array (0 to NUM_IIC_REGS-1) of std_logic_vector(24 to 31);
type INTEGER_ARRAY is array (24 to 31) of integer;
----------------------------------------------------------------------------
-- Function and Procedure Declarations
----------------------------------------------------------------------------
function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer;
C_IIC_FREQ : integer) return integer;
function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector;
function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector;
function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY) return
INTEGER_ARRAY;
end package iic_pkg;
-------------------------------------------------------------------------------
-- Package body
-------------------------------------------------------------------------------
package body iic_pkg is
----------------------------------------------------------------------------
-- Function Definitions
----------------------------------------------------------------------------
-- Function num_ctr_bits
--
-- This function returns the number of bits required to count 1/2 the period
-- of the SCL clock.
--
----------------------------------------------------------------------------
function num_ctr_bits(C_S_AXI_ACLK_FREQ_HZ : integer;
C_IIC_FREQ : integer) return integer is
variable num_bits : integer :=0;
variable i : integer :=0;
begin
-- for loop used because XST service pack 2 does not support While loops
if C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ > C_S_AXI_ACLK_FREQ_HZ/212766 then
for i in 0 to 30 loop -- 30 is a magic number needed for for loops
if 2**i < C_S_AXI_ACLK_FREQ_HZ/C_IIC_FREQ then
num_bits := num_bits + 1;
end if;
end loop;
return (num_bits);
else
for i in 0 to 30 loop
if 2**i < C_S_AXI_ACLK_FREQ_HZ/212766 then
num_bits := num_bits + 1;
end if;
end loop;
return (num_bits);
end if;
end function num_ctr_bits;
----------------------------------------------------------------------------
-- Function ten_bit_addr_used
--
-- This function returns either b"00000000" for no ten bit addressing or
-- b"00000111" for ten bit addressing
--
----------------------------------------------------------------------------
function ten_bit_addr_used(C_TEN_BIT_ADR : integer) return std_logic_vector is
begin
if C_TEN_BIT_ADR = 0 then
return (b"00000000");
else
return (b"00000111");
end if;
end function ten_bit_addr_used;
----------------------------------------------------------------------------
-- Function gpo_bit_used
--
-- This function returns b"00000000" up to b"11111111" depending on
-- C_GPO_WIDTH
--
----------------------------------------------------------------------------
function gpo_bit_used(C_GPO_WIDTH : integer) return std_logic_vector is
begin
if C_GPO_WIDTH = 1 then
return (b"00000001");
elsif C_GPO_WIDTH = 2 then
return (b"00000011");
elsif C_GPO_WIDTH = 3 then
return (b"00000111");
elsif C_GPO_WIDTH = 4 then
return (b"00001111");
elsif C_GPO_WIDTH = 5 then
return (b"00011111");
elsif C_GPO_WIDTH = 6 then
return (b"00111111");
elsif C_GPO_WIDTH = 7 then
return (b"01111111");
elsif C_GPO_WIDTH = 8 then
return (b"11111111");
end if;
end function gpo_bit_used;
----------------------------------------------------------------------------
-- Function count_reg_bits_used
--
-- This function returns either b"00000000" for no ten bit addressing or
-- b"00000111" for ten bit addressing
--
----------------------------------------------------------------------------
function count_reg_bits_used(REG_BITS_USED : STD_LOGIC_VECTOR_ARRAY)
return INTEGER_ARRAY is
variable count : INTEGER_ARRAY;
begin
for i in 24 to 31 loop
count(i) := 0;
for m in 0 to NUM_IIC_REGS-1 loop --IP_REG_NUM - 1
if (REG_BITS_USED(m)(i) = '1') then
count(i) := count(i) + 1;
end if;
end loop;
end loop;
return count;
end function count_reg_bits_used;
end package body iic_pkg;
| gpl-3.0 | 82c198e60c5b5cf8192fd9341d85c228 | 0.421592 | 4.95067 | false | false | false | false |
UnofficialRepos/OSVVM | OsvvmGlobalPkg.vhd | 1 | 16,584 | --
-- File Name: OsvvmGlobalPkg.vhd
-- Design Unit Name: OsvvmGlobalPkg
-- Revision: STANDARD VERSION, revision 2015.01
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Global Settings for OSVVM packages
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Added support for IdSeparator.
-- Supports PrintParent mode PRINT_NAME_AND_PARENT. <Parent Name> <IdSeparator> <AlertLogID Name>.
-- 01/2020 2020.01 Updated Licenses to Apache
-- 01/2014 2015.01 Initial revision
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2015 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use std.textio.all ;
use work.NamePkg.all ;
package OsvvmGlobalPkg is
-- FILE IO Global File Identifier -- Open using AlertLogPkg.TranscriptOpen
-- file TranscriptFile : text ;
-- Shared Options Type used in OSVVM
type OsvvmOptionsType is (OPT_INIT_PARM_DETECT, OPT_USE_DEFAULT, DISABLED, FALSE, ENABLED, TRUE) ;
function IsEnabled (A : OsvvmOptionsType) return boolean ; -- Requires that TRUE is last and ENABLED is 2nd to last
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType ;
-- Defaults for String values
constant OSVVM_DEFAULT_ALERT_PREFIX : string := "%% Alert" ;
constant OSVVM_DEFAULT_LOG_PREFIX : string := "%% Log " ;
constant OSVVM_DEFAULT_WRITE_PREFIX : string := "%% " ;
constant OSVVM_DEFAULT_DONE_NAME : string := "DONE" ;
constant OSVVM_DEFAULT_PASS_NAME : string := "PASSED" ;
constant OSVVM_DEFAULT_FAIL_NAME : string := "FAILED" ;
constant OSVVM_DEFAULT_ID_SEPARATOR : string := ": " ;
constant OSVVM_STRING_INIT_PARM_DETECT : string := NUL & NUL & NUL ;
constant OSVVM_STRING_USE_DEFAULT : string := NUL & "" ;
-- Coverage Settings
constant OSVVM_DEFAULT_WRITE_PASS_FAIL : OsvvmOptionsType := FALSE ;
constant OSVVM_DEFAULT_WRITE_BIN_INFO : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_COUNT : OsvvmOptionsType := TRUE ;
constant OSVVM_DEFAULT_WRITE_ANY_ILLEGAL : OsvvmOptionsType := FALSE ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT ;
IdSeparator : string := OSVVM_STRING_INIT_PARM_DETECT
) ;
------------------------------------------------------------
-- Accessor Functions
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType ;
function IsOsvvmStringSet (A : string) return boolean ;
function ResolveOsvvmOption(A, B : string) return string ;
function ResolveOsvvmOption(A, B, C : string) return string ;
function ResolveOsvvmOption(A, B, C, D : string) return string ;
impure function ResolveOsvvmWritePrefix (A : String) return string ;
impure function ResolveOsvvmDoneName (A : String) return string ;
impure function ResolveOsvvmPassName (A : String) return string ;
impure function ResolveOsvvmFailName (A : String) return string ;
impure function ResolveOsvvmIdSeparator (A : String) return string ;
impure function ResolveCovWritePassFail (A : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteBinInfo (A : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteCount (A : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteAnyIllegal(A : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveOsvvmWritePrefix (A, B : String) return string ;
impure function ResolveOsvvmDoneName (A, B : String) return string ;
impure function ResolveOsvvmPassName (A, B : String) return string ;
impure function ResolveOsvvmFailName (A, B : String) return string ;
impure function ResolveCovWritePassFail (A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteBinInfo (A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteCount (A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType ; -- Cov
procedure SetOsvvmDefaultTimeUnits (A : time) ;
impure function GetOsvvmDefaultTimeUnits return time ;
procedure OsvvmDeallocate ;
type OptionsPType is protected
procedure Set (A: OsvvmOptionsType) ;
impure function get return OsvvmOptionsType ;
end protected OptionsPType ;
type OsvvmDefaultTimeUnitsPType is protected
procedure Set (A: time) ;
impure function get return time ;
end protected OsvvmDefaultTimeUnitsPType ;
end OsvvmGlobalPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body OsvvmGlobalPkg is
type OptionsPType is protected body
variable GlobalVar : OsvvmOptionsType ;
procedure Set (A : OsvvmOptionsType) is
begin
GlobalVar := A ;
end procedure Set ;
impure function get return OsvvmOptionsType is
begin
return GlobalVar ;
end function get ;
end protected body OptionsPType ;
type OsvvmDefaultTimeUnitsPType is protected body
variable GlobalVar : time := std.env.resolution_limit ; -- VHDL-2008
procedure Set (A : time) is
begin
if A > std.env.resolution_limit then
GlobalVar := A ;
elsif A < std.env.resolution_limit then
report "SetOsvvmDefaultTimeUnits: time unit parameter too small" severity warning ;
end if ;
end procedure Set ;
impure function get return time is
begin
return GlobalVar ;
end function get ;
end protected body OsvvmDefaultTimeUnitsPType ;
shared variable WritePrefixVar : NamePType ;
shared variable DoneNameVar : NamePType ;
shared variable PassNameVar : NamePType ;
shared variable FailNameVar : NamePType ;
shared variable IdSeparatorVar : NamePType ;
shared variable WritePassFailVar : OptionsPType ; -- := FALSE ;
shared variable WriteBinInfoVar : OptionsPType ; -- := TRUE ;
shared variable WriteCountVar : OptionsPType ; -- := TRUE ;
shared variable WriteAnyIllegalVar : OptionsPType ; -- := FALSE ;
shared variable OsvvmDefaultTimeUnitsVar : OsvvmDefaultTimeUnitsPType ;
function IsEnabled (A : OsvvmOptionsType) return boolean is
begin
return A >= ENABLED ;
end function IsEnabled ;
function to_OsvvmOptionsType (A : boolean) return OsvvmOptionsType is
begin
if A then
return TRUE ;
else
return FALSE ;
end if ;
end function to_OsvvmOptionsType ;
------------------------------------------------------------
procedure SetOsvvmGlobalOptions (
------------------------------------------------------------
WritePassFail : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteBinInfo : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteCount : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WriteAnyIllegal : OsvvmOptionsType := OPT_INIT_PARM_DETECT ;
WritePrefix : string := OSVVM_STRING_INIT_PARM_DETECT ;
DoneName : string := OSVVM_STRING_INIT_PARM_DETECT ;
PassName : string := OSVVM_STRING_INIT_PARM_DETECT ;
FailName : string := OSVVM_STRING_INIT_PARM_DETECT ;
IdSeparator : string := OSVVM_STRING_INIT_PARM_DETECT
) is
begin
if WritePassFail /= OPT_INIT_PARM_DETECT then
WritePassFailVar.Set(WritePassFail) ;
end if ;
if WriteBinInfo /= OPT_INIT_PARM_DETECT then
WriteBinInfoVar.Set(WriteBinInfo) ;
end if ;
if WriteCount /= OPT_INIT_PARM_DETECT then
WriteCountVar.Set(WriteCount) ;
end if ;
if WriteAnyIllegal /= OPT_INIT_PARM_DETECT then
WriteAnyIllegalVar.Set(WriteAnyIllegal) ;
end if ;
if WritePrefix /= OSVVM_STRING_INIT_PARM_DETECT then
WritePrefixVar.Set(WritePrefix) ;
end if ;
if DoneName /= OSVVM_STRING_INIT_PARM_DETECT then
DoneNameVar.Set(DoneName) ;
end if ;
if PassName /= OSVVM_STRING_INIT_PARM_DETECT then
PassNameVar.Set(PassName) ;
end if ;
if FailName /= OSVVM_STRING_INIT_PARM_DETECT then
FailNameVar.Set(FailName) ;
end if ;
if IdSeparator /= OSVVM_STRING_INIT_PARM_DETECT then
IdSeparatorVar.Set(IdSeparator) ;
end if ;
end procedure SetOsvvmGlobalOptions ;
------------------------------------------------------------
-- Accessor Functions
-- Local Function
function IsOsvvmOptionSet (A : OsvvmOptionsType) return boolean is
begin
return A > OPT_USE_DEFAULT ;
end function IsOsvvmOptionSet ;
function ResolveOsvvmOption(A, B, C : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : OsvvmOptionsType) return OsvvmOptionsType is
begin
if IsOsvvmOptionSet(A) then
return A ;
elsif IsOsvvmOptionSet(B) then
return B ;
elsif IsOsvvmOptionSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
-- Local Function
function IsOsvvmStringSet (A : string) return boolean is
begin
if A'length = 0 then -- Null strings permitted
return TRUE ;
else
return A(A'left) /= NUL ;
end if;
end function IsOsvvmStringSet ;
function ResolveOsvvmOption(A, B : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
else
return B ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
else
return C ;
end if ;
end function ResolveOsvvmOption ;
function ResolveOsvvmOption(A, B, C, D : string) return string is
begin
if IsOsvvmStringSet(A) then
return A ;
elsif IsOsvvmStringSet(B) then
return B ;
elsif IsOsvvmStringSet(C) then
return C ;
else
return D ;
end if ;
end function ResolveOsvvmOption ;
impure function ResolveOsvvmWritePrefix(A : String) return string is
begin
return ResolveOsvvmOption(A, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmDoneName(A : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmPassName(A : String) return string is
begin
return ResolveOsvvmOption(A, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmFailName(A : String) return string is
begin
return ResolveOsvvmOption(A, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveOsvvmIdSeparator(A : String) return string is
begin
return ResolveOsvvmOption(A, IdSeparatorVar.GetOpt, OSVVM_DEFAULT_ID_SEPARATOR) ;
end function ResolveOsvvmIdSeparator ;
impure function ResolveCovWritePassFail(A : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, WritePassFailVar.Get, OSVVM_DEFAULT_WRITE_PASS_FAIL) ;
end function ResolveCovWritePassFail ; -- Cov
impure function ResolveCovWriteBinInfo(A : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, WriteBinInfoVar.Get, OSVVM_DEFAULT_WRITE_BIN_INFO) ;
end function ResolveCovWriteBinInfo ; -- Cov
impure function ResolveCovWriteCount(A : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, WriteCountVar.Get, OSVVM_DEFAULT_WRITE_COUNT) ;
end function ResolveCovWriteCount ; -- Cov
impure function ResolveCovWriteAnyIllegal(A : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, WriteAnyIllegalVar.Get, OSVVM_DEFAULT_WRITE_ANY_ILLEGAL) ;
end function ResolveCovWriteAnyIllegal ; -- Cov
impure function ResolveOsvvmWritePrefix(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, WritePrefixVar.GetOpt, OSVVM_DEFAULT_WRITE_PREFIX) ;
end function ResolveOsvvmWritePrefix ;
impure function ResolveOsvvmDoneName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, DoneNameVar.GetOpt, OSVVM_DEFAULT_DONE_NAME) ;
end function ResolveOsvvmDoneName ;
impure function ResolveOsvvmPassName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, PassNameVar.GetOpt, OSVVM_DEFAULT_PASS_NAME) ;
end function ResolveOsvvmPassName ;
impure function ResolveOsvvmFailName(A, B : String) return string is
begin
return ResolveOsvvmOption(A, B, FailNameVar.GetOpt, OSVVM_DEFAULT_FAIL_NAME) ;
end function ResolveOsvvmFailName ;
impure function ResolveCovWritePassFail(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WritePassFailVar.Get, OSVVM_DEFAULT_WRITE_PASS_FAIL) ;
end function ResolveCovWritePassFail ; -- Cov
impure function ResolveCovWriteBinInfo(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteBinInfoVar.Get, OSVVM_DEFAULT_WRITE_BIN_INFO) ;
end function ResolveCovWriteBinInfo ; -- Cov
impure function ResolveCovWriteCount(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteCountVar.Get, OSVVM_DEFAULT_WRITE_COUNT) ;
end function ResolveCovWriteCount ; -- Cov
impure function ResolveCovWriteAnyIllegal(A, B : OsvvmOptionsType) return OsvvmOptionsType is
begin
return ResolveOsvvmOption(A, B, WriteAnyIllegalVar.Get, OSVVM_DEFAULT_WRITE_ANY_ILLEGAL) ;
end function ResolveCovWriteAnyIllegal ; -- Cov
procedure SetOsvvmDefaultTimeUnits (A : time) is
begin
OsvvmDefaultTimeUnitsVar.Set(A) ;
end procedure SetOsvvmDefaultTimeUnits ;
impure function GetOsvvmDefaultTimeUnits return time is
begin
return OsvvmDefaultTimeUnitsVar.Get ;
end function GetOsvvmDefaultTimeUnits ;
procedure OsvvmDeallocate is
begin
-- Free up space used by NamePType within OsvvmGlobalPkg
WritePrefixVar.Deallocate ;
DoneNameVar.Deallocate ;
PassNameVar.Deallocate ;
FailNameVar.Deallocate ;
WritePassFailVar.Set(FALSE) ; -- := FALSE ;
WriteBinInfoVar.Set(TRUE ) ; -- := TRUE ;
WriteCountVar.Set(TRUE ) ; -- := TRUE ;
WriteAnyIllegalVar.Set(FALSE) ; -- := FALSE ;
end procedure OsvvmDeallocate ;
end package body OsvvmGlobalPkg ; | artistic-2.0 | 6492c240a95729fada34d52c525e73f4 | 0.679812 | 4.138757 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/FIFO_Wrapper.vhd | 1 | 6,794 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity eb_wrapper is
Generic (
C_ASYNFIFO_WIDTH : integer := 72
);
Port (
--FIFO PCIe-->USER
H2B_wr_clk : IN std_logic;
H2B_wr_en : IN std_logic;
H2B_wr_din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
H2B_wr_pfull : OUT std_logic;
H2B_wr_full : OUT std_logic;
H2B_wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
H2B_rd_clk : IN std_logic;
H2B_rd_en : IN std_logic;
H2B_rd_dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
H2B_rd_pempty : OUT std_logic;
H2B_rd_empty : OUT std_logic;
H2B_rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
H2B_rd_valid : OUT std_logic;
--FIFO USER-->PCIe
B2H_wr_clk : IN std_logic;
B2H_wr_en : IN std_logic;
B2H_wr_din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
B2H_wr_pfull : OUT std_logic;
B2H_wr_full : OUT std_logic;
B2H_wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
B2H_rd_clk : IN std_logic;
B2H_rd_en : IN std_logic;
B2H_rd_dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
B2H_rd_pempty : OUT std_logic;
B2H_rd_empty : OUT std_logic;
B2H_rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
B2H_rd_valid : OUT std_logic;
--RESET from PCIe
rst : IN std_logic
);
end entity eb_wrapper;
architecture Behavioral of eb_wrapper is
--- 32768 x 64, with data count synchronized to rd_clk
component k7_eb_fifo_counted_resized
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic;
rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
wr_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
valid : OUT std_logic;
rst : IN std_logic
);
end component;
signal B2H_rd_data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal B2H_rd_data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_rd_data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_rd_data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal B2H_wr_data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal B2H_wr_data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_wr_data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal H2B_wr_data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal resized_H2B_wr_din : std_logic_VECTOR(64-1 downto 0);
signal resized_H2B_rd_dout : std_logic_VECTOR(64-1 downto 0);
signal resized_B2H_wr_din : std_logic_VECTOR(64-1 downto 0);
signal resized_B2H_rd_dout : std_logic_VECTOR(64-1 downto 0);
begin
B2H_rd_data_count <= B2H_rd_data_count_i;
H2B_rd_data_count <= H2B_rd_data_count_i;
B2H_wr_data_count <= B2H_wr_data_count_i;
H2B_wr_data_count <= H2B_wr_data_count_i;
resized_H2B_wr_din <= H2B_wr_din(64-1 downto 0);
resized_B2H_wr_din <= B2H_wr_din(64-1 downto 0);
H2B_rd_dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
H2B_rd_dout(63 downto 0) <= resized_H2B_rd_dout;
B2H_rd_dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
B2H_rd_dout(63 downto 0) <= resized_B2H_rd_dout;
-- ------------------------------------------
Syn_B2H_rd_data_count:
process (B2H_rd_clk)
begin
if B2H_rd_clk'event and B2H_rd_clk = '1' then
B2H_rd_data_count_i <= B2H_rd_data_count_wire;
end if;
end process;
Syn_H2B_rd_data_count:
process (H2B_rd_clk)
begin
if H2B_rd_clk'event and H2B_rd_clk = '1' then
H2B_rd_data_count_i <= H2B_rd_data_count_wire;
end if;
end process;
Syn_H2B_wr_data_count:
process (H2B_wr_clk)
begin
if H2B_wr_clk'event and H2B_wr_clk = '1' then
H2B_wr_data_count_i <= H2B_wr_data_count_wire;
end if;
end process;
Syn_B2H_wr_data_count:
process (B2H_wr_clk)
begin
if B2H_wr_clk'event and B2H_wr_clk = '1' then
B2H_wr_data_count_i <= B2H_wr_data_count_wire;
end if;
end process;
-- ------------------------------------------
----- Host2Board FIFO ----------
U0_H2B:
k7_eb_fifo_counted_resized
port map (
wr_clk => H2B_wr_clk ,
wr_en => H2B_wr_en ,
din => resized_H2B_wr_din ,
prog_full => H2B_wr_pfull ,
full => H2B_wr_full ,
rd_clk => H2B_rd_clk ,
rd_en => H2B_rd_en ,
dout => resized_H2B_rd_dout ,
prog_empty => H2B_rd_pempty ,
empty => H2B_rd_empty ,
rd_data_count => H2B_rd_data_count_wire ,
wr_data_count => H2B_wr_data_count_wire ,
valid => H2B_rd_valid ,
rst => rst
);
----- Board2Host FIFO ----------
U0_B2H:
k7_eb_fifo_counted_resized
port map (
wr_clk => B2H_wr_clk ,
wr_en => B2H_wr_en ,
din => resized_B2H_wr_din ,
prog_full => B2H_wr_pfull ,
full => B2H_wr_full ,
rd_clk => B2H_rd_clk ,
rd_en => B2H_rd_en ,
dout => resized_B2H_rd_dout ,
prog_empty => B2H_rd_pempty ,
empty => B2H_rd_empty ,
rd_data_count => B2H_rd_data_count_wire ,
wr_data_count => B2H_wr_data_count_wire ,
valid => B2H_rd_valid ,
rst => rst
);
end architecture Behavioral;
| gpl-2.0 | 5d661cc49bfc3e848f082265b5e41b41 | 0.531351 | 2.810923 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/ram_16x1k_dp_tb.vhd | 1 | 4,435 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ram_16x1k_dp_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ram_16x1k_dp_tb IS
END ENTITY;
ARCHITECTURE ram_16x1k_dp_tb_ARCH OF ram_16x1k_dp_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ram_16x1k_dp_synth_inst:ENTITY work.ram_16x1k_dp_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-3-clause | e0253611e0c9b59c61d6ae700080c6ad | 0.615107 | 4.461771 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_xadc_wiz_0_0/axi_lite_ipif_v1_01_a/hdl/src/vhdl/cpu_xadc_wiz_0_0_axi_lite_ipif.vhd | 1 | 14,877 | -------------------------------------------------------------------------------
-- AXI Lite IP Interface (IPIF) - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cpu_xadc_wiz_0_0_axi_lite_ipif.vhd
-- Version: v1.01.a
-- Description: This is the top level design file for the axi_lite_ipif
-- function. It provides a standardized slave interface
-- between the IP and the AXI. This version supports
-- single read/write transfers only. It does not provide
-- address pipelining or simultaneous read and write
-- operations.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- v1.01.a
-- 1. updated to reduce the utilization
-- Closed CR #574507
-- 2. Optimized the state machine code
-- 3. Optimized the address decoder logic to generate the CE's with common logic
-- 4. Address GAP decoding logic is removed and timeout counter is made active
-- for all transactions.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library work;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.all;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.clog2;
use work.cpu_xadc_wiz_0_0_proc_common_pkg.max2;
use work.cpu_xadc_wiz_0_0_family_support.all;
use work.cpu_xadc_wiz_0_0_ipif_pkg.all;
--library axi_lite_ipif_v1_01_a;
-- use axi_lite_ipif_v1_01_a.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_S_AXI_DATA_WIDTH -- AXI data bus width
-- C_S_AXI_ADDR_WIDTH -- AXI address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- s_axi_aclk -- AXI Clock
-- s_axi_aresetn -- AXI Reset
-- s_axi_awaddr -- AXI Write address
-- s_axi_awvalid -- Write address valid
-- s_axi_awready -- Write address ready
-- s_axi_wdata -- Write data
-- s_axi_wstrb -- Write strobes
-- s_axi_wvalid -- Write valid
-- s_axi_wready -- Write ready
-- s_axi_bresp -- Write response
-- s_axi_bvalid -- Write response valid
-- s_axi_bready -- Response ready
-- s_axi_araddr -- Read address
-- s_axi_arvalid -- Read address valid
-- s_axi_arready -- Read address ready
-- s_axi_rdata -- Read data
-- s_axi_rresp -- Read response
-- s_axi_rvalid -- Read valid
-- s_axi_rready -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity cpu_xadc_wiz_0_0_axi_lite_ipif is
generic (
C_S_AXI_DATA_WIDTH : integer range 32 to 32 := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 8;
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE := -- not used
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := -- not used
(
4, -- User0 CE Number
12 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
--System signals
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector
((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector
(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector
(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
((C_S_AXI_ADDR_WIDTH-1) downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_S_AXI_DATA_WIDTH/8)-1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY)-1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_S_AXI_DATA_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end cpu_xadc_wiz_0_0_axi_lite_ipif;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of cpu_xadc_wiz_0_0_axi_lite_ipif is
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Slave Attachment
-------------------------------------------------------------------------------
I_SLAVE_ATTACHMENT: entity work.cpu_xadc_wiz_0_0_slave_attachment
generic map(
C_ARD_ADDR_RANGE_ARRAY => C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_IPIF_ABUS_WIDTH => C_S_AXI_ADDR_WIDTH,
C_IPIF_DBUS_WIDTH => C_S_AXI_DATA_WIDTH,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_FAMILY => C_FAMILY
)
port map(
-- AXI signals
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
-- IPIC signals
Bus2IP_Clk => Bus2IP_Clk,
Bus2IP_Resetn => Bus2IP_Resetn,
Bus2IP_Addr => Bus2IP_Addr,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_CS => Bus2IP_CS,
Bus2IP_RdCE => Bus2IP_RdCE,
Bus2IP_WrCE => Bus2IP_WrCE,
Bus2IP_Data => Bus2IP_Data,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error
);
end imp;
| gpl-3.0 | afc733f8e23e2788d245424a8ffce245 | 0.451838 | 4.246931 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_rst_processing_system7_0_100M_0/sim/cpu_rst_processing_system7_0_100M_0.vhd | 1 | 5,905 | -- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY cpu_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END cpu_rst_processing_system7_0_100M_0;
ARCHITECTURE cpu_rst_processing_system7_0_100M_0_arch OF cpu_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF cpu_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END cpu_rst_processing_system7_0_100M_0_arch;
| gpl-3.0 | 375028820b92f5effcaed2e3545f5aac | 0.708552 | 3.583131 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rom_8192x32/example_design/rom_8192x32_prod.vhd | 1 | 9,941 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: rom_8192x32_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 3
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 32
-- C_READ_WIDTH_A : 32
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY rom_8192x32_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END rom_8192x32_prod;
ARCHITECTURE xilinx OF rom_8192x32_prod IS
COMPONENT rom_8192x32_exdes IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : rom_8192x32_exdes
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
| gpl-2.0 | 99522e48c5ede50608974eb9795bee8f | 0.495725 | 3.813195 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/superip_v1_00_a/hdl/vhdl/AmplifierFP.vhd | 4 | 2,579 | ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:27:41 04/17/2015
-- Design Name:
-- Module Name: AmplifierFP - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity AmplifierFP is
generic ( INTBIT_WIDTH : positive := 24;
FRACBIT_WIDTH : positive := 8);
Port ( CLK : in std_logic;
RESET : in std_logic;
IN_SIG : in signed ((INTBIT_WIDTH - 1) downto 0); --amplifier input signal
IN_COEF : in signed (((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0); --amplifying coefficient
OUT_AMP : out signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0'); --amplifier output
OUT_RDY : out std_logic
);
end AmplifierFP;
architecture Behavioral of AmplifierFP is
COMPONENT MultiplierFP
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
IN_SIG : IN signed((INTBIT_WIDTH - 1) downto 0);
IN_COEF : IN signed(((INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
OUT_MULT : OUT signed((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0);
READY : OUT std_logic
);
END COMPONENT;
signal mult_out : signed ((2*(INTBIT_WIDTH + FRACBIT_WIDTH) - 1) downto 0) := (others => '0');
signal AMP_OUT_in, AMP_OUT_out : signed ((INTBIT_WIDTH - 1) downto 0) := (others => '0');
signal mult_ready : std_logic := '0';
begin
Amp_multiplier: MultiplierFP PORT MAP(
CLK => CLK,
RESET => RESET,
IN_SIG => IN_SIG,
IN_COEF => IN_COEF,
OUT_MULT => mult_out,
READY => mult_ready
);
-- for fixed point
-- AMP_OUT_in <= mult_out(2*BIT_WIDTH - BIT_WIDTH - 1 downto 0);
-- for integers
AMP_OUT_in <= mult_out((2*FRACBIT_WIDTH + INTBIT_WIDTH) - 1 downto (2*FRACBIT_WIDTH ));
seq_proc : process (CLK)
begin
if(CLK'event and CLK = '1')then
-- update the ready signal when new values gets written to the buffer
if (mult_ready = '1') then
AMP_OUT_out <= AMP_OUT_in;
end if;
end if;
end process;
OUT_RDY <= mult_ready;
OUT_AMP <= AMP_OUT_out;
end Behavioral; | mit | 3fcbccdd8e509fb66c13a27ea1cb4bb1 | 0.53005 | 3.547455 | false | false | false | false |
UnofficialRepos/OSVVM | ReportPkg.vhd | 1 | 4,964 | --
-- File Name: ReportPkg.vhd
-- Design Unit Name: ReportPkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
-- Description:
-- Generate Final Reports
-- Elements of these reports come from AlertLogPkg, CoveragePkg, and
-- the ScoreboardGenericPkg instances of ScoreboardPkg_int and ScoreboardPkg_slv
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 EndOfTestReports now calls WriteScoreboardYaml
-- 10/2021 2021.10 Initial revision
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2021-2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use work.AlertLogPkg.AlertCountType ;
package ReportPkg is
impure function EndOfTestReports (
ReportAll : boolean := FALSE ;
ExternalErrors : AlertCountType := (0,0,0)
) return integer ;
procedure EndOfTestReports (
ReportAll : boolean := FALSE ;
ExternalErrors : AlertCountType := (0,0,0) ;
Stop : boolean := FALSE
) ;
alias EndOfTestSummary is EndOfTestReports[boolean, AlertCountType return integer] ;
alias EndOfTestSummary is EndOfTestReports[boolean, AlertCountType, boolean] ;
end ReportPkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body ReportPkg is
use std.textio.all ;
use work.AlertLogPkg.all ;
use work.CoveragePkg.all ;
use work.ScoreboardPkg_slv.all ;
use work.ScoreboardPkg_int.all ;
------------------------------------------------------------
procedure WriteCovSummaryYaml (FileName : string ) is
------------------------------------------------------------
file OsvvmYamlFile : text open APPEND_MODE is FileName ;
variable buf : line ;
begin
if GotCoverage then
swrite(buf, " FunctionalCoverage: " & to_string(GetCov, 2)) ;
else
swrite(buf, " FunctionalCoverage: ") ;
end if ;
writeline(OsvvmYamlFile, buf) ;
file_close(OsvvmYamlFile) ;
end procedure WriteCovSummaryYaml ;
------------------------------------------------------------
impure function EndOfTestReports (
------------------------------------------------------------
ReportAll : boolean := FALSE ;
ExternalErrors : AlertCountType := (0,0,0)
) return integer is
begin
ReportAlerts(ExternalErrors => ExternalErrors, ReportAll => ReportAll) ;
WriteAlertSummaryYaml(
FileName => "OsvvmRun.yml",
ExternalErrors => ExternalErrors
) ;
WriteCovSummaryYaml (
FileName => "OsvvmRun.yml"
) ;
WriteAlertYaml (
FileName => REPORTS_DIRECTORY & GetAlertLogName & "_alerts.yml",
ExternalErrors => ExternalErrors
) ;
if GotCoverage then
WriteCovYaml (
FileName => REPORTS_DIRECTORY & GetAlertLogName & "_cov.yml"
) ;
end if ;
if work.ScoreboardPkg_slv.GotScoreboards then
work.ScoreboardPkg_slv.WriteScoreboardYaml (
FileName => REPORTS_DIRECTORY & GetAlertLogName & "_sb_slv.yml"
) ;
end if ;
if work.ScoreboardPkg_int.GotScoreboards then
work.ScoreboardPkg_int.WriteScoreboardYaml (
FileName => REPORTS_DIRECTORY & GetAlertLogName & "_sb_int.yml"
) ;
end if ;
return SumAlertCount(GetAlertCount + ExternalErrors) ;
end function EndOfTestReports ;
------------------------------------------------------------
procedure EndOfTestReports (
------------------------------------------------------------
ReportAll : boolean := FALSE ;
ExternalErrors : AlertCountType := (0,0,0) ;
Stop : boolean := FALSE
) is
variable ErrorCount : integer ;
begin
ErrorCount := EndOfTestReports(ReportAll, ExternalErrors) ;
if Stop then
std.env.stop(ErrorCount) ;
end if ;
end procedure EndOfTestReports ;
end package body ReportPkg ; | artistic-2.0 | 38cabda5545cd13db74cd377204b0ace | 0.568695 | 4.424242 | false | true | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/FIFO_Wrapper_Loopback.vhd | 1 | 3,526 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity eb_wrapper_loopback is
Generic (
C_ASYNFIFO_WIDTH : integer := 72
);
Port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
pfull : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
pempty : OUT std_logic;
empty : OUT std_logic;
data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : IN std_logic
);
end entity eb_wrapper_loopback;
architecture Behavioral of eb_wrapper_loopback is
--- 16384 x 72
component eb_fifo
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic;
rst : IN std_logic
);
end component;
--- 16384 x 64, with data count synchronized to rd_clk
component k7_eb_fifo_counted_resized
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1-8 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic;
rd_data_count : OUT std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
rst : IN std_logic
);
end component;
signal data_count_wire : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal data_count_i : std_logic_VECTOR(C_EMU_FIFO_DC_WIDTH-1 downto 0);
signal my_din : std_logic_VECTOR(64-1 downto 0);
signal my_dout : std_logic_VECTOR(64-1 downto 0);
begin
data_count <= data_count_i;
my_din <= din(64-1 downto 0);
dout(71 downto 64) <= C_ALL_ZEROS(71 downto 64);
dout(63 downto 0) <= my_dout;
-- ------------------------------------------
Syn_EB_FIFO_data_count:
process (rd_clk)
begin
if rd_clk'event and rd_clk = '1' then
data_count_i <= data_count_wire;
end if;
end process;
-- ------------------------------------------
U0:
k7_eb_fifo_counted_resized
port map (
wr_clk => wr_clk ,
wr_en => wr_en ,
din => my_din ,
prog_full => pfull ,
full => full ,
rd_clk => rd_clk ,
rd_en => rd_en ,
dout => my_dout ,
prog_empty => pempty ,
empty => empty ,
rd_data_count => data_count_wire ,
rst => rst
);
end architecture Behavioral;
| gpl-2.0 | c1a4db11070ed003736c32133bb6d7a2 | 0.515315 | 3.390385 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rd_fifo_256to64/example_design/rd_fifo_256to64_exdes.vhd | 1 | 5,687 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: rd_fifo_256to64_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity rd_fifo_256to64_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(12-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end rd_fifo_256to64_exdes;
architecture xilinx of rd_fifo_256to64_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component rd_fifo_256to64 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(12-1 DOWNTO 0);
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(64-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : rd_fifo_256to64
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | 21cb85938008991c2606a62ebb028e0c | 0.513628 | 4.653846 | false | false | false | false |
UnofficialRepos/OSVVM | RandomBasePkg.vhd | 1 | 24,542 | --
-- File Name: RandomBasePkg.vhd
-- Design Unit Name: RandomBasePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis [email protected]
--
--
-- Description:
-- Defines Base randomization, seed definition, seed generation,
-- and seed IO functionality for RandomPkg.vhd
-- Defines:
-- Procedure Uniform - baseline randomization
-- Type RandomSeedType - the seed as a single object
-- function GenRandSeed from integer_vector, integer, or string
-- IO function to_string, & procedures write, read
--
-- In revision 2.0 these types and functions are included by package reference.
-- Long term these will be passed as generics to RandomGenericPkg
--
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 06/2021 2021.06 Updated GenRandSeed hash to DJBX33A
-- 01/2020 2020.01 Updated Licenses to Apache
-- 6/2015 2015.06 Changed GenRandSeed to impure
-- 1/2015 2015.01 Changed Assert/Report to Alert
-- 5/2013 2013.05 No Changes
-- 4/2013 2013.04 No Changes
-- 03/01/2011 2.0 STANDARD VERSION
-- Fixed abstraction by moving RandomParmType to RandomPkg.vhd
-- 02/25/2009 1.1 Replaced reference to std_2008 with a reference
-- to ieee_proposed.standard_additions.all ;
-- 02/2009: 1.0 First Public Released Version
-- 01/2008: 0.1 Initial revision
-- Numerous revisions for VHDL Testbenches and Verification
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2008 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
library ieee ;
use ieee.math_real.all ;
use std.textio.all ;
use work.OsvvmGlobalPkg.all ;
use work.AlertLogPkg.all ;
use work.SortListPkg_int.all ;
-- comment out following 2 lines with VHDL-2008. Leave in for VHDL-2002
-- library ieee_proposed ; -- remove with VHDL-2008
-- use ieee_proposed.standard_additions.all ; -- remove with VHDL-2008
package RandomBasePkg is
constant OSVVM_RANDOM_ALERTLOG_ID : AlertLogIDType := OSVVM_ALERTLOG_ID ;
-----------------------------------------------------------------
-- note NULL_RANGE_TYPE should probably be in std.standard
subtype NULL_RANGE_TYPE is integer range 0 downto 1 ;
constant NULL_INTV : integer_vector (NULL_RANGE_TYPE) := (others => 0) ;
-----------------------------------------------------------------
-- RandomSeedType - Abstract the type for randomization
type RandomSeedType is array (1 to 2) of integer ;
-----------------------------------------------------------------
-- Uniform
-- Generate a random number with a Uniform distribution
-- Required by RandomPkg. All randomization is derived from here.
-- Value produced must be either:
-- 0 <= Value < 1 or 0 < Value < 1
--
-- Current version uses ieee.math_real.Uniform
-- This abstraction allows higher precision version
-- of a uniform distribution to be used provided
--
procedure Uniform (Result : out real ; Seed : inout RandomSeedType) ;
-----------------------------------------------------------------
-- GenRandSeed
-- Generate / hash a seed from a value that is integer_vector, String, Time, or Integer to RandomSeedType
-- Used by RandomPkg.InitSeed
-- GenRandSeed makes sure all values are in a valid range
impure function GenRandSeed (IV : integer_vector) return RandomSeedType ;
impure function OldGenRandSeed(IV : integer_vector) return RandomSeedType ;
impure function GenRandSeed (I : integer) return RandomSeedType ;
impure function OldGenRandSeed(I : integer) return RandomSeedType ;
impure function GenRandSeed (S : string) return RandomSeedType ;
impure function OldGenRandSeed(S : string) return RandomSeedType ;
-----------------------------------------------------------------
--- RandomSeedType IO
function to_string(A : RandomSeedType; Separator : string := " ") return string ;
procedure write(variable L: inout line ; A : RandomSeedType ) ;
procedure read (variable L: inout line ; A : out RandomSeedType ; good : out boolean ) ;
procedure read (variable L: inout line ; A : out RandomSeedType ) ;
-----------------------------------------------------------------
--- Distribution Types and read/write procedures
type RandomDistType is (NONE, UNIFORM, FAVOR_SMALL, FAVOR_BIG, NORMAL, POISSON) ;
type RandomParmType is record
Distribution : RandomDistType ;
Mean : Real ; -- also used as probability of success
StdDeviation : Real ; -- also used as number of trials for binomial
end record ;
-----------------------------------------------------------------
-- RandomParm IO
function to_string(A : RandomDistType) return string ;
procedure write(variable L : inout line ; A : RandomDistType ) ;
procedure read (variable L : inout line ; A : out RandomDistType ; good : out boolean ) ;
procedure read (variable L : inout line ; A : out RandomDistType ) ;
function to_string(A : RandomParmType) return string ;
procedure write(variable L : inout line ; A : RandomParmType ) ;
procedure read (variable L : inout line ; A : out RandomParmType ; good : out boolean ) ;
procedure read (variable L : inout line ; A : out RandomParmType ) ;
-----------------------------------------------------------------
--- Randomization Support
--- Scale - Scale a value to be within a given range
--- FavorSmall, FavorBig - Distribution Support
--- RemoveExclude
function Scale (A, Min, Max : real) return real ;
function Scale (A : real ; Min, Max : integer) return integer ;
function FavorSmall (A : real) return real ;
function FavorBig (A : real) return real ;
function to_time_vector (A : integer_vector ; Unit : time) return time_vector ;
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector ;
procedure RemoveExclude (A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) ;
function inside (A : real ; Exclude : real_vector) return boolean ;
procedure RemoveExclude (A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) ;
function inside (A : time ; Exclude : time_vector) return boolean ;
procedure RemoveExclude (A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) ;
end RandomBasePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body RandomBasePkg is
-----------------------------------------------------------------
-- Uniform
-- Generate a random number with a Uniform distribution
-- Required by RandomPkg. All randomization is derived from here.
-- Value produced must be either:
-- 0 <= Value < 1 or 0 < Value < 1
--
-- Current version uses ieee.math_real.Uniform
-- This abstraction allows higher precision version
-- of a uniform distribution to be used provided
--
-----------------------------------------------------------------
procedure Uniform (
-----------------------------------------------------------------
Result : out real ;
Seed : inout RandomSeedType
) is
begin
ieee.math_real.Uniform (Seed(Seed'left), Seed(Seed'right), Result) ;
end procedure Uniform ;
-----------------------------------------------------------------
-- GenRandSeed
-- Convert integer_vector to RandomSeedType
-- Uniform requires two seed values of the form:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
--
-- if 2 seed values are passed to GenRandSeed and they are
-- in the above range, then they must remain unmodified.
------------------------------------------------------------
impure function GenRandSeed(IV : integer_vector) return RandomSeedType is
------------------------------------------------------------
alias iIV : integer_vector(1 to IV'length) is IV ;
variable Seed1 : integer ;
variable Seed2 : integer ;
constant SEED1_MAX : integer := 2147483562 ;
constant SEED2_MAX : integer := 2147483398 ;
begin
if iIV'Length <= 0 then -- no seed
Alert(OSVVM_ALERTLOG_ID, "RandomBasePkg.GenRandSeed received NULL integer_vector", FAILURE) ;
return (3, 17) ; -- if continue seed = (3, 17)
elsif iIV'Length = 1 then -- one seed value
-- inefficient handling, but condition is unlikely
return GenRandSeed(iIV(1)) ; -- generate a seed
else -- only use the left two values
-- mod returns 0 to MAX-1, the -1 adjusts legal values, +1 adjusts them back
-- 1 <= SEED1 <= 2147483562
Seed1 := ((iIV(1)-1) mod SEED1_MAX) + 1 ;
-- 1 <= SEED2 <= 2147483398
Seed2 := ((iIV(2)-1) mod SEED2_MAX) + 1 ;
return (Seed1, Seed2) ;
end if ;
end function GenRandSeed ;
------------------------------------------------------------
impure function OldGenRandSeed(IV : integer_vector) return RandomSeedType is
------------------------------------------------------------
alias iIV : integer_vector(1 to IV'length) is IV ;
variable Seed1 : integer ;
variable Seed2 : integer ;
constant SEED1_MAX : integer := 2147483562 ;
constant SEED2_MAX : integer := 2147483398 ;
begin
if iIV'Length <= 0 then -- no seed
Alert(OSVVM_ALERTLOG_ID, "RandomBasePkg.GenRandSeed received NULL integer_vector", FAILURE) ;
return (3, 17) ; -- if continue seed = (3, 17)
elsif iIV'Length = 1 then -- one seed value
-- inefficient handling, but condition is unlikely
return OldGenRandSeed(iIV(1)) ; -- generate a seed
else -- only use the left two values
-- mod returns 0 to MAX-1, the -1 adjusts legal values, +1 adjusts them back
-- 1 <= SEED1 <= 2147483562
Seed1 := ((iIV(1)-1) mod SEED1_MAX) + 1 ;
-- 1 <= SEED2 <= 2147483398
Seed2 := ((iIV(2)-1) mod SEED2_MAX) + 1 ;
return (Seed1, Seed2) ;
end if ;
end function OldGenRandSeed ;
-----------------------------------------------------------------
-- GenRandSeed - Integer
impure function GenRandSeed(I : integer) return RandomSeedType is
-----------------------------------------------------------------
variable result : RandomSeedType ;
begin
result(1) := integer((real(I) * 5381.0 + 313.0) mod 2.0 ** 30) ;
result(2) := integer((real(I) * 313.0 + 5381.0) mod 2.0 ** 30) ;
return result ; -- make value ranges legal
end function GenRandSeed ;
-----------------------------------------------------------------
impure function OldGenRandSeed(I : integer) return RandomSeedType is
-----------------------------------------------------------------
variable result : integer_vector(1 to 2) ;
begin
result(1) := I ;
result(2) := I/3 + 1 ;
return OldGenRandSeed(result) ; -- make value ranges legal
end function OldGenRandSeed ;
-----------------------------------------------------------------
-- GenRandSeed - String
-- usage: RV.GenRandSeed(RV'instance_path));
-- hash based on DJBX33A
impure function GenRandSeed(S : string) return RandomSeedType is
-----------------------------------------------------------------
constant LEN : integer := S'length ;
constant HALF_LEN : integer := LEN/2 ;
alias revS : string(LEN downto 1) is S ;
variable result : RandomSeedType ;
variable temp : real := 5381.0 ;
begin
for i in 1 to HALF_LEN loop
temp := (temp*33.0 + real(character'pos(revS(i)))) mod (2.0**30) ;
end loop ;
result(1) := integer(temp) ;
for i in HALF_LEN + 1 to LEN loop
temp := (temp*33.0 + real(character'pos(revS(i)))) mod (2.0**30) ;
end loop ;
result(2) := integer(temp) ;
return result ;
end function GenRandSeed ;
-----------------------------------------------------------------
impure function OldGenRandSeed(S : string) return RandomSeedType is
-----------------------------------------------------------------
constant LEN : integer := S'length ;
constant HALF_LEN : integer := LEN/2 ;
alias revS : string(LEN downto 1) is S ;
variable result : integer_vector(1 to 2) ;
variable temp : integer := 0 ;
begin
for i in 1 to HALF_LEN loop
temp := (temp + character'pos(revS(i))) mod (integer'right - 2**8) ;
end loop ;
result(1) := temp ;
for i in HALF_LEN + 1 to LEN loop
temp := (temp + character'pos(revS(i))) mod (integer'right - 2**8) ;
end loop ;
result(2) := temp ;
return OldGenRandSeed(result) ; -- make value ranges legal
end function OldGenRandSeed ;
-----------------------------------------------------------------
-- RandomSeedType IO
--
-----------------------------------------------------------------
function to_string(A : RandomSeedType; Separator : string := " ") return string is
-----------------------------------------------------------------
begin
return to_string(A(A'left)) & Separator & to_string(A(A'right)) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L: inout line ; A : RandomSeedType ) is
-----------------------------------------------------------------
begin
write(L, to_string(A)) ;
end procedure ;
-----------------------------------------------------------------
procedure read(variable L: inout line ; A : out RandomSeedType ; good : out boolean ) is
-----------------------------------------------------------------
variable iReadValid : boolean ;
begin
for i in A'range loop
read(L, A(i), iReadValid) ;
exit when not iReadValid ;
end loop ;
good := iReadValid ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L: inout line ; A : out RandomSeedType ) is
-----------------------------------------------------------------
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot(ReadValid, OSVVM_ALERTLOG_ID, "RandomBasePkg.read[line, RandomSeedType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-- RandomParmType IO
--
-----------------------------------------------------------------
function to_string(A : RandomDistType) return string is
-----------------------------------------------------------------
begin
return RandomDistType'image(A) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomDistType ) is
-----------------------------------------------------------------
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ; good : out boolean ) is
-----------------------------------------------------------------
variable strval : string(1 to 40) ;
variable len : natural ;
begin
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A := RandomDistType'value(strval(1 to len)) ;
good := len > 0 ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomDistType ) is
-----------------------------------------------------------------
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomDistType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
function to_string(A : RandomParmType) return string is
-----------------------------------------------------------------
begin
return RandomDistType'image(A.Distribution) & " " &
to_string(A.Mean, 2) & " " & to_string(A.StdDeviation, 2) ;
end function to_string ;
-----------------------------------------------------------------
procedure write(variable L : inout line ; A : RandomParmType ) is
-----------------------------------------------------------------
begin
write(L, to_string(A)) ;
end procedure write ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ; good : out boolean ) is
-----------------------------------------------------------------
variable strval : string(1 to 40) ;
variable len : natural ;
variable igood : boolean ;
begin
loop
-- procedure SREAD (L : inout LINE ; VALUE : out STRING ; STRLEN : out NATURAL) ;
sread(L, strval, len) ;
A.Distribution := RandomDistType'value(strval(1 to len)) ;
igood := len > 0 ;
exit when not igood ;
read(L, A.Mean, igood) ;
exit when not igood ;
read(L, A.StdDeviation, igood) ;
exit ;
end loop ;
good := igood ;
end procedure read ;
-----------------------------------------------------------------
procedure read(variable L : inout line ; A : out RandomParmType ) is
-----------------------------------------------------------------
variable ReadValid : boolean ;
begin
read(L, A, ReadValid) ;
AlertIfNot( OSVVM_ALERTLOG_ID, ReadValid, "RandomPkg.read[line, RandomParmType] failed", FAILURE) ;
end procedure read ;
-----------------------------------------------------------------
-- Randomization Support
-- Scale - Scale a value to be within a given range
-- FavorSmall, FavorBig - Distribution Support
-- RemoveExclude
--
-----------------------------------------------------------------
-- Scale - Scale a value to be within a given range
function Scale (A, Min, Max : real) return real is
-----------------------------------------------------------------
variable ValRange : Real ;
begin
ValRange := Max - Min ;
return A * ValRange + Min ;
--!! -- Already done checked and failed if error.
--!! -- If continuing this calculation is no worse than returning real'left
--!! if Max >= Min then
--!! ValRange := Max - Min ;
--!! return A * ValRange + Min ;
--!! else
--!! return real'left ;
--!! end if ;
end function Scale ;
-----------------------------------------------------------------
function Scale (A : real ; Min, Max : integer) return integer is
-----------------------------------------------------------------
variable ValRange : real ;
variable rMin, rMax : real ;
begin
rMin := real(Min) - 0.5 ;
rMax := real(Max) + 0.5 ;
ValRange := rMax - rMin ;
return integer(round(A * ValRange + rMin)) ;
--!! -- Already done checked and failed if error.
--!! -- If continuing this calculation is no worse than returning real'left
--!! if Max >= Min then
--!! rMin := real(Min) - 0.5 ;
--!! rMax := real(Max) + 0.5 ;
--!! ValRange := rMax - rMin ;
--!! return integer(round(A * ValRange + rMin)) ;
--!! else
--!! return integer'left ;
--!! end if ;
end function Scale ;
-----------------------------------------------------------------
-- FavorSmall - create more smaller values
function FavorSmall (A : real) return real is
-----------------------------------------------------------------
begin
return 1.0 - sqrt(A) ;
end FavorSmall ;
-----------------------------------------------------------------
-- FavorBig - create more larger values
-- alias FavorBig is sqrt[real return real] ;
function FavorBig (A : real) return real is
-----------------------------------------------------------------
begin
return sqrt(A) ;
end FavorBig ;
-----------------------------------------------------------------
-- local.
function to_time_vector (A : integer_vector ; Unit : time) return time_vector is
-----------------------------------------------------------------
variable result : time_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) * Unit ;
end loop ;
return result ;
end function to_time_vector ;
-----------------------------------------------------------------
-- local
function to_integer_vector (A : time_vector ; Unit : time) return integer_vector is
-----------------------------------------------------------------
variable result : integer_vector(A'range) ;
begin
for i in A'range loop
result(i) := A(i) / Unit ;
end loop ;
return result ;
end function to_integer_vector ;
-----------------------------------------------------------------
-- Remove the exclude list from the list - integer_vector
procedure RemoveExclude(A, Exclude : integer_vector ; variable NewA : out integer_vector ; variable NewALength : inout natural ) is
-----------------------------------------------------------------
alias norm_NewA : integer_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- Inside - real_vector
function inside(A : real ; Exclude : real_vector) return boolean is
-----------------------------------------------------------------
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-----------------------------------------------------------------
-- Remove the exclude list from the list - real_vector
procedure RemoveExclude(A, Exclude : real_vector ; variable NewA : out real_vector ; variable NewALength : inout natural ) is
-----------------------------------------------------------------
alias norm_NewA : real_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
-----------------------------------------------------------------
-- Inside - time_vector
function inside(A : time ; Exclude : time_vector) return boolean is
-----------------------------------------------------------------
begin
for i in Exclude'range loop
if A = Exclude(i) then
return TRUE ;
end if ;
end loop ;
return FALSE ;
end function inside ;
-----------------------------------------------------------------
-- Remove the exclude list from the list - time_vector
procedure RemoveExclude(A, Exclude : time_vector ; variable NewA : out time_vector ; variable NewALength : inout natural ) is
-----------------------------------------------------------------
alias norm_NewA : time_vector(1 to NewA'length) is NewA ;
begin
NewALength := 0 ;
for i in A'range loop
if not inside(A(i), Exclude) then
NewALength := NewALength + 1 ;
norm_NewA(NewALength) := A(i) ;
end if ;
end loop ;
end procedure RemoveExclude ;
end RandomBasePkg ; | artistic-2.0 | 6fedfc1426bae4a500b18bb0066ffa4f | 0.510431 | 4.538931 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/rom_8192x32/simulation/rom_8192x32_tb.vhd | 1 | 4,373 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: rom_8192x32_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY rom_8192x32_tb IS
END ENTITY;
ARCHITECTURE rom_8192x32_tb_ARCH OF rom_8192x32_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
rom_8192x32_synth_inst:ENTITY work.rom_8192x32_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| gpl-2.0 | a8e18613b3a0749ee4ffe65f405945b1 | 0.620627 | 4.583857 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_tb.vhd | 1 | 6,092 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
ENTITY counter_fifo_tb IS
END ENTITY;
ARCHITECTURE counter_fifo_arch OF counter_fifo_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 200 ns;
CONSTANT rd_clk_period_by_2 : TIME := 100 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 400 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 200 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from counter_fifo_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of counter_fifo_synth
counter_fifo_synth_inst:counter_fifo_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 36
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
| gpl-2.0 | 2d6864d5ee08f79fa1b7f527aad9924d | 0.616382 | 4.1414 | false | false | false | false |
peteut/nvc | test/parse/bitstring.vhd | 1 | 541 | PACKAGE bitstring IS
CONSTANT x : t := X"1234";
CONSTANT y : t := O"1234";
CONSTANT z : t := X"ab";
CONSTANT b : t := B"101";
CONSTANT c : t := x"f";
CONSTANT d : t := X"a_b";
CONSTANT e : t := B"1111_1111_1111";
CONSTANT f : t := X"FFF";
CONSTANT g : t := O"777";
CONSTANT h : t := X"777";
CONSTANT i : t := B%1111_1111_1111%;
CONSTANT j : t := X%FFF%;
CONSTANT k : t := O%777%;
CONSTANT l : t := X%777%;
END PACKAGE;
PACKAGE bitstring_error IS
CONSTANT e1 : t := O"9"; -- Error
END PACKAGE;
| gpl-3.0 | a613404c3ca7cbbc60dfb90642a0853e | 0.537893 | 2.893048 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x8k_dp/simulation/ram_16x8k_dp_tb.vhd | 1 | 4,435 | --------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ram_16x8k_dp_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ram_16x8k_dp_tb IS
END ENTITY;
ARCHITECTURE ram_16x8k_dp_tb_ARCH OF ram_16x8k_dp_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ram_16x8k_dp_synth_inst:ENTITY work.ram_16x8k_dp_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
| bsd-3-clause | 95eae4d2d999acb2dabfd40eafeedf29 | 0.615107 | 4.461771 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/k7_sfifo_15x128/simulation/k7_sfifo_15x128_pctrl.vhd | 1 | 15,417 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: k7_sfifo_15x128_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.k7_sfifo_15x128_pkg.ALL;
ENTITY k7_sfifo_15x128_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF k7_sfifo_15x128_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 50 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:k7_sfifo_15x128_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:k7_sfifo_15x128_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | aa93efee4626a6e1560c58a3fe9a4164 | 0.520464 | 3.365422 | false | false | false | false |
tutkowskim/UART | uart_rx.vhd | 1 | 1,295 | library ieee;
use ieee.std_logic_1164.all;
entity UART_RX is
port(
RX : in std_logic;
CLK : in std_logic;
RST : in std_logic;
DR : out std_logic;
DA : out std_logic_vector(7 downto 0)
);
end entity UART_RX;
architecture BEHAVORIAL of UART_RX is
type STATES is (IDLE,START,DATA0,DATA1,DATA2,DATA3,DATA4,DATA5,DATA6,DATA7,STOP);
signal Q, D : STATES;
begin
SEND: process(RX,CLK,RST)
begin
if RST = '0' Then
Q <= IDLE;
DR <= '0';
elsif rising_edge(CLK) then
Q <= D;
end if;
case Q is
when IDLE =>
If RX = '0' then
D <= START;
Else
D <= IDLE;
End if;
DR <= '0';
when START =>
D <= DATA0;
DR <= '0';
when DATA0 =>
DA(0) <= RX;
D <= DATA1;
DR <= '0';
when DATA1 =>
DA(1) <= RX;
D <= DATA2;
DR <= '0';
when DATA2 =>
DA(2) <= RX;
D <= DATA3;
DR <= '0';
when DATA3 =>
DA(3) <= RX;
D <= DATA4;
DR <= '0';
when DATA4 =>
DA(4) <= RX;
D <= DATA5;
DR <= '0';
when DATA5 =>
DA(5) <= RX;
D <= DATA6;
DR <= '0';
when DATA6 =>
DA(6) <= RX;
D <= DATA7;
DR <= '0';
when DATA7 =>
DA(7) <= RX;
D <= STOP;
DR <= '0';
when STOP =>
D <= IDLE;
DR <= '1';
end case;
end process;
end architecture BEHAVORIAL;
| mit | 3ac720bdbbe97cd47f6fc829bcad57e0 | 0.491892 | 2.416045 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/counter_fifo/simulation/counter_fifo_pctrl.vhd | 1 | 18,301 |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: counter_fifo_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.counter_fifo_pkg.ALL;
ENTITY counter_fifo_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF counter_fifo_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 100 ns;
PRC_RD_EN <= prc_re_i AFTER 50 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:counter_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:counter_fifo_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
| gpl-2.0 | 2f0428c9f0e859710d0bb534bfefa095 | 0.50948 | 3.25409 | false | false | false | false |
peteut/nvc | test/sem/scope.vhd | 1 | 7,719 | package pack1 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
package pack2 is
type my_int1 is range 0 to 10;
end package;
-------------------------------------------------------------------------------
use work.pack1;
use work.pack2;
entity no_use_clause is
port (
a : in pack1.my_int1;
b : out pack2.my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of no_use_clause is
type my_int1 is range 10 to 50;
begin
process is
begin
-- Should fail as types have same name but from different packages
b <= a;
end process;
process is
variable v : pack2.my_int1;
begin
b <= v; -- OK
end process;
process is
variable v : my_int1;
begin
-- Should fail as local my_int1 distinct from pack1.my_int1
v := a;
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack1.all;
entity foo is
generic ( g : my_int1 );
port ( p : in my_int1 );
end entity;
-------------------------------------------------------------------------------
architecture a of foo is
-- Architecture decls exist in same scope as entity so this should
-- generate an error
signal g : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture b of foo is
-- Should also generate an error
signal p : my_int1;
begin
end architecture;
-------------------------------------------------------------------------------
architecture c of foo is
begin
-- This is OK as processes define a new scope
process is
variable p : my_int1;
variable g : my_int1;
begin
g := 6;
p := 2;
wait for 1 ns;
end process;
end architecture;
-------------------------------------------------------------------------------
entity overload is
port (
SI: in bit;
SO: out bit
);
end ;
architecture behave of overload is
begin
foo_inst:
SO <= SI;
end behave;
-------------------------------------------------------------------------------
use work.all;
entity no_use_clause is
port (
a : in pack1.my_int1; -- OK
b : out my_int1 ); -- Error
end entity;
-------------------------------------------------------------------------------
package pack3 is
type my_enum is (E1, E2, E3);
end package;
-------------------------------------------------------------------------------
use work.pack3.all;
package pack4 is
type my_enum_array is array (integer range <>) of my_enum;
end package;
-------------------------------------------------------------------------------
use work.pack4.all;
architecture a of foo is
signal x : my_enum_array(1 to 3); -- OK
signal y : my_enum_array(1 to 3) := (others => E1);
-- Error: E1 not visible
begin
end architecture;
-------------------------------------------------------------------------------
package pack5 is
function func1(x : integer) return boolean;
function func2(x : integer) return boolean;
function "and"(x, y : integer) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack5.func1;
architecture a2 of foo is
begin
process is
begin
assert func1(4); -- OK
assert func2(5); -- Error
end process;
end architecture;
-------------------------------------------------------------------------------
use work.pack5.not_here; -- Error
architecture a3 of foo is
begin
end architecture;
-------------------------------------------------------------------------------
entity bar is
end entity;
architecture a4 of bar is
begin
process is
use work.pack1.all;
variable x : my_int1; -- OK
begin
x := 5;
end process;
process is
variable x : my_int1; -- Error
begin
end process;
b: block is
use work.pack1;
signal x : pack1.my_int1; -- OK
begin
end block;
end architecture;
-------------------------------------------------------------------------------
use work.pack5."and";
architecture a5 of bar is
begin
process is
begin
assert 1 and 2; -- OK
assert work.pack5."and"(1, 2); -- OK
assert pack5."and"(1, 2); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
package pack6 is
component bar is
end component;
end package;
-------------------------------------------------------------------------------
use work.pack6.all;
architecture a6 of bar is
begin
process is
begin
report bar'path_name; -- OK (references entity)
end process;
end architecture;
-------------------------------------------------------------------------------
use foo.bar.all; -- Error
architecture a7 of bar is
begin
end architecture;
-------------------------------------------------------------------------------
package pack7 is
function foo(x : in integer) return boolean;
function foo(y : in real) return boolean;
end package;
-------------------------------------------------------------------------------
use work.pack7.foo;
architecture issue62 of bar is
begin
process is
begin
assert foo(integer'(1)); -- OK
assert foo(real'(1.6)); -- OK
end process;
end architecture;
-------------------------------------------------------------------------------
use work.all;
use work.pack1.all;
architecture issue63 of bar is
signal x : my_int1; -- OK
begin
end architecture;
-------------------------------------------------------------------------------
package pack8 is
function min(x, y : in integer) return integer;
end package;
-------------------------------------------------------------------------------
use work.pack8.all; -- OK
architecture unit_decl_crash of bar is
begin
process is
variable x : integer := min(1, 2); -- OK
begin
end process;
end architecture;
-------------------------------------------------------------------------------
architecture labels of bar is
signal mySignalVector: bit_vector (7 downto 0);
signal myOtherSignal: bit := '1';
begin
process
begin
L1:
for i in 0 to 9 loop
for i in 0 to 7 loop
mySignalVector(i) <= myOtherSignal;
report "outer loop i = " & integer'image(L1.i);
report "inner loop i = " & integer'image(i);
report integer'image(L1.x); -- Error
end loop;
end loop;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
architecture more_labels of bar is
begin
p1: process is
variable x : boolean;
begin
p1.x := true; -- OK
for x in 1 to 10 loop
p1.x := false; -- OK
end loop;
end process;
b1: block is
constant x : integer := 2;
begin
process is
variable x : boolean;
begin
x := true; -- OK
assert b1.x = 2; -- OK
end process;
end block;
end architecture;
| gpl-3.0 | 36a8c5174cd886c5a310b76194c0126e | 0.407436 | 4.818352 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/ipcore_dir/test_image/simulation/test_image_synth.vhd | 1 | 7,890 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: test_image_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY test_image_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE test_image_synth_ARCH OF test_image_synth IS
COMPONENT test_image_exdes
PORT (
--Inputs - Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 8,
READ_WIDTH => 8 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECKER_EN AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLK => clk_in_i,
RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
WEA => WEA,
CHECK_DATA => CHECKER_EN
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: test_image_exdes PORT MAP (
--Port A
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA
);
END ARCHITECTURE;
| bsd-2-clause | d9ef8c5dd3895ff085b8b2d3430bc18c | 0.565019 | 3.771511 | false | false | false | false |
dcsun88/ntpserver-fpga | cpu/ip/cpu_axi_epc_0_0/axi_epc_v2_0/hdl/src/vhdl/access_mux.vhd | 1 | 25,607 |
-------------------------------------------------------------------------------
-- access_mux.vhd - entity/architecture pair
-------------------------------------------------------------------------------
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2005, 2006, 2008, 2009 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
-------------------------------------------------------------------------------
-- File : access_mux.vhd
-- Company : Xilinx
-- Version : v1.00.a
-- Description : Multiplexes the device ready signal from external periphera.
-- -- It also multiplexes the address and data bus to be driven out
-- -- to the external peripheral devices
-- Standard : VHDL-93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Structure:
-- axi_epc.vhd
-- -axi_lite_ipif
-- -epc_core.vhd
-- -ipic_if_decode.vhd
-- -sync_cntl.vhd
-- -async_cntl.vhd
-- -- async_counters.vhd
-- -- async_statemachine.vhd
-- -address_gen.vhd
-- -data_steer.vhd
-- -access_mux.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Author : VB
-- History :
--
-- VB 08-24-2010 -- v2_0 version for AXI
-- ^^^^^^
-- The core updated for AXI based on xps_epc_v1_02_a
-- ~~~~~~
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library axi_lite_ipif_v3_0;
use axi_lite_ipif_v3_0.ipif_pkg.INTEGER_ARRAY_TYPE;
-------------------------------------------------------------------------------
-- Definition of Generics --
-------------------------------------------------------------------------------
-- C_NUM_PERIPHERALS - No of peripherals currently configured
-- C_PRH_MAX_AWIDTH - Maximum of address bus width of all peripherals
-- C_PRH_MAX_DWIDTH - Maximum of data bus width of all peripherals
-- C_PRH_MAX_ADWIDTH - Maximum of data bus width of all peripherals and
-- - address bus width of peripherals employing bus
-- - multiplexing
-- C_PRH(0:3)_AWIDTH - Address bus width of peripherals
-- C_PRH(0:3)_DWIDTH - Data bus width of peripherals
-- C_PRH(0:3)_BUS_MULTIPLEX - Indication if the peripheral employs address/data
-- - bus multiplexing
-- MAX_PERIPHERALS - Maximum no of peripherals supported by external
-- - peripheral controller
-- NO_PRH_SYNC - Indicates all devices are configured for
-- asynchronous interface
-- NO_PRH_ASYNC - Indicates all devices are configured for
-- synchronous interface
-- NO_PRH_BUS_MULTIPLEX - Indicates that no device is employing
-- multiplexed bus for address and data
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports --
-------------------------------------------------------------------------------
-- Dev_id - The decoded identification vector for the currently
-- - selected device
-- Dev_sync - Indicates if the current device being accessed
-- is synchronous device
-- Dev_dbus_width - Indicates the data bus width of current device
-- Sync_CS_n - Chip select signals for the peripherals
-- - from synchronous control
-- Sync_ADS - Address strobe from synchronous control
-- Sync_RNW - Read/Write control from synchronous control
-- Sync_Burst - Burst indication from synchronous control
-- Sync_addr_ph - Address phase indication from synchronous control
-- in case of multiplexed address and data bus
-- Sync_data_oe - Data bus output enable from synchronous control
-- Async_CS_n - Chip select signals for the peripherals from
-- - asynchronous control
-- Async_ADS - Address strobe from asynchronous control
-- Async_Rd_n - Read control from asynchronous control
-- Async_Wr_n - Write control from asynchronous control
-- Async_addr_ph - Address phase indication from asynchronous control
-- in case of multiplexed address and data bus
-- Async_data_oe - Data bus output enable from asynchronous control
-- Addr_Int - Internal peripheral address bus
-- Data_Int - Internal peripheral data bus
-- PRH_CS_n - Peripheral chip select signals
-- PRH_ADS - Peripheral address strobe
-- PRH_RNW - Peripheral read/write control
-- PRH_Rd_n - Peripheral read strobe
-- PRH_Wr_n - Peripheral write strobe
-- PRH_Burst - Peripheral burst indication
-- PRH_Rdy - Peripheral ready indication
-- Dev_Rdy - Device ready indication from currently selected
-- - device driven to internal logic
-- PRH_Addr - Peripheral address bus
-- PRH_Data_O - Peripheral output data bus
-- PRH_Data_T - 3-state control for peripheral output data bus
-------------------------------------------------------------------------------
entity access_mux is
generic (
C_NUM_PERIPHERALS : integer;
C_PRH_MAX_AWIDTH : integer;
C_PRH_MAX_DWIDTH : integer;
C_PRH_MAX_ADWIDTH : integer;
C_PRH0_AWIDTH : integer;
C_PRH1_AWIDTH : integer;
C_PRH2_AWIDTH : integer;
C_PRH3_AWIDTH : integer;
C_PRH0_DWIDTH : integer;
C_PRH1_DWIDTH : integer;
C_PRH2_DWIDTH : integer;
C_PRH3_DWIDTH : integer;
C_PRH0_BUS_MULTIPLEX : integer;
C_PRH1_BUS_MULTIPLEX : integer;
C_PRH2_BUS_MULTIPLEX : integer;
C_PRH3_BUS_MULTIPLEX : integer;
MAX_PERIPHERALS : integer;
NO_PRH_SYNC : integer;
NO_PRH_ASYNC : integer;
NO_PRH_BUS_MULTIPLEX : integer
);
port (
Local_Clk : in std_logic;
Dev_id : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
--Dev_sync : in std_logic;
--Dev_dbus_width : in std_logic_vector(0 to 2);
Sync_CS_n : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Sync_ADS : in std_logic;
Sync_RNW : in std_logic;
Sync_Burst : in std_logic;
Sync_addr_ph : in std_logic;
Sync_data_oe : in std_logic;
Async_CS_n : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Async_ADS : in std_logic;
Async_Rd_n : in std_logic;
Async_Wr_n : in std_logic;
Async_addr_ph : in std_logic;
Async_data_oe : in std_logic;
Addr_Int : in std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
Data_Int : in std_logic_vector(0 to C_PRH_MAX_DWIDTH-1);
PRH_CS_n : out std_logic_vector(0 to C_NUM_PERIPHERALS-1);
PRH_ADS : out std_logic;
PRH_RNW : out std_logic;
PRH_Rd_n : out std_logic;
PRH_Wr_n : out std_logic;
PRH_Burst : out std_logic;
PRH_Rdy : in std_logic_vector(0 to C_NUM_PERIPHERALS-1);
Dev_Rdy : out std_logic;
PRH_Addr : out std_logic_vector(0 to C_PRH_MAX_AWIDTH-1);
PRH_Data_O : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1);
PRH_Data_T : out std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1)
);
end entity access_mux;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture imp of access_mux is
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- NAME: get_adbus_width
-----------------------------------------------------------------------------
-- Description: XPS EPC supports bus multiplexing. If bus is multiplexed
-- the value of data bus width will be maximum of address bus
-- and data bus of the device.
-----------------------------------------------------------------------------
function get_adbus_width (bmux : integer;
awidth : integer;
dwidth : integer)
return integer is
variable adwidth : integer;
begin
if bmux = 0 then
adwidth := dwidth;
else
if dwidth > awidth then
adwidth := dwidth;
else
adwidth := awidth;
end if;
end if;
return adwidth;
end function get_adbus_width;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant PRH_ADWIDTH_ARRAY : INTEGER_ARRAY_TYPE(0 to MAX_PERIPHERALS-1) :=
( get_adbus_width(C_PRH0_BUS_MULTIPLEX, C_PRH0_AWIDTH, C_PRH0_DWIDTH),
get_adbus_width(C_PRH1_BUS_MULTIPLEX, C_PRH1_AWIDTH, C_PRH1_DWIDTH),
get_adbus_width(C_PRH2_BUS_MULTIPLEX, C_PRH2_AWIDTH, C_PRH2_DWIDTH),
get_adbus_width(C_PRH3_BUS_MULTIPLEX, C_PRH3_AWIDTH, C_PRH3_DWIDTH)
);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal addr_ph : std_logic := '0';
signal addr_out : std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1) :=
(others => '0');
signal data_out : std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1) :=
(others => '0');
--
signal sync_data_oe_i : std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1) :=
(others => '0');
signal async_data_oe_i : std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1) :=
(others => '0');
signal sync_async_data_oe_i : std_logic_vector(0 to C_PRH_MAX_ADWIDTH-1) :=
(others => '0');
signal prh_cs_n_i : std_logic_vector(0 to C_NUM_PERIPHERALS-1);
--
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- NAME: ALL_DEV_SYNC_GEN
-------------------------------------------------------------------------------
-- Description: All devices are configured as synchronous devices
-------------------------------------------------------------------------------
ALL_DEV_SYNC_GEN: if NO_PRH_ASYNC = 1 generate
REG_PRH_SIGS40 : process(Local_Clk)
begin
if(Local_Clk'event and Local_Clk = '1')then
PRH_CS_n <= Sync_CS_n;
PRH_ADS <= Sync_ADS;
PRH_RNW <= Sync_RNW;
PRH_Rd_n <= '1';
PRH_Wr_n <= '1';
PRH_Burst <= Sync_Burst;
end if;
end process REG_PRH_SIGS40;
-----------------------------------------------------------------------------
-- NAME: REG_PRH_SIGS41
-----------------------------------------------------------------------------
-- Description: register output data bus enable for each bit in sync mode
-----------------------------------------------------------------------------
REG_PRH_SIGS41 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
for i in 0 to C_PRH_MAX_ADWIDTH-1 loop
sync_data_oe_i(i) <= not (Sync_data_oe);
end loop;
end if;
end process REG_PRH_SIGS41;
-----------------------------------------------------------------------------
-- NAME: PRH_DATA_T_GEN
-----------------------------------------------------------------------------
-- Description: Generate output data bus enable for each bit of data bus
-----------------------------------------------------------------------------
PRH_DATA_T_GEN: for i in 0 to C_PRH_MAX_ADWIDTH-1 generate
PRH_Data_T(i) <= sync_data_oe_i(i);
end generate PRH_DATA_T_GEN;
end generate ALL_DEV_SYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: ALL_DEV_ASYNC_GEN
-------------------------------------------------------------------------------
-- Description: All devices are configured as asynchronous devices
-------------------------------------------------------------------------------
ALL_DEV_ASYNC_GEN: if NO_PRH_SYNC = 1 generate
REG_PRH_SIGS42 : process(Local_Clk)
begin
if(Local_Clk'event and Local_Clk = '1')then
PRH_CS_n <= Async_CS_n;
PRH_ADS <= Async_ADS;
PRH_RNW <= '1';
PRH_Rd_n <= Async_Rd_n;
PRH_Wr_n <= Async_Wr_n;
PRH_Burst <= '0';
end if;
end process REG_PRH_SIGS42;
-----------------------------------------------------------------------------
-- NAME: PRH_DATA_T_GEN
-----------------------------------------------------------------------------
-- Description: Generate output data bus enable for each bit of data bus
-----------------------------------------------------------------------------
REG_PRH_SIGS43 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
for i in 0 to C_PRH_MAX_ADWIDTH-1 loop
async_data_oe_i(i) <= not (Async_data_oe);
end loop;
end if;
end process REG_PRH_SIGS43;
PRH_DATA_T_GEN: for i in 0 to C_PRH_MAX_ADWIDTH-1 generate
PRH_Data_T(i) <= async_data_oe_i(i);
end generate PRH_DATA_T_GEN;
end generate ALL_DEV_ASYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: DEV_SYNC_AND_ASYNC_GEN
-------------------------------------------------------------------------------
-- Description: Some devices are configured as synchronous and some
-- asynchronous
-------------------------------------------------------------------------------
DEV_SYNC_AND_ASYNC_GEN: if NO_PRH_SYNC = 0 and NO_PRH_ASYNC = 0 generate
-----------------------------------------------------------------------------
-- NAME: PRH_CS_N_GEN
-----------------------------------------------------------------------------
-- Description: Generate chip select for external peripheral device
-----------------------------------------------------------------------------
REG_PRH_SIGS44 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
for i in 0 to C_NUM_PERIPHERALS-1 loop
prh_cs_n_i(i) <= Sync_CS_n(i) and Async_CS_n(i);
end loop;
end if;
end process REG_PRH_SIGS44;
-- PRH_CS_N_GEN: Generate the PRH_CS_n signal.
PRH_CS_N_GEN: for i in 0 to C_NUM_PERIPHERALS-1 generate
PRH_CS_n(i) <= prh_cs_n_i(i);
end generate PRH_CS_N_GEN;
-- REG_PRH_SIGS45 : Register the PRH_* signals
REG_PRH_SIGS45 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
PRH_ADS <= Sync_ADS or Async_ADS;
PRH_RNW <= Sync_RNW;
PRH_Rd_n <= Async_Rd_n;
PRH_Wr_n <= Async_Wr_n;
PRH_Burst <= Sync_Burst;
end if;
end process REG_PRH_SIGS45;
-----------------------------------------------------------------------------
-- NAME: PRH_DATA_T_GEN
-----------------------------------------------------------------------------
-- Description: Generate output data bus enable for each bit of data bus
-----------------------------------------------------------------------------
REG_PRH_SIGS46 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
for i in 0 to C_PRH_MAX_ADWIDTH-1 loop
sync_async_data_oe_i(i) <= not((Async_data_oe) xor (Sync_data_oe));
end loop;
end if;
end process REG_PRH_SIGS46;
PRH_DATA_T_GEN: for i in 0 to C_PRH_MAX_ADWIDTH-1 generate
PRH_Data_T(i) <= sync_async_data_oe_i(i);
end generate PRH_DATA_T_GEN;
end generate DEV_SYNC_AND_ASYNC_GEN;
-------------------------------------------------------------------------------
-- NAME: NO_PRH_BUS_MULTIPLEX_GEN
-------------------------------------------------------------------------------
-- Description: No peripheral employs bus multiplexing for address/data bus
-------------------------------------------------------------------------------
NO_PRH_BUS_MULTIPLEX_GEN: if NO_PRH_BUS_MULTIPLEX = 1 generate
addr_ph <= '0';
REG_PRH_SIGS47 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
PRH_Data_O(0 to C_PRH_MAX_DWIDTH-1) <= Data_Int;
end if;
end process REG_PRH_SIGS47;
end generate NO_PRH_BUS_MULTIPLEX_GEN;
-------------------------------------------------------------------------------
-- NAME: PRH_BUS_MULTIPLEX_GEN
-------------------------------------------------------------------------------
-- Description: Atleast some peripheral employs bus multiplexing
-------------------------------------------------------------------------------
PRH_BUS_MULTIPLEX_GEN: if NO_PRH_BUS_MULTIPLEX = 0 generate
addr_ph <= Sync_addr_ph or Async_addr_ph;
-----------------------------------------------------------------------------
-- NAME: ADDR_OUT_PROCESS
-----------------------------------------------------------------------------
-- Description: Generate adddress out for the current device
-----------------------------------------------------------------------------
ADDR_OUT_PROCESS: process (Dev_id, Addr_Int) is
begin
addr_out <= (others => '0');
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Dev_id(i) = '1') then
if (PRH_ADWIDTH_ARRAY(i) > C_PRH_MAX_AWIDTH) then
addr_out(0 to PRH_ADWIDTH_ARRAY(i)-C_PRH_MAX_AWIDTH-1)
<= (others => '0');
addr_out(PRH_ADWIDTH_ARRAY(i)-C_PRH_MAX_AWIDTH
to PRH_ADWIDTH_ARRAY(i)-1)
<= Addr_Int(0 to C_PRH_MAX_AWIDTH-1);
if (PRH_ADWIDTH_ARRAY(i) < C_PRH_MAX_ADWIDTH) then
addr_out(PRH_ADWIDTH_ARRAY(i) to C_PRH_MAX_ADWIDTH-1)
<= (others => '0');
end if;
else
addr_out(0 to PRH_ADWIDTH_ARRAY(i)-1) <=
Addr_Int(C_PRH_MAX_AWIDTH-PRH_ADWIDTH_ARRAY(i)
to C_PRH_MAX_AWIDTH-1);
if (PRH_ADWIDTH_ARRAY(i) < C_PRH_MAX_ADWIDTH) then
addr_out(PRH_ADWIDTH_ARRAY(i) to C_PRH_MAX_ADWIDTH-1)
<= (others => '0');
end if;
end if;
end if;
end loop;
end process ADDR_OUT_PROCESS;
data_out(0 to C_PRH_MAX_DWIDTH-1) <= Data_Int;
-----------------------------------------------------------------------------
-- NAME: DWIDTH_LT_ADWIDTH_GEN
-----------------------------------------------------------------------------
-- Description: Tie higher bits of data bus to zero
-----------------------------------------------------------------------------
DWIDTH_LT_ADWIDTH_GEN: if C_PRH_MAX_DWIDTH < C_PRH_MAX_ADWIDTH generate
data_out(C_PRH_MAX_DWIDTH to C_PRH_MAX_ADWIDTH-1) <= (others => '0');
end generate DWIDTH_LT_ADWIDTH_GEN;
-----------------------------------------------------------------------------
-- NAME: AD_MUX_OUT_PROCESS
-----------------------------------------------------------------------------
-- Description: Multiplexes the address and data bus to be driven out to the
-- external peripheral device if the device uses multiplexed bus
-- for address and data
-----------------------------------------------------------------------------
AD_MUX_OUT_PROCESS: process (Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
if (addr_ph = '1') then
PRH_Data_O <= addr_out;
else
PRH_Data_O <= data_out;
end if;
end if;
end process AD_MUX_OUT_PROCESS;
end generate PRH_BUS_MULTIPLEX_GEN;
REG_PRH_SIGS48 : process(Local_Clk)
begin
if (Local_Clk'event and Local_Clk = '1')then
PRH_Addr <= Addr_Int;
end if;
end process REG_PRH_SIGS48;
-------------------------------------------------------------------------------
-- NAME: DEV_RDY_PROCESS
-------------------------------------------------------------------------------
-- Description: Multiplexes the device ready signal from external peripheral
-- devices and drives to the internal logic
-------------------------------------------------------------------------------
DEV_RDY_PROCESS: process (Dev_id,PRH_Rdy) is
begin
Dev_Rdy <= '0';
for i in 0 to C_NUM_PERIPHERALS-1 loop
if (Dev_id(i) = '1') then
Dev_Rdy <= PRH_Rdy(i);
end if;
end loop;
end process DEV_RDY_PROCESS;
end architecture imp;
--------------------------------end of file------------------------------------
| gpl-3.0 | 7d8c7d7ca320ae0f4c8054b8b00725c4 | 0.431093 | 4.488519 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/Interrupts.vhd | 1 | 18,218 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Interrupts is
port (
-- System Interrupt register from Registers module
Sys_IRQ : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt generator signals
IG_Reset : IN std_logic;
IG_Host_Clear : IN std_logic;
IG_Latency : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : OUT std_logic;
-- Interrupt Interface
cfg_interrupt_n : OUT std_logic;
cfg_interrupt_rdy_n : IN std_logic;
cfg_interrupt_mmenable : IN std_logic_VECTOR(2 downto 0);
cfg_interrupt_msienable : IN std_logic;
cfg_interrupt_di : OUT std_logic_VECTOR(7 downto 0);
cfg_interrupt_do : IN std_logic_VECTOR(7 downto 0);
cfg_interrupt_assert_n : OUT std_logic;
-- Irpt Channel
Irpt_Req : OUT std_logic;
Irpt_RE : IN std_logic;
Irpt_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
IrptStatesOut : OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed : OUT std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
-- Clock and reset
trn_clk : IN std_logic;
trn_reset_n : IN std_logic
);
end Interrupts;
architecture Behavioral of Interrupts is
-- State machine: Interrupt control
type IrptStates is ( IntST_RST
, IntST_Idle
, IntST_Asserting
, IntST_Asserted
, IntST_Deasserting
);
signal edge_Intrpt_State : IrptStates;
signal level_Intrpt_State : IrptStates;
signal cfg_interrupt_n_i : std_logic;
signal cfg_interrupt_rdy_n_i : std_logic;
signal cfg_interrupt_di_i : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert_n_i : std_logic;
signal edge_Irpt_Req_i : std_logic;
signal level_Irpt_Req_i : std_logic;
signal Irpt_RE_i : std_logic;
signal Irpt_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0)
:= (OTHERS=>'0');
signal Msg_Tag_Lo : std_logic_vector( 3 downto 0);
signal Msg_Code : std_logic_vector( 7 downto 0);
signal edge_MsgCode_is_ASSERT : std_logic;
signal level_MsgCode_is_ASSERT : std_logic;
signal IrptStatesOut_i : std_logic_vector(7 downto 0);
signal Interrupts_ORed_i : std_logic;
-- Interrupt Generator
signal IG_Trigger_i : std_logic;
-- Interrupt Generator Counter
signal IG_Counter : std_logic_vector(C_CNT_GINT_WIDTH-1 downto 0);
signal IG_Run : std_logic;
signal IG_Run_DAQ : std_logic;
-- Interrupt Generator Statistic: Assert number
signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Deassert number
signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator indicator
signal IG_Asserting_i : std_logic;
-- signal DAQ_irq_i : std_logic;
-- signal CTL_irq_i : std_logic;
-- signal DLM_irq_i : std_logic;
begin
-- Interrupt interface
-- cfg_interrupt_n should be explicitly clarified!
cfg_interrupt_assert_n <= cfg_interrupt_assert_n_i;
cfg_interrupt_rdy_n_i <= cfg_interrupt_rdy_n;
-- Only Legacy IntA for the moment ...
cfg_interrupt_di <= cfg_interrupt_di_i;
cfg_interrupt_di_i <= (Others=>'0');
-- Channel mode interface.
Irpt_RE_i <= Irpt_RE;
Irpt_Qout <= Irpt_Qout_i;
Interrupts_ORed <= Interrupts_ORed_i;
IrptStatesOut <= IrptStatesOut_i;
-- DAQ_irq_i <= DAQ_irq;
-- CTL_irq_i <= CTL_irq;
-- DLM_irq_i <= DLM_irq;
-- ---------------------------------------------------
-- emulates a channel buffer output
-- Note: Type not shows in this buffer
--
-- 127 ~ 97 : reserved
-- 96 : reserved
-- 95 : reserved
-- 94 : Valid
-- 93 ~ 35 : reserved
-- 34 ~ 27 : Msg code
-- 26 ~ 19 : Tag
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
Irpt_Qout_i(C_CHBUF_QVALID_BIT) <= '1';
Irpt_Qout_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= C_MSG_TAG_HI & Msg_Tag_Lo;
Irpt_Qout_i(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT) <= Msg_Code;
Irpt_Qout_i(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT4_NO_DATA;
Irpt_Qout_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
IG_Run_DAQ <= IG_Run AND (DLM_irq OR DLMTOUT_irq);--Sys_IRQ(8)
-- ---------------------------------------------------------------
-- All Interrups are OR'ed
--
Syn_Interrupts_ORed:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
if Sys_IRQ(C_NUM_OF_INTERRUPTS-1 downto 0)
= C_ALL_ZEROS(C_NUM_OF_INTERRUPTS-1 downto 0)
then
Interrupts_ORed_i <= '0';
else
Interrupts_ORed_i <= '1';
end if;
end if;
end process;
-------------------------------------------
---- Cfg Interface mode
-------------------------------------------
Gen_Cfg_Irpt: if USE_CFG_INTERRUPT generate
cfg_interrupt_n <= cfg_interrupt_n_i;
--Irpt_Req <= '0'; -- Cfg interface mode, channel disabled.
Irpt_Req <= level_Irpt_Req_i;
Msg_Code <= (Others=>'0');
States_Machine_Irpt:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
edge_Intrpt_State <= IntST_RST;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000000";
elsif trn_clk'event and trn_clk = '1' then
case edge_Intrpt_State is
when IntST_RST =>----0
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000001";
when IntST_Idle =>----1
if Interrupts_ORed_i='1' then
edge_Intrpt_State <= IntST_Asserting;
cfg_interrupt_n_i <= '0';
cfg_interrupt_assert_n_i <= '0';
level_Irpt_Req_i <= '1';
IrptStatesOut_i <= "00000010";
else
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000001";
end if;
when IntST_Asserting =>----2
if cfg_interrupt_rdy_n='1' then
edge_Intrpt_State <= IntST_Asserting;
cfg_interrupt_n_i <= '0';
cfg_interrupt_assert_n_i <= '0';
level_Irpt_Req_i <= '1';
IrptStatesOut_i <= "00000010";
else
edge_Intrpt_State <= IntST_Asserted;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '0';
level_Irpt_Req_i <= '1';
IrptStatesOut_i <= "00000011";
end if;
when IntST_Asserted =>----3
if Interrupts_ORed_i='0' then
edge_Intrpt_State <= IntST_Deasserting;
cfg_interrupt_n_i <= '0';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000100";
else
edge_Intrpt_State <= IntST_Asserted;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '0';
level_Irpt_Req_i <= '1';
IrptStatesOut_i <= "00000011";
end if;
when IntST_Deasserting =>----4
if Irpt_RE_i='0' then
edge_Intrpt_State <= IntST_Deasserting;
cfg_interrupt_n_i <= '0';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000100";
else
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000001";
end if;
when OTHERS =>
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_n_i <= '1';
cfg_interrupt_assert_n_i <= '1';
level_Irpt_Req_i <= '0';
IrptStatesOut_i <= "00000001";
end case;
end if;
end process;
end generate;
----------------------------------------------
-- Channel mode
----------------------------------------------
Gen_Chan_MSI: if not USE_CFG_INTERRUPT generate
cfg_interrupt_n <= '1'; -- Channel mode, cfg interface disabled.
cfg_interrupt_assert_n_i <= '1';
Irpt_Req <= edge_Irpt_Req_i;
Msg_Code <= C_MSGCODE_INTA when edge_MsgCode_is_ASSERT='1'
else C_MSGCODE_INTA_N;
-- State Machine for edge interrupts
State_Machine_edge_Irpt:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
edge_Intrpt_State <= IntST_RST;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
IrptStatesOut_i <= "00000000";
elsif trn_clk'event and trn_clk = '1' then
case edge_Intrpt_State is
when IntST_RST =>
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
IrptStatesOut_i <= "00000001";
when IntST_Idle =>
if Interrupts_ORed_i='1' then
edge_Intrpt_State <= IntST_Asserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
IrptStatesOut_i <= "00000010";
else
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;
IrptStatesOut_i <= "00000001";
end if;
when IntST_Asserting =>
if Irpt_RE_i='0' then
edge_Intrpt_State <= IntST_Asserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
IrptStatesOut_i <= "00000010";
else
edge_Intrpt_State <= IntST_Asserted;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '1';
IrptStatesOut_i <= "00000011";
end if;
when IntST_Asserted =>
if Interrupts_ORed_i='0' then
edge_Intrpt_State <= IntST_Deasserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- !!
IrptStatesOut_i <= "00000100";
else
edge_Intrpt_State <= IntST_Asserted;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
IrptStatesOut_i <= "00000011";
end if;
when IntST_Deasserting =>
if Irpt_RE_i='0' then
edge_Intrpt_State <= IntST_Deasserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '0';
IrptStatesOut_i <= "00000100";
else
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
IrptStatesOut_i <= "00000001";
end if;
when OTHERS =>
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
IrptStatesOut_i <= "00000001";
end case;
end if;
end process;
-- Tag of Msg TLP increments
Sync_Msg_Tag_Increment:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
Msg_Tag_Lo <= (Others=>'0');
elsif trn_clk'event and trn_clk = '1' then
if Irpt_RE_i = '1' then
Msg_Tag_Lo <= Msg_Tag_Lo + '1';
else
Msg_Tag_Lo <= Msg_Tag_Lo;
end if;
end if;
end process;
end generate; -- Gen_Chan_MSI: if not USE_CFG_INTERRUPT
--
-------------- Generate Interrupt Generator ------------------
--
Gen_IG: if IMP_INT_GENERATOR generate
IG_Num_Assert <= IG_Num_Assert_i;
IG_Num_Deassert <= IG_Num_Deassert_i;
IG_Asserting <= IG_Asserting_i;
-- -------------------------------------------------------
-- FSM: generating interrupts
FSM_Generate_Interrupts:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
IG_Counter <= (Others=>'0');
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset = '1' then
IG_Counter <= (Others=>'0');
elsif IG_Counter /= C_ALL_ZEROS(C_CNT_GINT_WIDTH-1 downto 0) then
IG_Counter <= IG_Counter - '1';
elsif IG_Run_DAQ = '0' then
IG_Counter <= (Others=>'0');
else
IG_Counter <= IG_Latency(C_CNT_GINT_WIDTH-1 downto 0);
end if;
end if;
end process;
-- -------------------------------------------------------
-- Issuing: Interrupt trigger
Synch_Interrupt_Trigger:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
IG_Trigger_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset = '1' then
IG_Trigger_i <= '0';
elsif IG_Counter = CONV_STD_LOGIC_VECTOR(1, C_CNT_GINT_WIDTH) then
IG_Trigger_i <= '1';
else
IG_Trigger_i <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------
-- register: IG_Run
Synch_IG_Run:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
IG_Run <= '0';
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset = '1' then
IG_Run <= '0';
elsif IG_Latency(C_DBUS_WIDTH-1 downto 2)=C_ALL_ZEROS(C_DBUS_WIDTH-1 downto 2) then
IG_Run <= '0';
else
IG_Run <= '1';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Register: IG_Num_Assert_i
SysReg_IntGen_Number_of_Assert:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
IG_Num_Assert_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset='1' then
IG_Num_Assert_i <= (OTHERS => '0');
elsif IG_Trigger_i = '1' then
IG_Num_Assert_i <= IG_Num_Assert_i + '1';
else
IG_Num_Assert_i <= IG_Num_Assert_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Register: IG_Num_Deassert_i
SysReg_IntGen_Number_of_Deassert:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
IG_Num_Deassert_i <= (OTHERS => '0');
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset='1' then
IG_Num_Deassert_i <= (OTHERS => '0');
elsif IG_Host_Clear='1' and IG_Asserting_i='1' then
IG_Num_Deassert_i <= IG_Num_Deassert_i + '1';
else
IG_Num_Deassert_i <= IG_Num_Deassert_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Register: IG_Asserting_i
SysReg_IntGen_IG_Asserting_i:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
IG_Asserting_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
if IG_Reset='1' then
IG_Asserting_i <= '0';
elsif IG_Asserting_i='0' and IG_Trigger_i='1' then
IG_Asserting_i <= '1';
elsif IG_Asserting_i='0' and IG_Trigger_i='0' then
IG_Asserting_i <= '0';
elsif IG_Asserting_i='1' and IG_Host_Clear='0' then
IG_Asserting_i <= '1';
elsif IG_Asserting_i='1' and IG_Host_Clear='1' then
IG_Asserting_i <= '0';
else
IG_Asserting_i <= IG_Asserting_i;
end if;
end if;
end process;
end generate;
--
-------------- No Generation of Interrupt Generator ----------------
--
NotGen_IG: if not IMP_INT_GENERATOR generate
IG_Num_Assert <= (OTHERS=>'0');
IG_Num_Deassert <= (OTHERS=>'0');
IG_Asserting <= '0';
end generate;
end Behavioral;
| gpl-2.0 | a9c31c0bfcf54109f76f079cbc2ceb70 | 0.484411 | 3.608239 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/rx_Transact.vhd | 1 | 52,461 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_Transact is
port (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rdst_rdy_n : OUT std_logic;
trn_rnp_ok_n : OUT std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
-- PIO MRd Channel
pioCplD_Req : OUT std_logic;
pioCplD_RE : IN std_logic;
pioCplD_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
pio_FC_stop : IN std_logic;
-- downstream MRd Channel
dsMRd_Req : OUT std_logic;
dsMRd_RE : IN std_logic;
dsMRd_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- upstream MWr/MRd Channel
usTlp_Req : OUT std_logic;
usTlp_RE : IN std_logic;
usTlp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
us_FC_stop : IN std_logic;
us_Last_sof : IN std_logic;
us_Last_eof : IN std_logic;
-- Irpt Channel
Irpt_Req : OUT std_logic;
Irpt_RE : IN std_logic;
Irpt_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
IrptStatesOut : OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed : OUT std_logic;
-- Interrupt Interface
cfg_interrupt_n : OUT std_logic;
cfg_interrupt_rdy_n : IN std_logic;
cfg_interrupt_mmenable : IN std_logic_VECTOR(2 downto 0);
cfg_interrupt_msienable : IN std_logic;
cfg_interrupt_di : OUT std_logic_VECTOR(7 downto 0);
cfg_interrupt_do : IN std_logic_VECTOR(7 downto 0);
cfg_interrupt_assert_n : OUT std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : OUT std_logic;
ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- --------------------------
-- Registers
DMA_ds_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : IN std_logic;
DMA_ds_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Done : OUT std_logic;
DMA_ds_Busy : OUT std_logic;
DMA_ds_Tout : OUT std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : IN std_logic;
dsBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : IN std_logic;
dsLeng_Lo7b_True : IN std_logic;
--
dsDMA_Start : IN std_logic;
dsDMA_Stop : IN std_logic;
dsDMA_Start2 : IN std_logic;
dsDMA_Stop2 : IN std_logic;
dsDMA_Channel_Rst : IN std_logic;
dsDMA_Cmd_Ack : OUT std_logic;
--
DMA_us_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : IN std_logic;
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
DMA_us_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Done : OUT std_logic;
DMA_us_Busy : OUT std_logic;
DMA_us_Tout : OUT std_logic;
-- Calculation in advance, for better timing
usHA_is_64b : IN std_logic;
usBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : IN std_logic;
usLeng_Lo7b_True : IN std_logic;
--
usDMA_Start : IN std_logic;
usDMA_Stop : IN std_logic;
usDMA_Start2 : IN std_logic;
usDMA_Stop2 : IN std_logic;
usDMA_Channel_Rst : IN std_logic;
usDMA_Cmd_Ack : OUT std_logic;
MRd_Channel_Rst : IN std_logic;
-- to Interrupt module
Sys_IRQ : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
eb_FIFO_data_count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
eb_FIFO_Empty : IN std_logic;
eb_FIFO_Reading : IN std_logic;
pio_reading_status : OUT std_logic;
Link_Buf_full : IN std_logic;
-- Registers Write Port
Regs_WrEn0 : OUT std_logic;
Regs_WrMask0 : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr0 : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin0 : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
Regs_WrEn1 : OUT std_logic;
Regs_WrMask1 : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr1 : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin1 : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof_A : OUT std_logic;
DDR_wr_eof_A : OUT std_logic;
DDR_wr_v_A : OUT std_logic;
DDR_wr_FA_A : OUT std_logic;
DDR_wr_Shift_A : OUT std_logic;
DDR_wr_Mask_A : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_A : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_sof_B : OUT std_logic;
DDR_wr_eof_B : OUT std_logic;
DDR_wr_v_B : OUT std_logic;
DDR_wr_FA_B : OUT std_logic;
DDR_wr_Shift_B : OUT std_logic;
DDR_wr_Mask_B : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din_B : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt generator signals
IG_Reset : IN std_logic;
IG_Host_Clear : IN std_logic;
IG_Latency : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : OUT std_logic;
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
end entity rx_Transact;
architecture Behavioral of rx_Transact is
signal eb_FIFO_we_i : std_logic;
signal eb_FIFO_wsof_i : std_logic;
signal eb_FIFO_weof_i : std_logic;
signal eb_FIFO_din_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
------------------------------------------------------------------
-- Rx input delay
-- some calculation in advance, to achieve better timing
--
COMPONENT
RxIn_Delay
PORT (
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic;
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
trn_rdst_rdy_n : OUT std_logic;
Pool_wrBuf_full : IN std_logic;
Link_Buf_full : IN std_logic;
-- Delayed
trn_rsof_n_dly : OUT std_logic;
trn_reof_n_dly : OUT std_logic;
trn_rd_dly : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n_dly : OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n_dly : OUT std_logic;
trn_rsrc_rdy_n_dly : OUT std_logic;
trn_rdst_rdy_n_dly : OUT std_logic;
trn_rsrc_dsc_n_dly : OUT std_logic;
trn_rbar_hit_n_dly : OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
IORd_Type : OUT std_logic;
IOWr_Type : OUT std_logic;
MRd_Type : OUT std_logic_vector(3 downto 0);
MWr_Type : OUT std_logic_vector(1 downto 0);
CplD_Type : OUT std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
dsDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB : OUT std_logic;
-- To Cpl/D channel
Tlp_has_4KB : OUT std_logic;
Tlp_has_1DW : OUT std_logic;
CplD_is_the_Last : OUT std_logic;
CplD_on_Pool : OUT std_logic;
CplD_on_EB : OUT std_logic;
Req_ID_Match : OUT std_logic;
usDex_Tag_Matched : OUT std_logic;
dsDex_Tag_Matched : OUT std_logic;
CplD_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
localID : IN std_logic_vector(C_ID_WIDTH-1 downto 0)
);
END COMPONENT;
-- One clock delayed
signal trn_rsof_n_dly : std_logic;
signal trn_reof_n_dly : std_logic;
signal trn_rd_dly : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rrem_n_dly : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rerrfwd_n_dly : std_logic;
signal trn_rsrc_rdy_n_dly : std_logic;
signal trn_rdst_rdy_n_dly : std_logic;
signal trn_rsrc_dsc_n_dly : std_logic;
signal trn_rbar_hit_n_dly : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP types
signal IORd_Type : std_logic;
signal IOWr_Type : std_logic;
signal MRd_Type : std_logic_vector(3 downto 0);
signal MWr_Type : std_logic_vector(1 downto 0);
signal CplD_Type : std_logic_vector(3 downto 0);
signal Tlp_straddles_4KB : std_logic;
-- To Cpl/D channel
signal Tlp_has_4KB : std_logic;
signal Tlp_has_1DW : std_logic;
signal CplD_is_the_Last : std_logic;
signal CplD_on_Pool : std_logic;
signal CplD_on_EB : std_logic;
signal Req_ID_Match : std_logic;
signal usDex_Tag_Matched : std_logic;
signal dsDex_Tag_Matched : std_logic;
signal CplD_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
------------------------------------------------------------------
-- MRd TLP processing
-- contains channel buffer for PIO Completions
--
COMPONENT
rx_MRd_Transact
PORT(
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
-- trn_rdst_rdy_n : OUT std_logic;
trn_rnp_ok_n : OUT std_logic; -----------------
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
IORd_Type : IN std_logic;
MRd_Type : IN std_logic_vector(3 downto 0);
Tlp_straddles_4KB : IN std_logic;
pioCplD_RE : IN std_logic;
pioCplD_Req : OUT std_logic;
pioCplD_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
FIFO_Empty : IN std_logic;
FIFO_Reading : IN std_logic;
pio_FC_stop : IN std_logic;
pio_reading_status : OUT std_logic;
Channel_Rst : IN std_logic;
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
END COMPONENT;
------------------------------------------------------------------
-- MWr TLP processing
--
COMPONENT
rx_MWr_Transact
PORT(
--
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rdst_rdy_n : IN std_logic; -- !!
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
IOWr_Type : IN std_logic;
MWr_Type : IN std_logic_vector(1 downto 0);
Tlp_straddles_4KB : IN std_logic;
Tlp_has_4KB : IN std_logic;
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : OUT std_logic;
Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
-- Data generator table write
tab_we : OUT std_logic_vector(2-1 downto 0);
tab_wa : OUT std_logic_vector(12-1 downto 0);
tab_wd : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
END COMPONENT;
signal eb_FIFO_we_MWr : std_logic;
signal eb_FIFO_wsof_MWr : std_logic;
signal eb_FIFO_weof_MWr : std_logic;
signal eb_FIFO_din_MWr : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
------------------------------------------------------------------
-- Cpl/D TLP processing
--
COMPONENT
rx_CplD_Transact
PORT(
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rdst_rdy_n : IN std_logic;
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
CplD_Type : IN std_logic_vector(3 downto 0);
Req_ID_Match : IN std_logic;
usDex_Tag_Matched : IN std_logic;
dsDex_Tag_Matched : IN std_logic;
Tlp_has_4KB : IN std_logic;
Tlp_has_1DW : IN std_logic;
CplD_is_the_Last : IN std_logic;
CplD_on_Pool : IN std_logic;
CplD_on_EB : IN std_logic;
CplD_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
FC_pop : OUT std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add : OUT std_logic;
ds_DMA_Bytes : OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- for descriptor of the downstream DMA
dsDMA_Dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Downstream Handshake Signals with ds Channel for Busy/Done
Tag_Map_Clear : OUT std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
-- Downstream tRAM port A write request
tRAM_weB : IN std_logic;
tRAM_addrB : IN std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : IN std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- for descriptor of the upstream DMA
usDMA_dex_Tag : OUT std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Event Buffer write port
eb_FIFO_we : OUT std_logic;
eb_FIFO_wsof : OUT std_logic;
eb_FIFO_weof : OUT std_logic;
eb_FIFO_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Registers Write Port
Regs_WrEn : OUT std_logic;
Regs_WrMask : OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr : OUT std_logic_vector(C_EP_AWIDTH-1 downto 0);
Regs_WrDin : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR write port
DDR_wr_sof : OUT std_logic;
DDR_wr_eof : OUT std_logic;
DDR_wr_v : OUT std_logic;
DDR_wr_FA : OUT std_logic;
DDR_wr_Shift : OUT std_logic;
DDR_wr_Mask : OUT std_logic_vector(2-1 downto 0);
DDR_wr_din : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : IN std_logic;
-- Common signals
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
END COMPONENT;
signal eb_FIFO_we_CplD : std_logic;
signal eb_FIFO_wsof_CplD : std_logic;
signal eb_FIFO_weof_CplD : std_logic;
signal eb_FIFO_din_CplD : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal usDMA_dex_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal dsDMA_dex_Tag : std_logic_vector(C_TAG_WIDTH-1 downto 0);
signal Tag_Map_Clear : std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
signal FC_pop : std_logic;
------------------------------------------------------------------
-- Interrupts generation
--
COMPONENT
Interrupts
PORT(
Sys_IRQ : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt generator signals
IG_Reset : IN std_logic;
IG_Host_Clear : IN std_logic;
IG_Latency : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : OUT std_logic;
-- cfg interface
cfg_interrupt_n : OUT std_logic;
cfg_interrupt_rdy_n : IN std_logic;
cfg_interrupt_mmenable : IN std_logic_vector(2 downto 0);
cfg_interrupt_msienable : IN std_logic;
cfg_interrupt_di : OUT std_logic_vector(7 downto 0);
cfg_interrupt_do : IN std_logic_vector(7 downto 0);
cfg_interrupt_assert_n : OUT std_logic;
-- Irpt Channel
Irpt_Req : OUT std_logic;
Irpt_RE : IN std_logic;
Irpt_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
IrptStatesOut : OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed : OUT std_logic;
DAQ_irq : IN std_logic;
CTL_irq : IN std_logic;
DLM_irq : IN std_logic;
DAQTOUT_irq : IN std_logic;
CTLTOUT_irq : IN std_logic;
DLMTOUT_irq : IN std_logic;
trn_clk : IN std_logic;
trn_reset_n : IN std_logic
);
END COMPONENT;
------------------------------------------------------------------
-- Upstream DMA Channel
-- contains channel buffer for upstream DMA
--
COMPONENT
usDMA_Transact
PORT(
-- command buffer
usTlp_Req : OUT std_logic;
usTlp_RE : IN std_logic;
usTlp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
FIFO_Data_Count : IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
FIFO_Reading : IN std_logic;
-- Upstream DMA Control Signals from MWr Channel
usDMA_Start : IN std_logic;
usDMA_Stop : IN std_logic;
usDMA_Channel_Rst : IN std_logic;
us_FC_stop : IN std_logic;
us_Last_sof : IN std_logic;
us_Last_eof : IN std_logic;
--- Upstream registers from CplD channel
DMA_us_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_us_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
usDMA_BDA_eq_Null : IN std_logic;
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
-- Calculation in advance, for better timing
usHA_is_64b : IN std_logic;
usBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
usLeng_Hi19b_True : IN std_logic;
usLeng_Lo7b_True : IN std_logic;
--- Upstream commands from CplD channel
usDMA_Start2 : IN std_logic;
usDMA_Stop2 : IN std_logic;
-- DMA Acknowledge to the start command
DMA_Cmd_Ack : OUT std_logic;
--- Tag for descriptor
usDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
-- To Tx channel
DMA_us_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- common
trn_clk : IN std_logic
);
END COMPONENT;
------------------------------------------------------------------
-- Downstream DMA Channel
-- contains channel buffer for downstream DMA
--
COMPONENT
dsDMA_Transact
PORT(
-- command buffer
MRd_dsp_RE : IN std_logic;
MRd_dsp_Req : OUT std_logic;
MRd_dsp_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Downstream tRAM port A write request, to CplD channel
tRAM_weB : OUT std_logic;
tRAM_addrB : OUT std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
tRAM_dinB : OUT std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
-- Downstream Registers from MWr Channel
DMA_ds_PA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_HA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_BDA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Length : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_ds_Control : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
dsDMA_BDA_eq_Null : IN std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b : IN std_logic;
dsBDA_is_64b : IN std_logic;
-- Calculation in advance, for better timing
dsLeng_Hi19b_True : IN std_logic;
dsLeng_Lo7b_True : IN std_logic;
-- Downstream Control Signals from MWr Channel
dsDMA_Start : IN std_logic;
dsDMA_Stop : IN std_logic;
-- DMA Acknowledge to the start command
DMA_Cmd_Ack : OUT std_logic;
dsDMA_Channel_Rst : IN std_logic;
-- Downstream Control Signals from CplD Channel, out of consecutive dex
dsDMA_Start2 : IN std_logic;
dsDMA_Stop2 : IN std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear : IN std_logic_vector(C_TAG_MAP_WIDTH-1 downto 0);
FC_pop : IN std_logic;
-- Tag for descriptor
dsDMA_dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- To Interrupt module
DMA_Done : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
-- To Cpl/D channel
DMA_ds_Status : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Additional
cfg_dcommand : IN std_logic_vector(C_CFG_COMMAND_DWIDTH-1 downto 0);
-- common
trn_clk : IN std_logic
);
END COMPONENT;
-- tag RAM port A write request
signal tRAM_weB : std_logic;
signal tRAM_addrB : std_logic_vector(C_TAGRAM_AWIDTH-1 downto 0);
signal tRAM_dinB : std_logic_vector(C_TAGRAM_DWIDTH-1 downto 0);
begin
eb_FIFO_we <= eb_FIFO_we_i ;
eb_FIFO_wsof <= eb_FIFO_wsof_i ;
eb_FIFO_weof <= eb_FIFO_weof_i ;
eb_FIFO_din <= eb_FIFO_din_i ;
eb_FIFO_we_i <= eb_FIFO_we_MWr or eb_FIFO_we_CplD;
eb_FIFO_wsof_i <= eb_FIFO_wsof_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_wsof_MWr;
eb_FIFO_weof_i <= eb_FIFO_weof_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_weof_MWr;
eb_FIFO_din_i <= eb_FIFO_din_CplD when eb_FIFO_we_CplD='1' else eb_FIFO_din_MWr;
-- ------------------------------------------------
-- Delay of Rx inputs
-- ------------------------------------------------
Rx_Input_Delays:
RxIn_Delay
PORT MAP(
-- Common ports
trn_clk => trn_clk , -- IN std_logic;
trn_reset_n => trn_reset_n , -- IN std_logic;
trn_lnk_up_n => trn_lnk_up_n , -- IN std_logic;
-- Transaction receive interface
trn_rsof_n => trn_rsof_n , -- IN std_logic;
trn_reof_n => trn_reof_n , -- IN std_logic;
trn_rd => trn_rd , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n => trn_rrem_n , -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n => trn_rerrfwd_n , -- IN std_logic;
trn_rsrc_rdy_n => trn_rsrc_rdy_n , -- IN std_logic;
trn_rsrc_dsc_n => trn_rsrc_dsc_n , -- IN std_logic;
trn_rbar_hit_n => trn_rbar_hit_n , -- IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
trn_rdst_rdy_n => trn_rdst_rdy_n , -- OUT std_logic;
Pool_wrBuf_full => DDR_wr_full , -- IN std_logic;
Link_Buf_full => Link_Buf_full , -- IN std_logic;
-- Delayed
trn_rsof_n_dly => trn_rsof_n_dly , -- OUT std_logic;
trn_reof_n_dly => trn_reof_n_dly , -- OUT std_logic;
trn_rd_dly => trn_rd_dly , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n_dly => trn_rrem_n_dly , -- OUT std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n_dly => trn_rerrfwd_n_dly , -- OUT std_logic;
trn_rsrc_rdy_n_dly => trn_rsrc_rdy_n_dly, -- OUT std_logic;
trn_rdst_rdy_n_dly => trn_rdst_rdy_n_dly, -- OUT std_logic;
trn_rsrc_dsc_n_dly => trn_rsrc_dsc_n_dly, -- OUT std_logic;
trn_rbar_hit_n_dly => trn_rbar_hit_n_dly, -- OUT std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- TLP resolution
IORd_Type => IORd_Type , -- OUT std_logic;
IOWr_Type => IOWr_Type , -- OUT std_logic;
MRd_Type => MRd_Type , -- OUT std_logic_vector(3 downto 0);
MWr_Type => MWr_Type , -- OUT std_logic_vector(1 downto 0);
CplD_Type => CplD_Type , -- OUT std_logic_vector(3 downto 0);
-- From Cpl/D channel
usDMA_dex_Tag => usDMA_dex_Tag , -- IN std_logic_vector(7 downto 0);
dsDMA_dex_Tag => dsDMA_dex_Tag , -- IN std_logic_vector(7 downto 0);
-- To Memory request process modules
Tlp_straddles_4KB => Tlp_straddles_4KB , -- OUT std_logic;
-- To Cpl/D channel
Tlp_has_4KB => Tlp_has_4KB , -- OUT std_logic;
Tlp_has_1DW => Tlp_has_1DW , -- OUT std_logic;
CplD_is_the_Last => CplD_is_the_Last , -- OUT std_logic;
CplD_on_Pool => CplD_on_Pool , -- OUT std_logic;
CplD_on_EB => CplD_on_EB , -- OUT std_logic;
Req_ID_Match => Req_ID_Match , -- OUT std_logic;
usDex_Tag_Matched => usDex_Tag_Matched , -- OUT std_logic;
dsDex_Tag_Matched => dsDex_Tag_Matched , -- OUT std_logic;
CplD_Tag => CplD_Tag , -- OUT std_logic_vector(7 downto 0);
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(16-1 downto 0)
localID => localID -- IN std_logic_vector(15 downto 0)
);
-- ------------------------------------------------
-- Processing MRd Requests
-- ------------------------------------------------
MRd_Channel:
rx_MRd_Transact
PORT MAP(
--
trn_rsof_n => trn_rsof_n_dly, -- IN std_logic;
trn_reof_n => trn_reof_n_dly, -- IN std_logic;
trn_rd => trn_rd_dly, -- IN std_logic_vector(31 downto 0);
trn_rrem_n => trn_rrem_n_dly, -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n => trn_rerrfwd_n_dly, -- IN std_logic;
trn_rsrc_rdy_n => trn_rsrc_rdy_n_dly, -- IN std_logic;
trn_rsrc_dsc_n => trn_rsrc_dsc_n_dly, -- IN std_logic;
trn_rbar_hit_n => trn_rbar_hit_n_dly, -- IN std_logic_vector(6 downto 0);
-- trn_rdst_rdy_n => open, -- trn_rdst_rdy_n_MRd, -- OUT std_logic;
trn_rnp_ok_n => trn_rnp_ok_n, -- OUT std_logic;
IORd_Type => IORd_Type , -- IN std_logic;
MRd_Type => MRd_Type , -- IN std_logic_vector(3 downto 0);
Tlp_straddles_4KB => Tlp_straddles_4KB , -- IN std_logic;
pioCplD_RE => pioCplD_RE, -- IN std_logic;
pioCplD_Req => pioCplD_Req, -- OUT std_logic;
pioCplD_Qout => pioCplD_Qout, -- OUT std_logic_vector(127 downto 0);
pio_FC_stop => pio_FC_stop, -- IN std_logic;
FIFO_Empty => eb_FIFO_Empty, -- IN std_logic;
FIFO_Reading => eb_FIFO_Reading, -- IN std_logic;
pio_reading_status => pio_reading_status, -- OUT std_logic;
Channel_Rst => MRd_Channel_Rst, -- IN std_logic;
trn_clk => trn_clk, -- IN std_logic;
trn_reset_n => trn_reset_n, -- IN std_logic;
trn_lnk_up_n => trn_lnk_up_n -- IN std_logic;
);
-- ------------------------------------------------
-- Processing MWr Requests
-- ------------------------------------------------
MWr_Channel:
rx_MWr_Transact
PORT MAP(
--
trn_rsof_n => trn_rsof_n_dly, -- IN std_logic;
trn_reof_n => trn_reof_n_dly, -- IN std_logic;
trn_rd => trn_rd_dly, -- IN std_logic_vector(31 downto 0);
trn_rrem_n => trn_rrem_n_dly, -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n => trn_rerrfwd_n_dly , -- IN std_logic;
trn_rsrc_rdy_n => trn_rsrc_rdy_n_dly, -- IN std_logic;
trn_rdst_rdy_n => trn_rdst_rdy_n_dly, -- IN std_logic;
trn_rsrc_dsc_n => trn_rsrc_dsc_n_dly, -- IN std_logic;
trn_rbar_hit_n => trn_rbar_hit_n_dly, -- IN std_logic_vector(6 downto 0);
IOWr_Type => IOWr_Type , -- OUT std_logic;
MWr_Type => MWr_Type , -- IN std_logic_vector(1 downto 0);
Tlp_straddles_4KB => Tlp_straddles_4KB , -- IN std_logic;
Tlp_has_4KB => Tlp_has_4KB , -- IN std_logic;
-- Event Buffer write port
eb_FIFO_we => eb_FIFO_we_MWr , -- OUT std_logic;
eb_FIFO_wsof => eb_FIFO_wsof_MWr , -- OUT std_logic;
eb_FIFO_weof => eb_FIFO_weof_MWr , -- OUT std_logic;
eb_FIFO_din => eb_FIFO_din_MWr , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- To registers module
Regs_WrEn => Regs_WrEn0 , -- OUT std_logic;
Regs_WrMask => Regs_WrMask0 , -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr => Regs_WrAddr0 , -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin => Regs_WrDin0 , -- OUT std_logic_vector(32-1 downto 0);
-- DDR write port
DDR_wr_sof => DDR_wr_sof_A , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof_A , -- OUT std_logic;
DDR_wr_v => DDR_wr_v_A , -- OUT std_logic;
DDR_wr_FA => DDR_wr_FA_A , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift_A , -- OUT std_logic;
DDR_wr_din => DDR_wr_din_A , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_Mask => DDR_wr_Mask_A , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
-- Data generator table write
tab_we => tab_we , -- OUT std_logic_vector(2-1 downto 0);
tab_wa => tab_wa , -- OUT std_logic_vector(12-1 downto 0);
tab_wd => tab_wd , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common
trn_clk => trn_clk , -- IN std_logic;
trn_reset_n => trn_reset_n , -- IN std_logic;
trn_lnk_up_n => trn_lnk_up_n -- IN std_logic;
);
-- ---------------------------------------------------
-- Processing Completions
-- ---------------------------------------------------
CplD_Channel:
rx_CplD_Transact
PORT MAP(
--
trn_rsof_n => trn_rsof_n_dly, -- IN std_logic;
trn_reof_n => trn_reof_n_dly, -- IN std_logic;
trn_rd => trn_rd_dly, -- IN std_logic_vector(31 downto 0);
trn_rrem_n => trn_rrem_n_dly, -- IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n => trn_rerrfwd_n_dly, -- IN std_logic;
trn_rsrc_rdy_n => trn_rsrc_rdy_n_dly, -- IN std_logic;
trn_rdst_rdy_n => trn_rdst_rdy_n_dly, -- IN std_logic;
trn_rsrc_dsc_n => trn_rsrc_dsc_n_dly, -- IN std_logic;
trn_rbar_hit_n => trn_rbar_hit_n_dly, -- IN std_logic_vector(6 downto 0);
CplD_Type => CplD_Type, -- IN std_logic_vector(3 downto 0);
Req_ID_Match => Req_ID_Match, -- IN std_logic;
usDex_Tag_Matched => usDex_Tag_Matched, -- IN std_logic;
dsDex_Tag_Matched => dsDex_Tag_Matched, -- IN std_logic;
Tlp_has_4KB => Tlp_has_4KB , -- IN std_logic;
Tlp_has_1DW => Tlp_has_1DW , -- IN std_logic;
CplD_is_the_Last => CplD_is_the_Last, -- IN std_logic;
CplD_on_Pool => CplD_on_Pool , -- IN std_logic;
CplD_on_EB => CplD_on_EB , -- IN std_logic;
CplD_Tag => CplD_Tag, -- IN std_logic_vector( 7 downto 0);
FC_pop => FC_pop, -- OUT std_logic;
-- Downstream DMA transferred bytes count up
ds_DMA_Bytes_Add => ds_DMA_Bytes_Add, -- OUT std_logic;
ds_DMA_Bytes => ds_DMA_Bytes , -- OUT std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+2 downto 0);
-- Downstream tRAM port A write request
tRAM_weB => tRAM_weB, -- IN std_logic;
tRAM_addrB => tRAM_addrB, -- IN std_logic_vector( 6 downto 0);
tRAM_dinB => tRAM_dinB, -- IN std_logic_vector(47 downto 0);
-- Downstream channel descriptor tag
dsDMA_dex_Tag => dsDMA_dex_Tag, -- OUT std_logic_vector( 7 downto 0);
-- Downstream Tag Map Signal for Busy/Done
Tag_Map_Clear => Tag_Map_Clear, -- OUT std_logic_vector(127 downto 0);
-- Upstream channel descriptor tag
usDMA_dex_Tag => usDMA_dex_Tag, -- OUT std_logic_vector( 7 downto 0);
-- Event Buffer write port
eb_FIFO_we => eb_FIFO_we_CplD , -- OUT std_logic;
eb_FIFO_wsof => eb_FIFO_wsof_CplD , -- OUT std_logic;
eb_FIFO_weof => eb_FIFO_weof_CplD , -- OUT std_logic;
eb_FIFO_din => eb_FIFO_din_CplD , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- To registers module
Regs_WrEn => Regs_WrEn1, -- OUT std_logic;
Regs_WrMask => Regs_WrMask1, -- OUT std_logic_vector(2-1 downto 0);
Regs_WrAddr => Regs_WrAddr1, -- OUT std_logic_vector(16-1 downto 0);
Regs_WrDin => Regs_WrDin1, -- OUT std_logic_vector(32-1 downto 0);
-- DDR write port
DDR_wr_sof => DDR_wr_sof_B , -- OUT std_logic;
DDR_wr_eof => DDR_wr_eof_B , -- OUT std_logic;
DDR_wr_v => DDR_wr_v_B , -- OUT std_logic;
DDR_wr_FA => DDR_wr_FA_B , -- OUT std_logic;
DDR_wr_Shift => DDR_wr_Shift_B , -- OUT std_logic;
DDR_wr_Mask => DDR_wr_Mask_B , -- OUT std_logic_vector(2-1 downto 0);
DDR_wr_din => DDR_wr_din_B , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full => DDR_wr_full , -- IN std_logic;
-- Common
trn_clk => trn_clk, -- IN std_logic;
trn_reset_n => trn_reset_n, -- IN std_logic;
trn_lnk_up_n => trn_lnk_up_n -- IN std_logic;
);
-- ------------------------------------------------
-- Processing upstream DMA Requests
-- ------------------------------------------------
Upstream_DMA_Engine:
usDMA_Transact
PORT MAP(
-- TLP buffer
usTlp_RE => usTlp_RE, -- IN std_logic;
usTlp_Req => usTlp_Req, -- OUT std_logic;
usTlp_Qout => usTlp_Qout, -- OUT std_logic_vector(127 downto 0)
FIFO_Data_Count => eb_FIFO_data_count, -- IN std_logic_vector(C_FIFO_DC_WIDTH downto 0);
FIFO_Reading => eb_FIFO_Reading, -- IN std_logic;
-- upstream Control Signals from MWr Channel
usDMA_Start => usDMA_Start, -- IN std_logic;
usDMA_Stop => usDMA_Stop, -- IN std_logic;
-- Upstream Control Signals from CplD Channel
usDMA_Start2 => usDMA_Start2, -- IN std_logic;
usDMA_Stop2 => usDMA_Stop2, -- IN std_logic;
DMA_Cmd_Ack => usDMA_Cmd_Ack, -- OUT std_logic;
usDMA_Channel_Rst => usDMA_Channel_Rst, -- IN std_logic;
us_FC_stop => us_FC_stop, -- IN std_logic;
us_Last_sof => us_Last_sof, -- IN std_logic;
us_Last_eof => us_Last_eof, -- IN std_logic;
-- To Interrupt module
DMA_Done => DMA_us_Done, -- OUT std_logic;
DMA_TimeOut => DMA_us_Tout, -- OUT std_logic;
DMA_Busy => DMA_us_Busy, -- OUT std_logic;
-- To Tx channel
DMA_us_Status => DMA_us_Status, -- OUT std_logic_vector(31 downto 0);
-- upstream Registers
DMA_us_PA => DMA_us_PA, -- IN std_logic_vector(63 downto 0);
DMA_us_HA => DMA_us_HA, -- IN std_logic_vector(63 downto 0);
DMA_us_BDA => DMA_us_BDA, -- IN std_logic_vector(63 downto 0);
DMA_us_Length => DMA_us_Length, -- IN std_logic_vector(31 downto 0);
DMA_us_Control => DMA_us_Control, -- IN std_logic_vector(31 downto 0);
usDMA_BDA_eq_Null => usDMA_BDA_eq_Null, -- IN std_logic;
us_MWr_Param_Vec => us_MWr_Param_Vec, -- IN std_logic_vector(5 downto 0);
-- Calculation in advance, for better timing
usHA_is_64b => usHA_is_64b , -- IN std_logic;
usBDA_is_64b => usBDA_is_64b , -- IN std_logic;
usLeng_Hi19b_True => usLeng_Hi19b_True , -- IN std_logic;
usLeng_Lo7b_True => usLeng_Lo7b_True , -- IN std_logic;
usDMA_dex_Tag => usDMA_dex_Tag , -- OUT std_logic_vector( 7 downto 0);
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(16-1 downto 0)
trn_clk => trn_clk -- IN std_logic;
);
-- ------------------------------------------------
-- Processing downstream DMA Requests
-- ------------------------------------------------
Downstream_DMA_Engine:
dsDMA_Transact
PORT MAP(
-- Downstream tRAM port A write request
tRAM_weB => tRAM_weB, -- OUT std_logic;
tRAM_addrB => tRAM_addrB, -- OUT std_logic_vector( 6 downto 0);
tRAM_dinB => tRAM_dinB, -- OUT std_logic_vector(47 downto 0);
-- TLP buffer
MRd_dsp_RE => dsMRd_RE, -- IN std_logic;
MRd_dsp_Req => dsMRd_Req, -- OUT std_logic;
MRd_dsp_Qout => dsMRd_Qout, -- OUT std_logic_vector(127 downto 0);
-- Downstream Registers
DMA_ds_PA => DMA_ds_PA, -- IN std_logic_vector(63 downto 0);
DMA_ds_HA => DMA_ds_HA, -- IN std_logic_vector(63 downto 0);
DMA_ds_BDA => DMA_ds_BDA, -- IN std_logic_vector(63 downto 0);
DMA_ds_Length => DMA_ds_Length, -- IN std_logic_vector(31 downto 0);
DMA_ds_Control => DMA_ds_Control, -- IN std_logic_vector(31 downto 0);
dsDMA_BDA_eq_Null => dsDMA_BDA_eq_Null, -- IN std_logic;
-- Calculation in advance, for better timing
dsHA_is_64b => dsHA_is_64b , -- IN std_logic;
dsBDA_is_64b => dsBDA_is_64b , -- IN std_logic;
dsLeng_Hi19b_True => dsLeng_Hi19b_True , -- IN std_logic;
dsLeng_Lo7b_True => dsLeng_Lo7b_True , -- IN std_logic;
-- Downstream Control Signals from MWr Channel
dsDMA_Start => dsDMA_Start, -- IN std_logic;
dsDMA_Stop => dsDMA_Stop, -- IN std_logic;
-- Downstream Control Signals from CplD Channel
dsDMA_Start2 => dsDMA_Start2, -- IN std_logic;
dsDMA_Stop2 => dsDMA_Stop2, -- IN std_logic;
DMA_Cmd_Ack => dsDMA_Cmd_Ack, -- OUT std_logic;
dsDMA_Channel_Rst => dsDMA_Channel_Rst, -- IN std_logic;
-- Downstream Handshake Signals with CplD Channel for Busy/Done
Tag_Map_Clear => Tag_Map_Clear, -- IN std_logic_vector(127 downto 0);
FC_pop => FC_pop, -- IN std_logic;
-- To Interrupt module
DMA_Done => DMA_ds_Done, -- OUT std_logic;
DMA_TimeOut => DMA_ds_Tout, -- OUT std_logic;
DMA_Busy => DMA_ds_Busy, -- OUT std_logic;
-- To Tx channel
DMA_ds_Status => DMA_ds_Status, -- OUT std_logic_vector(31 downto 0);
-- tag for descriptor
dsDMA_dex_Tag => dsDMA_dex_Tag, -- IN std_logic_vector( 7 downto 0);
-- Additional
cfg_dcommand => cfg_dcommand , -- IN std_logic_vector(16-1 downto 0)
-- common
trn_clk => trn_clk -- IN std_logic;
);
-- ------------------------------------------------
-- Interrupts generation
-- ------------------------------------------------
Intrpt_Handle:
Interrupts
PORT MAP(
Sys_IRQ => Sys_IRQ , -- IN std_logic_vector(31 downto 0);
-- Interrupt generator signals
IG_Reset => IG_Reset , -- IN std_logic;
IG_Host_Clear => IG_Host_Clear , -- IN std_logic;
IG_Latency => IG_Latency , -- IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert => IG_Num_Assert , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert => IG_Num_Deassert , -- OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting => IG_Asserting , -- OUT std_logic;
-- cfg interface
cfg_interrupt_n => cfg_interrupt_n , -- OUT std_logic;
cfg_interrupt_rdy_n => cfg_interrupt_rdy_n , -- IN std_logic;
cfg_interrupt_mmenable => cfg_interrupt_mmenable , -- IN std_logic_vector(2 downto 0);
cfg_interrupt_msienable => cfg_interrupt_msienable , -- IN std_logic;
cfg_interrupt_di => cfg_interrupt_di , -- OUT std_logic_vector(7 downto 0);
cfg_interrupt_do => cfg_interrupt_do , -- IN std_logic_vector(7 downto 0);
cfg_interrupt_assert_n => cfg_interrupt_assert_n , -- OUT std_logic;
-- Irpt Channel
Irpt_Req => Irpt_Req , -- OUT std_logic;
Irpt_RE => Irpt_RE , -- IN std_logic;
Irpt_Qout => Irpt_Qout , -- OUT std_logic_vector(127 downto 0);
IrptStatesOut => IrptStatesOut , -- OUT std_logic_VECTOR(7 downto 0);
Interrupts_ORed => Interrupts_ORed , -- OUT std_logic;
DAQ_irq => DAQ_irq , -- IN std_logic;
CTL_irq => CTL_irq , -- IN std_logic;
DLM_irq => DLM_irq , -- IN std_logic;
DAQTOUT_irq => DAQTOUT_irq , -- IN std_logic;
CTLTOUT_irq => CTLTOUT_irq , -- IN std_logic;
DLMTOUT_irq => DLMTOUT_irq , -- IN std_logic;
trn_clk => trn_clk , -- IN std_logic;
trn_reset_n => trn_reset_n -- IN std_logic
);
end architecture Behavioral;
| gpl-2.0 | 5dd4604670842a271896018912168f94 | 0.472313 | 3.449566 | false | false | false | false |
olgirard/openmsp430 | fpga/xilinx_avnet_lx9microbard/rtl/verilog/coregen/ram_16x1k_dp/simulation/ram_16x1k_dp_synth.vhd | 1 | 10,859 |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Synthesizable Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_dp_synth.vhd
--
-- Description:
-- Synthesizable Testbench
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY STD;
USE STD.TEXTIO.ALL;
--LIBRARY unisim;
--USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY ram_16x1k_dp_synth IS
PORT(
CLK_IN : IN STD_LOGIC;
CLKB_IN : IN STD_LOGIC;
RESET_IN : IN STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA
);
END ENTITY;
ARCHITECTURE ram_16x1k_dp_synth_ARCH OF ram_16x1k_dp_synth IS
COMPONENT ram_16x1k_dp_exdes
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA: STD_LOGIC := '0';
SIGNAL RSTA: STD_LOGIC := '0';
SIGNAL ENA: STD_LOGIC := '0';
SIGNAL ENA_R: STD_LOGIC := '0';
SIGNAL WEA: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEA_R: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRA_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_R: STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTA: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CLKB: STD_LOGIC := '0';
SIGNAL RSTB: STD_LOGIC := '0';
SIGNAL ENB: STD_LOGIC := '0';
SIGNAL ENB_R: STD_LOGIC := '0';
SIGNAL WEB: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL WEB_R: STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL ADDRB_R: STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_R: STD_LOGIC_VECTOR( 15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DOUTB: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL CHECKER_EN : STD_LOGIC:='0';
SIGNAL CHECKER_EN_R : STD_LOGIC:='0';
SIGNAL CHECK_DATA_TDP : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL CHECKER_ENB_R : STD_LOGIC := '0';
SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0');
SIGNAL clk_in_i: STD_LOGIC;
SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1';
SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1';
SIGNAL clkb_in_i: STD_LOGIC;
SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1';
SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1';
SIGNAL ITER_R0 : STD_LOGIC := '0';
SIGNAL ITER_R1 : STD_LOGIC := '0';
SIGNAL ITER_R2 : STD_LOGIC := '0';
SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- clk_buf: bufg
-- PORT map(
-- i => CLK_IN,
-- o => clk_in_i
-- );
clk_in_i <= CLK_IN;
CLKA <= clk_in_i;
-- clkb_buf: bufg
-- PORT map(
-- i => CLKB_IN,
-- o => clkb_in_i
-- );
clkb_in_i <= CLKB_IN;
CLKB <= clkb_in_i;
RSTA <= RESET_SYNC_R3 AFTER 50 ns;
PROCESS(clk_in_i)
BEGIN
IF(RISING_EDGE(clk_in_i)) THEN
RESET_SYNC_R1 <= RESET_IN;
RESET_SYNC_R2 <= RESET_SYNC_R1;
RESET_SYNC_R3 <= RESET_SYNC_R2;
END IF;
END PROCESS;
RSTB <= RESETB_SYNC_R3 AFTER 50 ns;
PROCESS(clkb_in_i)
BEGIN
IF(RISING_EDGE(clkb_in_i)) THEN
RESETB_SYNC_R1 <= RESET_IN;
RESETB_SYNC_R2 <= RESETB_SYNC_R1;
RESETB_SYNC_R3 <= RESETB_SYNC_R2;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ISSUE_FLAG_STATUS<= (OTHERS => '0');
ELSE
ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG;
END IF;
END IF;
END PROCESS;
STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS;
BMG_DATA_CHECKER_INST_A: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKA,
RST => RSTA,
EN => CHECKER_EN_R,
DATA_IN => DOUTA,
STATUS => ISSUE_FLAG(0)
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RSTA='1') THEN
CHECKER_EN_R <= '0';
ELSE
CHECKER_EN_R <= CHECK_DATA_TDP(0) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_DATA_CHECKER_INST_B: ENTITY work.CHECKER
GENERIC MAP (
WRITE_WIDTH => 16,
READ_WIDTH => 16 )
PORT MAP (
CLK => CLKB,
RST => RSTB,
EN => CHECKER_ENB_R,
DATA_IN => DOUTB,
STATUS => ISSUE_FLAG(1)
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(RSTB='1') THEN
CHECKER_ENB_R <= '0';
ELSE
CHECKER_ENB_R <= CHECK_DATA_TDP(1) AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN
PORT MAP(
CLKA => CLKA,
CLKB => CLKB,
TB_RST => RSTA,
ADDRA => ADDRA,
DINA => DINA,
ENA => ENA,
WEA => WEA,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
ENB => ENB,
CHECK_DATA => CHECK_DATA_TDP
);
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STATUS(8) <= '0';
iter_r2 <= '0';
iter_r1 <= '0';
iter_r0 <= '0';
ELSE
STATUS(8) <= iter_r2;
iter_r2 <= iter_r1;
iter_r1 <= iter_r0;
iter_r0 <= STIMULUS_FLOW(8);
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
STIMULUS_FLOW <= (OTHERS => '0');
ELSIF(WEA(0)='1') THEN
STIMULUS_FLOW <= STIMULUS_FLOW+1;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ENA_R <= '0' AFTER 50 ns;
WEA_R <= (OTHERS=>'0') AFTER 50 ns;
DINA_R <= (OTHERS=>'0') AFTER 50 ns;
ENB_R <= '0' AFTER 50 ns;
WEB_R <= (OTHERS=>'0') AFTER 50 ns;
DINB_R <= (OTHERS=>'0') AFTER 50 ns;
ELSE
ENA_R <= ENA AFTER 50 ns;
WEA_R <= WEA AFTER 50 ns;
DINA_R <= DINA AFTER 50 ns;
ENB_R <= ENB AFTER 50 ns;
WEB_R <= WEB AFTER 50 ns;
DINB_R <= DINB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(RESET_SYNC_R3='1') THEN
ADDRA_R <= (OTHERS=> '0') AFTER 50 ns;
ADDRB_R <= (OTHERS=> '0') AFTER 50 ns;
ELSE
ADDRA_R <= ADDRA AFTER 50 ns;
ADDRB_R <= ADDRB AFTER 50 ns;
END IF;
END IF;
END PROCESS;
BMG_PORT: ram_16x1k_dp_exdes PORT MAP (
--Port A
ENA => ENA_R,
WEA => WEA_R,
ADDRA => ADDRA_R,
DINA => DINA_R,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB_R,
WEB => WEB_R,
ADDRB => ADDRB_R,
DINB => DINB_R,
DOUTB => DOUTB,
CLKB => CLKB
);
END ARCHITECTURE;
| bsd-3-clause | 23d79da1840434dff5d23e014f6b3d10 | 0.550143 | 3.554501 | false | false | false | false |
vira-lytvyn/labsAndOthersNiceThings | HardwareAndSoftwareOfNeuralNetworks/KR2/Zavdannja_1/T_FF.vhd | 1 | 671 | library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF is
port( T: in std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end T_FF;
architecture Behavioral of T_FF is
signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='0') then
if Reset='1' then
temp <= '0' after 6ns;
elsif Clock_enable ='1' then
if T='0' then
temp <= temp after 10ns;
elsif T='1' then
temp <= not (temp) after 10ns;
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral; | gpl-2.0 | 04b89f05912589931ba6527e2905eaa3 | 0.561848 | 3.371859 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/bram_DDRs_Control.vhd | 1 | 46,970 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity bram_DDRs_Control is
Generic (
C_ASYNFIFO_WIDTH : integer := 72 ;
P_SIMULATION : boolean := TRUE
);
Port (
-- -- Pins
-- DDR_CLKn : OUT std_logic;
-- DDR_CLK : OUT std_logic;
-- DDR_CKE : OUT std_logic;
-- DDR_CSn : OUT std_logic;
-- DDR_RASn : OUT std_logic;
-- DDR_CASn : OUT std_logic;
-- DDR_WEn : OUT std_logic;
-- DDR_BankAddr : OUT std_logic_vector(C_DDR_BANK_AWIDTH-1 downto 0);
-- DDR_Addr : OUT std_logic_vector(C_DDR_AWIDTH-1 downto 0);
-- DDR_DM : OUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
-- DDR_DQ : INOUT std_logic_vector(C_DDR_DWIDTH-1 downto 0);
-- DDR_DQS : INOUT std_logic_vector(C_DDR_DWIDTH/8-1 downto 0);
--USER Logic Interface
user_wr_weA : IN std_logic_vector(7 downto 0);
user_wr_addrA : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
user_wr_dinA : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
user_rd_addrB : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
user_rd_doutB : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
user_rd_clk : IN std_logic;
user_wr_clk : IN std_logic;
-- DMA interface
DDR_wr_sof : IN std_logic;
DDR_wr_eof : IN std_logic;
DDR_wr_v : IN std_logic;
DDR_wr_FA : IN std_logic;
DDR_wr_Shift : IN std_logic;
DDR_wr_Mask : IN std_logic_vector(2-1 downto 0);
DDR_wr_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_wr_full : OUT std_logic;
DDR_rdc_sof : IN std_logic;
DDR_rdc_eof : IN std_logic;
DDR_rdc_v : IN std_logic;
DDR_rdc_FA : IN std_logic;
DDR_rdc_Shift : IN std_logic;
DDR_rdc_din : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DDR_rdc_full : OUT std_logic;
-- DDR_rdD_sof : OUT std_logic;
-- DDR_rdD_eof : OUT std_logic;
-- DDR_rdDout_V : OUT std_logic;
-- DDR_rdDout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- DDR payload FIFO Read Port
DDR_FIFO_RdEn : IN std_logic;
DDR_FIFO_Empty : OUT std_logic;
DDR_FIFO_RdQout : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Common interface
DDR_Ready : OUT std_logic;
DDR_blinker : OUT std_logic;
Sim_Zeichen : OUT std_logic;
mem_clk : IN std_logic;
trn_clk : IN std_logic;
trn_reset_n : IN std_logic
);
end entity bram_DDRs_Control;
architecture Behavioral of bram_DDRs_Control is
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
COMPONENT DDR_ClkGen
PORT(
ddr_Clock : OUT std_logic;
ddr_Clock_n : OUT std_logic;
ddr_Clock90 : OUT std_logic;
ddr_Clock90_n : OUT std_logic;
Clk_ddr_rddata : OUT std_logic;
Clk_ddr_rddata_n : OUT std_logic;
ddr_DCM_locked : OUT std_logic;
clk_in : IN std_logic;
trn_reset_n : IN std_logic
);
END COMPONENT;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
COMPONENT asyn_rw_FIFO72
-- GENERIC (
-- OUTPUT_REGISTERED : BOOLEAN
-- );
PORT(
wClk : IN std_logic;
wEn : IN std_logic;
Din : IN std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aFull : OUT std_logic;
Full : OUT std_logic;
rClk : IN std_logic;
rEn : IN std_logic;
Qout : OUT std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
aEmpty : OUT std_logic;
Empty : OUT std_logic;
Rst : IN std_logic
);
END COMPONENT;
component k7_prime_FIFO_plain
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
full : OUT std_logic;
prog_full: OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
empty : OUT std_logic;
rst : IN std_logic
);
end component;
-- component fifo_512x36_v4_2
-- port (
-- wr_clk : IN std_logic;
-- wr_en : IN std_logic;
-- din : IN std_logic_VECTOR(35 downto 0);
-- prog_full : OUT std_logic;
-- full : OUT std_logic;
--
-- rd_clk : IN std_logic;
-- rd_en : IN std_logic;
-- dout : OUT std_logic_VECTOR(35 downto 0);
-- prog_empty : OUT std_logic;
-- empty : OUT std_logic;
--
-- rst : IN std_logic
-- );
-- end component;
component fifo_512x72_v4_4
port (
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
prog_full : OUT std_logic;
full : OUT std_logic;
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_ASYNFIFO_WIDTH-1 downto 0);
-- prog_empty : OUT std_logic;
empty : OUT std_logic;
rst : IN std_logic
);
end component;
---- Dual-port block RAM for packets
--- Core output registered
--
-- component v5bram4096x32
-- port (
-- clka : IN std_logic;
-- addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- wea : IN std_logic_vector(0 downto 0);
-- dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
--
-- clkb : IN std_logic;
-- addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
-- web : IN std_logic_vector(0 downto 0);
-- dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
-- );
-- end component;
--SIMONE DEBUG
--component pcie_userlogic_02_cw
-- port (
-- addra: in std_logic_vector(11 downto 0);
-- addrb: in std_logic_vector(11 downto 0);
-- ce: in std_logic := '1';
-- clk: in std_logic; -- clock period = 5.0 ns (200.0 Mhz)
-- dina: in std_logic_vector(63 downto 0);
-- dinb: in std_logic_vector(63 downto 0);
-- douta: in std_logic_vector(63 downto 0);
-- doutb: in std_logic_vector(63 downto 0);
-- rst_i: in std_logic;
-- wea: in std_logic_vector(7 downto 0);
-- web: in std_logic_vector(7 downto 0);
-- rst_o: out std_logic
-- );
--end component;
component k7_bram4096x64
port (
clka : IN std_logic;
addra : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
wea : IN std_logic_vector(7 downto 0);
dina : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
douta : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0);
clkb : IN std_logic;
addrb : IN std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
web : IN std_logic_vector(7 downto 0);
dinb : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
doutb : OUT std_logic_vector(C_DBUS_WIDTH-1 downto 0)
);
end component;
-- Blinking -_-_-_-_-_-_-_-_-_-_-_-_-_-_-
COMPONENT DDR_Blink
PORT(
DDR_Blinker : OUT std_logic;
DDR_Write : IN std_logic;
DDR_Read : IN std_logic;
DDR_Both : IN std_logic;
ddr_Clock : IN std_logic;
DDr_Rst_n : IN std_logic
);
END COMPONENT;
-- ---------------------------------------------------------------------
signal ddr_DCM_locked : std_logic;
-- -- ---------------------------------------------------------------------
signal Rst_i : std_logic;
-- -- ---------------------------------------------------------------------
signal DDR_Ready_i : std_logic;
-- -- ---------------------------------------------------------------------
signal ddr_Clock : std_logic;
signal ddr_Clock_n : std_logic;
signal ddr_Clock90 : std_logic;
signal ddr_Clock90_n : std_logic;
signal Clk_ddr_rddata : std_logic;
signal Clk_ddr_rddata_n : std_logic;
-- -- -- Write Pipe Channel
signal wpipe_wEn : std_logic;
signal wpipe_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal wpipe_aFull : std_logic;
signal wpipe_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_wr_Cross_Row : std_logic;
signal DDR_wr_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_write_ALC : std_logic_vector(11-1 downto 0);
signal wpipe_rEn : std_logic;
signal wpipe_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal wpipe_aEmpty : std_logic;
signal wpipe_Empty : std_logic;
signal wpipe_Qout_latch : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- -- -- Read Pipe Command Channel
signal rpipec_wEn : std_logic;
signal rpipec_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpipec_aFull : std_logic;
signal rpipec_Full : std_logic;
-- Earlier calculate for better timing
signal DDR_rd_Cross_Row : std_logic;
signal DDR_rdc_din_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DDR_read_ALC : std_logic_vector(11-1 downto 0);
signal rpipec_rEn : std_logic;
signal rpipec_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpipec_aEmpty : std_logic;
signal rpipec_Empty : std_logic;
-- -- -- Read Pipe Data Channel
signal rpiped_wEn : std_logic;
signal rpiped_Din : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
signal rpiped_aFull : std_logic;
signal rpiped_Full : std_logic;
-- signal rpiped_rEn : std_logic;
signal rpiped_Qout : std_logic_vector(C_ASYNFIFO_WIDTH-1 downto 0);
-- signal rpiped_aEmpty : std_logic;
-- signal rpiped_Empty : std_logic;
-- write State machine
type bram_wrStates is ( wrST_bram_RESET
, wrST_bram_IDLE
-- , wrST_bram_Address
, wrST_bram_1st_Data
, wrST_bram_1st_Data_b2b
, wrST_bram_more_Data
, wrST_bram_last_DW
);
-- State variables
signal pseudo_DDR_wr_State : bram_wrStates;
-- Block RAM
signal pRAM_weA : std_logic_vector(7 downto 0);
signal pRAM_addrA : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_dinA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal user_wr_doutA : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal user_rd_weB : std_logic_vector(7 downto 0);
signal user_rd_dinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_weB : std_logic_vector(7 downto 0);
signal pRAM_dinB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_addrB : std_logic_vector(C_PRAM_AWIDTH-1 downto 0);
signal pRAM_doutB : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal pRAM_doutB_shifted : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal wpipe_qout_lo32b : std_logic_vector(33-1 downto 0);
signal wpipe_QW_Aligned : std_logic;
signal pRAM_AddrA_Inc : std_logic;
signal wpipe_read_valid : std_logic;
-- read State machine
type bram_rdStates is ( rdST_bram_RESET
, rdST_bram_IDLE
, rdST_bram_b4_LA
, rdST_bram_LA
-- , rdST_bram_b4_Length
-- , rdST_bram_Length
-- , rdST_bram_b4_Address
-- , rdST_bram_Address
, rdST_bram_Data
-- , rdST_bram_Data_shift
);
-- State variables
signal pseudo_DDR_rd_State : bram_rdStates;
signal rpiped_rd_counter : std_logic_vector(10-1 downto 0);
signal rpiped_wEn_b3 : std_logic;
signal rpiped_wEn_b2 : std_logic;
signal rpiped_wEn_b1 : std_logic;
signal rpiped_wr_EOF : std_logic;
signal rpipec_read_valid : std_logic;
signal rpiped_wr_skew : std_logic;
signal rpiped_wr_postpone : std_logic;
signal simone_debug : std_logic;
begin
Rst_i <= not trn_reset_n;
DDR_Ready <= DDR_Ready_i;
pRAM_doutB_shifted <= pRAM_doutB_r1(32-1 downto 0) & pRAM_doutB(64-1 downto 32);
-- Delay
Syn_Shifting_pRAM_doutB:
process ( trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
pRAM_doutB_r1 <= pRAM_doutB;
end if;
end process;
-- -----------------------------------------------
--
Syn_DDR_CKE:
process (trn_clk, Rst_i)
begin
if Rst_i = '1' then
DDR_Ready_i <= '0';
elsif trn_clk'event and trn_clk = '1' then
DDR_Ready_i <= '1'; -- ddr_DCM_locked;
end if;
end process;
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_Clock_Generator:
-- DDR_ClkGen
-- PORT MAP(
-- ddr_Clock => ddr_Clock , -- OUT std_logic;
-- ddr_Clock_n => ddr_Clock_n , -- OUT std_logic;
-- ddr_Clock90 => ddr_Clock90 , -- OUT std_logic;
-- ddr_Clock90_n => ddr_Clock90_n , -- OUT std_logic;
-- Clk_ddr_rddata => Clk_ddr_rddata , -- OUT std_logic;
-- Clk_ddr_rddata_n => Clk_ddr_rddata_n , -- OUT std_logic;
-- ddr_DCM_locked => ddr_DCM_locked , -- OUT std_logic;
--
-- clk_in => mem_clk , -- IN std_logic;
-- trn_reset_n => trn_reset_n -- IN std_logic
-- );
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => wpipe_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => wpipe_aEmpty ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_write_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => wpipe_wEn ,
-- Din => wpipe_Din ,
-- aFull => wpipe_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => wpipe_rEn ,
-- Qout => wpipe_Qout ,
-- aEmpty => open ,
-- Empty => wpipe_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_write_fifo:
k7_prime_FIFO_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => wpipe_wEn , -- IN std_logic;
din => wpipe_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => wpipe_aFull , -- OUT std_logic;
full => wpipe_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => wpipe_rEn , -- IN std_logic;
dout => wpipe_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => wpipe_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
wpipe_wEn <= DDR_wr_v;
wpipe_Din <= DDR_wr_Mask & DDR_wr_Shift & '0' & DDR_wr_sof & DDR_wr_eof & DDR_wr_Cross_Row & DDR_wr_FA & DDR_wr_din;
DDR_wr_full <= wpipe_aFull;
Sim_Zeichen <= simone_debug; --S wpipe_Empty;
Syn_DDR_wrD_Cross_Row:
process (trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
DDR_wr_din_r1(64-1 downto 10) <= (OTHERS=>'0');
DDR_wr_din_r1( 9 downto 0) <= DDR_wr_din(9 downto 0) - "100";
end if;
end process;
DDR_write_ALC <= (DDR_wr_din_r1(10 downto 2) &"00") + ('0' & DDR_wr_din(9 downto 2) &"00");
DDR_wr_Cross_Row <= '0'; -- DDR_write_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => rpipec_Full ,
--
-- rClk => ddr_Clock , -- ddr_Clock_n ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => rpipec_aEmpty ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
--
-- DDR_pipe_read_C_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => trn_clk ,
-- wEn => rpipec_wEn ,
-- Din => rpipec_Din ,
-- aFull => rpipec_aFull ,
-- Full => open ,
--
-- rClk => ddr_Clock ,
-- rEn => rpipec_rEn ,
-- Qout => rpipec_Qout ,
-- aEmpty => open ,
-- Empty => rpipec_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_C_fifo:
k7_prime_FIFO_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => rpipec_wEn , -- IN std_logic;
din => rpipec_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpipec_aFull , -- OUT std_logic;
full => open, --rpipec_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => rpipec_rEn , -- IN std_logic;
dout => rpipec_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => rpipec_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
rpipec_wEn <= DDR_rdc_v;
rpipec_Din <= "00" & DDR_rdc_Shift & '0' & DDR_rdc_sof & DDR_rdc_eof & DDR_rd_Cross_Row & DDR_rdc_FA & DDR_rdc_din;
DDR_rdc_full <= rpipec_aFull;
Syn_DDR_rdC_Cross_Row:
process (trn_clk)
begin
if trn_clk'event and trn_clk = '1' then
DDR_rdc_din_r1(64-1 downto 10) <= (OTHERS=>'0');
DDR_rdc_din_r1( 9 downto 0) <= DDR_rdc_din(9 downto 0) - "100";
end if;
end process;
DDR_read_ALC <= (DDR_rdc_din_r1(10 downto 2) &"00") + ('0' & DDR_rdc_din(9 downto 2) &"00");
DDR_rd_Cross_Row <= '0'; -- DDR_read_ALC(10);
-- ----------------------------------------------------------------------------
--
-- ----------------------------------------------------------------------------
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO
-- GENERIC MAP (
-- OUTPUT_REGISTERED => TRUE
-- )
-- PORT MAP(
-- wClk => ddr_Clock, -- Clk_ddr_rddata , -- ddr_Clock , -- ddr_Clock_n ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => rpiped_Full ,
--
-- rClk => trn_clk ,
-- rEn => DDR_FIFO_RdEn , -- rpiped_rEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open , -- rpiped_aEmpty ,
-- Empty => DDR_FIFO_Empty , -- rpiped_Empty ,
--
-- Rst => Rst_i
-- );
-- DDR_pipe_read_D_fifo:
-- asyn_rw_FIFO72
-- PORT MAP(
-- wClk => ddr_Clock ,
-- wEn => rpiped_wEn ,
-- Din => rpiped_Din ,
-- aFull => rpiped_aFull ,
-- Full => open ,
--
-- rClk => trn_clk ,
-- rEn => DDR_FIFO_RdEn ,
-- Qout => rpiped_Qout ,
-- aEmpty => open ,
-- Empty => DDR_FIFO_Empty ,
--
-- Rst => Rst_i
-- );
DDR_pipe_read_D_fifo:
k7_prime_FIFO_plain
PORT MAP(
wr_clk => trn_clk , -- IN std_logic;
wr_en => rpiped_wEn , -- IN std_logic;
din => rpiped_Din , -- IN std_logic_VECTOR(35 downto 0);
prog_full => rpiped_aFull , -- OUT std_logic;
full => open, -- rpiped_Full , -- OUT std_logic;
rd_clk => trn_clk , -- IN std_logic;
rd_en => DDR_FIFO_RdEn , -- IN std_logic;
dout => rpiped_Qout , -- OUT std_logic_VECTOR(35 downto 0);
empty => DDR_FIFO_Empty , -- OUT std_logic;
rst => Rst_i -- IN std_logic
);
DDR_FIFO_RdQout <= rpiped_Qout(C_DBUS_WIDTH-1 downto 0);
-- -------------------------------------------------
-- pkt_RAM instantiate
--
pkt_RAM_IN:
k7_bram4096x64
port map (
clka => trn_clk ,
addra => pRAM_addrA ,
wea => pRAM_weA ,
dina => pRAM_dinA ,
douta => pRAM_doutA ,
clkb => user_rd_clk ,
addrb => user_rd_addrB ,
web => user_rd_weB , --'0'
dinb => user_rd_dinB , --'0'
doutb => user_rd_doutB
);
user_rd_weB <= X"00";
user_rd_dinB <= (Others =>'0');
pkt_RAM_OUT:
k7_bram4096x64
port map (
clka => user_wr_clk ,
addra => user_wr_addrA ,
wea => user_wr_weA ,
dina => user_wr_dinA ,
douta => user_wr_doutA , --'open'
clkb => trn_clk ,
addrb => pRAM_addrB ,
web => pRAM_weB ,
dinb => pRAM_dinB ,
doutb => pRAM_doutB
);
pRAM_weB <= X"00";
pRAM_dinB <= (Others =>'0');
--my_pcie_userlogic_02_cw : pcie_userlogic_02_cw
-- port map (
--
-- addra => pRAM_addrA,
-- addrb => pRAM_addrB,
-- ce => '1',
-- clk => trn_clk,
-- dina => pRAM_dinA,
-- dinb => pRAM_dinB,
-- douta => pRAM_doutA,
-- doutb => pRAM_doutB,
-- rst_i => Rst_i,
-- wea => pRAM_weA,
-- web => pRAM_weB,
-- rst_o => simone_debug
-- );
simone_debug <= '0';
-- ------------------------------------------------
-- write States synchronous
--
Syn_Pseudo_DDR_wr_States:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (OTHERS=>'1');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
wpipe_qout_lo32b <= (OTHERS=>'0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
elsif trn_clk'event and trn_clk = '1' then
case pseudo_DDR_wr_State is
when wrST_bram_RESET =>
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_addrA <= (OTHERS=>'1');
wpipe_QW_Aligned <= '1';
wpipe_qout_lo32b <= (OTHERS=>'0');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
pRAM_AddrA_Inc <= '1';
when wrST_bram_IDLE =>
pRAM_addrA <= wpipe_Qout(14 downto 3);
pRAM_AddrA_Inc <= wpipe_Qout(2);
wpipe_QW_Aligned <= not wpipe_Qout(69);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= pRAM_dinA;
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data; -- wrST_bram_Address;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
end if;
when wrST_bram_1st_Data =>
pRAM_addrA <= pRAM_addrA;
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
elsif wpipe_Qout(71)='1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif pRAM_AddrA_Inc='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_more_Data =>
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_more_Data; -- wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_addrA <= pRAM_addrA;
pRAM_dinA <= pRAM_dinA;
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_QW_Aligned='1' then
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32) & wpipe_qout_lo32b(32)
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
end if;
when wrST_bram_last_DW =>
-- pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_addrA <= pRAM_addrA + '1';
pRAM_dinA <= wpipe_qout_lo32b(32-1 downto 0) & X"00000000";
if wpipe_read_valid = '1' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data_b2b; -- wrST_bram_Address;
wpipe_Qout_latch <= wpipe_Qout;
else
pseudo_DDR_wr_State <= wrST_bram_IDLE;
wpipe_Qout_latch <= wpipe_Qout;
end if;
when wrST_bram_1st_Data_b2b =>
pRAM_addrA <= wpipe_Qout_latch(14 downto 3);
wpipe_QW_Aligned <= not wpipe_Qout_latch(69);
if wpipe_read_valid = '0' then
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_weA <= (OTHERS=>'0'); --pRAM_weA;
pRAM_dinA <= pRAM_dinA;
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(66)='1' then -- eof
if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(70)='1' then -- mask(0)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout(71)='1' then -- mask(1)
pseudo_DDR_wr_State <= wrST_bram_IDLE;
pRAM_weA <= X"F0";
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1-32 downto 0) & X"00000000";
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
else
pseudo_DDR_wr_State <= wrST_bram_last_DW;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
end if;
else
if wpipe_Qout_latch(69)='0' then -- wpipe_QW_Aligned
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
& wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70) & wpipe_Qout(70)
);
pRAM_dinA <= wpipe_Qout(C_DBUS_WIDTH-1 downto 0);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= (32=>'1', OTHERS=>'0');
elsif wpipe_Qout_latch(2)='1' then -- pRAM_AddrA_Inc
pseudo_DDR_wr_State <= wrST_bram_more_Data;
pRAM_weA <= not ( X"f"
& wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71) & wpipe_Qout(71)
);
pRAM_dinA <= X"00000000" & wpipe_Qout(C_DBUS_WIDTH-1 downto 32);
pRAM_AddrA_Inc <= wpipe_Qout_latch(2);
wpipe_qout_lo32b <= '0' & wpipe_Qout(32-1 downto 0);
else
pseudo_DDR_wr_State <= wrST_bram_1st_Data;
pRAM_AddrA_Inc <= '1';
pRAM_weA <= X"00";
pRAM_dinA <= pRAM_dinA;
wpipe_qout_lo32b <= wpipe_Qout(70) & wpipe_Qout(32-1 downto 0);
end if;
end if;
when OTHERS =>
pseudo_DDR_wr_State <= wrST_bram_RESET;
pRAM_addrA <= (OTHERS=>'1');
pRAM_weA <= (OTHERS=>'0');
pRAM_dinA <= (OTHERS=>'0');
wpipe_qout_lo32b <= (OTHERS=>'0');
wpipe_QW_Aligned <= '1';
pRAM_AddrA_Inc <= '1';
end case;
end if;
end process;
--
Syn_wPipe_read:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
wpipe_rEn <= '0';
wpipe_read_valid <= '0';
elsif trn_clk'event and trn_clk = '1' then
wpipe_rEn <= '1';
wpipe_read_valid <= wpipe_rEn and not wpipe_Empty;
end if;
end process;
--
Syn_rPipeC_read:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpipec_read_valid <= '0';
rpiped_wr_postpone <= '0';
rpiped_wr_skew <= '0';
elsif trn_clk'event and trn_clk = '1' then
rpipec_read_valid <= rpipec_rEn and not rpipec_Empty;
if rpipec_read_valid='1' then
rpiped_wr_postpone <= rpipec_Qout(2) and not rpipec_Qout(69);
rpiped_wr_skew <= rpipec_Qout(69) xor rpipec_Qout(2);
else
rpiped_wr_postpone <= rpiped_wr_postpone;
rpiped_wr_skew <= rpiped_wr_skew;
end if;
end if;
end process;
-- ------------------------------------------------
-- Read States synchronous
--
Syn_Pseudo_DDR_rd_States:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
pseudo_DDR_rd_State <= rdST_bram_RESET;
rpipec_rEn <= '0';
pRAM_addrB <= (OTHERS=>'1');
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
elsif trn_clk'event and trn_clk = '1' then
case pseudo_DDR_rd_State is
when rdST_bram_RESET =>
pseudo_DDR_rd_State <= rdST_bram_IDLE;
rpipec_rEn <= '0';
pRAM_addrB <= (OTHERS=>'1');
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
when rdST_bram_IDLE =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
if rpipec_Empty = '0' then
rpipec_rEn <= '1';
pseudo_DDR_rd_State <= rdST_bram_b4_LA; --rdST_bram_b4_Length;
else
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
end if;
when rdST_bram_b4_LA =>
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= (OTHERS=>'0');
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
rpipec_rEn <= '0';
pseudo_DDR_rd_State <= rdST_bram_LA;
when rdST_bram_LA =>
rpipec_rEn <= '0';
pRAM_addrB <= rpipec_Qout(14 downto 3);
rpiped_wr_EOF <= '0';
rpiped_wEn_b3 <= '0';
if rpipec_Qout(2+32)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + '1';
elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2)='0' and rpipec_Qout(69)='1' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
elsif rpipec_Qout(2)='1' and rpipec_Qout(69)='0' then
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
else
rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
end if;
-- elsif rpipec_Qout(2)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- elsif rpipec_Qout(69)='1' then
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32) + "10";
-- else
-- rpiped_rd_counter <= rpipec_Qout(11+32 downto 2+32);
-- end if;
pseudo_DDR_rd_State <= rdST_bram_Data;
when rdST_bram_Data =>
rpipec_rEn <= '0';
if rpiped_rd_counter = CONV_STD_LOGIC_VECTOR(2, 10) then
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '1';
pseudo_DDR_rd_State <= rdST_bram_IDLE;
elsif rpiped_aFull = '1' then
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
else
pRAM_addrB <= pRAM_addrB + '1';
rpiped_rd_counter <= rpiped_rd_counter - "10";
rpiped_wEn_b3 <= '1';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_Data;
end if;
when OTHERS =>
rpipec_rEn <= '0';
pRAM_addrB <= pRAM_addrB;
rpiped_rd_counter <= rpiped_rd_counter;
rpiped_wEn_b3 <= '0';
rpiped_wr_EOF <= '0';
pseudo_DDR_rd_State <= rdST_bram_RESET;
end case;
end if;
end process;
Syn_Pseudo_DDR_rdd_write:
process ( trn_clk, DDR_Ready_i)
begin
if DDR_Ready_i = '0' then
rpiped_wEn_b1 <= '0';
rpiped_wEn_b2 <= '0';
rpiped_wEn <= '0';
rpiped_Din <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
rpiped_wEn_b2 <= rpiped_wEn_b3;
rpiped_wEn_b1 <= rpiped_wEn_b2;
if rpiped_wr_skew='1' then
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB_shifted;
else
-- rpiped_wEn <= rpiped_wEn_b2;
rpiped_wEn <= (rpiped_wEn_b2 and not rpiped_wr_postpone)
or (rpiped_wEn_b1 and rpiped_wr_postpone);
rpiped_Din <= "0000" & '0' & rpiped_wr_EOF & "00" & pRAM_doutB;
end if;
end if;
end process;
--
DDR_Blinker_Module:
DDR_Blink
PORT MAP(
DDR_Blinker => DDR_Blinker ,
DDR_Write => wpipe_rEn ,
DDR_Read => rpiped_wEn ,
DDR_Both => '0' ,
ddr_Clock => trn_clk ,
DDr_Rst_n => DDR_Ready_i -- DDR_CKE_i
);
end architecture Behavioral;
| gpl-2.0 | 688247feb6212f4f8492b6bf59928d6c | 0.417905 | 3.6544 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/OpenSource/rx_MRd_Channel.vhd | 1 | 27,608 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rx_MRd_Transact is
port (
-- Transaction receive interface
trn_rsof_n : IN std_logic;
trn_reof_n : IN std_logic;
trn_rd : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
trn_rrem_n : IN std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
trn_rerrfwd_n : IN std_logic;
trn_rsrc_rdy_n : IN std_logic;
-- trn_rdst_rdy_n : OUT std_logic;
trn_rnp_ok_n : OUT std_logic;
trn_rsrc_dsc_n : IN std_logic;
trn_rbar_hit_n : IN std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- trn_rfc_ph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_pd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_nph_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_npd_av : IN std_logic_vector(11 downto 0);
-- trn_rfc_cplh_av : IN std_logic_vector(7 downto 0);
-- trn_rfc_cpld_av : IN std_logic_vector(11 downto 0);
IORd_Type : IN std_logic;
MRd_Type : IN std_logic_vector(3 downto 0);
Tlp_straddles_4KB : IN std_logic;
-- MRd Channel
pioCplD_Req : OUT std_logic;
pioCplD_RE : IN std_logic;
pioCplD_Qout : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FIFO_Data_Count : IN std_logic_vector(C_FIFO_DC_WIDTH-1 downto 0);
FIFO_Empty : IN std_logic;
FIFO_Reading : IN std_logic;
pio_FC_stop : IN std_logic;
pio_reading_status : OUT std_logic;
-- Channel reset (from MWr channel)
Channel_Rst : IN std_logic;
-- Common ports
trn_clk : IN std_logic;
trn_reset_n : IN std_logic;
trn_lnk_up_n : IN std_logic
);
end entity rx_MRd_Transact;
architecture Behavioral of rx_MRd_Transact is
type RxMRdTrnStates is ( ST_MRd_RESET
, ST_MRd_IDLE
, ST_MRd_HEAD2
, ST_MRd_Tail
);
-- State variables
signal RxMRdTrn_NextState : RxMRdTrnStates;
signal RxMRdTrn_State : RxMRdTrnStates;
-- trn_rx stubs
signal trn_rsof_n_i : std_logic;
signal trn_reof_n_i : std_logic;
signal trn_rd_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rrem_n_i : std_logic_vector(C_DBUS_WIDTH/8-1 downto 0);
signal trn_rbar_hit_n_i : std_logic_vector(C_BAR_NUMBER-1 downto 0);
signal trn_rerrfwd_n_i : std_logic;
-- delays
signal trn_rd_r1 : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal trn_rbar_hit_n_r1 : std_logic_vector(C_BAR_NUMBER-1 downto 0);
-- BAR encoded
signal Encoded_BAR_Index : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Reset
signal local_Reset : std_logic;
-- Output signals
-- signal trn_rdst_rdy_n_i : std_logic;
signal trn_rnp_ok_n_i : std_logic;
signal trn_rsrc_dsc_n_i : std_logic;
-- Throttle
signal trn_rx_throttle : std_logic;
signal pio_reading_status_i : std_logic;
signal pio_read_fading_cnt : std_logic_vector(8-1 downto 0);
signal MRd_Has_3DW_Header : std_logic;
signal MRd_Has_4DW_Header : std_logic;
signal Tlp_is_Zero_Length : std_logic;
signal Illegal_Leng_on_FIFO : std_logic;
-- Built-in single-port fifo as MRd channel buffer
component k7_sfifo_15x128
port (
clk : IN std_logic;
rst : IN std_logic;
prog_full : OUT std_logic;
-- wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
full : OUT std_logic;
-- rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(C_CHANNEL_BUF_WIDTH-1 downto 0);
prog_empty : OUT std_logic;
empty : OUT std_logic
);
end component;
-- Signal with MRd channel FIFO
signal pioCplD_din : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_wire : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_RE_i : std_logic;
signal pioCplD_we : std_logic;
signal pioCplD_empty_i : std_logic;
signal pioCplD_full : std_logic;
signal pioCplD_prog_Full : std_logic;
signal pioCplD_empty_r1 : std_logic;
signal pioCplD_prog_full_r1 : std_logic;
signal pioCplD_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal pioCplD_Qout_reg : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Request for output arbitration
signal pioCplD_Req_i : std_logic;
signal pioCplD_Leng : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG-1 downto 0);
-- Busy/Done state bits generation
type FSM_Request is (
REQST_Idle
, REQST_1Read
, REQST_Decision
, REQST_nFIFO_Req
-- , REQST_Quantity
-- , REQST_FIFO_Req
);
signal FSM_REQ_pio : FSM_Request;
begin
-- positive reset and local
local_Reset <= not trn_reset_n or Channel_Rst;
-- MRd channel buffer control
-- pioCplD_RE_i <= pioCplD_RE;
pioCplD_Qout <= pioCplD_Qout_i;
pioCplD_Req <= pioCplD_Req_i; -- and not FIFO_Reading;
pio_reading_status <= pio_reading_status_i;
-- Output to the core as handshaking
trn_rsof_n_i <= trn_rsof_n;
trn_reof_n_i <= trn_reof_n;
trn_rd_i <= trn_rd;
trn_rrem_n_i <= trn_rrem_n;
trn_rerrfwd_n_i <= trn_rerrfwd_n;
trn_rsrc_dsc_n_i <= trn_rsrc_dsc_n;
trn_rbar_hit_n_i <= trn_rbar_hit_n;
-- Output to the core as handshaking
trn_rnp_ok_n <= trn_rnp_ok_n_i;
trn_rnp_ok_n_i <= pioCplD_prog_full_r1;
-- ( trn_rsrc_rdy_n seems never deasserted during packet)
trn_rx_throttle <= trn_rsrc_rdy_n; -- or trn_rdst_rdy_n_i;
-- ------------------------------------------------
-- Synchronous Delay: trn_rd + trn_rbar_hit_n
--
Synch_Delay_trn_rd:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
trn_rd_r1 <= trn_rd_i;
trn_rbar_hit_n_r1 <= trn_rbar_hit_n_i;
end if;
end process;
-- ------------------------------------------------
-- States synchronous
--
Syn_RxTrn_States:
process ( trn_clk, local_Reset)
begin
if local_Reset = '1' then
RxMRdTrn_State <= ST_MRd_RESET;
elsif trn_clk'event and trn_clk = '1' then
RxMRdTrn_State <= RxMRdTrn_NextState;
end if;
end process;
-- Next States
Comb_RxTrn_NextStates:
process (
RxMRdTrn_State
, MRd_Type
-- , IORd_Type
, trn_rx_throttle
, trn_rnp_ok_n_i
, trn_rsrc_dsc_n_i
, trn_rerrfwd_n_i
)
begin
case RxMRdTrn_State is
when ST_MRd_RESET =>
RxMRdTrn_NextState <= ST_MRd_IDLE;
when ST_MRd_IDLE =>
if trn_rnp_ok_n_i='0' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when OTHERS =>
-- if IORd_Type='1' then -- Temp taking IORd as MRd3
-- RxMRdTrn_NextState <= ST_MRd3_HEAD1;
-- else
RxMRdTrn_NextState <= ST_MRd_IDLE;
-- end if;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when ST_MRd_HEAD2 =>
if trn_rx_throttle = '1' then
RxMRdTrn_NextState <= ST_MRd_HEAD2;
else
RxMRdTrn_NextState <= ST_MRd_Tail;
end if;
when ST_MRd_Tail => -- support back-to-back transactions
if trn_rnp_ok_n_i='0' then
case MRd_Type is
when C_TLP_TYPE_IS_MRD_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRD_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H3 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when C_TLP_TYPE_IS_MRDLK_H4 =>
RxMRdTrn_NextState <= ST_MRd_HEAD2;
when OTHERS =>
-- if IORd_Type='1' then -- Temp taking IORd as MRd3
-- RxMRdTrn_NextState <= ST_MRd3_HEAD1;
-- else
RxMRdTrn_NextState <= ST_MRd_IDLE;
-- end if;
end case; -- MRd_Type
else
RxMRdTrn_NextState <= ST_MRd_IDLE;
end if;
when OTHERS =>
RxMRdTrn_NextState <= ST_MRd_RESET;
end case;
end process;
-- ------------------------------------------------
-- Synchronous calculation: Encoded_BAR_Index
--
Syn_Calc_Encoded_BAR_Index:
process ( trn_clk, local_Reset)
begin
if local_Reset = '1' then
Encoded_BAR_Index <= (OTHERS=>'1');
elsif trn_clk'event and trn_clk = '1' then
if trn_rbar_hit_n(0)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(1)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(1, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(2)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(2, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(3)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(3, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(4)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(4, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(5)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(5, C_ENCODE_BAR_NUMBER);
elsif trn_rbar_hit_n(6)='0' then
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(6, C_ENCODE_BAR_NUMBER);
else
Encoded_BAR_Index <= CONV_STD_LOGIC_VECTOR(7, C_ENCODE_BAR_NUMBER);
end if;
end if;
end process;
-- ----------------------------------------------------------------------------------
--
-- Synchronous output: MRd FIFO write port
--
-- PIO Channel Buffer (128-bit) definition:
-- Note: Type not shows in this buffer
--
-- 127 ~ xxx : Peripheral address
-- xxy ~ 97 : reserved
-- 96 : Zero-length
-- 95 : reserved
-- 94 : Valid
-- 93 ~ 68 : reserved
-- 67 ~ 65 : BAR number
-- 64 ~ 49 : Requester ID
-- 48 ~ 41 : Tag
-- 40 ~ 34 : Lower Address
-- 33 ~ 31 : Completion Status
-- 30 ~ 19 : Byte count
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
RxFSM_Output_pioCplD_WR:
process ( trn_clk, local_Reset)
begin
if local_Reset = '1' then
pioCplD_we <= '0';
pioCplD_din <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
case RxMRdTrn_State is
when ST_MRd_HEAD2 =>
pioCplD_we <= '0';
if Illegal_Leng_on_FIFO='1' then -- Cpl : unsupported request
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT)
<= C_FMT3_NO_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT)
<= "001"; --------------- ############
else
pioCplD_din(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT)
<= C_FMT3_WITH_DATA;
pioCplD_din(C_CHBUF_CPLD_CS_BIT_TOP downto C_CHBUF_CPLD_CS_BIT_BOT)
<= "000"; --------------- ############
end if;
pioCplD_din(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT)
<= trn_rd_r1(C_TLP_TC_BIT_TOP downto C_TLP_TC_BIT_BOT);
pioCplD_din(C_CHBUF_TD_BIT) <= '0';
pioCplD_din(C_CHBUF_EP_BIT) <= '0';
pioCplD_din(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT)
-- <= trn_rd_r1(C_TLP_ATTR_BIT_TOP) & C_NO_SNOOP; -- downto C_TLP_ATTR_BIT_BOT);
<= trn_rd_r1(C_TLP_ATTR_BIT_TOP downto C_TLP_ATTR_BIT_BOT);
pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT)
<= trn_rd_r1(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT);
pioCplD_din(C_CHBUF_QVALID_BIT) <= '1';
pioCplD_din(C_CHBUF_CPLD_REQID_BIT_TOP downto C_CHBUF_CPLD_REQID_BIT_BOT)
<= trn_rd_r1(C_TLP_REQID_BIT_TOP downto C_TLP_REQID_BIT_BOT);
pioCplD_din(C_CHBUF_CPLD_TAG_BIT_TOP downto C_CHBUF_CPLD_TAG_BIT_BOT)
<= trn_rd_r1(C_TLP_TAG_BIT_TOP downto C_TLP_TAG_BIT_BOT);
pioCplD_din(C_CHBUF_0LENG_BIT) <= Tlp_is_Zero_Length;
if Tlp_is_Zero_Length='1' then
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
<= CONV_STD_LOGIC_VECTOR(0, C_ENCODE_BAR_NUMBER);
else
pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
<= Encoded_BAR_Index;
end if;
when ST_MRd_Tail =>
if MRd_Has_4DW_Header='1' then
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT downto 0);
if trn_rbar_hit_n_r1(CINT_REGS_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT downto 0);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "000";
elsif trn_rbar_hit_n_r1(CINT_BRAM_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_MA_BIT_TOP-C_CHBUF_MA_BIT_BOT downto 0);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
elsif trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT downto 0);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= C_ALL_ONES(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT); --- "111" !!!
end if;
else
pioCplD_din(C_CHBUF_CPLD_LA_BIT_TOP downto C_CHBUF_CPLD_LA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_CPLD_LA_BIT_TOP-C_CHBUF_CPLD_LA_BIT_BOT+32 downto 32);
if trn_rbar_hit_n_r1(CINT_REGS_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_PA_BIT_TOP-C_CHBUF_PA_BIT_BOT+32 downto 32);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_REGS_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "000";
elsif trn_rbar_hit_n_r1(CINT_BRAM_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_MA_BIT_TOP-C_CHBUF_MA_BIT_BOT+32 downto 32);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
elsif trn_rbar_hit_n_r1(CINT_DDR_SPACE_BAR)='0' then
pioCplD_din(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT)
<= trn_rd_r1(C_CHBUF_DDA_BIT_TOP-C_CHBUF_DDA_BIT_BOT+32 downto 32);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER); --- "001";
else
pioCplD_din(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT)
<= C_ALL_ZEROS(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT);
-- pioCplD_din(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- <= C_ALL_ONES(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT); --- "111" !!!
end if;
end if;
if pioCplD_din(C_CHBUF_0LENG_BIT) ='1' then -- Zero-length
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= CONV_STD_LOGIC_VECTOR(1, C_CHBUF_CPLD_BC_BIT_TOP-C_CHBUF_CPLD_BC_BIT_BOT+1);
else
pioCplD_din(C_CHBUF_CPLD_BC_BIT_TOP downto C_CHBUF_CPLD_BC_BIT_BOT)
<= pioCplD_din(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) &"00";
end if;
-- if trn_rbar_hit_n_r1(CINT_REGS_SPACE_BAR)='0'
-- or trn_rbar_hit_n_r1(CINT_BRAM_SPACE_BAR)='0'
-- then
if trn_rbar_hit_n_r1(CINT_BAR_SPACES-1 downto 0) /= C_ALL_ONES(CINT_BAR_SPACES-1 downto 0) then
pioCplD_we <= not Tlp_straddles_4KB; --'1';
else
pioCplD_we <= '0';
end if;
when OTHERS =>
pioCplD_we <= '0';
pioCplD_din <= pioCplD_din;
end case;
end if;
end process;
-- -----------------------------------------------------------------------
-- Capture: MRd_Has_4DW_Header
-- : Tlp_is_Zero_Length
--
Syn_Capture_MRd_Has_4DW_Header:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
MRd_Has_3DW_Header <= '0';
MRd_Has_4DW_Header <= '0';
Tlp_is_Zero_Length <= '0';
Illegal_Leng_on_FIFO <= '0';
elsif trn_clk'event and trn_clk = '1' then
if trn_rsof_n_i='0' then
MRd_Has_3DW_Header <= not trn_rd_i(C_TLP_FMT_BIT_BOT) and not trn_rd_i(C_TLP_FMT_BIT_BOT+1);
MRd_Has_4DW_Header <= trn_rd_i(C_TLP_FMT_BIT_BOT) and not trn_rd_i(C_TLP_FMT_BIT_BOT+1);
Tlp_is_Zero_Length <= not (trn_rd_i(3) or trn_rd_i(2) or trn_rd_i(1) or trn_rd_i(0));
if trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)/=CONV_STD_LOGIC_VECTOR(1, C_TLP_FLD_WIDTH_OF_LENG)
and trn_rd_i(C_TLP_LENG_BIT_TOP downto C_TLP_LENG_BIT_BOT)/=CONV_STD_LOGIC_VECTOR(2, C_TLP_FLD_WIDTH_OF_LENG)
and trn_rbar_hit_n(CINT_FIFO_SPACE_BAR)='0'
then
Illegal_Leng_on_FIFO <= '1';
else
Illegal_Leng_on_FIFO <= '0';
end if;
else
MRd_Has_3DW_Header <= MRd_Has_3DW_Header;
MRd_Has_4DW_Header <= MRd_Has_4DW_Header;
Tlp_is_Zero_Length <= Tlp_is_Zero_Length;
Illegal_Leng_on_FIFO <= Illegal_Leng_on_FIFO;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- syn
-- : pio_reading_status
--
Syn_PIO_Reading_EB_Status:
process ( trn_clk, trn_reset_n)
begin
if trn_reset_n = '0' then
pio_reading_status_i <= '0';
pio_read_fading_cnt <= (OTHERS=>'0');
elsif trn_clk'event and trn_clk = '1' then
if trn_reof_n_i='0' then
if MRd_Has_4DW_Header='1'
and trn_rbar_hit_n(CINT_REGS_SPACE_BAR)='0'
and trn_rd_i(8-1 downto 0)=X"90" then
pio_reading_status_i <= '1';
pio_read_fading_cnt <= X"E0";
elsif MRd_Has_3DW_Header='1'
and trn_rbar_hit_n(CINT_REGS_SPACE_BAR)='0'
and trn_rd_i(32+8-1 downto 32)=X"90" then
pio_reading_status_i <= '1';
pio_read_fading_cnt <= X"E0";
elsif pio_read_fading_cnt(7)='1' then
pio_reading_status_i <= '1';
pio_read_fading_cnt <= pio_read_fading_cnt + '1';
else
pio_reading_status_i <= '0';
pio_read_fading_cnt <= (OTHERS=>'0');
end if;
elsif pio_read_fading_cnt=X"00" then
pio_reading_status_i <= '0';
pio_read_fading_cnt <= (OTHERS=>'0');
else
pio_reading_status_i <= pio_reading_status_i;
pio_read_fading_cnt <= pio_read_fading_cnt + '1';
end if;
end if;
end process;
-- -------------------------------------------------
-- MRd TLP Buffer
-- -------------------------------------------------
pioCplD_Buffer:
k7_sfifo_15x128
port map (
clk => trn_clk,
rst => local_Reset,
prog_full => pioCplD_prog_Full,
-- wr_clk => trn_clk,
wr_en => pioCplD_we,
din => pioCplD_din,
full => pioCplD_full,
-- rd_clk => trn_clk,
rd_en => pioCplD_RE_i,
dout => pioCplD_Qout_wire,
prog_empty => open,
empty => pioCplD_empty_i
);
-- ---------------------------------------------
-- Request for arbitration
--
Synch_Req_Proc:
process (local_Reset, trn_clk )
begin
if local_Reset = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (OTHERS=>'0');
pioCplD_Qout_reg <= (OTHERS=>'0');
pioCplD_Leng <= (0=>'1', OTHERS=>'0');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
elsif trn_clk'event and trn_clk = '1' then
case FSM_REQ_pio is
when REQST_IDLE =>
if pioCplD_empty_i = '0' then
pioCplD_RE_i <= '1';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_1Read;
else
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_IDLE;
end if;
when REQST_1Read =>
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
FSM_REQ_pio <= REQST_Decision;
when REQST_Decision =>
pioCplD_Qout_reg <= pioCplD_Qout_wire;
pioCplD_Leng <= pioCplD_Qout_wire(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
pioCplD_Qout_i <= pioCplD_Qout_i;
-- if pioCplD_Qout_wire(C_CHBUF_FMT_BIT_TOP) = '1' -- Has Payload
-- and pioCplD_Qout_wire(C_CHBUF_CPLD_BAR_BIT_TOP downto C_CHBUF_CPLD_BAR_BIT_BOT)
-- =CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER)
-- then
-- pioCplD_RE_i <= '0';
-- pioCplD_Req_i <= '0';
-- FSM_REQ_pio <= REQST_Quantity;
-- else
pioCplD_RE_i <= '0';
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
-- end if;
when REQST_nFIFO_Req =>
if pioCplD_RE = '1' then
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_reg;
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
else
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= pioCplD_Qout_i;
pioCplD_Req_i <= '1';
FSM_REQ_pio <= REQST_nFIFO_Req;
end if;
-- when REQST_Quantity =>
-- if FIFO_Empty='1' then
-- pioCplD_RE_i <= '0';
-- pioCplD_Req_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- FSM_REQ_pio <= REQST_Quantity;
-- else
-- pioCplD_RE_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- pioCplD_Req_i <= '1';
-- FSM_REQ_pio <= REQST_FIFO_Req;
-- end if;
--
-- when REQST_FIFO_Req =>
-- if FIFO_Empty='1' then
-- pioCplD_RE_i <= '0';
-- pioCplD_Req_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- FSM_REQ_pio <= REQST_Quantity;
-- elsif pioCplD_RE = '1' then
-- pioCplD_RE_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_reg;
-- pioCplD_Req_i <= '0';
-- FSM_REQ_pio <= REQST_IDLE;
-- else
-- pioCplD_RE_i <= '0';
-- pioCplD_Qout_i <= pioCplD_Qout_i;
-- pioCplD_Req_i <= '1';
-- FSM_REQ_pio <= REQST_FIFO_Req;
-- end if;
when OTHERS =>
pioCplD_RE_i <= '0';
pioCplD_Qout_i <= (OTHERS=>'0');
pioCplD_Qout_reg <= (OTHERS=>'0');
pioCplD_Leng <= (OTHERS=>'1');
pioCplD_Req_i <= '0';
FSM_REQ_pio <= REQST_IDLE;
end case;
end if;
end process;
-- ---------------------------------------------
-- Delay of Empty and prog_Full
--
Synch_Delay_empty_and_full:
process ( trn_clk )
begin
if trn_clk'event and trn_clk = '1' then
pioCplD_empty_r1 <= pioCplD_empty_i;
pioCplD_prog_full_r1 <= pioCplD_prog_Full;
end if;
end process;
end architecture Behavioral;
| gpl-2.0 | 8d32b23a8c602f7e4f9fb4cb1af7192a | 0.486562 | 3.340755 | false | false | false | false |
dcsun88/ntpserver-fpga | vhd/hdl/disp.vhd | 1 | 6,519 | -------------------------------------------------------------------------------
-- Title : CLock
-- Project :
-------------------------------------------------------------------------------
-- File : disp.vhd
-- Author : Daniel Sun <[email protected]>
-- Company :
-- Created : 2016-05-14
-- Last update: 2018-04-21
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Display controller
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-05-14 1.0 dcsun88osh Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library work;
use work.types_pkg.all;
entity disp is
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
-- Display memory
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
-- Time of day
cur_time : in time_ty;
-- Output to tlc59282 LED driver
disp_sclk : OUT std_logic;
disp_blank : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic;
disp_status : OUT std_logic
);
end disp;
architecture rtl of disp is
component disp_sr
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1pps : in std_logic;
tsc_1ppms : in std_logic;
tsc_1ppus : in std_logic;
disp_data : in std_logic_vector(255 downto 0);
disp_sclk : OUT std_logic;
disp_lat : OUT std_logic;
disp_sin : OUT std_logic
);
end component;
component disp_lut
port (
rst_n : in std_logic;
clk : in std_logic;
sram_addr : in std_logic_vector(9 downto 0);
sram_we : in std_logic;
sram_datao : in std_logic_vector(31 downto 0);
sram_datai : out std_logic_vector(31 downto 0);
lut_addr : in std_logic_vector(11 downto 0);
lut_data : out std_logic_vector(7 downto 0)
);
end component;
component disp_dark
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppus : in std_logic;
stat_src : in std_logic_vector(3 downto 0);
stat : in std_logic_vector(15 downto 0);
disp_pdm : in std_logic_vector(7 downto 0);
disp_blank : OUT std_logic;
disp_status : OUT std_logic
);
end component;
component disp_ctl
port (
rst_n : in std_logic;
clk : in std_logic;
tsc_1ppms : in std_logic;
disp_ena : in std_logic;
disp_page : in std_logic_vector(7 downto 0);
-- Time of day
cur_time : in time_ty;
-- Block memory display buffer and lut
lut_addr : out std_logic_vector(11 downto 0);
lut_data : in std_logic_vector(7 downto 0);
-- Segment driver data
disp_data : out std_logic_vector(255 downto 0)
);
end component;
SIGNAL disp_data : std_logic_vector(255 downto 0);
SIGNAL lut_addr : std_logic_vector(11 downto 0);
SIGNAL lut_data : std_logic_vector(7 downto 0);
begin
disp_sr_i : disp_sr
port map (
rst_n => rst_n,
clk => clk,
tsc_1pps => tsc_1pps,
tsc_1ppms => tsc_1ppms,
tsc_1ppus => tsc_1ppus,
disp_data => disp_data,
disp_sclk => disp_sclk,
disp_lat => disp_lat,
disp_sin => disp_sin
);
disp_lut_i : disp_lut
port map (
rst_n => rst_n,
clk => clk,
sram_addr => sram_addr,
sram_we => sram_we,
sram_datao => sram_datao,
sram_datai => sram_datai,
lut_addr => lut_addr,
lut_data => lut_data
);
disp_dark_i : disp_dark
port map (
rst_n => rst_n,
clk => clk,
tsc_1ppus => tsc_1ppus,
stat_src => stat_src,
stat => stat,
disp_pdm => disp_pdm,
disp_blank => disp_blank,
disp_status => disp_status
);
disp_ctl_i : disp_ctl
port map (
rst_n => rst_n,
clk => clk,
tsc_1ppms => tsc_1ppms,
disp_page => disp_page,
disp_ena => disp_ena,
-- Time of day
cur_time => cur_time,
-- Block memory display buffer and lut
lut_addr => lut_addr,
lut_data => lut_data,
-- Segment driver data
disp_data => disp_data
);
end rtl;
| gpl-3.0 | 0daac055c574f71d1b58ec0cb64561d9 | 0.389477 | 4.157526 | false | false | false | false |
saidwivedi/Face-Recognition-Hardware | ANN_FPGA/activation_hid_count.vhd | 1 | 944 |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity activation_hid_count is
port ( clk : in std_logic;
count_en : in std_logic;
num_operations : in std_logic_vector(7 downto 0);
activation : out std_logic
);
end activation_hid_count;
architecture Behavioral of activation_hid_count is
signal count : std_logic_vector (7 downto 0) := (others => '0');
begin
process (clk,count,count_en,num_operations) begin
--if rising_edge(clk) then
if count_en = '1' then
if count = num_operations + 1 then ----- it takes one clock cycle to read data from BRAM so the weighted_sum_layer has to operate for 1 cycle more
activation <= '1';
else
activation <= '0';
if rising_edge(clk) then
count <= count + 1;
end if;
end if;
else
count <= "00000000";
activation <= '0';
end if;
--end if;
end process;
end Behavioral;
| bsd-2-clause | fcc85f5dc7599bfa87e2b09fbaa8e88d | 0.652542 | 3.167785 | false | false | false | false |
peteut/nvc | lib/std/textio.vhd | 1 | 19,049 | --
-- TEXTIO package as defined by IEEE 1076-1993
--
package textio is
type line is access string;
type text is file of string;
type side is (RIGHT, LEFT);
subtype width is natural;
file input : text open READ_MODE is "STD_INPUT";
file output : text open WRITE_MODE is "STD_OUTPUT";
procedure readline (file f: text; l: inout line);
procedure read (l : inout line;
value : out bit;
good : out boolean );
procedure read (l : inout line;
value : out bit );
procedure read (l : inout line;
value : out bit_vector;
good : out boolean );
procedure read (l : inout line;
value : out bit_vector );
procedure read (l : inout line;
value : out boolean;
good : out boolean );
procedure read (l : inout line;
value : out boolean );
procedure read (l : inout line;
value : out character;
good : out boolean );
procedure read (l : inout line;
value : out character );
procedure read (l : inout line;
value : out integer;
good : out boolean );
procedure read (l : inout line;
value : out integer );
procedure read (l : inout line;
value : out real;
good : out boolean );
procedure read (l : inout line;
value : out real );
procedure read (l : inout line;
value : out string;
good : out boolean );
procedure read (l : inout line;
value : out string );
procedure read (l : inout line;
value : out time;
good : out boolean );
procedure read (l : inout line;
value : out time );
procedure writeline (file f : text; l : inout line);
procedure tee (file f : text; l : inout line);
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 );
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 );
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns );
end package;
package body textio is
procedure grow (l : inout line;
extra : in natural;
old_size : out natural ) is
variable tmp : line;
begin
if l = null then
l := new string(1 to extra);
old_size := 0;
elsif extra > 0 then
old_size := l'length;
tmp := new string(1 to l'length + extra);
tmp(1 to l'length) := l.all;
deallocate(l);
l := tmp;
end if;
end procedure;
procedure shrink (l : inout line; size : in natural) is
variable tmp : line;
begin
assert l /= null;
assert size < l'length;
tmp := new string(1 to size);
tmp.all := l.all(1 to size);
deallocate(l);
l := tmp;
end procedure;
procedure consume (l : inout line; nchars : in natural) is
variable tmp : line;
begin
if nchars = 0 then
return;
end if;
assert l /= null;
if nchars = l'length then
tmp := new string'("");
else
assert nchars <= l'length;
tmp := new string(1 to l'length - nchars);
tmp.all := l.all(1 + nchars to l'length);
end if;
deallocate(l);
l := tmp;
end procedure;
function is_whitespace (x : character) return boolean is
begin
return x = ' ' or x = CR or x = LF or x = HT;
end function;
procedure skip_whitespace (l : inout line) is
variable skip : natural := 0;
begin
while skip < l'length and is_whitespace(l.all(1 + skip)) loop
skip := skip + 1;
end loop;
consume(l, skip);
end procedure;
function max (a, b : integer) return integer is
begin
if a > b then
return a;
else
return b;
end if;
end function;
procedure read (l : inout line;
value : out bit;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out bit )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit read failed";
end procedure;
procedure read (l : inout line;
value : out bit_vector;
good : out boolean ) is
variable consumed : natural := 0;
variable char : character;
begin
good := true;
skip_whitespace(l);
for i in value'range loop
if l.all'length < consumed then
good := false;
exit;
end if;
char := l.all(consumed + 1);
if char = '0' then
value(i) := '0';
elsif char = '1' then
value(i) := '1';
else
good := false;
exit;
end if;
consumed := consumed + 1;
end loop;
consume(l, consumed);
end procedure;
procedure read (l : inout line;
value : out bit_vector )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "bit_vector read failed";
end procedure;
procedure read (l : inout line;
value : out boolean;
good : out boolean ) is
begin
good := false;
skip_whitespace(l);
if l.all'length = 0 then
return;
end if;
if l(1) = 'T' or l(1) = 't' then
if l.all'length >= 4
and (l(2) = 'R' or l(2) = 'r')
and (l(3) = 'U' or l(3) = 'u')
and (l(4) = 'E' or l(4) = 'e')
then
consume(l, 4);
good := true;
value := true;
end if;
elsif l(1) = 'F' or l(1) = 'f' then
if l.all'length >= 5
and (l(2) = 'A' or l(2) = 'a')
and (l(3) = 'L' or l(3) = 'l')
and (l(4) = 'S' or l(4) = 's')
and (l(5) = 'E' or l(5) = 'e')
then
consume(l, 5);
good := true;
value := false;
end if;
end if;
end procedure;
procedure read (l : inout line;
value : out boolean )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "boolean read failed";
end procedure;
procedure read (l : inout line;
value : out character;
good : out boolean ) is
begin
if l'length > 0 then
value := l.all(1);
consume(l, 1);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out character )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "character read failed";
end procedure;
procedure read (l : inout line;
value : out integer;
good : out boolean ) is
variable pos : integer := 1;
variable digit : integer;
variable result : integer := 0;
variable is_negative : boolean := false;
begin
skip_whitespace(l);
if pos <= l.all'right and l.all(pos) = '-' then
pos := pos + 1;
is_negative := true;
end if;
while pos <= l.all'right loop
exit when l.all(pos) < '0' or l.all(pos) > '9';
digit := character'pos(l.all(pos)) - character'pos('0');
if is_negative then
digit := -digit;
end if;
result := (result * 10) + digit;
pos := pos + 1;
end loop;
if is_negative and pos = 2 then
-- Single dash without trailing digit is not good
pos := 1;
end if;
good := pos > 1;
value := result;
consume(l, pos - 1);
end procedure;
procedure read (l : inout line;
value : out integer )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "integer read failed";
end procedure;
procedure read (l : inout line;
value : out real;
good : out boolean ) is
variable prefix : integer;
variable result : real;
variable pgood : boolean;
variable digit : integer;
variable shift : real := 0.1;
variable pos : integer := 2;
begin
read(l, prefix, pgood);
if not pgood then
good := false;
return;
end if;
result := real(prefix);
good := true;
if l.all'length > 0 and l.all(1) = '.' then
while pos <= l.all'right loop
exit when l.all(pos) < '0' or l.all(pos) > '9';
digit := character'pos(l.all(pos)) - character'pos('0');
result := result + (real(digit) * shift);
shift := shift / 10.0;
pos := pos + 1;
end loop;
good := pos > 2;
consume(l, pos - 1);
end if;
value := result;
end procedure;
procedure read (l : inout line;
value : out real )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "real read failed";
end procedure;
procedure read (l : inout line;
value : out string;
good : out boolean ) is
begin
if value'length <= l'length then
value := l.all(1 to value'length);
consume(l, value'length);
good := true;
else
good := false;
end if;
end procedure;
procedure read (l : inout line;
value : out string )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "string read failed";
end procedure;
procedure read (l : inout line;
value : out time;
good : out boolean ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure read (l : inout line;
value : out time )
is
variable good : boolean;
begin
read(l, value, good);
assert good report "time read failed";
end procedure;
procedure readline (file f: text; l: inout line) is
variable tmp : line;
variable ch : string(1 to 1);
variable used : natural;
variable got : integer;
begin
if l /= null then
deallocate(l);
end if;
tmp := new string(1 to 128);
loop
exit when endfile(f);
read(f, ch, got);
exit when got /= 1;
next when ch(1) = CR;
if ch(1) = LF then
exit;
else
if used = tmp'length then
grow(tmp, 128, used);
end if;
used := used + 1;
tmp(used) := ch(1);
end if;
end loop;
if used = 0 then
l := new string'("");
else
shrink(tmp, used);
l := tmp;
end if;
end procedure;
procedure writeline (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
l := new string'("");
end procedure;
procedure tee (file f : text; l : inout line) is
begin
if l /= null then
write(f, l.all);
write(output, l.all);
deallocate(l);
end if;
write(f, (1 => LF)); -- Prepend CR on Windows?
write(output, (1 => LF));
l := new string'("");
end procedure;
procedure write (l : inout line;
value : in string;
justified : in side := right;
field : in width := 0 )
is
variable orig : natural;
variable width : natural;
begin
width := max(value'length, field);
grow(l, width, orig);
if justified = left then
l(orig + 1 to orig + value'length) := value;
for i in orig + value'length + 1 to orig + width loop
l(i) := ' ';
end loop;
else
for i in orig + 1 to orig + width - value'length loop
l(i) := ' ';
end loop;
l(orig + 1 + width - value'length to orig + width) := value;
end if;
end procedure;
procedure write (l : inout line;
value : in character;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, string'(1 => value), justified, field);
end procedure;
function bit_to_char (b : bit) return character is
type table_t is array (bit) of character;
constant table : table_t := ( '0' => '0',
'1' => '1' );
begin
return table(b);
end function;
procedure write (l : inout line;
value : in bit;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, bit_to_char(value), justified, field);
end procedure;
procedure write (l : inout line;
value : in bit_vector;
justified : in side := right;
field : in width := 0 )
is
variable s : string(1 to value'length);
alias v : bit_vector(1 to value'length) is value;
begin
for i in s'range loop
s(i) := bit_to_char(v(i));
end loop;
write(l, s, justified, field);
end procedure;
procedure write (l : inout line;
value : in boolean;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, boolean'image(value), justified, field);
end procedure;
function unit_string (unit : time) return string is
begin
-- Standard requires unit in lower case
if unit = fs then
return " fs";
elsif unit = ps then
return " ps";
elsif unit = ns then
return " ns";
elsif unit = us then
return " us";
elsif unit = ms then
return " ms";
elsif unit = sec then
return " sec";
elsif unit = min then
return " min";
elsif unit = hr then
return " hr";
else
report "invalid unit " & time'image(unit);
end if;
end function;
procedure write (l : inout line;
value : in time;
justified : in side := right;
field : in width := 0;
unit : in time := ns )
is
variable value_time: time := abs(value);
variable digit_time: time := unit;
variable str : string (1 to 22);
variable pos : natural := str'left;
variable digit : integer;
begin
if value < 0 ns then
str(pos) := '-';
pos := pos + 1;
end if;
while value_time / 10 >= digit_time loop
digit_time := digit_time * 10;
end loop;
while (pos <= str'right) loop
digit := value_time / digit_time;
value_time := value_time - digit * digit_time;
str(pos) := character'val(digit + character'pos ('0'));
pos := pos + 1;
exit when value_time = 0 fs and digit_time <= unit;
if digit_time = unit and pos <= str'right then
str(pos) := '.';
pos := pos + 1;
end if;
exit when (digit_time / 10) * 10 /= digit_time;
digit_time := digit_time / 10;
end loop;
write(l, str(1 to pos-1) & unit_string(unit), justified, field);
end procedure;
procedure write (l : inout line;
value : in real;
justified : in side:= right;
field : in width := 0;
digits : in natural:= 0 ) is
begin
-- TODO
report "unimplemented" severity failure;
end procedure;
procedure write (l : inout line;
value : in integer;
justified : in side := right;
field : in width := 0 ) is
begin
write(l, integer'image(value), justified, field);
end procedure;
end package body;
| gpl-3.0 | b35491e58c92ed7a1f8a6a79888d3205 | 0.447688 | 4.496931 | false | false | false | false |
MyAUTComputerArchitectureCourse/SEMI-MIPS | src/mips/datapath/alu/components/not_component.vhd | 1 | 1,124 | --------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 06-04-2017
-- Package Name: alu_component
-- Module Name: NOT_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity NOT_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end entity;
architecture NOT_COMPONENT_ARCH of NOT_COMPONENT is
begin
OUTPUT(0) <= not INPUT(0);
OUTPUT(1) <= not INPUT(1);
OUTPUT(2) <= not INPUT(2);
OUTPUT(3) <= not INPUT(3);
OUTPUT(4) <= not INPUT(4);
OUTPUT(5) <= not INPUT(5);
OUTPUT(6) <= not INPUT(6);
OUTPUT(7) <= not INPUT(7);
OUTPUT(8) <= not INPUT(8);
OUTPUT(9) <= not INPUT(9);
OUTPUT(10) <= not INPUT(10);
OUTPUT(11) <= not INPUT(11);
OUTPUT(12) <= not INPUT(12);
OUTPUT(13) <= not INPUT(13);
OUTPUT(14) <= not INPUT(14);
OUTPUT(15) <= not INPUT(15);
end architecture;
| gpl-3.0 | 5b17e3178a53693e5418c88bf806f2b2 | 0.482206 | 3.426829 | false | false | false | false |
v3best/R7Lite | R7Lite_PCIE/fpga_code/r7lite_DMA/ipcore_dir/wr_fifo32to256/example_design/wr_fifo32to256_exdes.vhd | 1 | 5,522 | --------------------------------------------------------------------------------
--
-- FIFO Generator Core - core top file for implementation
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: wr_fifo32to256_exdes.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity wr_fifo32to256_exdes is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end wr_fifo32to256_exdes;
architecture xilinx of wr_fifo32to256_exdes is
signal wr_clk_i : std_logic;
signal rd_clk_i : std_logic;
component wr_fifo32to256 is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
WR_DATA_COUNT : OUT std_logic_vector(13-1 DOWNTO 0);
RD_DATA_COUNT : OUT std_logic_vector(10-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(256-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
exdes_inst : wr_fifo32to256
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
WR_DATA_COUNT => wr_data_count,
RD_DATA_COUNT => rd_data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
| gpl-2.0 | f1bf87f0bede4123a24d88047a863f83 | 0.519196 | 4.663851 | false | false | false | false |
SoCdesign/inputboard | ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_spdif_tx_v1_00_a/hdl/vhdl/tx_bitbuf.vhd | 3 | 5,012 | ----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Bit buffer holding 2x192 bits of either channel status or ----
---- user data for the transmitter. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2004/07/17 17:21:11 gedra
-- Fixed bug.
--
-- Revision 1.1 2004/07/14 17:58:19 gedra
-- Transmitter channel status buffer.
--
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_bitbuf is
generic (ENABLE_BUFFER: integer range 0 to 1 := 0);
port (
up_clk: in std_logic; -- clock
up_rstn: in std_logic; -- reset
buf_wr: in std_logic; -- buffer write strobe
up_addr: in std_logic_vector(4 downto 0); -- address
up_wdata: in std_logic_vector(15 downto 0); -- data
buf_data_a: out std_logic_vector(191 downto 0);
buf_data_b: out std_logic_vector(191 downto 0));
end tx_bitbuf;
architecture rtl of tx_bitbuf is
type buf_type is array (0 to 23) of std_logic_vector(7 downto 0);
signal buffer_a, buffer_b: buf_type;
begin
-- the byte buffer is 192 bits (24 bytes) for each channel
EB: if ENABLE_BUFFER = 1 generate
WBUF: process (up_clk, up_rstn)
begin
if up_rstn = '0' then
for i in 0 to 23 loop
buffer_a(i) <= (others => '0');
buffer_b(i) <= (others => '0');
end loop;
elsif rising_edge(up_clk) then
if buf_wr = '1' and to_integer(unsigned(up_addr)) < 24 then
buffer_a(to_integer(unsigned(up_addr))) <= up_wdata(7 downto 0);
buffer_b(to_integer(unsigned(up_addr))) <= up_wdata(15 downto 8);
end if;
end if;
end process WBUF;
VGEN: for k in 0 to 23 generate
buf_data_a(8 * k + 7 downto 8 * k) <= buffer_a(k);
buf_data_b(8 * k + 7 downto 8 * k) <= buffer_b(k);
end generate VGEN;
end generate EB;
-- if the byte buffer is not enabled, set all bits to zero
NEB: if ENABLE_BUFFER = 0 generate
buf_data_a(191 downto 0) <= (others => '0');
buf_data_b(191 downto 0) <= (others => '0');
end generate NEB;
end rtl;
| mit | e8cc82a22abf8bdf4f59144a61ad960d | 0.424781 | 4.791587 | false | false | false | false |
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